1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988-2012 Free Software Foundation, Inc.
5 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
6 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 #include "gdb_string.h"
25 #include "gdb_assert.h"
37 #include "arch-utils.h"
40 #include "mips-tdep.h"
42 #include "reggroups.h"
43 #include "opcode/mips.h"
47 #include "sim-regno.h"
49 #include "frame-unwind.h"
50 #include "frame-base.h"
51 #include "trad-frame.h"
53 #include "floatformat.h"
55 #include "target-descriptions.h"
56 #include "dwarf2-frame.h"
57 #include "user-regs.h"
61 static const struct objfile_data
*mips_pdr_data
;
63 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
65 static int mips32_instruction_has_delay_slot (struct gdbarch
*, CORE_ADDR
);
66 static int micromips_instruction_has_delay_slot (struct gdbarch
*, CORE_ADDR
,
68 static int mips16_instruction_has_delay_slot (struct gdbarch
*, CORE_ADDR
,
71 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
72 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
73 #define ST0_FR (1 << 26)
75 /* The sizes of floating point registers. */
79 MIPS_FPU_SINGLE_REGSIZE
= 4,
80 MIPS_FPU_DOUBLE_REGSIZE
= 8
89 static const char *mips_abi_string
;
91 static const char *const mips_abi_strings
[] = {
102 /* For backwards compatibility we default to MIPS16. This flag is
103 overridden as soon as unambiguous ELF file flags tell us the
104 compressed ISA encoding used. */
105 static const char mips_compression_mips16
[] = "mips16";
106 static const char mips_compression_micromips
[] = "micromips";
107 static const char *const mips_compression_strings
[] =
109 mips_compression_mips16
,
110 mips_compression_micromips
,
114 static const char *mips_compression_string
= mips_compression_mips16
;
116 /* The standard register names, and all the valid aliases for them. */
117 struct register_alias
123 /* Aliases for o32 and most other ABIs. */
124 const struct register_alias mips_o32_aliases
[] = {
131 /* Aliases for n32 and n64. */
132 const struct register_alias mips_n32_n64_aliases
[] = {
139 /* Aliases for ABI-independent registers. */
140 const struct register_alias mips_register_aliases
[] = {
141 /* The architecture manuals specify these ABI-independent names for
143 #define R(n) { "r" #n, n }
144 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
145 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
146 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
147 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
150 /* k0 and k1 are sometimes called these instead (for "kernel
155 /* This is the traditional GDB name for the CP0 status register. */
156 { "sr", MIPS_PS_REGNUM
},
158 /* This is the traditional GDB name for the CP0 BadVAddr register. */
159 { "bad", MIPS_EMBED_BADVADDR_REGNUM
},
161 /* This is the traditional GDB name for the FCSR. */
162 { "fsr", MIPS_EMBED_FP0_REGNUM
+ 32 }
165 const struct register_alias mips_numeric_register_aliases
[] = {
166 #define R(n) { #n, n }
167 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
168 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
169 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
170 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
174 #ifndef MIPS_DEFAULT_FPU_TYPE
175 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
177 static int mips_fpu_type_auto
= 1;
178 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
180 static unsigned int mips_debug
= 0;
182 /* Properties (for struct target_desc) describing the g/G packet
184 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
185 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
187 struct target_desc
*mips_tdesc_gp32
;
188 struct target_desc
*mips_tdesc_gp64
;
190 const struct mips_regnum
*
191 mips_regnum (struct gdbarch
*gdbarch
)
193 return gdbarch_tdep (gdbarch
)->regnum
;
197 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
199 return mips_regnum (gdbarch
)->fp0
+ 12;
202 /* Return 1 if REGNUM refers to a floating-point general register, raw
203 or cooked. Otherwise return 0. */
206 mips_float_register_p (struct gdbarch
*gdbarch
, int regnum
)
208 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
210 return (rawnum
>= mips_regnum (gdbarch
)->fp0
211 && rawnum
< mips_regnum (gdbarch
)->fp0
+ 32);
214 #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \
216 || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64)
218 #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \
219 (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum)
221 #define MIPS_LAST_ARG_REGNUM(gdbarch) \
222 (gdbarch_tdep (gdbarch)->mips_last_arg_regnum)
224 #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type)
226 /* Return the MIPS ABI associated with GDBARCH. */
228 mips_abi (struct gdbarch
*gdbarch
)
230 return gdbarch_tdep (gdbarch
)->mips_abi
;
234 mips_isa_regsize (struct gdbarch
*gdbarch
)
236 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
238 /* If we know how big the registers are, use that size. */
239 if (tdep
->register_size_valid_p
)
240 return tdep
->register_size
;
242 /* Fall back to the previous behavior. */
243 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
244 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
247 /* Return the currently configured (or set) saved register size. */
250 mips_abi_regsize (struct gdbarch
*gdbarch
)
252 switch (mips_abi (gdbarch
))
254 case MIPS_ABI_EABI32
:
260 case MIPS_ABI_EABI64
:
262 case MIPS_ABI_UNKNOWN
:
265 internal_error (__FILE__
, __LINE__
, _("bad switch"));
269 /* MIPS16/microMIPS function addresses are odd (bit 0 is set). Here
270 are some functions to handle addresses associated with compressed
271 code including but not limited to testing, setting, or clearing
272 bit 0 of such addresses. */
274 /* Return one iff compressed code is the MIPS16 instruction set. */
277 is_mips16_isa (struct gdbarch
*gdbarch
)
279 return gdbarch_tdep (gdbarch
)->mips_isa
== ISA_MIPS16
;
282 /* Return one iff compressed code is the microMIPS instruction set. */
285 is_micromips_isa (struct gdbarch
*gdbarch
)
287 return gdbarch_tdep (gdbarch
)->mips_isa
== ISA_MICROMIPS
;
290 /* Return one iff ADDR denotes compressed code. */
293 is_compact_addr (CORE_ADDR addr
)
298 /* Return one iff ADDR denotes standard ISA code. */
301 is_mips_addr (CORE_ADDR addr
)
303 return !is_compact_addr (addr
);
306 /* Return one iff ADDR denotes MIPS16 code. */
309 is_mips16_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
311 return is_compact_addr (addr
) && is_mips16_isa (gdbarch
);
314 /* Return one iff ADDR denotes microMIPS code. */
317 is_micromips_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
319 return is_compact_addr (addr
) && is_micromips_isa (gdbarch
);
322 /* Strip the ISA (compression) bit off from ADDR. */
325 unmake_compact_addr (CORE_ADDR addr
)
327 return ((addr
) & ~(CORE_ADDR
) 1);
330 /* Add the ISA (compression) bit to ADDR. */
333 make_compact_addr (CORE_ADDR addr
)
335 return ((addr
) | (CORE_ADDR
) 1);
338 /* Functions for setting and testing a bit in a minimal symbol that
339 marks it as MIPS16 or microMIPS function. The MSB of the minimal
340 symbol's "info" field is used for this purpose.
342 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is
343 "special", i.e. refers to a MIPS16 or microMIPS function, and sets
344 one of the "special" bits in a minimal symbol to mark it accordingly.
345 The test checks an ELF-private flag that is valid for true function
346 symbols only; in particular synthetic symbols such as for PLT stubs
347 have no ELF-private part at all.
349 msymbol_is_mips16 and msymbol_is_micromips test the "special" bit
350 in a minimal symbol. */
353 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
355 elf_symbol_type
*elfsym
= (elf_symbol_type
*) sym
;
357 if ((sym
->flags
& BSF_SYNTHETIC
) != 0)
360 if (ELF_ST_IS_MICROMIPS (elfsym
->internal_elf_sym
.st_other
))
361 MSYMBOL_TARGET_FLAG_2 (msym
) = 1;
362 else if (ELF_ST_IS_MIPS16 (elfsym
->internal_elf_sym
.st_other
))
363 MSYMBOL_TARGET_FLAG_1 (msym
) = 1;
366 /* Return one iff MSYM refers to standard ISA code. */
369 msymbol_is_mips (struct minimal_symbol
*msym
)
371 return !(MSYMBOL_TARGET_FLAG_1 (msym
) | MSYMBOL_TARGET_FLAG_2 (msym
));
374 /* Return one iff MSYM refers to MIPS16 code. */
377 msymbol_is_mips16 (struct minimal_symbol
*msym
)
379 return MSYMBOL_TARGET_FLAG_1 (msym
);
382 /* Return one iff MSYM refers to microMIPS code. */
385 msymbol_is_micromips (struct minimal_symbol
*msym
)
387 return MSYMBOL_TARGET_FLAG_2 (msym
);
390 /* XFER a value from the big/little/left end of the register.
391 Depending on the size of the value it might occupy the entire
392 register or just part of it. Make an allowance for this, aligning
393 things accordingly. */
396 mips_xfer_register (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
397 int reg_num
, int length
,
398 enum bfd_endian endian
, gdb_byte
*in
,
399 const gdb_byte
*out
, int buf_offset
)
403 gdb_assert (reg_num
>= gdbarch_num_regs (gdbarch
));
404 /* Need to transfer the left or right part of the register, based on
405 the targets byte order. */
409 reg_offset
= register_size (gdbarch
, reg_num
) - length
;
411 case BFD_ENDIAN_LITTLE
:
414 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
418 internal_error (__FILE__
, __LINE__
, _("bad switch"));
421 fprintf_unfiltered (gdb_stderr
,
422 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
423 reg_num
, reg_offset
, buf_offset
, length
);
424 if (mips_debug
&& out
!= NULL
)
427 fprintf_unfiltered (gdb_stdlog
, "out ");
428 for (i
= 0; i
< length
; i
++)
429 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
432 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
435 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
437 if (mips_debug
&& in
!= NULL
)
440 fprintf_unfiltered (gdb_stdlog
, "in ");
441 for (i
= 0; i
< length
; i
++)
442 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
445 fprintf_unfiltered (gdb_stdlog
, "\n");
448 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
449 compatiblity mode. A return value of 1 means that we have
450 physical 64-bit registers, but should treat them as 32-bit registers. */
453 mips2_fp_compat (struct frame_info
*frame
)
455 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
456 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
458 if (register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) == 4)
462 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
463 in all the places we deal with FP registers. PR gdb/413. */
464 /* Otherwise check the FR bit in the status register - it controls
465 the FP compatiblity mode. If it is clear we are in compatibility
467 if ((get_frame_register_unsigned (frame
, MIPS_PS_REGNUM
) & ST0_FR
) == 0)
474 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
476 static CORE_ADDR
heuristic_proc_start (struct gdbarch
*, CORE_ADDR
);
478 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
480 /* The list of available "set mips " and "show mips " commands. */
482 static struct cmd_list_element
*setmipscmdlist
= NULL
;
483 static struct cmd_list_element
*showmipscmdlist
= NULL
;
485 /* Integer registers 0 thru 31 are handled explicitly by
486 mips_register_name(). Processor specific registers 32 and above
487 are listed in the following tables. */
490 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
494 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
495 "sr", "lo", "hi", "bad", "cause", "pc",
496 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
497 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
498 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
499 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
503 /* Names of IDT R3041 registers. */
505 static const char *mips_r3041_reg_names
[] = {
506 "sr", "lo", "hi", "bad", "cause", "pc",
507 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
508 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
509 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
510 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
511 "fsr", "fir", "", /*"fp" */ "",
512 "", "", "bus", "ccfg", "", "", "", "",
513 "", "", "port", "cmp", "", "", "epc", "prid",
516 /* Names of tx39 registers. */
518 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
519 "sr", "lo", "hi", "bad", "cause", "pc",
520 "", "", "", "", "", "", "", "",
521 "", "", "", "", "", "", "", "",
522 "", "", "", "", "", "", "", "",
523 "", "", "", "", "", "", "", "",
525 "", "", "", "", "", "", "", "",
526 "", "", "config", "cache", "debug", "depc", "epc",
529 /* Names of IRIX registers. */
530 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
531 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
532 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
533 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
534 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
535 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
538 /* Names of registers with Linux kernels. */
539 static const char *mips_linux_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
540 "sr", "lo", "hi", "bad", "cause", "pc",
541 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
542 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
543 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
544 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
549 /* Return the name of the register corresponding to REGNO. */
551 mips_register_name (struct gdbarch
*gdbarch
, int regno
)
553 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
554 /* GPR names for all ABIs other than n32/n64. */
555 static char *mips_gpr_names
[] = {
556 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
557 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
558 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
559 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
562 /* GPR names for n32 and n64 ABIs. */
563 static char *mips_n32_n64_gpr_names
[] = {
564 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
565 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
566 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
567 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
570 enum mips_abi abi
= mips_abi (gdbarch
);
572 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
573 but then don't make the raw register names visible. This (upper)
574 range of user visible register numbers are the pseudo-registers.
576 This approach was adopted accommodate the following scenario:
577 It is possible to debug a 64-bit device using a 32-bit
578 programming model. In such instances, the raw registers are
579 configured to be 64-bits wide, while the pseudo registers are
580 configured to be 32-bits wide. The registers that the user
581 sees - the pseudo registers - match the users expectations
582 given the programming model being used. */
583 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
584 if (regno
< gdbarch_num_regs (gdbarch
))
587 /* The MIPS integer registers are always mapped from 0 to 31. The
588 names of the registers (which reflects the conventions regarding
589 register use) vary depending on the ABI. */
590 if (0 <= rawnum
&& rawnum
< 32)
592 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
593 return mips_n32_n64_gpr_names
[rawnum
];
595 return mips_gpr_names
[rawnum
];
597 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
598 return tdesc_register_name (gdbarch
, rawnum
);
599 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (gdbarch
))
601 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
602 if (tdep
->mips_processor_reg_names
[rawnum
- 32])
603 return tdep
->mips_processor_reg_names
[rawnum
- 32];
607 internal_error (__FILE__
, __LINE__
,
608 _("mips_register_name: bad register number %d"), rawnum
);
611 /* Return the groups that a MIPS register can be categorised into. */
614 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
615 struct reggroup
*reggroup
)
620 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
621 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
622 if (reggroup
== all_reggroup
)
624 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
625 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
626 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
627 (gdbarch), as not all architectures are multi-arch. */
628 raw_p
= rawnum
< gdbarch_num_regs (gdbarch
);
629 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
630 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
632 if (reggroup
== float_reggroup
)
633 return float_p
&& pseudo
;
634 if (reggroup
== vector_reggroup
)
635 return vector_p
&& pseudo
;
636 if (reggroup
== general_reggroup
)
637 return (!vector_p
&& !float_p
) && pseudo
;
638 /* Save the pseudo registers. Need to make certain that any code
639 extracting register values from a saved register cache also uses
641 if (reggroup
== save_reggroup
)
642 return raw_p
&& pseudo
;
643 /* Restore the same pseudo register. */
644 if (reggroup
== restore_reggroup
)
645 return raw_p
&& pseudo
;
649 /* Return the groups that a MIPS register can be categorised into.
650 This version is only used if we have a target description which
651 describes real registers (and their groups). */
654 mips_tdesc_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
655 struct reggroup
*reggroup
)
657 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
658 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
661 /* Only save, restore, and display the pseudo registers. Need to
662 make certain that any code extracting register values from a
663 saved register cache also uses pseudo registers.
665 Note: saving and restoring the pseudo registers is slightly
666 strange; if we have 64 bits, we should save and restore all
667 64 bits. But this is hard and has little benefit. */
671 ret
= tdesc_register_in_reggroup_p (gdbarch
, rawnum
, reggroup
);
675 return mips_register_reggroup_p (gdbarch
, regnum
, reggroup
);
678 /* Map the symbol table registers which live in the range [1 *
679 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
680 registers. Take care of alignment and size problems. */
682 static enum register_status
683 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
684 int cookednum
, gdb_byte
*buf
)
686 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
687 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
688 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
689 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
690 return regcache_raw_read (regcache
, rawnum
, buf
);
691 else if (register_size (gdbarch
, rawnum
) >
692 register_size (gdbarch
, cookednum
))
694 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
695 return regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
698 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
700 enum register_status status
;
702 status
= regcache_raw_read_signed (regcache
, rawnum
, ®val
);
703 if (status
== REG_VALID
)
704 store_signed_integer (buf
, 4, byte_order
, regval
);
709 internal_error (__FILE__
, __LINE__
, _("bad register size"));
713 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
714 struct regcache
*regcache
, int cookednum
,
717 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
718 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
719 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
720 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
721 regcache_raw_write (regcache
, rawnum
, buf
);
722 else if (register_size (gdbarch
, rawnum
) >
723 register_size (gdbarch
, cookednum
))
725 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
726 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
729 /* Sign extend the shortened version of the register prior
730 to placing it in the raw register. This is required for
731 some mips64 parts in order to avoid unpredictable behavior. */
732 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
733 LONGEST regval
= extract_signed_integer (buf
, 4, byte_order
);
734 regcache_raw_write_signed (regcache
, rawnum
, regval
);
738 internal_error (__FILE__
, __LINE__
, _("bad register size"));
742 mips_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
743 struct agent_expr
*ax
, int reg
)
745 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
746 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
747 && reg
< 2 * gdbarch_num_regs (gdbarch
));
749 ax_reg_mask (ax
, rawnum
);
755 mips_ax_pseudo_register_push_stack (struct gdbarch
*gdbarch
,
756 struct agent_expr
*ax
, int reg
)
758 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
759 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
760 && reg
< 2 * gdbarch_num_regs (gdbarch
));
761 if (register_size (gdbarch
, rawnum
) >= register_size (gdbarch
, reg
))
765 if (register_size (gdbarch
, rawnum
) > register_size (gdbarch
, reg
))
767 if (!gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
768 || gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_BIG
)
771 ax_simple (ax
, aop_lsh
);
774 ax_simple (ax
, aop_rsh_signed
);
778 internal_error (__FILE__
, __LINE__
, _("bad register size"));
783 /* Table to translate 3-bit register field to actual register number. */
784 static const signed char mips_reg3_to_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
786 /* Heuristic_proc_start may hunt through the text section for a long
787 time across a 2400 baud serial line. Allows the user to limit this
790 static unsigned int heuristic_fence_post
= 0;
792 /* Number of bytes of storage in the actual machine representation for
793 register N. NOTE: This defines the pseudo register type so need to
794 rebuild the architecture vector. */
796 static int mips64_transfers_32bit_regs_p
= 0;
799 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
800 struct cmd_list_element
*c
)
802 struct gdbarch_info info
;
803 gdbarch_info_init (&info
);
804 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
805 instead of relying on globals. Doing that would let generic code
806 handle the search for this specific architecture. */
807 if (!gdbarch_update_p (info
))
809 mips64_transfers_32bit_regs_p
= 0;
810 error (_("32-bit compatibility mode not supported"));
814 /* Convert to/from a register and the corresponding memory value. */
816 /* This predicate tests for the case of an 8 byte floating point
817 value that is being transferred to or from a pair of floating point
818 registers each of which are (or are considered to be) only 4 bytes
821 mips_convert_register_float_case_p (struct gdbarch
*gdbarch
, int regnum
,
824 return (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
825 && register_size (gdbarch
, regnum
) == 4
826 && mips_float_register_p (gdbarch
, regnum
)
827 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
830 /* This predicate tests for the case of a value of less than 8
831 bytes in width that is being transfered to or from an 8 byte
832 general purpose register. */
834 mips_convert_register_gpreg_case_p (struct gdbarch
*gdbarch
, int regnum
,
837 int num_regs
= gdbarch_num_regs (gdbarch
);
839 return (register_size (gdbarch
, regnum
) == 8
840 && regnum
% num_regs
> 0 && regnum
% num_regs
< 32
841 && TYPE_LENGTH (type
) < 8);
845 mips_convert_register_p (struct gdbarch
*gdbarch
,
846 int regnum
, struct type
*type
)
848 return (mips_convert_register_float_case_p (gdbarch
, regnum
, type
)
849 || mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
));
853 mips_register_to_value (struct frame_info
*frame
, int regnum
,
854 struct type
*type
, gdb_byte
*to
,
855 int *optimizedp
, int *unavailablep
)
857 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
859 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
861 get_frame_register (frame
, regnum
+ 0, to
+ 4);
862 get_frame_register (frame
, regnum
+ 1, to
+ 0);
864 if (!get_frame_register_bytes (frame
, regnum
+ 0, 0, 4, to
+ 4,
865 optimizedp
, unavailablep
))
868 if (!get_frame_register_bytes (frame
, regnum
+ 1, 0, 4, to
+ 0,
869 optimizedp
, unavailablep
))
871 *optimizedp
= *unavailablep
= 0;
874 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
876 int len
= TYPE_LENGTH (type
);
879 offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 8 - len
: 0;
880 if (!get_frame_register_bytes (frame
, regnum
, offset
, len
, to
,
881 optimizedp
, unavailablep
))
884 *optimizedp
= *unavailablep
= 0;
889 internal_error (__FILE__
, __LINE__
,
890 _("mips_register_to_value: unrecognized case"));
895 mips_value_to_register (struct frame_info
*frame
, int regnum
,
896 struct type
*type
, const gdb_byte
*from
)
898 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
900 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
902 put_frame_register (frame
, regnum
+ 0, from
+ 4);
903 put_frame_register (frame
, regnum
+ 1, from
+ 0);
905 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
908 int len
= TYPE_LENGTH (type
);
910 /* Sign extend values, irrespective of type, that are stored to
911 a 64-bit general purpose register. (32-bit unsigned values
912 are stored as signed quantities within a 64-bit register.
913 When performing an operation, in compiled code, that combines
914 a 32-bit unsigned value with a signed 64-bit value, a type
915 conversion is first performed that zeroes out the high 32 bits.) */
916 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
919 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, -1);
921 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, 0);
922 put_frame_register_bytes (frame
, regnum
, 0, 8 - len
, fill
);
923 put_frame_register_bytes (frame
, regnum
, 8 - len
, len
, from
);
927 if (from
[len
-1] & 0x80)
928 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, -1);
930 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, 0);
931 put_frame_register_bytes (frame
, regnum
, 0, len
, from
);
932 put_frame_register_bytes (frame
, regnum
, len
, 8 - len
, fill
);
937 internal_error (__FILE__
, __LINE__
,
938 _("mips_value_to_register: unrecognized case"));
942 /* Return the GDB type object for the "standard" data type of data in
946 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
948 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (gdbarch
));
949 if (mips_float_register_p (gdbarch
, regnum
))
951 /* The floating-point registers raw, or cooked, always match
952 mips_isa_regsize(), and also map 1:1, byte for byte. */
953 if (mips_isa_regsize (gdbarch
) == 4)
954 return builtin_type (gdbarch
)->builtin_float
;
956 return builtin_type (gdbarch
)->builtin_double
;
958 else if (regnum
< gdbarch_num_regs (gdbarch
))
960 /* The raw or ISA registers. These are all sized according to
962 if (mips_isa_regsize (gdbarch
) == 4)
963 return builtin_type (gdbarch
)->builtin_int32
;
965 return builtin_type (gdbarch
)->builtin_int64
;
969 int rawnum
= regnum
- gdbarch_num_regs (gdbarch
);
971 /* The cooked or ABI registers. These are sized according to
972 the ABI (with a few complications). */
973 if (rawnum
== mips_regnum (gdbarch
)->fp_control_status
974 || rawnum
== mips_regnum (gdbarch
)->fp_implementation_revision
)
975 return builtin_type (gdbarch
)->builtin_int32
;
976 else if (gdbarch_osabi (gdbarch
) != GDB_OSABI_IRIX
977 && gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
978 && rawnum
>= MIPS_FIRST_EMBED_REGNUM
979 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
980 /* The pseudo/cooked view of the embedded registers is always
981 32-bit. The raw view is handled below. */
982 return builtin_type (gdbarch
)->builtin_int32
;
983 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
984 /* The target, while possibly using a 64-bit register buffer,
985 is only transfering 32-bits of each integer register.
986 Reflect this in the cooked/pseudo (ABI) register value. */
987 return builtin_type (gdbarch
)->builtin_int32
;
988 else if (mips_abi_regsize (gdbarch
) == 4)
989 /* The ABI is restricted to 32-bit registers (the ISA could be
991 return builtin_type (gdbarch
)->builtin_int32
;
994 return builtin_type (gdbarch
)->builtin_int64
;
998 /* Return the GDB type for the pseudo register REGNUM, which is the
999 ABI-level view. This function is only called if there is a target
1000 description which includes registers, so we know precisely the
1001 types of hardware registers. */
1003 static struct type
*
1004 mips_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
1006 const int num_regs
= gdbarch_num_regs (gdbarch
);
1007 int rawnum
= regnum
% num_regs
;
1008 struct type
*rawtype
;
1010 gdb_assert (regnum
>= num_regs
&& regnum
< 2 * num_regs
);
1012 /* Absent registers are still absent. */
1013 rawtype
= gdbarch_register_type (gdbarch
, rawnum
);
1014 if (TYPE_LENGTH (rawtype
) == 0)
1017 if (mips_float_register_p (gdbarch
, rawnum
))
1018 /* Present the floating point registers however the hardware did;
1019 do not try to convert between FPU layouts. */
1022 /* Use pointer types for registers if we can. For n32 we can not,
1023 since we do not have a 64-bit pointer type. */
1024 if (mips_abi_regsize (gdbarch
)
1025 == TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
))
1027 if (rawnum
== MIPS_SP_REGNUM
1028 || rawnum
== mips_regnum (gdbarch
)->badvaddr
)
1029 return builtin_type (gdbarch
)->builtin_data_ptr
;
1030 else if (rawnum
== mips_regnum (gdbarch
)->pc
)
1031 return builtin_type (gdbarch
)->builtin_func_ptr
;
1034 if (mips_abi_regsize (gdbarch
) == 4 && TYPE_LENGTH (rawtype
) == 8
1035 && ((rawnum
>= MIPS_ZERO_REGNUM
&& rawnum
<= MIPS_PS_REGNUM
)
1036 || rawnum
== mips_regnum (gdbarch
)->lo
1037 || rawnum
== mips_regnum (gdbarch
)->hi
1038 || rawnum
== mips_regnum (gdbarch
)->badvaddr
1039 || rawnum
== mips_regnum (gdbarch
)->cause
1040 || rawnum
== mips_regnum (gdbarch
)->pc
1041 || (mips_regnum (gdbarch
)->dspacc
!= -1
1042 && rawnum
>= mips_regnum (gdbarch
)->dspacc
1043 && rawnum
< mips_regnum (gdbarch
)->dspacc
+ 6)))
1044 return builtin_type (gdbarch
)->builtin_int32
;
1046 if (gdbarch_osabi (gdbarch
) != GDB_OSABI_IRIX
1047 && gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
1048 && rawnum
>= MIPS_EMBED_FP0_REGNUM
+ 32
1049 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
1051 /* The pseudo/cooked view of embedded registers is always
1052 32-bit, even if the target transfers 64-bit values for them.
1053 New targets relying on XML descriptions should only transfer
1054 the necessary 32 bits, but older versions of GDB expected 64,
1055 so allow the target to provide 64 bits without interfering
1056 with the displayed type. */
1057 return builtin_type (gdbarch
)->builtin_int32
;
1060 /* For all other registers, pass through the hardware type. */
1064 /* Should the upper word of 64-bit addresses be zeroed? */
1065 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
1068 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
1070 switch (mask_address_var
)
1072 case AUTO_BOOLEAN_TRUE
:
1074 case AUTO_BOOLEAN_FALSE
:
1077 case AUTO_BOOLEAN_AUTO
:
1078 return tdep
->default_mask_address_p
;
1080 internal_error (__FILE__
, __LINE__
,
1081 _("mips_mask_address_p: bad switch"));
1087 show_mask_address (struct ui_file
*file
, int from_tty
,
1088 struct cmd_list_element
*c
, const char *value
)
1090 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
1092 deprecated_show_value_hack (file
, from_tty
, c
, value
);
1093 switch (mask_address_var
)
1095 case AUTO_BOOLEAN_TRUE
:
1096 printf_filtered ("The 32 bit mips address mask is enabled\n");
1098 case AUTO_BOOLEAN_FALSE
:
1099 printf_filtered ("The 32 bit mips address mask is disabled\n");
1101 case AUTO_BOOLEAN_AUTO
:
1103 ("The 32 bit address mask is set automatically. Currently %s\n",
1104 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
1107 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
1112 /* Tell if the program counter value in MEMADDR is in a standard ISA
1116 mips_pc_is_mips (CORE_ADDR memaddr
)
1118 struct minimal_symbol
*sym
;
1120 /* Flags indicating that this is a MIPS16 or microMIPS function is
1121 stored by elfread.c in the high bit of the info field. Use this
1122 to decide if the function is standard MIPS. Otherwise if bit 0
1123 of the address is clear, then this is a standard MIPS function. */
1124 sym
= lookup_minimal_symbol_by_pc (memaddr
);
1126 return msymbol_is_mips (sym
);
1128 return is_mips_addr (memaddr
);
1131 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
1134 mips_pc_is_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1136 struct minimal_symbol
*sym
;
1138 /* A flag indicating that this is a MIPS16 function is stored by
1139 elfread.c in the high bit of the info field. Use this to decide
1140 if the function is MIPS16. Otherwise if bit 0 of the address is
1141 set, then ELF file flags will tell if this is a MIPS16 function. */
1142 sym
= lookup_minimal_symbol_by_pc (memaddr
);
1144 return msymbol_is_mips16 (sym
);
1146 return is_mips16_addr (gdbarch
, memaddr
);
1149 /* Tell if the program counter value in MEMADDR is in a microMIPS function. */
1152 mips_pc_is_micromips (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1154 struct minimal_symbol
*sym
;
1156 /* A flag indicating that this is a microMIPS function is stored by
1157 elfread.c in the high bit of the info field. Use this to decide
1158 if the function is microMIPS. Otherwise if bit 0 of the address
1159 is set, then ELF file flags will tell if this is a microMIPS
1161 sym
= lookup_minimal_symbol_by_pc (memaddr
);
1163 return msymbol_is_micromips (sym
);
1165 return is_micromips_addr (gdbarch
, memaddr
);
1168 /* Tell the ISA type of the function the program counter value in MEMADDR
1171 static enum mips_isa
1172 mips_pc_isa (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1174 struct minimal_symbol
*sym
;
1176 /* A flag indicating that this is a MIPS16 or a microMIPS function
1177 is stored by elfread.c in the high bit of the info field. Use
1178 this to decide if the function is MIPS16 or microMIPS or normal
1179 MIPS. Otherwise if bit 0 of the address is set, then ELF file
1180 flags will tell if this is a MIPS16 or a microMIPS function. */
1181 sym
= lookup_minimal_symbol_by_pc (memaddr
);
1184 if (msymbol_is_micromips (sym
))
1185 return ISA_MICROMIPS
;
1186 else if (msymbol_is_mips16 (sym
))
1193 if (is_mips_addr (memaddr
))
1195 else if (is_micromips_addr (gdbarch
, memaddr
))
1196 return ISA_MICROMIPS
;
1202 /* Various MIPS16 thunk (aka stub or trampoline) names. */
1204 static const char mips_str_mips16_call_stub
[] = "__mips16_call_stub_";
1205 static const char mips_str_mips16_ret_stub
[] = "__mips16_ret_";
1206 static const char mips_str_call_fp_stub
[] = "__call_stub_fp_";
1207 static const char mips_str_call_stub
[] = "__call_stub_";
1208 static const char mips_str_fn_stub
[] = "__fn_stub_";
1210 /* This is used as a PIC thunk prefix. */
1212 static const char mips_str_pic
[] = ".pic.";
1214 /* Return non-zero if the PC is inside a call thunk (aka stub or
1215 trampoline) that should be treated as a temporary frame. */
1218 mips_in_frame_stub (CORE_ADDR pc
)
1220 CORE_ADDR start_addr
;
1223 /* Find the starting address of the function containing the PC. */
1224 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
1227 /* If the PC is in __mips16_call_stub_*, this is a call/return stub. */
1228 if (strncmp (name
, mips_str_mips16_call_stub
,
1229 strlen (mips_str_mips16_call_stub
)) == 0)
1231 /* If the PC is in __call_stub_*, this is a call/return or a call stub. */
1232 if (strncmp (name
, mips_str_call_stub
, strlen (mips_str_call_stub
)) == 0)
1234 /* If the PC is in __fn_stub_*, this is a call stub. */
1235 if (strncmp (name
, mips_str_fn_stub
, strlen (mips_str_fn_stub
)) == 0)
1238 return 0; /* Not a stub. */
1241 /* MIPS believes that the PC has a sign extended value. Perhaps the
1242 all registers should be sign extended for simplicity? */
1245 mips_read_pc (struct regcache
*regcache
)
1247 int regnum
= gdbarch_pc_regnum (get_regcache_arch (regcache
));
1250 regcache_cooked_read_signed (regcache
, regnum
, &pc
);
1251 if (is_compact_addr (pc
))
1252 pc
= unmake_compact_addr (pc
);
1257 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1261 pc
= frame_unwind_register_signed (next_frame
, gdbarch_pc_regnum (gdbarch
));
1262 if (is_compact_addr (pc
))
1263 pc
= unmake_compact_addr (pc
);
1264 /* macro/2012-04-20: This hack skips over MIPS16 call thunks as
1265 intermediate frames. In this case we can get the caller's address
1266 from $ra, or if $ra contains an address within a thunk as well, then
1267 it must be in the return path of __mips16_call_stub_{s,d}{f,c}_{0..10}
1268 and thus the caller's address is in $s2. */
1269 if (frame_relative_level (next_frame
) >= 0 && mips_in_frame_stub (pc
))
1271 pc
= frame_unwind_register_signed
1272 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
1273 if (is_compact_addr (pc
))
1274 pc
= unmake_compact_addr (pc
);
1275 if (mips_in_frame_stub (pc
))
1277 pc
= frame_unwind_register_signed
1278 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
1279 if (is_compact_addr (pc
))
1280 pc
= unmake_compact_addr (pc
);
1287 mips_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1289 return frame_unwind_register_signed
1290 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
);
1293 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1294 dummy frame. The frame ID's base needs to match the TOS value
1295 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1298 static struct frame_id
1299 mips_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1301 return frame_id_build
1302 (get_frame_register_signed (this_frame
,
1303 gdbarch_num_regs (gdbarch
)
1305 get_frame_pc (this_frame
));
1308 /* Implement the "write_pc" gdbarch method. */
1311 mips_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1313 int regnum
= gdbarch_pc_regnum (get_regcache_arch (regcache
));
1315 if (mips_pc_is_mips (pc
))
1316 regcache_cooked_write_unsigned (regcache
, regnum
, pc
);
1318 regcache_cooked_write_unsigned (regcache
, regnum
, make_compact_addr (pc
));
1321 /* Fetch and return instruction from the specified location. Handle
1322 MIPS16/microMIPS as appropriate. */
1325 mips_fetch_instruction (struct gdbarch
*gdbarch
,
1326 enum mips_isa isa
, CORE_ADDR addr
, int *statusp
)
1328 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1329 gdb_byte buf
[MIPS_INSN32_SIZE
];
1337 instlen
= MIPS_INSN16_SIZE
;
1338 addr
= unmake_compact_addr (addr
);
1341 instlen
= MIPS_INSN32_SIZE
;
1344 internal_error (__FILE__
, __LINE__
, _("invalid ISA"));
1347 status
= target_read_memory (addr
, buf
, instlen
);
1348 if (statusp
!= NULL
)
1352 if (statusp
== NULL
)
1353 memory_error (status
, addr
);
1356 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1359 /* These are the fields of 32 bit mips instructions. */
1360 #define mips32_op(x) (x >> 26)
1361 #define itype_op(x) (x >> 26)
1362 #define itype_rs(x) ((x >> 21) & 0x1f)
1363 #define itype_rt(x) ((x >> 16) & 0x1f)
1364 #define itype_immediate(x) (x & 0xffff)
1366 #define jtype_op(x) (x >> 26)
1367 #define jtype_target(x) (x & 0x03ffffff)
1369 #define rtype_op(x) (x >> 26)
1370 #define rtype_rs(x) ((x >> 21) & 0x1f)
1371 #define rtype_rt(x) ((x >> 16) & 0x1f)
1372 #define rtype_rd(x) ((x >> 11) & 0x1f)
1373 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1374 #define rtype_funct(x) (x & 0x3f)
1376 /* MicroMIPS instruction fields. */
1377 #define micromips_op(x) ((x) >> 10)
1379 /* 16-bit/32-bit-high-part instruction formats, B and S refer to the lowest
1380 bit and the size respectively of the field extracted. */
1381 #define b0s4_imm(x) ((x) & 0xf)
1382 #define b0s5_imm(x) ((x) & 0x1f)
1383 #define b0s5_reg(x) ((x) & 0x1f)
1384 #define b0s7_imm(x) ((x) & 0x7f)
1385 #define b0s10_imm(x) ((x) & 0x3ff)
1386 #define b1s4_imm(x) (((x) >> 1) & 0xf)
1387 #define b1s9_imm(x) (((x) >> 1) & 0x1ff)
1388 #define b2s3_cc(x) (((x) >> 2) & 0x7)
1389 #define b4s2_regl(x) (((x) >> 4) & 0x3)
1390 #define b5s5_op(x) (((x) >> 5) & 0x1f)
1391 #define b5s5_reg(x) (((x) >> 5) & 0x1f)
1392 #define b6s4_op(x) (((x) >> 6) & 0xf)
1393 #define b7s3_reg(x) (((x) >> 7) & 0x7)
1395 /* 32-bit instruction formats, B and S refer to the lowest bit and the size
1396 respectively of the field extracted. */
1397 #define b0s6_op(x) ((x) & 0x3f)
1398 #define b0s11_op(x) ((x) & 0x7ff)
1399 #define b0s12_imm(x) ((x) & 0xfff)
1400 #define b0s16_imm(x) ((x) & 0xffff)
1401 #define b0s26_imm(x) ((x) & 0x3ffffff)
1402 #define b6s10_ext(x) (((x) >> 6) & 0x3ff)
1403 #define b11s5_reg(x) (((x) >> 11) & 0x1f)
1404 #define b12s4_op(x) (((x) >> 12) & 0xf)
1406 /* Return the size in bytes of the instruction INSN encoded in the ISA
1410 mips_insn_size (enum mips_isa isa
, ULONGEST insn
)
1415 if (micromips_op (insn
) == 0x1f)
1416 return 3 * MIPS_INSN16_SIZE
;
1417 else if (((micromips_op (insn
) & 0x4) == 0x4)
1418 || ((micromips_op (insn
) & 0x7) == 0x0))
1419 return 2 * MIPS_INSN16_SIZE
;
1421 return MIPS_INSN16_SIZE
;
1423 if ((insn
& 0xf800) == 0xf000)
1424 return 2 * MIPS_INSN16_SIZE
;
1426 return MIPS_INSN16_SIZE
;
1428 return MIPS_INSN32_SIZE
;
1430 internal_error (__FILE__
, __LINE__
, _("invalid ISA"));
1434 mips32_relative_offset (ULONGEST inst
)
1436 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
1439 /* Determine the address of the next instruction executed after the INST
1440 floating condition branch instruction at PC. COUNT specifies the
1441 number of the floating condition bits tested by the branch. */
1444 mips32_bc1_pc (struct gdbarch
*gdbarch
, struct frame_info
*frame
,
1445 ULONGEST inst
, CORE_ADDR pc
, int count
)
1447 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1448 int cnum
= (itype_rt (inst
) >> 2) & (count
- 1);
1449 int tf
= itype_rt (inst
) & 1;
1450 int mask
= (1 << count
) - 1;
1455 /* No way to handle; it'll most likely trap anyway. */
1458 fcs
= get_frame_register_unsigned (frame
, fcsr
);
1459 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1461 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1462 pc
+= mips32_relative_offset (inst
);
1469 /* Determine where to set a single step breakpoint while considering
1470 branch prediction. */
1473 mips32_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1475 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1478 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
1479 op
= itype_op (inst
);
1480 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch
1484 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1495 goto greater_branch
;
1500 else if (op
== 17 && itype_rs (inst
) == 8)
1501 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1502 pc
= mips32_bc1_pc (gdbarch
, frame
, inst
, pc
+ 4, 1);
1503 else if (op
== 17 && itype_rs (inst
) == 9
1504 && (itype_rt (inst
) & 2) == 0)
1505 /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */
1506 pc
= mips32_bc1_pc (gdbarch
, frame
, inst
, pc
+ 4, 2);
1507 else if (op
== 17 && itype_rs (inst
) == 10
1508 && (itype_rt (inst
) & 2) == 0)
1509 /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */
1510 pc
= mips32_bc1_pc (gdbarch
, frame
, inst
, pc
+ 4, 4);
1513 /* The new PC will be alternate mode. */
1517 reg
= jtype_target (inst
) << 2;
1518 /* Add 1 to indicate 16-bit mode -- invert ISA mode. */
1519 pc
= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + reg
+ 1;
1522 pc
+= 4; /* Not a branch, next instruction is easy. */
1525 { /* This gets way messy. */
1527 /* Further subdivide into SPECIAL, REGIMM and other. */
1528 switch (op
& 0x07) /* Extract bits 28,27,26. */
1530 case 0: /* SPECIAL */
1531 op
= rtype_funct (inst
);
1536 /* Set PC to that address. */
1537 pc
= get_frame_register_signed (frame
, rtype_rs (inst
));
1539 case 12: /* SYSCALL */
1541 struct gdbarch_tdep
*tdep
;
1543 tdep
= gdbarch_tdep (get_frame_arch (frame
));
1544 if (tdep
->syscall_next_pc
!= NULL
)
1545 pc
= tdep
->syscall_next_pc (frame
);
1554 break; /* end SPECIAL */
1555 case 1: /* REGIMM */
1557 op
= itype_rt (inst
); /* branch condition */
1562 case 16: /* BLTZAL */
1563 case 18: /* BLTZALL */
1565 if (get_frame_register_signed (frame
, itype_rs (inst
)) < 0)
1566 pc
+= mips32_relative_offset (inst
) + 4;
1568 pc
+= 8; /* after the delay slot */
1572 case 17: /* BGEZAL */
1573 case 19: /* BGEZALL */
1574 if (get_frame_register_signed (frame
, itype_rs (inst
)) >= 0)
1575 pc
+= mips32_relative_offset (inst
) + 4;
1577 pc
+= 8; /* after the delay slot */
1579 case 0x1c: /* BPOSGE32 */
1580 case 0x1e: /* BPOSGE64 */
1582 if (itype_rs (inst
) == 0)
1584 unsigned int pos
= (op
& 2) ? 64 : 32;
1585 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
1588 /* No way to handle; it'll most likely trap anyway. */
1591 if ((get_frame_register_unsigned (frame
,
1592 dspctl
) & 0x7f) >= pos
)
1593 pc
+= mips32_relative_offset (inst
);
1598 /* All of the other instructions in the REGIMM category */
1603 break; /* end REGIMM */
1608 reg
= jtype_target (inst
) << 2;
1609 /* Upper four bits get never changed... */
1610 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1613 case 4: /* BEQ, BEQL */
1615 if (get_frame_register_signed (frame
, itype_rs (inst
)) ==
1616 get_frame_register_signed (frame
, itype_rt (inst
)))
1617 pc
+= mips32_relative_offset (inst
) + 4;
1621 case 5: /* BNE, BNEL */
1623 if (get_frame_register_signed (frame
, itype_rs (inst
)) !=
1624 get_frame_register_signed (frame
, itype_rt (inst
)))
1625 pc
+= mips32_relative_offset (inst
) + 4;
1629 case 6: /* BLEZ, BLEZL */
1630 if (get_frame_register_signed (frame
, itype_rs (inst
)) <= 0)
1631 pc
+= mips32_relative_offset (inst
) + 4;
1637 greater_branch
: /* BGTZ, BGTZL */
1638 if (get_frame_register_signed (frame
, itype_rs (inst
)) > 0)
1639 pc
+= mips32_relative_offset (inst
) + 4;
1646 } /* mips32_next_pc */
1648 /* Extract the 7-bit signed immediate offset from the microMIPS instruction
1652 micromips_relative_offset7 (ULONGEST insn
)
1654 return ((b0s7_imm (insn
) ^ 0x40) - 0x40) << 1;
1657 /* Extract the 10-bit signed immediate offset from the microMIPS instruction
1661 micromips_relative_offset10 (ULONGEST insn
)
1663 return ((b0s10_imm (insn
) ^ 0x200) - 0x200) << 1;
1666 /* Extract the 16-bit signed immediate offset from the microMIPS instruction
1670 micromips_relative_offset16 (ULONGEST insn
)
1672 return ((b0s16_imm (insn
) ^ 0x8000) - 0x8000) << 1;
1675 /* Return the size in bytes of the microMIPS instruction at the address PC. */
1678 micromips_pc_insn_size (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1682 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1683 return mips_insn_size (ISA_MICROMIPS
, insn
);
1686 /* Calculate the address of the next microMIPS instruction to execute
1687 after the INSN coprocessor 1 conditional branch instruction at the
1688 address PC. COUNT denotes the number of coprocessor condition bits
1689 examined by the branch. */
1692 micromips_bc1_pc (struct gdbarch
*gdbarch
, struct frame_info
*frame
,
1693 ULONGEST insn
, CORE_ADDR pc
, int count
)
1695 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1696 int cnum
= b2s3_cc (insn
>> 16) & (count
- 1);
1697 int tf
= b5s5_op (insn
>> 16) & 1;
1698 int mask
= (1 << count
) - 1;
1703 /* No way to handle; it'll most likely trap anyway. */
1706 fcs
= get_frame_register_unsigned (frame
, fcsr
);
1707 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1709 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1710 pc
+= micromips_relative_offset16 (insn
);
1712 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1717 /* Calculate the address of the next microMIPS instruction to execute
1718 after the instruction at the address PC. */
1721 micromips_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1723 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1726 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1727 pc
+= MIPS_INSN16_SIZE
;
1728 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
1730 /* 48-bit instructions. */
1731 case 3 * MIPS_INSN16_SIZE
: /* POOL48A: bits 011111 */
1732 /* No branch or jump instructions in this category. */
1733 pc
+= 2 * MIPS_INSN16_SIZE
;
1736 /* 32-bit instructions. */
1737 case 2 * MIPS_INSN16_SIZE
:
1739 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1740 pc
+= MIPS_INSN16_SIZE
;
1741 switch (micromips_op (insn
>> 16))
1743 case 0x00: /* POOL32A: bits 000000 */
1744 if (b0s6_op (insn
) == 0x3c
1745 /* POOL32Axf: bits 000000 ... 111100 */
1746 && (b6s10_ext (insn
) & 0x2bf) == 0x3c)
1747 /* JALR, JALR.HB: 000000 000x111100 111100 */
1748 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
1749 pc
= get_frame_register_signed (frame
, b0s5_reg (insn
>> 16));
1752 case 0x10: /* POOL32I: bits 010000 */
1753 switch (b5s5_op (insn
>> 16))
1755 case 0x00: /* BLTZ: bits 010000 00000 */
1756 case 0x01: /* BLTZAL: bits 010000 00001 */
1757 case 0x11: /* BLTZALS: bits 010000 10001 */
1758 if (get_frame_register_signed (frame
,
1759 b0s5_reg (insn
>> 16)) < 0)
1760 pc
+= micromips_relative_offset16 (insn
);
1762 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1765 case 0x02: /* BGEZ: bits 010000 00010 */
1766 case 0x03: /* BGEZAL: bits 010000 00011 */
1767 case 0x13: /* BGEZALS: bits 010000 10011 */
1768 if (get_frame_register_signed (frame
,
1769 b0s5_reg (insn
>> 16)) >= 0)
1770 pc
+= micromips_relative_offset16 (insn
);
1772 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1775 case 0x04: /* BLEZ: bits 010000 00100 */
1776 if (get_frame_register_signed (frame
,
1777 b0s5_reg (insn
>> 16)) <= 0)
1778 pc
+= micromips_relative_offset16 (insn
);
1780 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1783 case 0x05: /* BNEZC: bits 010000 00101 */
1784 if (get_frame_register_signed (frame
,
1785 b0s5_reg (insn
>> 16)) != 0)
1786 pc
+= micromips_relative_offset16 (insn
);
1789 case 0x06: /* BGTZ: bits 010000 00110 */
1790 if (get_frame_register_signed (frame
,
1791 b0s5_reg (insn
>> 16)) > 0)
1792 pc
+= micromips_relative_offset16 (insn
);
1794 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1797 case 0x07: /* BEQZC: bits 010000 00111 */
1798 if (get_frame_register_signed (frame
,
1799 b0s5_reg (insn
>> 16)) == 0)
1800 pc
+= micromips_relative_offset16 (insn
);
1803 case 0x14: /* BC2F: bits 010000 10100 xxx00 */
1804 case 0x15: /* BC2T: bits 010000 10101 xxx00 */
1805 if (((insn
>> 16) & 0x3) == 0x0)
1806 /* BC2F, BC2T: don't know how to handle these. */
1810 case 0x1a: /* BPOSGE64: bits 010000 11010 */
1811 case 0x1b: /* BPOSGE32: bits 010000 11011 */
1813 unsigned int pos
= (b5s5_op (insn
>> 16) & 1) ? 32 : 64;
1814 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
1817 /* No way to handle; it'll most likely trap anyway. */
1820 if ((get_frame_register_unsigned (frame
,
1821 dspctl
) & 0x7f) >= pos
)
1822 pc
+= micromips_relative_offset16 (insn
);
1824 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1828 case 0x1c: /* BC1F: bits 010000 11100 xxx00 */
1829 /* BC1ANY2F: bits 010000 11100 xxx01 */
1830 case 0x1d: /* BC1T: bits 010000 11101 xxx00 */
1831 /* BC1ANY2T: bits 010000 11101 xxx01 */
1832 if (((insn
>> 16) & 0x2) == 0x0)
1833 pc
= micromips_bc1_pc (gdbarch
, frame
, insn
, pc
,
1834 ((insn
>> 16) & 0x1) + 1);
1837 case 0x1e: /* BC1ANY4F: bits 010000 11110 xxx01 */
1838 case 0x1f: /* BC1ANY4T: bits 010000 11111 xxx01 */
1839 if (((insn
>> 16) & 0x3) == 0x1)
1840 pc
= micromips_bc1_pc (gdbarch
, frame
, insn
, pc
, 4);
1845 case 0x1d: /* JALS: bits 011101 */
1846 case 0x35: /* J: bits 110101 */
1847 case 0x3d: /* JAL: bits 111101 */
1848 pc
= ((pc
| 0x7fffffe) ^ 0x7fffffe) | (b0s26_imm (insn
) << 1);
1851 case 0x25: /* BEQ: bits 100101 */
1852 if (get_frame_register_signed (frame
, b0s5_reg (insn
>> 16))
1853 == get_frame_register_signed (frame
, b5s5_reg (insn
>> 16)))
1854 pc
+= micromips_relative_offset16 (insn
);
1856 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1859 case 0x2d: /* BNE: bits 101101 */
1860 if (get_frame_register_signed (frame
, b0s5_reg (insn
>> 16))
1861 != get_frame_register_signed (frame
, b5s5_reg (insn
>> 16)))
1862 pc
+= micromips_relative_offset16 (insn
);
1864 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1867 case 0x3c: /* JALX: bits 111100 */
1868 pc
= ((pc
| 0xfffffff) ^ 0xfffffff) | (b0s26_imm (insn
) << 2);
1873 /* 16-bit instructions. */
1874 case MIPS_INSN16_SIZE
:
1875 switch (micromips_op (insn
))
1877 case 0x11: /* POOL16C: bits 010001 */
1878 if ((b5s5_op (insn
) & 0x1c) == 0xc)
1879 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
1880 pc
= get_frame_register_signed (frame
, b0s5_reg (insn
));
1881 else if (b5s5_op (insn
) == 0x18)
1882 /* JRADDIUSP: bits 010001 11000 */
1883 pc
= get_frame_register_signed (frame
, MIPS_RA_REGNUM
);
1886 case 0x23: /* BEQZ16: bits 100011 */
1888 int rs
= mips_reg3_to_reg
[b7s3_reg (insn
)];
1890 if (get_frame_register_signed (frame
, rs
) == 0)
1891 pc
+= micromips_relative_offset7 (insn
);
1893 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1897 case 0x2b: /* BNEZ16: bits 101011 */
1899 int rs
= mips_reg3_to_reg
[b7s3_reg (insn
)];
1901 if (get_frame_register_signed (frame
, rs
) != 0)
1902 pc
+= micromips_relative_offset7 (insn
);
1904 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1908 case 0x33: /* B16: bits 110011 */
1909 pc
+= micromips_relative_offset10 (insn
);
1918 /* Decoding the next place to set a breakpoint is irregular for the
1919 mips 16 variant, but fortunately, there fewer instructions. We have
1920 to cope ith extensions for 16 bit instructions and a pair of actual
1921 32 bit instructions. We dont want to set a single step instruction
1922 on the extend instruction either. */
1924 /* Lots of mips16 instruction formats */
1925 /* Predicting jumps requires itype,ritype,i8type
1926 and their extensions extItype,extritype,extI8type. */
1927 enum mips16_inst_fmts
1929 itype
, /* 0 immediate 5,10 */
1930 ritype
, /* 1 5,3,8 */
1931 rrtype
, /* 2 5,3,3,5 */
1932 rritype
, /* 3 5,3,3,5 */
1933 rrrtype
, /* 4 5,3,3,3,2 */
1934 rriatype
, /* 5 5,3,3,1,4 */
1935 shifttype
, /* 6 5,3,3,3,2 */
1936 i8type
, /* 7 5,3,8 */
1937 i8movtype
, /* 8 5,3,3,5 */
1938 i8mov32rtype
, /* 9 5,3,5,3 */
1939 i64type
, /* 10 5,3,8 */
1940 ri64type
, /* 11 5,3,3,5 */
1941 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1942 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1943 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1944 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1945 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1946 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1947 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1948 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1949 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1950 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1952 /* I am heaping all the fields of the formats into one structure and
1953 then, only the fields which are involved in instruction extension. */
1957 unsigned int regx
; /* Function in i8 type. */
1962 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1963 for the bits which make up the immediate extension. */
1966 extended_offset (unsigned int extension
)
1970 value
= (extension
>> 16) & 0x1f; /* Extract 15:11. */
1972 value
|= (extension
>> 21) & 0x3f; /* Extract 10:5. */
1974 value
|= extension
& 0x1f; /* Extract 4:0. */
1979 /* Only call this function if you know that this is an extendable
1980 instruction. It won't malfunction, but why make excess remote memory
1981 references? If the immediate operands get sign extended or something,
1982 do it after the extension is performed. */
1983 /* FIXME: Every one of these cases needs to worry about sign extension
1984 when the offset is to be used in relative addressing. */
1987 fetch_mips_16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1989 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1991 pc
&= 0xfffffffe; /* Clear the low order bit. */
1992 target_read_memory (pc
, buf
, 2);
1993 return extract_unsigned_integer (buf
, 2, byte_order
);
1997 unpack_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
1998 unsigned int extension
,
2000 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
2005 switch (insn_format
)
2012 value
= extended_offset ((extension
<< 16) | inst
);
2013 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
2017 value
= inst
& 0x7ff;
2018 value
= (value
^ 0x400) - 0x400; /* Sign-extend. */
2027 { /* A register identifier and an offset. */
2028 /* Most of the fields are the same as I type but the
2029 immediate value is of a different length. */
2033 value
= extended_offset ((extension
<< 16) | inst
);
2034 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
2038 value
= inst
& 0xff; /* 8 bits */
2039 value
= (value
^ 0x80) - 0x80; /* Sign-extend. */
2042 regx
= (inst
>> 8) & 0x07; /* i8 funct */
2048 unsigned long value
;
2049 unsigned int nexthalf
;
2050 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
2051 value
= value
<< 16;
2052 nexthalf
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, pc
+ 2, NULL
);
2053 /* Low bit still set. */
2061 internal_error (__FILE__
, __LINE__
, _("bad switch"));
2063 upk
->offset
= offset
;
2070 add_offset_16 (CORE_ADDR pc
, int offset
)
2072 return ((offset
<< 2) | ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)));
2076 extended_mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
,
2077 unsigned int extension
, unsigned int insn
)
2079 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2080 int op
= (insn
>> 11);
2083 case 2: /* Branch */
2085 struct upk_mips16 upk
;
2086 unpack_mips16 (gdbarch
, pc
, extension
, insn
, itype
, &upk
);
2087 pc
+= (upk
.offset
<< 1) + 2;
2090 case 3: /* JAL , JALX - Watch out, these are 32 bit
2093 struct upk_mips16 upk
;
2094 unpack_mips16 (gdbarch
, pc
, extension
, insn
, jalxtype
, &upk
);
2095 pc
= add_offset_16 (pc
, upk
.offset
);
2096 if ((insn
>> 10) & 0x01) /* Exchange mode */
2097 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode. */
2104 struct upk_mips16 upk
;
2106 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
2107 reg
= get_frame_register_signed (frame
, mips_reg3_to_reg
[upk
.regx
]);
2109 pc
+= (upk
.offset
<< 1) + 2;
2116 struct upk_mips16 upk
;
2118 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
2119 reg
= get_frame_register_signed (frame
, mips_reg3_to_reg
[upk
.regx
]);
2121 pc
+= (upk
.offset
<< 1) + 2;
2126 case 12: /* I8 Formats btez btnez */
2128 struct upk_mips16 upk
;
2130 unpack_mips16 (gdbarch
, pc
, extension
, insn
, i8type
, &upk
);
2131 /* upk.regx contains the opcode */
2132 reg
= get_frame_register_signed (frame
, 24); /* Test register is 24 */
2133 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
2134 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
2135 /* pc = add_offset_16(pc,upk.offset) ; */
2136 pc
+= (upk
.offset
<< 1) + 2;
2141 case 29: /* RR Formats JR, JALR, JALR-RA */
2143 struct upk_mips16 upk
;
2144 /* upk.fmt = rrtype; */
2149 upk
.regx
= (insn
>> 8) & 0x07;
2150 upk
.regy
= (insn
>> 5) & 0x07;
2151 if ((upk
.regy
& 1) == 0)
2152 reg
= mips_reg3_to_reg
[upk
.regx
];
2154 reg
= 31; /* Function return instruction. */
2155 pc
= get_frame_register_signed (frame
, reg
);
2162 /* This is an instruction extension. Fetch the real instruction
2163 (which follows the extension) and decode things based on
2167 pc
= extended_mips16_next_pc (frame
, pc
, insn
,
2168 fetch_mips_16 (gdbarch
, pc
));
2181 mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
2183 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2184 unsigned int insn
= fetch_mips_16 (gdbarch
, pc
);
2185 return extended_mips16_next_pc (frame
, pc
, 0, insn
);
2188 /* The mips_next_pc function supports single_step when the remote
2189 target monitor or stub is not developed enough to do a single_step.
2190 It works by decoding the current instruction and predicting where a
2191 branch will go. This isnt hard because all the data is available.
2192 The MIPS32, MIPS16 and microMIPS variants are quite different. */
2194 mips_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
2196 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2198 if (mips_pc_is_mips16 (gdbarch
, pc
))
2199 return mips16_next_pc (frame
, pc
);
2200 else if (mips_pc_is_micromips (gdbarch
, pc
))
2201 return micromips_next_pc (frame
, pc
);
2203 return mips32_next_pc (frame
, pc
);
2206 struct mips_frame_cache
2209 struct trad_frame_saved_reg
*saved_regs
;
2212 /* Set a register's saved stack address in temp_saved_regs. If an
2213 address has already been set for this register, do nothing; this
2214 way we will only recognize the first save of a given register in a
2217 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
2218 [gdbarch_num_regs .. 2*gdbarch_num_regs).
2219 Strictly speaking, only the second range is used as it is only second
2220 range (the ABI instead of ISA registers) that comes into play when finding
2221 saved registers in a frame. */
2224 set_reg_offset (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
,
2225 int regnum
, CORE_ADDR offset
)
2227 if (this_cache
!= NULL
2228 && this_cache
->saved_regs
[regnum
].addr
== -1)
2230 this_cache
->saved_regs
[regnum
+ 0 * gdbarch_num_regs (gdbarch
)].addr
2232 this_cache
->saved_regs
[regnum
+ 1 * gdbarch_num_regs (gdbarch
)].addr
2238 /* Fetch the immediate value from a MIPS16 instruction.
2239 If the previous instruction was an EXTEND, use it to extend
2240 the upper bits of the immediate value. This is a helper function
2241 for mips16_scan_prologue. */
2244 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
2245 unsigned short inst
, /* current instruction */
2246 int nbits
, /* number of bits in imm field */
2247 int scale
, /* scale factor to be applied to imm */
2248 int is_signed
) /* is the imm field signed? */
2252 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
2254 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
2255 if (offset
& 0x8000) /* check for negative extend */
2256 offset
= 0 - (0x10000 - (offset
& 0xffff));
2257 return offset
| (inst
& 0x1f);
2261 int max_imm
= 1 << nbits
;
2262 int mask
= max_imm
- 1;
2263 int sign_bit
= max_imm
>> 1;
2265 offset
= inst
& mask
;
2266 if (is_signed
&& (offset
& sign_bit
))
2267 offset
= 0 - (max_imm
- offset
);
2268 return offset
* scale
;
2273 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
2274 the associated FRAME_CACHE if not null.
2275 Return the address of the first instruction past the prologue. */
2278 mips16_scan_prologue (struct gdbarch
*gdbarch
,
2279 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2280 struct frame_info
*this_frame
,
2281 struct mips_frame_cache
*this_cache
)
2284 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer. */
2286 long frame_offset
= 0; /* Size of stack frame. */
2287 long frame_adjust
= 0; /* Offset of FP from SP. */
2288 int frame_reg
= MIPS_SP_REGNUM
;
2289 unsigned short prev_inst
= 0; /* saved copy of previous instruction. */
2290 unsigned inst
= 0; /* current instruction */
2291 unsigned entry_inst
= 0; /* the entry instruction */
2292 unsigned save_inst
= 0; /* the save instruction */
2295 int extend_bytes
= 0;
2296 int prev_extend_bytes
;
2297 CORE_ADDR end_prologue_addr
= 0;
2299 /* Can be called when there's no process, and hence when there's no
2301 if (this_frame
!= NULL
)
2302 sp
= get_frame_register_signed (this_frame
,
2303 gdbarch_num_regs (gdbarch
)
2308 if (limit_pc
> start_pc
+ 200)
2309 limit_pc
= start_pc
+ 200;
2311 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
2313 /* Save the previous instruction. If it's an EXTEND, we'll extract
2314 the immediate offset extension from it in mips16_get_imm. */
2317 /* Fetch and decode the instruction. */
2318 inst
= (unsigned short) mips_fetch_instruction (gdbarch
, ISA_MIPS16
,
2321 /* Normally we ignore extend instructions. However, if it is
2322 not followed by a valid prologue instruction, then this
2323 instruction is not part of the prologue either. We must
2324 remember in this case to adjust the end_prologue_addr back
2326 if ((inst
& 0xf800) == 0xf000) /* extend */
2328 extend_bytes
= MIPS_INSN16_SIZE
;
2332 prev_extend_bytes
= extend_bytes
;
2335 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2336 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2338 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
2339 if (offset
< 0) /* Negative stack adjustment? */
2340 frame_offset
-= offset
;
2342 /* Exit loop if a positive stack adjustment is found, which
2343 usually means that the stack cleanup code in the function
2344 epilogue is reached. */
2347 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
2349 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2350 reg
= mips_reg3_to_reg
[(inst
& 0x700) >> 8];
2351 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2353 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
2355 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2356 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2357 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2359 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
2361 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2362 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2364 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2366 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
2367 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2369 else if (inst
== 0x673d) /* move $s1, $sp */
2374 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
2376 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2377 frame_addr
= sp
+ offset
;
2379 frame_adjust
= offset
;
2381 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2383 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
2384 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2385 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
2387 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2389 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2390 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2391 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
2393 else if ((inst
& 0xf81f) == 0xe809
2394 && (inst
& 0x700) != 0x700) /* entry */
2395 entry_inst
= inst
; /* Save for later processing. */
2396 else if ((inst
& 0xff80) == 0x6480) /* save */
2398 save_inst
= inst
; /* Save for later processing. */
2399 if (prev_extend_bytes
) /* extend */
2400 save_inst
|= prev_inst
<< 16;
2402 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
2403 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
2404 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
2406 /* This instruction is part of the prologue, but we don't
2407 need to do anything special to handle it. */
2411 /* This instruction is not an instruction typically found
2412 in a prologue, so we must have reached the end of the
2414 if (end_prologue_addr
== 0)
2415 end_prologue_addr
= cur_pc
- prev_extend_bytes
;
2419 /* The entry instruction is typically the first instruction in a function,
2420 and it stores registers at offsets relative to the value of the old SP
2421 (before the prologue). But the value of the sp parameter to this
2422 function is the new SP (after the prologue has been executed). So we
2423 can't calculate those offsets until we've seen the entire prologue,
2424 and can calculate what the old SP must have been. */
2425 if (entry_inst
!= 0)
2427 int areg_count
= (entry_inst
>> 8) & 7;
2428 int sreg_count
= (entry_inst
>> 6) & 3;
2430 /* The entry instruction always subtracts 32 from the SP. */
2433 /* Now we can calculate what the SP must have been at the
2434 start of the function prologue. */
2437 /* Check if a0-a3 were saved in the caller's argument save area. */
2438 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
2440 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2441 offset
+= mips_abi_regsize (gdbarch
);
2444 /* Check if the ra register was pushed on the stack. */
2446 if (entry_inst
& 0x20)
2448 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2449 offset
-= mips_abi_regsize (gdbarch
);
2452 /* Check if the s0 and s1 registers were pushed on the stack. */
2453 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2455 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2456 offset
-= mips_abi_regsize (gdbarch
);
2460 /* The SAVE instruction is similar to ENTRY, except that defined by the
2461 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
2462 size of the frame is specified as an immediate field of instruction
2463 and an extended variation exists which lets additional registers and
2464 frame space to be specified. The instruction always treats registers
2465 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
2466 if (save_inst
!= 0 && mips_abi_regsize (gdbarch
) == 4)
2468 static int args_table
[16] = {
2469 0, 0, 0, 0, 1, 1, 1, 1,
2470 2, 2, 2, 0, 3, 3, 4, -1,
2472 static int astatic_table
[16] = {
2473 0, 1, 2, 3, 0, 1, 2, 3,
2474 0, 1, 2, 4, 0, 1, 0, -1,
2476 int aregs
= (save_inst
>> 16) & 0xf;
2477 int xsregs
= (save_inst
>> 24) & 0x7;
2478 int args
= args_table
[aregs
];
2479 int astatic
= astatic_table
[aregs
];
2484 warning (_("Invalid number of argument registers encoded in SAVE."));
2489 warning (_("Invalid number of static registers encoded in SAVE."));
2493 /* For standard SAVE the frame size of 0 means 128. */
2494 frame_size
= ((save_inst
>> 16) & 0xf0) | (save_inst
& 0xf);
2495 if (frame_size
== 0 && (save_inst
>> 16) == 0)
2498 frame_offset
+= frame_size
;
2500 /* Now we can calculate what the SP must have been at the
2501 start of the function prologue. */
2504 /* Check if A0-A3 were saved in the caller's argument save area. */
2505 for (reg
= MIPS_A0_REGNUM
, offset
= 0; reg
< args
+ 4; reg
++)
2507 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2508 offset
+= mips_abi_regsize (gdbarch
);
2513 /* Check if the RA register was pushed on the stack. */
2514 if (save_inst
& 0x40)
2516 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2517 offset
-= mips_abi_regsize (gdbarch
);
2520 /* Check if the S8 register was pushed on the stack. */
2523 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ offset
);
2524 offset
-= mips_abi_regsize (gdbarch
);
2527 /* Check if S2-S7 were pushed on the stack. */
2528 for (reg
= 18 + xsregs
- 1; reg
> 18 - 1; reg
--)
2530 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2531 offset
-= mips_abi_regsize (gdbarch
);
2534 /* Check if the S1 register was pushed on the stack. */
2535 if (save_inst
& 0x10)
2537 set_reg_offset (gdbarch
, this_cache
, 17, sp
+ offset
);
2538 offset
-= mips_abi_regsize (gdbarch
);
2540 /* Check if the S0 register was pushed on the stack. */
2541 if (save_inst
& 0x20)
2543 set_reg_offset (gdbarch
, this_cache
, 16, sp
+ offset
);
2544 offset
-= mips_abi_regsize (gdbarch
);
2547 /* Check if A0-A3 were pushed on the stack. */
2548 for (reg
= MIPS_A0_REGNUM
+ 3; reg
> MIPS_A0_REGNUM
+ 3 - astatic
; reg
--)
2550 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2551 offset
-= mips_abi_regsize (gdbarch
);
2555 if (this_cache
!= NULL
)
2558 (get_frame_register_signed (this_frame
,
2559 gdbarch_num_regs (gdbarch
) + frame_reg
)
2560 + frame_offset
- frame_adjust
);
2561 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
2562 be able to get rid of the assignment below, evetually. But it's
2563 still needed for now. */
2564 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2565 + mips_regnum (gdbarch
)->pc
]
2566 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
2569 /* If we didn't reach the end of the prologue when scanning the function
2570 instructions, then set end_prologue_addr to the address of the
2571 instruction immediately after the last one we scanned. */
2572 if (end_prologue_addr
== 0)
2573 end_prologue_addr
= cur_pc
;
2575 return end_prologue_addr
;
2578 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
2579 Procedures that use the 32-bit instruction set are handled by the
2580 mips_insn32 unwinder. */
2582 static struct mips_frame_cache
*
2583 mips_insn16_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2585 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2586 struct mips_frame_cache
*cache
;
2588 if ((*this_cache
) != NULL
)
2589 return (*this_cache
);
2590 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2591 (*this_cache
) = cache
;
2592 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2594 /* Analyze the function prologue. */
2596 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2597 CORE_ADDR start_addr
;
2599 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2600 if (start_addr
== 0)
2601 start_addr
= heuristic_proc_start (gdbarch
, pc
);
2602 /* We can't analyze the prologue if we couldn't find the begining
2604 if (start_addr
== 0)
2607 mips16_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
, *this_cache
);
2610 /* gdbarch_sp_regnum contains the value and not the address. */
2611 trad_frame_set_value (cache
->saved_regs
,
2612 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
2615 return (*this_cache
);
2619 mips_insn16_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2620 struct frame_id
*this_id
)
2622 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2624 /* This marks the outermost frame. */
2625 if (info
->base
== 0)
2627 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2630 static struct value
*
2631 mips_insn16_frame_prev_register (struct frame_info
*this_frame
,
2632 void **this_cache
, int regnum
)
2634 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2636 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2640 mips_insn16_frame_sniffer (const struct frame_unwind
*self
,
2641 struct frame_info
*this_frame
, void **this_cache
)
2643 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2644 CORE_ADDR pc
= get_frame_pc (this_frame
);
2645 if (mips_pc_is_mips16 (gdbarch
, pc
))
2650 static const struct frame_unwind mips_insn16_frame_unwind
=
2653 default_frame_unwind_stop_reason
,
2654 mips_insn16_frame_this_id
,
2655 mips_insn16_frame_prev_register
,
2657 mips_insn16_frame_sniffer
2661 mips_insn16_frame_base_address (struct frame_info
*this_frame
,
2664 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2669 static const struct frame_base mips_insn16_frame_base
=
2671 &mips_insn16_frame_unwind
,
2672 mips_insn16_frame_base_address
,
2673 mips_insn16_frame_base_address
,
2674 mips_insn16_frame_base_address
2677 static const struct frame_base
*
2678 mips_insn16_frame_base_sniffer (struct frame_info
*this_frame
)
2680 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2681 CORE_ADDR pc
= get_frame_pc (this_frame
);
2682 if (mips_pc_is_mips16 (gdbarch
, pc
))
2683 return &mips_insn16_frame_base
;
2688 /* Decode a 9-bit signed immediate argument of ADDIUSP -- -2 is mapped
2689 to -258, -1 -- to -257, 0 -- to 256, 1 -- to 257 and other values are
2690 interpreted directly, and then multiplied by 4. */
2693 micromips_decode_imm9 (int imm
)
2695 imm
= (imm
^ 0x100) - 0x100;
2696 if (imm
> -3 && imm
< 2)
2701 /* Analyze the function prologue from START_PC to LIMIT_PC. Return
2702 the address of the first instruction past the prologue. */
2705 micromips_scan_prologue (struct gdbarch
*gdbarch
,
2706 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2707 struct frame_info
*this_frame
,
2708 struct mips_frame_cache
*this_cache
)
2710 CORE_ADDR end_prologue_addr
= 0;
2711 int prev_non_prologue_insn
= 0;
2712 int frame_reg
= MIPS_SP_REGNUM
;
2713 int this_non_prologue_insn
;
2714 int non_prologue_insns
= 0;
2715 long frame_offset
= 0; /* Size of stack frame. */
2716 long frame_adjust
= 0; /* Offset of FP from SP. */
2717 CORE_ADDR frame_addr
= 0; /* Value of $30, used as frame pointer. */
2720 ULONGEST insn
; /* current instruction */
2724 long v1_off
= 0; /* The assumption is LUI will replace it. */
2735 /* Can be called when there's no process, and hence when there's no
2737 if (this_frame
!= NULL
)
2738 sp
= get_frame_register_signed (this_frame
,
2739 gdbarch_num_regs (gdbarch
)
2744 if (limit_pc
> start_pc
+ 200)
2745 limit_pc
= start_pc
+ 200;
2748 /* Permit at most one non-prologue non-control-transfer instruction
2749 in the middle which may have been reordered by the compiler for
2751 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= loc
)
2753 this_non_prologue_insn
= 0;
2756 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, cur_pc
, NULL
);
2757 loc
+= MIPS_INSN16_SIZE
;
2758 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
2760 /* 48-bit instructions. */
2761 case 3 * MIPS_INSN16_SIZE
:
2762 /* No prologue instructions in this category. */
2763 this_non_prologue_insn
= 1;
2764 loc
+= 2 * MIPS_INSN16_SIZE
;
2767 /* 32-bit instructions. */
2768 case 2 * MIPS_INSN16_SIZE
:
2770 insn
|= mips_fetch_instruction (gdbarch
,
2771 ISA_MICROMIPS
, cur_pc
+ loc
, NULL
);
2772 loc
+= MIPS_INSN16_SIZE
;
2773 switch (micromips_op (insn
>> 16))
2775 /* Record $sp/$fp adjustment. */
2776 /* Discard (D)ADDU $gp,$jp used for PIC code. */
2777 case 0x0: /* POOL32A: bits 000000 */
2778 case 0x16: /* POOL32S: bits 010110 */
2779 op
= b0s11_op (insn
);
2780 sreg
= b0s5_reg (insn
>> 16);
2781 treg
= b5s5_reg (insn
>> 16);
2782 dreg
= b11s5_reg (insn
);
2784 /* SUBU: bits 000000 00111010000 */
2785 /* DSUBU: bits 010110 00111010000 */
2786 && dreg
== MIPS_SP_REGNUM
&& sreg
== MIPS_SP_REGNUM
2788 /* (D)SUBU $sp, $v1 */
2790 else if (op
!= 0x150
2791 /* ADDU: bits 000000 00101010000 */
2792 /* DADDU: bits 010110 00101010000 */
2793 || dreg
!= 28 || sreg
!= 28 || treg
!= MIPS_T9_REGNUM
)
2794 this_non_prologue_insn
= 1;
2797 case 0x8: /* POOL32B: bits 001000 */
2798 op
= b12s4_op (insn
);
2799 breg
= b0s5_reg (insn
>> 16);
2800 reglist
= sreg
= b5s5_reg (insn
>> 16);
2801 offset
= (b0s12_imm (insn
) ^ 0x800) - 0x800;
2802 if ((op
== 0x9 || op
== 0xc)
2803 /* SWP: bits 001000 1001 */
2804 /* SDP: bits 001000 1100 */
2805 && breg
== MIPS_SP_REGNUM
&& sreg
< MIPS_RA_REGNUM
)
2806 /* S[DW]P reg,offset($sp) */
2808 s
= 4 << ((b12s4_op (insn
) & 0x4) == 0x4);
2809 set_reg_offset (gdbarch
, this_cache
,
2811 set_reg_offset (gdbarch
, this_cache
,
2812 sreg
+ 1, sp
+ offset
+ s
);
2814 else if ((op
== 0xd || op
== 0xf)
2815 /* SWM: bits 001000 1101 */
2816 /* SDM: bits 001000 1111 */
2817 && breg
== MIPS_SP_REGNUM
2818 /* SWM reglist,offset($sp) */
2819 && ((reglist
>= 1 && reglist
<= 9)
2820 || (reglist
>= 16 && reglist
<= 25)))
2822 int sreglist
= min(reglist
& 0xf, 8);
2824 s
= 4 << ((b12s4_op (insn
) & 0x2) == 0x2);
2825 for (i
= 0; i
< sreglist
; i
++)
2826 set_reg_offset (gdbarch
, this_cache
, 16 + i
, sp
+ s
* i
);
2827 if ((reglist
& 0xf) > 8)
2828 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ s
* i
++);
2829 if ((reglist
& 0x10) == 0x10)
2830 set_reg_offset (gdbarch
, this_cache
,
2831 MIPS_RA_REGNUM
, sp
+ s
* i
++);
2834 this_non_prologue_insn
= 1;
2837 /* Record $sp/$fp adjustment. */
2838 /* Discard (D)ADDIU $gp used for PIC code. */
2839 case 0xc: /* ADDIU: bits 001100 */
2840 case 0x17: /* DADDIU: bits 010111 */
2841 sreg
= b0s5_reg (insn
>> 16);
2842 dreg
= b5s5_reg (insn
>> 16);
2843 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
2844 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
)
2845 /* (D)ADDIU $sp, imm */
2847 else if (sreg
== MIPS_SP_REGNUM
&& dreg
== 30)
2848 /* (D)ADDIU $fp, $sp, imm */
2850 frame_addr
= sp
+ offset
;
2851 frame_adjust
= offset
;
2854 else if (sreg
!= 28 || dreg
!= 28)
2855 /* (D)ADDIU $gp, imm */
2856 this_non_prologue_insn
= 1;
2859 /* LUI $v1 is used for larger $sp adjustments. */
2860 /* Discard LUI $gp is used for PIC code. */
2861 case 0x10: /* POOL32I: bits 010000 */
2862 if (b5s5_op (insn
>> 16) == 0xd
2863 /* LUI: bits 010000 001101 */
2864 && b0s5_reg (insn
>> 16) == 3)
2866 v1_off
= ((b0s16_imm (insn
) << 16) ^ 0x80000000) - 0x80000000;
2867 else if (b5s5_op (insn
>> 16) != 0xd
2868 /* LUI: bits 010000 001101 */
2869 || b0s5_reg (insn
>> 16) != 28)
2871 this_non_prologue_insn
= 1;
2874 /* ORI $v1 is used for larger $sp adjustments. */
2875 case 0x14: /* ORI: bits 010100 */
2876 sreg
= b0s5_reg (insn
>> 16);
2877 dreg
= b5s5_reg (insn
>> 16);
2878 if (sreg
== 3 && dreg
== 3)
2880 v1_off
|= b0s16_imm (insn
);
2882 this_non_prologue_insn
= 1;
2885 case 0x26: /* SWC1: bits 100110 */
2886 case 0x2e: /* SDC1: bits 101110 */
2887 breg
= b0s5_reg (insn
>> 16);
2888 if (breg
!= MIPS_SP_REGNUM
)
2889 /* S[DW]C1 reg,offset($sp) */
2890 this_non_prologue_insn
= 1;
2893 case 0x36: /* SD: bits 110110 */
2894 case 0x3e: /* SW: bits 111110 */
2895 breg
= b0s5_reg (insn
>> 16);
2896 sreg
= b5s5_reg (insn
>> 16);
2897 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
2898 if (breg
== MIPS_SP_REGNUM
)
2899 /* S[DW] reg,offset($sp) */
2900 set_reg_offset (gdbarch
, this_cache
, sreg
, sp
+ offset
);
2902 this_non_prologue_insn
= 1;
2906 this_non_prologue_insn
= 1;
2911 /* 16-bit instructions. */
2912 case MIPS_INSN16_SIZE
:
2913 switch (micromips_op (insn
))
2915 case 0x3: /* MOVE: bits 000011 */
2916 sreg
= b0s5_reg (insn
);
2917 dreg
= b5s5_reg (insn
);
2918 if (sreg
== MIPS_SP_REGNUM
&& dreg
== 30)
2924 else if ((sreg
& 0x1c) != 0x4)
2925 /* MOVE reg, $a0-$a3 */
2926 this_non_prologue_insn
= 1;
2929 case 0x11: /* POOL16C: bits 010001 */
2930 if (b6s4_op (insn
) == 0x5)
2931 /* SWM: bits 010001 0101 */
2933 offset
= ((b0s4_imm (insn
) << 2) ^ 0x20) - 0x20;
2934 reglist
= b4s2_regl (insn
);
2935 for (i
= 0; i
<= reglist
; i
++)
2936 set_reg_offset (gdbarch
, this_cache
, 16 + i
, sp
+ 4 * i
);
2937 set_reg_offset (gdbarch
, this_cache
,
2938 MIPS_RA_REGNUM
, sp
+ 4 * i
++);
2941 this_non_prologue_insn
= 1;
2944 case 0x13: /* POOL16D: bits 010011 */
2945 if ((insn
& 0x1) == 0x1)
2946 /* ADDIUSP: bits 010011 1 */
2947 sp_adj
= micromips_decode_imm9 (b1s9_imm (insn
));
2948 else if (b5s5_reg (insn
) == MIPS_SP_REGNUM
)
2949 /* ADDIUS5: bits 010011 0 */
2950 /* ADDIUS5 $sp, imm */
2951 sp_adj
= (b1s4_imm (insn
) ^ 8) - 8;
2953 this_non_prologue_insn
= 1;
2956 case 0x32: /* SWSP: bits 110010 */
2957 offset
= b0s5_imm (insn
) << 2;
2958 sreg
= b5s5_reg (insn
);
2959 set_reg_offset (gdbarch
, this_cache
, sreg
, sp
+ offset
);
2963 this_non_prologue_insn
= 1;
2969 frame_offset
-= sp_adj
;
2971 non_prologue_insns
+= this_non_prologue_insn
;
2972 /* Enough non-prologue insns seen or positive stack adjustment? */
2973 if (end_prologue_addr
== 0 && (non_prologue_insns
> 1 || sp_adj
> 0))
2975 end_prologue_addr
= prev_non_prologue_insn
? prev_pc
: cur_pc
;
2978 prev_non_prologue_insn
= this_non_prologue_insn
;
2982 if (this_cache
!= NULL
)
2985 (get_frame_register_signed (this_frame
,
2986 gdbarch_num_regs (gdbarch
) + frame_reg
)
2987 + frame_offset
- frame_adjust
);
2988 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
2989 be able to get rid of the assignment below, evetually. But it's
2990 still needed for now. */
2991 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2992 + mips_regnum (gdbarch
)->pc
]
2993 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
2996 /* If we didn't reach the end of the prologue when scanning the function
2997 instructions, then set end_prologue_addr to the address of the
2998 instruction immediately after the last one we scanned. Unless the
2999 last one looked like a non-prologue instruction (and we looked ahead),
3000 in which case use its address instead. */
3001 if (end_prologue_addr
== 0)
3002 end_prologue_addr
= prev_non_prologue_insn
? prev_pc
: cur_pc
;
3004 return end_prologue_addr
;
3007 /* Heuristic unwinder for procedures using microMIPS instructions.
3008 Procedures that use the 32-bit instruction set are handled by the
3009 mips_insn32 unwinder. Likewise MIPS16 and the mips_insn16 unwinder. */
3011 static struct mips_frame_cache
*
3012 mips_micro_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3014 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3015 struct mips_frame_cache
*cache
;
3017 if ((*this_cache
) != NULL
)
3018 return (*this_cache
);
3020 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
3021 (*this_cache
) = cache
;
3022 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3024 /* Analyze the function prologue. */
3026 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3027 CORE_ADDR start_addr
;
3029 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3030 if (start_addr
== 0)
3031 start_addr
= heuristic_proc_start (get_frame_arch (this_frame
), pc
);
3032 /* We can't analyze the prologue if we couldn't find the begining
3034 if (start_addr
== 0)
3037 micromips_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
, *this_cache
);
3040 /* gdbarch_sp_regnum contains the value and not the address. */
3041 trad_frame_set_value (cache
->saved_regs
,
3042 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
3045 return (*this_cache
);
3049 mips_micro_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3050 struct frame_id
*this_id
)
3052 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3054 /* This marks the outermost frame. */
3055 if (info
->base
== 0)
3057 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3060 static struct value
*
3061 mips_micro_frame_prev_register (struct frame_info
*this_frame
,
3062 void **this_cache
, int regnum
)
3064 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3066 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3070 mips_micro_frame_sniffer (const struct frame_unwind
*self
,
3071 struct frame_info
*this_frame
, void **this_cache
)
3073 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3074 CORE_ADDR pc
= get_frame_pc (this_frame
);
3076 if (mips_pc_is_micromips (gdbarch
, pc
))
3081 static const struct frame_unwind mips_micro_frame_unwind
=
3084 default_frame_unwind_stop_reason
,
3085 mips_micro_frame_this_id
,
3086 mips_micro_frame_prev_register
,
3088 mips_micro_frame_sniffer
3092 mips_micro_frame_base_address (struct frame_info
*this_frame
,
3095 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3100 static const struct frame_base mips_micro_frame_base
=
3102 &mips_micro_frame_unwind
,
3103 mips_micro_frame_base_address
,
3104 mips_micro_frame_base_address
,
3105 mips_micro_frame_base_address
3108 static const struct frame_base
*
3109 mips_micro_frame_base_sniffer (struct frame_info
*this_frame
)
3111 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3112 CORE_ADDR pc
= get_frame_pc (this_frame
);
3114 if (mips_pc_is_micromips (gdbarch
, pc
))
3115 return &mips_micro_frame_base
;
3120 /* Mark all the registers as unset in the saved_regs array
3121 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
3124 reset_saved_regs (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
)
3126 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
3130 const int num_regs
= gdbarch_num_regs (gdbarch
);
3133 for (i
= 0; i
< num_regs
; i
++)
3135 this_cache
->saved_regs
[i
].addr
= -1;
3140 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
3141 the associated FRAME_CACHE if not null.
3142 Return the address of the first instruction past the prologue. */
3145 mips32_scan_prologue (struct gdbarch
*gdbarch
,
3146 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
3147 struct frame_info
*this_frame
,
3148 struct mips_frame_cache
*this_cache
)
3151 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for
3155 int frame_reg
= MIPS_SP_REGNUM
;
3157 CORE_ADDR end_prologue_addr
= 0;
3158 int seen_sp_adjust
= 0;
3159 int load_immediate_bytes
= 0;
3160 int in_delay_slot
= 0;
3161 int regsize_is_64_bits
= (mips_abi_regsize (gdbarch
) == 8);
3163 /* Can be called when there's no process, and hence when there's no
3165 if (this_frame
!= NULL
)
3166 sp
= get_frame_register_signed (this_frame
,
3167 gdbarch_num_regs (gdbarch
)
3172 if (limit_pc
> start_pc
+ 200)
3173 limit_pc
= start_pc
+ 200;
3178 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
3180 unsigned long inst
, high_word
, low_word
;
3183 /* Fetch the instruction. */
3184 inst
= (unsigned long) mips_fetch_instruction (gdbarch
, ISA_MIPS
,
3187 /* Save some code by pre-extracting some useful fields. */
3188 high_word
= (inst
>> 16) & 0xffff;
3189 low_word
= inst
& 0xffff;
3190 reg
= high_word
& 0x1f;
3192 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
3193 || high_word
== 0x23bd /* addi $sp,$sp,-i */
3194 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
3196 if (low_word
& 0x8000) /* Negative stack adjustment? */
3197 frame_offset
+= 0x10000 - low_word
;
3199 /* Exit loop if a positive stack adjustment is found, which
3200 usually means that the stack cleanup code in the function
3201 epilogue is reached. */
3205 else if (((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
3206 && !regsize_is_64_bits
)
3208 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ low_word
);
3210 else if (((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
3211 && regsize_is_64_bits
)
3213 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
3214 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ low_word
);
3216 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
3218 /* Old gcc frame, r30 is virtual frame pointer. */
3219 if ((long) low_word
!= frame_offset
)
3220 frame_addr
= sp
+ low_word
;
3221 else if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
3223 unsigned alloca_adjust
;
3226 frame_addr
= get_frame_register_signed
3227 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
3229 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
3230 if (alloca_adjust
> 0)
3232 /* FP > SP + frame_size. This may be because of
3233 an alloca or somethings similar. Fix sp to
3234 "pre-alloca" value, and try again. */
3235 sp
+= alloca_adjust
;
3236 /* Need to reset the status of all registers. Otherwise,
3237 we will hit a guard that prevents the new address
3238 for each register to be recomputed during the second
3240 reset_saved_regs (gdbarch
, this_cache
);
3245 /* move $30,$sp. With different versions of gas this will be either
3246 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
3247 Accept any one of these. */
3248 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
3250 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
3251 if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
3253 unsigned alloca_adjust
;
3256 frame_addr
= get_frame_register_signed
3257 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
3259 alloca_adjust
= (unsigned) (frame_addr
- sp
);
3260 if (alloca_adjust
> 0)
3262 /* FP > SP + frame_size. This may be because of
3263 an alloca or somethings similar. Fix sp to
3264 "pre-alloca" value, and try again. */
3266 /* Need to reset the status of all registers. Otherwise,
3267 we will hit a guard that prevents the new address
3268 for each register to be recomputed during the second
3270 reset_saved_regs (gdbarch
, this_cache
);
3275 else if ((high_word
& 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
3276 && !regsize_is_64_bits
)
3278 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ low_word
);
3280 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
3281 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
3282 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
3283 || high_word
== 0x3c1c /* lui $gp,n */
3284 || high_word
== 0x279c /* addiu $gp,$gp,n */
3285 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
3286 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
3289 /* These instructions are part of the prologue, but we don't
3290 need to do anything special to handle them. */
3292 /* The instructions below load $at or $t0 with an immediate
3293 value in preparation for a stack adjustment via
3294 subu $sp,$sp,[$at,$t0]. These instructions could also
3295 initialize a local variable, so we accept them only before
3296 a stack adjustment instruction was seen. */
3297 else if (!seen_sp_adjust
3298 && (high_word
== 0x3c01 /* lui $at,n */
3299 || high_word
== 0x3c08 /* lui $t0,n */
3300 || high_word
== 0x3421 /* ori $at,$at,n */
3301 || high_word
== 0x3508 /* ori $t0,$t0,n */
3302 || high_word
== 0x3401 /* ori $at,$zero,n */
3303 || high_word
== 0x3408 /* ori $t0,$zero,n */
3306 if (end_prologue_addr
== 0)
3307 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
3311 /* This instruction is not an instruction typically found
3312 in a prologue, so we must have reached the end of the
3314 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
3315 loop now? Why would we need to continue scanning the function
3317 if (end_prologue_addr
== 0)
3318 end_prologue_addr
= cur_pc
;
3320 /* Check for branches and jumps. For now, only jump to
3321 register are caught (i.e. returns). */
3322 if ((itype_op (inst
) & 0x07) == 0 && rtype_funct (inst
) == 8)
3326 /* If the previous instruction was a jump, we must have reached
3327 the end of the prologue by now. Stop scanning so that we do
3328 not go past the function return. */
3333 if (this_cache
!= NULL
)
3336 (get_frame_register_signed (this_frame
,
3337 gdbarch_num_regs (gdbarch
) + frame_reg
)
3339 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
3340 this assignment below, eventually. But it's still needed
3342 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3343 + mips_regnum (gdbarch
)->pc
]
3344 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3348 /* If we didn't reach the end of the prologue when scanning the function
3349 instructions, then set end_prologue_addr to the address of the
3350 instruction immediately after the last one we scanned. */
3351 /* brobecker/2004-10-10: I don't think this would ever happen, but
3352 we may as well be careful and do our best if we have a null
3353 end_prologue_addr. */
3354 if (end_prologue_addr
== 0)
3355 end_prologue_addr
= cur_pc
;
3357 /* In a frameless function, we might have incorrectly
3358 skipped some load immediate instructions. Undo the skipping
3359 if the load immediate was not followed by a stack adjustment. */
3360 if (load_immediate_bytes
&& !seen_sp_adjust
)
3361 end_prologue_addr
-= load_immediate_bytes
;
3363 return end_prologue_addr
;
3366 /* Heuristic unwinder for procedures using 32-bit instructions (covers
3367 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
3368 instructions (a.k.a. MIPS16) are handled by the mips_insn16
3369 unwinder. Likewise microMIPS and the mips_micro unwinder. */
3371 static struct mips_frame_cache
*
3372 mips_insn32_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3374 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3375 struct mips_frame_cache
*cache
;
3377 if ((*this_cache
) != NULL
)
3378 return (*this_cache
);
3380 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
3381 (*this_cache
) = cache
;
3382 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3384 /* Analyze the function prologue. */
3386 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3387 CORE_ADDR start_addr
;
3389 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3390 if (start_addr
== 0)
3391 start_addr
= heuristic_proc_start (gdbarch
, pc
);
3392 /* We can't analyze the prologue if we couldn't find the begining
3394 if (start_addr
== 0)
3397 mips32_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
, *this_cache
);
3400 /* gdbarch_sp_regnum contains the value and not the address. */
3401 trad_frame_set_value (cache
->saved_regs
,
3402 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
3405 return (*this_cache
);
3409 mips_insn32_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3410 struct frame_id
*this_id
)
3412 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3414 /* This marks the outermost frame. */
3415 if (info
->base
== 0)
3417 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3420 static struct value
*
3421 mips_insn32_frame_prev_register (struct frame_info
*this_frame
,
3422 void **this_cache
, int regnum
)
3424 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3426 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3430 mips_insn32_frame_sniffer (const struct frame_unwind
*self
,
3431 struct frame_info
*this_frame
, void **this_cache
)
3433 CORE_ADDR pc
= get_frame_pc (this_frame
);
3434 if (mips_pc_is_mips (pc
))
3439 static const struct frame_unwind mips_insn32_frame_unwind
=
3442 default_frame_unwind_stop_reason
,
3443 mips_insn32_frame_this_id
,
3444 mips_insn32_frame_prev_register
,
3446 mips_insn32_frame_sniffer
3450 mips_insn32_frame_base_address (struct frame_info
*this_frame
,
3453 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3458 static const struct frame_base mips_insn32_frame_base
=
3460 &mips_insn32_frame_unwind
,
3461 mips_insn32_frame_base_address
,
3462 mips_insn32_frame_base_address
,
3463 mips_insn32_frame_base_address
3466 static const struct frame_base
*
3467 mips_insn32_frame_base_sniffer (struct frame_info
*this_frame
)
3469 CORE_ADDR pc
= get_frame_pc (this_frame
);
3470 if (mips_pc_is_mips (pc
))
3471 return &mips_insn32_frame_base
;
3476 static struct trad_frame_cache
*
3477 mips_stub_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3480 CORE_ADDR start_addr
;
3481 CORE_ADDR stack_addr
;
3482 struct trad_frame_cache
*this_trad_cache
;
3483 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3484 int num_regs
= gdbarch_num_regs (gdbarch
);
3486 if ((*this_cache
) != NULL
)
3487 return (*this_cache
);
3488 this_trad_cache
= trad_frame_cache_zalloc (this_frame
);
3489 (*this_cache
) = this_trad_cache
;
3491 /* The return address is in the link register. */
3492 trad_frame_set_reg_realreg (this_trad_cache
,
3493 gdbarch_pc_regnum (gdbarch
),
3494 num_regs
+ MIPS_RA_REGNUM
);
3496 /* Frame ID, since it's a frameless / stackless function, no stack
3497 space is allocated and SP on entry is the current SP. */
3498 pc
= get_frame_pc (this_frame
);
3499 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3500 stack_addr
= get_frame_register_signed (this_frame
,
3501 num_regs
+ MIPS_SP_REGNUM
);
3502 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
3504 /* Assume that the frame's base is the same as the
3506 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
3508 return this_trad_cache
;
3512 mips_stub_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3513 struct frame_id
*this_id
)
3515 struct trad_frame_cache
*this_trad_cache
3516 = mips_stub_frame_cache (this_frame
, this_cache
);
3517 trad_frame_get_id (this_trad_cache
, this_id
);
3520 static struct value
*
3521 mips_stub_frame_prev_register (struct frame_info
*this_frame
,
3522 void **this_cache
, int regnum
)
3524 struct trad_frame_cache
*this_trad_cache
3525 = mips_stub_frame_cache (this_frame
, this_cache
);
3526 return trad_frame_get_register (this_trad_cache
, this_frame
, regnum
);
3530 mips_stub_frame_sniffer (const struct frame_unwind
*self
,
3531 struct frame_info
*this_frame
, void **this_cache
)
3534 struct obj_section
*s
;
3535 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3536 struct minimal_symbol
*msym
;
3538 /* Use the stub unwinder for unreadable code. */
3539 if (target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
3542 if (in_plt_section (pc
, NULL
))
3545 /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */
3546 s
= find_pc_section (pc
);
3549 && strcmp (bfd_get_section_name (s
->objfile
->obfd
, s
->the_bfd_section
),
3550 ".MIPS.stubs") == 0)
3553 /* Calling a PIC function from a non-PIC function passes through a
3554 stub. The stub for foo is named ".pic.foo". */
3555 msym
= lookup_minimal_symbol_by_pc (pc
);
3557 && SYMBOL_LINKAGE_NAME (msym
) != NULL
3558 && strncmp (SYMBOL_LINKAGE_NAME (msym
), ".pic.", 5) == 0)
3564 static const struct frame_unwind mips_stub_frame_unwind
=
3567 default_frame_unwind_stop_reason
,
3568 mips_stub_frame_this_id
,
3569 mips_stub_frame_prev_register
,
3571 mips_stub_frame_sniffer
3575 mips_stub_frame_base_address (struct frame_info
*this_frame
,
3578 struct trad_frame_cache
*this_trad_cache
3579 = mips_stub_frame_cache (this_frame
, this_cache
);
3580 return trad_frame_get_this_base (this_trad_cache
);
3583 static const struct frame_base mips_stub_frame_base
=
3585 &mips_stub_frame_unwind
,
3586 mips_stub_frame_base_address
,
3587 mips_stub_frame_base_address
,
3588 mips_stub_frame_base_address
3591 static const struct frame_base
*
3592 mips_stub_frame_base_sniffer (struct frame_info
*this_frame
)
3594 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind
, this_frame
, NULL
))
3595 return &mips_stub_frame_base
;
3600 /* mips_addr_bits_remove - remove useless address bits */
3603 mips_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
3605 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3607 if (is_compact_addr (addr
))
3608 addr
= unmake_compact_addr (addr
);
3610 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
3611 /* This hack is a work-around for existing boards using PMON, the
3612 simulator, and any other 64-bit targets that doesn't have true
3613 64-bit addressing. On these targets, the upper 32 bits of
3614 addresses are ignored by the hardware. Thus, the PC or SP are
3615 likely to have been sign extended to all 1s by instruction
3616 sequences that load 32-bit addresses. For example, a typical
3617 piece of code that loads an address is this:
3619 lui $r2, <upper 16 bits>
3620 ori $r2, <lower 16 bits>
3622 But the lui sign-extends the value such that the upper 32 bits
3623 may be all 1s. The workaround is simply to mask off these
3624 bits. In the future, gcc may be changed to support true 64-bit
3625 addressing, and this masking will have to be disabled. */
3626 return addr
&= 0xffffffffUL
;
3632 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
3633 instruction and ending with a SC/SCD instruction. If such a sequence
3634 is found, attempt to step through it. A breakpoint is placed at the end of
3637 /* Instructions used during single-stepping of atomic sequences, standard
3639 #define LL_OPCODE 0x30
3640 #define LLD_OPCODE 0x34
3641 #define SC_OPCODE 0x38
3642 #define SCD_OPCODE 0x3c
3645 mips_deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
3646 struct address_space
*aspace
, CORE_ADDR pc
)
3648 CORE_ADDR breaks
[2] = {-1, -1};
3650 CORE_ADDR branch_bp
; /* Breakpoint at branch instruction's destination. */
3654 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
3655 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
3657 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, loc
, NULL
);
3658 /* Assume all atomic sequences start with a ll/lld instruction. */
3659 if (itype_op (insn
) != LL_OPCODE
&& itype_op (insn
) != LLD_OPCODE
)
3662 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
3664 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
3667 loc
+= MIPS_INSN32_SIZE
;
3668 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, loc
, NULL
);
3670 /* Assume that there is at most one branch in the atomic
3671 sequence. If a branch is found, put a breakpoint in its
3672 destination address. */
3673 switch (itype_op (insn
))
3675 case 0: /* SPECIAL */
3676 if (rtype_funct (insn
) >> 1 == 4) /* JR, JALR */
3677 return 0; /* fallback to the standard single-step code. */
3679 case 1: /* REGIMM */
3680 is_branch
= ((itype_rt (insn
) & 0xc) == 0 /* B{LT,GE}Z* */
3681 || ((itype_rt (insn
) & 0x1e) == 0
3682 && itype_rs (insn
) == 0)); /* BPOSGE* */
3686 return 0; /* fallback to the standard single-step code. */
3693 case 22: /* BLEZL */
3694 case 23: /* BGTTL */
3698 is_branch
= ((itype_rs (insn
) == 9 || itype_rs (insn
) == 10)
3699 && (itype_rt (insn
) & 0x2) == 0);
3700 if (is_branch
) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */
3705 is_branch
= (itype_rs (insn
) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
3710 branch_bp
= loc
+ mips32_relative_offset (insn
) + 4;
3711 if (last_breakpoint
>= 1)
3712 return 0; /* More than one branch found, fallback to the
3713 standard single-step code. */
3714 breaks
[1] = branch_bp
;
3718 if (itype_op (insn
) == SC_OPCODE
|| itype_op (insn
) == SCD_OPCODE
)
3722 /* Assume that the atomic sequence ends with a sc/scd instruction. */
3723 if (itype_op (insn
) != SC_OPCODE
&& itype_op (insn
) != SCD_OPCODE
)
3726 loc
+= MIPS_INSN32_SIZE
;
3728 /* Insert a breakpoint right after the end of the atomic sequence. */
3731 /* Check for duplicated breakpoints. Check also for a breakpoint
3732 placed (branch instruction's destination) in the atomic sequence. */
3733 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
3734 last_breakpoint
= 0;
3736 /* Effectively inserts the breakpoints. */
3737 for (index
= 0; index
<= last_breakpoint
; index
++)
3738 insert_single_step_breakpoint (gdbarch
, aspace
, breaks
[index
]);
3744 micromips_deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
3745 struct address_space
*aspace
,
3748 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
3749 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
3750 CORE_ADDR breaks
[2] = {-1, -1};
3751 CORE_ADDR branch_bp
; /* Breakpoint at branch instruction's destination. */
3758 /* Assume all atomic sequences start with a ll/lld instruction. */
3759 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
3760 if (micromips_op (insn
) != 0x18) /* POOL32C: bits 011000 */
3762 loc
+= MIPS_INSN16_SIZE
;
3764 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
3765 if ((b12s4_op (insn
) & 0xb) != 0x3) /* LL, LLD: bits 011000 0x11 */
3767 loc
+= MIPS_INSN16_SIZE
;
3769 /* Assume all atomic sequences end with an sc/scd instruction. Assume
3770 that no atomic sequence is longer than "atomic_sequence_length"
3772 for (insn_count
= 0;
3773 !sc_found
&& insn_count
< atomic_sequence_length
;
3778 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
3779 loc
+= MIPS_INSN16_SIZE
;
3781 /* Assume that there is at most one conditional branch in the
3782 atomic sequence. If a branch is found, put a breakpoint in
3783 its destination address. */
3784 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
3786 /* 48-bit instructions. */
3787 case 3 * MIPS_INSN16_SIZE
: /* POOL48A: bits 011111 */
3788 loc
+= 2 * MIPS_INSN16_SIZE
;
3791 /* 32-bit instructions. */
3792 case 2 * MIPS_INSN16_SIZE
:
3793 switch (micromips_op (insn
))
3795 case 0x10: /* POOL32I: bits 010000 */
3796 if ((b5s5_op (insn
) & 0x18) != 0x0
3797 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
3798 /* BLEZ, BNEZC, BGTZ, BEQZC: 010000 001xx */
3799 && (b5s5_op (insn
) & 0x1d) != 0x11
3800 /* BLTZALS, BGEZALS: bits 010000 100x1 */
3801 && ((b5s5_op (insn
) & 0x1e) != 0x14
3802 || (insn
& 0x3) != 0x0)
3803 /* BC2F, BC2T: bits 010000 1010x xxx00 */
3804 && (b5s5_op (insn
) & 0x1e) != 0x1a
3805 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
3806 && ((b5s5_op (insn
) & 0x1e) != 0x1c
3807 || (insn
& 0x3) != 0x0)
3808 /* BC1F, BC1T: bits 010000 1110x xxx00 */
3809 && ((b5s5_op (insn
) & 0x1c) != 0x1c
3810 || (insn
& 0x3) != 0x1))
3811 /* BC1ANY*: bits 010000 111xx xxx01 */
3815 case 0x25: /* BEQ: bits 100101 */
3816 case 0x2d: /* BNE: bits 101101 */
3818 insn
|= mips_fetch_instruction (gdbarch
,
3819 ISA_MICROMIPS
, loc
, NULL
);
3820 branch_bp
= (loc
+ MIPS_INSN16_SIZE
3821 + micromips_relative_offset16 (insn
));
3825 case 0x00: /* POOL32A: bits 000000 */
3827 insn
|= mips_fetch_instruction (gdbarch
,
3828 ISA_MICROMIPS
, loc
, NULL
);
3829 if (b0s6_op (insn
) != 0x3c
3830 /* POOL32Axf: bits 000000 ... 111100 */
3831 || (b6s10_ext (insn
) & 0x2bf) != 0x3c)
3832 /* JALR, JALR.HB: 000000 000x111100 111100 */
3833 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
3837 case 0x1d: /* JALS: bits 011101 */
3838 case 0x35: /* J: bits 110101 */
3839 case 0x3d: /* JAL: bits 111101 */
3840 case 0x3c: /* JALX: bits 111100 */
3841 return 0; /* Fall back to the standard single-step code. */
3843 case 0x18: /* POOL32C: bits 011000 */
3844 if ((b12s4_op (insn
) & 0xb) == 0xb)
3845 /* SC, SCD: bits 011000 1x11 */
3849 loc
+= MIPS_INSN16_SIZE
;
3852 /* 16-bit instructions. */
3853 case MIPS_INSN16_SIZE
:
3854 switch (micromips_op (insn
))
3856 case 0x23: /* BEQZ16: bits 100011 */
3857 case 0x2b: /* BNEZ16: bits 101011 */
3858 branch_bp
= loc
+ micromips_relative_offset7 (insn
);
3862 case 0x11: /* POOL16C: bits 010001 */
3863 if ((b5s5_op (insn
) & 0x1c) != 0xc
3864 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
3865 && b5s5_op (insn
) != 0x18)
3866 /* JRADDIUSP: bits 010001 11000 */
3868 return 0; /* Fall back to the standard single-step code. */
3870 case 0x33: /* B16: bits 110011 */
3871 return 0; /* Fall back to the standard single-step code. */
3877 if (last_breakpoint
>= 1)
3878 return 0; /* More than one branch found, fallback to the
3879 standard single-step code. */
3880 breaks
[1] = branch_bp
;
3887 /* Insert a breakpoint right after the end of the atomic sequence. */
3890 /* Check for duplicated breakpoints. Check also for a breakpoint
3891 placed (branch instruction's destination) in the atomic sequence */
3892 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
3893 last_breakpoint
= 0;
3895 /* Effectively inserts the breakpoints. */
3896 for (index
= 0; index
<= last_breakpoint
; index
++)
3897 insert_single_step_breakpoint (gdbarch
, aspace
, breaks
[index
]);
3903 deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
3904 struct address_space
*aspace
, CORE_ADDR pc
)
3906 if (mips_pc_is_mips (pc
))
3907 return mips_deal_with_atomic_sequence (gdbarch
, aspace
, pc
);
3908 else if (mips_pc_is_micromips (gdbarch
, pc
))
3909 return micromips_deal_with_atomic_sequence (gdbarch
, aspace
, pc
);
3914 /* mips_software_single_step() is called just before we want to resume
3915 the inferior, if we want to single-step it but there is no hardware
3916 or kernel single-step support (MIPS on GNU/Linux for example). We find
3917 the target of the coming instruction and breakpoint it. */
3920 mips_software_single_step (struct frame_info
*frame
)
3922 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3923 struct address_space
*aspace
= get_frame_address_space (frame
);
3924 CORE_ADDR pc
, next_pc
;
3926 pc
= get_frame_pc (frame
);
3927 if (deal_with_atomic_sequence (gdbarch
, aspace
, pc
))
3930 next_pc
= mips_next_pc (frame
, pc
);
3932 insert_single_step_breakpoint (gdbarch
, aspace
, next_pc
);
3936 /* Test whether the PC points to the return instruction at the
3937 end of a function. */
3940 mips_about_to_return (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3945 /* This used to check for MIPS16, but this piece of code is never
3946 called for MIPS16 functions. And likewise microMIPS ones. */
3947 gdb_assert (mips_pc_is_mips (pc
));
3949 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
3951 return (insn
& ~hint
) == 0x3e00008; /* jr(.hb) $ra */
3955 /* This fencepost looks highly suspicious to me. Removing it also
3956 seems suspicious as it could affect remote debugging across serial
3960 heuristic_proc_start (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3966 struct inferior
*inf
;
3968 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
3970 fence
= start_pc
- heuristic_fence_post
;
3974 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
3975 fence
= VM_MIN_ADDRESS
;
3977 instlen
= mips_pc_is_mips (pc
) ? MIPS_INSN32_SIZE
: MIPS_INSN16_SIZE
;
3979 inf
= current_inferior ();
3981 /* Search back for previous return. */
3982 for (start_pc
-= instlen
;; start_pc
-= instlen
)
3983 if (start_pc
< fence
)
3985 /* It's not clear to me why we reach this point when
3986 stop_soon, but with this test, at least we
3987 don't print out warnings for every child forked (eg, on
3988 decstation). 22apr93 rich@cygnus.com. */
3989 if (inf
->control
.stop_soon
== NO_STOP_QUIETLY
)
3991 static int blurb_printed
= 0;
3993 warning (_("GDB can't find the start of the function at %s."),
3994 paddress (gdbarch
, pc
));
3998 /* This actually happens frequently in embedded
3999 development, when you first connect to a board
4000 and your stack pointer and pc are nowhere in
4001 particular. This message needs to give people
4002 in that situation enough information to
4003 determine that it's no big deal. */
4004 printf_filtered ("\n\
4005 GDB is unable to find the start of the function at %s\n\
4006 and thus can't determine the size of that function's stack frame.\n\
4007 This means that GDB may be unable to access that stack frame, or\n\
4008 the frames below it.\n\
4009 This problem is most likely caused by an invalid program counter or\n\
4011 However, if you think GDB should simply search farther back\n\
4012 from %s for code which looks like the beginning of a\n\
4013 function, you can increase the range of the search using the `set\n\
4014 heuristic-fence-post' command.\n",
4015 paddress (gdbarch
, pc
), paddress (gdbarch
, pc
));
4022 else if (mips_pc_is_mips16 (gdbarch
, start_pc
))
4024 unsigned short inst
;
4026 /* On MIPS16, any one of the following is likely to be the
4027 start of a function:
4033 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */
4034 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, start_pc
, NULL
);
4035 if ((inst
& 0xff80) == 0x6480) /* save */
4037 if (start_pc
- instlen
>= fence
)
4039 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
,
4040 start_pc
- instlen
, NULL
);
4041 if ((inst
& 0xf800) == 0xf000) /* extend */
4042 start_pc
-= instlen
;
4046 else if (((inst
& 0xf81f) == 0xe809
4047 && (inst
& 0x700) != 0x700) /* entry */
4048 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
4049 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
4050 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
4052 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
4053 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
4058 else if (mips_pc_is_micromips (gdbarch
, start_pc
))
4066 /* On microMIPS, any one of the following is likely to be the
4067 start of a function:
4071 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
4072 switch (micromips_op (insn
))
4074 case 0xc: /* ADDIU: bits 001100 */
4075 case 0x17: /* DADDIU: bits 010111 */
4076 sreg
= b0s5_reg (insn
);
4077 dreg
= b5s5_reg (insn
);
4079 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
,
4080 pc
+ MIPS_INSN16_SIZE
, NULL
);
4081 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
4082 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
4083 /* (D)ADDIU $sp, imm */
4088 case 0x10: /* POOL32I: bits 010000 */
4089 if (b5s5_op (insn
) == 0xd
4090 /* LUI: bits 010000 001101 */
4091 && b0s5_reg (insn
>> 16) == 28)
4096 case 0x13: /* POOL16D: bits 010011 */
4097 if ((insn
& 0x1) == 0x1)
4098 /* ADDIUSP: bits 010011 1 */
4100 offset
= micromips_decode_imm9 (b1s9_imm (insn
));
4106 /* ADDIUS5: bits 010011 0 */
4108 dreg
= b5s5_reg (insn
);
4109 offset
= (b1s4_imm (insn
) ^ 8) - 8;
4110 if (dreg
== MIPS_SP_REGNUM
&& offset
< 0)
4111 /* ADDIUS5 $sp, -imm */
4119 else if (mips_about_to_return (gdbarch
, start_pc
))
4121 /* Skip return and its delay slot. */
4122 start_pc
+= 2 * MIPS_INSN32_SIZE
;
4129 struct mips_objfile_private
4135 /* According to the current ABI, should the type be passed in a
4136 floating-point register (assuming that there is space)? When there
4137 is no FPU, FP are not even considered as possible candidates for
4138 FP registers and, consequently this returns false - forces FP
4139 arguments into integer registers. */
4142 fp_register_arg_p (struct gdbarch
*gdbarch
, enum type_code typecode
,
4143 struct type
*arg_type
)
4145 return ((typecode
== TYPE_CODE_FLT
4146 || (MIPS_EABI (gdbarch
)
4147 && (typecode
== TYPE_CODE_STRUCT
4148 || typecode
== TYPE_CODE_UNION
)
4149 && TYPE_NFIELDS (arg_type
) == 1
4150 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type
, 0)))
4152 && MIPS_FPU_TYPE(gdbarch
) != MIPS_FPU_NONE
);
4155 /* On o32, argument passing in GPRs depends on the alignment of the type being
4156 passed. Return 1 if this type must be aligned to a doubleword boundary. */
4159 mips_type_needs_double_align (struct type
*type
)
4161 enum type_code typecode
= TYPE_CODE (type
);
4163 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
4165 else if (typecode
== TYPE_CODE_STRUCT
)
4167 if (TYPE_NFIELDS (type
) < 1)
4169 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
4171 else if (typecode
== TYPE_CODE_UNION
)
4175 n
= TYPE_NFIELDS (type
);
4176 for (i
= 0; i
< n
; i
++)
4177 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
4184 /* Adjust the address downward (direction of stack growth) so that it
4185 is correctly aligned for a new stack frame. */
4187 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
4189 return align_down (addr
, 16);
4192 /* Implement the "push_dummy_code" gdbarch method. */
4195 mips_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
4196 CORE_ADDR funaddr
, struct value
**args
,
4197 int nargs
, struct type
*value_type
,
4198 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
4199 struct regcache
*regcache
)
4201 static gdb_byte nop_insn
[] = { 0, 0, 0, 0 };
4205 /* Reserve enough room on the stack for our breakpoint instruction. */
4206 bp_slot
= sp
- sizeof (nop_insn
);
4208 /* Return to microMIPS mode if calling microMIPS code to avoid
4209 triggering an address error exception on processors that only
4210 support microMIPS execution. */
4211 *bp_addr
= (mips_pc_is_micromips (gdbarch
, funaddr
)
4212 ? make_compact_addr (bp_slot
) : bp_slot
);
4214 /* The breakpoint layer automatically adjusts the address of
4215 breakpoints inserted in a branch delay slot. With enough
4216 bad luck, the 4 bytes located just before our breakpoint
4217 instruction could look like a branch instruction, and thus
4218 trigger the adjustement, and break the function call entirely.
4219 So, we reserve those 4 bytes and write a nop instruction
4220 to prevent that from happening. */
4221 nop_addr
= bp_slot
- sizeof (nop_insn
);
4222 write_memory (nop_addr
, nop_insn
, sizeof (nop_insn
));
4223 sp
= mips_frame_align (gdbarch
, nop_addr
);
4225 /* Inferior resumes at the function entry point. */
4232 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4233 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4234 int nargs
, struct value
**args
, CORE_ADDR sp
,
4235 int struct_return
, CORE_ADDR struct_addr
)
4241 int stack_offset
= 0;
4242 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4243 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4244 int regsize
= mips_abi_regsize (gdbarch
);
4246 /* For shared libraries, "t9" needs to point at the function
4248 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4250 /* Set the return address register to point to the entry point of
4251 the program, where a breakpoint lies in wait. */
4252 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4254 /* First ensure that the stack and structure return address (if any)
4255 are properly aligned. The stack has to be at least 64-bit
4256 aligned even on 32-bit machines, because doubles must be 64-bit
4257 aligned. For n32 and n64, stack frames need to be 128-bit
4258 aligned, so we round to this widest known alignment. */
4260 sp
= align_down (sp
, 16);
4261 struct_addr
= align_down (struct_addr
, 16);
4263 /* Now make space on the stack for the args. We allocate more
4264 than necessary for EABI, because the first few arguments are
4265 passed in registers, but that's OK. */
4266 for (argnum
= 0; argnum
< nargs
; argnum
++)
4267 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), regsize
);
4268 sp
-= align_up (len
, 16);
4271 fprintf_unfiltered (gdb_stdlog
,
4272 "mips_eabi_push_dummy_call: sp=%s allocated %ld\n",
4273 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
4275 /* Initialize the integer and float register pointers. */
4276 argreg
= MIPS_A0_REGNUM
;
4277 float_argreg
= mips_fpa0_regnum (gdbarch
);
4279 /* The struct_return pointer occupies the first parameter-passing reg. */
4283 fprintf_unfiltered (gdb_stdlog
,
4284 "mips_eabi_push_dummy_call: "
4285 "struct_return reg=%d %s\n",
4286 argreg
, paddress (gdbarch
, struct_addr
));
4287 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4290 /* Now load as many as possible of the first arguments into
4291 registers, and push the rest onto the stack. Loop thru args
4292 from first to last. */
4293 for (argnum
= 0; argnum
< nargs
; argnum
++)
4295 const gdb_byte
*val
;
4296 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
4297 struct value
*arg
= args
[argnum
];
4298 struct type
*arg_type
= check_typedef (value_type (arg
));
4299 int len
= TYPE_LENGTH (arg_type
);
4300 enum type_code typecode
= TYPE_CODE (arg_type
);
4303 fprintf_unfiltered (gdb_stdlog
,
4304 "mips_eabi_push_dummy_call: %d len=%d type=%d",
4305 argnum
+ 1, len
, (int) typecode
);
4307 /* Function pointer arguments to mips16 code need to be made into
4309 if (typecode
== TYPE_CODE_PTR
4310 && TYPE_CODE (TYPE_TARGET_TYPE (arg_type
)) == TYPE_CODE_FUNC
)
4312 CORE_ADDR addr
= extract_signed_integer (value_contents (arg
),
4314 if (mips_pc_is_mips (addr
))
4315 val
= value_contents (arg
);
4318 store_signed_integer (valbuf
, len
, byte_order
,
4319 make_compact_addr (addr
));
4323 /* The EABI passes structures that do not fit in a register by
4325 else if (len
> regsize
4326 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
4328 store_unsigned_integer (valbuf
, regsize
, byte_order
,
4329 value_address (arg
));
4330 typecode
= TYPE_CODE_PTR
;
4334 fprintf_unfiltered (gdb_stdlog
, " push");
4337 val
= value_contents (arg
);
4339 /* 32-bit ABIs always start floating point arguments in an
4340 even-numbered floating point register. Round the FP register
4341 up before the check to see if there are any FP registers
4342 left. Non MIPS_EABI targets also pass the FP in the integer
4343 registers so also round up normal registers. */
4344 if (regsize
< 8 && fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4346 if ((float_argreg
& 1))
4350 /* Floating point arguments passed in registers have to be
4351 treated specially. On 32-bit architectures, doubles
4352 are passed in register pairs; the even register gets
4353 the low word, and the odd register gets the high word.
4354 On non-EABI processors, the first two floating point arguments are
4355 also copied to general registers, because MIPS16 functions
4356 don't use float registers for arguments. This duplication of
4357 arguments in general registers can't hurt non-MIPS16 functions
4358 because those registers are normally skipped. */
4359 /* MIPS_EABI squeezes a struct that contains a single floating
4360 point value into an FP register instead of pushing it onto the
4362 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4363 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
4365 /* EABI32 will pass doubles in consecutive registers, even on
4366 64-bit cores. At one time, we used to check the size of
4367 `float_argreg' to determine whether or not to pass doubles
4368 in consecutive registers, but this is not sufficient for
4369 making the ABI determination. */
4370 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
4372 int low_offset
= gdbarch_byte_order (gdbarch
)
4373 == BFD_ENDIAN_BIG
? 4 : 0;
4376 /* Write the low word of the double to the even register(s). */
4377 regval
= extract_signed_integer (val
+ low_offset
,
4380 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4381 float_argreg
, phex (regval
, 4));
4382 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4384 /* Write the high word of the double to the odd register(s). */
4385 regval
= extract_signed_integer (val
+ 4 - low_offset
,
4388 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4389 float_argreg
, phex (regval
, 4));
4390 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4394 /* This is a floating point value that fits entirely
4395 in a single register. */
4396 /* On 32 bit ABI's the float_argreg is further adjusted
4397 above to ensure that it is even register aligned. */
4398 LONGEST regval
= extract_signed_integer (val
, len
, byte_order
);
4400 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4401 float_argreg
, phex (regval
, len
));
4402 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4407 /* Copy the argument to general registers or the stack in
4408 register-sized pieces. Large arguments are split between
4409 registers and stack. */
4410 /* Note: structs whose size is not a multiple of regsize
4411 are treated specially: Irix cc passes
4412 them in registers where gcc sometimes puts them on the
4413 stack. For maximum compatibility, we will put them in
4415 int odd_sized_struct
= (len
> regsize
&& len
% regsize
!= 0);
4417 /* Note: Floating-point values that didn't fit into an FP
4418 register are only written to memory. */
4421 /* Remember if the argument was written to the stack. */
4422 int stack_used_p
= 0;
4423 int partial_len
= (len
< regsize
? len
: regsize
);
4426 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4429 /* Write this portion of the argument to the stack. */
4430 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
4432 || fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4434 /* Should shorter than int integer values be
4435 promoted to int before being stored? */
4436 int longword_offset
= 0;
4439 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4442 && (typecode
== TYPE_CODE_INT
4443 || typecode
== TYPE_CODE_PTR
4444 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
4445 longword_offset
= regsize
- len
;
4446 else if ((typecode
== TYPE_CODE_STRUCT
4447 || typecode
== TYPE_CODE_UNION
)
4448 && TYPE_LENGTH (arg_type
) < regsize
)
4449 longword_offset
= regsize
- len
;
4454 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
4455 paddress (gdbarch
, stack_offset
));
4456 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
4457 paddress (gdbarch
, longword_offset
));
4460 addr
= sp
+ stack_offset
+ longword_offset
;
4465 fprintf_unfiltered (gdb_stdlog
, " @%s ",
4466 paddress (gdbarch
, addr
));
4467 for (i
= 0; i
< partial_len
; i
++)
4469 fprintf_unfiltered (gdb_stdlog
, "%02x",
4473 write_memory (addr
, val
, partial_len
);
4476 /* Note!!! This is NOT an else clause. Odd sized
4477 structs may go thru BOTH paths. Floating point
4478 arguments will not. */
4479 /* Write this portion of the argument to a general
4480 purpose register. */
4481 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
)
4482 && !fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4485 extract_signed_integer (val
, partial_len
, byte_order
);
4488 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4490 phex (regval
, regsize
));
4491 regcache_cooked_write_signed (regcache
, argreg
, regval
);
4498 /* Compute the offset into the stack at which we will
4499 copy the next parameter.
4501 In the new EABI (and the NABI32), the stack_offset
4502 only needs to be adjusted when it has been used. */
4505 stack_offset
+= align_up (partial_len
, regsize
);
4509 fprintf_unfiltered (gdb_stdlog
, "\n");
4512 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4514 /* Return adjusted stack pointer. */
4518 /* Determine the return value convention being used. */
4520 static enum return_value_convention
4521 mips_eabi_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
4522 struct type
*type
, struct regcache
*regcache
,
4523 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4525 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4526 int fp_return_type
= 0;
4527 int offset
, regnum
, xfer
;
4529 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
4530 return RETURN_VALUE_STRUCT_CONVENTION
;
4532 /* Floating point type? */
4533 if (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4535 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
4537 /* Structs with a single field of float type
4538 are returned in a floating point register. */
4539 if ((TYPE_CODE (type
) == TYPE_CODE_STRUCT
4540 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4541 && TYPE_NFIELDS (type
) == 1)
4543 struct type
*fieldtype
= TYPE_FIELD_TYPE (type
, 0);
4545 if (TYPE_CODE (check_typedef (fieldtype
)) == TYPE_CODE_FLT
)
4552 /* A floating-point value belongs in the least significant part
4555 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4556 regnum
= mips_regnum (gdbarch
)->fp0
;
4560 /* An integer value goes in V0/V1. */
4562 fprintf_unfiltered (gdb_stderr
, "Return scalar in $v0\n");
4563 regnum
= MIPS_V0_REGNUM
;
4566 offset
< TYPE_LENGTH (type
);
4567 offset
+= mips_abi_regsize (gdbarch
), regnum
++)
4569 xfer
= mips_abi_regsize (gdbarch
);
4570 if (offset
+ xfer
> TYPE_LENGTH (type
))
4571 xfer
= TYPE_LENGTH (type
) - offset
;
4572 mips_xfer_register (gdbarch
, regcache
,
4573 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
4574 gdbarch_byte_order (gdbarch
), readbuf
, writebuf
,
4578 return RETURN_VALUE_REGISTER_CONVENTION
;
4582 /* N32/N64 ABI stuff. */
4584 /* Search for a naturally aligned double at OFFSET inside a struct
4585 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
4589 mips_n32n64_fp_arg_chunk_p (struct gdbarch
*gdbarch
, struct type
*arg_type
,
4594 if (TYPE_CODE (arg_type
) != TYPE_CODE_STRUCT
)
4597 if (MIPS_FPU_TYPE (gdbarch
) != MIPS_FPU_DOUBLE
)
4600 if (TYPE_LENGTH (arg_type
) < offset
+ MIPS64_REGSIZE
)
4603 for (i
= 0; i
< TYPE_NFIELDS (arg_type
); i
++)
4606 struct type
*field_type
;
4608 /* We're only looking at normal fields. */
4609 if (field_is_static (&TYPE_FIELD (arg_type
, i
))
4610 || (TYPE_FIELD_BITPOS (arg_type
, i
) % 8) != 0)
4613 /* If we have gone past the offset, there is no double to pass. */
4614 pos
= TYPE_FIELD_BITPOS (arg_type
, i
) / 8;
4618 field_type
= check_typedef (TYPE_FIELD_TYPE (arg_type
, i
));
4620 /* If this field is entirely before the requested offset, go
4621 on to the next one. */
4622 if (pos
+ TYPE_LENGTH (field_type
) <= offset
)
4625 /* If this is our special aligned double, we can stop. */
4626 if (TYPE_CODE (field_type
) == TYPE_CODE_FLT
4627 && TYPE_LENGTH (field_type
) == MIPS64_REGSIZE
)
4630 /* This field starts at or before the requested offset, and
4631 overlaps it. If it is a structure, recurse inwards. */
4632 return mips_n32n64_fp_arg_chunk_p (gdbarch
, field_type
, offset
- pos
);
4639 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4640 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4641 int nargs
, struct value
**args
, CORE_ADDR sp
,
4642 int struct_return
, CORE_ADDR struct_addr
)
4648 int stack_offset
= 0;
4649 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4650 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4652 /* For shared libraries, "t9" needs to point at the function
4654 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4656 /* Set the return address register to point to the entry point of
4657 the program, where a breakpoint lies in wait. */
4658 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4660 /* First ensure that the stack and structure return address (if any)
4661 are properly aligned. The stack has to be at least 64-bit
4662 aligned even on 32-bit machines, because doubles must be 64-bit
4663 aligned. For n32 and n64, stack frames need to be 128-bit
4664 aligned, so we round to this widest known alignment. */
4666 sp
= align_down (sp
, 16);
4667 struct_addr
= align_down (struct_addr
, 16);
4669 /* Now make space on the stack for the args. */
4670 for (argnum
= 0; argnum
< nargs
; argnum
++)
4671 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), MIPS64_REGSIZE
);
4672 sp
-= align_up (len
, 16);
4675 fprintf_unfiltered (gdb_stdlog
,
4676 "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n",
4677 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
4679 /* Initialize the integer and float register pointers. */
4680 argreg
= MIPS_A0_REGNUM
;
4681 float_argreg
= mips_fpa0_regnum (gdbarch
);
4683 /* The struct_return pointer occupies the first parameter-passing reg. */
4687 fprintf_unfiltered (gdb_stdlog
,
4688 "mips_n32n64_push_dummy_call: "
4689 "struct_return reg=%d %s\n",
4690 argreg
, paddress (gdbarch
, struct_addr
));
4691 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4694 /* Now load as many as possible of the first arguments into
4695 registers, and push the rest onto the stack. Loop thru args
4696 from first to last. */
4697 for (argnum
= 0; argnum
< nargs
; argnum
++)
4699 const gdb_byte
*val
;
4700 struct value
*arg
= args
[argnum
];
4701 struct type
*arg_type
= check_typedef (value_type (arg
));
4702 int len
= TYPE_LENGTH (arg_type
);
4703 enum type_code typecode
= TYPE_CODE (arg_type
);
4706 fprintf_unfiltered (gdb_stdlog
,
4707 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
4708 argnum
+ 1, len
, (int) typecode
);
4710 val
= value_contents (arg
);
4712 /* A 128-bit long double value requires an even-odd pair of
4713 floating-point registers. */
4715 && fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4716 && (float_argreg
& 1))
4722 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4723 && argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
4725 /* This is a floating point value that fits entirely
4726 in a single register or a pair of registers. */
4727 int reglen
= (len
<= MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
4728 LONGEST regval
= extract_unsigned_integer (val
, reglen
, byte_order
);
4730 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4731 float_argreg
, phex (regval
, reglen
));
4732 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
4735 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4736 argreg
, phex (regval
, reglen
));
4737 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4742 regval
= extract_unsigned_integer (val
+ reglen
,
4743 reglen
, byte_order
);
4745 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4746 float_argreg
, phex (regval
, reglen
));
4747 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
4750 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4751 argreg
, phex (regval
, reglen
));
4752 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4759 /* Copy the argument to general registers or the stack in
4760 register-sized pieces. Large arguments are split between
4761 registers and stack. */
4762 /* For N32/N64, structs, unions, or other composite types are
4763 treated as a sequence of doublewords, and are passed in integer
4764 or floating point registers as though they were simple scalar
4765 parameters to the extent that they fit, with any excess on the
4766 stack packed according to the normal memory layout of the
4768 The caller does not reserve space for the register arguments;
4769 the callee is responsible for reserving it if required. */
4770 /* Note: Floating-point values that didn't fit into an FP
4771 register are only written to memory. */
4774 /* Remember if the argument was written to the stack. */
4775 int stack_used_p
= 0;
4776 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
4779 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4782 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4783 gdb_assert (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
));
4785 /* Write this portion of the argument to the stack. */
4786 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
))
4788 /* Should shorter than int integer values be
4789 promoted to int before being stored? */
4790 int longword_offset
= 0;
4793 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4795 if ((typecode
== TYPE_CODE_INT
4796 || typecode
== TYPE_CODE_PTR
)
4798 longword_offset
= MIPS64_REGSIZE
- len
;
4803 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
4804 paddress (gdbarch
, stack_offset
));
4805 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
4806 paddress (gdbarch
, longword_offset
));
4809 addr
= sp
+ stack_offset
+ longword_offset
;
4814 fprintf_unfiltered (gdb_stdlog
, " @%s ",
4815 paddress (gdbarch
, addr
));
4816 for (i
= 0; i
< partial_len
; i
++)
4818 fprintf_unfiltered (gdb_stdlog
, "%02x",
4822 write_memory (addr
, val
, partial_len
);
4825 /* Note!!! This is NOT an else clause. Odd sized
4826 structs may go thru BOTH paths. */
4827 /* Write this portion of the argument to a general
4828 purpose register. */
4829 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
4833 /* Sign extend pointers, 32-bit integers and signed
4834 16-bit and 8-bit integers; everything else is taken
4837 if ((partial_len
== 4
4838 && (typecode
== TYPE_CODE_PTR
4839 || typecode
== TYPE_CODE_INT
))
4841 && typecode
== TYPE_CODE_INT
4842 && !TYPE_UNSIGNED (arg_type
)))
4843 regval
= extract_signed_integer (val
, partial_len
,
4846 regval
= extract_unsigned_integer (val
, partial_len
,
4849 /* A non-floating-point argument being passed in a
4850 general register. If a struct or union, and if
4851 the remaining length is smaller than the register
4852 size, we have to adjust the register value on
4855 It does not seem to be necessary to do the
4856 same for integral types. */
4858 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
4859 && partial_len
< MIPS64_REGSIZE
4860 && (typecode
== TYPE_CODE_STRUCT
4861 || typecode
== TYPE_CODE_UNION
))
4862 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
4866 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4868 phex (regval
, MIPS64_REGSIZE
));
4869 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4871 if (mips_n32n64_fp_arg_chunk_p (gdbarch
, arg_type
,
4872 TYPE_LENGTH (arg_type
) - len
))
4875 fprintf_filtered (gdb_stdlog
, " - fpreg=%d val=%s",
4877 phex (regval
, MIPS64_REGSIZE
));
4878 regcache_cooked_write_unsigned (regcache
, float_argreg
,
4889 /* Compute the offset into the stack at which we will
4890 copy the next parameter.
4892 In N32 (N64?), the stack_offset only needs to be
4893 adjusted when it has been used. */
4896 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
4900 fprintf_unfiltered (gdb_stdlog
, "\n");
4903 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4905 /* Return adjusted stack pointer. */
4909 static enum return_value_convention
4910 mips_n32n64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
4911 struct type
*type
, struct regcache
*regcache
,
4912 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4914 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4916 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
4918 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
4919 if needed), as appropriate for the type. Composite results (struct,
4920 union, or array) are returned in $2/$f0 and $3/$f2 according to the
4923 * A struct with only one or two floating point fields is returned in $f0
4924 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
4927 * Any other composite results of at most 128 bits are returned in
4928 $2 (first 64 bits) and $3 (remainder, if necessary).
4930 * Larger composite results are handled by converting the function to a
4931 procedure with an implicit first parameter, which is a pointer to an area
4932 reserved by the caller to receive the result. [The o32-bit ABI requires
4933 that all composite results be handled by conversion to implicit first
4934 parameters. The MIPS/SGI Fortran implementation has always made a
4935 specific exception to return COMPLEX results in the floating point
4938 if (TYPE_LENGTH (type
) > 2 * MIPS64_REGSIZE
)
4939 return RETURN_VALUE_STRUCT_CONVENTION
;
4940 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4941 && TYPE_LENGTH (type
) == 16
4942 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4944 /* A 128-bit floating-point value fills both $f0 and $f2. The
4945 two registers are used in the same as memory order, so the
4946 eight bytes with the lower memory address are in $f0. */
4948 fprintf_unfiltered (gdb_stderr
, "Return float in $f0 and $f2\n");
4949 mips_xfer_register (gdbarch
, regcache
,
4950 (gdbarch_num_regs (gdbarch
)
4951 + mips_regnum (gdbarch
)->fp0
),
4952 8, gdbarch_byte_order (gdbarch
),
4953 readbuf
, writebuf
, 0);
4954 mips_xfer_register (gdbarch
, regcache
,
4955 (gdbarch_num_regs (gdbarch
)
4956 + mips_regnum (gdbarch
)->fp0
+ 2),
4957 8, gdbarch_byte_order (gdbarch
),
4958 readbuf
? readbuf
+ 8 : readbuf
,
4959 writebuf
? writebuf
+ 8 : writebuf
, 0);
4960 return RETURN_VALUE_REGISTER_CONVENTION
;
4962 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4963 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4965 /* A single or double floating-point value that fits in FP0. */
4967 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4968 mips_xfer_register (gdbarch
, regcache
,
4969 (gdbarch_num_regs (gdbarch
)
4970 + mips_regnum (gdbarch
)->fp0
),
4972 gdbarch_byte_order (gdbarch
),
4973 readbuf
, writebuf
, 0);
4974 return RETURN_VALUE_REGISTER_CONVENTION
;
4976 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4977 && TYPE_NFIELDS (type
) <= 2
4978 && TYPE_NFIELDS (type
) >= 1
4979 && ((TYPE_NFIELDS (type
) == 1
4980 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
4982 || (TYPE_NFIELDS (type
) == 2
4983 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
4985 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 1)))
4986 == TYPE_CODE_FLT
))))
4988 /* A struct that contains one or two floats. Each value is part
4989 in the least significant part of their floating point
4990 register (or GPR, for soft float). */
4993 for (field
= 0, regnum
= (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
4994 ? mips_regnum (gdbarch
)->fp0
4996 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
4998 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
5001 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
5003 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)) == 16)
5005 /* A 16-byte long double field goes in two consecutive
5007 mips_xfer_register (gdbarch
, regcache
,
5008 gdbarch_num_regs (gdbarch
) + regnum
,
5010 gdbarch_byte_order (gdbarch
),
5011 readbuf
, writebuf
, offset
);
5012 mips_xfer_register (gdbarch
, regcache
,
5013 gdbarch_num_regs (gdbarch
) + regnum
+ 1,
5015 gdbarch_byte_order (gdbarch
),
5016 readbuf
, writebuf
, offset
+ 8);
5019 mips_xfer_register (gdbarch
, regcache
,
5020 gdbarch_num_regs (gdbarch
) + regnum
,
5021 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
5022 gdbarch_byte_order (gdbarch
),
5023 readbuf
, writebuf
, offset
);
5025 return RETURN_VALUE_REGISTER_CONVENTION
;
5027 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5028 || TYPE_CODE (type
) == TYPE_CODE_UNION
5029 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
5031 /* A composite type. Extract the left justified value,
5032 regardless of the byte order. I.e. DO NOT USE
5036 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5037 offset
< TYPE_LENGTH (type
);
5038 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5040 int xfer
= register_size (gdbarch
, regnum
);
5041 if (offset
+ xfer
> TYPE_LENGTH (type
))
5042 xfer
= TYPE_LENGTH (type
) - offset
;
5044 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5045 offset
, xfer
, regnum
);
5046 mips_xfer_register (gdbarch
, regcache
,
5047 gdbarch_num_regs (gdbarch
) + regnum
,
5048 xfer
, BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
,
5051 return RETURN_VALUE_REGISTER_CONVENTION
;
5055 /* A scalar extract each part but least-significant-byte
5059 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5060 offset
< TYPE_LENGTH (type
);
5061 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5063 int xfer
= register_size (gdbarch
, regnum
);
5064 if (offset
+ xfer
> TYPE_LENGTH (type
))
5065 xfer
= TYPE_LENGTH (type
) - offset
;
5067 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5068 offset
, xfer
, regnum
);
5069 mips_xfer_register (gdbarch
, regcache
,
5070 gdbarch_num_regs (gdbarch
) + regnum
,
5071 xfer
, gdbarch_byte_order (gdbarch
),
5072 readbuf
, writebuf
, offset
);
5074 return RETURN_VALUE_REGISTER_CONVENTION
;
5078 /* Which registers to use for passing floating-point values between
5079 function calls, one of floating-point, general and both kinds of
5080 registers. O32 and O64 use different register kinds for standard
5081 MIPS and MIPS16 code; to make the handling of cases where we may
5082 not know what kind of code is being used (e.g. no debug information)
5083 easier we sometimes use both kinds. */
5092 /* O32 ABI stuff. */
5095 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
5096 struct regcache
*regcache
, CORE_ADDR bp_addr
,
5097 int nargs
, struct value
**args
, CORE_ADDR sp
,
5098 int struct_return
, CORE_ADDR struct_addr
)
5104 int stack_offset
= 0;
5105 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5106 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
5108 /* For shared libraries, "t9" needs to point at the function
5110 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
5112 /* Set the return address register to point to the entry point of
5113 the program, where a breakpoint lies in wait. */
5114 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
5116 /* First ensure that the stack and structure return address (if any)
5117 are properly aligned. The stack has to be at least 64-bit
5118 aligned even on 32-bit machines, because doubles must be 64-bit
5119 aligned. For n32 and n64, stack frames need to be 128-bit
5120 aligned, so we round to this widest known alignment. */
5122 sp
= align_down (sp
, 16);
5123 struct_addr
= align_down (struct_addr
, 16);
5125 /* Now make space on the stack for the args. */
5126 for (argnum
= 0; argnum
< nargs
; argnum
++)
5128 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
5129 int arglen
= TYPE_LENGTH (arg_type
);
5131 /* Align to double-word if necessary. */
5132 if (mips_type_needs_double_align (arg_type
))
5133 len
= align_up (len
, MIPS32_REGSIZE
* 2);
5134 /* Allocate space on the stack. */
5135 len
+= align_up (arglen
, MIPS32_REGSIZE
);
5137 sp
-= align_up (len
, 16);
5140 fprintf_unfiltered (gdb_stdlog
,
5141 "mips_o32_push_dummy_call: sp=%s allocated %ld\n",
5142 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
5144 /* Initialize the integer and float register pointers. */
5145 argreg
= MIPS_A0_REGNUM
;
5146 float_argreg
= mips_fpa0_regnum (gdbarch
);
5148 /* The struct_return pointer occupies the first parameter-passing reg. */
5152 fprintf_unfiltered (gdb_stdlog
,
5153 "mips_o32_push_dummy_call: "
5154 "struct_return reg=%d %s\n",
5155 argreg
, paddress (gdbarch
, struct_addr
));
5156 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
5157 stack_offset
+= MIPS32_REGSIZE
;
5160 /* Now load as many as possible of the first arguments into
5161 registers, and push the rest onto the stack. Loop thru args
5162 from first to last. */
5163 for (argnum
= 0; argnum
< nargs
; argnum
++)
5165 const gdb_byte
*val
;
5166 struct value
*arg
= args
[argnum
];
5167 struct type
*arg_type
= check_typedef (value_type (arg
));
5168 int len
= TYPE_LENGTH (arg_type
);
5169 enum type_code typecode
= TYPE_CODE (arg_type
);
5172 fprintf_unfiltered (gdb_stdlog
,
5173 "mips_o32_push_dummy_call: %d len=%d type=%d",
5174 argnum
+ 1, len
, (int) typecode
);
5176 val
= value_contents (arg
);
5178 /* 32-bit ABIs always start floating point arguments in an
5179 even-numbered floating point register. Round the FP register
5180 up before the check to see if there are any FP registers
5181 left. O32 targets also pass the FP in the integer registers
5182 so also round up normal registers. */
5183 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
5185 if ((float_argreg
& 1))
5189 /* Floating point arguments passed in registers have to be
5190 treated specially. On 32-bit architectures, doubles are
5191 passed in register pairs; the even FP register gets the
5192 low word, and the odd FP register gets the high word.
5193 On O32, the first two floating point arguments are also
5194 copied to general registers, following their memory order,
5195 because MIPS16 functions don't use float registers for
5196 arguments. This duplication of arguments in general
5197 registers can't hurt non-MIPS16 functions, because those
5198 registers are normally skipped. */
5200 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5201 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
5203 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
5205 int freg_offset
= gdbarch_byte_order (gdbarch
)
5206 == BFD_ENDIAN_BIG
? 1 : 0;
5207 unsigned long regval
;
5210 regval
= extract_unsigned_integer (val
, 4, byte_order
);
5212 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5213 float_argreg
+ freg_offset
,
5215 regcache_cooked_write_unsigned (regcache
,
5216 float_argreg
++ + freg_offset
,
5219 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5220 argreg
, phex (regval
, 4));
5221 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5224 regval
= extract_unsigned_integer (val
+ 4, 4, byte_order
);
5226 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5227 float_argreg
- freg_offset
,
5229 regcache_cooked_write_unsigned (regcache
,
5230 float_argreg
++ - freg_offset
,
5233 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5234 argreg
, phex (regval
, 4));
5235 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5239 /* This is a floating point value that fits entirely
5240 in a single register. */
5241 /* On 32 bit ABI's the float_argreg is further adjusted
5242 above to ensure that it is even register aligned. */
5243 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
5245 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5246 float_argreg
, phex (regval
, len
));
5247 regcache_cooked_write_unsigned (regcache
,
5248 float_argreg
++, regval
);
5249 /* Although two FP registers are reserved for each
5250 argument, only one corresponding integer register is
5253 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5254 argreg
, phex (regval
, len
));
5255 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5257 /* Reserve space for the FP register. */
5258 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
5262 /* Copy the argument to general registers or the stack in
5263 register-sized pieces. Large arguments are split between
5264 registers and stack. */
5265 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
5266 are treated specially: Irix cc passes
5267 them in registers where gcc sometimes puts them on the
5268 stack. For maximum compatibility, we will put them in
5270 int odd_sized_struct
= (len
> MIPS32_REGSIZE
5271 && len
% MIPS32_REGSIZE
!= 0);
5272 /* Structures should be aligned to eight bytes (even arg registers)
5273 on MIPS_ABI_O32, if their first member has double precision. */
5274 if (mips_type_needs_double_align (arg_type
))
5279 stack_offset
+= MIPS32_REGSIZE
;
5284 /* Remember if the argument was written to the stack. */
5285 int stack_used_p
= 0;
5286 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
5289 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
5292 /* Write this portion of the argument to the stack. */
5293 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
5294 || odd_sized_struct
)
5296 /* Should shorter than int integer values be
5297 promoted to int before being stored? */
5298 int longword_offset
= 0;
5304 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
5305 paddress (gdbarch
, stack_offset
));
5306 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
5307 paddress (gdbarch
, longword_offset
));
5310 addr
= sp
+ stack_offset
+ longword_offset
;
5315 fprintf_unfiltered (gdb_stdlog
, " @%s ",
5316 paddress (gdbarch
, addr
));
5317 for (i
= 0; i
< partial_len
; i
++)
5319 fprintf_unfiltered (gdb_stdlog
, "%02x",
5323 write_memory (addr
, val
, partial_len
);
5326 /* Note!!! This is NOT an else clause. Odd sized
5327 structs may go thru BOTH paths. */
5328 /* Write this portion of the argument to a general
5329 purpose register. */
5330 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
5332 LONGEST regval
= extract_signed_integer (val
, partial_len
,
5334 /* Value may need to be sign extended, because
5335 mips_isa_regsize() != mips_abi_regsize(). */
5337 /* A non-floating-point argument being passed in a
5338 general register. If a struct or union, and if
5339 the remaining length is smaller than the register
5340 size, we have to adjust the register value on
5343 It does not seem to be necessary to do the
5344 same for integral types.
5346 Also don't do this adjustment on O64 binaries.
5348 cagney/2001-07-23: gdb/179: Also, GCC, when
5349 outputting LE O32 with sizeof (struct) <
5350 mips_abi_regsize(), generates a left shift
5351 as part of storing the argument in a register
5352 (the left shift isn't generated when
5353 sizeof (struct) >= mips_abi_regsize()). Since
5354 it is quite possible that this is GCC
5355 contradicting the LE/O32 ABI, GDB has not been
5356 adjusted to accommodate this. Either someone
5357 needs to demonstrate that the LE/O32 ABI
5358 specifies such a left shift OR this new ABI gets
5359 identified as such and GDB gets tweaked
5362 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
5363 && partial_len
< MIPS32_REGSIZE
5364 && (typecode
== TYPE_CODE_STRUCT
5365 || typecode
== TYPE_CODE_UNION
))
5366 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
5370 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
5372 phex (regval
, MIPS32_REGSIZE
));
5373 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5376 /* Prevent subsequent floating point arguments from
5377 being passed in floating point registers. */
5378 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
5384 /* Compute the offset into the stack at which we will
5385 copy the next parameter.
5387 In older ABIs, the caller reserved space for
5388 registers that contained arguments. This was loosely
5389 refered to as their "home". Consequently, space is
5390 always allocated. */
5392 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
5396 fprintf_unfiltered (gdb_stdlog
, "\n");
5399 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
5401 /* Return adjusted stack pointer. */
5405 static enum return_value_convention
5406 mips_o32_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
5407 struct type
*type
, struct regcache
*regcache
,
5408 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5410 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
5411 int mips16
= mips_pc_is_mips16 (gdbarch
, func_addr
);
5412 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5413 enum mips_fval_reg fval_reg
;
5415 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
5416 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5417 || TYPE_CODE (type
) == TYPE_CODE_UNION
5418 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
5419 return RETURN_VALUE_STRUCT_CONVENTION
;
5420 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
5421 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5423 /* A single-precision floating-point value. If reading in or copying,
5424 then we get it from/put it to FP0 for standard MIPS code or GPR2
5425 for MIPS16 code. If writing out only, then we put it to both FP0
5426 and GPR2. We do not support reading in with no function known, if
5427 this safety check ever triggers, then we'll have to try harder. */
5428 gdb_assert (function
|| !readbuf
);
5433 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
5436 fprintf_unfiltered (gdb_stderr
, "Return float in $2\n");
5438 case mips_fval_both
:
5439 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0 and $2\n");
5442 if (fval_reg
!= mips_fval_gpr
)
5443 mips_xfer_register (gdbarch
, regcache
,
5444 (gdbarch_num_regs (gdbarch
)
5445 + mips_regnum (gdbarch
)->fp0
),
5447 gdbarch_byte_order (gdbarch
),
5448 readbuf
, writebuf
, 0);
5449 if (fval_reg
!= mips_fval_fpr
)
5450 mips_xfer_register (gdbarch
, regcache
,
5451 gdbarch_num_regs (gdbarch
) + 2,
5453 gdbarch_byte_order (gdbarch
),
5454 readbuf
, writebuf
, 0);
5455 return RETURN_VALUE_REGISTER_CONVENTION
;
5457 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
5458 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5460 /* A double-precision floating-point value. If reading in or copying,
5461 then we get it from/put it to FP1 and FP0 for standard MIPS code or
5462 GPR2 and GPR3 for MIPS16 code. If writing out only, then we put it
5463 to both FP1/FP0 and GPR2/GPR3. We do not support reading in with
5464 no function known, if this safety check ever triggers, then we'll
5465 have to try harder. */
5466 gdb_assert (function
|| !readbuf
);
5471 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
5474 fprintf_unfiltered (gdb_stderr
, "Return float in $2/$3\n");
5476 case mips_fval_both
:
5477 fprintf_unfiltered (gdb_stderr
,
5478 "Return float in $fp1/$fp0 and $2/$3\n");
5481 if (fval_reg
!= mips_fval_gpr
)
5483 /* The most significant part goes in FP1, and the least significant
5485 switch (gdbarch_byte_order (gdbarch
))
5487 case BFD_ENDIAN_LITTLE
:
5488 mips_xfer_register (gdbarch
, regcache
,
5489 (gdbarch_num_regs (gdbarch
)
5490 + mips_regnum (gdbarch
)->fp0
+ 0),
5491 4, gdbarch_byte_order (gdbarch
),
5492 readbuf
, writebuf
, 0);
5493 mips_xfer_register (gdbarch
, regcache
,
5494 (gdbarch_num_regs (gdbarch
)
5495 + mips_regnum (gdbarch
)->fp0
+ 1),
5496 4, gdbarch_byte_order (gdbarch
),
5497 readbuf
, writebuf
, 4);
5499 case BFD_ENDIAN_BIG
:
5500 mips_xfer_register (gdbarch
, regcache
,
5501 (gdbarch_num_regs (gdbarch
)
5502 + mips_regnum (gdbarch
)->fp0
+ 1),
5503 4, gdbarch_byte_order (gdbarch
),
5504 readbuf
, writebuf
, 0);
5505 mips_xfer_register (gdbarch
, regcache
,
5506 (gdbarch_num_regs (gdbarch
)
5507 + mips_regnum (gdbarch
)->fp0
+ 0),
5508 4, gdbarch_byte_order (gdbarch
),
5509 readbuf
, writebuf
, 4);
5512 internal_error (__FILE__
, __LINE__
, _("bad switch"));
5515 if (fval_reg
!= mips_fval_fpr
)
5517 /* The two 32-bit parts are always placed in GPR2 and GPR3
5518 following these registers' memory order. */
5519 mips_xfer_register (gdbarch
, regcache
,
5520 gdbarch_num_regs (gdbarch
) + 2,
5521 4, gdbarch_byte_order (gdbarch
),
5522 readbuf
, writebuf
, 0);
5523 mips_xfer_register (gdbarch
, regcache
,
5524 gdbarch_num_regs (gdbarch
) + 3,
5525 4, gdbarch_byte_order (gdbarch
),
5526 readbuf
, writebuf
, 4);
5528 return RETURN_VALUE_REGISTER_CONVENTION
;
5531 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5532 && TYPE_NFIELDS (type
) <= 2
5533 && TYPE_NFIELDS (type
) >= 1
5534 && ((TYPE_NFIELDS (type
) == 1
5535 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
5537 || (TYPE_NFIELDS (type
) == 2
5538 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
5540 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
5542 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5544 /* A struct that contains one or two floats. Each value is part
5545 in the least significant part of their floating point
5547 gdb_byte reg
[MAX_REGISTER_SIZE
];
5550 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
5551 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
5553 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
5556 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
5558 mips_xfer_register (gdbarch
, regcache
,
5559 gdbarch_num_regs (gdbarch
) + regnum
,
5560 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
5561 gdbarch_byte_order (gdbarch
),
5562 readbuf
, writebuf
, offset
);
5564 return RETURN_VALUE_REGISTER_CONVENTION
;
5568 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5569 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
5571 /* A structure or union. Extract the left justified value,
5572 regardless of the byte order. I.e. DO NOT USE
5576 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5577 offset
< TYPE_LENGTH (type
);
5578 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5580 int xfer
= register_size (gdbarch
, regnum
);
5581 if (offset
+ xfer
> TYPE_LENGTH (type
))
5582 xfer
= TYPE_LENGTH (type
) - offset
;
5584 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5585 offset
, xfer
, regnum
);
5586 mips_xfer_register (gdbarch
, regcache
,
5587 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
5588 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
5590 return RETURN_VALUE_REGISTER_CONVENTION
;
5595 /* A scalar extract each part but least-significant-byte
5596 justified. o32 thinks registers are 4 byte, regardless of
5600 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5601 offset
< TYPE_LENGTH (type
);
5602 offset
+= MIPS32_REGSIZE
, regnum
++)
5604 int xfer
= MIPS32_REGSIZE
;
5605 if (offset
+ xfer
> TYPE_LENGTH (type
))
5606 xfer
= TYPE_LENGTH (type
) - offset
;
5608 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5609 offset
, xfer
, regnum
);
5610 mips_xfer_register (gdbarch
, regcache
,
5611 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
5612 gdbarch_byte_order (gdbarch
),
5613 readbuf
, writebuf
, offset
);
5615 return RETURN_VALUE_REGISTER_CONVENTION
;
5619 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
5623 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
5624 struct regcache
*regcache
, CORE_ADDR bp_addr
,
5626 struct value
**args
, CORE_ADDR sp
,
5627 int struct_return
, CORE_ADDR struct_addr
)
5633 int stack_offset
= 0;
5634 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5635 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
5637 /* For shared libraries, "t9" needs to point at the function
5639 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
5641 /* Set the return address register to point to the entry point of
5642 the program, where a breakpoint lies in wait. */
5643 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
5645 /* First ensure that the stack and structure return address (if any)
5646 are properly aligned. The stack has to be at least 64-bit
5647 aligned even on 32-bit machines, because doubles must be 64-bit
5648 aligned. For n32 and n64, stack frames need to be 128-bit
5649 aligned, so we round to this widest known alignment. */
5651 sp
= align_down (sp
, 16);
5652 struct_addr
= align_down (struct_addr
, 16);
5654 /* Now make space on the stack for the args. */
5655 for (argnum
= 0; argnum
< nargs
; argnum
++)
5657 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
5658 int arglen
= TYPE_LENGTH (arg_type
);
5660 /* Allocate space on the stack. */
5661 len
+= align_up (arglen
, MIPS64_REGSIZE
);
5663 sp
-= align_up (len
, 16);
5666 fprintf_unfiltered (gdb_stdlog
,
5667 "mips_o64_push_dummy_call: sp=%s allocated %ld\n",
5668 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
5670 /* Initialize the integer and float register pointers. */
5671 argreg
= MIPS_A0_REGNUM
;
5672 float_argreg
= mips_fpa0_regnum (gdbarch
);
5674 /* The struct_return pointer occupies the first parameter-passing reg. */
5678 fprintf_unfiltered (gdb_stdlog
,
5679 "mips_o64_push_dummy_call: "
5680 "struct_return reg=%d %s\n",
5681 argreg
, paddress (gdbarch
, struct_addr
));
5682 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
5683 stack_offset
+= MIPS64_REGSIZE
;
5686 /* Now load as many as possible of the first arguments into
5687 registers, and push the rest onto the stack. Loop thru args
5688 from first to last. */
5689 for (argnum
= 0; argnum
< nargs
; argnum
++)
5691 const gdb_byte
*val
;
5692 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
5693 struct value
*arg
= args
[argnum
];
5694 struct type
*arg_type
= check_typedef (value_type (arg
));
5695 int len
= TYPE_LENGTH (arg_type
);
5696 enum type_code typecode
= TYPE_CODE (arg_type
);
5699 fprintf_unfiltered (gdb_stdlog
,
5700 "mips_o64_push_dummy_call: %d len=%d type=%d",
5701 argnum
+ 1, len
, (int) typecode
);
5703 val
= value_contents (arg
);
5705 /* Function pointer arguments to mips16 code need to be made into
5707 if (typecode
== TYPE_CODE_PTR
5708 && TYPE_CODE (TYPE_TARGET_TYPE (arg_type
)) == TYPE_CODE_FUNC
)
5710 CORE_ADDR addr
= extract_signed_integer (value_contents (arg
),
5712 if (!mips_pc_is_mips (addr
))
5714 store_signed_integer (valbuf
, len
, byte_order
,
5715 make_compact_addr (addr
));
5720 /* Floating point arguments passed in registers have to be
5721 treated specially. On 32-bit architectures, doubles are
5722 passed in register pairs; the even FP register gets the
5723 low word, and the odd FP register gets the high word.
5724 On O64, the first two floating point arguments are also
5725 copied to general registers, because MIPS16 functions
5726 don't use float registers for arguments. This duplication
5727 of arguments in general registers can't hurt non-MIPS16
5728 functions because those registers are normally skipped. */
5730 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5731 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
5733 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
5735 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5736 float_argreg
, phex (regval
, len
));
5737 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
5739 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5740 argreg
, phex (regval
, len
));
5741 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5743 /* Reserve space for the FP register. */
5744 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
5748 /* Copy the argument to general registers or the stack in
5749 register-sized pieces. Large arguments are split between
5750 registers and stack. */
5751 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
5752 are treated specially: Irix cc passes them in registers
5753 where gcc sometimes puts them on the stack. For maximum
5754 compatibility, we will put them in both places. */
5755 int odd_sized_struct
= (len
> MIPS64_REGSIZE
5756 && len
% MIPS64_REGSIZE
!= 0);
5759 /* Remember if the argument was written to the stack. */
5760 int stack_used_p
= 0;
5761 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
5764 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
5767 /* Write this portion of the argument to the stack. */
5768 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
5769 || odd_sized_struct
)
5771 /* Should shorter than int integer values be
5772 promoted to int before being stored? */
5773 int longword_offset
= 0;
5776 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5778 if ((typecode
== TYPE_CODE_INT
5779 || typecode
== TYPE_CODE_PTR
5780 || typecode
== TYPE_CODE_FLT
)
5782 longword_offset
= MIPS64_REGSIZE
- len
;
5787 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
5788 paddress (gdbarch
, stack_offset
));
5789 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
5790 paddress (gdbarch
, longword_offset
));
5793 addr
= sp
+ stack_offset
+ longword_offset
;
5798 fprintf_unfiltered (gdb_stdlog
, " @%s ",
5799 paddress (gdbarch
, addr
));
5800 for (i
= 0; i
< partial_len
; i
++)
5802 fprintf_unfiltered (gdb_stdlog
, "%02x",
5806 write_memory (addr
, val
, partial_len
);
5809 /* Note!!! This is NOT an else clause. Odd sized
5810 structs may go thru BOTH paths. */
5811 /* Write this portion of the argument to a general
5812 purpose register. */
5813 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
5815 LONGEST regval
= extract_signed_integer (val
, partial_len
,
5817 /* Value may need to be sign extended, because
5818 mips_isa_regsize() != mips_abi_regsize(). */
5820 /* A non-floating-point argument being passed in a
5821 general register. If a struct or union, and if
5822 the remaining length is smaller than the register
5823 size, we have to adjust the register value on
5826 It does not seem to be necessary to do the
5827 same for integral types. */
5829 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
5830 && partial_len
< MIPS64_REGSIZE
5831 && (typecode
== TYPE_CODE_STRUCT
5832 || typecode
== TYPE_CODE_UNION
))
5833 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
5837 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
5839 phex (regval
, MIPS64_REGSIZE
));
5840 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5843 /* Prevent subsequent floating point arguments from
5844 being passed in floating point registers. */
5845 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
5851 /* Compute the offset into the stack at which we will
5852 copy the next parameter.
5854 In older ABIs, the caller reserved space for
5855 registers that contained arguments. This was loosely
5856 refered to as their "home". Consequently, space is
5857 always allocated. */
5859 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
5863 fprintf_unfiltered (gdb_stdlog
, "\n");
5866 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
5868 /* Return adjusted stack pointer. */
5872 static enum return_value_convention
5873 mips_o64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
5874 struct type
*type
, struct regcache
*regcache
,
5875 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5877 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
5878 int mips16
= mips_pc_is_mips16 (gdbarch
, func_addr
);
5879 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5880 enum mips_fval_reg fval_reg
;
5882 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
5883 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5884 || TYPE_CODE (type
) == TYPE_CODE_UNION
5885 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
5886 return RETURN_VALUE_STRUCT_CONVENTION
;
5887 else if (fp_register_arg_p (gdbarch
, TYPE_CODE (type
), type
))
5889 /* A floating-point value. If reading in or copying, then we get it
5890 from/put it to FP0 for standard MIPS code or GPR2 for MIPS16 code.
5891 If writing out only, then we put it to both FP0 and GPR2. We do
5892 not support reading in with no function known, if this safety
5893 check ever triggers, then we'll have to try harder. */
5894 gdb_assert (function
|| !readbuf
);
5899 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
5902 fprintf_unfiltered (gdb_stderr
, "Return float in $2\n");
5904 case mips_fval_both
:
5905 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0 and $2\n");
5908 if (fval_reg
!= mips_fval_gpr
)
5909 mips_xfer_register (gdbarch
, regcache
,
5910 (gdbarch_num_regs (gdbarch
)
5911 + mips_regnum (gdbarch
)->fp0
),
5913 gdbarch_byte_order (gdbarch
),
5914 readbuf
, writebuf
, 0);
5915 if (fval_reg
!= mips_fval_fpr
)
5916 mips_xfer_register (gdbarch
, regcache
,
5917 gdbarch_num_regs (gdbarch
) + 2,
5919 gdbarch_byte_order (gdbarch
),
5920 readbuf
, writebuf
, 0);
5921 return RETURN_VALUE_REGISTER_CONVENTION
;
5925 /* A scalar extract each part but least-significant-byte
5929 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5930 offset
< TYPE_LENGTH (type
);
5931 offset
+= MIPS64_REGSIZE
, regnum
++)
5933 int xfer
= MIPS64_REGSIZE
;
5934 if (offset
+ xfer
> TYPE_LENGTH (type
))
5935 xfer
= TYPE_LENGTH (type
) - offset
;
5937 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5938 offset
, xfer
, regnum
);
5939 mips_xfer_register (gdbarch
, regcache
,
5940 gdbarch_num_regs (gdbarch
) + regnum
,
5941 xfer
, gdbarch_byte_order (gdbarch
),
5942 readbuf
, writebuf
, offset
);
5944 return RETURN_VALUE_REGISTER_CONVENTION
;
5948 /* Floating point register management.
5950 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
5951 64bit operations, these early MIPS cpus treat fp register pairs
5952 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
5953 registers and offer a compatibility mode that emulates the MIPS2 fp
5954 model. When operating in MIPS2 fp compat mode, later cpu's split
5955 double precision floats into two 32-bit chunks and store them in
5956 consecutive fp regs. To display 64-bit floats stored in this
5957 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
5958 Throw in user-configurable endianness and you have a real mess.
5960 The way this works is:
5961 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
5962 double-precision value will be split across two logical registers.
5963 The lower-numbered logical register will hold the low-order bits,
5964 regardless of the processor's endianness.
5965 - If we are on a 64-bit processor, and we are looking for a
5966 single-precision value, it will be in the low ordered bits
5967 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
5968 save slot in memory.
5969 - If we are in 64-bit mode, everything is straightforward.
5971 Note that this code only deals with "live" registers at the top of the
5972 stack. We will attempt to deal with saved registers later, when
5973 the raw/cooked register interface is in place. (We need a general
5974 interface that can deal with dynamic saved register sizes -- fp
5975 regs could be 32 bits wide in one frame and 64 on the frame above
5978 /* Copy a 32-bit single-precision value from the current frame
5979 into rare_buffer. */
5982 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
5983 gdb_byte
*rare_buffer
)
5985 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5986 int raw_size
= register_size (gdbarch
, regno
);
5987 gdb_byte
*raw_buffer
= alloca (raw_size
);
5989 if (!frame_register_read (frame
, regno
, raw_buffer
))
5990 error (_("can't read register %d (%s)"),
5991 regno
, gdbarch_register_name (gdbarch
, regno
));
5994 /* We have a 64-bit value for this register. Find the low-order
5998 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6003 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
6007 memcpy (rare_buffer
, raw_buffer
, 4);
6011 /* Copy a 64-bit double-precision value from the current frame into
6012 rare_buffer. This may include getting half of it from the next
6016 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
6017 gdb_byte
*rare_buffer
)
6019 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6020 int raw_size
= register_size (gdbarch
, regno
);
6022 if (raw_size
== 8 && !mips2_fp_compat (frame
))
6024 /* We have a 64-bit value for this register, and we should use
6026 if (!frame_register_read (frame
, regno
, rare_buffer
))
6027 error (_("can't read register %d (%s)"),
6028 regno
, gdbarch_register_name (gdbarch
, regno
));
6032 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
6034 if ((rawnum
- mips_regnum (gdbarch
)->fp0
) & 1)
6035 internal_error (__FILE__
, __LINE__
,
6036 _("mips_read_fp_register_double: bad access to "
6037 "odd-numbered FP register"));
6039 /* mips_read_fp_register_single will find the correct 32 bits from
6041 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6043 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
6044 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
6048 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
6049 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
6055 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
6057 { /* Do values for FP (float) regs. */
6058 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6059 gdb_byte
*raw_buffer
;
6060 double doub
, flt1
; /* Doubles extracted from raw hex data. */
6063 raw_buffer
= alloca (2 * register_size (gdbarch
,
6064 mips_regnum (gdbarch
)->fp0
));
6066 fprintf_filtered (file
, "%s:", gdbarch_register_name (gdbarch
, regnum
));
6067 fprintf_filtered (file
, "%*s",
6068 4 - (int) strlen (gdbarch_register_name (gdbarch
, regnum
)),
6071 if (register_size (gdbarch
, regnum
) == 4 || mips2_fp_compat (frame
))
6073 struct value_print_options opts
;
6075 /* 4-byte registers: Print hex and floating. Also print even
6076 numbered registers as doubles. */
6077 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
6078 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
6081 get_formatted_print_options (&opts
, 'x');
6082 print_scalar_formatted (raw_buffer
,
6083 builtin_type (gdbarch
)->builtin_uint32
,
6086 fprintf_filtered (file
, " flt: ");
6088 fprintf_filtered (file
, " <invalid float> ");
6090 fprintf_filtered (file
, "%-17.9g", flt1
);
6092 if ((regnum
- gdbarch_num_regs (gdbarch
)) % 2 == 0)
6094 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
6095 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
6098 fprintf_filtered (file
, " dbl: ");
6100 fprintf_filtered (file
, "<invalid double>");
6102 fprintf_filtered (file
, "%-24.17g", doub
);
6107 struct value_print_options opts
;
6109 /* Eight byte registers: print each one as hex, float and double. */
6110 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
6111 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
6114 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
6115 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
6118 get_formatted_print_options (&opts
, 'x');
6119 print_scalar_formatted (raw_buffer
,
6120 builtin_type (gdbarch
)->builtin_uint64
,
6123 fprintf_filtered (file
, " flt: ");
6125 fprintf_filtered (file
, "<invalid float>");
6127 fprintf_filtered (file
, "%-17.9g", flt1
);
6129 fprintf_filtered (file
, " dbl: ");
6131 fprintf_filtered (file
, "<invalid double>");
6133 fprintf_filtered (file
, "%-24.17g", doub
);
6138 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
6141 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6142 struct value_print_options opts
;
6145 if (mips_float_register_p (gdbarch
, regnum
))
6147 mips_print_fp_register (file
, frame
, regnum
);
6151 val
= get_frame_register_value (frame
, regnum
);
6152 if (value_optimized_out (val
))
6154 fprintf_filtered (file
, "%s: [Invalid]",
6155 gdbarch_register_name (gdbarch
, regnum
));
6159 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
6161 /* The problem with printing numeric register names (r26, etc.) is that
6162 the user can't use them on input. Probably the best solution is to
6163 fix it so that either the numeric or the funky (a2, etc.) names
6164 are accepted on input. */
6165 if (regnum
< MIPS_NUMREGS
)
6166 fprintf_filtered (file
, "(r%d): ", regnum
);
6168 fprintf_filtered (file
, ": ");
6170 get_formatted_print_options (&opts
, 'x');
6171 val_print_scalar_formatted (value_type (val
),
6172 value_contents_for_printing (val
),
6173 value_embedded_offset (val
),
6178 /* Replacement for generic do_registers_info.
6179 Print regs in pretty columns. */
6182 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
6185 fprintf_filtered (file
, " ");
6186 mips_print_fp_register (file
, frame
, regnum
);
6187 fprintf_filtered (file
, "\n");
6192 /* Print a row's worth of GP (int) registers, with name labels above. */
6195 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
6198 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6199 /* Do values for GP (int) regs. */
6200 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
6201 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols
6206 /* For GP registers, we print a separate row of names above the vals. */
6207 for (col
= 0, regnum
= start_regnum
;
6208 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
6209 + gdbarch_num_pseudo_regs (gdbarch
);
6212 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
6213 continue; /* unused register */
6214 if (mips_float_register_p (gdbarch
, regnum
))
6215 break; /* End the row: reached FP register. */
6216 /* Large registers are handled separately. */
6217 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
6220 break; /* End the row before this register. */
6222 /* Print this register on a row by itself. */
6223 mips_print_register (file
, frame
, regnum
);
6224 fprintf_filtered (file
, "\n");
6228 fprintf_filtered (file
, " ");
6229 fprintf_filtered (file
,
6230 mips_abi_regsize (gdbarch
) == 8 ? "%17s" : "%9s",
6231 gdbarch_register_name (gdbarch
, regnum
));
6238 /* Print the R0 to R31 names. */
6239 if ((start_regnum
% gdbarch_num_regs (gdbarch
)) < MIPS_NUMREGS
)
6240 fprintf_filtered (file
, "\n R%-4d",
6241 start_regnum
% gdbarch_num_regs (gdbarch
));
6243 fprintf_filtered (file
, "\n ");
6245 /* Now print the values in hex, 4 or 8 to the row. */
6246 for (col
= 0, regnum
= start_regnum
;
6247 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
6248 + gdbarch_num_pseudo_regs (gdbarch
);
6251 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
6252 continue; /* unused register */
6253 if (mips_float_register_p (gdbarch
, regnum
))
6254 break; /* End row: reached FP register. */
6255 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
6256 break; /* End row: large register. */
6258 /* OK: get the data in raw format. */
6259 if (!frame_register_read (frame
, regnum
, raw_buffer
))
6260 error (_("can't read register %d (%s)"),
6261 regnum
, gdbarch_register_name (gdbarch
, regnum
));
6262 /* pad small registers */
6264 byte
< (mips_abi_regsize (gdbarch
)
6265 - register_size (gdbarch
, regnum
)); byte
++)
6266 printf_filtered (" ");
6267 /* Now print the register value in hex, endian order. */
6268 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6270 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
6271 byte
< register_size (gdbarch
, regnum
); byte
++)
6272 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
6274 for (byte
= register_size (gdbarch
, regnum
) - 1;
6276 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
6277 fprintf_filtered (file
, " ");
6280 if (col
> 0) /* ie. if we actually printed anything... */
6281 fprintf_filtered (file
, "\n");
6286 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */
6289 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
6290 struct frame_info
*frame
, int regnum
, int all
)
6292 if (regnum
!= -1) /* Do one specified register. */
6294 gdb_assert (regnum
>= gdbarch_num_regs (gdbarch
));
6295 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
6296 error (_("Not a valid register for the current processor type"));
6298 mips_print_register (file
, frame
, regnum
);
6299 fprintf_filtered (file
, "\n");
6302 /* Do all (or most) registers. */
6304 regnum
= gdbarch_num_regs (gdbarch
);
6305 while (regnum
< gdbarch_num_regs (gdbarch
)
6306 + gdbarch_num_pseudo_regs (gdbarch
))
6308 if (mips_float_register_p (gdbarch
, regnum
))
6310 if (all
) /* True for "INFO ALL-REGISTERS" command. */
6311 regnum
= print_fp_register_row (file
, frame
, regnum
);
6313 regnum
+= MIPS_NUMREGS
; /* Skip floating point regs. */
6316 regnum
= print_gp_register_row (file
, frame
, regnum
);
6322 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
6323 struct frame_info
*frame
)
6325 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
6326 CORE_ADDR pc
= get_frame_pc (frame
);
6327 struct address_space
*aspace
;
6333 if ((mips_pc_is_mips (pc
)
6334 && !mips32_instruction_has_delay_slot (gdbarch
, pc
))
6335 || (mips_pc_is_micromips (gdbarch
, pc
)
6336 && !micromips_instruction_has_delay_slot (gdbarch
, pc
, 0))
6337 || (mips_pc_is_mips16 (gdbarch
, pc
)
6338 && !mips16_instruction_has_delay_slot (gdbarch
, pc
, 0)))
6341 isa
= mips_pc_isa (gdbarch
, pc
);
6342 /* _has_delay_slot above will have validated the read. */
6343 insn
= mips_fetch_instruction (gdbarch
, isa
, pc
, NULL
);
6344 size
= mips_insn_size (isa
, insn
);
6345 aspace
= get_frame_address_space (frame
);
6346 return breakpoint_here_p (aspace
, pc
+ size
) != no_breakpoint_here
;
6349 /* To skip prologues, I use this predicate. Returns either PC itself
6350 if the code at PC does not look like a function prologue; otherwise
6351 returns an address that (if we're lucky) follows the prologue. If
6352 LENIENT, then we must skip everything which is involved in setting
6353 up the frame (it's OK to skip more, just so long as we don't skip
6354 anything which might clobber the registers which are being saved.
6355 We must skip more in the case where part of the prologue is in the
6356 delay slot of a non-prologue instruction). */
6359 mips_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6362 CORE_ADDR func_addr
;
6364 /* See if we can determine the end of the prologue via the symbol table.
6365 If so, then return either PC, or the PC after the prologue, whichever
6367 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
6369 CORE_ADDR post_prologue_pc
6370 = skip_prologue_using_sal (gdbarch
, func_addr
);
6371 if (post_prologue_pc
!= 0)
6372 return max (pc
, post_prologue_pc
);
6375 /* Can't determine prologue from the symbol table, need to examine
6378 /* Find an upper limit on the function prologue using the debug
6379 information. If the debug information could not be used to provide
6380 that bound, then use an arbitrary large number as the upper bound. */
6381 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
6383 limit_pc
= pc
+ 100; /* Magic. */
6385 if (mips_pc_is_mips16 (gdbarch
, pc
))
6386 return mips16_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6387 else if (mips_pc_is_micromips (gdbarch
, pc
))
6388 return micromips_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6390 return mips32_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6393 /* Check whether the PC is in a function epilogue (32-bit version).
6394 This is a helper function for mips_in_function_epilogue_p. */
6396 mips32_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6398 CORE_ADDR func_addr
= 0, func_end
= 0;
6400 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6402 /* The MIPS epilogue is max. 12 bytes long. */
6403 CORE_ADDR addr
= func_end
- 12;
6405 if (addr
< func_addr
+ 4)
6406 addr
= func_addr
+ 4;
6410 for (; pc
< func_end
; pc
+= MIPS_INSN32_SIZE
)
6412 unsigned long high_word
;
6415 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
6416 high_word
= (inst
>> 16) & 0xffff;
6418 if (high_word
!= 0x27bd /* addiu $sp,$sp,offset */
6419 && high_word
!= 0x67bd /* daddiu $sp,$sp,offset */
6420 && inst
!= 0x03e00008 /* jr $ra */
6421 && inst
!= 0x00000000) /* nop */
6431 /* Check whether the PC is in a function epilogue (microMIPS version).
6432 This is a helper function for mips_in_function_epilogue_p. */
6435 micromips_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6437 CORE_ADDR func_addr
= 0;
6438 CORE_ADDR func_end
= 0;
6446 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6449 /* The microMIPS epilogue is max. 12 bytes long. */
6450 addr
= func_end
- 12;
6452 if (addr
< func_addr
+ 2)
6453 addr
= func_addr
+ 2;
6457 for (; pc
< func_end
; pc
+= loc
)
6460 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
6461 loc
+= MIPS_INSN16_SIZE
;
6462 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
6464 /* 48-bit instructions. */
6465 case 3 * MIPS_INSN16_SIZE
:
6466 /* No epilogue instructions in this category. */
6469 /* 32-bit instructions. */
6470 case 2 * MIPS_INSN16_SIZE
:
6472 insn
|= mips_fetch_instruction (gdbarch
,
6473 ISA_MICROMIPS
, pc
+ loc
, NULL
);
6474 loc
+= MIPS_INSN16_SIZE
;
6475 switch (micromips_op (insn
>> 16))
6477 case 0xc: /* ADDIU: bits 001100 */
6478 case 0x17: /* DADDIU: bits 010111 */
6479 sreg
= b0s5_reg (insn
>> 16);
6480 dreg
= b5s5_reg (insn
>> 16);
6481 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
6482 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
6483 /* (D)ADDIU $sp, imm */
6493 /* 16-bit instructions. */
6494 case MIPS_INSN16_SIZE
:
6495 switch (micromips_op (insn
))
6497 case 0x3: /* MOVE: bits 000011 */
6498 sreg
= b0s5_reg (insn
);
6499 dreg
= b5s5_reg (insn
);
6500 if (sreg
== 0 && dreg
== 0)
6501 /* MOVE $zero, $zero aka NOP */
6505 case 0x11: /* POOL16C: bits 010001 */
6506 if (b5s5_op (insn
) == 0x18
6507 /* JRADDIUSP: bits 010011 11000 */
6508 || (b5s5_op (insn
) == 0xd
6509 /* JRC: bits 010011 01101 */
6510 && b0s5_reg (insn
) == MIPS_RA_REGNUM
))
6515 case 0x13: /* POOL16D: bits 010011 */
6516 offset
= micromips_decode_imm9 (b1s9_imm (insn
));
6517 if ((insn
& 0x1) == 0x1
6518 /* ADDIUSP: bits 010011 1 */
6532 /* Check whether the PC is in a function epilogue (16-bit version).
6533 This is a helper function for mips_in_function_epilogue_p. */
6535 mips16_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6537 CORE_ADDR func_addr
= 0, func_end
= 0;
6539 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6541 /* The MIPS epilogue is max. 12 bytes long. */
6542 CORE_ADDR addr
= func_end
- 12;
6544 if (addr
< func_addr
+ 4)
6545 addr
= func_addr
+ 4;
6549 for (; pc
< func_end
; pc
+= MIPS_INSN16_SIZE
)
6551 unsigned short inst
;
6553 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, pc
, NULL
);
6555 if ((inst
& 0xf800) == 0xf000) /* extend */
6558 if (inst
!= 0x6300 /* addiu $sp,offset */
6559 && inst
!= 0xfb00 /* daddiu $sp,$sp,offset */
6560 && inst
!= 0xe820 /* jr $ra */
6561 && inst
!= 0xe8a0 /* jrc $ra */
6562 && inst
!= 0x6500) /* nop */
6572 /* The epilogue is defined here as the area at the end of a function,
6573 after an instruction which destroys the function's stack frame. */
6575 mips_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6577 if (mips_pc_is_mips16 (gdbarch
, pc
))
6578 return mips16_in_function_epilogue_p (gdbarch
, pc
);
6579 else if (mips_pc_is_micromips (gdbarch
, pc
))
6580 return micromips_in_function_epilogue_p (gdbarch
, pc
);
6582 return mips32_in_function_epilogue_p (gdbarch
, pc
);
6585 /* Root of all "set mips "/"show mips " commands. This will eventually be
6586 used for all MIPS-specific commands. */
6589 show_mips_command (char *args
, int from_tty
)
6591 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
6595 set_mips_command (char *args
, int from_tty
)
6598 ("\"set mips\" must be followed by an appropriate subcommand.\n");
6599 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
6602 /* Commands to show/set the MIPS FPU type. */
6605 show_mipsfpu_command (char *args
, int from_tty
)
6609 if (gdbarch_bfd_arch_info (target_gdbarch
)->arch
!= bfd_arch_mips
)
6612 ("The MIPS floating-point coprocessor is unknown "
6613 "because the current architecture is not MIPS.\n");
6617 switch (MIPS_FPU_TYPE (target_gdbarch
))
6619 case MIPS_FPU_SINGLE
:
6620 fpu
= "single-precision";
6622 case MIPS_FPU_DOUBLE
:
6623 fpu
= "double-precision";
6626 fpu
= "absent (none)";
6629 internal_error (__FILE__
, __LINE__
, _("bad switch"));
6631 if (mips_fpu_type_auto
)
6632 printf_unfiltered ("The MIPS floating-point coprocessor "
6633 "is set automatically (currently %s)\n",
6637 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
6642 set_mipsfpu_command (char *args
, int from_tty
)
6644 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", "
6645 "\"single\",\"none\" or \"auto\".\n");
6646 show_mipsfpu_command (args
, from_tty
);
6650 set_mipsfpu_single_command (char *args
, int from_tty
)
6652 struct gdbarch_info info
;
6653 gdbarch_info_init (&info
);
6654 mips_fpu_type
= MIPS_FPU_SINGLE
;
6655 mips_fpu_type_auto
= 0;
6656 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6657 instead of relying on globals. Doing that would let generic code
6658 handle the search for this specific architecture. */
6659 if (!gdbarch_update_p (info
))
6660 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6664 set_mipsfpu_double_command (char *args
, int from_tty
)
6666 struct gdbarch_info info
;
6667 gdbarch_info_init (&info
);
6668 mips_fpu_type
= MIPS_FPU_DOUBLE
;
6669 mips_fpu_type_auto
= 0;
6670 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6671 instead of relying on globals. Doing that would let generic code
6672 handle the search for this specific architecture. */
6673 if (!gdbarch_update_p (info
))
6674 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6678 set_mipsfpu_none_command (char *args
, int from_tty
)
6680 struct gdbarch_info info
;
6681 gdbarch_info_init (&info
);
6682 mips_fpu_type
= MIPS_FPU_NONE
;
6683 mips_fpu_type_auto
= 0;
6684 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6685 instead of relying on globals. Doing that would let generic code
6686 handle the search for this specific architecture. */
6687 if (!gdbarch_update_p (info
))
6688 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6692 set_mipsfpu_auto_command (char *args
, int from_tty
)
6694 mips_fpu_type_auto
= 1;
6697 /* Attempt to identify the particular processor model by reading the
6698 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
6699 the relevant processor still exists (it dates back to '94) and
6700 secondly this is not the way to do this. The processor type should
6701 be set by forcing an architecture change. */
6704 deprecated_mips_set_processor_regs_hack (void)
6706 struct regcache
*regcache
= get_current_regcache ();
6707 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
6708 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
6711 regcache_cooked_read_unsigned (regcache
, MIPS_PRID_REGNUM
, &prid
);
6712 if ((prid
& ~0xf) == 0x700)
6713 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
6716 /* Just like reinit_frame_cache, but with the right arguments to be
6717 callable as an sfunc. */
6720 reinit_frame_cache_sfunc (char *args
, int from_tty
,
6721 struct cmd_list_element
*c
)
6723 reinit_frame_cache ();
6727 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
6729 struct gdbarch
*gdbarch
= info
->application_data
;
6731 /* FIXME: cagney/2003-06-26: Is this even necessary? The
6732 disassembler needs to be able to locally determine the ISA, and
6733 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
6735 if (mips_pc_is_mips16 (gdbarch
, memaddr
))
6736 info
->mach
= bfd_mach_mips16
;
6737 else if (mips_pc_is_micromips (gdbarch
, memaddr
))
6738 info
->mach
= bfd_mach_mips_micromips
;
6740 /* Round down the instruction address to the appropriate boundary. */
6741 memaddr
&= (info
->mach
== bfd_mach_mips16
6742 || info
->mach
== bfd_mach_mips_micromips
) ? ~1 : ~3;
6744 /* Set the disassembler options. */
6745 if (!info
->disassembler_options
)
6746 /* This string is not recognized explicitly by the disassembler,
6747 but it tells the disassembler to not try to guess the ABI from
6748 the bfd elf headers, such that, if the user overrides the ABI
6749 of a program linked as NewABI, the disassembly will follow the
6750 register naming conventions specified by the user. */
6751 info
->disassembler_options
= "gpr-names=32";
6753 /* Call the appropriate disassembler based on the target endian-ness. */
6754 if (info
->endian
== BFD_ENDIAN_BIG
)
6755 return print_insn_big_mips (memaddr
, info
);
6757 return print_insn_little_mips (memaddr
, info
);
6761 gdb_print_insn_mips_n32 (bfd_vma memaddr
, struct disassemble_info
*info
)
6763 /* Set up the disassembler info, so that we get the right
6764 register names from libopcodes. */
6765 info
->disassembler_options
= "gpr-names=n32";
6766 info
->flavour
= bfd_target_elf_flavour
;
6768 return gdb_print_insn_mips (memaddr
, info
);
6772 gdb_print_insn_mips_n64 (bfd_vma memaddr
, struct disassemble_info
*info
)
6774 /* Set up the disassembler info, so that we get the right
6775 register names from libopcodes. */
6776 info
->disassembler_options
= "gpr-names=64";
6777 info
->flavour
= bfd_target_elf_flavour
;
6779 return gdb_print_insn_mips (memaddr
, info
);
6782 /* This function implements gdbarch_breakpoint_from_pc. It uses the
6783 program counter value to determine whether a 16- or 32-bit breakpoint
6784 should be used. It returns a pointer to a string of bytes that encode a
6785 breakpoint instruction, stores the length of the string to *lenptr, and
6786 adjusts pc (if necessary) to point to the actual memory location where
6787 the breakpoint should be inserted. */
6789 static const gdb_byte
*
6790 mips_breakpoint_from_pc (struct gdbarch
*gdbarch
,
6791 CORE_ADDR
*pcptr
, int *lenptr
)
6793 CORE_ADDR pc
= *pcptr
;
6795 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6797 if (mips_pc_is_mips16 (gdbarch
, pc
))
6799 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
6800 *pcptr
= unmake_compact_addr (pc
);
6801 *lenptr
= sizeof (mips16_big_breakpoint
);
6802 return mips16_big_breakpoint
;
6804 else if (mips_pc_is_micromips (gdbarch
, pc
))
6806 static gdb_byte micromips16_big_breakpoint
[] = { 0x46, 0x85 };
6807 static gdb_byte micromips32_big_breakpoint
[] = { 0, 0x5, 0, 0x7 };
6812 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, &status
);
6814 : mips_insn_size (ISA_MICROMIPS
, insn
) == 2 ? 2 : 4;
6815 *pcptr
= unmake_compact_addr (pc
);
6817 return (size
== 2) ? micromips16_big_breakpoint
6818 : micromips32_big_breakpoint
;
6822 /* The IDT board uses an unusual breakpoint value, and
6823 sometimes gets confused when it sees the usual MIPS
6824 breakpoint instruction. */
6825 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
6826 static gdb_byte pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
6827 static gdb_byte idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
6828 /* Likewise, IRIX appears to expect a different breakpoint,
6829 although this is not apparent until you try to use pthreads. */
6830 static gdb_byte irix_big_breakpoint
[] = { 0, 0, 0, 0xd };
6832 *lenptr
= sizeof (big_breakpoint
);
6834 if (strcmp (target_shortname
, "mips") == 0)
6835 return idt_big_breakpoint
;
6836 else if (strcmp (target_shortname
, "ddb") == 0
6837 || strcmp (target_shortname
, "pmon") == 0
6838 || strcmp (target_shortname
, "lsi") == 0)
6839 return pmon_big_breakpoint
;
6840 else if (gdbarch_osabi (gdbarch
) == GDB_OSABI_IRIX
)
6841 return irix_big_breakpoint
;
6843 return big_breakpoint
;
6848 if (mips_pc_is_mips16 (gdbarch
, pc
))
6850 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
6851 *pcptr
= unmake_compact_addr (pc
);
6852 *lenptr
= sizeof (mips16_little_breakpoint
);
6853 return mips16_little_breakpoint
;
6855 else if (mips_pc_is_micromips (gdbarch
, pc
))
6857 static gdb_byte micromips16_little_breakpoint
[] = { 0x85, 0x46 };
6858 static gdb_byte micromips32_little_breakpoint
[] = { 0x5, 0, 0x7, 0 };
6863 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, &status
);
6865 : mips_insn_size (ISA_MICROMIPS
, insn
) == 2 ? 2 : 4;
6866 *pcptr
= unmake_compact_addr (pc
);
6868 return (size
== 2) ? micromips16_little_breakpoint
6869 : micromips32_little_breakpoint
;
6873 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
6874 static gdb_byte pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
6875 static gdb_byte idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
6877 *lenptr
= sizeof (little_breakpoint
);
6879 if (strcmp (target_shortname
, "mips") == 0)
6880 return idt_little_breakpoint
;
6881 else if (strcmp (target_shortname
, "ddb") == 0
6882 || strcmp (target_shortname
, "pmon") == 0
6883 || strcmp (target_shortname
, "lsi") == 0)
6884 return pmon_little_breakpoint
;
6886 return little_breakpoint
;
6891 /* Determine the remote breakpoint kind suitable for the PC. The following
6894 * 2 -- 16-bit MIPS16 mode breakpoint,
6896 * 3 -- 16-bit microMIPS mode breakpoint,
6898 * 4 -- 32-bit standard MIPS mode breakpoint,
6900 * 5 -- 32-bit microMIPS mode breakpoint. */
6903 mips_remote_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
,
6906 CORE_ADDR pc
= *pcptr
;
6908 if (mips_pc_is_mips16 (gdbarch
, pc
))
6910 *pcptr
= unmake_compact_addr (pc
);
6913 else if (mips_pc_is_micromips (gdbarch
, pc
))
6919 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, &status
);
6920 size
= status
? 2 : mips_insn_size (ISA_MICROMIPS
, insn
) == 2 ? 2 : 4;
6921 *pcptr
= unmake_compact_addr (pc
);
6922 *kindptr
= size
| 1;
6928 /* Return non-zero if the ADDR instruction has a branch delay slot
6929 (i.e. it is a jump or branch instruction). This function is based
6930 on mips32_next_pc. */
6933 mips32_instruction_has_delay_slot (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
6941 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, addr
, &status
);
6945 op
= itype_op (inst
);
6946 if ((inst
& 0xe0000000) != 0)
6948 rs
= itype_rs (inst
);
6949 rt
= itype_rt (inst
);
6950 return (op
>> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
6951 || op
== 29 /* JALX: bits 011101 */
6954 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
6955 || (rs
== 9 && (rt
& 0x2) == 0)
6956 /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */
6957 || (rs
== 10 && (rt
& 0x2) == 0))));
6958 /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */
6961 switch (op
& 0x07) /* extract bits 28,27,26 */
6963 case 0: /* SPECIAL */
6964 op
= rtype_funct (inst
);
6965 return (op
== 8 /* JR */
6966 || op
== 9); /* JALR */
6967 break; /* end SPECIAL */
6968 case 1: /* REGIMM */
6969 rs
= itype_rs (inst
);
6970 rt
= itype_rt (inst
); /* branch condition */
6971 return ((rt
& 0xc) == 0
6972 /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */
6973 /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */
6974 || ((rt
& 0x1e) == 0x1c && rs
== 0));
6975 /* BPOSGE32, BPOSGE64: bits 1110x */
6976 break; /* end REGIMM */
6977 default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */
6983 /* Return non-zero if the ADDR instruction, which must be a 32-bit
6984 instruction if MUSTBE32 is set or can be any instruction otherwise,
6985 has a branch delay slot (i.e. it is a non-compact jump instruction). */
6988 micromips_instruction_has_delay_slot (struct gdbarch
*gdbarch
,
6989 CORE_ADDR addr
, int mustbe32
)
6994 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, addr
, &status
);
6998 if (!mustbe32
) /* 16-bit instructions. */
6999 return (micromips_op (insn
) == 0x11
7000 /* POOL16C: bits 010001 */
7001 && (b5s5_op (insn
) == 0xc
7002 /* JR16: bits 010001 01100 */
7003 || (b5s5_op (insn
) & 0x1e) == 0xe))
7004 /* JALR16, JALRS16: bits 010001 0111x */
7005 || (micromips_op (insn
) & 0x37) == 0x23
7006 /* BEQZ16, BNEZ16: bits 10x011 */
7007 || micromips_op (insn
) == 0x33;
7008 /* B16: bits 110011 */
7010 /* 32-bit instructions. */
7011 if (micromips_op (insn
) == 0x0)
7012 /* POOL32A: bits 000000 */
7015 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, addr
, &status
);
7018 return b0s6_op (insn
) == 0x3c
7019 /* POOL32Axf: bits 000000 ... 111100 */
7020 && (b6s10_ext (insn
) & 0x2bf) == 0x3c;
7021 /* JALR, JALR.HB: 000000 000x111100 111100 */
7022 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
7025 return (micromips_op (insn
) == 0x10
7026 /* POOL32I: bits 010000 */
7027 && ((b5s5_op (insn
) & 0x1c) == 0x0
7028 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
7029 || (b5s5_op (insn
) & 0x1d) == 0x4
7030 /* BLEZ, BGTZ: bits 010000 001x0 */
7031 || (b5s5_op (insn
) & 0x1d) == 0x11
7032 /* BLTZALS, BGEZALS: bits 010000 100x1 */
7033 || ((b5s5_op (insn
) & 0x1e) == 0x14
7034 && (insn
& 0x3) == 0x0)
7035 /* BC2F, BC2T: bits 010000 1010x xxx00 */
7036 || (b5s5_op (insn
) & 0x1e) == 0x1a
7037 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
7038 || ((b5s5_op (insn
) & 0x1e) == 0x1c
7039 && (insn
& 0x3) == 0x0)
7040 /* BC1F, BC1T: bits 010000 1110x xxx00 */
7041 || ((b5s5_op (insn
) & 0x1c) == 0x1c
7042 && (insn
& 0x3) == 0x1)))
7043 /* BC1ANY*: bits 010000 111xx xxx01 */
7044 || (micromips_op (insn
) & 0x1f) == 0x1d
7045 /* JALS, JAL: bits x11101 */
7046 || (micromips_op (insn
) & 0x37) == 0x25
7047 /* BEQ, BNE: bits 10x101 */
7048 || micromips_op (insn
) == 0x35
7049 /* J: bits 110101 */
7050 || micromips_op (insn
) == 0x3c;
7051 /* JALX: bits 111100 */
7055 mips16_instruction_has_delay_slot (struct gdbarch
*gdbarch
, CORE_ADDR addr
,
7058 unsigned short inst
;
7061 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, addr
, &status
);
7066 return (inst
& 0xf89f) == 0xe800; /* JR/JALR (16-bit instruction) */
7067 return (inst
& 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */
7070 /* Calculate the starting address of the MIPS memory segment BPADDR is in.
7071 This assumes KSSEG exists. */
7074 mips_segment_boundary (CORE_ADDR bpaddr
)
7076 CORE_ADDR mask
= CORE_ADDR_MAX
;
7079 if (sizeof (CORE_ADDR
) == 8)
7080 /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid
7081 a compiler warning produced where CORE_ADDR is a 32-bit type even
7082 though in that case this is dead code). */
7083 switch (bpaddr
>> ((sizeof (CORE_ADDR
) << 3) - 2) & 3)
7086 if (bpaddr
== (bfd_signed_vma
) (int32_t) bpaddr
)
7087 segsize
= 29; /* 32-bit compatibility segment */
7089 segsize
= 62; /* xkseg */
7091 case 2: /* xkphys */
7094 default: /* xksseg (1), xkuseg/kuseg (0) */
7098 else if (bpaddr
& 0x80000000) /* kernel segment */
7101 segsize
= 31; /* user segment */
7103 return bpaddr
& mask
;
7106 /* Move the breakpoint at BPADDR out of any branch delay slot by shifting
7107 it backwards if necessary. Return the address of the new location. */
7110 mips_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
7112 CORE_ADDR prev_addr
;
7114 CORE_ADDR func_addr
;
7116 /* If a breakpoint is set on the instruction in a branch delay slot,
7117 GDB gets confused. When the breakpoint is hit, the PC isn't on
7118 the instruction in the branch delay slot, the PC will point to
7119 the branch instruction. Since the PC doesn't match any known
7120 breakpoints, GDB reports a trap exception.
7122 There are two possible fixes for this problem.
7124 1) When the breakpoint gets hit, see if the BD bit is set in the
7125 Cause register (which indicates the last exception occurred in a
7126 branch delay slot). If the BD bit is set, fix the PC to point to
7127 the instruction in the branch delay slot.
7129 2) When the user sets the breakpoint, don't allow him to set the
7130 breakpoint on the instruction in the branch delay slot. Instead
7131 move the breakpoint to the branch instruction (which will have
7134 The problem with the first solution is that if the user then
7135 single-steps the processor, the branch instruction will get
7136 skipped (since GDB thinks the PC is on the instruction in the
7139 So, we'll use the second solution. To do this we need to know if
7140 the instruction we're trying to set the breakpoint on is in the
7141 branch delay slot. */
7143 boundary
= mips_segment_boundary (bpaddr
);
7145 /* Make sure we don't scan back before the beginning of the current
7146 function, since we may fetch constant data or insns that look like
7147 a jump. Of course we might do that anyway if the compiler has
7148 moved constants inline. :-( */
7149 if (find_pc_partial_function (bpaddr
, NULL
, &func_addr
, NULL
)
7150 && func_addr
> boundary
&& func_addr
<= bpaddr
)
7151 boundary
= func_addr
;
7153 if (mips_pc_is_mips (bpaddr
))
7155 if (bpaddr
== boundary
)
7158 /* If the previous instruction has a branch delay slot, we have
7159 to move the breakpoint to the branch instruction. */
7160 prev_addr
= bpaddr
- 4;
7161 if (mips32_instruction_has_delay_slot (gdbarch
, prev_addr
))
7166 int (*instruction_has_delay_slot
) (struct gdbarch
*, CORE_ADDR
, int);
7167 CORE_ADDR addr
, jmpaddr
;
7170 boundary
= unmake_compact_addr (boundary
);
7172 /* The only MIPS16 instructions with delay slots are JAL, JALX,
7173 JALR and JR. An absolute JAL/JALX is always 4 bytes long,
7174 so try for that first, then try the 2 byte JALR/JR.
7175 The microMIPS ASE has a whole range of jumps and branches
7176 with delay slots, some of which take 4 bytes and some take
7177 2 bytes, so the idea is the same.
7178 FIXME: We have to assume that bpaddr is not the second half
7179 of an extended instruction. */
7180 instruction_has_delay_slot
= (mips_pc_is_micromips (gdbarch
, bpaddr
)
7181 ? micromips_instruction_has_delay_slot
7182 : mips16_instruction_has_delay_slot
);
7186 for (i
= 1; i
< 4; i
++)
7188 if (unmake_compact_addr (addr
) == boundary
)
7190 addr
-= MIPS_INSN16_SIZE
;
7191 if (i
== 1 && instruction_has_delay_slot (gdbarch
, addr
, 0))
7192 /* Looks like a JR/JALR at [target-1], but it could be
7193 the second word of a previous JAL/JALX, so record it
7194 and check back one more. */
7196 else if (i
> 1 && instruction_has_delay_slot (gdbarch
, addr
, 1))
7199 /* Looks like a JAL/JALX at [target-2], but it could also
7200 be the second word of a previous JAL/JALX, record it,
7201 and check back one more. */
7204 /* Looks like a JAL/JALX at [target-3], so any previously
7205 recorded JAL/JALX or JR/JALR must be wrong, because:
7208 -2: JAL-ext (can't be JAL/JALX)
7209 -1: bdslot (can't be JR/JALR)
7212 Of course it could be another JAL-ext which looks
7213 like a JAL, but in that case we'd have broken out
7214 of this loop at [target-2]:
7218 -2: bdslot (can't be jmp)
7225 /* Not a jump instruction: if we're at [target-1] this
7226 could be the second word of a JAL/JALX, so continue;
7227 otherwise we're done. */
7240 /* Return non-zero if SUFFIX is one of the numeric suffixes used for MIPS16
7241 call stubs, one of 1, 2, 5, 6, 9, 10, or, if ZERO is non-zero, also 0. */
7244 mips_is_stub_suffix (const char *suffix
, int zero
)
7249 return zero
&& suffix
[1] == '\0';
7251 return suffix
[1] == '\0' || (suffix
[1] == '0' && suffix
[2] == '\0');
7256 return suffix
[1] == '\0';
7262 /* Return non-zero if MODE is one of the mode infixes used for MIPS16
7263 call stubs, one of sf, df, sc, or dc. */
7266 mips_is_stub_mode (const char *mode
)
7268 return ((mode
[0] == 's' || mode
[0] == 'd')
7269 && (mode
[1] == 'f' || mode
[1] == 'c'));
7272 /* Code at PC is a compiler-generated stub. Such a stub for a function
7273 bar might have a name like __fn_stub_bar, and might look like this:
7280 followed by (or interspersed with):
7287 addiu $25, $25, %lo(bar)
7290 ($1 may be used in old code; for robustness we accept any register)
7293 lui $28, %hi(_gp_disp)
7294 addiu $28, $28, %lo(_gp_disp)
7297 addiu $25, $25, %lo(bar)
7300 In the case of a __call_stub_bar stub, the sequence to set up
7301 arguments might look like this:
7308 followed by (or interspersed with) one of the jump sequences above.
7310 In the case of a __call_stub_fp_bar stub, JAL or JALR is used instead
7311 of J or JR, respectively, followed by:
7317 We are at the beginning of the stub here, and scan down and extract
7318 the target address from the jump immediate instruction or, if a jump
7319 register instruction is used, from the register referred. Return
7320 the value of PC calculated or 0 if inconclusive.
7322 The limit on the search is arbitrarily set to 20 instructions. FIXME. */
7325 mips_get_mips16_fn_stub_pc (struct frame_info
*frame
, CORE_ADDR pc
)
7327 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7328 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7329 int addrreg
= MIPS_ZERO_REGNUM
;
7330 CORE_ADDR start_pc
= pc
;
7331 CORE_ADDR target_pc
= 0;
7338 status
== 0 && target_pc
== 0 && i
< 20;
7339 i
++, pc
+= MIPS_INSN32_SIZE
)
7341 ULONGEST inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
7347 switch (itype_op (inst
))
7349 case 0: /* SPECIAL */
7350 switch (rtype_funct (inst
))
7354 rs
= rtype_rs (inst
);
7355 if (rs
== MIPS_GP_REGNUM
)
7356 target_pc
= gp
; /* Hmm... */
7357 else if (rs
== addrreg
)
7361 case 0x21: /* ADDU */
7362 rt
= rtype_rt (inst
);
7363 rs
= rtype_rs (inst
);
7364 rd
= rtype_rd (inst
);
7365 if (rd
== MIPS_GP_REGNUM
7366 && ((rs
== MIPS_GP_REGNUM
&& rt
== MIPS_T9_REGNUM
)
7367 || (rs
== MIPS_T9_REGNUM
&& rt
== MIPS_GP_REGNUM
)))
7375 target_pc
= jtype_target (inst
) << 2;
7376 target_pc
+= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
7380 rt
= itype_rt (inst
);
7381 rs
= itype_rs (inst
);
7384 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
7385 if (rt
== MIPS_GP_REGNUM
)
7387 else if (rt
== addrreg
)
7393 rt
= itype_rt (inst
);
7394 imm
= ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 16;
7395 if (rt
== MIPS_GP_REGNUM
)
7397 else if (rt
!= MIPS_ZERO_REGNUM
)
7405 rt
= itype_rt (inst
);
7406 rs
= itype_rs (inst
);
7407 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
7408 if (gp
!= 0 && rs
== MIPS_GP_REGNUM
)
7412 memset (buf
, 0, sizeof (buf
));
7413 status
= target_read_memory (gp
+ imm
, buf
, sizeof (buf
));
7415 addr
= extract_signed_integer (buf
, sizeof (buf
), byte_order
);
7424 /* If PC is in a MIPS16 call or return stub, return the address of the
7425 target PC, which is either the callee or the caller. There are several
7426 cases which must be handled:
7428 * If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7429 and the target PC is in $31 ($ra).
7430 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7431 and the target PC is in $2.
7432 * If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7433 i.e. before the JALR instruction, this is effectively a call stub
7434 and the target PC is in $2. Otherwise this is effectively
7435 a return stub and the target PC is in $18.
7436 * If the PC is at the start of __call_stub_fp_*, i.e. before the
7437 JAL or JALR instruction, this is effectively a call stub and the
7438 target PC is buried in the instruction stream. Otherwise this
7439 is effectively a return stub and the target PC is in $18.
7440 * If the PC is in __call_stub_* or in __fn_stub_*, this is a call
7441 stub and the target PC is buried in the instruction stream.
7443 See the source code for the stubs in gcc/config/mips/mips16.S, or the
7444 stub builder in gcc/config/mips/mips.c (mips16_build_call_stub) for the
7448 mips_skip_mips16_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7450 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7451 CORE_ADDR start_addr
;
7455 /* Find the starting address and name of the function containing the PC. */
7456 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
7459 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7460 and the target PC is in $31 ($ra). */
7461 prefixlen
= strlen (mips_str_mips16_ret_stub
);
7462 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
7463 && mips_is_stub_mode (name
+ prefixlen
)
7464 && name
[prefixlen
+ 2] == '\0')
7465 return get_frame_register_signed
7466 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
7468 /* If the PC is in __mips16_call_stub_*, this is one of the call
7469 call/return stubs. */
7470 prefixlen
= strlen (mips_str_mips16_call_stub
);
7471 if (strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0)
7473 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7474 and the target PC is in $2. */
7475 if (mips_is_stub_suffix (name
+ prefixlen
, 0))
7476 return get_frame_register_signed
7477 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
7479 /* If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7480 i.e. before the JALR instruction, this is effectively a call stub
7481 and the target PC is in $2. Otherwise this is effectively
7482 a return stub and the target PC is in $18. */
7483 else if (mips_is_stub_mode (name
+ prefixlen
)
7484 && name
[prefixlen
+ 2] == '_'
7485 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 0))
7487 if (pc
== start_addr
)
7488 /* This is the 'call' part of a call stub. The return
7489 address is in $2. */
7490 return get_frame_register_signed
7491 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
7493 /* This is the 'return' part of a call stub. The return
7494 address is in $18. */
7495 return get_frame_register_signed
7496 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
7499 return 0; /* Not a stub. */
7502 /* If the PC is in __call_stub_* or __fn_stub*, this is one of the
7503 compiler-generated call or call/return stubs. */
7504 if (strncmp (name
, mips_str_fn_stub
, strlen (mips_str_fn_stub
)) == 0
7505 || strncmp (name
, mips_str_call_stub
, strlen (mips_str_call_stub
)) == 0)
7507 if (pc
== start_addr
)
7508 /* This is the 'call' part of a call stub. Call this helper
7509 to scan through this code for interesting instructions
7510 and determine the final PC. */
7511 return mips_get_mips16_fn_stub_pc (frame
, pc
);
7513 /* This is the 'return' part of a call stub. The return address
7515 return get_frame_register_signed
7516 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
7519 return 0; /* Not a stub. */
7522 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
7523 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
7526 mips_in_return_stub (struct gdbarch
*gdbarch
, CORE_ADDR pc
, const char *name
)
7528 CORE_ADDR start_addr
;
7531 /* Find the starting address of the function containing the PC. */
7532 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
7535 /* If the PC is in __mips16_call_stub_{s,d}{f,c}_{0..10} but not at
7536 the start, i.e. after the JALR instruction, this is effectively
7538 prefixlen
= strlen (mips_str_mips16_call_stub
);
7539 if (pc
!= start_addr
7540 && strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0
7541 && mips_is_stub_mode (name
+ prefixlen
)
7542 && name
[prefixlen
+ 2] == '_'
7543 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 1))
7546 /* If the PC is in __call_stub_fp_* but not at the start, i.e. after
7547 the JAL or JALR instruction, this is effectively a return stub. */
7548 prefixlen
= strlen (mips_str_call_fp_stub
);
7549 if (pc
!= start_addr
7550 && strncmp (name
, mips_str_call_fp_stub
, prefixlen
) == 0)
7553 /* Consume the .pic. prefix of any PIC stub, this function must return
7554 true when the PC is in a PIC stub of a __mips16_ret_{d,s}{f,c} stub
7555 or the call stub path will trigger in handle_inferior_event causing
7557 prefixlen
= strlen (mips_str_pic
);
7558 if (strncmp (name
, mips_str_pic
, prefixlen
) == 0)
7561 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub. */
7562 prefixlen
= strlen (mips_str_mips16_ret_stub
);
7563 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
7564 && mips_is_stub_mode (name
+ prefixlen
)
7565 && name
[prefixlen
+ 2] == '\0')
7568 return 0; /* Not a stub. */
7571 /* If the current PC is the start of a non-PIC-to-PIC stub, return the
7572 PC of the stub target. The stub just loads $t9 and jumps to it,
7573 so that $t9 has the correct value at function entry. */
7576 mips_skip_pic_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7578 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7579 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7580 struct minimal_symbol
*msym
;
7582 gdb_byte stub_code
[16];
7583 int32_t stub_words
[4];
7585 /* The stub for foo is named ".pic.foo", and is either two
7586 instructions inserted before foo or a three instruction sequence
7587 which jumps to foo. */
7588 msym
= lookup_minimal_symbol_by_pc (pc
);
7590 || SYMBOL_VALUE_ADDRESS (msym
) != pc
7591 || SYMBOL_LINKAGE_NAME (msym
) == NULL
7592 || strncmp (SYMBOL_LINKAGE_NAME (msym
), ".pic.", 5) != 0)
7595 /* A two-instruction header. */
7596 if (MSYMBOL_SIZE (msym
) == 8)
7599 /* A three-instruction (plus delay slot) trampoline. */
7600 if (MSYMBOL_SIZE (msym
) == 16)
7602 if (target_read_memory (pc
, stub_code
, 16) != 0)
7604 for (i
= 0; i
< 4; i
++)
7605 stub_words
[i
] = extract_unsigned_integer (stub_code
+ i
* 4,
7608 /* A stub contains these instructions:
7611 addiu t9, t9, %lo(target)
7614 This works even for N64, since stubs are only generated with
7616 if ((stub_words
[0] & 0xffff0000U
) == 0x3c190000
7617 && (stub_words
[1] & 0xfc000000U
) == 0x08000000
7618 && (stub_words
[2] & 0xffff0000U
) == 0x27390000
7619 && stub_words
[3] == 0x00000000)
7620 return ((((stub_words
[0] & 0x0000ffff) << 16)
7621 + (stub_words
[2] & 0x0000ffff)) ^ 0x8000) - 0x8000;
7624 /* Not a recognized stub. */
7629 mips_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7631 CORE_ADDR requested_pc
= pc
;
7632 CORE_ADDR target_pc
;
7639 new_pc
= mips_skip_mips16_trampoline_code (frame
, pc
);
7643 if (is_compact_addr (pc
))
7644 pc
= unmake_compact_addr (pc
);
7647 new_pc
= find_solib_trampoline_target (frame
, pc
);
7651 if (is_compact_addr (pc
))
7652 pc
= unmake_compact_addr (pc
);
7655 new_pc
= mips_skip_pic_trampoline_code (frame
, pc
);
7659 if (is_compact_addr (pc
))
7660 pc
= unmake_compact_addr (pc
);
7663 while (pc
!= target_pc
);
7665 return pc
!= requested_pc
? pc
: 0;
7668 /* Convert a dbx stab register number (from `r' declaration) to a GDB
7669 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7672 mips_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
7675 if (num
>= 0 && num
< 32)
7677 else if (num
>= 38 && num
< 70)
7678 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 38;
7680 regnum
= mips_regnum (gdbarch
)->hi
;
7682 regnum
= mips_regnum (gdbarch
)->lo
;
7683 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 72 && num
< 78)
7684 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 72;
7686 /* This will hopefully (eventually) provoke a warning. Should
7687 we be calling complaint() here? */
7688 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
7689 return gdbarch_num_regs (gdbarch
) + regnum
;
7693 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
7694 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7697 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
7700 if (num
>= 0 && num
< 32)
7702 else if (num
>= 32 && num
< 64)
7703 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 32;
7705 regnum
= mips_regnum (gdbarch
)->hi
;
7707 regnum
= mips_regnum (gdbarch
)->lo
;
7708 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 66 && num
< 72)
7709 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 66;
7711 /* This will hopefully (eventually) provoke a warning. Should we
7712 be calling complaint() here? */
7713 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
7714 return gdbarch_num_regs (gdbarch
) + regnum
;
7718 mips_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
7720 /* Only makes sense to supply raw registers. */
7721 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
));
7722 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
7723 decide if it is valid. Should instead define a standard sim/gdb
7724 register numbering scheme. */
7725 if (gdbarch_register_name (gdbarch
,
7726 gdbarch_num_regs (gdbarch
) + regnum
) != NULL
7727 && gdbarch_register_name (gdbarch
,
7728 gdbarch_num_regs (gdbarch
)
7729 + regnum
)[0] != '\0')
7732 return LEGACY_SIM_REGNO_IGNORE
;
7736 /* Convert an integer into an address. Extracting the value signed
7737 guarantees a correctly sign extended address. */
7740 mips_integer_to_address (struct gdbarch
*gdbarch
,
7741 struct type
*type
, const gdb_byte
*buf
)
7743 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7744 return extract_signed_integer (buf
, TYPE_LENGTH (type
), byte_order
);
7747 /* Dummy virtual frame pointer method. This is no more or less accurate
7748 than most other architectures; we just need to be explicit about it,
7749 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
7750 an assertion failure. */
7753 mips_virtual_frame_pointer (struct gdbarch
*gdbarch
,
7754 CORE_ADDR pc
, int *reg
, LONGEST
*offset
)
7756 *reg
= MIPS_SP_REGNUM
;
7761 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
7763 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
7764 const char *name
= bfd_get_section_name (abfd
, sect
);
7766 if (*abip
!= MIPS_ABI_UNKNOWN
)
7769 if (strncmp (name
, ".mdebug.", 8) != 0)
7772 if (strcmp (name
, ".mdebug.abi32") == 0)
7773 *abip
= MIPS_ABI_O32
;
7774 else if (strcmp (name
, ".mdebug.abiN32") == 0)
7775 *abip
= MIPS_ABI_N32
;
7776 else if (strcmp (name
, ".mdebug.abi64") == 0)
7777 *abip
= MIPS_ABI_N64
;
7778 else if (strcmp (name
, ".mdebug.abiO64") == 0)
7779 *abip
= MIPS_ABI_O64
;
7780 else if (strcmp (name
, ".mdebug.eabi32") == 0)
7781 *abip
= MIPS_ABI_EABI32
;
7782 else if (strcmp (name
, ".mdebug.eabi64") == 0)
7783 *abip
= MIPS_ABI_EABI64
;
7785 warning (_("unsupported ABI %s."), name
+ 8);
7789 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
7791 int *lbp
= (int *) obj
;
7792 const char *name
= bfd_get_section_name (abfd
, sect
);
7794 if (strncmp (name
, ".gcc_compiled_long32", 20) == 0)
7796 else if (strncmp (name
, ".gcc_compiled_long64", 20) == 0)
7798 else if (strncmp (name
, ".gcc_compiled_long", 18) == 0)
7799 warning (_("unrecognized .gcc_compiled_longXX"));
7802 static enum mips_abi
7803 global_mips_abi (void)
7807 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
7808 if (mips_abi_strings
[i
] == mips_abi_string
)
7809 return (enum mips_abi
) i
;
7811 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
7814 /* Return the default compressed instruction set, either of MIPS16
7815 or microMIPS, selected when none could have been determined from
7816 the ELF header of the binary being executed (or no binary has been
7819 static enum mips_isa
7820 global_mips_compression (void)
7824 for (i
= 0; mips_compression_strings
[i
] != NULL
; i
++)
7825 if (mips_compression_strings
[i
] == mips_compression_string
)
7826 return (enum mips_isa
) i
;
7828 internal_error (__FILE__
, __LINE__
, _("unknown compressed ISA string"));
7832 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
7834 /* If the size matches the set of 32-bit or 64-bit integer registers,
7835 assume that's what we've got. */
7836 register_remote_g_packet_guess (gdbarch
, 38 * 4, mips_tdesc_gp32
);
7837 register_remote_g_packet_guess (gdbarch
, 38 * 8, mips_tdesc_gp64
);
7839 /* If the size matches the full set of registers GDB traditionally
7840 knows about, including floating point, for either 32-bit or
7841 64-bit, assume that's what we've got. */
7842 register_remote_g_packet_guess (gdbarch
, 90 * 4, mips_tdesc_gp32
);
7843 register_remote_g_packet_guess (gdbarch
, 90 * 8, mips_tdesc_gp64
);
7845 /* Otherwise we don't have a useful guess. */
7848 static struct value
*
7849 value_of_mips_user_reg (struct frame_info
*frame
, const void *baton
)
7851 const int *reg_p
= baton
;
7852 return value_of_register (*reg_p
, frame
);
7855 static struct gdbarch
*
7856 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
7858 struct gdbarch
*gdbarch
;
7859 struct gdbarch_tdep
*tdep
;
7861 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
7863 enum mips_fpu_type fpu_type
;
7864 struct tdesc_arch_data
*tdesc_data
= NULL
;
7865 int elf_fpu_type
= 0;
7866 const char **reg_names
;
7867 struct mips_regnum mips_regnum
, *regnum
;
7868 enum mips_isa mips_isa
;
7872 /* Fill in the OS dependent register numbers and names. */
7873 if (info
.osabi
== GDB_OSABI_IRIX
)
7875 mips_regnum
.fp0
= 32;
7876 mips_regnum
.pc
= 64;
7877 mips_regnum
.cause
= 65;
7878 mips_regnum
.badvaddr
= 66;
7879 mips_regnum
.hi
= 67;
7880 mips_regnum
.lo
= 68;
7881 mips_regnum
.fp_control_status
= 69;
7882 mips_regnum
.fp_implementation_revision
= 70;
7883 mips_regnum
.dspacc
= dspacc
= -1;
7884 mips_regnum
.dspctl
= dspctl
= -1;
7886 reg_names
= mips_irix_reg_names
;
7888 else if (info
.osabi
== GDB_OSABI_LINUX
)
7890 mips_regnum
.fp0
= 38;
7891 mips_regnum
.pc
= 37;
7892 mips_regnum
.cause
= 36;
7893 mips_regnum
.badvaddr
= 35;
7894 mips_regnum
.hi
= 34;
7895 mips_regnum
.lo
= 33;
7896 mips_regnum
.fp_control_status
= 70;
7897 mips_regnum
.fp_implementation_revision
= 71;
7898 mips_regnum
.dspacc
= -1;
7899 mips_regnum
.dspctl
= -1;
7903 reg_names
= mips_linux_reg_names
;
7907 mips_regnum
.lo
= MIPS_EMBED_LO_REGNUM
;
7908 mips_regnum
.hi
= MIPS_EMBED_HI_REGNUM
;
7909 mips_regnum
.badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
7910 mips_regnum
.cause
= MIPS_EMBED_CAUSE_REGNUM
;
7911 mips_regnum
.pc
= MIPS_EMBED_PC_REGNUM
;
7912 mips_regnum
.fp0
= MIPS_EMBED_FP0_REGNUM
;
7913 mips_regnum
.fp_control_status
= 70;
7914 mips_regnum
.fp_implementation_revision
= 71;
7915 mips_regnum
.dspacc
= dspacc
= -1;
7916 mips_regnum
.dspctl
= dspctl
= -1;
7917 num_regs
= MIPS_LAST_EMBED_REGNUM
+ 1;
7918 if (info
.bfd_arch_info
!= NULL
7919 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
7920 reg_names
= mips_tx39_reg_names
;
7922 reg_names
= mips_generic_reg_names
;
7925 /* Check any target description for validity. */
7926 if (tdesc_has_registers (info
.target_desc
))
7928 static const char *const mips_gprs
[] = {
7929 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
7930 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
7931 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
7932 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
7934 static const char *const mips_fprs
[] = {
7935 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
7936 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
7937 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
7938 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
7941 const struct tdesc_feature
*feature
;
7944 feature
= tdesc_find_feature (info
.target_desc
,
7945 "org.gnu.gdb.mips.cpu");
7946 if (feature
== NULL
)
7949 tdesc_data
= tdesc_data_alloc ();
7952 for (i
= MIPS_ZERO_REGNUM
; i
<= MIPS_RA_REGNUM
; i
++)
7953 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
7957 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
7958 mips_regnum
.lo
, "lo");
7959 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
7960 mips_regnum
.hi
, "hi");
7961 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
7962 mips_regnum
.pc
, "pc");
7966 tdesc_data_cleanup (tdesc_data
);
7970 feature
= tdesc_find_feature (info
.target_desc
,
7971 "org.gnu.gdb.mips.cp0");
7972 if (feature
== NULL
)
7974 tdesc_data_cleanup (tdesc_data
);
7979 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
7980 mips_regnum
.badvaddr
, "badvaddr");
7981 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
7982 MIPS_PS_REGNUM
, "status");
7983 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
7984 mips_regnum
.cause
, "cause");
7988 tdesc_data_cleanup (tdesc_data
);
7992 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
7993 backend is not prepared for that, though. */
7994 feature
= tdesc_find_feature (info
.target_desc
,
7995 "org.gnu.gdb.mips.fpu");
7996 if (feature
== NULL
)
7998 tdesc_data_cleanup (tdesc_data
);
8003 for (i
= 0; i
< 32; i
++)
8004 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8005 i
+ mips_regnum
.fp0
, mips_fprs
[i
]);
8007 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8008 mips_regnum
.fp_control_status
,
8011 &= tdesc_numbered_register (feature
, tdesc_data
,
8012 mips_regnum
.fp_implementation_revision
,
8017 tdesc_data_cleanup (tdesc_data
);
8023 feature
= tdesc_find_feature (info
.target_desc
,
8024 "org.gnu.gdb.mips.dsp");
8025 /* The DSP registers are optional; it's OK if they are absent. */
8026 if (feature
!= NULL
)
8030 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8031 dspacc
+ i
++, "hi1");
8032 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8033 dspacc
+ i
++, "lo1");
8034 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8035 dspacc
+ i
++, "hi2");
8036 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8037 dspacc
+ i
++, "lo2");
8038 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8039 dspacc
+ i
++, "hi3");
8040 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8041 dspacc
+ i
++, "lo3");
8043 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8048 tdesc_data_cleanup (tdesc_data
);
8052 mips_regnum
.dspacc
= dspacc
;
8053 mips_regnum
.dspctl
= dspctl
;
8057 /* It would be nice to detect an attempt to use a 64-bit ABI
8058 when only 32-bit registers are provided. */
8062 /* First of all, extract the elf_flags, if available. */
8063 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
8064 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
8065 else if (arches
!= NULL
)
8066 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
8070 fprintf_unfiltered (gdb_stdlog
,
8071 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
8073 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
8074 switch ((elf_flags
& EF_MIPS_ABI
))
8076 case E_MIPS_ABI_O32
:
8077 found_abi
= MIPS_ABI_O32
;
8079 case E_MIPS_ABI_O64
:
8080 found_abi
= MIPS_ABI_O64
;
8082 case E_MIPS_ABI_EABI32
:
8083 found_abi
= MIPS_ABI_EABI32
;
8085 case E_MIPS_ABI_EABI64
:
8086 found_abi
= MIPS_ABI_EABI64
;
8089 if ((elf_flags
& EF_MIPS_ABI2
))
8090 found_abi
= MIPS_ABI_N32
;
8092 found_abi
= MIPS_ABI_UNKNOWN
;
8096 /* GCC creates a pseudo-section whose name describes the ABI. */
8097 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
8098 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
8100 /* If we have no useful BFD information, use the ABI from the last
8101 MIPS architecture (if there is one). */
8102 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
8103 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
8105 /* Try the architecture for any hint of the correct ABI. */
8106 if (found_abi
== MIPS_ABI_UNKNOWN
8107 && info
.bfd_arch_info
!= NULL
8108 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
8110 switch (info
.bfd_arch_info
->mach
)
8112 case bfd_mach_mips3900
:
8113 found_abi
= MIPS_ABI_EABI32
;
8115 case bfd_mach_mips4100
:
8116 case bfd_mach_mips5000
:
8117 found_abi
= MIPS_ABI_EABI64
;
8119 case bfd_mach_mips8000
:
8120 case bfd_mach_mips10000
:
8121 /* On Irix, ELF64 executables use the N64 ABI. The
8122 pseudo-sections which describe the ABI aren't present
8123 on IRIX. (Even for executables created by gcc.) */
8124 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
8125 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
8126 found_abi
= MIPS_ABI_N64
;
8128 found_abi
= MIPS_ABI_N32
;
8133 /* Default 64-bit objects to N64 instead of O32. */
8134 if (found_abi
== MIPS_ABI_UNKNOWN
8135 && info
.abfd
!= NULL
8136 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
8137 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
8138 found_abi
= MIPS_ABI_N64
;
8141 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
8144 /* What has the user specified from the command line? */
8145 wanted_abi
= global_mips_abi ();
8147 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
8150 /* Now that we have found what the ABI for this binary would be,
8151 check whether the user is overriding it. */
8152 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
8153 mips_abi
= wanted_abi
;
8154 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
8155 mips_abi
= found_abi
;
8157 mips_abi
= MIPS_ABI_O32
;
8159 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
8162 /* Determine the default compressed ISA. */
8163 if ((elf_flags
& EF_MIPS_ARCH_ASE_MICROMIPS
) != 0
8164 && (elf_flags
& EF_MIPS_ARCH_ASE_M16
) == 0)
8165 mips_isa
= ISA_MICROMIPS
;
8166 else if ((elf_flags
& EF_MIPS_ARCH_ASE_M16
) != 0
8167 && (elf_flags
& EF_MIPS_ARCH_ASE_MICROMIPS
) == 0)
8168 mips_isa
= ISA_MIPS16
;
8170 mips_isa
= global_mips_compression ();
8171 mips_compression_string
= mips_compression_strings
[mips_isa
];
8173 /* Also used when doing an architecture lookup. */
8175 fprintf_unfiltered (gdb_stdlog
,
8176 "mips_gdbarch_init: "
8177 "mips64_transfers_32bit_regs_p = %d\n",
8178 mips64_transfers_32bit_regs_p
);
8180 /* Determine the MIPS FPU type. */
8183 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
8184 elf_fpu_type
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
8185 Tag_GNU_MIPS_ABI_FP
);
8186 #endif /* HAVE_ELF */
8188 if (!mips_fpu_type_auto
)
8189 fpu_type
= mips_fpu_type
;
8190 else if (elf_fpu_type
!= 0)
8192 switch (elf_fpu_type
)
8195 fpu_type
= MIPS_FPU_DOUBLE
;
8198 fpu_type
= MIPS_FPU_SINGLE
;
8202 /* Soft float or unknown. */
8203 fpu_type
= MIPS_FPU_NONE
;
8207 else if (info
.bfd_arch_info
!= NULL
8208 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
8209 switch (info
.bfd_arch_info
->mach
)
8211 case bfd_mach_mips3900
:
8212 case bfd_mach_mips4100
:
8213 case bfd_mach_mips4111
:
8214 case bfd_mach_mips4120
:
8215 fpu_type
= MIPS_FPU_NONE
;
8217 case bfd_mach_mips4650
:
8218 fpu_type
= MIPS_FPU_SINGLE
;
8221 fpu_type
= MIPS_FPU_DOUBLE
;
8224 else if (arches
!= NULL
)
8225 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
8227 fpu_type
= MIPS_FPU_DOUBLE
;
8229 fprintf_unfiltered (gdb_stdlog
,
8230 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
8232 /* Check for blatant incompatibilities. */
8234 /* If we have only 32-bit registers, then we can't debug a 64-bit
8236 if (info
.target_desc
8237 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
8238 && mips_abi
!= MIPS_ABI_EABI32
8239 && mips_abi
!= MIPS_ABI_O32
)
8241 if (tdesc_data
!= NULL
)
8242 tdesc_data_cleanup (tdesc_data
);
8246 /* Try to find a pre-existing architecture. */
8247 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
8249 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
8251 /* MIPS needs to be pedantic about which ABI the object is
8253 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
8255 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
8257 /* Need to be pedantic about which register virtual size is
8259 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
8260 != mips64_transfers_32bit_regs_p
)
8262 /* Be pedantic about which FPU is selected. */
8263 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
8266 if (tdesc_data
!= NULL
)
8267 tdesc_data_cleanup (tdesc_data
);
8268 return arches
->gdbarch
;
8271 /* Need a new architecture. Fill in a target specific vector. */
8272 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
8273 gdbarch
= gdbarch_alloc (&info
, tdep
);
8274 tdep
->elf_flags
= elf_flags
;
8275 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
8276 tdep
->found_abi
= found_abi
;
8277 tdep
->mips_abi
= mips_abi
;
8278 tdep
->mips_isa
= mips_isa
;
8279 tdep
->mips_fpu_type
= fpu_type
;
8280 tdep
->register_size_valid_p
= 0;
8281 tdep
->register_size
= 0;
8282 tdep
->gregset
= NULL
;
8283 tdep
->gregset64
= NULL
;
8284 tdep
->fpregset
= NULL
;
8285 tdep
->fpregset64
= NULL
;
8287 if (info
.target_desc
)
8289 /* Some useful properties can be inferred from the target. */
8290 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
8292 tdep
->register_size_valid_p
= 1;
8293 tdep
->register_size
= 4;
8295 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
8297 tdep
->register_size_valid_p
= 1;
8298 tdep
->register_size
= 8;
8302 /* Initially set everything according to the default ABI/ISA. */
8303 set_gdbarch_short_bit (gdbarch
, 16);
8304 set_gdbarch_int_bit (gdbarch
, 32);
8305 set_gdbarch_float_bit (gdbarch
, 32);
8306 set_gdbarch_double_bit (gdbarch
, 64);
8307 set_gdbarch_long_double_bit (gdbarch
, 64);
8308 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
8309 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
8310 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
8312 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
8313 mips_ax_pseudo_register_collect
);
8314 set_gdbarch_ax_pseudo_register_push_stack
8315 (gdbarch
, mips_ax_pseudo_register_push_stack
);
8317 set_gdbarch_elf_make_msymbol_special (gdbarch
,
8318 mips_elf_make_msymbol_special
);
8320 regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
, struct mips_regnum
);
8321 *regnum
= mips_regnum
;
8322 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
8323 set_gdbarch_num_regs (gdbarch
, num_regs
);
8324 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
8325 set_gdbarch_register_name (gdbarch
, mips_register_name
);
8326 set_gdbarch_virtual_frame_pointer (gdbarch
, mips_virtual_frame_pointer
);
8327 tdep
->mips_processor_reg_names
= reg_names
;
8328 tdep
->regnum
= regnum
;
8333 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
8334 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
8335 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
8336 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
8337 tdep
->default_mask_address_p
= 0;
8338 set_gdbarch_long_bit (gdbarch
, 32);
8339 set_gdbarch_ptr_bit (gdbarch
, 32);
8340 set_gdbarch_long_long_bit (gdbarch
, 64);
8343 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
8344 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
8345 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
8346 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
8347 tdep
->default_mask_address_p
= 0;
8348 set_gdbarch_long_bit (gdbarch
, 32);
8349 set_gdbarch_ptr_bit (gdbarch
, 32);
8350 set_gdbarch_long_long_bit (gdbarch
, 64);
8352 case MIPS_ABI_EABI32
:
8353 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
8354 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
8355 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8356 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8357 tdep
->default_mask_address_p
= 0;
8358 set_gdbarch_long_bit (gdbarch
, 32);
8359 set_gdbarch_ptr_bit (gdbarch
, 32);
8360 set_gdbarch_long_long_bit (gdbarch
, 64);
8362 case MIPS_ABI_EABI64
:
8363 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
8364 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
8365 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8366 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8367 tdep
->default_mask_address_p
= 0;
8368 set_gdbarch_long_bit (gdbarch
, 64);
8369 set_gdbarch_ptr_bit (gdbarch
, 64);
8370 set_gdbarch_long_long_bit (gdbarch
, 64);
8373 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
8374 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
8375 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8376 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8377 tdep
->default_mask_address_p
= 0;
8378 set_gdbarch_long_bit (gdbarch
, 32);
8379 set_gdbarch_ptr_bit (gdbarch
, 32);
8380 set_gdbarch_long_long_bit (gdbarch
, 64);
8381 set_gdbarch_long_double_bit (gdbarch
, 128);
8382 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
8385 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
8386 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
8387 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8388 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8389 tdep
->default_mask_address_p
= 0;
8390 set_gdbarch_long_bit (gdbarch
, 64);
8391 set_gdbarch_ptr_bit (gdbarch
, 64);
8392 set_gdbarch_long_long_bit (gdbarch
, 64);
8393 set_gdbarch_long_double_bit (gdbarch
, 128);
8394 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
8397 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
8400 /* GCC creates a pseudo-section whose name specifies the size of
8401 longs, since -mlong32 or -mlong64 may be used independent of
8402 other options. How those options affect pointer sizes is ABI and
8403 architecture dependent, so use them to override the default sizes
8404 set by the ABI. This table shows the relationship between ABI,
8405 -mlongXX, and size of pointers:
8407 ABI -mlongXX ptr bits
8408 --- -------- --------
8422 Note that for o32 and eabi32, pointers are always 32 bits
8423 regardless of any -mlongXX option. For all others, pointers and
8424 longs are the same, as set by -mlongXX or set by defaults. */
8426 if (info
.abfd
!= NULL
)
8430 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
8433 set_gdbarch_long_bit (gdbarch
, long_bit
);
8437 case MIPS_ABI_EABI32
:
8442 case MIPS_ABI_EABI64
:
8443 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
8446 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
8451 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
8452 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
8455 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
8456 flag in object files because to do so would make it impossible to
8457 link with libraries compiled without "-gp32". This is
8458 unnecessarily restrictive.
8460 We could solve this problem by adding "-gp32" multilibs to gcc,
8461 but to set this flag before gcc is built with such multilibs will
8462 break too many systems.''
8464 But even more unhelpfully, the default linker output target for
8465 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
8466 for 64-bit programs - you need to change the ABI to change this,
8467 and not all gcc targets support that currently. Therefore using
8468 this flag to detect 32-bit mode would do the wrong thing given
8469 the current gcc - it would make GDB treat these 64-bit programs
8470 as 32-bit programs by default. */
8472 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
8473 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
8475 /* Add/remove bits from an address. The MIPS needs be careful to
8476 ensure that all 32 bit addresses are sign extended to 64 bits. */
8477 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
8479 /* Unwind the frame. */
8480 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
8481 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
8482 set_gdbarch_dummy_id (gdbarch
, mips_dummy_id
);
8484 /* Map debug register numbers onto internal register numbers. */
8485 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
8486 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
8487 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
8488 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
8489 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
8490 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
8492 /* MIPS version of CALL_DUMMY. */
8494 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
8495 set_gdbarch_push_dummy_code (gdbarch
, mips_push_dummy_code
);
8496 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
8498 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
8499 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
8500 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
8502 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
8503 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
8504 set_gdbarch_remote_breakpoint_from_pc (gdbarch
,
8505 mips_remote_breakpoint_from_pc
);
8506 set_gdbarch_adjust_breakpoint_address (gdbarch
,
8507 mips_adjust_breakpoint_address
);
8509 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
8511 set_gdbarch_in_function_epilogue_p (gdbarch
, mips_in_function_epilogue_p
);
8513 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
8514 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
8515 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
8517 set_gdbarch_register_type (gdbarch
, mips_register_type
);
8519 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
8521 if (mips_abi
== MIPS_ABI_N32
)
8522 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n32
);
8523 else if (mips_abi
== MIPS_ABI_N64
)
8524 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n64
);
8526 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
8528 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint,
8529 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint
8530 need to all be folded into the target vector. Since they are
8531 being used as guards for target_stopped_by_watchpoint, why not have
8532 target_stopped_by_watchpoint return the type of watchpoint that the code
8534 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
8536 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
8538 /* NOTE drow/2012-04-25: We overload the core solib trampoline code
8539 to support MIPS16. This is a bad thing. Make sure not to do it
8540 if we have an OS ABI that actually supports shared libraries, since
8541 shared library support is more important. If we have an OS someday
8542 that supports both shared libraries and MIPS16, we'll have to find
8543 a better place for these.
8544 macro/2012-04-25: But that applies to return trampolines only and
8545 currently no MIPS OS ABI uses shared libraries that have them. */
8546 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
8548 set_gdbarch_single_step_through_delay (gdbarch
,
8549 mips_single_step_through_delay
);
8551 /* Virtual tables. */
8552 set_gdbarch_vbit_in_delta (gdbarch
, 1);
8554 mips_register_g_packet_guesses (gdbarch
);
8556 /* Hook in OS ABI-specific overrides, if they have been registered. */
8557 info
.tdep_info
= (void *) tdesc_data
;
8558 gdbarch_init_osabi (info
, gdbarch
);
8560 /* The hook may have adjusted num_regs, fetch the final value and
8561 set pc_regnum and sp_regnum now that it has been fixed. */
8562 num_regs
= gdbarch_num_regs (gdbarch
);
8563 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
8564 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
8566 /* Unwind the frame. */
8567 dwarf2_append_unwinders (gdbarch
);
8568 frame_unwind_append_unwinder (gdbarch
, &mips_stub_frame_unwind
);
8569 frame_unwind_append_unwinder (gdbarch
, &mips_insn16_frame_unwind
);
8570 frame_unwind_append_unwinder (gdbarch
, &mips_micro_frame_unwind
);
8571 frame_unwind_append_unwinder (gdbarch
, &mips_insn32_frame_unwind
);
8572 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
8573 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
8574 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
8575 frame_base_append_sniffer (gdbarch
, mips_micro_frame_base_sniffer
);
8576 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
8580 set_tdesc_pseudo_register_type (gdbarch
, mips_pseudo_register_type
);
8581 tdesc_use_registers (gdbarch
, info
.target_desc
, tdesc_data
);
8583 /* Override the normal target description methods to handle our
8584 dual real and pseudo registers. */
8585 set_gdbarch_register_name (gdbarch
, mips_register_name
);
8586 set_gdbarch_register_reggroup_p (gdbarch
,
8587 mips_tdesc_register_reggroup_p
);
8589 num_regs
= gdbarch_num_regs (gdbarch
);
8590 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
8591 set_gdbarch_pc_regnum (gdbarch
, tdep
->regnum
->pc
+ num_regs
);
8592 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
8595 /* Add ABI-specific aliases for the registers. */
8596 if (mips_abi
== MIPS_ABI_N32
|| mips_abi
== MIPS_ABI_N64
)
8597 for (i
= 0; i
< ARRAY_SIZE (mips_n32_n64_aliases
); i
++)
8598 user_reg_add (gdbarch
, mips_n32_n64_aliases
[i
].name
,
8599 value_of_mips_user_reg
, &mips_n32_n64_aliases
[i
].regnum
);
8601 for (i
= 0; i
< ARRAY_SIZE (mips_o32_aliases
); i
++)
8602 user_reg_add (gdbarch
, mips_o32_aliases
[i
].name
,
8603 value_of_mips_user_reg
, &mips_o32_aliases
[i
].regnum
);
8605 /* Add some other standard aliases. */
8606 for (i
= 0; i
< ARRAY_SIZE (mips_register_aliases
); i
++)
8607 user_reg_add (gdbarch
, mips_register_aliases
[i
].name
,
8608 value_of_mips_user_reg
, &mips_register_aliases
[i
].regnum
);
8610 for (i
= 0; i
< ARRAY_SIZE (mips_numeric_register_aliases
); i
++)
8611 user_reg_add (gdbarch
, mips_numeric_register_aliases
[i
].name
,
8612 value_of_mips_user_reg
,
8613 &mips_numeric_register_aliases
[i
].regnum
);
8619 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
8621 struct gdbarch_info info
;
8623 /* Force the architecture to update, and (if it's a MIPS architecture)
8624 mips_gdbarch_init will take care of the rest. */
8625 gdbarch_info_init (&info
);
8626 gdbarch_update_p (info
);
8629 /* Print out which MIPS ABI is in use. */
8632 show_mips_abi (struct ui_file
*file
,
8634 struct cmd_list_element
*ignored_cmd
,
8635 const char *ignored_value
)
8637 if (gdbarch_bfd_arch_info (target_gdbarch
)->arch
!= bfd_arch_mips
)
8640 "The MIPS ABI is unknown because the current architecture "
8644 enum mips_abi global_abi
= global_mips_abi ();
8645 enum mips_abi actual_abi
= mips_abi (target_gdbarch
);
8646 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
8648 if (global_abi
== MIPS_ABI_UNKNOWN
)
8651 "The MIPS ABI is set automatically (currently \"%s\").\n",
8653 else if (global_abi
== actual_abi
)
8656 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
8660 /* Probably shouldn't happen... */
8661 fprintf_filtered (file
,
8662 "The (auto detected) MIPS ABI \"%s\" is in use "
8663 "even though the user setting was \"%s\".\n",
8664 actual_abi_str
, mips_abi_strings
[global_abi
]);
8669 /* Print out which MIPS compressed ISA encoding is used. */
8672 show_mips_compression (struct ui_file
*file
, int from_tty
,
8673 struct cmd_list_element
*c
, const char *value
)
8675 fprintf_filtered (file
, _("The compressed ISA encoding used is %s.\n"),
8680 mips_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
8682 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
8686 int ef_mips_32bitmode
;
8687 /* Determine the ISA. */
8688 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
8706 /* Determine the size of a pointer. */
8707 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
8708 fprintf_unfiltered (file
,
8709 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
8711 fprintf_unfiltered (file
,
8712 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
8714 fprintf_unfiltered (file
,
8715 "mips_dump_tdep: ef_mips_arch = %d\n",
8717 fprintf_unfiltered (file
,
8718 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
8719 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
8720 fprintf_unfiltered (file
,
8722 "mips_mask_address_p() %d (default %d)\n",
8723 mips_mask_address_p (tdep
),
8724 tdep
->default_mask_address_p
);
8726 fprintf_unfiltered (file
,
8727 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
8728 MIPS_DEFAULT_FPU_TYPE
,
8729 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
8730 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
8731 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
8733 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n",
8734 MIPS_EABI (gdbarch
));
8735 fprintf_unfiltered (file
,
8736 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
8737 MIPS_FPU_TYPE (gdbarch
),
8738 (MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_NONE
? "none"
8739 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_SINGLE
? "single"
8740 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_DOUBLE
? "double"
8744 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
8747 _initialize_mips_tdep (void)
8749 static struct cmd_list_element
*mipsfpulist
= NULL
;
8750 struct cmd_list_element
*c
;
8752 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
8753 if (MIPS_ABI_LAST
+ 1
8754 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
8755 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
8757 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
8759 mips_pdr_data
= register_objfile_data ();
8761 /* Create feature sets with the appropriate properties. The values
8762 are not important. */
8763 mips_tdesc_gp32
= allocate_target_description ();
8764 set_tdesc_property (mips_tdesc_gp32
, PROPERTY_GP32
, "");
8766 mips_tdesc_gp64
= allocate_target_description ();
8767 set_tdesc_property (mips_tdesc_gp64
, PROPERTY_GP64
, "");
8769 /* Add root prefix command for all "set mips"/"show mips" commands. */
8770 add_prefix_cmd ("mips", no_class
, set_mips_command
,
8771 _("Various MIPS specific commands."),
8772 &setmipscmdlist
, "set mips ", 0, &setlist
);
8774 add_prefix_cmd ("mips", no_class
, show_mips_command
,
8775 _("Various MIPS specific commands."),
8776 &showmipscmdlist
, "show mips ", 0, &showlist
);
8778 /* Allow the user to override the ABI. */
8779 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
8780 &mips_abi_string
, _("\
8781 Set the MIPS ABI used by this program."), _("\
8782 Show the MIPS ABI used by this program."), _("\
8783 This option can be set to one of:\n\
8784 auto - the default ABI associated with the current binary\n\
8793 &setmipscmdlist
, &showmipscmdlist
);
8795 /* Allow the user to set the ISA to assume for compressed code if ELF
8796 file flags don't tell or there is no program file selected. This
8797 setting is updated whenever unambiguous ELF file flags are interpreted,
8798 and carried over to subsequent sessions. */
8799 add_setshow_enum_cmd ("compression", class_obscure
, mips_compression_strings
,
8800 &mips_compression_string
, _("\
8801 Set the compressed ISA encoding used by MIPS code."), _("\
8802 Show the compressed ISA encoding used by MIPS code."), _("\
8803 Select the compressed ISA encoding used in functions that have no symbol\n\
8804 information available. The encoding can be set to either of:\n\
8807 and is updated automatically from ELF file flags if available."),
8809 show_mips_compression
,
8810 &setmipscmdlist
, &showmipscmdlist
);
8812 /* Let the user turn off floating point and set the fence post for
8813 heuristic_proc_start. */
8815 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
8816 _("Set use of MIPS floating-point coprocessor."),
8817 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
8818 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
8819 _("Select single-precision MIPS floating-point coprocessor."),
8821 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
8822 _("Select double-precision MIPS floating-point coprocessor."),
8824 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
8825 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
8826 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
8827 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
8828 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
8829 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
8830 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
8831 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
8832 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
8833 _("Select MIPS floating-point coprocessor automatically."),
8835 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
8836 _("Show current use of MIPS floating-point coprocessor target."),
8839 /* We really would like to have both "0" and "unlimited" work, but
8840 command.c doesn't deal with that. So make it a var_zinteger
8841 because the user can always use "999999" or some such for unlimited. */
8842 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
8843 &heuristic_fence_post
, _("\
8844 Set the distance searched for the start of a function."), _("\
8845 Show the distance searched for the start of a function."), _("\
8846 If you are debugging a stripped executable, GDB needs to search through the\n\
8847 program for the start of a function. This command sets the distance of the\n\
8848 search. The only need to set it is when debugging a stripped executable."),
8849 reinit_frame_cache_sfunc
,
8850 NULL
, /* FIXME: i18n: The distance searched for
8851 the start of a function is %s. */
8852 &setlist
, &showlist
);
8854 /* Allow the user to control whether the upper bits of 64-bit
8855 addresses should be zeroed. */
8856 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
8857 &mask_address_var
, _("\
8858 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
8859 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
8860 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\
8861 allow GDB to determine the correct value."),
8862 NULL
, show_mask_address
,
8863 &setmipscmdlist
, &showmipscmdlist
);
8865 /* Allow the user to control the size of 32 bit registers within the
8866 raw remote packet. */
8867 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
8868 &mips64_transfers_32bit_regs_p
, _("\
8869 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
8871 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
8873 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
8874 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
8875 64 bits for others. Use \"off\" to disable compatibility mode"),
8876 set_mips64_transfers_32bit_regs
,
8877 NULL
, /* FIXME: i18n: Compatibility with 64-bit
8878 MIPS target that transfers 32-bit
8879 quantities is %s. */
8880 &setlist
, &showlist
);
8882 /* Debug this files internals. */
8883 add_setshow_zuinteger_cmd ("mips", class_maintenance
,
8885 Set mips debugging."), _("\
8886 Show mips debugging."), _("\
8887 When non-zero, mips specific debugging is enabled."),
8889 NULL
, /* FIXME: i18n: Mips debugging is
8891 &setdebuglist
, &showdebuglist
);