1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988-2022 Free Software Foundation, Inc.
5 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
6 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
35 #include "arch-utils.h"
38 #include "mips-tdep.h"
40 #include "reggroups.h"
41 #include "opcode/mips.h"
45 #include "sim-regno.h"
48 #include "frame-unwind.h"
49 #include "frame-base.h"
50 #include "trad-frame.h"
53 #include "target-descriptions.h"
54 #include "dwarf2/frame.h"
55 #include "user-regs.h"
58 #include "target-float.h"
61 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
63 static int mips32_instruction_has_delay_slot (struct gdbarch
*gdbarch
,
65 static int micromips_instruction_has_delay_slot (ULONGEST insn
, int mustbe32
);
66 static int mips16_instruction_has_delay_slot (unsigned short inst
,
69 static int mips32_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
71 static int micromips_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
72 CORE_ADDR addr
, int mustbe32
);
73 static int mips16_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
74 CORE_ADDR addr
, int mustbe32
);
76 static void mips_print_float_info (struct gdbarch
*, struct ui_file
*,
77 struct frame_info
*, const char *);
79 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
80 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
81 #define ST0_FR (1 << 26)
83 /* The sizes of floating point registers. */
87 MIPS_FPU_SINGLE_REGSIZE
= 4,
88 MIPS_FPU_DOUBLE_REGSIZE
= 8
97 static const char *mips_abi_string
;
99 static const char *const mips_abi_strings
[] = {
110 /* Enum describing the different kinds of breakpoints. */
112 enum mips_breakpoint_kind
114 /* 16-bit MIPS16 mode breakpoint. */
115 MIPS_BP_KIND_MIPS16
= 2,
117 /* 16-bit microMIPS mode breakpoint. */
118 MIPS_BP_KIND_MICROMIPS16
= 3,
120 /* 32-bit standard MIPS mode breakpoint. */
121 MIPS_BP_KIND_MIPS32
= 4,
123 /* 32-bit microMIPS mode breakpoint. */
124 MIPS_BP_KIND_MICROMIPS32
= 5,
127 /* For backwards compatibility we default to MIPS16. This flag is
128 overridden as soon as unambiguous ELF file flags tell us the
129 compressed ISA encoding used. */
130 static const char mips_compression_mips16
[] = "mips16";
131 static const char mips_compression_micromips
[] = "micromips";
132 static const char *const mips_compression_strings
[] =
134 mips_compression_mips16
,
135 mips_compression_micromips
,
139 static const char *mips_compression_string
= mips_compression_mips16
;
141 /* The standard register names, and all the valid aliases for them. */
142 struct register_alias
148 /* Aliases for o32 and most other ABIs. */
149 const struct register_alias mips_o32_aliases
[] = {
156 /* Aliases for n32 and n64. */
157 const struct register_alias mips_n32_n64_aliases
[] = {
164 /* Aliases for ABI-independent registers. */
165 const struct register_alias mips_register_aliases
[] = {
166 /* The architecture manuals specify these ABI-independent names for
168 #define R(n) { "r" #n, n }
169 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
170 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
171 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
172 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
175 /* k0 and k1 are sometimes called these instead (for "kernel
180 /* This is the traditional GDB name for the CP0 status register. */
181 { "sr", MIPS_PS_REGNUM
},
183 /* This is the traditional GDB name for the CP0 BadVAddr register. */
184 { "bad", MIPS_EMBED_BADVADDR_REGNUM
},
186 /* This is the traditional GDB name for the FCSR. */
187 { "fsr", MIPS_EMBED_FP0_REGNUM
+ 32 }
190 const struct register_alias mips_numeric_register_aliases
[] = {
191 #define R(n) { #n, n }
192 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
193 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
194 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
195 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
199 #ifndef MIPS_DEFAULT_FPU_TYPE
200 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
202 static int mips_fpu_type_auto
= 1;
203 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
205 static unsigned int mips_debug
= 0;
207 /* Properties (for struct target_desc) describing the g/G packet
209 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
210 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
212 struct target_desc
*mips_tdesc_gp32
;
213 struct target_desc
*mips_tdesc_gp64
;
215 /* The current set of options to be passed to the disassembler. */
216 static char *mips_disassembler_options
;
218 /* Implicit disassembler options for individual ABIs. These tell
219 libopcodes to use general-purpose register names corresponding
220 to the ABI we have selected, perhaps via a `set mips abi ...'
221 override, rather than ones inferred from the ABI set in the ELF
222 headers of the binary file selected for debugging. */
223 static const char mips_disassembler_options_o32
[] = "gpr-names=32";
224 static const char mips_disassembler_options_n32
[] = "gpr-names=n32";
225 static const char mips_disassembler_options_n64
[] = "gpr-names=64";
227 const struct mips_regnum
*
228 mips_regnum (struct gdbarch
*gdbarch
)
230 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
235 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
237 return mips_regnum (gdbarch
)->fp0
+ 12;
240 /* Return 1 if REGNUM refers to a floating-point general register, raw
241 or cooked. Otherwise return 0. */
244 mips_float_register_p (struct gdbarch
*gdbarch
, int regnum
)
246 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
248 return (rawnum
>= mips_regnum (gdbarch
)->fp0
249 && rawnum
< mips_regnum (gdbarch
)->fp0
+ 32);
253 mips_eabi (gdbarch
*arch
)
255 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (arch
);
256 return (tdep
->mips_abi
== MIPS_ABI_EABI32 \
257 || tdep
->mips_abi
== MIPS_ABI_EABI64
);
261 mips_last_fp_arg_regnum (gdbarch
*arch
)
263 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (arch
);
264 return tdep
->mips_last_fp_arg_regnum
;
268 mips_last_arg_regnum (gdbarch
*arch
)
270 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (arch
);
271 return tdep
->mips_last_arg_regnum
;
274 static enum mips_fpu_type
275 mips_get_fpu_type (gdbarch
*arch
)
277 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (arch
);
278 return tdep
->mips_fpu_type
;
281 /* Return the MIPS ABI associated with GDBARCH. */
283 mips_abi (struct gdbarch
*gdbarch
)
285 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
286 return tdep
->mips_abi
;
290 mips_isa_regsize (struct gdbarch
*gdbarch
)
292 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
294 /* If we know how big the registers are, use that size. */
295 if (tdep
->register_size_valid_p
)
296 return tdep
->register_size
;
298 /* Fall back to the previous behavior. */
299 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
300 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
303 /* Max saved register size. */
304 #define MAX_MIPS_ABI_REGSIZE 8
306 /* Return the currently configured (or set) saved register size. */
309 mips_abi_regsize (struct gdbarch
*gdbarch
)
311 switch (mips_abi (gdbarch
))
313 case MIPS_ABI_EABI32
:
319 case MIPS_ABI_EABI64
:
321 case MIPS_ABI_UNKNOWN
:
324 internal_error (__FILE__
, __LINE__
, _("bad switch"));
328 /* MIPS16/microMIPS function addresses are odd (bit 0 is set). Here
329 are some functions to handle addresses associated with compressed
330 code including but not limited to testing, setting, or clearing
331 bit 0 of such addresses. */
333 /* Return one iff compressed code is the MIPS16 instruction set. */
336 is_mips16_isa (struct gdbarch
*gdbarch
)
338 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
339 return tdep
->mips_isa
== ISA_MIPS16
;
342 /* Return one iff compressed code is the microMIPS instruction set. */
345 is_micromips_isa (struct gdbarch
*gdbarch
)
347 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
348 return tdep
->mips_isa
== ISA_MICROMIPS
;
351 /* Return one iff ADDR denotes compressed code. */
354 is_compact_addr (CORE_ADDR addr
)
359 /* Return one iff ADDR denotes standard ISA code. */
362 is_mips_addr (CORE_ADDR addr
)
364 return !is_compact_addr (addr
);
367 /* Return one iff ADDR denotes MIPS16 code. */
370 is_mips16_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
372 return is_compact_addr (addr
) && is_mips16_isa (gdbarch
);
375 /* Return one iff ADDR denotes microMIPS code. */
378 is_micromips_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
380 return is_compact_addr (addr
) && is_micromips_isa (gdbarch
);
383 /* Strip the ISA (compression) bit off from ADDR. */
386 unmake_compact_addr (CORE_ADDR addr
)
388 return ((addr
) & ~(CORE_ADDR
) 1);
391 /* Add the ISA (compression) bit to ADDR. */
394 make_compact_addr (CORE_ADDR addr
)
396 return ((addr
) | (CORE_ADDR
) 1);
399 /* Extern version of unmake_compact_addr; we use a separate function
400 so that unmake_compact_addr can be inlined throughout this file. */
403 mips_unmake_compact_addr (CORE_ADDR addr
)
405 return unmake_compact_addr (addr
);
408 /* Functions for setting and testing a bit in a minimal symbol that
409 marks it as MIPS16 or microMIPS function. The MSB of the minimal
410 symbol's "info" field is used for this purpose.
412 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is
413 "special", i.e. refers to a MIPS16 or microMIPS function, and sets
414 one of the "special" bits in a minimal symbol to mark it accordingly.
415 The test checks an ELF-private flag that is valid for true function
416 symbols only; for synthetic symbols such as for PLT stubs that have
417 no ELF-private part at all the MIPS BFD backend arranges for this
418 information to be carried in the asymbol's udata field instead.
420 msymbol_is_mips16 and msymbol_is_micromips test the "special" bit
421 in a minimal symbol. */
424 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
426 elf_symbol_type
*elfsym
= (elf_symbol_type
*) sym
;
427 unsigned char st_other
;
429 if ((sym
->flags
& BSF_SYNTHETIC
) == 0)
430 st_other
= elfsym
->internal_elf_sym
.st_other
;
431 else if ((sym
->flags
& BSF_FUNCTION
) != 0)
432 st_other
= sym
->udata
.i
;
436 if (ELF_ST_IS_MICROMIPS (st_other
))
438 MSYMBOL_TARGET_FLAG_MICROMIPS (msym
) = 1;
439 SET_MSYMBOL_VALUE_ADDRESS (msym
, MSYMBOL_VALUE_RAW_ADDRESS (msym
) | 1);
441 else if (ELF_ST_IS_MIPS16 (st_other
))
443 MSYMBOL_TARGET_FLAG_MIPS16 (msym
) = 1;
444 SET_MSYMBOL_VALUE_ADDRESS (msym
, MSYMBOL_VALUE_RAW_ADDRESS (msym
) | 1);
448 /* Return one iff MSYM refers to standard ISA code. */
451 msymbol_is_mips (struct minimal_symbol
*msym
)
453 return !(MSYMBOL_TARGET_FLAG_MIPS16 (msym
)
454 | MSYMBOL_TARGET_FLAG_MICROMIPS (msym
));
457 /* Return one iff MSYM refers to MIPS16 code. */
460 msymbol_is_mips16 (struct minimal_symbol
*msym
)
462 return MSYMBOL_TARGET_FLAG_MIPS16 (msym
);
465 /* Return one iff MSYM refers to microMIPS code. */
468 msymbol_is_micromips (struct minimal_symbol
*msym
)
470 return MSYMBOL_TARGET_FLAG_MICROMIPS (msym
);
473 /* Set the ISA bit in the main symbol too, complementing the corresponding
474 minimal symbol setting and reflecting the run-time value of the symbol.
475 The need for comes from the ISA bit having been cleared as code in
476 `_bfd_mips_elf_symbol_processing' separated it into the ELF symbol's
477 `st_other' STO_MIPS16 or STO_MICROMIPS annotation, making the values
478 of symbols referring to compressed code different in GDB to the values
479 used by actual code. That in turn makes them evaluate incorrectly in
480 expressions, producing results different to what the same expressions
481 yield when compiled into the program being debugged. */
484 mips_make_symbol_special (struct symbol
*sym
, struct objfile
*objfile
)
486 if (SYMBOL_CLASS (sym
) == LOC_BLOCK
)
488 /* We are in symbol reading so it is OK to cast away constness. */
489 struct block
*block
= (struct block
*) SYMBOL_BLOCK_VALUE (sym
);
490 CORE_ADDR compact_block_start
;
491 struct bound_minimal_symbol msym
;
493 compact_block_start
= BLOCK_START (block
) | 1;
494 msym
= lookup_minimal_symbol_by_pc (compact_block_start
);
495 if (msym
.minsym
&& !msymbol_is_mips (msym
.minsym
))
497 BLOCK_START (block
) = compact_block_start
;
502 /* XFER a value from the big/little/left end of the register.
503 Depending on the size of the value it might occupy the entire
504 register or just part of it. Make an allowance for this, aligning
505 things accordingly. */
508 mips_xfer_register (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
509 int reg_num
, int length
,
510 enum bfd_endian endian
, gdb_byte
*in
,
511 const gdb_byte
*out
, int buf_offset
)
515 gdb_assert (reg_num
>= gdbarch_num_regs (gdbarch
));
516 /* Need to transfer the left or right part of the register, based on
517 the targets byte order. */
521 reg_offset
= register_size (gdbarch
, reg_num
) - length
;
523 case BFD_ENDIAN_LITTLE
:
526 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
530 internal_error (__FILE__
, __LINE__
, _("bad switch"));
533 fprintf_unfiltered (gdb_stderr
,
534 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
535 reg_num
, reg_offset
, buf_offset
, length
);
536 if (mips_debug
&& out
!= NULL
)
539 fprintf_unfiltered (gdb_stdlog
, "out ");
540 for (i
= 0; i
< length
; i
++)
541 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
544 regcache
->cooked_read_part (reg_num
, reg_offset
, length
, in
+ buf_offset
);
546 regcache
->cooked_write_part (reg_num
, reg_offset
, length
, out
+ buf_offset
);
547 if (mips_debug
&& in
!= NULL
)
550 fprintf_unfiltered (gdb_stdlog
, "in ");
551 for (i
= 0; i
< length
; i
++)
552 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
555 fprintf_unfiltered (gdb_stdlog
, "\n");
558 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
559 compatiblity mode. A return value of 1 means that we have
560 physical 64-bit registers, but should treat them as 32-bit registers. */
563 mips2_fp_compat (struct frame_info
*frame
)
565 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
566 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
568 if (register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) == 4)
572 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
573 in all the places we deal with FP registers. PR gdb/413. */
574 /* Otherwise check the FR bit in the status register - it controls
575 the FP compatiblity mode. If it is clear we are in compatibility
577 if ((get_frame_register_unsigned (frame
, MIPS_PS_REGNUM
) & ST0_FR
) == 0)
584 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
586 static CORE_ADDR
heuristic_proc_start (struct gdbarch
*, CORE_ADDR
);
588 /* The list of available "set mips " and "show mips " commands. */
590 static struct cmd_list_element
*setmipscmdlist
= NULL
;
591 static struct cmd_list_element
*showmipscmdlist
= NULL
;
593 /* Integer registers 0 thru 31 are handled explicitly by
594 mips_register_name(). Processor specific registers 32 and above
595 are listed in the following tables. */
598 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
602 static const char * const mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
603 "sr", "lo", "hi", "bad", "cause", "pc",
604 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
605 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
606 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
607 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
611 /* Names of tx39 registers. */
613 static const char * const mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
614 "sr", "lo", "hi", "bad", "cause", "pc",
615 "", "", "", "", "", "", "", "",
616 "", "", "", "", "", "", "", "",
617 "", "", "", "", "", "", "", "",
618 "", "", "", "", "", "", "", "",
620 "", "", "", "", "", "", "", "",
621 "", "", "config", "cache", "debug", "depc", "epc",
624 /* Names of registers with Linux kernels. */
625 static const char * const mips_linux_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
626 "sr", "lo", "hi", "bad", "cause", "pc",
627 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
628 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
629 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
630 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
635 /* Return the name of the register corresponding to REGNO. */
637 mips_register_name (struct gdbarch
*gdbarch
, int regno
)
639 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
640 /* GPR names for all ABIs other than n32/n64. */
641 static const char *mips_gpr_names
[] = {
642 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
643 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
644 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
645 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
648 /* GPR names for n32 and n64 ABIs. */
649 static const char *mips_n32_n64_gpr_names
[] = {
650 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
651 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
652 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
653 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
656 enum mips_abi abi
= mips_abi (gdbarch
);
658 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
659 but then don't make the raw register names visible. This (upper)
660 range of user visible register numbers are the pseudo-registers.
662 This approach was adopted accommodate the following scenario:
663 It is possible to debug a 64-bit device using a 32-bit
664 programming model. In such instances, the raw registers are
665 configured to be 64-bits wide, while the pseudo registers are
666 configured to be 32-bits wide. The registers that the user
667 sees - the pseudo registers - match the users expectations
668 given the programming model being used. */
669 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
670 if (regno
< gdbarch_num_regs (gdbarch
))
673 /* The MIPS integer registers are always mapped from 0 to 31. The
674 names of the registers (which reflects the conventions regarding
675 register use) vary depending on the ABI. */
676 if (0 <= rawnum
&& rawnum
< 32)
678 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
679 return mips_n32_n64_gpr_names
[rawnum
];
681 return mips_gpr_names
[rawnum
];
683 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
684 return tdesc_register_name (gdbarch
, rawnum
);
685 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (gdbarch
))
687 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
688 if (tdep
->mips_processor_reg_names
[rawnum
- 32])
689 return tdep
->mips_processor_reg_names
[rawnum
- 32];
693 internal_error (__FILE__
, __LINE__
,
694 _("mips_register_name: bad register number %d"), rawnum
);
697 /* Return the groups that a MIPS register can be categorised into. */
700 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
701 struct reggroup
*reggroup
)
706 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
707 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
708 if (reggroup
== all_reggroup
)
710 vector_p
= register_type (gdbarch
, regnum
)->is_vector ();
711 float_p
= register_type (gdbarch
, regnum
)->code () == TYPE_CODE_FLT
;
712 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
713 (gdbarch), as not all architectures are multi-arch. */
714 raw_p
= rawnum
< gdbarch_num_regs (gdbarch
);
715 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
716 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
718 if (reggroup
== float_reggroup
)
719 return float_p
&& pseudo
;
720 if (reggroup
== vector_reggroup
)
721 return vector_p
&& pseudo
;
722 if (reggroup
== general_reggroup
)
723 return (!vector_p
&& !float_p
) && pseudo
;
724 /* Save the pseudo registers. Need to make certain that any code
725 extracting register values from a saved register cache also uses
727 if (reggroup
== save_reggroup
)
728 return raw_p
&& pseudo
;
729 /* Restore the same pseudo register. */
730 if (reggroup
== restore_reggroup
)
731 return raw_p
&& pseudo
;
735 /* Return the groups that a MIPS register can be categorised into.
736 This version is only used if we have a target description which
737 describes real registers (and their groups). */
740 mips_tdesc_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
741 struct reggroup
*reggroup
)
743 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
744 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
747 /* Only save, restore, and display the pseudo registers. Need to
748 make certain that any code extracting register values from a
749 saved register cache also uses pseudo registers.
751 Note: saving and restoring the pseudo registers is slightly
752 strange; if we have 64 bits, we should save and restore all
753 64 bits. But this is hard and has little benefit. */
757 ret
= tdesc_register_in_reggroup_p (gdbarch
, rawnum
, reggroup
);
761 return mips_register_reggroup_p (gdbarch
, regnum
, reggroup
);
764 /* Map the symbol table registers which live in the range [1 *
765 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
766 registers. Take care of alignment and size problems. */
768 static enum register_status
769 mips_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
770 int cookednum
, gdb_byte
*buf
)
772 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
773 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
774 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
775 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
776 return regcache
->raw_read (rawnum
, buf
);
777 else if (register_size (gdbarch
, rawnum
) >
778 register_size (gdbarch
, cookednum
))
780 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
782 if (tdep
->mips64_transfers_32bit_regs_p
)
783 return regcache
->raw_read_part (rawnum
, 0, 4, buf
);
786 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
788 enum register_status status
;
790 status
= regcache
->raw_read (rawnum
, ®val
);
791 if (status
== REG_VALID
)
792 store_signed_integer (buf
, 4, byte_order
, regval
);
797 internal_error (__FILE__
, __LINE__
, _("bad register size"));
801 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
802 struct regcache
*regcache
, int cookednum
,
805 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
806 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
807 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
808 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
809 regcache
->raw_write (rawnum
, buf
);
810 else if (register_size (gdbarch
, rawnum
) >
811 register_size (gdbarch
, cookednum
))
813 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
815 if (tdep
->mips64_transfers_32bit_regs_p
)
816 regcache
->raw_write_part (rawnum
, 0, 4, buf
);
819 /* Sign extend the shortened version of the register prior
820 to placing it in the raw register. This is required for
821 some mips64 parts in order to avoid unpredictable behavior. */
822 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
823 LONGEST regval
= extract_signed_integer (buf
, 4, byte_order
);
824 regcache_raw_write_signed (regcache
, rawnum
, regval
);
828 internal_error (__FILE__
, __LINE__
, _("bad register size"));
832 mips_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
833 struct agent_expr
*ax
, int reg
)
835 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
836 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
837 && reg
< 2 * gdbarch_num_regs (gdbarch
));
839 ax_reg_mask (ax
, rawnum
);
845 mips_ax_pseudo_register_push_stack (struct gdbarch
*gdbarch
,
846 struct agent_expr
*ax
, int reg
)
848 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
849 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
850 && reg
< 2 * gdbarch_num_regs (gdbarch
));
851 if (register_size (gdbarch
, rawnum
) >= register_size (gdbarch
, reg
))
855 if (register_size (gdbarch
, rawnum
) > register_size (gdbarch
, reg
))
857 mips_gdbarch_tdep
*tdep
858 = (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
860 if (!tdep
->mips64_transfers_32bit_regs_p
861 || gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_BIG
)
864 ax_simple (ax
, aop_lsh
);
867 ax_simple (ax
, aop_rsh_signed
);
871 internal_error (__FILE__
, __LINE__
, _("bad register size"));
876 /* Table to translate 3-bit register field to actual register number. */
877 static const signed char mips_reg3_to_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
879 /* Heuristic_proc_start may hunt through the text section for a long
880 time across a 2400 baud serial line. Allows the user to limit this
883 static int heuristic_fence_post
= 0;
885 /* Number of bytes of storage in the actual machine representation for
886 register N. NOTE: This defines the pseudo register type so need to
887 rebuild the architecture vector. */
889 static bool mips64_transfers_32bit_regs_p
= false;
892 set_mips64_transfers_32bit_regs (const char *args
, int from_tty
,
893 struct cmd_list_element
*c
)
895 struct gdbarch_info info
;
896 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
897 instead of relying on globals. Doing that would let generic code
898 handle the search for this specific architecture. */
899 if (!gdbarch_update_p (info
))
901 mips64_transfers_32bit_regs_p
= 0;
902 error (_("32-bit compatibility mode not supported"));
906 /* Convert to/from a register and the corresponding memory value. */
908 /* This predicate tests for the case of an 8 byte floating point
909 value that is being transferred to or from a pair of floating point
910 registers each of which are (or are considered to be) only 4 bytes
913 mips_convert_register_float_case_p (struct gdbarch
*gdbarch
, int regnum
,
916 return (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
917 && register_size (gdbarch
, regnum
) == 4
918 && mips_float_register_p (gdbarch
, regnum
)
919 && type
->code () == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
922 /* This predicate tests for the case of a value of less than 8
923 bytes in width that is being transfered to or from an 8 byte
924 general purpose register. */
926 mips_convert_register_gpreg_case_p (struct gdbarch
*gdbarch
, int regnum
,
929 int num_regs
= gdbarch_num_regs (gdbarch
);
931 return (register_size (gdbarch
, regnum
) == 8
932 && regnum
% num_regs
> 0 && regnum
% num_regs
< 32
933 && TYPE_LENGTH (type
) < 8);
937 mips_convert_register_p (struct gdbarch
*gdbarch
,
938 int regnum
, struct type
*type
)
940 return (mips_convert_register_float_case_p (gdbarch
, regnum
, type
)
941 || mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
));
945 mips_register_to_value (struct frame_info
*frame
, int regnum
,
946 struct type
*type
, gdb_byte
*to
,
947 int *optimizedp
, int *unavailablep
)
949 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
951 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
953 get_frame_register (frame
, regnum
+ 0, to
+ 4);
954 get_frame_register (frame
, regnum
+ 1, to
+ 0);
956 if (!get_frame_register_bytes (frame
, regnum
+ 0, 0, {to
+ 4, 4},
957 optimizedp
, unavailablep
))
960 if (!get_frame_register_bytes (frame
, regnum
+ 1, 0, {to
+ 0, 4},
961 optimizedp
, unavailablep
))
963 *optimizedp
= *unavailablep
= 0;
966 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
968 size_t len
= TYPE_LENGTH (type
);
971 offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 8 - len
: 0;
972 if (!get_frame_register_bytes (frame
, regnum
, offset
, {to
, len
},
973 optimizedp
, unavailablep
))
976 *optimizedp
= *unavailablep
= 0;
981 internal_error (__FILE__
, __LINE__
,
982 _("mips_register_to_value: unrecognized case"));
987 mips_value_to_register (struct frame_info
*frame
, int regnum
,
988 struct type
*type
, const gdb_byte
*from
)
990 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
992 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
994 put_frame_register (frame
, regnum
+ 0, from
+ 4);
995 put_frame_register (frame
, regnum
+ 1, from
+ 0);
997 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
1000 size_t len
= TYPE_LENGTH (type
);
1002 /* Sign extend values, irrespective of type, that are stored to
1003 a 64-bit general purpose register. (32-bit unsigned values
1004 are stored as signed quantities within a 64-bit register.
1005 When performing an operation, in compiled code, that combines
1006 a 32-bit unsigned value with a signed 64-bit value, a type
1007 conversion is first performed that zeroes out the high 32 bits.) */
1008 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1011 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, -1);
1013 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, 0);
1014 put_frame_register_bytes (frame
, regnum
, 0, {fill
, 8 - len
});
1015 put_frame_register_bytes (frame
, regnum
, 8 - len
, {from
, len
});
1019 if (from
[len
-1] & 0x80)
1020 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, -1);
1022 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, 0);
1023 put_frame_register_bytes (frame
, regnum
, 0, {from
, len
});
1024 put_frame_register_bytes (frame
, regnum
, len
, {fill
, 8 - len
});
1029 internal_error (__FILE__
, __LINE__
,
1030 _("mips_value_to_register: unrecognized case"));
1034 /* Return the GDB type object for the "standard" data type of data in
1037 static struct type
*
1038 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
1040 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (gdbarch
));
1041 if (mips_float_register_p (gdbarch
, regnum
))
1043 /* The floating-point registers raw, or cooked, always match
1044 mips_isa_regsize(), and also map 1:1, byte for byte. */
1045 if (mips_isa_regsize (gdbarch
) == 4)
1046 return builtin_type (gdbarch
)->builtin_float
;
1048 return builtin_type (gdbarch
)->builtin_double
;
1050 else if (regnum
< gdbarch_num_regs (gdbarch
))
1052 /* The raw or ISA registers. These are all sized according to
1054 if (mips_isa_regsize (gdbarch
) == 4)
1055 return builtin_type (gdbarch
)->builtin_int32
;
1057 return builtin_type (gdbarch
)->builtin_int64
;
1061 int rawnum
= regnum
- gdbarch_num_regs (gdbarch
);
1062 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
1064 /* The cooked or ABI registers. These are sized according to
1065 the ABI (with a few complications). */
1066 if (rawnum
== mips_regnum (gdbarch
)->fp_control_status
1067 || rawnum
== mips_regnum (gdbarch
)->fp_implementation_revision
)
1068 return builtin_type (gdbarch
)->builtin_int32
;
1069 else if (gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
1070 && rawnum
>= MIPS_FIRST_EMBED_REGNUM
1071 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
1072 /* The pseudo/cooked view of the embedded registers is always
1073 32-bit. The raw view is handled below. */
1074 return builtin_type (gdbarch
)->builtin_int32
;
1075 else if (tdep
->mips64_transfers_32bit_regs_p
)
1076 /* The target, while possibly using a 64-bit register buffer,
1077 is only transfering 32-bits of each integer register.
1078 Reflect this in the cooked/pseudo (ABI) register value. */
1079 return builtin_type (gdbarch
)->builtin_int32
;
1080 else if (mips_abi_regsize (gdbarch
) == 4)
1081 /* The ABI is restricted to 32-bit registers (the ISA could be
1083 return builtin_type (gdbarch
)->builtin_int32
;
1086 return builtin_type (gdbarch
)->builtin_int64
;
1090 /* Return the GDB type for the pseudo register REGNUM, which is the
1091 ABI-level view. This function is only called if there is a target
1092 description which includes registers, so we know precisely the
1093 types of hardware registers. */
1095 static struct type
*
1096 mips_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
1098 const int num_regs
= gdbarch_num_regs (gdbarch
);
1099 int rawnum
= regnum
% num_regs
;
1100 struct type
*rawtype
;
1102 gdb_assert (regnum
>= num_regs
&& regnum
< 2 * num_regs
);
1104 /* Absent registers are still absent. */
1105 rawtype
= gdbarch_register_type (gdbarch
, rawnum
);
1106 if (TYPE_LENGTH (rawtype
) == 0)
1109 /* Present the floating point registers however the hardware did;
1110 do not try to convert between FPU layouts. */
1111 if (mips_float_register_p (gdbarch
, rawnum
))
1114 /* Floating-point control registers are always 32-bit even though for
1115 backwards compatibility reasons 64-bit targets will transfer them
1116 as 64-bit quantities even if using XML descriptions. */
1117 if (rawnum
== mips_regnum (gdbarch
)->fp_control_status
1118 || rawnum
== mips_regnum (gdbarch
)->fp_implementation_revision
)
1119 return builtin_type (gdbarch
)->builtin_int32
;
1121 /* Use pointer types for registers if we can. For n32 we can not,
1122 since we do not have a 64-bit pointer type. */
1123 if (mips_abi_regsize (gdbarch
)
1124 == TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
))
1126 if (rawnum
== MIPS_SP_REGNUM
1127 || rawnum
== mips_regnum (gdbarch
)->badvaddr
)
1128 return builtin_type (gdbarch
)->builtin_data_ptr
;
1129 else if (rawnum
== mips_regnum (gdbarch
)->pc
)
1130 return builtin_type (gdbarch
)->builtin_func_ptr
;
1133 if (mips_abi_regsize (gdbarch
) == 4 && TYPE_LENGTH (rawtype
) == 8
1134 && ((rawnum
>= MIPS_ZERO_REGNUM
&& rawnum
<= MIPS_PS_REGNUM
)
1135 || rawnum
== mips_regnum (gdbarch
)->lo
1136 || rawnum
== mips_regnum (gdbarch
)->hi
1137 || rawnum
== mips_regnum (gdbarch
)->badvaddr
1138 || rawnum
== mips_regnum (gdbarch
)->cause
1139 || rawnum
== mips_regnum (gdbarch
)->pc
1140 || (mips_regnum (gdbarch
)->dspacc
!= -1
1141 && rawnum
>= mips_regnum (gdbarch
)->dspacc
1142 && rawnum
< mips_regnum (gdbarch
)->dspacc
+ 6)))
1143 return builtin_type (gdbarch
)->builtin_int32
;
1145 /* The pseudo/cooked view of embedded registers is always
1146 32-bit, even if the target transfers 64-bit values for them.
1147 New targets relying on XML descriptions should only transfer
1148 the necessary 32 bits, but older versions of GDB expected 64,
1149 so allow the target to provide 64 bits without interfering
1150 with the displayed type. */
1151 if (gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
1152 && rawnum
>= MIPS_FIRST_EMBED_REGNUM
1153 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
1154 return builtin_type (gdbarch
)->builtin_int32
;
1156 /* For all other registers, pass through the hardware type. */
1160 /* Should the upper word of 64-bit addresses be zeroed? */
1161 static enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
1164 mips_mask_address_p (mips_gdbarch_tdep
*tdep
)
1166 switch (mask_address_var
)
1168 case AUTO_BOOLEAN_TRUE
:
1170 case AUTO_BOOLEAN_FALSE
:
1173 case AUTO_BOOLEAN_AUTO
:
1174 return tdep
->default_mask_address_p
;
1176 internal_error (__FILE__
, __LINE__
,
1177 _("mips_mask_address_p: bad switch"));
1183 show_mask_address (struct ui_file
*file
, int from_tty
,
1184 struct cmd_list_element
*c
, const char *value
)
1186 mips_gdbarch_tdep
*tdep
1187 = (mips_gdbarch_tdep
*) gdbarch_tdep (target_gdbarch ());
1189 deprecated_show_value_hack (file
, from_tty
, c
, value
);
1190 switch (mask_address_var
)
1192 case AUTO_BOOLEAN_TRUE
:
1193 fprintf_filtered (file
, "The 32 bit mips address mask is enabled\n");
1195 case AUTO_BOOLEAN_FALSE
:
1196 fprintf_filtered (file
, "The 32 bit mips address mask is disabled\n");
1198 case AUTO_BOOLEAN_AUTO
:
1201 "The 32 bit address mask is set automatically. Currently %s\n",
1202 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
1205 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
1210 /* Tell if the program counter value in MEMADDR is in a standard ISA
1214 mips_pc_is_mips (CORE_ADDR memaddr
)
1216 struct bound_minimal_symbol sym
;
1218 /* Flags indicating that this is a MIPS16 or microMIPS function is
1219 stored by elfread.c in the high bit of the info field. Use this
1220 to decide if the function is standard MIPS. Otherwise if bit 0
1221 of the address is clear, then this is a standard MIPS function. */
1222 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1224 return msymbol_is_mips (sym
.minsym
);
1226 return is_mips_addr (memaddr
);
1229 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
1232 mips_pc_is_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1234 struct bound_minimal_symbol sym
;
1236 /* A flag indicating that this is a MIPS16 function is stored by
1237 elfread.c in the high bit of the info field. Use this to decide
1238 if the function is MIPS16. Otherwise if bit 0 of the address is
1239 set, then ELF file flags will tell if this is a MIPS16 function. */
1240 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1242 return msymbol_is_mips16 (sym
.minsym
);
1244 return is_mips16_addr (gdbarch
, memaddr
);
1247 /* Tell if the program counter value in MEMADDR is in a microMIPS function. */
1250 mips_pc_is_micromips (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1252 struct bound_minimal_symbol sym
;
1254 /* A flag indicating that this is a microMIPS function is stored by
1255 elfread.c in the high bit of the info field. Use this to decide
1256 if the function is microMIPS. Otherwise if bit 0 of the address
1257 is set, then ELF file flags will tell if this is a microMIPS
1259 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1261 return msymbol_is_micromips (sym
.minsym
);
1263 return is_micromips_addr (gdbarch
, memaddr
);
1266 /* Tell the ISA type of the function the program counter value in MEMADDR
1269 static enum mips_isa
1270 mips_pc_isa (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1272 struct bound_minimal_symbol sym
;
1274 /* A flag indicating that this is a MIPS16 or a microMIPS function
1275 is stored by elfread.c in the high bit of the info field. Use
1276 this to decide if the function is MIPS16 or microMIPS or normal
1277 MIPS. Otherwise if bit 0 of the address is set, then ELF file
1278 flags will tell if this is a MIPS16 or a microMIPS function. */
1279 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1282 if (msymbol_is_micromips (sym
.minsym
))
1283 return ISA_MICROMIPS
;
1284 else if (msymbol_is_mips16 (sym
.minsym
))
1291 if (is_mips_addr (memaddr
))
1293 else if (is_micromips_addr (gdbarch
, memaddr
))
1294 return ISA_MICROMIPS
;
1300 /* Set the ISA bit correctly in the PC, used by DWARF-2 machinery.
1301 The need for comes from the ISA bit having been cleared, making
1302 addresses in FDE, range records, etc. referring to compressed code
1303 different to those in line information, the symbol table and finally
1304 the PC register. That in turn confuses many operations. */
1307 mips_adjust_dwarf2_addr (CORE_ADDR pc
)
1309 pc
= unmake_compact_addr (pc
);
1310 return mips_pc_is_mips (pc
) ? pc
: make_compact_addr (pc
);
1313 /* Recalculate the line record requested so that the resulting PC has
1314 the ISA bit set correctly, used by DWARF-2 machinery. The need for
1315 this adjustment comes from some records associated with compressed
1316 code having the ISA bit cleared, most notably at function prologue
1317 ends. The ISA bit is in this context retrieved from the minimal
1318 symbol covering the address requested, which in turn has been
1319 constructed from the binary's symbol table rather than DWARF-2
1320 information. The correct setting of the ISA bit is required for
1321 breakpoint addresses to correctly match against the stop PC.
1323 As line entries can specify relative address adjustments we need to
1324 keep track of the absolute value of the last line address recorded
1325 in line information, so that we can calculate the actual address to
1326 apply the ISA bit adjustment to. We use PC for this tracking and
1327 keep the original address there.
1329 As such relative address adjustments can be odd within compressed
1330 code we need to keep track of the last line address with the ISA
1331 bit adjustment applied too, as the original address may or may not
1332 have had the ISA bit set. We use ADJ_PC for this tracking and keep
1333 the adjusted address there.
1335 For relative address adjustments we then use these variables to
1336 calculate the address intended by line information, which will be
1337 PC-relative, and return an updated adjustment carrying ISA bit
1338 information, which will be ADJ_PC-relative. For absolute address
1339 adjustments we just return the same address that we store in ADJ_PC
1342 As the first line entry can be relative to an implied address value
1343 of 0 we need to have the initial address set up that we store in PC
1344 and ADJ_PC. This is arranged with a call from `dwarf_decode_lines_1'
1345 that sets PC to 0 and ADJ_PC accordingly, usually 0 as well. */
1348 mips_adjust_dwarf2_line (CORE_ADDR addr
, int rel
)
1350 static CORE_ADDR adj_pc
;
1351 static CORE_ADDR pc
;
1354 pc
= rel
? pc
+ addr
: addr
;
1355 isa_pc
= mips_adjust_dwarf2_addr (pc
);
1356 addr
= rel
? isa_pc
- adj_pc
: isa_pc
;
1361 /* Various MIPS16 thunk (aka stub or trampoline) names. */
1363 static const char mips_str_mips16_call_stub
[] = "__mips16_call_stub_";
1364 static const char mips_str_mips16_ret_stub
[] = "__mips16_ret_";
1365 static const char mips_str_call_fp_stub
[] = "__call_stub_fp_";
1366 static const char mips_str_call_stub
[] = "__call_stub_";
1367 static const char mips_str_fn_stub
[] = "__fn_stub_";
1369 /* This is used as a PIC thunk prefix. */
1371 static const char mips_str_pic
[] = ".pic.";
1373 /* Return non-zero if the PC is inside a call thunk (aka stub or
1374 trampoline) that should be treated as a temporary frame. */
1377 mips_in_frame_stub (CORE_ADDR pc
)
1379 CORE_ADDR start_addr
;
1382 /* Find the starting address of the function containing the PC. */
1383 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
1386 /* If the PC is in __mips16_call_stub_*, this is a call/return stub. */
1387 if (startswith (name
, mips_str_mips16_call_stub
))
1389 /* If the PC is in __call_stub_*, this is a call/return or a call stub. */
1390 if (startswith (name
, mips_str_call_stub
))
1392 /* If the PC is in __fn_stub_*, this is a call stub. */
1393 if (startswith (name
, mips_str_fn_stub
))
1396 return 0; /* Not a stub. */
1399 /* MIPS believes that the PC has a sign extended value. Perhaps the
1400 all registers should be sign extended for simplicity? */
1403 mips_read_pc (readable_regcache
*regcache
)
1405 int regnum
= gdbarch_pc_regnum (regcache
->arch ());
1408 regcache
->cooked_read (regnum
, &pc
);
1413 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1417 pc
= frame_unwind_register_signed (next_frame
, gdbarch_pc_regnum (gdbarch
));
1418 /* macro/2012-04-20: This hack skips over MIPS16 call thunks as
1419 intermediate frames. In this case we can get the caller's address
1420 from $ra, or if $ra contains an address within a thunk as well, then
1421 it must be in the return path of __mips16_call_stub_{s,d}{f,c}_{0..10}
1422 and thus the caller's address is in $s2. */
1423 if (frame_relative_level (next_frame
) >= 0 && mips_in_frame_stub (pc
))
1425 pc
= frame_unwind_register_signed
1426 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
1427 if (mips_in_frame_stub (pc
))
1428 pc
= frame_unwind_register_signed
1429 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
1435 mips_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1437 return frame_unwind_register_signed
1438 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
);
1441 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1442 dummy frame. The frame ID's base needs to match the TOS value
1443 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1446 static struct frame_id
1447 mips_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1449 return frame_id_build
1450 (get_frame_register_signed (this_frame
,
1451 gdbarch_num_regs (gdbarch
)
1453 get_frame_pc (this_frame
));
1456 /* Implement the "write_pc" gdbarch method. */
1459 mips_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1461 int regnum
= gdbarch_pc_regnum (regcache
->arch ());
1463 regcache_cooked_write_unsigned (regcache
, regnum
, pc
);
1466 /* Fetch and return instruction from the specified location. Handle
1467 MIPS16/microMIPS as appropriate. */
1470 mips_fetch_instruction (struct gdbarch
*gdbarch
,
1471 enum mips_isa isa
, CORE_ADDR addr
, int *errp
)
1473 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1474 gdb_byte buf
[MIPS_INSN32_SIZE
];
1482 instlen
= MIPS_INSN16_SIZE
;
1483 addr
= unmake_compact_addr (addr
);
1486 instlen
= MIPS_INSN32_SIZE
;
1489 internal_error (__FILE__
, __LINE__
, _("invalid ISA"));
1492 err
= target_read_memory (addr
, buf
, instlen
);
1498 memory_error (TARGET_XFER_E_IO
, addr
);
1501 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1504 /* These are the fields of 32 bit mips instructions. */
1505 #define mips32_op(x) (x >> 26)
1506 #define itype_op(x) (x >> 26)
1507 #define itype_rs(x) ((x >> 21) & 0x1f)
1508 #define itype_rt(x) ((x >> 16) & 0x1f)
1509 #define itype_immediate(x) (x & 0xffff)
1511 #define jtype_op(x) (x >> 26)
1512 #define jtype_target(x) (x & 0x03ffffff)
1514 #define rtype_op(x) (x >> 26)
1515 #define rtype_rs(x) ((x >> 21) & 0x1f)
1516 #define rtype_rt(x) ((x >> 16) & 0x1f)
1517 #define rtype_rd(x) ((x >> 11) & 0x1f)
1518 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1519 #define rtype_funct(x) (x & 0x3f)
1521 /* MicroMIPS instruction fields. */
1522 #define micromips_op(x) ((x) >> 10)
1524 /* 16-bit/32-bit-high-part instruction formats, B and S refer to the lowest
1525 bit and the size respectively of the field extracted. */
1526 #define b0s4_imm(x) ((x) & 0xf)
1527 #define b0s5_imm(x) ((x) & 0x1f)
1528 #define b0s5_reg(x) ((x) & 0x1f)
1529 #define b0s7_imm(x) ((x) & 0x7f)
1530 #define b0s10_imm(x) ((x) & 0x3ff)
1531 #define b1s4_imm(x) (((x) >> 1) & 0xf)
1532 #define b1s9_imm(x) (((x) >> 1) & 0x1ff)
1533 #define b2s3_cc(x) (((x) >> 2) & 0x7)
1534 #define b4s2_regl(x) (((x) >> 4) & 0x3)
1535 #define b5s5_op(x) (((x) >> 5) & 0x1f)
1536 #define b5s5_reg(x) (((x) >> 5) & 0x1f)
1537 #define b6s4_op(x) (((x) >> 6) & 0xf)
1538 #define b7s3_reg(x) (((x) >> 7) & 0x7)
1540 /* 32-bit instruction formats, B and S refer to the lowest bit and the size
1541 respectively of the field extracted. */
1542 #define b0s6_op(x) ((x) & 0x3f)
1543 #define b0s11_op(x) ((x) & 0x7ff)
1544 #define b0s12_imm(x) ((x) & 0xfff)
1545 #define b0s16_imm(x) ((x) & 0xffff)
1546 #define b0s26_imm(x) ((x) & 0x3ffffff)
1547 #define b6s10_ext(x) (((x) >> 6) & 0x3ff)
1548 #define b11s5_reg(x) (((x) >> 11) & 0x1f)
1549 #define b12s4_op(x) (((x) >> 12) & 0xf)
1551 /* Return the size in bytes of the instruction INSN encoded in the ISA
1555 mips_insn_size (enum mips_isa isa
, ULONGEST insn
)
1560 if ((micromips_op (insn
) & 0x4) == 0x4
1561 || (micromips_op (insn
) & 0x7) == 0x0)
1562 return 2 * MIPS_INSN16_SIZE
;
1564 return MIPS_INSN16_SIZE
;
1566 if ((insn
& 0xf800) == 0xf000)
1567 return 2 * MIPS_INSN16_SIZE
;
1569 return MIPS_INSN16_SIZE
;
1571 return MIPS_INSN32_SIZE
;
1573 internal_error (__FILE__
, __LINE__
, _("invalid ISA"));
1577 mips32_relative_offset (ULONGEST inst
)
1579 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
1582 /* Determine the address of the next instruction executed after the INST
1583 floating condition branch instruction at PC. COUNT specifies the
1584 number of the floating condition bits tested by the branch. */
1587 mips32_bc1_pc (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1588 ULONGEST inst
, CORE_ADDR pc
, int count
)
1590 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1591 int cnum
= (itype_rt (inst
) >> 2) & (count
- 1);
1592 int tf
= itype_rt (inst
) & 1;
1593 int mask
= (1 << count
) - 1;
1598 /* No way to handle; it'll most likely trap anyway. */
1601 fcs
= regcache_raw_get_unsigned (regcache
, fcsr
);
1602 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1604 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1605 pc
+= mips32_relative_offset (inst
);
1612 /* Return nonzero if the gdbarch is an Octeon series. */
1615 is_octeon (struct gdbarch
*gdbarch
)
1617 const struct bfd_arch_info
*info
= gdbarch_bfd_arch_info (gdbarch
);
1619 return (info
->mach
== bfd_mach_mips_octeon
1620 || info
->mach
== bfd_mach_mips_octeonp
1621 || info
->mach
== bfd_mach_mips_octeon2
);
1624 /* Return true if the OP represents the Octeon's BBIT instruction. */
1627 is_octeon_bbit_op (int op
, struct gdbarch
*gdbarch
)
1629 if (!is_octeon (gdbarch
))
1631 /* BBIT0 is encoded as LWC2: 110 010. */
1632 /* BBIT032 is encoded as LDC2: 110 110. */
1633 /* BBIT1 is encoded as SWC2: 111 010. */
1634 /* BBIT132 is encoded as SDC2: 111 110. */
1635 if (op
== 50 || op
== 54 || op
== 58 || op
== 62)
1641 /* Determine where to set a single step breakpoint while considering
1642 branch prediction. */
1645 mips32_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1647 struct gdbarch
*gdbarch
= regcache
->arch ();
1650 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
1651 op
= itype_op (inst
);
1652 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch
1656 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1667 goto greater_branch
;
1672 else if (op
== 17 && itype_rs (inst
) == 8)
1673 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1674 pc
= mips32_bc1_pc (gdbarch
, regcache
, inst
, pc
+ 4, 1);
1675 else if (op
== 17 && itype_rs (inst
) == 9
1676 && (itype_rt (inst
) & 2) == 0)
1677 /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */
1678 pc
= mips32_bc1_pc (gdbarch
, regcache
, inst
, pc
+ 4, 2);
1679 else if (op
== 17 && itype_rs (inst
) == 10
1680 && (itype_rt (inst
) & 2) == 0)
1681 /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */
1682 pc
= mips32_bc1_pc (gdbarch
, regcache
, inst
, pc
+ 4, 4);
1685 /* The new PC will be alternate mode. */
1689 reg
= jtype_target (inst
) << 2;
1690 /* Add 1 to indicate 16-bit mode -- invert ISA mode. */
1691 pc
= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + reg
+ 1;
1693 else if (is_octeon_bbit_op (op
, gdbarch
))
1697 branch_if
= op
== 58 || op
== 62;
1698 bit
= itype_rt (inst
);
1700 /* Take into account the *32 instructions. */
1701 if (op
== 54 || op
== 62)
1704 if (((regcache_raw_get_signed (regcache
,
1705 itype_rs (inst
)) >> bit
) & 1)
1707 pc
+= mips32_relative_offset (inst
) + 4;
1709 pc
+= 8; /* After the delay slot. */
1713 pc
+= 4; /* Not a branch, next instruction is easy. */
1716 { /* This gets way messy. */
1718 /* Further subdivide into SPECIAL, REGIMM and other. */
1719 switch (op
& 0x07) /* Extract bits 28,27,26. */
1721 case 0: /* SPECIAL */
1722 op
= rtype_funct (inst
);
1727 /* Set PC to that address. */
1728 pc
= regcache_raw_get_signed (regcache
, rtype_rs (inst
));
1730 case 12: /* SYSCALL */
1732 mips_gdbarch_tdep
*tdep
1733 = (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
1735 if (tdep
->syscall_next_pc
!= NULL
)
1736 pc
= tdep
->syscall_next_pc (get_current_frame ());
1745 break; /* end SPECIAL */
1746 case 1: /* REGIMM */
1748 op
= itype_rt (inst
); /* branch condition */
1753 case 16: /* BLTZAL */
1754 case 18: /* BLTZALL */
1756 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) < 0)
1757 pc
+= mips32_relative_offset (inst
) + 4;
1759 pc
+= 8; /* after the delay slot */
1763 case 17: /* BGEZAL */
1764 case 19: /* BGEZALL */
1765 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) >= 0)
1766 pc
+= mips32_relative_offset (inst
) + 4;
1768 pc
+= 8; /* after the delay slot */
1770 case 0x1c: /* BPOSGE32 */
1771 case 0x1e: /* BPOSGE64 */
1773 if (itype_rs (inst
) == 0)
1775 unsigned int pos
= (op
& 2) ? 64 : 32;
1776 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
1779 /* No way to handle; it'll most likely trap anyway. */
1782 if ((regcache_raw_get_unsigned (regcache
,
1783 dspctl
) & 0x7f) >= pos
)
1784 pc
+= mips32_relative_offset (inst
);
1789 /* All of the other instructions in the REGIMM category */
1794 break; /* end REGIMM */
1799 reg
= jtype_target (inst
) << 2;
1800 /* Upper four bits get never changed... */
1801 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1804 case 4: /* BEQ, BEQL */
1806 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) ==
1807 regcache_raw_get_signed (regcache
, itype_rt (inst
)))
1808 pc
+= mips32_relative_offset (inst
) + 4;
1812 case 5: /* BNE, BNEL */
1814 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) !=
1815 regcache_raw_get_signed (regcache
, itype_rt (inst
)))
1816 pc
+= mips32_relative_offset (inst
) + 4;
1820 case 6: /* BLEZ, BLEZL */
1821 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) <= 0)
1822 pc
+= mips32_relative_offset (inst
) + 4;
1828 greater_branch
: /* BGTZ, BGTZL */
1829 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) > 0)
1830 pc
+= mips32_relative_offset (inst
) + 4;
1837 } /* mips32_next_pc */
1839 /* Extract the 7-bit signed immediate offset from the microMIPS instruction
1843 micromips_relative_offset7 (ULONGEST insn
)
1845 return ((b0s7_imm (insn
) ^ 0x40) - 0x40) << 1;
1848 /* Extract the 10-bit signed immediate offset from the microMIPS instruction
1852 micromips_relative_offset10 (ULONGEST insn
)
1854 return ((b0s10_imm (insn
) ^ 0x200) - 0x200) << 1;
1857 /* Extract the 16-bit signed immediate offset from the microMIPS instruction
1861 micromips_relative_offset16 (ULONGEST insn
)
1863 return ((b0s16_imm (insn
) ^ 0x8000) - 0x8000) << 1;
1866 /* Return the size in bytes of the microMIPS instruction at the address PC. */
1869 micromips_pc_insn_size (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1873 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1874 return mips_insn_size (ISA_MICROMIPS
, insn
);
1877 /* Calculate the address of the next microMIPS instruction to execute
1878 after the INSN coprocessor 1 conditional branch instruction at the
1879 address PC. COUNT denotes the number of coprocessor condition bits
1880 examined by the branch. */
1883 micromips_bc1_pc (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1884 ULONGEST insn
, CORE_ADDR pc
, int count
)
1886 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1887 int cnum
= b2s3_cc (insn
>> 16) & (count
- 1);
1888 int tf
= b5s5_op (insn
>> 16) & 1;
1889 int mask
= (1 << count
) - 1;
1894 /* No way to handle; it'll most likely trap anyway. */
1897 fcs
= regcache_raw_get_unsigned (regcache
, fcsr
);
1898 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1900 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1901 pc
+= micromips_relative_offset16 (insn
);
1903 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1908 /* Calculate the address of the next microMIPS instruction to execute
1909 after the instruction at the address PC. */
1912 micromips_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1914 struct gdbarch
*gdbarch
= regcache
->arch ();
1917 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1918 pc
+= MIPS_INSN16_SIZE
;
1919 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
1921 /* 32-bit instructions. */
1922 case 2 * MIPS_INSN16_SIZE
:
1924 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1925 pc
+= MIPS_INSN16_SIZE
;
1926 switch (micromips_op (insn
>> 16))
1928 case 0x00: /* POOL32A: bits 000000 */
1929 switch (b0s6_op (insn
))
1931 case 0x3c: /* POOL32Axf: bits 000000 ... 111100 */
1932 switch (b6s10_ext (insn
))
1934 case 0x3c: /* JALR: 000000 0000111100 111100 */
1935 case 0x7c: /* JALR.HB: 000000 0001111100 111100 */
1936 case 0x13c: /* JALRS: 000000 0100111100 111100 */
1937 case 0x17c: /* JALRS.HB: 000000 0101111100 111100 */
1938 pc
= regcache_raw_get_signed (regcache
,
1939 b0s5_reg (insn
>> 16));
1941 case 0x22d: /* SYSCALL: 000000 1000101101 111100 */
1943 mips_gdbarch_tdep
*tdep
1944 = (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
1946 if (tdep
->syscall_next_pc
!= NULL
)
1947 pc
= tdep
->syscall_next_pc (get_current_frame ());
1955 case 0x10: /* POOL32I: bits 010000 */
1956 switch (b5s5_op (insn
>> 16))
1958 case 0x00: /* BLTZ: bits 010000 00000 */
1959 case 0x01: /* BLTZAL: bits 010000 00001 */
1960 case 0x11: /* BLTZALS: bits 010000 10001 */
1961 if (regcache_raw_get_signed (regcache
,
1962 b0s5_reg (insn
>> 16)) < 0)
1963 pc
+= micromips_relative_offset16 (insn
);
1965 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1968 case 0x02: /* BGEZ: bits 010000 00010 */
1969 case 0x03: /* BGEZAL: bits 010000 00011 */
1970 case 0x13: /* BGEZALS: bits 010000 10011 */
1971 if (regcache_raw_get_signed (regcache
,
1972 b0s5_reg (insn
>> 16)) >= 0)
1973 pc
+= micromips_relative_offset16 (insn
);
1975 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1978 case 0x04: /* BLEZ: bits 010000 00100 */
1979 if (regcache_raw_get_signed (regcache
,
1980 b0s5_reg (insn
>> 16)) <= 0)
1981 pc
+= micromips_relative_offset16 (insn
);
1983 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1986 case 0x05: /* BNEZC: bits 010000 00101 */
1987 if (regcache_raw_get_signed (regcache
,
1988 b0s5_reg (insn
>> 16)) != 0)
1989 pc
+= micromips_relative_offset16 (insn
);
1992 case 0x06: /* BGTZ: bits 010000 00110 */
1993 if (regcache_raw_get_signed (regcache
,
1994 b0s5_reg (insn
>> 16)) > 0)
1995 pc
+= micromips_relative_offset16 (insn
);
1997 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2000 case 0x07: /* BEQZC: bits 010000 00111 */
2001 if (regcache_raw_get_signed (regcache
,
2002 b0s5_reg (insn
>> 16)) == 0)
2003 pc
+= micromips_relative_offset16 (insn
);
2006 case 0x14: /* BC2F: bits 010000 10100 xxx00 */
2007 case 0x15: /* BC2T: bits 010000 10101 xxx00 */
2008 if (((insn
>> 16) & 0x3) == 0x0)
2009 /* BC2F, BC2T: don't know how to handle these. */
2013 case 0x1a: /* BPOSGE64: bits 010000 11010 */
2014 case 0x1b: /* BPOSGE32: bits 010000 11011 */
2016 unsigned int pos
= (b5s5_op (insn
>> 16) & 1) ? 32 : 64;
2017 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
2020 /* No way to handle; it'll most likely trap anyway. */
2023 if ((regcache_raw_get_unsigned (regcache
,
2024 dspctl
) & 0x7f) >= pos
)
2025 pc
+= micromips_relative_offset16 (insn
);
2027 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2031 case 0x1c: /* BC1F: bits 010000 11100 xxx00 */
2032 /* BC1ANY2F: bits 010000 11100 xxx01 */
2033 case 0x1d: /* BC1T: bits 010000 11101 xxx00 */
2034 /* BC1ANY2T: bits 010000 11101 xxx01 */
2035 if (((insn
>> 16) & 0x2) == 0x0)
2036 pc
= micromips_bc1_pc (gdbarch
, regcache
, insn
, pc
,
2037 ((insn
>> 16) & 0x1) + 1);
2040 case 0x1e: /* BC1ANY4F: bits 010000 11110 xxx01 */
2041 case 0x1f: /* BC1ANY4T: bits 010000 11111 xxx01 */
2042 if (((insn
>> 16) & 0x3) == 0x1)
2043 pc
= micromips_bc1_pc (gdbarch
, regcache
, insn
, pc
, 4);
2048 case 0x1d: /* JALS: bits 011101 */
2049 case 0x35: /* J: bits 110101 */
2050 case 0x3d: /* JAL: bits 111101 */
2051 pc
= ((pc
| 0x7fffffe) ^ 0x7fffffe) | (b0s26_imm (insn
) << 1);
2054 case 0x25: /* BEQ: bits 100101 */
2055 if (regcache_raw_get_signed (regcache
, b0s5_reg (insn
>> 16))
2056 == regcache_raw_get_signed (regcache
, b5s5_reg (insn
>> 16)))
2057 pc
+= micromips_relative_offset16 (insn
);
2059 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2062 case 0x2d: /* BNE: bits 101101 */
2063 if (regcache_raw_get_signed (regcache
, b0s5_reg (insn
>> 16))
2064 != regcache_raw_get_signed (regcache
, b5s5_reg (insn
>> 16)))
2065 pc
+= micromips_relative_offset16 (insn
);
2067 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2070 case 0x3c: /* JALX: bits 111100 */
2071 pc
= ((pc
| 0xfffffff) ^ 0xfffffff) | (b0s26_imm (insn
) << 2);
2076 /* 16-bit instructions. */
2077 case MIPS_INSN16_SIZE
:
2078 switch (micromips_op (insn
))
2080 case 0x11: /* POOL16C: bits 010001 */
2081 if ((b5s5_op (insn
) & 0x1c) == 0xc)
2082 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
2083 pc
= regcache_raw_get_signed (regcache
, b0s5_reg (insn
));
2084 else if (b5s5_op (insn
) == 0x18)
2085 /* JRADDIUSP: bits 010001 11000 */
2086 pc
= regcache_raw_get_signed (regcache
, MIPS_RA_REGNUM
);
2089 case 0x23: /* BEQZ16: bits 100011 */
2091 int rs
= mips_reg3_to_reg
[b7s3_reg (insn
)];
2093 if (regcache_raw_get_signed (regcache
, rs
) == 0)
2094 pc
+= micromips_relative_offset7 (insn
);
2096 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2100 case 0x2b: /* BNEZ16: bits 101011 */
2102 int rs
= mips_reg3_to_reg
[b7s3_reg (insn
)];
2104 if (regcache_raw_get_signed (regcache
, rs
) != 0)
2105 pc
+= micromips_relative_offset7 (insn
);
2107 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2111 case 0x33: /* B16: bits 110011 */
2112 pc
+= micromips_relative_offset10 (insn
);
2121 /* Decoding the next place to set a breakpoint is irregular for the
2122 mips 16 variant, but fortunately, there fewer instructions. We have
2123 to cope ith extensions for 16 bit instructions and a pair of actual
2124 32 bit instructions. We dont want to set a single step instruction
2125 on the extend instruction either. */
2127 /* Lots of mips16 instruction formats */
2128 /* Predicting jumps requires itype,ritype,i8type
2129 and their extensions extItype,extritype,extI8type. */
2130 enum mips16_inst_fmts
2132 itype
, /* 0 immediate 5,10 */
2133 ritype
, /* 1 5,3,8 */
2134 rrtype
, /* 2 5,3,3,5 */
2135 rritype
, /* 3 5,3,3,5 */
2136 rrrtype
, /* 4 5,3,3,3,2 */
2137 rriatype
, /* 5 5,3,3,1,4 */
2138 shifttype
, /* 6 5,3,3,3,2 */
2139 i8type
, /* 7 5,3,8 */
2140 i8movtype
, /* 8 5,3,3,5 */
2141 i8mov32rtype
, /* 9 5,3,5,3 */
2142 i64type
, /* 10 5,3,8 */
2143 ri64type
, /* 11 5,3,3,5 */
2144 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
2145 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
2146 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
2147 extRRItype
, /* 15 5,5,5,5,3,3,5 */
2148 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
2149 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
2150 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
2151 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
2152 extRi64type
, /* 20 5,6,5,5,3,3,5 */
2153 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
2155 /* I am heaping all the fields of the formats into one structure and
2156 then, only the fields which are involved in instruction extension. */
2160 unsigned int regx
; /* Function in i8 type. */
2165 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
2166 for the bits which make up the immediate extension. */
2169 extended_offset (unsigned int extension
)
2173 value
= (extension
>> 16) & 0x1f; /* Extract 15:11. */
2175 value
|= (extension
>> 21) & 0x3f; /* Extract 10:5. */
2177 value
|= extension
& 0x1f; /* Extract 4:0. */
2182 /* Only call this function if you know that this is an extendable
2183 instruction. It won't malfunction, but why make excess remote memory
2184 references? If the immediate operands get sign extended or something,
2185 do it after the extension is performed. */
2186 /* FIXME: Every one of these cases needs to worry about sign extension
2187 when the offset is to be used in relative addressing. */
2190 fetch_mips_16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2192 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2195 pc
= unmake_compact_addr (pc
); /* Clear the low order bit. */
2196 target_read_memory (pc
, buf
, 2);
2197 return extract_unsigned_integer (buf
, 2, byte_order
);
2201 unpack_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
2202 unsigned int extension
,
2204 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
2209 switch (insn_format
)
2216 value
= extended_offset ((extension
<< 16) | inst
);
2217 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
2221 value
= inst
& 0x7ff;
2222 value
= (value
^ 0x400) - 0x400; /* Sign-extend. */
2231 { /* A register identifier and an offset. */
2232 /* Most of the fields are the same as I type but the
2233 immediate value is of a different length. */
2237 value
= extended_offset ((extension
<< 16) | inst
);
2238 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
2242 value
= inst
& 0xff; /* 8 bits */
2243 value
= (value
^ 0x80) - 0x80; /* Sign-extend. */
2246 regx
= (inst
>> 8) & 0x07; /* i8 funct */
2252 unsigned long value
;
2253 unsigned int nexthalf
;
2254 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
2255 value
= value
<< 16;
2256 nexthalf
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, pc
+ 2, NULL
);
2257 /* Low bit still set. */
2265 internal_error (__FILE__
, __LINE__
, _("bad switch"));
2267 upk
->offset
= offset
;
2273 /* Calculate the destination of a branch whose 16-bit opcode word is at PC,
2274 and having a signed 16-bit OFFSET. */
2277 add_offset_16 (CORE_ADDR pc
, int offset
)
2279 return pc
+ (offset
<< 1) + 2;
2283 extended_mips16_next_pc (regcache
*regcache
, CORE_ADDR pc
,
2284 unsigned int extension
, unsigned int insn
)
2286 struct gdbarch
*gdbarch
= regcache
->arch ();
2287 int op
= (insn
>> 11);
2290 case 2: /* Branch */
2292 struct upk_mips16 upk
;
2293 unpack_mips16 (gdbarch
, pc
, extension
, insn
, itype
, &upk
);
2294 pc
= add_offset_16 (pc
, upk
.offset
);
2297 case 3: /* JAL , JALX - Watch out, these are 32 bit
2300 struct upk_mips16 upk
;
2301 unpack_mips16 (gdbarch
, pc
, extension
, insn
, jalxtype
, &upk
);
2302 pc
= ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)) | (upk
.offset
<< 2);
2303 if ((insn
>> 10) & 0x01) /* Exchange mode */
2304 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode. */
2311 struct upk_mips16 upk
;
2313 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
2314 reg
= regcache_raw_get_signed (regcache
, mips_reg3_to_reg
[upk
.regx
]);
2316 pc
= add_offset_16 (pc
, upk
.offset
);
2323 struct upk_mips16 upk
;
2325 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
2326 reg
= regcache_raw_get_signed (regcache
, mips_reg3_to_reg
[upk
.regx
]);
2328 pc
= add_offset_16 (pc
, upk
.offset
);
2333 case 12: /* I8 Formats btez btnez */
2335 struct upk_mips16 upk
;
2337 unpack_mips16 (gdbarch
, pc
, extension
, insn
, i8type
, &upk
);
2338 /* upk.regx contains the opcode */
2339 /* Test register is 24 */
2340 reg
= regcache_raw_get_signed (regcache
, 24);
2341 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
2342 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
2343 pc
= add_offset_16 (pc
, upk
.offset
);
2348 case 29: /* RR Formats JR, JALR, JALR-RA */
2350 struct upk_mips16 upk
;
2351 /* upk.fmt = rrtype; */
2356 upk
.regx
= (insn
>> 8) & 0x07;
2357 upk
.regy
= (insn
>> 5) & 0x07;
2358 if ((upk
.regy
& 1) == 0)
2359 reg
= mips_reg3_to_reg
[upk
.regx
];
2361 reg
= 31; /* Function return instruction. */
2362 pc
= regcache_raw_get_signed (regcache
, reg
);
2369 /* This is an instruction extension. Fetch the real instruction
2370 (which follows the extension) and decode things based on
2374 pc
= extended_mips16_next_pc (regcache
, pc
, insn
,
2375 fetch_mips_16 (gdbarch
, pc
));
2388 mips16_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
2390 struct gdbarch
*gdbarch
= regcache
->arch ();
2391 unsigned int insn
= fetch_mips_16 (gdbarch
, pc
);
2392 return extended_mips16_next_pc (regcache
, pc
, 0, insn
);
2395 /* The mips_next_pc function supports single_step when the remote
2396 target monitor or stub is not developed enough to do a single_step.
2397 It works by decoding the current instruction and predicting where a
2398 branch will go. This isn't hard because all the data is available.
2399 The MIPS32, MIPS16 and microMIPS variants are quite different. */
2401 mips_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
2403 struct gdbarch
*gdbarch
= regcache
->arch ();
2405 if (mips_pc_is_mips16 (gdbarch
, pc
))
2406 return mips16_next_pc (regcache
, pc
);
2407 else if (mips_pc_is_micromips (gdbarch
, pc
))
2408 return micromips_next_pc (regcache
, pc
);
2410 return mips32_next_pc (regcache
, pc
);
2413 /* Return non-zero if the MIPS16 instruction INSN is a compact branch
2417 mips16_instruction_is_compact_branch (unsigned short insn
)
2419 switch (insn
& 0xf800)
2422 return (insn
& 0x009f) == 0x80; /* JALRC/JRC */
2424 return (insn
& 0x0600) == 0; /* BTNEZ/BTEQZ */
2425 case 0x2800: /* BNEZ */
2426 case 0x2000: /* BEQZ */
2427 case 0x1000: /* B */
2434 /* Return non-zero if the microMIPS instruction INSN is a compact branch
2438 micromips_instruction_is_compact_branch (unsigned short insn
)
2440 switch (micromips_op (insn
))
2442 case 0x11: /* POOL16C: bits 010001 */
2443 return (b5s5_op (insn
) == 0x18
2444 /* JRADDIUSP: bits 010001 11000 */
2445 || b5s5_op (insn
) == 0xd);
2446 /* JRC: bits 010011 01101 */
2447 case 0x10: /* POOL32I: bits 010000 */
2448 return (b5s5_op (insn
) & 0x1d) == 0x5;
2449 /* BEQZC/BNEZC: bits 010000 001x1 */
2455 struct mips_frame_cache
2458 trad_frame_saved_reg
*saved_regs
;
2461 /* Set a register's saved stack address in temp_saved_regs. If an
2462 address has already been set for this register, do nothing; this
2463 way we will only recognize the first save of a given register in a
2466 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
2467 [gdbarch_num_regs .. 2*gdbarch_num_regs).
2468 Strictly speaking, only the second range is used as it is only second
2469 range (the ABI instead of ISA registers) that comes into play when finding
2470 saved registers in a frame. */
2473 set_reg_offset (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
,
2474 int regnum
, CORE_ADDR offset
)
2476 if (this_cache
!= NULL
2477 && this_cache
->saved_regs
[regnum
].is_realreg ()
2478 && this_cache
->saved_regs
[regnum
].realreg () == regnum
)
2480 this_cache
->saved_regs
[regnum
+ 0
2481 * gdbarch_num_regs (gdbarch
)].set_addr (offset
);
2482 this_cache
->saved_regs
[regnum
+ 1
2483 * gdbarch_num_regs (gdbarch
)].set_addr (offset
);
2488 /* Fetch the immediate value from a MIPS16 instruction.
2489 If the previous instruction was an EXTEND, use it to extend
2490 the upper bits of the immediate value. This is a helper function
2491 for mips16_scan_prologue. */
2494 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
2495 unsigned short inst
, /* current instruction */
2496 int nbits
, /* number of bits in imm field */
2497 int scale
, /* scale factor to be applied to imm */
2498 int is_signed
) /* is the imm field signed? */
2502 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
2504 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
2505 if (offset
& 0x8000) /* check for negative extend */
2506 offset
= 0 - (0x10000 - (offset
& 0xffff));
2507 return offset
| (inst
& 0x1f);
2511 int max_imm
= 1 << nbits
;
2512 int mask
= max_imm
- 1;
2513 int sign_bit
= max_imm
>> 1;
2515 offset
= inst
& mask
;
2516 if (is_signed
&& (offset
& sign_bit
))
2517 offset
= 0 - (max_imm
- offset
);
2518 return offset
* scale
;
2523 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
2524 the associated FRAME_CACHE if not null.
2525 Return the address of the first instruction past the prologue. */
2528 mips16_scan_prologue (struct gdbarch
*gdbarch
,
2529 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2530 struct frame_info
*this_frame
,
2531 struct mips_frame_cache
*this_cache
)
2533 int prev_non_prologue_insn
= 0;
2534 int this_non_prologue_insn
;
2535 int non_prologue_insns
= 0;
2538 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer. */
2540 long frame_offset
= 0; /* Size of stack frame. */
2541 long frame_adjust
= 0; /* Offset of FP from SP. */
2542 int frame_reg
= MIPS_SP_REGNUM
;
2543 unsigned short prev_inst
= 0; /* saved copy of previous instruction. */
2544 unsigned inst
= 0; /* current instruction */
2545 unsigned entry_inst
= 0; /* the entry instruction */
2546 unsigned save_inst
= 0; /* the save instruction */
2547 int prev_delay_slot
= 0;
2551 int extend_bytes
= 0;
2552 int prev_extend_bytes
= 0;
2553 CORE_ADDR end_prologue_addr
;
2555 /* Can be called when there's no process, and hence when there's no
2557 if (this_frame
!= NULL
)
2558 sp
= get_frame_register_signed (this_frame
,
2559 gdbarch_num_regs (gdbarch
)
2564 if (limit_pc
> start_pc
+ 200)
2565 limit_pc
= start_pc
+ 200;
2568 /* Permit at most one non-prologue non-control-transfer instruction
2569 in the middle which may have been reordered by the compiler for
2571 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
2573 this_non_prologue_insn
= 0;
2576 /* Save the previous instruction. If it's an EXTEND, we'll extract
2577 the immediate offset extension from it in mips16_get_imm. */
2580 /* Fetch and decode the instruction. */
2581 inst
= (unsigned short) mips_fetch_instruction (gdbarch
, ISA_MIPS16
,
2584 /* Normally we ignore extend instructions. However, if it is
2585 not followed by a valid prologue instruction, then this
2586 instruction is not part of the prologue either. We must
2587 remember in this case to adjust the end_prologue_addr back
2589 if ((inst
& 0xf800) == 0xf000) /* extend */
2591 extend_bytes
= MIPS_INSN16_SIZE
;
2595 prev_extend_bytes
= extend_bytes
;
2598 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2599 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2601 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
2602 if (offset
< 0) /* Negative stack adjustment? */
2603 frame_offset
-= offset
;
2605 /* Exit loop if a positive stack adjustment is found, which
2606 usually means that the stack cleanup code in the function
2607 epilogue is reached. */
2610 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
2612 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2613 reg
= mips_reg3_to_reg
[(inst
& 0x700) >> 8];
2614 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2616 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
2618 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2619 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2620 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2622 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
2624 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2625 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2627 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2629 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
2630 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2632 else if (inst
== 0x673d) /* move $s1, $sp */
2637 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
2639 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2640 frame_addr
= sp
+ offset
;
2642 frame_adjust
= offset
;
2644 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2646 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
2647 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2648 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
2650 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2652 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2653 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2654 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
2656 else if ((inst
& 0xf81f) == 0xe809
2657 && (inst
& 0x700) != 0x700) /* entry */
2658 entry_inst
= inst
; /* Save for later processing. */
2659 else if ((inst
& 0xff80) == 0x6480) /* save */
2661 save_inst
= inst
; /* Save for later processing. */
2662 if (prev_extend_bytes
) /* extend */
2663 save_inst
|= prev_inst
<< 16;
2665 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
2667 /* This instruction is part of the prologue, but we don't
2668 need to do anything special to handle it. */
2670 else if (mips16_instruction_has_delay_slot (inst
, 0))
2671 /* JAL/JALR/JALX/JR */
2673 /* The instruction in the delay slot can be a part
2674 of the prologue, so move forward once more. */
2676 if (mips16_instruction_has_delay_slot (inst
, 1))
2679 prev_extend_bytes
= MIPS_INSN16_SIZE
;
2680 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
2685 this_non_prologue_insn
= 1;
2688 non_prologue_insns
+= this_non_prologue_insn
;
2690 /* A jump or branch, or enough non-prologue insns seen? If so,
2691 then we must have reached the end of the prologue by now. */
2692 if (prev_delay_slot
|| non_prologue_insns
> 1
2693 || mips16_instruction_is_compact_branch (inst
))
2696 prev_non_prologue_insn
= this_non_prologue_insn
;
2697 prev_delay_slot
= in_delay_slot
;
2698 prev_pc
= cur_pc
- prev_extend_bytes
;
2701 /* The entry instruction is typically the first instruction in a function,
2702 and it stores registers at offsets relative to the value of the old SP
2703 (before the prologue). But the value of the sp parameter to this
2704 function is the new SP (after the prologue has been executed). So we
2705 can't calculate those offsets until we've seen the entire prologue,
2706 and can calculate what the old SP must have been. */
2707 if (entry_inst
!= 0)
2709 int areg_count
= (entry_inst
>> 8) & 7;
2710 int sreg_count
= (entry_inst
>> 6) & 3;
2712 /* The entry instruction always subtracts 32 from the SP. */
2715 /* Now we can calculate what the SP must have been at the
2716 start of the function prologue. */
2719 /* Check if a0-a3 were saved in the caller's argument save area. */
2720 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
2722 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2723 offset
+= mips_abi_regsize (gdbarch
);
2726 /* Check if the ra register was pushed on the stack. */
2728 if (entry_inst
& 0x20)
2730 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2731 offset
-= mips_abi_regsize (gdbarch
);
2734 /* Check if the s0 and s1 registers were pushed on the stack. */
2735 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2737 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2738 offset
-= mips_abi_regsize (gdbarch
);
2742 /* The SAVE instruction is similar to ENTRY, except that defined by the
2743 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
2744 size of the frame is specified as an immediate field of instruction
2745 and an extended variation exists which lets additional registers and
2746 frame space to be specified. The instruction always treats registers
2747 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
2748 if (save_inst
!= 0 && mips_abi_regsize (gdbarch
) == 4)
2750 static int args_table
[16] = {
2751 0, 0, 0, 0, 1, 1, 1, 1,
2752 2, 2, 2, 0, 3, 3, 4, -1,
2754 static int astatic_table
[16] = {
2755 0, 1, 2, 3, 0, 1, 2, 3,
2756 0, 1, 2, 4, 0, 1, 0, -1,
2758 int aregs
= (save_inst
>> 16) & 0xf;
2759 int xsregs
= (save_inst
>> 24) & 0x7;
2760 int args
= args_table
[aregs
];
2761 int astatic
= astatic_table
[aregs
];
2766 warning (_("Invalid number of argument registers encoded in SAVE."));
2771 warning (_("Invalid number of static registers encoded in SAVE."));
2775 /* For standard SAVE the frame size of 0 means 128. */
2776 frame_size
= ((save_inst
>> 16) & 0xf0) | (save_inst
& 0xf);
2777 if (frame_size
== 0 && (save_inst
>> 16) == 0)
2780 frame_offset
+= frame_size
;
2782 /* Now we can calculate what the SP must have been at the
2783 start of the function prologue. */
2786 /* Check if A0-A3 were saved in the caller's argument save area. */
2787 for (reg
= MIPS_A0_REGNUM
, offset
= 0; reg
< args
+ 4; reg
++)
2789 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2790 offset
+= mips_abi_regsize (gdbarch
);
2795 /* Check if the RA register was pushed on the stack. */
2796 if (save_inst
& 0x40)
2798 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2799 offset
-= mips_abi_regsize (gdbarch
);
2802 /* Check if the S8 register was pushed on the stack. */
2805 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ offset
);
2806 offset
-= mips_abi_regsize (gdbarch
);
2809 /* Check if S2-S7 were pushed on the stack. */
2810 for (reg
= 18 + xsregs
- 1; reg
> 18 - 1; reg
--)
2812 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2813 offset
-= mips_abi_regsize (gdbarch
);
2816 /* Check if the S1 register was pushed on the stack. */
2817 if (save_inst
& 0x10)
2819 set_reg_offset (gdbarch
, this_cache
, 17, sp
+ offset
);
2820 offset
-= mips_abi_regsize (gdbarch
);
2822 /* Check if the S0 register was pushed on the stack. */
2823 if (save_inst
& 0x20)
2825 set_reg_offset (gdbarch
, this_cache
, 16, sp
+ offset
);
2826 offset
-= mips_abi_regsize (gdbarch
);
2829 /* Check if A0-A3 were pushed on the stack. */
2830 for (reg
= MIPS_A0_REGNUM
+ 3; reg
> MIPS_A0_REGNUM
+ 3 - astatic
; reg
--)
2832 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2833 offset
-= mips_abi_regsize (gdbarch
);
2837 if (this_cache
!= NULL
)
2840 (get_frame_register_signed (this_frame
,
2841 gdbarch_num_regs (gdbarch
) + frame_reg
)
2842 + frame_offset
- frame_adjust
);
2843 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
2844 be able to get rid of the assignment below, evetually. But it's
2845 still needed for now. */
2846 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2847 + mips_regnum (gdbarch
)->pc
]
2848 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
2851 /* Set end_prologue_addr to the address of the instruction immediately
2852 after the last one we scanned. Unless the last one looked like a
2853 non-prologue instruction (and we looked ahead), in which case use
2854 its address instead. */
2855 end_prologue_addr
= (prev_non_prologue_insn
|| prev_delay_slot
2856 ? prev_pc
: cur_pc
- prev_extend_bytes
);
2858 return end_prologue_addr
;
2861 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
2862 Procedures that use the 32-bit instruction set are handled by the
2863 mips_insn32 unwinder. */
2865 static struct mips_frame_cache
*
2866 mips_insn16_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2868 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2869 struct mips_frame_cache
*cache
;
2871 if ((*this_cache
) != NULL
)
2872 return (struct mips_frame_cache
*) (*this_cache
);
2873 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2874 (*this_cache
) = cache
;
2875 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2877 /* Analyze the function prologue. */
2879 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2880 CORE_ADDR start_addr
;
2882 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2883 if (start_addr
== 0)
2884 start_addr
= heuristic_proc_start (gdbarch
, pc
);
2885 /* We can't analyze the prologue if we couldn't find the begining
2887 if (start_addr
== 0)
2890 mips16_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
2891 (struct mips_frame_cache
*) *this_cache
);
2894 /* gdbarch_sp_regnum contains the value and not the address. */
2895 cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2896 + MIPS_SP_REGNUM
].set_value (cache
->base
);
2898 return (struct mips_frame_cache
*) (*this_cache
);
2902 mips_insn16_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2903 struct frame_id
*this_id
)
2905 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2907 /* This marks the outermost frame. */
2908 if (info
->base
== 0)
2910 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2913 static struct value
*
2914 mips_insn16_frame_prev_register (struct frame_info
*this_frame
,
2915 void **this_cache
, int regnum
)
2917 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2919 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2923 mips_insn16_frame_sniffer (const struct frame_unwind
*self
,
2924 struct frame_info
*this_frame
, void **this_cache
)
2926 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2927 CORE_ADDR pc
= get_frame_pc (this_frame
);
2928 if (mips_pc_is_mips16 (gdbarch
, pc
))
2933 static const struct frame_unwind mips_insn16_frame_unwind
=
2935 "mips insn16 prologue",
2937 default_frame_unwind_stop_reason
,
2938 mips_insn16_frame_this_id
,
2939 mips_insn16_frame_prev_register
,
2941 mips_insn16_frame_sniffer
2945 mips_insn16_frame_base_address (struct frame_info
*this_frame
,
2948 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2953 static const struct frame_base mips_insn16_frame_base
=
2955 &mips_insn16_frame_unwind
,
2956 mips_insn16_frame_base_address
,
2957 mips_insn16_frame_base_address
,
2958 mips_insn16_frame_base_address
2961 static const struct frame_base
*
2962 mips_insn16_frame_base_sniffer (struct frame_info
*this_frame
)
2964 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2965 CORE_ADDR pc
= get_frame_pc (this_frame
);
2966 if (mips_pc_is_mips16 (gdbarch
, pc
))
2967 return &mips_insn16_frame_base
;
2972 /* Decode a 9-bit signed immediate argument of ADDIUSP -- -2 is mapped
2973 to -258, -1 -- to -257, 0 -- to 256, 1 -- to 257 and other values are
2974 interpreted directly, and then multiplied by 4. */
2977 micromips_decode_imm9 (int imm
)
2979 imm
= (imm
^ 0x100) - 0x100;
2980 if (imm
> -3 && imm
< 2)
2985 /* Analyze the function prologue from START_PC to LIMIT_PC. Return
2986 the address of the first instruction past the prologue. */
2989 micromips_scan_prologue (struct gdbarch
*gdbarch
,
2990 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2991 struct frame_info
*this_frame
,
2992 struct mips_frame_cache
*this_cache
)
2994 CORE_ADDR end_prologue_addr
;
2995 int prev_non_prologue_insn
= 0;
2996 int frame_reg
= MIPS_SP_REGNUM
;
2997 int this_non_prologue_insn
;
2998 int non_prologue_insns
= 0;
2999 long frame_offset
= 0; /* Size of stack frame. */
3000 long frame_adjust
= 0; /* Offset of FP from SP. */
3001 int prev_delay_slot
= 0;
3005 ULONGEST insn
; /* current instruction */
3009 long v1_off
= 0; /* The assumption is LUI will replace it. */
3020 /* Can be called when there's no process, and hence when there's no
3022 if (this_frame
!= NULL
)
3023 sp
= get_frame_register_signed (this_frame
,
3024 gdbarch_num_regs (gdbarch
)
3029 if (limit_pc
> start_pc
+ 200)
3030 limit_pc
= start_pc
+ 200;
3033 /* Permit at most one non-prologue non-control-transfer instruction
3034 in the middle which may have been reordered by the compiler for
3036 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= loc
)
3038 this_non_prologue_insn
= 0;
3042 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, cur_pc
, NULL
);
3043 loc
+= MIPS_INSN16_SIZE
;
3044 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
3046 /* 32-bit instructions. */
3047 case 2 * MIPS_INSN16_SIZE
:
3049 insn
|= mips_fetch_instruction (gdbarch
,
3050 ISA_MICROMIPS
, cur_pc
+ loc
, NULL
);
3051 loc
+= MIPS_INSN16_SIZE
;
3052 switch (micromips_op (insn
>> 16))
3054 /* Record $sp/$fp adjustment. */
3055 /* Discard (D)ADDU $gp,$jp used for PIC code. */
3056 case 0x0: /* POOL32A: bits 000000 */
3057 case 0x16: /* POOL32S: bits 010110 */
3058 op
= b0s11_op (insn
);
3059 sreg
= b0s5_reg (insn
>> 16);
3060 treg
= b5s5_reg (insn
>> 16);
3061 dreg
= b11s5_reg (insn
);
3063 /* SUBU: bits 000000 00111010000 */
3064 /* DSUBU: bits 010110 00111010000 */
3065 && dreg
== MIPS_SP_REGNUM
&& sreg
== MIPS_SP_REGNUM
3067 /* (D)SUBU $sp, $v1 */
3069 else if (op
!= 0x150
3070 /* ADDU: bits 000000 00101010000 */
3071 /* DADDU: bits 010110 00101010000 */
3072 || dreg
!= 28 || sreg
!= 28 || treg
!= MIPS_T9_REGNUM
)
3073 this_non_prologue_insn
= 1;
3076 case 0x8: /* POOL32B: bits 001000 */
3077 op
= b12s4_op (insn
);
3078 breg
= b0s5_reg (insn
>> 16);
3079 reglist
= sreg
= b5s5_reg (insn
>> 16);
3080 offset
= (b0s12_imm (insn
) ^ 0x800) - 0x800;
3081 if ((op
== 0x9 || op
== 0xc)
3082 /* SWP: bits 001000 1001 */
3083 /* SDP: bits 001000 1100 */
3084 && breg
== MIPS_SP_REGNUM
&& sreg
< MIPS_RA_REGNUM
)
3085 /* S[DW]P reg,offset($sp) */
3087 s
= 4 << ((b12s4_op (insn
) & 0x4) == 0x4);
3088 set_reg_offset (gdbarch
, this_cache
,
3090 set_reg_offset (gdbarch
, this_cache
,
3091 sreg
+ 1, sp
+ offset
+ s
);
3093 else if ((op
== 0xd || op
== 0xf)
3094 /* SWM: bits 001000 1101 */
3095 /* SDM: bits 001000 1111 */
3096 && breg
== MIPS_SP_REGNUM
3097 /* SWM reglist,offset($sp) */
3098 && ((reglist
>= 1 && reglist
<= 9)
3099 || (reglist
>= 16 && reglist
<= 25)))
3101 int sreglist
= std::min(reglist
& 0xf, 8);
3103 s
= 4 << ((b12s4_op (insn
) & 0x2) == 0x2);
3104 for (i
= 0; i
< sreglist
; i
++)
3105 set_reg_offset (gdbarch
, this_cache
, 16 + i
, sp
+ s
* i
);
3106 if ((reglist
& 0xf) > 8)
3107 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ s
* i
++);
3108 if ((reglist
& 0x10) == 0x10)
3109 set_reg_offset (gdbarch
, this_cache
,
3110 MIPS_RA_REGNUM
, sp
+ s
* i
++);
3113 this_non_prologue_insn
= 1;
3116 /* Record $sp/$fp adjustment. */
3117 /* Discard (D)ADDIU $gp used for PIC code. */
3118 case 0xc: /* ADDIU: bits 001100 */
3119 case 0x17: /* DADDIU: bits 010111 */
3120 sreg
= b0s5_reg (insn
>> 16);
3121 dreg
= b5s5_reg (insn
>> 16);
3122 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
3123 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
)
3124 /* (D)ADDIU $sp, imm */
3126 else if (sreg
== MIPS_SP_REGNUM
&& dreg
== 30)
3127 /* (D)ADDIU $fp, $sp, imm */
3129 frame_adjust
= offset
;
3132 else if (sreg
!= 28 || dreg
!= 28)
3133 /* (D)ADDIU $gp, imm */
3134 this_non_prologue_insn
= 1;
3137 /* LUI $v1 is used for larger $sp adjustments. */
3138 /* Discard LUI $gp used for PIC code. */
3139 case 0x10: /* POOL32I: bits 010000 */
3140 if (b5s5_op (insn
>> 16) == 0xd
3141 /* LUI: bits 010000 001101 */
3142 && b0s5_reg (insn
>> 16) == 3)
3144 v1_off
= ((b0s16_imm (insn
) << 16) ^ 0x80000000) - 0x80000000;
3145 else if (b5s5_op (insn
>> 16) != 0xd
3146 /* LUI: bits 010000 001101 */
3147 || b0s5_reg (insn
>> 16) != 28)
3149 this_non_prologue_insn
= 1;
3152 /* ORI $v1 is used for larger $sp adjustments. */
3153 case 0x14: /* ORI: bits 010100 */
3154 sreg
= b0s5_reg (insn
>> 16);
3155 dreg
= b5s5_reg (insn
>> 16);
3156 if (sreg
== 3 && dreg
== 3)
3158 v1_off
|= b0s16_imm (insn
);
3160 this_non_prologue_insn
= 1;
3163 case 0x26: /* SWC1: bits 100110 */
3164 case 0x2e: /* SDC1: bits 101110 */
3165 breg
= b0s5_reg (insn
>> 16);
3166 if (breg
!= MIPS_SP_REGNUM
)
3167 /* S[DW]C1 reg,offset($sp) */
3168 this_non_prologue_insn
= 1;
3171 case 0x36: /* SD: bits 110110 */
3172 case 0x3e: /* SW: bits 111110 */
3173 breg
= b0s5_reg (insn
>> 16);
3174 sreg
= b5s5_reg (insn
>> 16);
3175 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
3176 if (breg
== MIPS_SP_REGNUM
)
3177 /* S[DW] reg,offset($sp) */
3178 set_reg_offset (gdbarch
, this_cache
, sreg
, sp
+ offset
);
3180 this_non_prologue_insn
= 1;
3184 /* The instruction in the delay slot can be a part
3185 of the prologue, so move forward once more. */
3186 if (micromips_instruction_has_delay_slot (insn
, 0))
3189 this_non_prologue_insn
= 1;
3195 /* 16-bit instructions. */
3196 case MIPS_INSN16_SIZE
:
3197 switch (micromips_op (insn
))
3199 case 0x3: /* MOVE: bits 000011 */
3200 sreg
= b0s5_reg (insn
);
3201 dreg
= b5s5_reg (insn
);
3202 if (sreg
== MIPS_SP_REGNUM
&& dreg
== 30)
3205 else if ((sreg
& 0x1c) != 0x4)
3206 /* MOVE reg, $a0-$a3 */
3207 this_non_prologue_insn
= 1;
3210 case 0x11: /* POOL16C: bits 010001 */
3211 if (b6s4_op (insn
) == 0x5)
3212 /* SWM: bits 010001 0101 */
3214 offset
= ((b0s4_imm (insn
) << 2) ^ 0x20) - 0x20;
3215 reglist
= b4s2_regl (insn
);
3216 for (i
= 0; i
<= reglist
; i
++)
3217 set_reg_offset (gdbarch
, this_cache
, 16 + i
, sp
+ 4 * i
);
3218 set_reg_offset (gdbarch
, this_cache
,
3219 MIPS_RA_REGNUM
, sp
+ 4 * i
++);
3222 this_non_prologue_insn
= 1;
3225 case 0x13: /* POOL16D: bits 010011 */
3226 if ((insn
& 0x1) == 0x1)
3227 /* ADDIUSP: bits 010011 1 */
3228 sp_adj
= micromips_decode_imm9 (b1s9_imm (insn
));
3229 else if (b5s5_reg (insn
) == MIPS_SP_REGNUM
)
3230 /* ADDIUS5: bits 010011 0 */
3231 /* ADDIUS5 $sp, imm */
3232 sp_adj
= (b1s4_imm (insn
) ^ 8) - 8;
3234 this_non_prologue_insn
= 1;
3237 case 0x32: /* SWSP: bits 110010 */
3238 offset
= b0s5_imm (insn
) << 2;
3239 sreg
= b5s5_reg (insn
);
3240 set_reg_offset (gdbarch
, this_cache
, sreg
, sp
+ offset
);
3244 /* The instruction in the delay slot can be a part
3245 of the prologue, so move forward once more. */
3246 if (micromips_instruction_has_delay_slot (insn
<< 16, 0))
3249 this_non_prologue_insn
= 1;
3255 frame_offset
-= sp_adj
;
3257 non_prologue_insns
+= this_non_prologue_insn
;
3259 /* A jump or branch, enough non-prologue insns seen or positive
3260 stack adjustment? If so, then we must have reached the end
3261 of the prologue by now. */
3262 if (prev_delay_slot
|| non_prologue_insns
> 1 || sp_adj
> 0
3263 || micromips_instruction_is_compact_branch (insn
))
3266 prev_non_prologue_insn
= this_non_prologue_insn
;
3267 prev_delay_slot
= in_delay_slot
;
3271 if (this_cache
!= NULL
)
3274 (get_frame_register_signed (this_frame
,
3275 gdbarch_num_regs (gdbarch
) + frame_reg
)
3276 + frame_offset
- frame_adjust
);
3277 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
3278 be able to get rid of the assignment below, evetually. But it's
3279 still needed for now. */
3280 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3281 + mips_regnum (gdbarch
)->pc
]
3282 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
3285 /* Set end_prologue_addr to the address of the instruction immediately
3286 after the last one we scanned. Unless the last one looked like a
3287 non-prologue instruction (and we looked ahead), in which case use
3288 its address instead. */
3290 = prev_non_prologue_insn
|| prev_delay_slot
? prev_pc
: cur_pc
;
3292 return end_prologue_addr
;
3295 /* Heuristic unwinder for procedures using microMIPS instructions.
3296 Procedures that use the 32-bit instruction set are handled by the
3297 mips_insn32 unwinder. Likewise MIPS16 and the mips_insn16 unwinder. */
3299 static struct mips_frame_cache
*
3300 mips_micro_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3302 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3303 struct mips_frame_cache
*cache
;
3305 if ((*this_cache
) != NULL
)
3306 return (struct mips_frame_cache
*) (*this_cache
);
3308 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
3309 (*this_cache
) = cache
;
3310 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3312 /* Analyze the function prologue. */
3314 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3315 CORE_ADDR start_addr
;
3317 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3318 if (start_addr
== 0)
3319 start_addr
= heuristic_proc_start (get_frame_arch (this_frame
), pc
);
3320 /* We can't analyze the prologue if we couldn't find the begining
3322 if (start_addr
== 0)
3325 micromips_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
3326 (struct mips_frame_cache
*) *this_cache
);
3329 /* gdbarch_sp_regnum contains the value and not the address. */
3330 cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3331 + MIPS_SP_REGNUM
].set_value (cache
->base
);
3333 return (struct mips_frame_cache
*) (*this_cache
);
3337 mips_micro_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3338 struct frame_id
*this_id
)
3340 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3342 /* This marks the outermost frame. */
3343 if (info
->base
== 0)
3345 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3348 static struct value
*
3349 mips_micro_frame_prev_register (struct frame_info
*this_frame
,
3350 void **this_cache
, int regnum
)
3352 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3354 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3358 mips_micro_frame_sniffer (const struct frame_unwind
*self
,
3359 struct frame_info
*this_frame
, void **this_cache
)
3361 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3362 CORE_ADDR pc
= get_frame_pc (this_frame
);
3364 if (mips_pc_is_micromips (gdbarch
, pc
))
3369 static const struct frame_unwind mips_micro_frame_unwind
=
3371 "mips micro prologue",
3373 default_frame_unwind_stop_reason
,
3374 mips_micro_frame_this_id
,
3375 mips_micro_frame_prev_register
,
3377 mips_micro_frame_sniffer
3381 mips_micro_frame_base_address (struct frame_info
*this_frame
,
3384 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3389 static const struct frame_base mips_micro_frame_base
=
3391 &mips_micro_frame_unwind
,
3392 mips_micro_frame_base_address
,
3393 mips_micro_frame_base_address
,
3394 mips_micro_frame_base_address
3397 static const struct frame_base
*
3398 mips_micro_frame_base_sniffer (struct frame_info
*this_frame
)
3400 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3401 CORE_ADDR pc
= get_frame_pc (this_frame
);
3403 if (mips_pc_is_micromips (gdbarch
, pc
))
3404 return &mips_micro_frame_base
;
3409 /* Mark all the registers as unset in the saved_regs array
3410 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
3413 reset_saved_regs (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
)
3415 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
3419 const int num_regs
= gdbarch_num_regs (gdbarch
);
3422 /* Reset the register values to their default state. Register i's value
3423 is in register i. */
3424 for (i
= 0; i
< num_regs
; i
++)
3425 this_cache
->saved_regs
[i
].set_realreg (i
);
3429 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
3430 the associated FRAME_CACHE if not null.
3431 Return the address of the first instruction past the prologue. */
3434 mips32_scan_prologue (struct gdbarch
*gdbarch
,
3435 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
3436 struct frame_info
*this_frame
,
3437 struct mips_frame_cache
*this_cache
)
3439 int prev_non_prologue_insn
;
3440 int this_non_prologue_insn
;
3441 int non_prologue_insns
;
3442 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for
3444 int prev_delay_slot
;
3449 int frame_reg
= MIPS_SP_REGNUM
;
3451 CORE_ADDR end_prologue_addr
;
3452 int seen_sp_adjust
= 0;
3453 int load_immediate_bytes
= 0;
3455 int regsize_is_64_bits
= (mips_abi_regsize (gdbarch
) == 8);
3457 /* Can be called when there's no process, and hence when there's no
3459 if (this_frame
!= NULL
)
3460 sp
= get_frame_register_signed (this_frame
,
3461 gdbarch_num_regs (gdbarch
)
3466 if (limit_pc
> start_pc
+ 200)
3467 limit_pc
= start_pc
+ 200;
3470 prev_non_prologue_insn
= 0;
3471 non_prologue_insns
= 0;
3472 prev_delay_slot
= 0;
3475 /* Permit at most one non-prologue non-control-transfer instruction
3476 in the middle which may have been reordered by the compiler for
3479 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
3481 unsigned long inst
, high_word
;
3485 this_non_prologue_insn
= 0;
3488 /* Fetch the instruction. */
3489 inst
= (unsigned long) mips_fetch_instruction (gdbarch
, ISA_MIPS
,
3492 /* Save some code by pre-extracting some useful fields. */
3493 high_word
= (inst
>> 16) & 0xffff;
3494 offset
= ((inst
& 0xffff) ^ 0x8000) - 0x8000;
3495 reg
= high_word
& 0x1f;
3497 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
3498 || high_word
== 0x23bd /* addi $sp,$sp,-i */
3499 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
3501 if (offset
< 0) /* Negative stack adjustment? */
3502 frame_offset
-= offset
;
3504 /* Exit loop if a positive stack adjustment is found, which
3505 usually means that the stack cleanup code in the function
3506 epilogue is reached. */
3510 else if (((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
3511 && !regsize_is_64_bits
)
3513 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
3515 else if (((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
3516 && regsize_is_64_bits
)
3518 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
3519 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
3521 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
3523 /* Old gcc frame, r30 is virtual frame pointer. */
3524 if (offset
!= frame_offset
)
3525 frame_addr
= sp
+ offset
;
3526 else if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
3528 unsigned alloca_adjust
;
3531 frame_addr
= get_frame_register_signed
3532 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
3535 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ offset
));
3536 if (alloca_adjust
> 0)
3538 /* FP > SP + frame_size. This may be because of
3539 an alloca or somethings similar. Fix sp to
3540 "pre-alloca" value, and try again. */
3541 sp
+= alloca_adjust
;
3542 /* Need to reset the status of all registers. Otherwise,
3543 we will hit a guard that prevents the new address
3544 for each register to be recomputed during the second
3546 reset_saved_regs (gdbarch
, this_cache
);
3551 /* move $30,$sp. With different versions of gas this will be either
3552 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
3553 Accept any one of these. */
3554 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
3556 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
3557 if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
3559 unsigned alloca_adjust
;
3562 frame_addr
= get_frame_register_signed
3563 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
3565 alloca_adjust
= (unsigned) (frame_addr
- sp
);
3566 if (alloca_adjust
> 0)
3568 /* FP > SP + frame_size. This may be because of
3569 an alloca or somethings similar. Fix sp to
3570 "pre-alloca" value, and try again. */
3572 /* Need to reset the status of all registers. Otherwise,
3573 we will hit a guard that prevents the new address
3574 for each register to be recomputed during the second
3576 reset_saved_regs (gdbarch
, this_cache
);
3581 else if ((high_word
& 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
3582 && !regsize_is_64_bits
)
3584 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
3586 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
3587 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
3588 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
3589 || high_word
== 0x3c1c /* lui $gp,n */
3590 || high_word
== 0x279c /* addiu $gp,$gp,n */
3591 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
3592 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
3595 /* These instructions are part of the prologue, but we don't
3596 need to do anything special to handle them. */
3598 /* The instructions below load $at or $t0 with an immediate
3599 value in preparation for a stack adjustment via
3600 subu $sp,$sp,[$at,$t0]. These instructions could also
3601 initialize a local variable, so we accept them only before
3602 a stack adjustment instruction was seen. */
3603 else if (!seen_sp_adjust
3605 && (high_word
== 0x3c01 /* lui $at,n */
3606 || high_word
== 0x3c08 /* lui $t0,n */
3607 || high_word
== 0x3421 /* ori $at,$at,n */
3608 || high_word
== 0x3508 /* ori $t0,$t0,n */
3609 || high_word
== 0x3401 /* ori $at,$zero,n */
3610 || high_word
== 0x3408 /* ori $t0,$zero,n */
3613 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
3615 /* Check for branches and jumps. The instruction in the delay
3616 slot can be a part of the prologue, so move forward once more. */
3617 else if (mips32_instruction_has_delay_slot (gdbarch
, inst
))
3621 /* This instruction is not an instruction typically found
3622 in a prologue, so we must have reached the end of the
3626 this_non_prologue_insn
= 1;
3629 non_prologue_insns
+= this_non_prologue_insn
;
3631 /* A jump or branch, or enough non-prologue insns seen? If so,
3632 then we must have reached the end of the prologue by now. */
3633 if (prev_delay_slot
|| non_prologue_insns
> 1)
3636 prev_non_prologue_insn
= this_non_prologue_insn
;
3637 prev_delay_slot
= in_delay_slot
;
3641 if (this_cache
!= NULL
)
3644 (get_frame_register_signed (this_frame
,
3645 gdbarch_num_regs (gdbarch
) + frame_reg
)
3647 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
3648 this assignment below, eventually. But it's still needed
3650 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3651 + mips_regnum (gdbarch
)->pc
]
3652 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3656 /* Set end_prologue_addr to the address of the instruction immediately
3657 after the last one we scanned. Unless the last one looked like a
3658 non-prologue instruction (and we looked ahead), in which case use
3659 its address instead. */
3661 = prev_non_prologue_insn
|| prev_delay_slot
? prev_pc
: cur_pc
;
3663 /* In a frameless function, we might have incorrectly
3664 skipped some load immediate instructions. Undo the skipping
3665 if the load immediate was not followed by a stack adjustment. */
3666 if (load_immediate_bytes
&& !seen_sp_adjust
)
3667 end_prologue_addr
-= load_immediate_bytes
;
3669 return end_prologue_addr
;
3672 /* Heuristic unwinder for procedures using 32-bit instructions (covers
3673 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
3674 instructions (a.k.a. MIPS16) are handled by the mips_insn16
3675 unwinder. Likewise microMIPS and the mips_micro unwinder. */
3677 static struct mips_frame_cache
*
3678 mips_insn32_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3680 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3681 struct mips_frame_cache
*cache
;
3683 if ((*this_cache
) != NULL
)
3684 return (struct mips_frame_cache
*) (*this_cache
);
3686 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
3687 (*this_cache
) = cache
;
3688 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3690 /* Analyze the function prologue. */
3692 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3693 CORE_ADDR start_addr
;
3695 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3696 if (start_addr
== 0)
3697 start_addr
= heuristic_proc_start (gdbarch
, pc
);
3698 /* We can't analyze the prologue if we couldn't find the begining
3700 if (start_addr
== 0)
3703 mips32_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
3704 (struct mips_frame_cache
*) *this_cache
);
3707 /* gdbarch_sp_regnum contains the value and not the address. */
3708 cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3709 + MIPS_SP_REGNUM
].set_value (cache
->base
);
3711 return (struct mips_frame_cache
*) (*this_cache
);
3715 mips_insn32_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3716 struct frame_id
*this_id
)
3718 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3720 /* This marks the outermost frame. */
3721 if (info
->base
== 0)
3723 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3726 static struct value
*
3727 mips_insn32_frame_prev_register (struct frame_info
*this_frame
,
3728 void **this_cache
, int regnum
)
3730 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3732 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3736 mips_insn32_frame_sniffer (const struct frame_unwind
*self
,
3737 struct frame_info
*this_frame
, void **this_cache
)
3739 CORE_ADDR pc
= get_frame_pc (this_frame
);
3740 if (mips_pc_is_mips (pc
))
3745 static const struct frame_unwind mips_insn32_frame_unwind
=
3747 "mips insn32 prologue",
3749 default_frame_unwind_stop_reason
,
3750 mips_insn32_frame_this_id
,
3751 mips_insn32_frame_prev_register
,
3753 mips_insn32_frame_sniffer
3757 mips_insn32_frame_base_address (struct frame_info
*this_frame
,
3760 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3765 static const struct frame_base mips_insn32_frame_base
=
3767 &mips_insn32_frame_unwind
,
3768 mips_insn32_frame_base_address
,
3769 mips_insn32_frame_base_address
,
3770 mips_insn32_frame_base_address
3773 static const struct frame_base
*
3774 mips_insn32_frame_base_sniffer (struct frame_info
*this_frame
)
3776 CORE_ADDR pc
= get_frame_pc (this_frame
);
3777 if (mips_pc_is_mips (pc
))
3778 return &mips_insn32_frame_base
;
3783 static struct trad_frame_cache
*
3784 mips_stub_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3787 CORE_ADDR start_addr
;
3788 CORE_ADDR stack_addr
;
3789 struct trad_frame_cache
*this_trad_cache
;
3790 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3791 int num_regs
= gdbarch_num_regs (gdbarch
);
3793 if ((*this_cache
) != NULL
)
3794 return (struct trad_frame_cache
*) (*this_cache
);
3795 this_trad_cache
= trad_frame_cache_zalloc (this_frame
);
3796 (*this_cache
) = this_trad_cache
;
3798 /* The return address is in the link register. */
3799 trad_frame_set_reg_realreg (this_trad_cache
,
3800 gdbarch_pc_regnum (gdbarch
),
3801 num_regs
+ MIPS_RA_REGNUM
);
3803 /* Frame ID, since it's a frameless / stackless function, no stack
3804 space is allocated and SP on entry is the current SP. */
3805 pc
= get_frame_pc (this_frame
);
3806 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3807 stack_addr
= get_frame_register_signed (this_frame
,
3808 num_regs
+ MIPS_SP_REGNUM
);
3809 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
3811 /* Assume that the frame's base is the same as the
3813 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
3815 return this_trad_cache
;
3819 mips_stub_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3820 struct frame_id
*this_id
)
3822 struct trad_frame_cache
*this_trad_cache
3823 = mips_stub_frame_cache (this_frame
, this_cache
);
3824 trad_frame_get_id (this_trad_cache
, this_id
);
3827 static struct value
*
3828 mips_stub_frame_prev_register (struct frame_info
*this_frame
,
3829 void **this_cache
, int regnum
)
3831 struct trad_frame_cache
*this_trad_cache
3832 = mips_stub_frame_cache (this_frame
, this_cache
);
3833 return trad_frame_get_register (this_trad_cache
, this_frame
, regnum
);
3837 mips_stub_frame_sniffer (const struct frame_unwind
*self
,
3838 struct frame_info
*this_frame
, void **this_cache
)
3841 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3842 struct bound_minimal_symbol msym
;
3844 /* Use the stub unwinder for unreadable code. */
3845 if (target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
3848 if (in_plt_section (pc
) || in_mips_stubs_section (pc
))
3851 /* Calling a PIC function from a non-PIC function passes through a
3852 stub. The stub for foo is named ".pic.foo". */
3853 msym
= lookup_minimal_symbol_by_pc (pc
);
3854 if (msym
.minsym
!= NULL
3855 && msym
.minsym
->linkage_name () != NULL
3856 && startswith (msym
.minsym
->linkage_name (), ".pic."))
3862 static const struct frame_unwind mips_stub_frame_unwind
=
3866 default_frame_unwind_stop_reason
,
3867 mips_stub_frame_this_id
,
3868 mips_stub_frame_prev_register
,
3870 mips_stub_frame_sniffer
3874 mips_stub_frame_base_address (struct frame_info
*this_frame
,
3877 struct trad_frame_cache
*this_trad_cache
3878 = mips_stub_frame_cache (this_frame
, this_cache
);
3879 return trad_frame_get_this_base (this_trad_cache
);
3882 static const struct frame_base mips_stub_frame_base
=
3884 &mips_stub_frame_unwind
,
3885 mips_stub_frame_base_address
,
3886 mips_stub_frame_base_address
,
3887 mips_stub_frame_base_address
3890 static const struct frame_base
*
3891 mips_stub_frame_base_sniffer (struct frame_info
*this_frame
)
3893 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind
, this_frame
, NULL
))
3894 return &mips_stub_frame_base
;
3899 /* mips_addr_bits_remove - remove useless address bits */
3902 mips_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
3904 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
3906 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
3907 /* This hack is a work-around for existing boards using PMON, the
3908 simulator, and any other 64-bit targets that doesn't have true
3909 64-bit addressing. On these targets, the upper 32 bits of
3910 addresses are ignored by the hardware. Thus, the PC or SP are
3911 likely to have been sign extended to all 1s by instruction
3912 sequences that load 32-bit addresses. For example, a typical
3913 piece of code that loads an address is this:
3915 lui $r2, <upper 16 bits>
3916 ori $r2, <lower 16 bits>
3918 But the lui sign-extends the value such that the upper 32 bits
3919 may be all 1s. The workaround is simply to mask off these
3920 bits. In the future, gcc may be changed to support true 64-bit
3921 addressing, and this masking will have to be disabled. */
3922 return addr
&= 0xffffffffUL
;
3928 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
3929 instruction and ending with a SC/SCD instruction. If such a sequence
3930 is found, attempt to step through it. A breakpoint is placed at the end of
3933 /* Instructions used during single-stepping of atomic sequences, standard
3935 #define LL_OPCODE 0x30
3936 #define LLD_OPCODE 0x34
3937 #define SC_OPCODE 0x38
3938 #define SCD_OPCODE 0x3c
3940 static std::vector
<CORE_ADDR
>
3941 mips_deal_with_atomic_sequence (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3943 CORE_ADDR breaks
[2] = {CORE_ADDR_MAX
, CORE_ADDR_MAX
};
3945 CORE_ADDR branch_bp
; /* Breakpoint at branch instruction's destination. */
3949 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
3950 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
3952 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, loc
, NULL
);
3953 /* Assume all atomic sequences start with a ll/lld instruction. */
3954 if (itype_op (insn
) != LL_OPCODE
&& itype_op (insn
) != LLD_OPCODE
)
3957 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
3959 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
3962 loc
+= MIPS_INSN32_SIZE
;
3963 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, loc
, NULL
);
3965 /* Assume that there is at most one branch in the atomic
3966 sequence. If a branch is found, put a breakpoint in its
3967 destination address. */
3968 switch (itype_op (insn
))
3970 case 0: /* SPECIAL */
3971 if (rtype_funct (insn
) >> 1 == 4) /* JR, JALR */
3972 return {}; /* fallback to the standard single-step code. */
3974 case 1: /* REGIMM */
3975 is_branch
= ((itype_rt (insn
) & 0xc) == 0 /* B{LT,GE}Z* */
3976 || ((itype_rt (insn
) & 0x1e) == 0
3977 && itype_rs (insn
) == 0)); /* BPOSGE* */
3981 return {}; /* fallback to the standard single-step code. */
3988 case 22: /* BLEZL */
3989 case 23: /* BGTTL */
3993 is_branch
= ((itype_rs (insn
) == 9 || itype_rs (insn
) == 10)
3994 && (itype_rt (insn
) & 0x2) == 0);
3995 if (is_branch
) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */
4000 is_branch
= (itype_rs (insn
) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
4005 branch_bp
= loc
+ mips32_relative_offset (insn
) + 4;
4006 if (last_breakpoint
>= 1)
4007 return {}; /* More than one branch found, fallback to the
4008 standard single-step code. */
4009 breaks
[1] = branch_bp
;
4013 if (itype_op (insn
) == SC_OPCODE
|| itype_op (insn
) == SCD_OPCODE
)
4017 /* Assume that the atomic sequence ends with a sc/scd instruction. */
4018 if (itype_op (insn
) != SC_OPCODE
&& itype_op (insn
) != SCD_OPCODE
)
4021 loc
+= MIPS_INSN32_SIZE
;
4023 /* Insert a breakpoint right after the end of the atomic sequence. */
4026 /* Check for duplicated breakpoints. Check also for a breakpoint
4027 placed (branch instruction's destination) in the atomic sequence. */
4028 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
4029 last_breakpoint
= 0;
4031 std::vector
<CORE_ADDR
> next_pcs
;
4033 /* Effectively inserts the breakpoints. */
4034 for (index
= 0; index
<= last_breakpoint
; index
++)
4035 next_pcs
.push_back (breaks
[index
]);
4040 static std::vector
<CORE_ADDR
>
4041 micromips_deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
4044 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
4045 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
4046 CORE_ADDR breaks
[2] = {CORE_ADDR_MAX
, CORE_ADDR_MAX
};
4047 CORE_ADDR branch_bp
= 0; /* Breakpoint at branch instruction's
4055 /* Assume all atomic sequences start with a ll/lld instruction. */
4056 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
4057 if (micromips_op (insn
) != 0x18) /* POOL32C: bits 011000 */
4059 loc
+= MIPS_INSN16_SIZE
;
4061 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
4062 if ((b12s4_op (insn
) & 0xb) != 0x3) /* LL, LLD: bits 011000 0x11 */
4064 loc
+= MIPS_INSN16_SIZE
;
4066 /* Assume all atomic sequences end with an sc/scd instruction. Assume
4067 that no atomic sequence is longer than "atomic_sequence_length"
4069 for (insn_count
= 0;
4070 !sc_found
&& insn_count
< atomic_sequence_length
;
4075 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
4076 loc
+= MIPS_INSN16_SIZE
;
4078 /* Assume that there is at most one conditional branch in the
4079 atomic sequence. If a branch is found, put a breakpoint in
4080 its destination address. */
4081 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
4083 /* 32-bit instructions. */
4084 case 2 * MIPS_INSN16_SIZE
:
4085 switch (micromips_op (insn
))
4087 case 0x10: /* POOL32I: bits 010000 */
4088 if ((b5s5_op (insn
) & 0x18) != 0x0
4089 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
4090 /* BLEZ, BNEZC, BGTZ, BEQZC: 010000 001xx */
4091 && (b5s5_op (insn
) & 0x1d) != 0x11
4092 /* BLTZALS, BGEZALS: bits 010000 100x1 */
4093 && ((b5s5_op (insn
) & 0x1e) != 0x14
4094 || (insn
& 0x3) != 0x0)
4095 /* BC2F, BC2T: bits 010000 1010x xxx00 */
4096 && (b5s5_op (insn
) & 0x1e) != 0x1a
4097 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
4098 && ((b5s5_op (insn
) & 0x1e) != 0x1c
4099 || (insn
& 0x3) != 0x0)
4100 /* BC1F, BC1T: bits 010000 1110x xxx00 */
4101 && ((b5s5_op (insn
) & 0x1c) != 0x1c
4102 || (insn
& 0x3) != 0x1))
4103 /* BC1ANY*: bits 010000 111xx xxx01 */
4107 case 0x25: /* BEQ: bits 100101 */
4108 case 0x2d: /* BNE: bits 101101 */
4110 insn
|= mips_fetch_instruction (gdbarch
,
4111 ISA_MICROMIPS
, loc
, NULL
);
4112 branch_bp
= (loc
+ MIPS_INSN16_SIZE
4113 + micromips_relative_offset16 (insn
));
4117 case 0x00: /* POOL32A: bits 000000 */
4119 insn
|= mips_fetch_instruction (gdbarch
,
4120 ISA_MICROMIPS
, loc
, NULL
);
4121 if (b0s6_op (insn
) != 0x3c
4122 /* POOL32Axf: bits 000000 ... 111100 */
4123 || (b6s10_ext (insn
) & 0x2bf) != 0x3c)
4124 /* JALR, JALR.HB: 000000 000x111100 111100 */
4125 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
4129 case 0x1d: /* JALS: bits 011101 */
4130 case 0x35: /* J: bits 110101 */
4131 case 0x3d: /* JAL: bits 111101 */
4132 case 0x3c: /* JALX: bits 111100 */
4133 return {}; /* Fall back to the standard single-step code. */
4135 case 0x18: /* POOL32C: bits 011000 */
4136 if ((b12s4_op (insn
) & 0xb) == 0xb)
4137 /* SC, SCD: bits 011000 1x11 */
4141 loc
+= MIPS_INSN16_SIZE
;
4144 /* 16-bit instructions. */
4145 case MIPS_INSN16_SIZE
:
4146 switch (micromips_op (insn
))
4148 case 0x23: /* BEQZ16: bits 100011 */
4149 case 0x2b: /* BNEZ16: bits 101011 */
4150 branch_bp
= loc
+ micromips_relative_offset7 (insn
);
4154 case 0x11: /* POOL16C: bits 010001 */
4155 if ((b5s5_op (insn
) & 0x1c) != 0xc
4156 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
4157 && b5s5_op (insn
) != 0x18)
4158 /* JRADDIUSP: bits 010001 11000 */
4160 return {}; /* Fall back to the standard single-step code. */
4162 case 0x33: /* B16: bits 110011 */
4163 return {}; /* Fall back to the standard single-step code. */
4169 if (last_breakpoint
>= 1)
4170 return {}; /* More than one branch found, fallback to the
4171 standard single-step code. */
4172 breaks
[1] = branch_bp
;
4179 /* Insert a breakpoint right after the end of the atomic sequence. */
4182 /* Check for duplicated breakpoints. Check also for a breakpoint
4183 placed (branch instruction's destination) in the atomic sequence */
4184 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
4185 last_breakpoint
= 0;
4187 std::vector
<CORE_ADDR
> next_pcs
;
4189 /* Effectively inserts the breakpoints. */
4190 for (index
= 0; index
<= last_breakpoint
; index
++)
4191 next_pcs
.push_back (breaks
[index
]);
4196 static std::vector
<CORE_ADDR
>
4197 deal_with_atomic_sequence (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4199 if (mips_pc_is_mips (pc
))
4200 return mips_deal_with_atomic_sequence (gdbarch
, pc
);
4201 else if (mips_pc_is_micromips (gdbarch
, pc
))
4202 return micromips_deal_with_atomic_sequence (gdbarch
, pc
);
4207 /* mips_software_single_step() is called just before we want to resume
4208 the inferior, if we want to single-step it but there is no hardware
4209 or kernel single-step support (MIPS on GNU/Linux for example). We find
4210 the target of the coming instruction and breakpoint it. */
4212 std::vector
<CORE_ADDR
>
4213 mips_software_single_step (struct regcache
*regcache
)
4215 struct gdbarch
*gdbarch
= regcache
->arch ();
4216 CORE_ADDR pc
, next_pc
;
4218 pc
= regcache_read_pc (regcache
);
4219 std::vector
<CORE_ADDR
> next_pcs
= deal_with_atomic_sequence (gdbarch
, pc
);
4221 if (!next_pcs
.empty ())
4224 next_pc
= mips_next_pc (regcache
, pc
);
4229 /* Test whether the PC points to the return instruction at the
4230 end of a function. */
4233 mips_about_to_return (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4238 /* This used to check for MIPS16, but this piece of code is never
4239 called for MIPS16 functions. And likewise microMIPS ones. */
4240 gdb_assert (mips_pc_is_mips (pc
));
4242 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
4244 return (insn
& ~hint
) == 0x3e00008; /* jr(.hb) $ra */
4248 /* This fencepost looks highly suspicious to me. Removing it also
4249 seems suspicious as it could affect remote debugging across serial
4253 heuristic_proc_start (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4259 struct inferior
*inf
;
4261 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
4263 fence
= start_pc
- heuristic_fence_post
;
4267 if (heuristic_fence_post
== -1 || fence
< VM_MIN_ADDRESS
)
4268 fence
= VM_MIN_ADDRESS
;
4270 instlen
= mips_pc_is_mips (pc
) ? MIPS_INSN32_SIZE
: MIPS_INSN16_SIZE
;
4272 inf
= current_inferior ();
4274 /* Search back for previous return. */
4275 for (start_pc
-= instlen
;; start_pc
-= instlen
)
4276 if (start_pc
< fence
)
4278 /* It's not clear to me why we reach this point when
4279 stop_soon, but with this test, at least we
4280 don't print out warnings for every child forked (eg, on
4281 decstation). 22apr93 rich@cygnus.com. */
4282 if (inf
->control
.stop_soon
== NO_STOP_QUIETLY
)
4284 static int blurb_printed
= 0;
4286 warning (_("GDB can't find the start of the function at %s."),
4287 paddress (gdbarch
, pc
));
4291 /* This actually happens frequently in embedded
4292 development, when you first connect to a board
4293 and your stack pointer and pc are nowhere in
4294 particular. This message needs to give people
4295 in that situation enough information to
4296 determine that it's no big deal. */
4297 printf_filtered ("\n\
4298 GDB is unable to find the start of the function at %s\n\
4299 and thus can't determine the size of that function's stack frame.\n\
4300 This means that GDB may be unable to access that stack frame, or\n\
4301 the frames below it.\n\
4302 This problem is most likely caused by an invalid program counter or\n\
4304 However, if you think GDB should simply search farther back\n\
4305 from %s for code which looks like the beginning of a\n\
4306 function, you can increase the range of the search using the `set\n\
4307 heuristic-fence-post' command.\n",
4308 paddress (gdbarch
, pc
), paddress (gdbarch
, pc
));
4315 else if (mips_pc_is_mips16 (gdbarch
, start_pc
))
4317 unsigned short inst
;
4319 /* On MIPS16, any one of the following is likely to be the
4320 start of a function:
4326 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */
4327 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, start_pc
, NULL
);
4328 if ((inst
& 0xff80) == 0x6480) /* save */
4330 if (start_pc
- instlen
>= fence
)
4332 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
,
4333 start_pc
- instlen
, NULL
);
4334 if ((inst
& 0xf800) == 0xf000) /* extend */
4335 start_pc
-= instlen
;
4339 else if (((inst
& 0xf81f) == 0xe809
4340 && (inst
& 0x700) != 0x700) /* entry */
4341 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
4342 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
4343 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
4345 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
4346 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
4351 else if (mips_pc_is_micromips (gdbarch
, start_pc
))
4359 /* On microMIPS, any one of the following is likely to be the
4360 start of a function:
4364 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
4365 switch (micromips_op (insn
))
4367 case 0xc: /* ADDIU: bits 001100 */
4368 case 0x17: /* DADDIU: bits 010111 */
4369 sreg
= b0s5_reg (insn
);
4370 dreg
= b5s5_reg (insn
);
4372 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
,
4373 pc
+ MIPS_INSN16_SIZE
, NULL
);
4374 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
4375 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
4376 /* (D)ADDIU $sp, imm */
4381 case 0x10: /* POOL32I: bits 010000 */
4382 if (b5s5_op (insn
) == 0xd
4383 /* LUI: bits 010000 001101 */
4384 && b0s5_reg (insn
>> 16) == 28)
4389 case 0x13: /* POOL16D: bits 010011 */
4390 if ((insn
& 0x1) == 0x1)
4391 /* ADDIUSP: bits 010011 1 */
4393 offset
= micromips_decode_imm9 (b1s9_imm (insn
));
4399 /* ADDIUS5: bits 010011 0 */
4401 dreg
= b5s5_reg (insn
);
4402 offset
= (b1s4_imm (insn
) ^ 8) - 8;
4403 if (dreg
== MIPS_SP_REGNUM
&& offset
< 0)
4404 /* ADDIUS5 $sp, -imm */
4412 else if (mips_about_to_return (gdbarch
, start_pc
))
4414 /* Skip return and its delay slot. */
4415 start_pc
+= 2 * MIPS_INSN32_SIZE
;
4422 struct mips_objfile_private
4428 /* According to the current ABI, should the type be passed in a
4429 floating-point register (assuming that there is space)? When there
4430 is no FPU, FP are not even considered as possible candidates for
4431 FP registers and, consequently this returns false - forces FP
4432 arguments into integer registers. */
4435 fp_register_arg_p (struct gdbarch
*gdbarch
, enum type_code typecode
,
4436 struct type
*arg_type
)
4438 return ((typecode
== TYPE_CODE_FLT
4439 || (mips_eabi (gdbarch
)
4440 && (typecode
== TYPE_CODE_STRUCT
4441 || typecode
== TYPE_CODE_UNION
)
4442 && arg_type
->num_fields () == 1
4443 && check_typedef (arg_type
->field (0).type ())->code ()
4445 && mips_get_fpu_type (gdbarch
) != MIPS_FPU_NONE
);
4448 /* On o32, argument passing in GPRs depends on the alignment of the type being
4449 passed. Return 1 if this type must be aligned to a doubleword boundary. */
4452 mips_type_needs_double_align (struct type
*type
)
4454 enum type_code typecode
= type
->code ();
4456 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
4458 else if (typecode
== TYPE_CODE_STRUCT
)
4460 if (type
->num_fields () < 1)
4462 return mips_type_needs_double_align (type
->field (0).type ());
4464 else if (typecode
== TYPE_CODE_UNION
)
4468 n
= type
->num_fields ();
4469 for (i
= 0; i
< n
; i
++)
4470 if (mips_type_needs_double_align (type
->field (i
).type ()))
4477 /* Adjust the address downward (direction of stack growth) so that it
4478 is correctly aligned for a new stack frame. */
4480 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
4482 return align_down (addr
, 16);
4485 /* Implement the "push_dummy_code" gdbarch method. */
4488 mips_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
4489 CORE_ADDR funaddr
, struct value
**args
,
4490 int nargs
, struct type
*value_type
,
4491 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
4492 struct regcache
*regcache
)
4494 static gdb_byte nop_insn
[] = { 0, 0, 0, 0 };
4498 /* Reserve enough room on the stack for our breakpoint instruction. */
4499 bp_slot
= sp
- sizeof (nop_insn
);
4501 /* Return to microMIPS mode if calling microMIPS code to avoid
4502 triggering an address error exception on processors that only
4503 support microMIPS execution. */
4504 *bp_addr
= (mips_pc_is_micromips (gdbarch
, funaddr
)
4505 ? make_compact_addr (bp_slot
) : bp_slot
);
4507 /* The breakpoint layer automatically adjusts the address of
4508 breakpoints inserted in a branch delay slot. With enough
4509 bad luck, the 4 bytes located just before our breakpoint
4510 instruction could look like a branch instruction, and thus
4511 trigger the adjustement, and break the function call entirely.
4512 So, we reserve those 4 bytes and write a nop instruction
4513 to prevent that from happening. */
4514 nop_addr
= bp_slot
- sizeof (nop_insn
);
4515 write_memory (nop_addr
, nop_insn
, sizeof (nop_insn
));
4516 sp
= mips_frame_align (gdbarch
, nop_addr
);
4518 /* Inferior resumes at the function entry point. */
4525 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4526 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4527 int nargs
, struct value
**args
, CORE_ADDR sp
,
4528 function_call_return_method return_method
,
4529 CORE_ADDR struct_addr
)
4535 int stack_offset
= 0;
4536 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4537 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4538 int abi_regsize
= mips_abi_regsize (gdbarch
);
4540 /* For shared libraries, "t9" needs to point at the function
4542 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4544 /* Set the return address register to point to the entry point of
4545 the program, where a breakpoint lies in wait. */
4546 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4548 /* First ensure that the stack and structure return address (if any)
4549 are properly aligned. The stack has to be at least 64-bit
4550 aligned even on 32-bit machines, because doubles must be 64-bit
4551 aligned. For n32 and n64, stack frames need to be 128-bit
4552 aligned, so we round to this widest known alignment. */
4554 sp
= align_down (sp
, 16);
4555 struct_addr
= align_down (struct_addr
, 16);
4557 /* Now make space on the stack for the args. We allocate more
4558 than necessary for EABI, because the first few arguments are
4559 passed in registers, but that's OK. */
4560 for (argnum
= 0; argnum
< nargs
; argnum
++)
4561 arg_space
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), abi_regsize
);
4562 sp
-= align_up (arg_space
, 16);
4565 fprintf_unfiltered (gdb_stdlog
,
4566 "mips_eabi_push_dummy_call: sp=%s allocated %ld\n",
4567 paddress (gdbarch
, sp
),
4568 (long) align_up (arg_space
, 16));
4570 /* Initialize the integer and float register pointers. */
4571 argreg
= MIPS_A0_REGNUM
;
4572 float_argreg
= mips_fpa0_regnum (gdbarch
);
4574 /* The struct_return pointer occupies the first parameter-passing reg. */
4575 if (return_method
== return_method_struct
)
4578 fprintf_unfiltered (gdb_stdlog
,
4579 "mips_eabi_push_dummy_call: "
4580 "struct_return reg=%d %s\n",
4581 argreg
, paddress (gdbarch
, struct_addr
));
4582 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4585 /* Now load as many as possible of the first arguments into
4586 registers, and push the rest onto the stack. Loop thru args
4587 from first to last. */
4588 for (argnum
= 0; argnum
< nargs
; argnum
++)
4590 const gdb_byte
*val
;
4591 /* This holds the address of structures that are passed by
4593 gdb_byte ref_valbuf
[MAX_MIPS_ABI_REGSIZE
];
4594 struct value
*arg
= args
[argnum
];
4595 struct type
*arg_type
= check_typedef (value_type (arg
));
4596 int len
= TYPE_LENGTH (arg_type
);
4597 enum type_code typecode
= arg_type
->code ();
4600 fprintf_unfiltered (gdb_stdlog
,
4601 "mips_eabi_push_dummy_call: %d len=%d type=%d",
4602 argnum
+ 1, len
, (int) typecode
);
4604 /* The EABI passes structures that do not fit in a register by
4606 if (len
> abi_regsize
4607 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
4609 gdb_assert (abi_regsize
<= ARRAY_SIZE (ref_valbuf
));
4610 store_unsigned_integer (ref_valbuf
, abi_regsize
, byte_order
,
4611 value_address (arg
));
4612 typecode
= TYPE_CODE_PTR
;
4616 fprintf_unfiltered (gdb_stdlog
, " push");
4619 val
= value_contents (arg
).data ();
4621 /* 32-bit ABIs always start floating point arguments in an
4622 even-numbered floating point register. Round the FP register
4623 up before the check to see if there are any FP registers
4624 left. Non MIPS_EABI targets also pass the FP in the integer
4625 registers so also round up normal registers. */
4626 if (abi_regsize
< 8 && fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4628 if ((float_argreg
& 1))
4632 /* Floating point arguments passed in registers have to be
4633 treated specially. On 32-bit architectures, doubles
4634 are passed in register pairs; the even register gets
4635 the low word, and the odd register gets the high word.
4636 On non-EABI processors, the first two floating point arguments are
4637 also copied to general registers, because MIPS16 functions
4638 don't use float registers for arguments. This duplication of
4639 arguments in general registers can't hurt non-MIPS16 functions
4640 because those registers are normally skipped. */
4641 /* MIPS_EABI squeezes a struct that contains a single floating
4642 point value into an FP register instead of pushing it onto the
4644 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4645 && float_argreg
<= mips_last_fp_arg_regnum (gdbarch
))
4647 /* EABI32 will pass doubles in consecutive registers, even on
4648 64-bit cores. At one time, we used to check the size of
4649 `float_argreg' to determine whether or not to pass doubles
4650 in consecutive registers, but this is not sufficient for
4651 making the ABI determination. */
4652 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
4654 int low_offset
= gdbarch_byte_order (gdbarch
)
4655 == BFD_ENDIAN_BIG
? 4 : 0;
4658 /* Write the low word of the double to the even register(s). */
4659 regval
= extract_signed_integer (val
+ low_offset
,
4662 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4663 float_argreg
, phex (regval
, 4));
4664 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4666 /* Write the high word of the double to the odd register(s). */
4667 regval
= extract_signed_integer (val
+ 4 - low_offset
,
4670 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4671 float_argreg
, phex (regval
, 4));
4672 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4676 /* This is a floating point value that fits entirely
4677 in a single register. */
4678 /* On 32 bit ABI's the float_argreg is further adjusted
4679 above to ensure that it is even register aligned. */
4680 LONGEST regval
= extract_signed_integer (val
, len
, byte_order
);
4682 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4683 float_argreg
, phex (regval
, len
));
4684 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4689 /* Copy the argument to general registers or the stack in
4690 register-sized pieces. Large arguments are split between
4691 registers and stack. */
4692 /* Note: structs whose size is not a multiple of abi_regsize
4693 are treated specially: Irix cc passes
4694 them in registers where gcc sometimes puts them on the
4695 stack. For maximum compatibility, we will put them in
4697 int odd_sized_struct
= (len
> abi_regsize
&& len
% abi_regsize
!= 0);
4699 /* Note: Floating-point values that didn't fit into an FP
4700 register are only written to memory. */
4703 /* Remember if the argument was written to the stack. */
4704 int stack_used_p
= 0;
4705 int partial_len
= (len
< abi_regsize
? len
: abi_regsize
);
4708 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4711 /* Write this portion of the argument to the stack. */
4712 if (argreg
> mips_last_arg_regnum (gdbarch
)
4714 || fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4716 /* Should shorter than int integer values be
4717 promoted to int before being stored? */
4718 int longword_offset
= 0;
4721 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4723 if (abi_regsize
== 8
4724 && (typecode
== TYPE_CODE_INT
4725 || typecode
== TYPE_CODE_PTR
4726 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
4727 longword_offset
= abi_regsize
- len
;
4728 else if ((typecode
== TYPE_CODE_STRUCT
4729 || typecode
== TYPE_CODE_UNION
)
4730 && TYPE_LENGTH (arg_type
) < abi_regsize
)
4731 longword_offset
= abi_regsize
- len
;
4736 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
4737 paddress (gdbarch
, stack_offset
));
4738 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
4739 paddress (gdbarch
, longword_offset
));
4742 addr
= sp
+ stack_offset
+ longword_offset
;
4747 fprintf_unfiltered (gdb_stdlog
, " @%s ",
4748 paddress (gdbarch
, addr
));
4749 for (i
= 0; i
< partial_len
; i
++)
4751 fprintf_unfiltered (gdb_stdlog
, "%02x",
4755 write_memory (addr
, val
, partial_len
);
4758 /* Note!!! This is NOT an else clause. Odd sized
4759 structs may go thru BOTH paths. Floating point
4760 arguments will not. */
4761 /* Write this portion of the argument to a general
4762 purpose register. */
4763 if (argreg
<= mips_last_arg_regnum (gdbarch
)
4764 && !fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4767 extract_signed_integer (val
, partial_len
, byte_order
);
4770 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4772 phex (regval
, abi_regsize
));
4773 regcache_cooked_write_signed (regcache
, argreg
, regval
);
4780 /* Compute the offset into the stack at which we will
4781 copy the next parameter.
4783 In the new EABI (and the NABI32), the stack_offset
4784 only needs to be adjusted when it has been used. */
4787 stack_offset
+= align_up (partial_len
, abi_regsize
);
4791 fprintf_unfiltered (gdb_stdlog
, "\n");
4794 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4796 /* Return adjusted stack pointer. */
4800 /* Determine the return value convention being used. */
4802 static enum return_value_convention
4803 mips_eabi_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
4804 struct type
*type
, struct regcache
*regcache
,
4805 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4807 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
4808 int fp_return_type
= 0;
4809 int offset
, regnum
, xfer
;
4811 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
4812 return RETURN_VALUE_STRUCT_CONVENTION
;
4814 /* Floating point type? */
4815 if (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4817 if (type
->code () == TYPE_CODE_FLT
)
4819 /* Structs with a single field of float type
4820 are returned in a floating point register. */
4821 if ((type
->code () == TYPE_CODE_STRUCT
4822 || type
->code () == TYPE_CODE_UNION
)
4823 && type
->num_fields () == 1)
4825 struct type
*fieldtype
= type
->field (0).type ();
4827 if (check_typedef (fieldtype
)->code () == TYPE_CODE_FLT
)
4834 /* A floating-point value belongs in the least significant part
4837 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4838 regnum
= mips_regnum (gdbarch
)->fp0
;
4842 /* An integer value goes in V0/V1. */
4844 fprintf_unfiltered (gdb_stderr
, "Return scalar in $v0\n");
4845 regnum
= MIPS_V0_REGNUM
;
4848 offset
< TYPE_LENGTH (type
);
4849 offset
+= mips_abi_regsize (gdbarch
), regnum
++)
4851 xfer
= mips_abi_regsize (gdbarch
);
4852 if (offset
+ xfer
> TYPE_LENGTH (type
))
4853 xfer
= TYPE_LENGTH (type
) - offset
;
4854 mips_xfer_register (gdbarch
, regcache
,
4855 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
4856 gdbarch_byte_order (gdbarch
), readbuf
, writebuf
,
4860 return RETURN_VALUE_REGISTER_CONVENTION
;
4864 /* N32/N64 ABI stuff. */
4866 /* Search for a naturally aligned double at OFFSET inside a struct
4867 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
4871 mips_n32n64_fp_arg_chunk_p (struct gdbarch
*gdbarch
, struct type
*arg_type
,
4876 if (arg_type
->code () != TYPE_CODE_STRUCT
)
4879 if (mips_get_fpu_type (gdbarch
) != MIPS_FPU_DOUBLE
)
4882 if (TYPE_LENGTH (arg_type
) < offset
+ MIPS64_REGSIZE
)
4885 for (i
= 0; i
< arg_type
->num_fields (); i
++)
4888 struct type
*field_type
;
4890 /* We're only looking at normal fields. */
4891 if (field_is_static (&arg_type
->field (i
))
4892 || (arg_type
->field (i
).loc_bitpos () % 8) != 0)
4895 /* If we have gone past the offset, there is no double to pass. */
4896 pos
= arg_type
->field (i
).loc_bitpos () / 8;
4900 field_type
= check_typedef (arg_type
->field (i
).type ());
4902 /* If this field is entirely before the requested offset, go
4903 on to the next one. */
4904 if (pos
+ TYPE_LENGTH (field_type
) <= offset
)
4907 /* If this is our special aligned double, we can stop. */
4908 if (field_type
->code () == TYPE_CODE_FLT
4909 && TYPE_LENGTH (field_type
) == MIPS64_REGSIZE
)
4912 /* This field starts at or before the requested offset, and
4913 overlaps it. If it is a structure, recurse inwards. */
4914 return mips_n32n64_fp_arg_chunk_p (gdbarch
, field_type
, offset
- pos
);
4921 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4922 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4923 int nargs
, struct value
**args
, CORE_ADDR sp
,
4924 function_call_return_method return_method
,
4925 CORE_ADDR struct_addr
)
4931 int stack_offset
= 0;
4932 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4933 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4935 /* For shared libraries, "t9" needs to point at the function
4937 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4939 /* Set the return address register to point to the entry point of
4940 the program, where a breakpoint lies in wait. */
4941 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4943 /* First ensure that the stack and structure return address (if any)
4944 are properly aligned. The stack has to be at least 64-bit
4945 aligned even on 32-bit machines, because doubles must be 64-bit
4946 aligned. For n32 and n64, stack frames need to be 128-bit
4947 aligned, so we round to this widest known alignment. */
4949 sp
= align_down (sp
, 16);
4950 struct_addr
= align_down (struct_addr
, 16);
4952 /* Now make space on the stack for the args. */
4953 for (argnum
= 0; argnum
< nargs
; argnum
++)
4954 arg_space
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), MIPS64_REGSIZE
);
4955 sp
-= align_up (arg_space
, 16);
4958 fprintf_unfiltered (gdb_stdlog
,
4959 "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n",
4960 paddress (gdbarch
, sp
),
4961 (long) align_up (arg_space
, 16));
4963 /* Initialize the integer and float register pointers. */
4964 argreg
= MIPS_A0_REGNUM
;
4965 float_argreg
= mips_fpa0_regnum (gdbarch
);
4967 /* The struct_return pointer occupies the first parameter-passing reg. */
4968 if (return_method
== return_method_struct
)
4971 fprintf_unfiltered (gdb_stdlog
,
4972 "mips_n32n64_push_dummy_call: "
4973 "struct_return reg=%d %s\n",
4974 argreg
, paddress (gdbarch
, struct_addr
));
4975 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4978 /* Now load as many as possible of the first arguments into
4979 registers, and push the rest onto the stack. Loop thru args
4980 from first to last. */
4981 for (argnum
= 0; argnum
< nargs
; argnum
++)
4983 const gdb_byte
*val
;
4984 struct value
*arg
= args
[argnum
];
4985 struct type
*arg_type
= check_typedef (value_type (arg
));
4986 int len
= TYPE_LENGTH (arg_type
);
4987 enum type_code typecode
= arg_type
->code ();
4990 fprintf_unfiltered (gdb_stdlog
,
4991 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
4992 argnum
+ 1, len
, (int) typecode
);
4994 val
= value_contents (arg
).data ();
4996 /* A 128-bit long double value requires an even-odd pair of
4997 floating-point registers. */
4999 && fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5000 && (float_argreg
& 1))
5006 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5007 && argreg
<= mips_last_arg_regnum (gdbarch
))
5009 /* This is a floating point value that fits entirely
5010 in a single register or a pair of registers. */
5011 int reglen
= (len
<= MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
5012 LONGEST regval
= extract_unsigned_integer (val
, reglen
, byte_order
);
5014 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5015 float_argreg
, phex (regval
, reglen
));
5016 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
5019 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5020 argreg
, phex (regval
, reglen
));
5021 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5026 regval
= extract_unsigned_integer (val
+ reglen
,
5027 reglen
, byte_order
);
5029 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5030 float_argreg
, phex (regval
, reglen
));
5031 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
5034 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5035 argreg
, phex (regval
, reglen
));
5036 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5043 /* Copy the argument to general registers or the stack in
5044 register-sized pieces. Large arguments are split between
5045 registers and stack. */
5046 /* For N32/N64, structs, unions, or other composite types are
5047 treated as a sequence of doublewords, and are passed in integer
5048 or floating point registers as though they were simple scalar
5049 parameters to the extent that they fit, with any excess on the
5050 stack packed according to the normal memory layout of the
5052 The caller does not reserve space for the register arguments;
5053 the callee is responsible for reserving it if required. */
5054 /* Note: Floating-point values that didn't fit into an FP
5055 register are only written to memory. */
5058 /* Remember if the argument was written to the stack. */
5059 int stack_used_p
= 0;
5060 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
5063 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
5066 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
5067 gdb_assert (argreg
> mips_last_arg_regnum (gdbarch
));
5069 /* Write this portion of the argument to the stack. */
5070 if (argreg
> mips_last_arg_regnum (gdbarch
))
5072 /* Should shorter than int integer values be
5073 promoted to int before being stored? */
5074 int longword_offset
= 0;
5077 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5079 if ((typecode
== TYPE_CODE_INT
5080 || typecode
== TYPE_CODE_PTR
)
5082 longword_offset
= MIPS64_REGSIZE
- len
;
5087 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
5088 paddress (gdbarch
, stack_offset
));
5089 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
5090 paddress (gdbarch
, longword_offset
));
5093 addr
= sp
+ stack_offset
+ longword_offset
;
5098 fprintf_unfiltered (gdb_stdlog
, " @%s ",
5099 paddress (gdbarch
, addr
));
5100 for (i
= 0; i
< partial_len
; i
++)
5102 fprintf_unfiltered (gdb_stdlog
, "%02x",
5106 write_memory (addr
, val
, partial_len
);
5109 /* Note!!! This is NOT an else clause. Odd sized
5110 structs may go thru BOTH paths. */
5111 /* Write this portion of the argument to a general
5112 purpose register. */
5113 if (argreg
<= mips_last_arg_regnum (gdbarch
))
5117 /* Sign extend pointers, 32-bit integers and signed
5118 16-bit and 8-bit integers; everything else is taken
5121 if ((partial_len
== 4
5122 && (typecode
== TYPE_CODE_PTR
5123 || typecode
== TYPE_CODE_INT
))
5125 && typecode
== TYPE_CODE_INT
5126 && !arg_type
->is_unsigned ()))
5127 regval
= extract_signed_integer (val
, partial_len
,
5130 regval
= extract_unsigned_integer (val
, partial_len
,
5133 /* A non-floating-point argument being passed in a
5134 general register. If a struct or union, and if
5135 the remaining length is smaller than the register
5136 size, we have to adjust the register value on
5139 It does not seem to be necessary to do the
5140 same for integral types. */
5142 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
5143 && partial_len
< MIPS64_REGSIZE
5144 && (typecode
== TYPE_CODE_STRUCT
5145 || typecode
== TYPE_CODE_UNION
))
5146 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
5150 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
5152 phex (regval
, MIPS64_REGSIZE
));
5153 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5155 if (mips_n32n64_fp_arg_chunk_p (gdbarch
, arg_type
,
5156 TYPE_LENGTH (arg_type
) - len
))
5159 fprintf_filtered (gdb_stdlog
, " - fpreg=%d val=%s",
5161 phex (regval
, MIPS64_REGSIZE
));
5162 regcache_cooked_write_unsigned (regcache
, float_argreg
,
5173 /* Compute the offset into the stack at which we will
5174 copy the next parameter.
5176 In N32 (N64?), the stack_offset only needs to be
5177 adjusted when it has been used. */
5180 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
5184 fprintf_unfiltered (gdb_stdlog
, "\n");
5187 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
5189 /* Return adjusted stack pointer. */
5193 static enum return_value_convention
5194 mips_n32n64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
5195 struct type
*type
, struct regcache
*regcache
,
5196 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5198 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
5200 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
5202 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
5203 if needed), as appropriate for the type. Composite results (struct,
5204 union, or array) are returned in $2/$f0 and $3/$f2 according to the
5207 * A struct with only one or two floating point fields is returned in $f0
5208 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
5211 * Any other composite results of at most 128 bits are returned in
5212 $2 (first 64 bits) and $3 (remainder, if necessary).
5214 * Larger composite results are handled by converting the function to a
5215 procedure with an implicit first parameter, which is a pointer to an area
5216 reserved by the caller to receive the result. [The o32-bit ABI requires
5217 that all composite results be handled by conversion to implicit first
5218 parameters. The MIPS/SGI Fortran implementation has always made a
5219 specific exception to return COMPLEX results in the floating point
5222 if (TYPE_LENGTH (type
) > 2 * MIPS64_REGSIZE
)
5223 return RETURN_VALUE_STRUCT_CONVENTION
;
5224 else if (type
->code () == TYPE_CODE_FLT
5225 && TYPE_LENGTH (type
) == 16
5226 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5228 /* A 128-bit floating-point value fills both $f0 and $f2. The
5229 two registers are used in the same as memory order, so the
5230 eight bytes with the lower memory address are in $f0. */
5232 fprintf_unfiltered (gdb_stderr
, "Return float in $f0 and $f2\n");
5233 mips_xfer_register (gdbarch
, regcache
,
5234 (gdbarch_num_regs (gdbarch
)
5235 + mips_regnum (gdbarch
)->fp0
),
5236 8, gdbarch_byte_order (gdbarch
),
5237 readbuf
, writebuf
, 0);
5238 mips_xfer_register (gdbarch
, regcache
,
5239 (gdbarch_num_regs (gdbarch
)
5240 + mips_regnum (gdbarch
)->fp0
+ 2),
5241 8, gdbarch_byte_order (gdbarch
),
5242 readbuf
? readbuf
+ 8 : readbuf
,
5243 writebuf
? writebuf
+ 8 : writebuf
, 0);
5244 return RETURN_VALUE_REGISTER_CONVENTION
;
5246 else if (type
->code () == TYPE_CODE_FLT
5247 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5249 /* A single or double floating-point value that fits in FP0. */
5251 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
5252 mips_xfer_register (gdbarch
, regcache
,
5253 (gdbarch_num_regs (gdbarch
)
5254 + mips_regnum (gdbarch
)->fp0
),
5256 gdbarch_byte_order (gdbarch
),
5257 readbuf
, writebuf
, 0);
5258 return RETURN_VALUE_REGISTER_CONVENTION
;
5260 else if (type
->code () == TYPE_CODE_STRUCT
5261 && type
->num_fields () <= 2
5262 && type
->num_fields () >= 1
5263 && ((type
->num_fields () == 1
5264 && (check_typedef (type
->field (0).type ())->code ()
5266 || (type
->num_fields () == 2
5267 && (check_typedef (type
->field (0).type ())->code ()
5269 && (check_typedef (type
->field (1).type ())->code ()
5270 == TYPE_CODE_FLT
))))
5272 /* A struct that contains one or two floats. Each value is part
5273 in the least significant part of their floating point
5274 register (or GPR, for soft float). */
5277 for (field
= 0, regnum
= (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
5278 ? mips_regnum (gdbarch
)->fp0
5280 field
< type
->num_fields (); field
++, regnum
+= 2)
5282 int offset
= type
->field (field
).loc_bitpos () / TARGET_CHAR_BIT
;
5284 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
5286 if (TYPE_LENGTH (type
->field (field
).type ()) == 16)
5288 /* A 16-byte long double field goes in two consecutive
5290 mips_xfer_register (gdbarch
, regcache
,
5291 gdbarch_num_regs (gdbarch
) + regnum
,
5293 gdbarch_byte_order (gdbarch
),
5294 readbuf
, writebuf
, offset
);
5295 mips_xfer_register (gdbarch
, regcache
,
5296 gdbarch_num_regs (gdbarch
) + regnum
+ 1,
5298 gdbarch_byte_order (gdbarch
),
5299 readbuf
, writebuf
, offset
+ 8);
5302 mips_xfer_register (gdbarch
, regcache
,
5303 gdbarch_num_regs (gdbarch
) + regnum
,
5304 TYPE_LENGTH (type
->field (field
).type ()),
5305 gdbarch_byte_order (gdbarch
),
5306 readbuf
, writebuf
, offset
);
5308 return RETURN_VALUE_REGISTER_CONVENTION
;
5310 else if (type
->code () == TYPE_CODE_STRUCT
5311 || type
->code () == TYPE_CODE_UNION
5312 || type
->code () == TYPE_CODE_ARRAY
)
5314 /* A composite type. Extract the left justified value,
5315 regardless of the byte order. I.e. DO NOT USE
5319 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5320 offset
< TYPE_LENGTH (type
);
5321 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5323 int xfer
= register_size (gdbarch
, regnum
);
5324 if (offset
+ xfer
> TYPE_LENGTH (type
))
5325 xfer
= TYPE_LENGTH (type
) - offset
;
5327 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5328 offset
, xfer
, regnum
);
5329 mips_xfer_register (gdbarch
, regcache
,
5330 gdbarch_num_regs (gdbarch
) + regnum
,
5331 xfer
, BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
,
5334 return RETURN_VALUE_REGISTER_CONVENTION
;
5338 /* A scalar extract each part but least-significant-byte
5342 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5343 offset
< TYPE_LENGTH (type
);
5344 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5346 int xfer
= register_size (gdbarch
, regnum
);
5347 if (offset
+ xfer
> TYPE_LENGTH (type
))
5348 xfer
= TYPE_LENGTH (type
) - offset
;
5350 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5351 offset
, xfer
, regnum
);
5352 mips_xfer_register (gdbarch
, regcache
,
5353 gdbarch_num_regs (gdbarch
) + regnum
,
5354 xfer
, gdbarch_byte_order (gdbarch
),
5355 readbuf
, writebuf
, offset
);
5357 return RETURN_VALUE_REGISTER_CONVENTION
;
5361 /* Which registers to use for passing floating-point values between
5362 function calls, one of floating-point, general and both kinds of
5363 registers. O32 and O64 use different register kinds for standard
5364 MIPS and MIPS16 code; to make the handling of cases where we may
5365 not know what kind of code is being used (e.g. no debug information)
5366 easier we sometimes use both kinds. */
5375 /* O32 ABI stuff. */
5378 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
5379 struct regcache
*regcache
, CORE_ADDR bp_addr
,
5380 int nargs
, struct value
**args
, CORE_ADDR sp
,
5381 function_call_return_method return_method
,
5382 CORE_ADDR struct_addr
)
5388 int stack_offset
= 0;
5389 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5390 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
5392 /* For shared libraries, "t9" needs to point at the function
5394 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
5396 /* Set the return address register to point to the entry point of
5397 the program, where a breakpoint lies in wait. */
5398 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
5400 /* First ensure that the stack and structure return address (if any)
5401 are properly aligned. The stack has to be at least 64-bit
5402 aligned even on 32-bit machines, because doubles must be 64-bit
5403 aligned. For n32 and n64, stack frames need to be 128-bit
5404 aligned, so we round to this widest known alignment. */
5406 sp
= align_down (sp
, 16);
5407 struct_addr
= align_down (struct_addr
, 16);
5409 /* Now make space on the stack for the args. */
5410 for (argnum
= 0; argnum
< nargs
; argnum
++)
5412 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
5414 /* Align to double-word if necessary. */
5415 if (mips_type_needs_double_align (arg_type
))
5416 arg_space
= align_up (arg_space
, MIPS32_REGSIZE
* 2);
5417 /* Allocate space on the stack. */
5418 arg_space
+= align_up (TYPE_LENGTH (arg_type
), MIPS32_REGSIZE
);
5420 sp
-= align_up (arg_space
, 16);
5423 fprintf_unfiltered (gdb_stdlog
,
5424 "mips_o32_push_dummy_call: sp=%s allocated %ld\n",
5425 paddress (gdbarch
, sp
),
5426 (long) align_up (arg_space
, 16));
5428 /* Initialize the integer and float register pointers. */
5429 argreg
= MIPS_A0_REGNUM
;
5430 float_argreg
= mips_fpa0_regnum (gdbarch
);
5432 /* The struct_return pointer occupies the first parameter-passing reg. */
5433 if (return_method
== return_method_struct
)
5436 fprintf_unfiltered (gdb_stdlog
,
5437 "mips_o32_push_dummy_call: "
5438 "struct_return reg=%d %s\n",
5439 argreg
, paddress (gdbarch
, struct_addr
));
5440 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
5441 stack_offset
+= MIPS32_REGSIZE
;
5444 /* Now load as many as possible of the first arguments into
5445 registers, and push the rest onto the stack. Loop thru args
5446 from first to last. */
5447 for (argnum
= 0; argnum
< nargs
; argnum
++)
5449 const gdb_byte
*val
;
5450 struct value
*arg
= args
[argnum
];
5451 struct type
*arg_type
= check_typedef (value_type (arg
));
5452 int len
= TYPE_LENGTH (arg_type
);
5453 enum type_code typecode
= arg_type
->code ();
5456 fprintf_unfiltered (gdb_stdlog
,
5457 "mips_o32_push_dummy_call: %d len=%d type=%d",
5458 argnum
+ 1, len
, (int) typecode
);
5460 val
= value_contents (arg
).data ();
5462 /* 32-bit ABIs always start floating point arguments in an
5463 even-numbered floating point register. Round the FP register
5464 up before the check to see if there are any FP registers
5465 left. O32 targets also pass the FP in the integer registers
5466 so also round up normal registers. */
5467 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
5469 if ((float_argreg
& 1))
5473 /* Floating point arguments passed in registers have to be
5474 treated specially. On 32-bit architectures, doubles are
5475 passed in register pairs; the even FP register gets the
5476 low word, and the odd FP register gets the high word.
5477 On O32, the first two floating point arguments are also
5478 copied to general registers, following their memory order,
5479 because MIPS16 functions don't use float registers for
5480 arguments. This duplication of arguments in general
5481 registers can't hurt non-MIPS16 functions, because those
5482 registers are normally skipped. */
5484 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5485 && float_argreg
<= mips_last_fp_arg_regnum (gdbarch
))
5487 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
5489 int freg_offset
= gdbarch_byte_order (gdbarch
)
5490 == BFD_ENDIAN_BIG
? 1 : 0;
5491 unsigned long regval
;
5494 regval
= extract_unsigned_integer (val
, 4, byte_order
);
5496 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5497 float_argreg
+ freg_offset
,
5499 regcache_cooked_write_unsigned (regcache
,
5500 float_argreg
++ + freg_offset
,
5503 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5504 argreg
, phex (regval
, 4));
5505 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5508 regval
= extract_unsigned_integer (val
+ 4, 4, byte_order
);
5510 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5511 float_argreg
- freg_offset
,
5513 regcache_cooked_write_unsigned (regcache
,
5514 float_argreg
++ - freg_offset
,
5517 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5518 argreg
, phex (regval
, 4));
5519 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5523 /* This is a floating point value that fits entirely
5524 in a single register. */
5525 /* On 32 bit ABI's the float_argreg is further adjusted
5526 above to ensure that it is even register aligned. */
5527 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
5529 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5530 float_argreg
, phex (regval
, len
));
5531 regcache_cooked_write_unsigned (regcache
,
5532 float_argreg
++, regval
);
5533 /* Although two FP registers are reserved for each
5534 argument, only one corresponding integer register is
5537 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5538 argreg
, phex (regval
, len
));
5539 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5541 /* Reserve space for the FP register. */
5542 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
5546 /* Copy the argument to general registers or the stack in
5547 register-sized pieces. Large arguments are split between
5548 registers and stack. */
5549 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
5550 are treated specially: Irix cc passes
5551 them in registers where gcc sometimes puts them on the
5552 stack. For maximum compatibility, we will put them in
5554 int odd_sized_struct
= (len
> MIPS32_REGSIZE
5555 && len
% MIPS32_REGSIZE
!= 0);
5556 /* Structures should be aligned to eight bytes (even arg registers)
5557 on MIPS_ABI_O32, if their first member has double precision. */
5558 if (mips_type_needs_double_align (arg_type
))
5563 stack_offset
+= MIPS32_REGSIZE
;
5568 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
5571 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
5574 /* Write this portion of the argument to the stack. */
5575 if (argreg
> mips_last_arg_regnum (gdbarch
)
5576 || odd_sized_struct
)
5578 /* Should shorter than int integer values be
5579 promoted to int before being stored? */
5580 int longword_offset
= 0;
5585 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
5586 paddress (gdbarch
, stack_offset
));
5587 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
5588 paddress (gdbarch
, longword_offset
));
5591 addr
= sp
+ stack_offset
+ longword_offset
;
5596 fprintf_unfiltered (gdb_stdlog
, " @%s ",
5597 paddress (gdbarch
, addr
));
5598 for (i
= 0; i
< partial_len
; i
++)
5600 fprintf_unfiltered (gdb_stdlog
, "%02x",
5604 write_memory (addr
, val
, partial_len
);
5607 /* Note!!! This is NOT an else clause. Odd sized
5608 structs may go thru BOTH paths. */
5609 /* Write this portion of the argument to a general
5610 purpose register. */
5611 if (argreg
<= mips_last_arg_regnum (gdbarch
))
5613 LONGEST regval
= extract_signed_integer (val
, partial_len
,
5615 /* Value may need to be sign extended, because
5616 mips_isa_regsize() != mips_abi_regsize(). */
5618 /* A non-floating-point argument being passed in a
5619 general register. If a struct or union, and if
5620 the remaining length is smaller than the register
5621 size, we have to adjust the register value on
5624 It does not seem to be necessary to do the
5625 same for integral types.
5627 Also don't do this adjustment on O64 binaries.
5629 cagney/2001-07-23: gdb/179: Also, GCC, when
5630 outputting LE O32 with sizeof (struct) <
5631 mips_abi_regsize(), generates a left shift
5632 as part of storing the argument in a register
5633 (the left shift isn't generated when
5634 sizeof (struct) >= mips_abi_regsize()). Since
5635 it is quite possible that this is GCC
5636 contradicting the LE/O32 ABI, GDB has not been
5637 adjusted to accommodate this. Either someone
5638 needs to demonstrate that the LE/O32 ABI
5639 specifies such a left shift OR this new ABI gets
5640 identified as such and GDB gets tweaked
5643 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
5644 && partial_len
< MIPS32_REGSIZE
5645 && (typecode
== TYPE_CODE_STRUCT
5646 || typecode
== TYPE_CODE_UNION
))
5647 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
5651 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
5653 phex (regval
, MIPS32_REGSIZE
));
5654 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5657 /* Prevent subsequent floating point arguments from
5658 being passed in floating point registers. */
5659 float_argreg
= mips_last_fp_arg_regnum (gdbarch
) + 1;
5665 /* Compute the offset into the stack at which we will
5666 copy the next parameter.
5668 In older ABIs, the caller reserved space for
5669 registers that contained arguments. This was loosely
5670 refered to as their "home". Consequently, space is
5671 always allocated. */
5673 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
5677 fprintf_unfiltered (gdb_stdlog
, "\n");
5680 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
5682 /* Return adjusted stack pointer. */
5686 static enum return_value_convention
5687 mips_o32_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
5688 struct type
*type
, struct regcache
*regcache
,
5689 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5691 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
5692 int mips16
= mips_pc_is_mips16 (gdbarch
, func_addr
);
5693 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
5694 enum mips_fval_reg fval_reg
;
5696 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
5697 if (type
->code () == TYPE_CODE_STRUCT
5698 || type
->code () == TYPE_CODE_UNION
5699 || type
->code () == TYPE_CODE_ARRAY
)
5700 return RETURN_VALUE_STRUCT_CONVENTION
;
5701 else if (type
->code () == TYPE_CODE_FLT
5702 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5704 /* A single-precision floating-point value. If reading in or copying,
5705 then we get it from/put it to FP0 for standard MIPS code or GPR2
5706 for MIPS16 code. If writing out only, then we put it to both FP0
5707 and GPR2. We do not support reading in with no function known, if
5708 this safety check ever triggers, then we'll have to try harder. */
5709 gdb_assert (function
|| !readbuf
);
5714 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
5717 fprintf_unfiltered (gdb_stderr
, "Return float in $2\n");
5719 case mips_fval_both
:
5720 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0 and $2\n");
5723 if (fval_reg
!= mips_fval_gpr
)
5724 mips_xfer_register (gdbarch
, regcache
,
5725 (gdbarch_num_regs (gdbarch
)
5726 + mips_regnum (gdbarch
)->fp0
),
5728 gdbarch_byte_order (gdbarch
),
5729 readbuf
, writebuf
, 0);
5730 if (fval_reg
!= mips_fval_fpr
)
5731 mips_xfer_register (gdbarch
, regcache
,
5732 gdbarch_num_regs (gdbarch
) + 2,
5734 gdbarch_byte_order (gdbarch
),
5735 readbuf
, writebuf
, 0);
5736 return RETURN_VALUE_REGISTER_CONVENTION
;
5738 else if (type
->code () == TYPE_CODE_FLT
5739 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5741 /* A double-precision floating-point value. If reading in or copying,
5742 then we get it from/put it to FP1 and FP0 for standard MIPS code or
5743 GPR2 and GPR3 for MIPS16 code. If writing out only, then we put it
5744 to both FP1/FP0 and GPR2/GPR3. We do not support reading in with
5745 no function known, if this safety check ever triggers, then we'll
5746 have to try harder. */
5747 gdb_assert (function
|| !readbuf
);
5752 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
5755 fprintf_unfiltered (gdb_stderr
, "Return float in $2/$3\n");
5757 case mips_fval_both
:
5758 fprintf_unfiltered (gdb_stderr
,
5759 "Return float in $fp1/$fp0 and $2/$3\n");
5762 if (fval_reg
!= mips_fval_gpr
)
5764 /* The most significant part goes in FP1, and the least significant
5766 switch (gdbarch_byte_order (gdbarch
))
5768 case BFD_ENDIAN_LITTLE
:
5769 mips_xfer_register (gdbarch
, regcache
,
5770 (gdbarch_num_regs (gdbarch
)
5771 + mips_regnum (gdbarch
)->fp0
+ 0),
5772 4, gdbarch_byte_order (gdbarch
),
5773 readbuf
, writebuf
, 0);
5774 mips_xfer_register (gdbarch
, regcache
,
5775 (gdbarch_num_regs (gdbarch
)
5776 + mips_regnum (gdbarch
)->fp0
+ 1),
5777 4, gdbarch_byte_order (gdbarch
),
5778 readbuf
, writebuf
, 4);
5780 case BFD_ENDIAN_BIG
:
5781 mips_xfer_register (gdbarch
, regcache
,
5782 (gdbarch_num_regs (gdbarch
)
5783 + mips_regnum (gdbarch
)->fp0
+ 1),
5784 4, gdbarch_byte_order (gdbarch
),
5785 readbuf
, writebuf
, 0);
5786 mips_xfer_register (gdbarch
, regcache
,
5787 (gdbarch_num_regs (gdbarch
)
5788 + mips_regnum (gdbarch
)->fp0
+ 0),
5789 4, gdbarch_byte_order (gdbarch
),
5790 readbuf
, writebuf
, 4);
5793 internal_error (__FILE__
, __LINE__
, _("bad switch"));
5796 if (fval_reg
!= mips_fval_fpr
)
5798 /* The two 32-bit parts are always placed in GPR2 and GPR3
5799 following these registers' memory order. */
5800 mips_xfer_register (gdbarch
, regcache
,
5801 gdbarch_num_regs (gdbarch
) + 2,
5802 4, gdbarch_byte_order (gdbarch
),
5803 readbuf
, writebuf
, 0);
5804 mips_xfer_register (gdbarch
, regcache
,
5805 gdbarch_num_regs (gdbarch
) + 3,
5806 4, gdbarch_byte_order (gdbarch
),
5807 readbuf
, writebuf
, 4);
5809 return RETURN_VALUE_REGISTER_CONVENTION
;
5812 else if (type
->code () == TYPE_CODE_STRUCT
5813 && type
->num_fields () <= 2
5814 && type
->num_fields () >= 1
5815 && ((type
->num_fields () == 1
5816 && (TYPE_CODE (type
->field (0).type ())
5818 || (type
->num_fields () == 2
5819 && (TYPE_CODE (type
->field (0).type ())
5821 && (TYPE_CODE (type
->field (1).type ())
5823 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5825 /* A struct that contains one or two floats. Each value is part
5826 in the least significant part of their floating point
5830 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
5831 field
< type
->num_fields (); field
++, regnum
+= 2)
5833 int offset
= (type
->fields ()[field
].loc_bitpos () / TARGET_CHAR_BIT
);
5835 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
5837 mips_xfer_register (gdbarch
, regcache
,
5838 gdbarch_num_regs (gdbarch
) + regnum
,
5839 TYPE_LENGTH (type
->field (field
).type ()),
5840 gdbarch_byte_order (gdbarch
),
5841 readbuf
, writebuf
, offset
);
5843 return RETURN_VALUE_REGISTER_CONVENTION
;
5847 else if (type
->code () == TYPE_CODE_STRUCT
5848 || type
->code () == TYPE_CODE_UNION
)
5850 /* A structure or union. Extract the left justified value,
5851 regardless of the byte order. I.e. DO NOT USE
5855 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5856 offset
< TYPE_LENGTH (type
);
5857 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5859 int xfer
= register_size (gdbarch
, regnum
);
5860 if (offset
+ xfer
> TYPE_LENGTH (type
))
5861 xfer
= TYPE_LENGTH (type
) - offset
;
5863 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5864 offset
, xfer
, regnum
);
5865 mips_xfer_register (gdbarch
, regcache
,
5866 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
5867 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
5869 return RETURN_VALUE_REGISTER_CONVENTION
;
5874 /* A scalar extract each part but least-significant-byte
5875 justified. o32 thinks registers are 4 byte, regardless of
5879 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5880 offset
< TYPE_LENGTH (type
);
5881 offset
+= MIPS32_REGSIZE
, regnum
++)
5883 int xfer
= MIPS32_REGSIZE
;
5884 if (offset
+ xfer
> TYPE_LENGTH (type
))
5885 xfer
= TYPE_LENGTH (type
) - offset
;
5887 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5888 offset
, xfer
, regnum
);
5889 mips_xfer_register (gdbarch
, regcache
,
5890 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
5891 gdbarch_byte_order (gdbarch
),
5892 readbuf
, writebuf
, offset
);
5894 return RETURN_VALUE_REGISTER_CONVENTION
;
5898 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
5902 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
5903 struct regcache
*regcache
, CORE_ADDR bp_addr
,
5905 struct value
**args
, CORE_ADDR sp
,
5906 function_call_return_method return_method
, CORE_ADDR struct_addr
)
5912 int stack_offset
= 0;
5913 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5914 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
5916 /* For shared libraries, "t9" needs to point at the function
5918 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
5920 /* Set the return address register to point to the entry point of
5921 the program, where a breakpoint lies in wait. */
5922 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
5924 /* First ensure that the stack and structure return address (if any)
5925 are properly aligned. The stack has to be at least 64-bit
5926 aligned even on 32-bit machines, because doubles must be 64-bit
5927 aligned. For n32 and n64, stack frames need to be 128-bit
5928 aligned, so we round to this widest known alignment. */
5930 sp
= align_down (sp
, 16);
5931 struct_addr
= align_down (struct_addr
, 16);
5933 /* Now make space on the stack for the args. */
5934 for (argnum
= 0; argnum
< nargs
; argnum
++)
5936 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
5938 /* Allocate space on the stack. */
5939 arg_space
+= align_up (TYPE_LENGTH (arg_type
), MIPS64_REGSIZE
);
5941 sp
-= align_up (arg_space
, 16);
5944 fprintf_unfiltered (gdb_stdlog
,
5945 "mips_o64_push_dummy_call: sp=%s allocated %ld\n",
5946 paddress (gdbarch
, sp
),
5947 (long) align_up (arg_space
, 16));
5949 /* Initialize the integer and float register pointers. */
5950 argreg
= MIPS_A0_REGNUM
;
5951 float_argreg
= mips_fpa0_regnum (gdbarch
);
5953 /* The struct_return pointer occupies the first parameter-passing reg. */
5954 if (return_method
== return_method_struct
)
5957 fprintf_unfiltered (gdb_stdlog
,
5958 "mips_o64_push_dummy_call: "
5959 "struct_return reg=%d %s\n",
5960 argreg
, paddress (gdbarch
, struct_addr
));
5961 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
5962 stack_offset
+= MIPS64_REGSIZE
;
5965 /* Now load as many as possible of the first arguments into
5966 registers, and push the rest onto the stack. Loop thru args
5967 from first to last. */
5968 for (argnum
= 0; argnum
< nargs
; argnum
++)
5970 const gdb_byte
*val
;
5971 struct value
*arg
= args
[argnum
];
5972 struct type
*arg_type
= check_typedef (value_type (arg
));
5973 int len
= TYPE_LENGTH (arg_type
);
5974 enum type_code typecode
= arg_type
->code ();
5977 fprintf_unfiltered (gdb_stdlog
,
5978 "mips_o64_push_dummy_call: %d len=%d type=%d",
5979 argnum
+ 1, len
, (int) typecode
);
5981 val
= value_contents (arg
).data ();
5983 /* Floating point arguments passed in registers have to be
5984 treated specially. On 32-bit architectures, doubles are
5985 passed in register pairs; the even FP register gets the
5986 low word, and the odd FP register gets the high word.
5987 On O64, the first two floating point arguments are also
5988 copied to general registers, because MIPS16 functions
5989 don't use float registers for arguments. This duplication
5990 of arguments in general registers can't hurt non-MIPS16
5991 functions because those registers are normally skipped. */
5993 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5994 && float_argreg
<= mips_last_fp_arg_regnum (gdbarch
))
5996 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
5998 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5999 float_argreg
, phex (regval
, len
));
6000 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
6002 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
6003 argreg
, phex (regval
, len
));
6004 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
6006 /* Reserve space for the FP register. */
6007 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
6011 /* Copy the argument to general registers or the stack in
6012 register-sized pieces. Large arguments are split between
6013 registers and stack. */
6014 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
6015 are treated specially: Irix cc passes them in registers
6016 where gcc sometimes puts them on the stack. For maximum
6017 compatibility, we will put them in both places. */
6018 int odd_sized_struct
= (len
> MIPS64_REGSIZE
6019 && len
% MIPS64_REGSIZE
!= 0);
6022 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
6025 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
6028 /* Write this portion of the argument to the stack. */
6029 if (argreg
> mips_last_arg_regnum (gdbarch
)
6030 || odd_sized_struct
)
6032 /* Should shorter than int integer values be
6033 promoted to int before being stored? */
6034 int longword_offset
= 0;
6036 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6038 if ((typecode
== TYPE_CODE_INT
6039 || typecode
== TYPE_CODE_PTR
6040 || typecode
== TYPE_CODE_FLT
)
6042 longword_offset
= MIPS64_REGSIZE
- len
;
6047 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
6048 paddress (gdbarch
, stack_offset
));
6049 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
6050 paddress (gdbarch
, longword_offset
));
6053 addr
= sp
+ stack_offset
+ longword_offset
;
6058 fprintf_unfiltered (gdb_stdlog
, " @%s ",
6059 paddress (gdbarch
, addr
));
6060 for (i
= 0; i
< partial_len
; i
++)
6062 fprintf_unfiltered (gdb_stdlog
, "%02x",
6066 write_memory (addr
, val
, partial_len
);
6069 /* Note!!! This is NOT an else clause. Odd sized
6070 structs may go thru BOTH paths. */
6071 /* Write this portion of the argument to a general
6072 purpose register. */
6073 if (argreg
<= mips_last_arg_regnum (gdbarch
))
6075 LONGEST regval
= extract_signed_integer (val
, partial_len
,
6077 /* Value may need to be sign extended, because
6078 mips_isa_regsize() != mips_abi_regsize(). */
6080 /* A non-floating-point argument being passed in a
6081 general register. If a struct or union, and if
6082 the remaining length is smaller than the register
6083 size, we have to adjust the register value on
6086 It does not seem to be necessary to do the
6087 same for integral types. */
6089 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
6090 && partial_len
< MIPS64_REGSIZE
6091 && (typecode
== TYPE_CODE_STRUCT
6092 || typecode
== TYPE_CODE_UNION
))
6093 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
6097 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
6099 phex (regval
, MIPS64_REGSIZE
));
6100 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
6103 /* Prevent subsequent floating point arguments from
6104 being passed in floating point registers. */
6105 float_argreg
= mips_last_fp_arg_regnum (gdbarch
) + 1;
6111 /* Compute the offset into the stack at which we will
6112 copy the next parameter.
6114 In older ABIs, the caller reserved space for
6115 registers that contained arguments. This was loosely
6116 refered to as their "home". Consequently, space is
6117 always allocated. */
6119 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
6123 fprintf_unfiltered (gdb_stdlog
, "\n");
6126 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
6128 /* Return adjusted stack pointer. */
6132 static enum return_value_convention
6133 mips_o64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
6134 struct type
*type
, struct regcache
*regcache
,
6135 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
6137 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
6138 int mips16
= mips_pc_is_mips16 (gdbarch
, func_addr
);
6139 enum mips_fval_reg fval_reg
;
6141 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
6142 if (type
->code () == TYPE_CODE_STRUCT
6143 || type
->code () == TYPE_CODE_UNION
6144 || type
->code () == TYPE_CODE_ARRAY
)
6145 return RETURN_VALUE_STRUCT_CONVENTION
;
6146 else if (fp_register_arg_p (gdbarch
, type
->code (), type
))
6148 /* A floating-point value. If reading in or copying, then we get it
6149 from/put it to FP0 for standard MIPS code or GPR2 for MIPS16 code.
6150 If writing out only, then we put it to both FP0 and GPR2. We do
6151 not support reading in with no function known, if this safety
6152 check ever triggers, then we'll have to try harder. */
6153 gdb_assert (function
|| !readbuf
);
6158 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
6161 fprintf_unfiltered (gdb_stderr
, "Return float in $2\n");
6163 case mips_fval_both
:
6164 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0 and $2\n");
6167 if (fval_reg
!= mips_fval_gpr
)
6168 mips_xfer_register (gdbarch
, regcache
,
6169 (gdbarch_num_regs (gdbarch
)
6170 + mips_regnum (gdbarch
)->fp0
),
6172 gdbarch_byte_order (gdbarch
),
6173 readbuf
, writebuf
, 0);
6174 if (fval_reg
!= mips_fval_fpr
)
6175 mips_xfer_register (gdbarch
, regcache
,
6176 gdbarch_num_regs (gdbarch
) + 2,
6178 gdbarch_byte_order (gdbarch
),
6179 readbuf
, writebuf
, 0);
6180 return RETURN_VALUE_REGISTER_CONVENTION
;
6184 /* A scalar extract each part but least-significant-byte
6188 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
6189 offset
< TYPE_LENGTH (type
);
6190 offset
+= MIPS64_REGSIZE
, regnum
++)
6192 int xfer
= MIPS64_REGSIZE
;
6193 if (offset
+ xfer
> TYPE_LENGTH (type
))
6194 xfer
= TYPE_LENGTH (type
) - offset
;
6196 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
6197 offset
, xfer
, regnum
);
6198 mips_xfer_register (gdbarch
, regcache
,
6199 gdbarch_num_regs (gdbarch
) + regnum
,
6200 xfer
, gdbarch_byte_order (gdbarch
),
6201 readbuf
, writebuf
, offset
);
6203 return RETURN_VALUE_REGISTER_CONVENTION
;
6207 /* Floating point register management.
6209 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
6210 64bit operations, these early MIPS cpus treat fp register pairs
6211 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
6212 registers and offer a compatibility mode that emulates the MIPS2 fp
6213 model. When operating in MIPS2 fp compat mode, later cpu's split
6214 double precision floats into two 32-bit chunks and store them in
6215 consecutive fp regs. To display 64-bit floats stored in this
6216 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
6217 Throw in user-configurable endianness and you have a real mess.
6219 The way this works is:
6220 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
6221 double-precision value will be split across two logical registers.
6222 The lower-numbered logical register will hold the low-order bits,
6223 regardless of the processor's endianness.
6224 - If we are on a 64-bit processor, and we are looking for a
6225 single-precision value, it will be in the low ordered bits
6226 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
6227 save slot in memory.
6228 - If we are in 64-bit mode, everything is straightforward.
6230 Note that this code only deals with "live" registers at the top of the
6231 stack. We will attempt to deal with saved registers later, when
6232 the raw/cooked register interface is in place. (We need a general
6233 interface that can deal with dynamic saved register sizes -- fp
6234 regs could be 32 bits wide in one frame and 64 on the frame above
6237 /* Copy a 32-bit single-precision value from the current frame
6238 into rare_buffer. */
6241 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
6242 gdb_byte
*rare_buffer
)
6244 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6245 int raw_size
= register_size (gdbarch
, regno
);
6246 gdb_byte
*raw_buffer
= (gdb_byte
*) alloca (raw_size
);
6248 if (!deprecated_frame_register_read (frame
, regno
, raw_buffer
))
6249 error (_("can't read register %d (%s)"),
6250 regno
, gdbarch_register_name (gdbarch
, regno
));
6253 /* We have a 64-bit value for this register. Find the low-order
6257 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6262 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
6266 memcpy (rare_buffer
, raw_buffer
, 4);
6270 /* Copy a 64-bit double-precision value from the current frame into
6271 rare_buffer. This may include getting half of it from the next
6275 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
6276 gdb_byte
*rare_buffer
)
6278 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6279 int raw_size
= register_size (gdbarch
, regno
);
6281 if (raw_size
== 8 && !mips2_fp_compat (frame
))
6283 /* We have a 64-bit value for this register, and we should use
6285 if (!deprecated_frame_register_read (frame
, regno
, rare_buffer
))
6286 error (_("can't read register %d (%s)"),
6287 regno
, gdbarch_register_name (gdbarch
, regno
));
6291 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
6293 if ((rawnum
- mips_regnum (gdbarch
)->fp0
) & 1)
6294 internal_error (__FILE__
, __LINE__
,
6295 _("mips_read_fp_register_double: bad access to "
6296 "odd-numbered FP register"));
6298 /* mips_read_fp_register_single will find the correct 32 bits from
6300 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6302 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
6303 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
6307 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
6308 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
6314 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
6316 { /* Do values for FP (float) regs. */
6317 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6318 gdb_byte
*raw_buffer
;
6319 std::string flt_str
, dbl_str
;
6321 const struct type
*flt_type
= builtin_type (gdbarch
)->builtin_float
;
6322 const struct type
*dbl_type
= builtin_type (gdbarch
)->builtin_double
;
6326 alloca (2 * register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
)));
6328 fprintf_filtered (file
, "%s:", gdbarch_register_name (gdbarch
, regnum
));
6329 fprintf_filtered (file
, "%*s",
6330 4 - (int) strlen (gdbarch_register_name (gdbarch
, regnum
)),
6333 if (register_size (gdbarch
, regnum
) == 4 || mips2_fp_compat (frame
))
6335 struct value_print_options opts
;
6337 /* 4-byte registers: Print hex and floating. Also print even
6338 numbered registers as doubles. */
6339 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
6340 flt_str
= target_float_to_string (raw_buffer
, flt_type
, "%-17.9g");
6342 get_formatted_print_options (&opts
, 'x');
6343 print_scalar_formatted (raw_buffer
,
6344 builtin_type (gdbarch
)->builtin_uint32
,
6347 fprintf_filtered (file
, " flt: %s", flt_str
.c_str ());
6349 if ((regnum
- gdbarch_num_regs (gdbarch
)) % 2 == 0)
6351 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
6352 dbl_str
= target_float_to_string (raw_buffer
, dbl_type
, "%-24.17g");
6354 fprintf_filtered (file
, " dbl: %s", dbl_str
.c_str ());
6359 struct value_print_options opts
;
6361 /* Eight byte registers: print each one as hex, float and double. */
6362 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
6363 flt_str
= target_float_to_string (raw_buffer
, flt_type
, "%-17.9g");
6365 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
6366 dbl_str
= target_float_to_string (raw_buffer
, dbl_type
, "%-24.17g");
6368 get_formatted_print_options (&opts
, 'x');
6369 print_scalar_formatted (raw_buffer
,
6370 builtin_type (gdbarch
)->builtin_uint64
,
6373 fprintf_filtered (file
, " flt: %s", flt_str
.c_str ());
6374 fprintf_filtered (file
, " dbl: %s", dbl_str
.c_str ());
6379 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
6382 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6383 struct value_print_options opts
;
6386 if (mips_float_register_p (gdbarch
, regnum
))
6388 mips_print_fp_register (file
, frame
, regnum
);
6392 val
= get_frame_register_value (frame
, regnum
);
6394 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
6396 /* The problem with printing numeric register names (r26, etc.) is that
6397 the user can't use them on input. Probably the best solution is to
6398 fix it so that either the numeric or the funky (a2, etc.) names
6399 are accepted on input. */
6400 if (regnum
< MIPS_NUMREGS
)
6401 fprintf_filtered (file
, "(r%d): ", regnum
);
6403 fprintf_filtered (file
, ": ");
6405 get_formatted_print_options (&opts
, 'x');
6406 value_print_scalar_formatted (val
, &opts
, 0, file
);
6409 /* Print IEEE exception condition bits in FLAGS. */
6412 print_fpu_flags (struct ui_file
*file
, int flags
)
6414 if (flags
& (1 << 0))
6415 fputs_filtered (" inexact", file
);
6416 if (flags
& (1 << 1))
6417 fputs_filtered (" uflow", file
);
6418 if (flags
& (1 << 2))
6419 fputs_filtered (" oflow", file
);
6420 if (flags
& (1 << 3))
6421 fputs_filtered (" div0", file
);
6422 if (flags
& (1 << 4))
6423 fputs_filtered (" inval", file
);
6424 if (flags
& (1 << 5))
6425 fputs_filtered (" unimp", file
);
6426 fputc_filtered ('\n', file
);
6429 /* Print interesting information about the floating point processor
6430 (if present) or emulator. */
6433 mips_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
6434 struct frame_info
*frame
, const char *args
)
6436 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
6437 enum mips_fpu_type type
= mips_get_fpu_type (gdbarch
);
6441 if (fcsr
== -1 || !read_frame_register_unsigned (frame
, fcsr
, &fcs
))
6442 type
= MIPS_FPU_NONE
;
6444 fprintf_filtered (file
, "fpu type: %s\n",
6445 type
== MIPS_FPU_DOUBLE
? "double-precision"
6446 : type
== MIPS_FPU_SINGLE
? "single-precision"
6449 if (type
== MIPS_FPU_NONE
)
6452 fprintf_filtered (file
, "reg size: %d bits\n",
6453 register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) * 8);
6455 fputs_filtered ("cond :", file
);
6456 if (fcs
& (1 << 23))
6457 fputs_filtered (" 0", file
);
6458 for (i
= 1; i
<= 7; i
++)
6459 if (fcs
& (1 << (24 + i
)))
6460 fprintf_filtered (file
, " %d", i
);
6461 fputc_filtered ('\n', file
);
6463 fputs_filtered ("cause :", file
);
6464 print_fpu_flags (file
, (fcs
>> 12) & 0x3f);
6465 fputs ("mask :", stdout
);
6466 print_fpu_flags (file
, (fcs
>> 7) & 0x1f);
6467 fputs ("flags :", stdout
);
6468 print_fpu_flags (file
, (fcs
>> 2) & 0x1f);
6470 fputs_filtered ("rounding: ", file
);
6473 case 0: fputs_filtered ("nearest\n", file
); break;
6474 case 1: fputs_filtered ("zero\n", file
); break;
6475 case 2: fputs_filtered ("+inf\n", file
); break;
6476 case 3: fputs_filtered ("-inf\n", file
); break;
6479 fputs_filtered ("flush :", file
);
6480 if (fcs
& (1 << 21))
6481 fputs_filtered (" nearest", file
);
6482 if (fcs
& (1 << 22))
6483 fputs_filtered (" override", file
);
6484 if (fcs
& (1 << 24))
6485 fputs_filtered (" zero", file
);
6486 if ((fcs
& (0xb << 21)) == 0)
6487 fputs_filtered (" no", file
);
6488 fputc_filtered ('\n', file
);
6490 fprintf_filtered (file
, "nan2008 : %s\n", fcs
& (1 << 18) ? "yes" : "no");
6491 fprintf_filtered (file
, "abs2008 : %s\n", fcs
& (1 << 19) ? "yes" : "no");
6492 fputc_filtered ('\n', file
);
6494 default_print_float_info (gdbarch
, file
, frame
, args
);
6497 /* Replacement for generic do_registers_info.
6498 Print regs in pretty columns. */
6501 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
6504 fprintf_filtered (file
, " ");
6505 mips_print_fp_register (file
, frame
, regnum
);
6506 fprintf_filtered (file
, "\n");
6511 /* Print a row's worth of GP (int) registers, with name labels above. */
6514 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
6517 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6518 /* Do values for GP (int) regs. */
6519 const gdb_byte
*raw_buffer
;
6520 struct value
*value
;
6521 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols
6526 /* For GP registers, we print a separate row of names above the vals. */
6527 for (col
= 0, regnum
= start_regnum
;
6528 col
< ncols
&& regnum
< gdbarch_num_cooked_regs (gdbarch
);
6531 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
6532 continue; /* unused register */
6533 if (mips_float_register_p (gdbarch
, regnum
))
6534 break; /* End the row: reached FP register. */
6535 /* Large registers are handled separately. */
6536 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
6539 break; /* End the row before this register. */
6541 /* Print this register on a row by itself. */
6542 mips_print_register (file
, frame
, regnum
);
6543 fprintf_filtered (file
, "\n");
6547 fprintf_filtered (file
, " ");
6548 fprintf_filtered (file
,
6549 mips_abi_regsize (gdbarch
) == 8 ? "%17s" : "%9s",
6550 gdbarch_register_name (gdbarch
, regnum
));
6557 /* Print the R0 to R31 names. */
6558 if ((start_regnum
% gdbarch_num_regs (gdbarch
)) < MIPS_NUMREGS
)
6559 fprintf_filtered (file
, "\n R%-4d",
6560 start_regnum
% gdbarch_num_regs (gdbarch
));
6562 fprintf_filtered (file
, "\n ");
6564 /* Now print the values in hex, 4 or 8 to the row. */
6565 for (col
= 0, regnum
= start_regnum
;
6566 col
< ncols
&& regnum
< gdbarch_num_cooked_regs (gdbarch
);
6569 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
6570 continue; /* unused register */
6571 if (mips_float_register_p (gdbarch
, regnum
))
6572 break; /* End row: reached FP register. */
6573 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
6574 break; /* End row: large register. */
6576 /* OK: get the data in raw format. */
6577 value
= get_frame_register_value (frame
, regnum
);
6578 if (value_optimized_out (value
)
6579 || !value_entirely_available (value
))
6581 fprintf_filtered (file
, "%*s ",
6582 (int) mips_abi_regsize (gdbarch
) * 2,
6583 (mips_abi_regsize (gdbarch
) == 4 ? "<unavl>"
6584 : "<unavailable>"));
6588 raw_buffer
= value_contents_all (value
).data ();
6589 /* pad small registers */
6591 byte
< (mips_abi_regsize (gdbarch
)
6592 - register_size (gdbarch
, regnum
)); byte
++)
6593 fprintf_filtered (file
, " ");
6594 /* Now print the register value in hex, endian order. */
6595 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6597 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
6598 byte
< register_size (gdbarch
, regnum
); byte
++)
6599 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
6601 for (byte
= register_size (gdbarch
, regnum
) - 1;
6603 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
6604 fprintf_filtered (file
, " ");
6607 if (col
> 0) /* ie. if we actually printed anything... */
6608 fprintf_filtered (file
, "\n");
6613 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */
6616 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
6617 struct frame_info
*frame
, int regnum
, int all
)
6619 if (regnum
!= -1) /* Do one specified register. */
6621 gdb_assert (regnum
>= gdbarch_num_regs (gdbarch
));
6622 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
6623 error (_("Not a valid register for the current processor type"));
6625 mips_print_register (file
, frame
, regnum
);
6626 fprintf_filtered (file
, "\n");
6629 /* Do all (or most) registers. */
6631 regnum
= gdbarch_num_regs (gdbarch
);
6632 while (regnum
< gdbarch_num_cooked_regs (gdbarch
))
6634 if (mips_float_register_p (gdbarch
, regnum
))
6636 if (all
) /* True for "INFO ALL-REGISTERS" command. */
6637 regnum
= print_fp_register_row (file
, frame
, regnum
);
6639 regnum
+= MIPS_NUMREGS
; /* Skip floating point regs. */
6642 regnum
= print_gp_register_row (file
, frame
, regnum
);
6648 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
6649 struct frame_info
*frame
)
6651 CORE_ADDR pc
= get_frame_pc (frame
);
6656 if ((mips_pc_is_mips (pc
)
6657 && !mips32_insn_at_pc_has_delay_slot (gdbarch
, pc
))
6658 || (mips_pc_is_micromips (gdbarch
, pc
)
6659 && !micromips_insn_at_pc_has_delay_slot (gdbarch
, pc
, 0))
6660 || (mips_pc_is_mips16 (gdbarch
, pc
)
6661 && !mips16_insn_at_pc_has_delay_slot (gdbarch
, pc
, 0)))
6664 isa
= mips_pc_isa (gdbarch
, pc
);
6665 /* _has_delay_slot above will have validated the read. */
6666 insn
= mips_fetch_instruction (gdbarch
, isa
, pc
, NULL
);
6667 size
= mips_insn_size (isa
, insn
);
6669 const address_space
*aspace
= get_frame_address_space (frame
);
6671 return breakpoint_here_p (aspace
, pc
+ size
) != no_breakpoint_here
;
6674 /* To skip prologues, I use this predicate. Returns either PC itself
6675 if the code at PC does not look like a function prologue; otherwise
6676 returns an address that (if we're lucky) follows the prologue. If
6677 LENIENT, then we must skip everything which is involved in setting
6678 up the frame (it's OK to skip more, just so long as we don't skip
6679 anything which might clobber the registers which are being saved.
6680 We must skip more in the case where part of the prologue is in the
6681 delay slot of a non-prologue instruction). */
6684 mips_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6687 CORE_ADDR func_addr
;
6689 /* See if we can determine the end of the prologue via the symbol table.
6690 If so, then return either PC, or the PC after the prologue, whichever
6692 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
6694 CORE_ADDR post_prologue_pc
6695 = skip_prologue_using_sal (gdbarch
, func_addr
);
6696 if (post_prologue_pc
!= 0)
6697 return std::max (pc
, post_prologue_pc
);
6700 /* Can't determine prologue from the symbol table, need to examine
6703 /* Find an upper limit on the function prologue using the debug
6704 information. If the debug information could not be used to provide
6705 that bound, then use an arbitrary large number as the upper bound. */
6706 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
6708 limit_pc
= pc
+ 100; /* Magic. */
6710 if (mips_pc_is_mips16 (gdbarch
, pc
))
6711 return mips16_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6712 else if (mips_pc_is_micromips (gdbarch
, pc
))
6713 return micromips_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6715 return mips32_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6718 /* Implement the stack_frame_destroyed_p gdbarch method (32-bit version).
6719 This is a helper function for mips_stack_frame_destroyed_p. */
6722 mips32_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6724 CORE_ADDR func_addr
= 0, func_end
= 0;
6726 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6728 /* The MIPS epilogue is max. 12 bytes long. */
6729 CORE_ADDR addr
= func_end
- 12;
6731 if (addr
< func_addr
+ 4)
6732 addr
= func_addr
+ 4;
6736 for (; pc
< func_end
; pc
+= MIPS_INSN32_SIZE
)
6738 unsigned long high_word
;
6741 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
6742 high_word
= (inst
>> 16) & 0xffff;
6744 if (high_word
!= 0x27bd /* addiu $sp,$sp,offset */
6745 && high_word
!= 0x67bd /* daddiu $sp,$sp,offset */
6746 && inst
!= 0x03e00008 /* jr $ra */
6747 && inst
!= 0x00000000) /* nop */
6757 /* Implement the stack_frame_destroyed_p gdbarch method (microMIPS version).
6758 This is a helper function for mips_stack_frame_destroyed_p. */
6761 micromips_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6763 CORE_ADDR func_addr
= 0;
6764 CORE_ADDR func_end
= 0;
6772 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6775 /* The microMIPS epilogue is max. 12 bytes long. */
6776 addr
= func_end
- 12;
6778 if (addr
< func_addr
+ 2)
6779 addr
= func_addr
+ 2;
6783 for (; pc
< func_end
; pc
+= loc
)
6786 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
6787 loc
+= MIPS_INSN16_SIZE
;
6788 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
6790 /* 32-bit instructions. */
6791 case 2 * MIPS_INSN16_SIZE
:
6793 insn
|= mips_fetch_instruction (gdbarch
,
6794 ISA_MICROMIPS
, pc
+ loc
, NULL
);
6795 loc
+= MIPS_INSN16_SIZE
;
6796 switch (micromips_op (insn
>> 16))
6798 case 0xc: /* ADDIU: bits 001100 */
6799 case 0x17: /* DADDIU: bits 010111 */
6800 sreg
= b0s5_reg (insn
>> 16);
6801 dreg
= b5s5_reg (insn
>> 16);
6802 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
6803 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
6804 /* (D)ADDIU $sp, imm */
6814 /* 16-bit instructions. */
6815 case MIPS_INSN16_SIZE
:
6816 switch (micromips_op (insn
))
6818 case 0x3: /* MOVE: bits 000011 */
6819 sreg
= b0s5_reg (insn
);
6820 dreg
= b5s5_reg (insn
);
6821 if (sreg
== 0 && dreg
== 0)
6822 /* MOVE $zero, $zero aka NOP */
6826 case 0x11: /* POOL16C: bits 010001 */
6827 if (b5s5_op (insn
) == 0x18
6828 /* JRADDIUSP: bits 010011 11000 */
6829 || (b5s5_op (insn
) == 0xd
6830 /* JRC: bits 010011 01101 */
6831 && b0s5_reg (insn
) == MIPS_RA_REGNUM
))
6836 case 0x13: /* POOL16D: bits 010011 */
6837 offset
= micromips_decode_imm9 (b1s9_imm (insn
));
6838 if ((insn
& 0x1) == 0x1
6839 /* ADDIUSP: bits 010011 1 */
6853 /* Implement the stack_frame_destroyed_p gdbarch method (16-bit version).
6854 This is a helper function for mips_stack_frame_destroyed_p. */
6857 mips16_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6859 CORE_ADDR func_addr
= 0, func_end
= 0;
6861 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6863 /* The MIPS epilogue is max. 12 bytes long. */
6864 CORE_ADDR addr
= func_end
- 12;
6866 if (addr
< func_addr
+ 4)
6867 addr
= func_addr
+ 4;
6871 for (; pc
< func_end
; pc
+= MIPS_INSN16_SIZE
)
6873 unsigned short inst
;
6875 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, pc
, NULL
);
6877 if ((inst
& 0xf800) == 0xf000) /* extend */
6880 if (inst
!= 0x6300 /* addiu $sp,offset */
6881 && inst
!= 0xfb00 /* daddiu $sp,$sp,offset */
6882 && inst
!= 0xe820 /* jr $ra */
6883 && inst
!= 0xe8a0 /* jrc $ra */
6884 && inst
!= 0x6500) /* nop */
6894 /* Implement the stack_frame_destroyed_p gdbarch method.
6896 The epilogue is defined here as the area at the end of a function,
6897 after an instruction which destroys the function's stack frame. */
6900 mips_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6902 if (mips_pc_is_mips16 (gdbarch
, pc
))
6903 return mips16_stack_frame_destroyed_p (gdbarch
, pc
);
6904 else if (mips_pc_is_micromips (gdbarch
, pc
))
6905 return micromips_stack_frame_destroyed_p (gdbarch
, pc
);
6907 return mips32_stack_frame_destroyed_p (gdbarch
, pc
);
6910 /* Commands to show/set the MIPS FPU type. */
6913 show_mipsfpu_command (const char *args
, int from_tty
)
6917 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_mips
)
6920 ("The MIPS floating-point coprocessor is unknown "
6921 "because the current architecture is not MIPS.\n");
6925 switch (mips_get_fpu_type (target_gdbarch ()))
6927 case MIPS_FPU_SINGLE
:
6928 fpu
= "single-precision";
6930 case MIPS_FPU_DOUBLE
:
6931 fpu
= "double-precision";
6934 fpu
= "absent (none)";
6937 internal_error (__FILE__
, __LINE__
, _("bad switch"));
6939 if (mips_fpu_type_auto
)
6940 printf_filtered ("The MIPS floating-point coprocessor "
6941 "is set automatically (currently %s)\n",
6945 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
6950 set_mipsfpu_single_command (const char *args
, int from_tty
)
6952 struct gdbarch_info info
;
6953 mips_fpu_type
= MIPS_FPU_SINGLE
;
6954 mips_fpu_type_auto
= 0;
6955 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6956 instead of relying on globals. Doing that would let generic code
6957 handle the search for this specific architecture. */
6958 if (!gdbarch_update_p (info
))
6959 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6963 set_mipsfpu_double_command (const char *args
, int from_tty
)
6965 struct gdbarch_info info
;
6966 mips_fpu_type
= MIPS_FPU_DOUBLE
;
6967 mips_fpu_type_auto
= 0;
6968 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6969 instead of relying on globals. Doing that would let generic code
6970 handle the search for this specific architecture. */
6971 if (!gdbarch_update_p (info
))
6972 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6976 set_mipsfpu_none_command (const char *args
, int from_tty
)
6978 struct gdbarch_info info
;
6979 mips_fpu_type
= MIPS_FPU_NONE
;
6980 mips_fpu_type_auto
= 0;
6981 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6982 instead of relying on globals. Doing that would let generic code
6983 handle the search for this specific architecture. */
6984 if (!gdbarch_update_p (info
))
6985 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6989 set_mipsfpu_auto_command (const char *args
, int from_tty
)
6991 mips_fpu_type_auto
= 1;
6994 /* Just like reinit_frame_cache, but with the right arguments to be
6995 callable as an sfunc. */
6998 reinit_frame_cache_sfunc (const char *args
, int from_tty
,
6999 struct cmd_list_element
*c
)
7001 reinit_frame_cache ();
7005 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
7007 gdb_disassembler
*di
7008 = static_cast<gdb_disassembler
*>(info
->application_data
);
7009 struct gdbarch
*gdbarch
= di
->arch ();
7011 /* FIXME: cagney/2003-06-26: Is this even necessary? The
7012 disassembler needs to be able to locally determine the ISA, and
7013 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
7015 if (mips_pc_is_mips16 (gdbarch
, memaddr
))
7016 info
->mach
= bfd_mach_mips16
;
7017 else if (mips_pc_is_micromips (gdbarch
, memaddr
))
7018 info
->mach
= bfd_mach_mips_micromips
;
7020 /* Round down the instruction address to the appropriate boundary. */
7021 memaddr
&= (info
->mach
== bfd_mach_mips16
7022 || info
->mach
== bfd_mach_mips_micromips
) ? ~1 : ~3;
7024 return default_print_insn (memaddr
, info
);
7027 /* Implement the breakpoint_kind_from_pc gdbarch method. */
7030 mips_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
7032 CORE_ADDR pc
= *pcptr
;
7034 if (mips_pc_is_mips16 (gdbarch
, pc
))
7036 *pcptr
= unmake_compact_addr (pc
);
7037 return MIPS_BP_KIND_MIPS16
;
7039 else if (mips_pc_is_micromips (gdbarch
, pc
))
7044 *pcptr
= unmake_compact_addr (pc
);
7045 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, &status
);
7046 if (status
|| (mips_insn_size (ISA_MICROMIPS
, insn
) == 2))
7047 return MIPS_BP_KIND_MICROMIPS16
;
7049 return MIPS_BP_KIND_MICROMIPS32
;
7052 return MIPS_BP_KIND_MIPS32
;
7055 /* Implement the sw_breakpoint_from_kind gdbarch method. */
7057 static const gdb_byte
*
7058 mips_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
7060 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
7064 case MIPS_BP_KIND_MIPS16
:
7066 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
7067 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
7070 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7071 return mips16_big_breakpoint
;
7073 return mips16_little_breakpoint
;
7075 case MIPS_BP_KIND_MICROMIPS16
:
7077 static gdb_byte micromips16_big_breakpoint
[] = { 0x46, 0x85 };
7078 static gdb_byte micromips16_little_breakpoint
[] = { 0x85, 0x46 };
7082 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7083 return micromips16_big_breakpoint
;
7085 return micromips16_little_breakpoint
;
7087 case MIPS_BP_KIND_MICROMIPS32
:
7089 static gdb_byte micromips32_big_breakpoint
[] = { 0, 0x5, 0, 0x7 };
7090 static gdb_byte micromips32_little_breakpoint
[] = { 0x5, 0, 0x7, 0 };
7093 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7094 return micromips32_big_breakpoint
;
7096 return micromips32_little_breakpoint
;
7098 case MIPS_BP_KIND_MIPS32
:
7100 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
7101 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
7104 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7105 return big_breakpoint
;
7107 return little_breakpoint
;
7110 gdb_assert_not_reached ("unexpected mips breakpoint kind");
7114 /* Return non-zero if the standard MIPS instruction INST has a branch
7115 delay slot (i.e. it is a jump or branch instruction). This function
7116 is based on mips32_next_pc. */
7119 mips32_instruction_has_delay_slot (struct gdbarch
*gdbarch
, ULONGEST inst
)
7125 op
= itype_op (inst
);
7126 if ((inst
& 0xe0000000) != 0)
7128 rs
= itype_rs (inst
);
7129 rt
= itype_rt (inst
);
7130 return (is_octeon_bbit_op (op
, gdbarch
)
7131 || op
>> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
7132 || op
== 29 /* JALX: bits 011101 */
7135 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
7136 || (rs
== 9 && (rt
& 0x2) == 0)
7137 /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */
7138 || (rs
== 10 && (rt
& 0x2) == 0))));
7139 /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */
7142 switch (op
& 0x07) /* extract bits 28,27,26 */
7144 case 0: /* SPECIAL */
7145 op
= rtype_funct (inst
);
7146 return (op
== 8 /* JR */
7147 || op
== 9); /* JALR */
7148 break; /* end SPECIAL */
7149 case 1: /* REGIMM */
7150 rs
= itype_rs (inst
);
7151 rt
= itype_rt (inst
); /* branch condition */
7152 return ((rt
& 0xc) == 0
7153 /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */
7154 /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */
7155 || ((rt
& 0x1e) == 0x1c && rs
== 0));
7156 /* BPOSGE32, BPOSGE64: bits 1110x */
7157 break; /* end REGIMM */
7158 default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */
7164 /* Return non-zero if a standard MIPS instruction at ADDR has a branch
7165 delay slot (i.e. it is a jump or branch instruction). */
7168 mips32_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
7173 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, addr
, &status
);
7177 return mips32_instruction_has_delay_slot (gdbarch
, insn
);
7180 /* Return non-zero if the microMIPS instruction INSN, comprising the
7181 16-bit major opcode word in the high 16 bits and any second word
7182 in the low 16 bits, has a branch delay slot (i.e. it is a non-compact
7183 jump or branch instruction). The instruction must be 32-bit if
7184 MUSTBE32 is set or can be any instruction otherwise. */
7187 micromips_instruction_has_delay_slot (ULONGEST insn
, int mustbe32
)
7189 ULONGEST major
= insn
>> 16;
7191 switch (micromips_op (major
))
7193 /* 16-bit instructions. */
7194 case 0x33: /* B16: bits 110011 */
7195 case 0x2b: /* BNEZ16: bits 101011 */
7196 case 0x23: /* BEQZ16: bits 100011 */
7198 case 0x11: /* POOL16C: bits 010001 */
7200 && ((b5s5_op (major
) == 0xc
7201 /* JR16: bits 010001 01100 */
7202 || (b5s5_op (major
) & 0x1e) == 0xe)));
7203 /* JALR16, JALRS16: bits 010001 0111x */
7204 /* 32-bit instructions. */
7205 case 0x3d: /* JAL: bits 111101 */
7206 case 0x3c: /* JALX: bits 111100 */
7207 case 0x35: /* J: bits 110101 */
7208 case 0x2d: /* BNE: bits 101101 */
7209 case 0x25: /* BEQ: bits 100101 */
7210 case 0x1d: /* JALS: bits 011101 */
7212 case 0x10: /* POOL32I: bits 010000 */
7213 return ((b5s5_op (major
) & 0x1c) == 0x0
7214 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
7215 || (b5s5_op (major
) & 0x1d) == 0x4
7216 /* BLEZ, BGTZ: bits 010000 001x0 */
7217 || (b5s5_op (major
) & 0x1d) == 0x11
7218 /* BLTZALS, BGEZALS: bits 010000 100x1 */
7219 || ((b5s5_op (major
) & 0x1e) == 0x14
7220 && (major
& 0x3) == 0x0)
7221 /* BC2F, BC2T: bits 010000 1010x xxx00 */
7222 || (b5s5_op (major
) & 0x1e) == 0x1a
7223 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
7224 || ((b5s5_op (major
) & 0x1e) == 0x1c
7225 && (major
& 0x3) == 0x0)
7226 /* BC1F, BC1T: bits 010000 1110x xxx00 */
7227 || ((b5s5_op (major
) & 0x1c) == 0x1c
7228 && (major
& 0x3) == 0x1));
7229 /* BC1ANY*: bits 010000 111xx xxx01 */
7230 case 0x0: /* POOL32A: bits 000000 */
7231 return (b0s6_op (insn
) == 0x3c
7232 /* POOL32Axf: bits 000000 ... 111100 */
7233 && (b6s10_ext (insn
) & 0x2bf) == 0x3c);
7234 /* JALR, JALR.HB: 000000 000x111100 111100 */
7235 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
7241 /* Return non-zero if a microMIPS instruction at ADDR has a branch delay
7242 slot (i.e. it is a non-compact jump instruction). The instruction
7243 must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */
7246 micromips_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
7247 CORE_ADDR addr
, int mustbe32
)
7253 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, addr
, &status
);
7256 size
= mips_insn_size (ISA_MICROMIPS
, insn
);
7258 if (size
== 2 * MIPS_INSN16_SIZE
)
7260 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, addr
, &status
);
7265 return micromips_instruction_has_delay_slot (insn
, mustbe32
);
7268 /* Return non-zero if the MIPS16 instruction INST, which must be
7269 a 32-bit instruction if MUSTBE32 is set or can be any instruction
7270 otherwise, has a branch delay slot (i.e. it is a non-compact jump
7271 instruction). This function is based on mips16_next_pc. */
7274 mips16_instruction_has_delay_slot (unsigned short inst
, int mustbe32
)
7276 if ((inst
& 0xf89f) == 0xe800) /* JR/JALR (16-bit instruction) */
7278 return (inst
& 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */
7281 /* Return non-zero if a MIPS16 instruction at ADDR has a branch delay
7282 slot (i.e. it is a non-compact jump instruction). The instruction
7283 must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */
7286 mips16_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
7287 CORE_ADDR addr
, int mustbe32
)
7289 unsigned short insn
;
7292 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, addr
, &status
);
7296 return mips16_instruction_has_delay_slot (insn
, mustbe32
);
7299 /* Calculate the starting address of the MIPS memory segment BPADDR is in.
7300 This assumes KSSEG exists. */
7303 mips_segment_boundary (CORE_ADDR bpaddr
)
7305 CORE_ADDR mask
= CORE_ADDR_MAX
;
7308 if (sizeof (CORE_ADDR
) == 8)
7309 /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid
7310 a compiler warning produced where CORE_ADDR is a 32-bit type even
7311 though in that case this is dead code). */
7312 switch (bpaddr
>> ((sizeof (CORE_ADDR
) << 3) - 2) & 3)
7315 if (bpaddr
== (bfd_signed_vma
) (int32_t) bpaddr
)
7316 segsize
= 29; /* 32-bit compatibility segment */
7318 segsize
= 62; /* xkseg */
7320 case 2: /* xkphys */
7323 default: /* xksseg (1), xkuseg/kuseg (0) */
7327 else if (bpaddr
& 0x80000000) /* kernel segment */
7330 segsize
= 31; /* user segment */
7332 return bpaddr
& mask
;
7335 /* Move the breakpoint at BPADDR out of any branch delay slot by shifting
7336 it backwards if necessary. Return the address of the new location. */
7339 mips_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
7341 CORE_ADDR prev_addr
;
7343 CORE_ADDR func_addr
;
7345 /* If a breakpoint is set on the instruction in a branch delay slot,
7346 GDB gets confused. When the breakpoint is hit, the PC isn't on
7347 the instruction in the branch delay slot, the PC will point to
7348 the branch instruction. Since the PC doesn't match any known
7349 breakpoints, GDB reports a trap exception.
7351 There are two possible fixes for this problem.
7353 1) When the breakpoint gets hit, see if the BD bit is set in the
7354 Cause register (which indicates the last exception occurred in a
7355 branch delay slot). If the BD bit is set, fix the PC to point to
7356 the instruction in the branch delay slot.
7358 2) When the user sets the breakpoint, don't allow him to set the
7359 breakpoint on the instruction in the branch delay slot. Instead
7360 move the breakpoint to the branch instruction (which will have
7363 The problem with the first solution is that if the user then
7364 single-steps the processor, the branch instruction will get
7365 skipped (since GDB thinks the PC is on the instruction in the
7368 So, we'll use the second solution. To do this we need to know if
7369 the instruction we're trying to set the breakpoint on is in the
7370 branch delay slot. */
7372 boundary
= mips_segment_boundary (bpaddr
);
7374 /* Make sure we don't scan back before the beginning of the current
7375 function, since we may fetch constant data or insns that look like
7376 a jump. Of course we might do that anyway if the compiler has
7377 moved constants inline. :-( */
7378 if (find_pc_partial_function (bpaddr
, NULL
, &func_addr
, NULL
)
7379 && func_addr
> boundary
&& func_addr
<= bpaddr
)
7380 boundary
= func_addr
;
7382 if (mips_pc_is_mips (bpaddr
))
7384 if (bpaddr
== boundary
)
7387 /* If the previous instruction has a branch delay slot, we have
7388 to move the breakpoint to the branch instruction. */
7389 prev_addr
= bpaddr
- 4;
7390 if (mips32_insn_at_pc_has_delay_slot (gdbarch
, prev_addr
))
7395 int (*insn_at_pc_has_delay_slot
) (struct gdbarch
*, CORE_ADDR
, int);
7396 CORE_ADDR addr
, jmpaddr
;
7399 boundary
= unmake_compact_addr (boundary
);
7401 /* The only MIPS16 instructions with delay slots are JAL, JALX,
7402 JALR and JR. An absolute JAL/JALX is always 4 bytes long,
7403 so try for that first, then try the 2 byte JALR/JR.
7404 The microMIPS ASE has a whole range of jumps and branches
7405 with delay slots, some of which take 4 bytes and some take
7406 2 bytes, so the idea is the same.
7407 FIXME: We have to assume that bpaddr is not the second half
7408 of an extended instruction. */
7409 insn_at_pc_has_delay_slot
= (mips_pc_is_micromips (gdbarch
, bpaddr
)
7410 ? micromips_insn_at_pc_has_delay_slot
7411 : mips16_insn_at_pc_has_delay_slot
);
7415 for (i
= 1; i
< 4; i
++)
7417 if (unmake_compact_addr (addr
) == boundary
)
7419 addr
-= MIPS_INSN16_SIZE
;
7420 if (i
== 1 && insn_at_pc_has_delay_slot (gdbarch
, addr
, 0))
7421 /* Looks like a JR/JALR at [target-1], but it could be
7422 the second word of a previous JAL/JALX, so record it
7423 and check back one more. */
7425 else if (i
> 1 && insn_at_pc_has_delay_slot (gdbarch
, addr
, 1))
7428 /* Looks like a JAL/JALX at [target-2], but it could also
7429 be the second word of a previous JAL/JALX, record it,
7430 and check back one more. */
7433 /* Looks like a JAL/JALX at [target-3], so any previously
7434 recorded JAL/JALX or JR/JALR must be wrong, because:
7437 -2: JAL-ext (can't be JAL/JALX)
7438 -1: bdslot (can't be JR/JALR)
7441 Of course it could be another JAL-ext which looks
7442 like a JAL, but in that case we'd have broken out
7443 of this loop at [target-2]:
7447 -2: bdslot (can't be jmp)
7454 /* Not a jump instruction: if we're at [target-1] this
7455 could be the second word of a JAL/JALX, so continue;
7456 otherwise we're done. */
7469 /* Return non-zero if SUFFIX is one of the numeric suffixes used for MIPS16
7470 call stubs, one of 1, 2, 5, 6, 9, 10, or, if ZERO is non-zero, also 0. */
7473 mips_is_stub_suffix (const char *suffix
, int zero
)
7478 return zero
&& suffix
[1] == '\0';
7480 return suffix
[1] == '\0' || (suffix
[1] == '0' && suffix
[2] == '\0');
7485 return suffix
[1] == '\0';
7491 /* Return non-zero if MODE is one of the mode infixes used for MIPS16
7492 call stubs, one of sf, df, sc, or dc. */
7495 mips_is_stub_mode (const char *mode
)
7497 return ((mode
[0] == 's' || mode
[0] == 'd')
7498 && (mode
[1] == 'f' || mode
[1] == 'c'));
7501 /* Code at PC is a compiler-generated stub. Such a stub for a function
7502 bar might have a name like __fn_stub_bar, and might look like this:
7509 followed by (or interspersed with):
7516 addiu $25, $25, %lo(bar)
7519 ($1 may be used in old code; for robustness we accept any register)
7522 lui $28, %hi(_gp_disp)
7523 addiu $28, $28, %lo(_gp_disp)
7526 addiu $25, $25, %lo(bar)
7529 In the case of a __call_stub_bar stub, the sequence to set up
7530 arguments might look like this:
7537 followed by (or interspersed with) one of the jump sequences above.
7539 In the case of a __call_stub_fp_bar stub, JAL or JALR is used instead
7540 of J or JR, respectively, followed by:
7546 We are at the beginning of the stub here, and scan down and extract
7547 the target address from the jump immediate instruction or, if a jump
7548 register instruction is used, from the register referred. Return
7549 the value of PC calculated or 0 if inconclusive.
7551 The limit on the search is arbitrarily set to 20 instructions. FIXME. */
7554 mips_get_mips16_fn_stub_pc (struct frame_info
*frame
, CORE_ADDR pc
)
7556 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7557 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7558 int addrreg
= MIPS_ZERO_REGNUM
;
7559 CORE_ADDR start_pc
= pc
;
7560 CORE_ADDR target_pc
= 0;
7567 status
== 0 && target_pc
== 0 && i
< 20;
7568 i
++, pc
+= MIPS_INSN32_SIZE
)
7570 ULONGEST inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
7576 switch (itype_op (inst
))
7578 case 0: /* SPECIAL */
7579 switch (rtype_funct (inst
))
7583 rs
= rtype_rs (inst
);
7584 if (rs
== MIPS_GP_REGNUM
)
7585 target_pc
= gp
; /* Hmm... */
7586 else if (rs
== addrreg
)
7590 case 0x21: /* ADDU */
7591 rt
= rtype_rt (inst
);
7592 rs
= rtype_rs (inst
);
7593 rd
= rtype_rd (inst
);
7594 if (rd
== MIPS_GP_REGNUM
7595 && ((rs
== MIPS_GP_REGNUM
&& rt
== MIPS_T9_REGNUM
)
7596 || (rs
== MIPS_T9_REGNUM
&& rt
== MIPS_GP_REGNUM
)))
7604 target_pc
= jtype_target (inst
) << 2;
7605 target_pc
+= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
7609 rt
= itype_rt (inst
);
7610 rs
= itype_rs (inst
);
7613 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
7614 if (rt
== MIPS_GP_REGNUM
)
7616 else if (rt
== addrreg
)
7622 rt
= itype_rt (inst
);
7623 imm
= ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 16;
7624 if (rt
== MIPS_GP_REGNUM
)
7626 else if (rt
!= MIPS_ZERO_REGNUM
)
7634 rt
= itype_rt (inst
);
7635 rs
= itype_rs (inst
);
7636 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
7637 if (gp
!= 0 && rs
== MIPS_GP_REGNUM
)
7641 memset (buf
, 0, sizeof (buf
));
7642 status
= target_read_memory (gp
+ imm
, buf
, sizeof (buf
));
7644 addr
= extract_signed_integer (buf
, sizeof (buf
), byte_order
);
7653 /* If PC is in a MIPS16 call or return stub, return the address of the
7654 target PC, which is either the callee or the caller. There are several
7655 cases which must be handled:
7657 * If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7658 and the target PC is in $31 ($ra).
7659 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7660 and the target PC is in $2.
7661 * If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7662 i.e. before the JALR instruction, this is effectively a call stub
7663 and the target PC is in $2. Otherwise this is effectively
7664 a return stub and the target PC is in $18.
7665 * If the PC is at the start of __call_stub_fp_*, i.e. before the
7666 JAL or JALR instruction, this is effectively a call stub and the
7667 target PC is buried in the instruction stream. Otherwise this
7668 is effectively a return stub and the target PC is in $18.
7669 * If the PC is in __call_stub_* or in __fn_stub_*, this is a call
7670 stub and the target PC is buried in the instruction stream.
7672 See the source code for the stubs in gcc/config/mips/mips16.S, or the
7673 stub builder in gcc/config/mips/mips.c (mips16_build_call_stub) for the
7677 mips_skip_mips16_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7679 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7680 CORE_ADDR start_addr
;
7684 /* Find the starting address and name of the function containing the PC. */
7685 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
7688 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7689 and the target PC is in $31 ($ra). */
7690 prefixlen
= strlen (mips_str_mips16_ret_stub
);
7691 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
7692 && mips_is_stub_mode (name
+ prefixlen
)
7693 && name
[prefixlen
+ 2] == '\0')
7694 return get_frame_register_signed
7695 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
7697 /* If the PC is in __mips16_call_stub_*, this is one of the call
7698 call/return stubs. */
7699 prefixlen
= strlen (mips_str_mips16_call_stub
);
7700 if (strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0)
7702 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7703 and the target PC is in $2. */
7704 if (mips_is_stub_suffix (name
+ prefixlen
, 0))
7705 return get_frame_register_signed
7706 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
7708 /* If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7709 i.e. before the JALR instruction, this is effectively a call stub
7710 and the target PC is in $2. Otherwise this is effectively
7711 a return stub and the target PC is in $18. */
7712 else if (mips_is_stub_mode (name
+ prefixlen
)
7713 && name
[prefixlen
+ 2] == '_'
7714 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 0))
7716 if (pc
== start_addr
)
7717 /* This is the 'call' part of a call stub. The return
7718 address is in $2. */
7719 return get_frame_register_signed
7720 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
7722 /* This is the 'return' part of a call stub. The return
7723 address is in $18. */
7724 return get_frame_register_signed
7725 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
7728 return 0; /* Not a stub. */
7731 /* If the PC is in __call_stub_* or __fn_stub*, this is one of the
7732 compiler-generated call or call/return stubs. */
7733 if (startswith (name
, mips_str_fn_stub
)
7734 || startswith (name
, mips_str_call_stub
))
7736 if (pc
== start_addr
)
7737 /* This is the 'call' part of a call stub. Call this helper
7738 to scan through this code for interesting instructions
7739 and determine the final PC. */
7740 return mips_get_mips16_fn_stub_pc (frame
, pc
);
7742 /* This is the 'return' part of a call stub. The return address
7744 return get_frame_register_signed
7745 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
7748 return 0; /* Not a stub. */
7751 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
7752 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
7755 mips_in_return_stub (struct gdbarch
*gdbarch
, CORE_ADDR pc
, const char *name
)
7757 CORE_ADDR start_addr
;
7760 /* Find the starting address of the function containing the PC. */
7761 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
7764 /* If the PC is in __mips16_call_stub_{s,d}{f,c}_{0..10} but not at
7765 the start, i.e. after the JALR instruction, this is effectively
7767 prefixlen
= strlen (mips_str_mips16_call_stub
);
7768 if (pc
!= start_addr
7769 && strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0
7770 && mips_is_stub_mode (name
+ prefixlen
)
7771 && name
[prefixlen
+ 2] == '_'
7772 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 1))
7775 /* If the PC is in __call_stub_fp_* but not at the start, i.e. after
7776 the JAL or JALR instruction, this is effectively a return stub. */
7777 prefixlen
= strlen (mips_str_call_fp_stub
);
7778 if (pc
!= start_addr
7779 && strncmp (name
, mips_str_call_fp_stub
, prefixlen
) == 0)
7782 /* Consume the .pic. prefix of any PIC stub, this function must return
7783 true when the PC is in a PIC stub of a __mips16_ret_{d,s}{f,c} stub
7784 or the call stub path will trigger in handle_inferior_event causing
7786 prefixlen
= strlen (mips_str_pic
);
7787 if (strncmp (name
, mips_str_pic
, prefixlen
) == 0)
7790 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub. */
7791 prefixlen
= strlen (mips_str_mips16_ret_stub
);
7792 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
7793 && mips_is_stub_mode (name
+ prefixlen
)
7794 && name
[prefixlen
+ 2] == '\0')
7797 return 0; /* Not a stub. */
7800 /* If the current PC is the start of a non-PIC-to-PIC stub, return the
7801 PC of the stub target. The stub just loads $t9 and jumps to it,
7802 so that $t9 has the correct value at function entry. */
7805 mips_skip_pic_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7807 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7808 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7809 struct bound_minimal_symbol msym
;
7811 gdb_byte stub_code
[16];
7812 int32_t stub_words
[4];
7814 /* The stub for foo is named ".pic.foo", and is either two
7815 instructions inserted before foo or a three instruction sequence
7816 which jumps to foo. */
7817 msym
= lookup_minimal_symbol_by_pc (pc
);
7818 if (msym
.minsym
== NULL
7819 || BMSYMBOL_VALUE_ADDRESS (msym
) != pc
7820 || msym
.minsym
->linkage_name () == NULL
7821 || !startswith (msym
.minsym
->linkage_name (), ".pic."))
7824 /* A two-instruction header. */
7825 if (MSYMBOL_SIZE (msym
.minsym
) == 8)
7828 /* A three-instruction (plus delay slot) trampoline. */
7829 if (MSYMBOL_SIZE (msym
.minsym
) == 16)
7831 if (target_read_memory (pc
, stub_code
, 16) != 0)
7833 for (i
= 0; i
< 4; i
++)
7834 stub_words
[i
] = extract_unsigned_integer (stub_code
+ i
* 4,
7837 /* A stub contains these instructions:
7840 addiu t9, t9, %lo(target)
7843 This works even for N64, since stubs are only generated with
7845 if ((stub_words
[0] & 0xffff0000U
) == 0x3c190000
7846 && (stub_words
[1] & 0xfc000000U
) == 0x08000000
7847 && (stub_words
[2] & 0xffff0000U
) == 0x27390000
7848 && stub_words
[3] == 0x00000000)
7849 return ((((stub_words
[0] & 0x0000ffff) << 16)
7850 + (stub_words
[2] & 0x0000ffff)) ^ 0x8000) - 0x8000;
7853 /* Not a recognized stub. */
7858 mips_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7860 CORE_ADDR requested_pc
= pc
;
7861 CORE_ADDR target_pc
;
7868 new_pc
= mips_skip_mips16_trampoline_code (frame
, pc
);
7872 new_pc
= find_solib_trampoline_target (frame
, pc
);
7876 new_pc
= mips_skip_pic_trampoline_code (frame
, pc
);
7880 while (pc
!= target_pc
);
7882 return pc
!= requested_pc
? pc
: 0;
7885 /* Convert a dbx stab register number (from `r' declaration) to a GDB
7886 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7889 mips_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
7892 if (num
>= 0 && num
< 32)
7894 else if (num
>= 38 && num
< 70)
7895 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 38;
7897 regnum
= mips_regnum (gdbarch
)->hi
;
7899 regnum
= mips_regnum (gdbarch
)->lo
;
7900 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 72 && num
< 78)
7901 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 72;
7904 return gdbarch_num_regs (gdbarch
) + regnum
;
7908 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
7909 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7912 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
7915 if (num
>= 0 && num
< 32)
7917 else if (num
>= 32 && num
< 64)
7918 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 32;
7920 regnum
= mips_regnum (gdbarch
)->hi
;
7922 regnum
= mips_regnum (gdbarch
)->lo
;
7923 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 66 && num
< 72)
7924 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 66;
7927 return gdbarch_num_regs (gdbarch
) + regnum
;
7931 mips_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
7933 /* Only makes sense to supply raw registers. */
7934 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
));
7935 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
7936 decide if it is valid. Should instead define a standard sim/gdb
7937 register numbering scheme. */
7938 if (gdbarch_register_name (gdbarch
,
7939 gdbarch_num_regs (gdbarch
) + regnum
) != NULL
7940 && gdbarch_register_name (gdbarch
,
7941 gdbarch_num_regs (gdbarch
)
7942 + regnum
)[0] != '\0')
7945 return LEGACY_SIM_REGNO_IGNORE
;
7949 /* Convert an integer into an address. Extracting the value signed
7950 guarantees a correctly sign extended address. */
7953 mips_integer_to_address (struct gdbarch
*gdbarch
,
7954 struct type
*type
, const gdb_byte
*buf
)
7956 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7957 return extract_signed_integer (buf
, TYPE_LENGTH (type
), byte_order
);
7960 /* Dummy virtual frame pointer method. This is no more or less accurate
7961 than most other architectures; we just need to be explicit about it,
7962 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
7963 an assertion failure. */
7966 mips_virtual_frame_pointer (struct gdbarch
*gdbarch
,
7967 CORE_ADDR pc
, int *reg
, LONGEST
*offset
)
7969 *reg
= MIPS_SP_REGNUM
;
7974 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
7976 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
7977 const char *name
= bfd_section_name (sect
);
7979 if (*abip
!= MIPS_ABI_UNKNOWN
)
7982 if (!startswith (name
, ".mdebug."))
7985 if (strcmp (name
, ".mdebug.abi32") == 0)
7986 *abip
= MIPS_ABI_O32
;
7987 else if (strcmp (name
, ".mdebug.abiN32") == 0)
7988 *abip
= MIPS_ABI_N32
;
7989 else if (strcmp (name
, ".mdebug.abi64") == 0)
7990 *abip
= MIPS_ABI_N64
;
7991 else if (strcmp (name
, ".mdebug.abiO64") == 0)
7992 *abip
= MIPS_ABI_O64
;
7993 else if (strcmp (name
, ".mdebug.eabi32") == 0)
7994 *abip
= MIPS_ABI_EABI32
;
7995 else if (strcmp (name
, ".mdebug.eabi64") == 0)
7996 *abip
= MIPS_ABI_EABI64
;
7998 warning (_("unsupported ABI %s."), name
+ 8);
8002 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
8004 int *lbp
= (int *) obj
;
8005 const char *name
= bfd_section_name (sect
);
8007 if (startswith (name
, ".gcc_compiled_long32"))
8009 else if (startswith (name
, ".gcc_compiled_long64"))
8011 else if (startswith (name
, ".gcc_compiled_long"))
8012 warning (_("unrecognized .gcc_compiled_longXX"));
8015 static enum mips_abi
8016 global_mips_abi (void)
8020 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
8021 if (mips_abi_strings
[i
] == mips_abi_string
)
8022 return (enum mips_abi
) i
;
8024 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
8027 /* Return the default compressed instruction set, either of MIPS16
8028 or microMIPS, selected when none could have been determined from
8029 the ELF header of the binary being executed (or no binary has been
8032 static enum mips_isa
8033 global_mips_compression (void)
8037 for (i
= 0; mips_compression_strings
[i
] != NULL
; i
++)
8038 if (mips_compression_strings
[i
] == mips_compression_string
)
8039 return (enum mips_isa
) i
;
8041 internal_error (__FILE__
, __LINE__
, _("unknown compressed ISA string"));
8045 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
8047 /* If the size matches the set of 32-bit or 64-bit integer registers,
8048 assume that's what we've got. */
8049 register_remote_g_packet_guess (gdbarch
, 38 * 4, mips_tdesc_gp32
);
8050 register_remote_g_packet_guess (gdbarch
, 38 * 8, mips_tdesc_gp64
);
8052 /* If the size matches the full set of registers GDB traditionally
8053 knows about, including floating point, for either 32-bit or
8054 64-bit, assume that's what we've got. */
8055 register_remote_g_packet_guess (gdbarch
, 90 * 4, mips_tdesc_gp32
);
8056 register_remote_g_packet_guess (gdbarch
, 90 * 8, mips_tdesc_gp64
);
8058 /* Otherwise we don't have a useful guess. */
8061 static struct value
*
8062 value_of_mips_user_reg (struct frame_info
*frame
, const void *baton
)
8064 const int *reg_p
= (const int *) baton
;
8065 return value_of_register (*reg_p
, frame
);
8068 static struct gdbarch
*
8069 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
8071 struct gdbarch
*gdbarch
;
8073 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
8075 enum mips_fpu_type fpu_type
;
8076 tdesc_arch_data_up tdesc_data
;
8077 int elf_fpu_type
= Val_GNU_MIPS_ABI_FP_ANY
;
8078 const char * const *reg_names
;
8079 struct mips_regnum mips_regnum
, *regnum
;
8080 enum mips_isa mips_isa
;
8084 /* First of all, extract the elf_flags, if available. */
8085 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
8086 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
8087 else if (arches
!= NULL
)
8089 mips_gdbarch_tdep
*tdep
8090 = (mips_gdbarch_tdep
*) gdbarch_tdep (arches
->gdbarch
);
8091 elf_flags
= tdep
->elf_flags
;
8096 fprintf_unfiltered (gdb_stdlog
,
8097 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
8099 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
8100 switch ((elf_flags
& EF_MIPS_ABI
))
8102 case E_MIPS_ABI_O32
:
8103 found_abi
= MIPS_ABI_O32
;
8105 case E_MIPS_ABI_O64
:
8106 found_abi
= MIPS_ABI_O64
;
8108 case E_MIPS_ABI_EABI32
:
8109 found_abi
= MIPS_ABI_EABI32
;
8111 case E_MIPS_ABI_EABI64
:
8112 found_abi
= MIPS_ABI_EABI64
;
8115 if ((elf_flags
& EF_MIPS_ABI2
))
8116 found_abi
= MIPS_ABI_N32
;
8118 found_abi
= MIPS_ABI_UNKNOWN
;
8122 /* GCC creates a pseudo-section whose name describes the ABI. */
8123 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
8124 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
8126 /* If we have no useful BFD information, use the ABI from the last
8127 MIPS architecture (if there is one). */
8128 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
8130 mips_gdbarch_tdep
*tdep
8131 = (mips_gdbarch_tdep
*) gdbarch_tdep (arches
->gdbarch
);
8132 found_abi
= tdep
->found_abi
;
8135 /* Try the architecture for any hint of the correct ABI. */
8136 if (found_abi
== MIPS_ABI_UNKNOWN
8137 && info
.bfd_arch_info
!= NULL
8138 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
8140 switch (info
.bfd_arch_info
->mach
)
8142 case bfd_mach_mips3900
:
8143 found_abi
= MIPS_ABI_EABI32
;
8145 case bfd_mach_mips4100
:
8146 case bfd_mach_mips5000
:
8147 found_abi
= MIPS_ABI_EABI64
;
8149 case bfd_mach_mips8000
:
8150 case bfd_mach_mips10000
:
8151 /* On Irix, ELF64 executables use the N64 ABI. The
8152 pseudo-sections which describe the ABI aren't present
8153 on IRIX. (Even for executables created by gcc.) */
8154 if (info
.abfd
!= NULL
8155 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
8156 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
8157 found_abi
= MIPS_ABI_N64
;
8159 found_abi
= MIPS_ABI_N32
;
8164 /* Default 64-bit objects to N64 instead of O32. */
8165 if (found_abi
== MIPS_ABI_UNKNOWN
8166 && info
.abfd
!= NULL
8167 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
8168 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
8169 found_abi
= MIPS_ABI_N64
;
8172 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
8175 /* What has the user specified from the command line? */
8176 wanted_abi
= global_mips_abi ();
8178 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
8181 /* Now that we have found what the ABI for this binary would be,
8182 check whether the user is overriding it. */
8183 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
8184 mips_abi
= wanted_abi
;
8185 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
8186 mips_abi
= found_abi
;
8188 mips_abi
= MIPS_ABI_O32
;
8190 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
8193 /* Make sure we don't use a 32-bit architecture with a 64-bit ABI. */
8194 if (mips_abi
!= MIPS_ABI_EABI32
8195 && mips_abi
!= MIPS_ABI_O32
8196 && info
.bfd_arch_info
!= NULL
8197 && info
.bfd_arch_info
->arch
== bfd_arch_mips
8198 && info
.bfd_arch_info
->bits_per_word
< 64)
8199 info
.bfd_arch_info
= bfd_lookup_arch (bfd_arch_mips
, bfd_mach_mips4000
);
8201 /* Determine the default compressed ISA. */
8202 if ((elf_flags
& EF_MIPS_ARCH_ASE_MICROMIPS
) != 0
8203 && (elf_flags
& EF_MIPS_ARCH_ASE_M16
) == 0)
8204 mips_isa
= ISA_MICROMIPS
;
8205 else if ((elf_flags
& EF_MIPS_ARCH_ASE_M16
) != 0
8206 && (elf_flags
& EF_MIPS_ARCH_ASE_MICROMIPS
) == 0)
8207 mips_isa
= ISA_MIPS16
;
8209 mips_isa
= global_mips_compression ();
8210 mips_compression_string
= mips_compression_strings
[mips_isa
];
8212 /* Also used when doing an architecture lookup. */
8214 fprintf_unfiltered (gdb_stdlog
,
8215 "mips_gdbarch_init: "
8216 "mips64_transfers_32bit_regs_p = %d\n",
8217 mips64_transfers_32bit_regs_p
);
8219 /* Determine the MIPS FPU type. */
8222 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
8223 elf_fpu_type
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
8224 Tag_GNU_MIPS_ABI_FP
);
8225 #endif /* HAVE_ELF */
8227 if (!mips_fpu_type_auto
)
8228 fpu_type
= mips_fpu_type
;
8229 else if (elf_fpu_type
!= Val_GNU_MIPS_ABI_FP_ANY
)
8231 switch (elf_fpu_type
)
8233 case Val_GNU_MIPS_ABI_FP_DOUBLE
:
8234 fpu_type
= MIPS_FPU_DOUBLE
;
8236 case Val_GNU_MIPS_ABI_FP_SINGLE
:
8237 fpu_type
= MIPS_FPU_SINGLE
;
8239 case Val_GNU_MIPS_ABI_FP_SOFT
:
8241 /* Soft float or unknown. */
8242 fpu_type
= MIPS_FPU_NONE
;
8246 else if (info
.bfd_arch_info
!= NULL
8247 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
8248 switch (info
.bfd_arch_info
->mach
)
8250 case bfd_mach_mips3900
:
8251 case bfd_mach_mips4100
:
8252 case bfd_mach_mips4111
:
8253 case bfd_mach_mips4120
:
8254 fpu_type
= MIPS_FPU_NONE
;
8256 case bfd_mach_mips4650
:
8257 fpu_type
= MIPS_FPU_SINGLE
;
8260 fpu_type
= MIPS_FPU_DOUBLE
;
8263 else if (arches
!= NULL
)
8264 fpu_type
= mips_get_fpu_type (arches
->gdbarch
);
8266 fpu_type
= MIPS_FPU_DOUBLE
;
8268 fprintf_unfiltered (gdb_stdlog
,
8269 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
8271 /* Check for blatant incompatibilities. */
8273 /* If we have only 32-bit registers, then we can't debug a 64-bit
8275 if (info
.target_desc
8276 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
8277 && mips_abi
!= MIPS_ABI_EABI32
8278 && mips_abi
!= MIPS_ABI_O32
)
8281 /* Fill in the OS dependent register numbers and names. */
8282 if (info
.osabi
== GDB_OSABI_LINUX
)
8284 mips_regnum
.fp0
= 38;
8285 mips_regnum
.pc
= 37;
8286 mips_regnum
.cause
= 36;
8287 mips_regnum
.badvaddr
= 35;
8288 mips_regnum
.hi
= 34;
8289 mips_regnum
.lo
= 33;
8290 mips_regnum
.fp_control_status
= 70;
8291 mips_regnum
.fp_implementation_revision
= 71;
8292 mips_regnum
.dspacc
= -1;
8293 mips_regnum
.dspctl
= -1;
8297 reg_names
= mips_linux_reg_names
;
8301 mips_regnum
.lo
= MIPS_EMBED_LO_REGNUM
;
8302 mips_regnum
.hi
= MIPS_EMBED_HI_REGNUM
;
8303 mips_regnum
.badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
8304 mips_regnum
.cause
= MIPS_EMBED_CAUSE_REGNUM
;
8305 mips_regnum
.pc
= MIPS_EMBED_PC_REGNUM
;
8306 mips_regnum
.fp0
= MIPS_EMBED_FP0_REGNUM
;
8307 mips_regnum
.fp_control_status
= 70;
8308 mips_regnum
.fp_implementation_revision
= 71;
8309 mips_regnum
.dspacc
= dspacc
= -1;
8310 mips_regnum
.dspctl
= dspctl
= -1;
8311 num_regs
= MIPS_LAST_EMBED_REGNUM
+ 1;
8312 if (info
.bfd_arch_info
!= NULL
8313 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
8314 reg_names
= mips_tx39_reg_names
;
8316 reg_names
= mips_generic_reg_names
;
8319 /* Check any target description for validity. */
8320 if (tdesc_has_registers (info
.target_desc
))
8322 static const char *const mips_gprs
[] = {
8323 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
8324 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
8325 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
8326 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
8328 static const char *const mips_fprs
[] = {
8329 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
8330 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
8331 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
8332 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
8335 const struct tdesc_feature
*feature
;
8338 feature
= tdesc_find_feature (info
.target_desc
,
8339 "org.gnu.gdb.mips.cpu");
8340 if (feature
== NULL
)
8343 tdesc_data
= tdesc_data_alloc ();
8346 for (i
= MIPS_ZERO_REGNUM
; i
<= MIPS_RA_REGNUM
; i
++)
8347 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (), i
,
8351 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8352 mips_regnum
.lo
, "lo");
8353 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8354 mips_regnum
.hi
, "hi");
8355 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8356 mips_regnum
.pc
, "pc");
8361 feature
= tdesc_find_feature (info
.target_desc
,
8362 "org.gnu.gdb.mips.cp0");
8363 if (feature
== NULL
)
8367 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8368 mips_regnum
.badvaddr
, "badvaddr");
8369 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8370 MIPS_PS_REGNUM
, "status");
8371 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8372 mips_regnum
.cause
, "cause");
8377 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
8378 backend is not prepared for that, though. */
8379 feature
= tdesc_find_feature (info
.target_desc
,
8380 "org.gnu.gdb.mips.fpu");
8381 if (feature
== NULL
)
8385 for (i
= 0; i
< 32; i
++)
8386 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8387 i
+ mips_regnum
.fp0
, mips_fprs
[i
]);
8389 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8390 mips_regnum
.fp_control_status
,
8393 &= tdesc_numbered_register (feature
, tdesc_data
.get (),
8394 mips_regnum
.fp_implementation_revision
,
8400 num_regs
= mips_regnum
.fp_implementation_revision
+ 1;
8404 feature
= tdesc_find_feature (info
.target_desc
,
8405 "org.gnu.gdb.mips.dsp");
8406 /* The DSP registers are optional; it's OK if they are absent. */
8407 if (feature
!= NULL
)
8411 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8412 dspacc
+ i
++, "hi1");
8413 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8414 dspacc
+ i
++, "lo1");
8415 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8416 dspacc
+ i
++, "hi2");
8417 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8418 dspacc
+ i
++, "lo2");
8419 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8420 dspacc
+ i
++, "hi3");
8421 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8422 dspacc
+ i
++, "lo3");
8424 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8430 mips_regnum
.dspacc
= dspacc
;
8431 mips_regnum
.dspctl
= dspctl
;
8433 num_regs
= mips_regnum
.dspctl
+ 1;
8437 /* It would be nice to detect an attempt to use a 64-bit ABI
8438 when only 32-bit registers are provided. */
8442 /* Try to find a pre-existing architecture. */
8443 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
8445 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
8447 mips_gdbarch_tdep
*tdep
8448 = (mips_gdbarch_tdep
*) gdbarch_tdep (arches
->gdbarch
);
8450 /* MIPS needs to be pedantic about which ABI and the compressed
8451 ISA variation the object is using. */
8452 if (tdep
->elf_flags
!= elf_flags
)
8454 if (tdep
->mips_abi
!= mips_abi
)
8456 if (tdep
->mips_isa
!= mips_isa
)
8458 /* Need to be pedantic about which register virtual size is
8460 if (tdep
->mips64_transfers_32bit_regs_p
8461 != mips64_transfers_32bit_regs_p
)
8463 /* Be pedantic about which FPU is selected. */
8464 if (mips_get_fpu_type (arches
->gdbarch
) != fpu_type
)
8467 return arches
->gdbarch
;
8470 /* Need a new architecture. Fill in a target specific vector. */
8471 mips_gdbarch_tdep
*tdep
= new mips_gdbarch_tdep
;
8472 gdbarch
= gdbarch_alloc (&info
, tdep
);
8473 tdep
->elf_flags
= elf_flags
;
8474 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
8475 tdep
->found_abi
= found_abi
;
8476 tdep
->mips_abi
= mips_abi
;
8477 tdep
->mips_isa
= mips_isa
;
8478 tdep
->mips_fpu_type
= fpu_type
;
8479 tdep
->register_size_valid_p
= 0;
8480 tdep
->register_size
= 0;
8482 if (info
.target_desc
)
8484 /* Some useful properties can be inferred from the target. */
8485 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
8487 tdep
->register_size_valid_p
= 1;
8488 tdep
->register_size
= 4;
8490 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
8492 tdep
->register_size_valid_p
= 1;
8493 tdep
->register_size
= 8;
8497 /* Initially set everything according to the default ABI/ISA. */
8498 set_gdbarch_short_bit (gdbarch
, 16);
8499 set_gdbarch_int_bit (gdbarch
, 32);
8500 set_gdbarch_float_bit (gdbarch
, 32);
8501 set_gdbarch_double_bit (gdbarch
, 64);
8502 set_gdbarch_long_double_bit (gdbarch
, 64);
8503 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
8504 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
8505 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
8507 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
8508 mips_ax_pseudo_register_collect
);
8509 set_gdbarch_ax_pseudo_register_push_stack
8510 (gdbarch
, mips_ax_pseudo_register_push_stack
);
8512 set_gdbarch_elf_make_msymbol_special (gdbarch
,
8513 mips_elf_make_msymbol_special
);
8514 set_gdbarch_make_symbol_special (gdbarch
, mips_make_symbol_special
);
8515 set_gdbarch_adjust_dwarf2_addr (gdbarch
, mips_adjust_dwarf2_addr
);
8516 set_gdbarch_adjust_dwarf2_line (gdbarch
, mips_adjust_dwarf2_line
);
8518 regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
, struct mips_regnum
);
8519 *regnum
= mips_regnum
;
8520 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
8521 set_gdbarch_num_regs (gdbarch
, num_regs
);
8522 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
8523 set_gdbarch_register_name (gdbarch
, mips_register_name
);
8524 set_gdbarch_virtual_frame_pointer (gdbarch
, mips_virtual_frame_pointer
);
8525 tdep
->mips_processor_reg_names
= reg_names
;
8526 tdep
->regnum
= regnum
;
8531 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
8532 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
8533 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
8534 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
8535 tdep
->default_mask_address_p
= 0;
8536 set_gdbarch_long_bit (gdbarch
, 32);
8537 set_gdbarch_ptr_bit (gdbarch
, 32);
8538 set_gdbarch_long_long_bit (gdbarch
, 64);
8541 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
8542 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
8543 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
8544 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
8545 tdep
->default_mask_address_p
= 0;
8546 set_gdbarch_long_bit (gdbarch
, 32);
8547 set_gdbarch_ptr_bit (gdbarch
, 32);
8548 set_gdbarch_long_long_bit (gdbarch
, 64);
8550 case MIPS_ABI_EABI32
:
8551 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
8552 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
8553 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8554 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8555 tdep
->default_mask_address_p
= 0;
8556 set_gdbarch_long_bit (gdbarch
, 32);
8557 set_gdbarch_ptr_bit (gdbarch
, 32);
8558 set_gdbarch_long_long_bit (gdbarch
, 64);
8560 case MIPS_ABI_EABI64
:
8561 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
8562 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
8563 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8564 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8565 tdep
->default_mask_address_p
= 0;
8566 set_gdbarch_long_bit (gdbarch
, 64);
8567 set_gdbarch_ptr_bit (gdbarch
, 64);
8568 set_gdbarch_long_long_bit (gdbarch
, 64);
8571 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
8572 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
8573 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8574 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8575 tdep
->default_mask_address_p
= 0;
8576 set_gdbarch_long_bit (gdbarch
, 32);
8577 set_gdbarch_ptr_bit (gdbarch
, 32);
8578 set_gdbarch_long_long_bit (gdbarch
, 64);
8579 set_gdbarch_long_double_bit (gdbarch
, 128);
8580 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
8583 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
8584 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
8585 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8586 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8587 tdep
->default_mask_address_p
= 0;
8588 set_gdbarch_long_bit (gdbarch
, 64);
8589 set_gdbarch_ptr_bit (gdbarch
, 64);
8590 set_gdbarch_long_long_bit (gdbarch
, 64);
8591 set_gdbarch_long_double_bit (gdbarch
, 128);
8592 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
8595 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
8598 /* GCC creates a pseudo-section whose name specifies the size of
8599 longs, since -mlong32 or -mlong64 may be used independent of
8600 other options. How those options affect pointer sizes is ABI and
8601 architecture dependent, so use them to override the default sizes
8602 set by the ABI. This table shows the relationship between ABI,
8603 -mlongXX, and size of pointers:
8605 ABI -mlongXX ptr bits
8606 --- -------- --------
8620 Note that for o32 and eabi32, pointers are always 32 bits
8621 regardless of any -mlongXX option. For all others, pointers and
8622 longs are the same, as set by -mlongXX or set by defaults. */
8624 if (info
.abfd
!= NULL
)
8628 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
8631 set_gdbarch_long_bit (gdbarch
, long_bit
);
8635 case MIPS_ABI_EABI32
:
8640 case MIPS_ABI_EABI64
:
8641 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
8644 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
8649 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
8650 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
8653 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
8654 flag in object files because to do so would make it impossible to
8655 link with libraries compiled without "-gp32". This is
8656 unnecessarily restrictive.
8658 We could solve this problem by adding "-gp32" multilibs to gcc,
8659 but to set this flag before gcc is built with such multilibs will
8660 break too many systems.''
8662 But even more unhelpfully, the default linker output target for
8663 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
8664 for 64-bit programs - you need to change the ABI to change this,
8665 and not all gcc targets support that currently. Therefore using
8666 this flag to detect 32-bit mode would do the wrong thing given
8667 the current gcc - it would make GDB treat these 64-bit programs
8668 as 32-bit programs by default. */
8670 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
8671 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
8673 /* Add/remove bits from an address. The MIPS needs be careful to
8674 ensure that all 32 bit addresses are sign extended to 64 bits. */
8675 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
8677 /* Unwind the frame. */
8678 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
8679 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
8680 set_gdbarch_dummy_id (gdbarch
, mips_dummy_id
);
8682 /* Map debug register numbers onto internal register numbers. */
8683 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
8684 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
8685 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
8686 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
8687 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
8688 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
8690 /* MIPS version of CALL_DUMMY. */
8692 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
8693 set_gdbarch_push_dummy_code (gdbarch
, mips_push_dummy_code
);
8694 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
8696 set_gdbarch_print_float_info (gdbarch
, mips_print_float_info
);
8698 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
8699 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
8700 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
8702 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
8703 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, mips_breakpoint_kind_from_pc
);
8704 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, mips_sw_breakpoint_from_kind
);
8705 set_gdbarch_adjust_breakpoint_address (gdbarch
,
8706 mips_adjust_breakpoint_address
);
8708 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
8710 set_gdbarch_stack_frame_destroyed_p (gdbarch
, mips_stack_frame_destroyed_p
);
8712 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
8713 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
8714 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
8716 set_gdbarch_register_type (gdbarch
, mips_register_type
);
8718 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
8720 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
8721 if (mips_abi
== MIPS_ABI_N64
)
8722 set_gdbarch_disassembler_options_implicit
8723 (gdbarch
, (const char *) mips_disassembler_options_n64
);
8724 else if (mips_abi
== MIPS_ABI_N32
)
8725 set_gdbarch_disassembler_options_implicit
8726 (gdbarch
, (const char *) mips_disassembler_options_n32
);
8728 set_gdbarch_disassembler_options_implicit
8729 (gdbarch
, (const char *) mips_disassembler_options_o32
);
8730 set_gdbarch_disassembler_options (gdbarch
, &mips_disassembler_options
);
8731 set_gdbarch_valid_disassembler_options (gdbarch
,
8732 disassembler_options_mips ());
8734 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint,
8735 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint
8736 need to all be folded into the target vector. Since they are
8737 being used as guards for target_stopped_by_watchpoint, why not have
8738 target_stopped_by_watchpoint return the type of watchpoint that the code
8740 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
8742 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
8744 /* NOTE drow/2012-04-25: We overload the core solib trampoline code
8745 to support MIPS16. This is a bad thing. Make sure not to do it
8746 if we have an OS ABI that actually supports shared libraries, since
8747 shared library support is more important. If we have an OS someday
8748 that supports both shared libraries and MIPS16, we'll have to find
8749 a better place for these.
8750 macro/2012-04-25: But that applies to return trampolines only and
8751 currently no MIPS OS ABI uses shared libraries that have them. */
8752 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
8754 set_gdbarch_single_step_through_delay (gdbarch
,
8755 mips_single_step_through_delay
);
8757 /* Virtual tables. */
8758 set_gdbarch_vbit_in_delta (gdbarch
, 1);
8760 mips_register_g_packet_guesses (gdbarch
);
8762 /* Hook in OS ABI-specific overrides, if they have been registered. */
8763 info
.tdesc_data
= tdesc_data
.get ();
8764 gdbarch_init_osabi (info
, gdbarch
);
8766 /* The hook may have adjusted num_regs, fetch the final value and
8767 set pc_regnum and sp_regnum now that it has been fixed. */
8768 num_regs
= gdbarch_num_regs (gdbarch
);
8769 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
8770 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
8772 /* Unwind the frame. */
8773 dwarf2_append_unwinders (gdbarch
);
8774 frame_unwind_append_unwinder (gdbarch
, &mips_stub_frame_unwind
);
8775 frame_unwind_append_unwinder (gdbarch
, &mips_insn16_frame_unwind
);
8776 frame_unwind_append_unwinder (gdbarch
, &mips_micro_frame_unwind
);
8777 frame_unwind_append_unwinder (gdbarch
, &mips_insn32_frame_unwind
);
8778 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
8779 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
8780 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
8781 frame_base_append_sniffer (gdbarch
, mips_micro_frame_base_sniffer
);
8782 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
8784 if (tdesc_data
!= nullptr)
8786 set_tdesc_pseudo_register_type (gdbarch
, mips_pseudo_register_type
);
8787 tdesc_use_registers (gdbarch
, info
.target_desc
, std::move (tdesc_data
));
8789 /* Override the normal target description methods to handle our
8790 dual real and pseudo registers. */
8791 set_gdbarch_register_name (gdbarch
, mips_register_name
);
8792 set_gdbarch_register_reggroup_p (gdbarch
,
8793 mips_tdesc_register_reggroup_p
);
8795 num_regs
= gdbarch_num_regs (gdbarch
);
8796 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
8797 set_gdbarch_pc_regnum (gdbarch
, tdep
->regnum
->pc
+ num_regs
);
8798 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
8801 /* Add ABI-specific aliases for the registers. */
8802 if (mips_abi
== MIPS_ABI_N32
|| mips_abi
== MIPS_ABI_N64
)
8803 for (i
= 0; i
< ARRAY_SIZE (mips_n32_n64_aliases
); i
++)
8804 user_reg_add (gdbarch
, mips_n32_n64_aliases
[i
].name
,
8805 value_of_mips_user_reg
, &mips_n32_n64_aliases
[i
].regnum
);
8807 for (i
= 0; i
< ARRAY_SIZE (mips_o32_aliases
); i
++)
8808 user_reg_add (gdbarch
, mips_o32_aliases
[i
].name
,
8809 value_of_mips_user_reg
, &mips_o32_aliases
[i
].regnum
);
8811 /* Add some other standard aliases. */
8812 for (i
= 0; i
< ARRAY_SIZE (mips_register_aliases
); i
++)
8813 user_reg_add (gdbarch
, mips_register_aliases
[i
].name
,
8814 value_of_mips_user_reg
, &mips_register_aliases
[i
].regnum
);
8816 for (i
= 0; i
< ARRAY_SIZE (mips_numeric_register_aliases
); i
++)
8817 user_reg_add (gdbarch
, mips_numeric_register_aliases
[i
].name
,
8818 value_of_mips_user_reg
,
8819 &mips_numeric_register_aliases
[i
].regnum
);
8825 mips_abi_update (const char *ignore_args
,
8826 int from_tty
, struct cmd_list_element
*c
)
8828 struct gdbarch_info info
;
8830 /* Force the architecture to update, and (if it's a MIPS architecture)
8831 mips_gdbarch_init will take care of the rest. */
8832 gdbarch_update_p (info
);
8835 /* Print out which MIPS ABI is in use. */
8838 show_mips_abi (struct ui_file
*file
,
8840 struct cmd_list_element
*ignored_cmd
,
8841 const char *ignored_value
)
8843 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_mips
)
8846 "The MIPS ABI is unknown because the current architecture "
8850 enum mips_abi global_abi
= global_mips_abi ();
8851 enum mips_abi actual_abi
= mips_abi (target_gdbarch ());
8852 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
8854 if (global_abi
== MIPS_ABI_UNKNOWN
)
8857 "The MIPS ABI is set automatically (currently \"%s\").\n",
8859 else if (global_abi
== actual_abi
)
8862 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
8866 /* Probably shouldn't happen... */
8867 fprintf_filtered (file
,
8868 "The (auto detected) MIPS ABI \"%s\" is in use "
8869 "even though the user setting was \"%s\".\n",
8870 actual_abi_str
, mips_abi_strings
[global_abi
]);
8875 /* Print out which MIPS compressed ISA encoding is used. */
8878 show_mips_compression (struct ui_file
*file
, int from_tty
,
8879 struct cmd_list_element
*c
, const char *value
)
8881 fprintf_filtered (file
, _("The compressed ISA encoding used is %s.\n"),
8885 /* Return a textual name for MIPS FPU type FPU_TYPE. */
8888 mips_fpu_type_str (enum mips_fpu_type fpu_type
)
8894 case MIPS_FPU_SINGLE
:
8896 case MIPS_FPU_DOUBLE
:
8904 mips_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
8906 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
8910 int ef_mips_32bitmode
;
8911 /* Determine the ISA. */
8912 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
8930 /* Determine the size of a pointer. */
8931 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
8932 fprintf_filtered (file
,
8933 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
8935 fprintf_filtered (file
,
8936 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
8938 fprintf_filtered (file
,
8939 "mips_dump_tdep: ef_mips_arch = %d\n",
8941 fprintf_filtered (file
,
8942 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
8943 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
8944 fprintf_filtered (file
,
8946 "mips_mask_address_p() %d (default %d)\n",
8947 mips_mask_address_p (tdep
),
8948 tdep
->default_mask_address_p
);
8950 fprintf_filtered (file
,
8951 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
8952 MIPS_DEFAULT_FPU_TYPE
,
8953 mips_fpu_type_str (MIPS_DEFAULT_FPU_TYPE
));
8954 fprintf_filtered (file
, "mips_dump_tdep: MIPS_EABI = %d\n",
8955 mips_eabi (gdbarch
));
8956 fprintf_filtered (file
,
8957 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
8958 mips_get_fpu_type (gdbarch
),
8959 mips_fpu_type_str (mips_get_fpu_type (gdbarch
)));
8962 void _initialize_mips_tdep ();
8964 _initialize_mips_tdep ()
8966 static struct cmd_list_element
*mipsfpulist
= NULL
;
8968 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
8969 if (MIPS_ABI_LAST
+ 1
8970 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
8971 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
8973 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
8975 /* Create feature sets with the appropriate properties. The values
8976 are not important. */
8977 mips_tdesc_gp32
= allocate_target_description ().release ();
8978 set_tdesc_property (mips_tdesc_gp32
, PROPERTY_GP32
, "");
8980 mips_tdesc_gp64
= allocate_target_description ().release ();
8981 set_tdesc_property (mips_tdesc_gp64
, PROPERTY_GP64
, "");
8983 /* Add root prefix command for all "set mips"/"show mips" commands. */
8984 add_setshow_prefix_cmd ("mips", no_class
,
8985 _("Various MIPS specific commands."),
8986 _("Various MIPS specific commands."),
8987 &setmipscmdlist
, &showmipscmdlist
,
8988 &setlist
, &showlist
);
8990 /* Allow the user to override the ABI. */
8991 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
8992 &mips_abi_string
, _("\
8993 Set the MIPS ABI used by this program."), _("\
8994 Show the MIPS ABI used by this program."), _("\
8995 This option can be set to one of:\n\
8996 auto - the default ABI associated with the current binary\n\
9005 &setmipscmdlist
, &showmipscmdlist
);
9007 /* Allow the user to set the ISA to assume for compressed code if ELF
9008 file flags don't tell or there is no program file selected. This
9009 setting is updated whenever unambiguous ELF file flags are interpreted,
9010 and carried over to subsequent sessions. */
9011 add_setshow_enum_cmd ("compression", class_obscure
, mips_compression_strings
,
9012 &mips_compression_string
, _("\
9013 Set the compressed ISA encoding used by MIPS code."), _("\
9014 Show the compressed ISA encoding used by MIPS code."), _("\
9015 Select the compressed ISA encoding used in functions that have no symbol\n\
9016 information available. The encoding can be set to either of:\n\
9019 and is updated automatically from ELF file flags if available."),
9021 show_mips_compression
,
9022 &setmipscmdlist
, &showmipscmdlist
);
9024 /* Let the user turn off floating point and set the fence post for
9025 heuristic_proc_start. */
9027 add_basic_prefix_cmd ("mipsfpu", class_support
,
9028 _("Set use of MIPS floating-point coprocessor."),
9029 &mipsfpulist
, 0, &setlist
);
9030 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
9031 _("Select single-precision MIPS floating-point coprocessor."),
9033 cmd_list_element
*set_mipsfpu_double_cmd
9034 = add_cmd ("double", class_support
, set_mipsfpu_double_command
,
9035 _("Select double-precision MIPS floating-point coprocessor."),
9037 add_alias_cmd ("on", set_mipsfpu_double_cmd
, class_support
, 1, &mipsfpulist
);
9038 add_alias_cmd ("yes", set_mipsfpu_double_cmd
, class_support
, 1, &mipsfpulist
);
9039 add_alias_cmd ("1", set_mipsfpu_double_cmd
, class_support
, 1, &mipsfpulist
);
9041 cmd_list_element
*set_mipsfpu_none_cmd
9042 = add_cmd ("none", class_support
, set_mipsfpu_none_command
,
9043 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
9044 add_alias_cmd ("off", set_mipsfpu_none_cmd
, class_support
, 1, &mipsfpulist
);
9045 add_alias_cmd ("no", set_mipsfpu_none_cmd
, class_support
, 1, &mipsfpulist
);
9046 add_alias_cmd ("0", set_mipsfpu_none_cmd
, class_support
, 1, &mipsfpulist
);
9047 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
9048 _("Select MIPS floating-point coprocessor automatically."),
9050 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
9051 _("Show current use of MIPS floating-point coprocessor target."),
9054 /* We really would like to have both "0" and "unlimited" work, but
9055 command.c doesn't deal with that. So make it a var_zinteger
9056 because the user can always use "999999" or some such for unlimited. */
9057 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
9058 &heuristic_fence_post
, _("\
9059 Set the distance searched for the start of a function."), _("\
9060 Show the distance searched for the start of a function."), _("\
9061 If you are debugging a stripped executable, GDB needs to search through the\n\
9062 program for the start of a function. This command sets the distance of the\n\
9063 search. The only need to set it is when debugging a stripped executable."),
9064 reinit_frame_cache_sfunc
,
9065 NULL
, /* FIXME: i18n: The distance searched for
9066 the start of a function is %s. */
9067 &setlist
, &showlist
);
9069 /* Allow the user to control whether the upper bits of 64-bit
9070 addresses should be zeroed. */
9071 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
9072 &mask_address_var
, _("\
9073 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
9074 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
9075 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\
9076 allow GDB to determine the correct value."),
9077 NULL
, show_mask_address
,
9078 &setmipscmdlist
, &showmipscmdlist
);
9080 /* Allow the user to control the size of 32 bit registers within the
9081 raw remote packet. */
9082 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
9083 &mips64_transfers_32bit_regs_p
, _("\
9084 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
9086 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
9088 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
9089 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
9090 64 bits for others. Use \"off\" to disable compatibility mode"),
9091 set_mips64_transfers_32bit_regs
,
9092 NULL
, /* FIXME: i18n: Compatibility with 64-bit
9093 MIPS target that transfers 32-bit
9094 quantities is %s. */
9095 &setlist
, &showlist
);
9097 /* Debug this files internals. */
9098 add_setshow_zuinteger_cmd ("mips", class_maintenance
,
9100 Set mips debugging."), _("\
9101 Show mips debugging."), _("\
9102 When non-zero, mips specific debugging is enabled."),
9104 NULL
, /* FIXME: i18n: Mips debugging is
9106 &setdebuglist
, &showdebuglist
);