1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988-2022 Free Software Foundation, Inc.
5 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
6 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
35 #include "arch-utils.h"
38 #include "mips-tdep.h"
40 #include "reggroups.h"
41 #include "opcode/mips.h"
45 #include "sim-regno.h"
48 #include "frame-unwind.h"
49 #include "frame-base.h"
50 #include "trad-frame.h"
53 #include "target-descriptions.h"
54 #include "dwarf2/frame.h"
55 #include "user-regs.h"
58 #include "target-float.h"
61 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
63 static int mips32_instruction_has_delay_slot (struct gdbarch
*gdbarch
,
65 static int micromips_instruction_has_delay_slot (ULONGEST insn
, int mustbe32
);
66 static int mips16_instruction_has_delay_slot (unsigned short inst
,
69 static int mips32_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
71 static int micromips_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
72 CORE_ADDR addr
, int mustbe32
);
73 static int mips16_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
74 CORE_ADDR addr
, int mustbe32
);
76 static void mips_print_float_info (struct gdbarch
*, struct ui_file
*,
77 struct frame_info
*, const char *);
79 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
80 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
81 #define ST0_FR (1 << 26)
83 /* The sizes of floating point registers. */
87 MIPS_FPU_SINGLE_REGSIZE
= 4,
88 MIPS_FPU_DOUBLE_REGSIZE
= 8
97 static const char *mips_abi_string
;
99 static const char *const mips_abi_strings
[] = {
110 /* Enum describing the different kinds of breakpoints. */
112 enum mips_breakpoint_kind
114 /* 16-bit MIPS16 mode breakpoint. */
115 MIPS_BP_KIND_MIPS16
= 2,
117 /* 16-bit microMIPS mode breakpoint. */
118 MIPS_BP_KIND_MICROMIPS16
= 3,
120 /* 32-bit standard MIPS mode breakpoint. */
121 MIPS_BP_KIND_MIPS32
= 4,
123 /* 32-bit microMIPS mode breakpoint. */
124 MIPS_BP_KIND_MICROMIPS32
= 5,
127 /* For backwards compatibility we default to MIPS16. This flag is
128 overridden as soon as unambiguous ELF file flags tell us the
129 compressed ISA encoding used. */
130 static const char mips_compression_mips16
[] = "mips16";
131 static const char mips_compression_micromips
[] = "micromips";
132 static const char *const mips_compression_strings
[] =
134 mips_compression_mips16
,
135 mips_compression_micromips
,
139 static const char *mips_compression_string
= mips_compression_mips16
;
141 /* The standard register names, and all the valid aliases for them. */
142 struct register_alias
148 /* Aliases for o32 and most other ABIs. */
149 const struct register_alias mips_o32_aliases
[] = {
156 /* Aliases for n32 and n64. */
157 const struct register_alias mips_n32_n64_aliases
[] = {
164 /* Aliases for ABI-independent registers. */
165 const struct register_alias mips_register_aliases
[] = {
166 /* The architecture manuals specify these ABI-independent names for
168 #define R(n) { "r" #n, n }
169 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
170 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
171 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
172 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
175 /* k0 and k1 are sometimes called these instead (for "kernel
180 /* This is the traditional GDB name for the CP0 status register. */
181 { "sr", MIPS_PS_REGNUM
},
183 /* This is the traditional GDB name for the CP0 BadVAddr register. */
184 { "bad", MIPS_EMBED_BADVADDR_REGNUM
},
186 /* This is the traditional GDB name for the FCSR. */
187 { "fsr", MIPS_EMBED_FP0_REGNUM
+ 32 }
190 const struct register_alias mips_numeric_register_aliases
[] = {
191 #define R(n) { #n, n }
192 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
193 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
194 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
195 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
199 #ifndef MIPS_DEFAULT_FPU_TYPE
200 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
202 static int mips_fpu_type_auto
= 1;
203 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
205 static unsigned int mips_debug
= 0;
207 /* Properties (for struct target_desc) describing the g/G packet
209 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
210 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
212 struct target_desc
*mips_tdesc_gp32
;
213 struct target_desc
*mips_tdesc_gp64
;
215 /* The current set of options to be passed to the disassembler. */
216 static char *mips_disassembler_options
;
218 /* Implicit disassembler options for individual ABIs. These tell
219 libopcodes to use general-purpose register names corresponding
220 to the ABI we have selected, perhaps via a `set mips abi ...'
221 override, rather than ones inferred from the ABI set in the ELF
222 headers of the binary file selected for debugging. */
223 static const char mips_disassembler_options_o32
[] = "gpr-names=32";
224 static const char mips_disassembler_options_n32
[] = "gpr-names=n32";
225 static const char mips_disassembler_options_n64
[] = "gpr-names=64";
227 const struct mips_regnum
*
228 mips_regnum (struct gdbarch
*gdbarch
)
230 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
235 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
237 return mips_regnum (gdbarch
)->fp0
+ 12;
240 /* Return 1 if REGNUM refers to a floating-point general register, raw
241 or cooked. Otherwise return 0. */
244 mips_float_register_p (struct gdbarch
*gdbarch
, int regnum
)
246 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
248 return (rawnum
>= mips_regnum (gdbarch
)->fp0
249 && rawnum
< mips_regnum (gdbarch
)->fp0
+ 32);
253 mips_eabi (gdbarch
*arch
)
255 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (arch
);
256 return (tdep
->mips_abi
== MIPS_ABI_EABI32 \
257 || tdep
->mips_abi
== MIPS_ABI_EABI64
);
261 mips_last_fp_arg_regnum (gdbarch
*arch
)
263 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (arch
);
264 return tdep
->mips_last_fp_arg_regnum
;
268 mips_last_arg_regnum (gdbarch
*arch
)
270 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (arch
);
271 return tdep
->mips_last_arg_regnum
;
274 static enum mips_fpu_type
275 mips_get_fpu_type (gdbarch
*arch
)
277 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (arch
);
278 return tdep
->mips_fpu_type
;
281 /* Return the MIPS ABI associated with GDBARCH. */
283 mips_abi (struct gdbarch
*gdbarch
)
285 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
286 return tdep
->mips_abi
;
290 mips_isa_regsize (struct gdbarch
*gdbarch
)
292 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
294 /* If we know how big the registers are, use that size. */
295 if (tdep
->register_size_valid_p
)
296 return tdep
->register_size
;
298 /* Fall back to the previous behavior. */
299 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
300 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
303 /* Max saved register size. */
304 #define MAX_MIPS_ABI_REGSIZE 8
306 /* Return the currently configured (or set) saved register size. */
309 mips_abi_regsize (struct gdbarch
*gdbarch
)
311 switch (mips_abi (gdbarch
))
313 case MIPS_ABI_EABI32
:
319 case MIPS_ABI_EABI64
:
321 case MIPS_ABI_UNKNOWN
:
324 internal_error (__FILE__
, __LINE__
, _("bad switch"));
328 /* MIPS16/microMIPS function addresses are odd (bit 0 is set). Here
329 are some functions to handle addresses associated with compressed
330 code including but not limited to testing, setting, or clearing
331 bit 0 of such addresses. */
333 /* Return one iff compressed code is the MIPS16 instruction set. */
336 is_mips16_isa (struct gdbarch
*gdbarch
)
338 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
339 return tdep
->mips_isa
== ISA_MIPS16
;
342 /* Return one iff compressed code is the microMIPS instruction set. */
345 is_micromips_isa (struct gdbarch
*gdbarch
)
347 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
348 return tdep
->mips_isa
== ISA_MICROMIPS
;
351 /* Return one iff ADDR denotes compressed code. */
354 is_compact_addr (CORE_ADDR addr
)
359 /* Return one iff ADDR denotes standard ISA code. */
362 is_mips_addr (CORE_ADDR addr
)
364 return !is_compact_addr (addr
);
367 /* Return one iff ADDR denotes MIPS16 code. */
370 is_mips16_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
372 return is_compact_addr (addr
) && is_mips16_isa (gdbarch
);
375 /* Return one iff ADDR denotes microMIPS code. */
378 is_micromips_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
380 return is_compact_addr (addr
) && is_micromips_isa (gdbarch
);
383 /* Strip the ISA (compression) bit off from ADDR. */
386 unmake_compact_addr (CORE_ADDR addr
)
388 return ((addr
) & ~(CORE_ADDR
) 1);
391 /* Add the ISA (compression) bit to ADDR. */
394 make_compact_addr (CORE_ADDR addr
)
396 return ((addr
) | (CORE_ADDR
) 1);
399 /* Extern version of unmake_compact_addr; we use a separate function
400 so that unmake_compact_addr can be inlined throughout this file. */
403 mips_unmake_compact_addr (CORE_ADDR addr
)
405 return unmake_compact_addr (addr
);
408 /* Functions for setting and testing a bit in a minimal symbol that
409 marks it as MIPS16 or microMIPS function. The MSB of the minimal
410 symbol's "info" field is used for this purpose.
412 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is
413 "special", i.e. refers to a MIPS16 or microMIPS function, and sets
414 one of the "special" bits in a minimal symbol to mark it accordingly.
415 The test checks an ELF-private flag that is valid for true function
416 symbols only; for synthetic symbols such as for PLT stubs that have
417 no ELF-private part at all the MIPS BFD backend arranges for this
418 information to be carried in the asymbol's udata field instead.
420 msymbol_is_mips16 and msymbol_is_micromips test the "special" bit
421 in a minimal symbol. */
424 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
426 elf_symbol_type
*elfsym
= (elf_symbol_type
*) sym
;
427 unsigned char st_other
;
429 if ((sym
->flags
& BSF_SYNTHETIC
) == 0)
430 st_other
= elfsym
->internal_elf_sym
.st_other
;
431 else if ((sym
->flags
& BSF_FUNCTION
) != 0)
432 st_other
= sym
->udata
.i
;
436 if (ELF_ST_IS_MICROMIPS (st_other
))
438 SET_MSYMBOL_TARGET_FLAG_MICROMIPS (msym
);
439 msym
->set_value_address (msym
->value_raw_address () | 1);
441 else if (ELF_ST_IS_MIPS16 (st_other
))
443 SET_MSYMBOL_TARGET_FLAG_MIPS16 (msym
);
444 msym
->set_value_address (msym
->value_raw_address () | 1);
448 /* Return one iff MSYM refers to standard ISA code. */
451 msymbol_is_mips (struct minimal_symbol
*msym
)
453 return !(MSYMBOL_TARGET_FLAG_MIPS16 (msym
)
454 | MSYMBOL_TARGET_FLAG_MICROMIPS (msym
));
457 /* Return one iff MSYM refers to MIPS16 code. */
460 msymbol_is_mips16 (struct minimal_symbol
*msym
)
462 return MSYMBOL_TARGET_FLAG_MIPS16 (msym
);
465 /* Return one iff MSYM refers to microMIPS code. */
468 msymbol_is_micromips (struct minimal_symbol
*msym
)
470 return MSYMBOL_TARGET_FLAG_MICROMIPS (msym
);
473 /* Set the ISA bit in the main symbol too, complementing the corresponding
474 minimal symbol setting and reflecting the run-time value of the symbol.
475 The need for comes from the ISA bit having been cleared as code in
476 `_bfd_mips_elf_symbol_processing' separated it into the ELF symbol's
477 `st_other' STO_MIPS16 or STO_MICROMIPS annotation, making the values
478 of symbols referring to compressed code different in GDB to the values
479 used by actual code. That in turn makes them evaluate incorrectly in
480 expressions, producing results different to what the same expressions
481 yield when compiled into the program being debugged. */
484 mips_make_symbol_special (struct symbol
*sym
, struct objfile
*objfile
)
486 if (sym
->aclass () == LOC_BLOCK
)
488 /* We are in symbol reading so it is OK to cast away constness. */
489 struct block
*block
= (struct block
*) sym
->value_block ();
490 CORE_ADDR compact_block_start
;
491 struct bound_minimal_symbol msym
;
493 compact_block_start
= BLOCK_START (block
) | 1;
494 msym
= lookup_minimal_symbol_by_pc (compact_block_start
);
495 if (msym
.minsym
&& !msymbol_is_mips (msym
.minsym
))
497 BLOCK_START (block
) = compact_block_start
;
502 /* XFER a value from the big/little/left end of the register.
503 Depending on the size of the value it might occupy the entire
504 register or just part of it. Make an allowance for this, aligning
505 things accordingly. */
508 mips_xfer_register (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
509 int reg_num
, int length
,
510 enum bfd_endian endian
, gdb_byte
*in
,
511 const gdb_byte
*out
, int buf_offset
)
515 gdb_assert (reg_num
>= gdbarch_num_regs (gdbarch
));
516 /* Need to transfer the left or right part of the register, based on
517 the targets byte order. */
521 reg_offset
= register_size (gdbarch
, reg_num
) - length
;
523 case BFD_ENDIAN_LITTLE
:
526 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
530 internal_error (__FILE__
, __LINE__
, _("bad switch"));
533 gdb_printf (gdb_stderr
,
534 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
535 reg_num
, reg_offset
, buf_offset
, length
);
536 if (mips_debug
&& out
!= NULL
)
539 gdb_printf (gdb_stdlog
, "out ");
540 for (i
= 0; i
< length
; i
++)
541 gdb_printf (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
544 regcache
->cooked_read_part (reg_num
, reg_offset
, length
, in
+ buf_offset
);
546 regcache
->cooked_write_part (reg_num
, reg_offset
, length
, out
+ buf_offset
);
547 if (mips_debug
&& in
!= NULL
)
550 gdb_printf (gdb_stdlog
, "in ");
551 for (i
= 0; i
< length
; i
++)
552 gdb_printf (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
555 gdb_printf (gdb_stdlog
, "\n");
558 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
559 compatiblity mode. A return value of 1 means that we have
560 physical 64-bit registers, but should treat them as 32-bit registers. */
563 mips2_fp_compat (struct frame_info
*frame
)
565 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
566 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
568 if (register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) == 4)
572 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
573 in all the places we deal with FP registers. PR gdb/413. */
574 /* Otherwise check the FR bit in the status register - it controls
575 the FP compatiblity mode. If it is clear we are in compatibility
577 if ((get_frame_register_unsigned (frame
, MIPS_PS_REGNUM
) & ST0_FR
) == 0)
584 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
586 static CORE_ADDR
heuristic_proc_start (struct gdbarch
*, CORE_ADDR
);
588 /* The list of available "set mips " and "show mips " commands. */
590 static struct cmd_list_element
*setmipscmdlist
= NULL
;
591 static struct cmd_list_element
*showmipscmdlist
= NULL
;
593 /* Integer registers 0 thru 31 are handled explicitly by
594 mips_register_name(). Processor specific registers 32 and above
595 are listed in the following tables. */
598 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
602 static const char * const mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
603 "sr", "lo", "hi", "bad", "cause", "pc",
604 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
605 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
606 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
607 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
611 /* Names of tx39 registers. */
613 static const char * const mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
614 "sr", "lo", "hi", "bad", "cause", "pc",
615 "", "", "", "", "", "", "", "",
616 "", "", "", "", "", "", "", "",
617 "", "", "", "", "", "", "", "",
618 "", "", "", "", "", "", "", "",
620 "", "", "", "", "", "", "", "",
621 "", "", "config", "cache", "debug", "depc", "epc",
624 /* Names of registers with Linux kernels. */
625 static const char * const mips_linux_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
626 "sr", "lo", "hi", "bad", "cause", "pc",
627 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
628 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
629 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
630 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
635 /* Return the name of the register corresponding to REGNO. */
637 mips_register_name (struct gdbarch
*gdbarch
, int regno
)
639 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
640 /* GPR names for all ABIs other than n32/n64. */
641 static const char *mips_gpr_names
[] = {
642 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
643 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
644 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
645 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
648 /* GPR names for n32 and n64 ABIs. */
649 static const char *mips_n32_n64_gpr_names
[] = {
650 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
651 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
652 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
653 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
656 enum mips_abi abi
= mips_abi (gdbarch
);
658 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
659 but then don't make the raw register names visible. This (upper)
660 range of user visible register numbers are the pseudo-registers.
662 This approach was adopted accommodate the following scenario:
663 It is possible to debug a 64-bit device using a 32-bit
664 programming model. In such instances, the raw registers are
665 configured to be 64-bits wide, while the pseudo registers are
666 configured to be 32-bits wide. The registers that the user
667 sees - the pseudo registers - match the users expectations
668 given the programming model being used. */
669 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
670 if (regno
< gdbarch_num_regs (gdbarch
))
673 /* The MIPS integer registers are always mapped from 0 to 31. The
674 names of the registers (which reflects the conventions regarding
675 register use) vary depending on the ABI. */
676 if (0 <= rawnum
&& rawnum
< 32)
678 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
679 return mips_n32_n64_gpr_names
[rawnum
];
681 return mips_gpr_names
[rawnum
];
683 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
684 return tdesc_register_name (gdbarch
, rawnum
);
685 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (gdbarch
))
687 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
688 if (tdep
->mips_processor_reg_names
[rawnum
- 32])
689 return tdep
->mips_processor_reg_names
[rawnum
- 32];
693 internal_error (__FILE__
, __LINE__
,
694 _("mips_register_name: bad register number %d"), rawnum
);
697 /* Return the groups that a MIPS register can be categorised into. */
700 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
701 const struct reggroup
*reggroup
)
706 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
707 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
708 if (reggroup
== all_reggroup
)
710 vector_p
= register_type (gdbarch
, regnum
)->is_vector ();
711 float_p
= register_type (gdbarch
, regnum
)->code () == TYPE_CODE_FLT
;
712 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
713 (gdbarch), as not all architectures are multi-arch. */
714 raw_p
= rawnum
< gdbarch_num_regs (gdbarch
);
715 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
716 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
718 if (reggroup
== float_reggroup
)
719 return float_p
&& pseudo
;
720 if (reggroup
== vector_reggroup
)
721 return vector_p
&& pseudo
;
722 if (reggroup
== general_reggroup
)
723 return (!vector_p
&& !float_p
) && pseudo
;
724 /* Save the pseudo registers. Need to make certain that any code
725 extracting register values from a saved register cache also uses
727 if (reggroup
== save_reggroup
)
728 return raw_p
&& pseudo
;
729 /* Restore the same pseudo register. */
730 if (reggroup
== restore_reggroup
)
731 return raw_p
&& pseudo
;
735 /* Return the groups that a MIPS register can be categorised into.
736 This version is only used if we have a target description which
737 describes real registers (and their groups). */
740 mips_tdesc_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
741 const struct reggroup
*reggroup
)
743 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
744 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
747 /* Only save, restore, and display the pseudo registers. Need to
748 make certain that any code extracting register values from a
749 saved register cache also uses pseudo registers.
751 Note: saving and restoring the pseudo registers is slightly
752 strange; if we have 64 bits, we should save and restore all
753 64 bits. But this is hard and has little benefit. */
757 ret
= tdesc_register_in_reggroup_p (gdbarch
, rawnum
, reggroup
);
761 return mips_register_reggroup_p (gdbarch
, regnum
, reggroup
);
764 /* Map the symbol table registers which live in the range [1 *
765 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
766 registers. Take care of alignment and size problems. */
768 static enum register_status
769 mips_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
770 int cookednum
, gdb_byte
*buf
)
772 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
773 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
774 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
775 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
776 return regcache
->raw_read (rawnum
, buf
);
777 else if (register_size (gdbarch
, rawnum
) >
778 register_size (gdbarch
, cookednum
))
780 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
782 if (tdep
->mips64_transfers_32bit_regs_p
)
783 return regcache
->raw_read_part (rawnum
, 0, 4, buf
);
786 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
788 enum register_status status
;
790 status
= regcache
->raw_read (rawnum
, ®val
);
791 if (status
== REG_VALID
)
792 store_signed_integer (buf
, 4, byte_order
, regval
);
797 internal_error (__FILE__
, __LINE__
, _("bad register size"));
801 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
802 struct regcache
*regcache
, int cookednum
,
805 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
806 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
807 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
808 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
809 regcache
->raw_write (rawnum
, buf
);
810 else if (register_size (gdbarch
, rawnum
) >
811 register_size (gdbarch
, cookednum
))
813 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
815 if (tdep
->mips64_transfers_32bit_regs_p
)
816 regcache
->raw_write_part (rawnum
, 0, 4, buf
);
819 /* Sign extend the shortened version of the register prior
820 to placing it in the raw register. This is required for
821 some mips64 parts in order to avoid unpredictable behavior. */
822 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
823 LONGEST regval
= extract_signed_integer (buf
, 4, byte_order
);
824 regcache_raw_write_signed (regcache
, rawnum
, regval
);
828 internal_error (__FILE__
, __LINE__
, _("bad register size"));
832 mips_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
833 struct agent_expr
*ax
, int reg
)
835 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
836 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
837 && reg
< 2 * gdbarch_num_regs (gdbarch
));
839 ax_reg_mask (ax
, rawnum
);
845 mips_ax_pseudo_register_push_stack (struct gdbarch
*gdbarch
,
846 struct agent_expr
*ax
, int reg
)
848 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
849 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
850 && reg
< 2 * gdbarch_num_regs (gdbarch
));
851 if (register_size (gdbarch
, rawnum
) >= register_size (gdbarch
, reg
))
855 if (register_size (gdbarch
, rawnum
) > register_size (gdbarch
, reg
))
857 mips_gdbarch_tdep
*tdep
858 = (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
860 if (!tdep
->mips64_transfers_32bit_regs_p
861 || gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_BIG
)
864 ax_simple (ax
, aop_lsh
);
867 ax_simple (ax
, aop_rsh_signed
);
871 internal_error (__FILE__
, __LINE__
, _("bad register size"));
876 /* Table to translate 3-bit register field to actual register number. */
877 static const signed char mips_reg3_to_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
879 /* Heuristic_proc_start may hunt through the text section for a long
880 time across a 2400 baud serial line. Allows the user to limit this
883 static int heuristic_fence_post
= 0;
885 /* Number of bytes of storage in the actual machine representation for
886 register N. NOTE: This defines the pseudo register type so need to
887 rebuild the architecture vector. */
889 static bool mips64_transfers_32bit_regs_p
= false;
892 set_mips64_transfers_32bit_regs (const char *args
, int from_tty
,
893 struct cmd_list_element
*c
)
895 struct gdbarch_info info
;
896 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
897 instead of relying on globals. Doing that would let generic code
898 handle the search for this specific architecture. */
899 if (!gdbarch_update_p (info
))
901 mips64_transfers_32bit_regs_p
= 0;
902 error (_("32-bit compatibility mode not supported"));
906 /* Convert to/from a register and the corresponding memory value. */
908 /* This predicate tests for the case of an 8 byte floating point
909 value that is being transferred to or from a pair of floating point
910 registers each of which are (or are considered to be) only 4 bytes
913 mips_convert_register_float_case_p (struct gdbarch
*gdbarch
, int regnum
,
916 return (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
917 && register_size (gdbarch
, regnum
) == 4
918 && mips_float_register_p (gdbarch
, regnum
)
919 && type
->code () == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
922 /* This predicate tests for the case of a value of less than 8
923 bytes in width that is being transfered to or from an 8 byte
924 general purpose register. */
926 mips_convert_register_gpreg_case_p (struct gdbarch
*gdbarch
, int regnum
,
929 int num_regs
= gdbarch_num_regs (gdbarch
);
931 return (register_size (gdbarch
, regnum
) == 8
932 && regnum
% num_regs
> 0 && regnum
% num_regs
< 32
933 && TYPE_LENGTH (type
) < 8);
937 mips_convert_register_p (struct gdbarch
*gdbarch
,
938 int regnum
, struct type
*type
)
940 return (mips_convert_register_float_case_p (gdbarch
, regnum
, type
)
941 || mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
));
945 mips_register_to_value (struct frame_info
*frame
, int regnum
,
946 struct type
*type
, gdb_byte
*to
,
947 int *optimizedp
, int *unavailablep
)
949 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
951 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
953 get_frame_register (frame
, regnum
+ 0, to
+ 4);
954 get_frame_register (frame
, regnum
+ 1, to
+ 0);
956 if (!get_frame_register_bytes (frame
, regnum
+ 0, 0, {to
+ 4, 4},
957 optimizedp
, unavailablep
))
960 if (!get_frame_register_bytes (frame
, regnum
+ 1, 0, {to
+ 0, 4},
961 optimizedp
, unavailablep
))
963 *optimizedp
= *unavailablep
= 0;
966 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
968 size_t len
= TYPE_LENGTH (type
);
971 offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 8 - len
: 0;
972 if (!get_frame_register_bytes (frame
, regnum
, offset
, {to
, len
},
973 optimizedp
, unavailablep
))
976 *optimizedp
= *unavailablep
= 0;
981 internal_error (__FILE__
, __LINE__
,
982 _("mips_register_to_value: unrecognized case"));
987 mips_value_to_register (struct frame_info
*frame
, int regnum
,
988 struct type
*type
, const gdb_byte
*from
)
990 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
992 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
994 put_frame_register (frame
, regnum
+ 0, from
+ 4);
995 put_frame_register (frame
, regnum
+ 1, from
+ 0);
997 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
1000 size_t len
= TYPE_LENGTH (type
);
1002 /* Sign extend values, irrespective of type, that are stored to
1003 a 64-bit general purpose register. (32-bit unsigned values
1004 are stored as signed quantities within a 64-bit register.
1005 When performing an operation, in compiled code, that combines
1006 a 32-bit unsigned value with a signed 64-bit value, a type
1007 conversion is first performed that zeroes out the high 32 bits.) */
1008 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1011 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, -1);
1013 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, 0);
1014 put_frame_register_bytes (frame
, regnum
, 0, {fill
, 8 - len
});
1015 put_frame_register_bytes (frame
, regnum
, 8 - len
, {from
, len
});
1019 if (from
[len
-1] & 0x80)
1020 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, -1);
1022 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, 0);
1023 put_frame_register_bytes (frame
, regnum
, 0, {from
, len
});
1024 put_frame_register_bytes (frame
, regnum
, len
, {fill
, 8 - len
});
1029 internal_error (__FILE__
, __LINE__
,
1030 _("mips_value_to_register: unrecognized case"));
1034 /* Return the GDB type object for the "standard" data type of data in
1037 static struct type
*
1038 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
1040 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (gdbarch
));
1041 if (mips_float_register_p (gdbarch
, regnum
))
1043 /* The floating-point registers raw, or cooked, always match
1044 mips_isa_regsize(), and also map 1:1, byte for byte. */
1045 if (mips_isa_regsize (gdbarch
) == 4)
1046 return builtin_type (gdbarch
)->builtin_float
;
1048 return builtin_type (gdbarch
)->builtin_double
;
1050 else if (regnum
< gdbarch_num_regs (gdbarch
))
1052 /* The raw or ISA registers. These are all sized according to
1054 if (mips_isa_regsize (gdbarch
) == 4)
1055 return builtin_type (gdbarch
)->builtin_int32
;
1057 return builtin_type (gdbarch
)->builtin_int64
;
1061 int rawnum
= regnum
- gdbarch_num_regs (gdbarch
);
1062 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
1064 /* The cooked or ABI registers. These are sized according to
1065 the ABI (with a few complications). */
1066 if (rawnum
== mips_regnum (gdbarch
)->fp_control_status
1067 || rawnum
== mips_regnum (gdbarch
)->fp_implementation_revision
)
1068 return builtin_type (gdbarch
)->builtin_int32
;
1069 else if (gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
1070 && rawnum
>= MIPS_FIRST_EMBED_REGNUM
1071 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
1072 /* The pseudo/cooked view of the embedded registers is always
1073 32-bit. The raw view is handled below. */
1074 return builtin_type (gdbarch
)->builtin_int32
;
1075 else if (tdep
->mips64_transfers_32bit_regs_p
)
1076 /* The target, while possibly using a 64-bit register buffer,
1077 is only transfering 32-bits of each integer register.
1078 Reflect this in the cooked/pseudo (ABI) register value. */
1079 return builtin_type (gdbarch
)->builtin_int32
;
1080 else if (mips_abi_regsize (gdbarch
) == 4)
1081 /* The ABI is restricted to 32-bit registers (the ISA could be
1083 return builtin_type (gdbarch
)->builtin_int32
;
1086 return builtin_type (gdbarch
)->builtin_int64
;
1090 /* Return the GDB type for the pseudo register REGNUM, which is the
1091 ABI-level view. This function is only called if there is a target
1092 description which includes registers, so we know precisely the
1093 types of hardware registers. */
1095 static struct type
*
1096 mips_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
1098 const int num_regs
= gdbarch_num_regs (gdbarch
);
1099 int rawnum
= regnum
% num_regs
;
1100 struct type
*rawtype
;
1102 gdb_assert (regnum
>= num_regs
&& regnum
< 2 * num_regs
);
1104 /* Absent registers are still absent. */
1105 rawtype
= gdbarch_register_type (gdbarch
, rawnum
);
1106 if (TYPE_LENGTH (rawtype
) == 0)
1109 /* Present the floating point registers however the hardware did;
1110 do not try to convert between FPU layouts. */
1111 if (mips_float_register_p (gdbarch
, rawnum
))
1114 /* Floating-point control registers are always 32-bit even though for
1115 backwards compatibility reasons 64-bit targets will transfer them
1116 as 64-bit quantities even if using XML descriptions. */
1117 if (rawnum
== mips_regnum (gdbarch
)->fp_control_status
1118 || rawnum
== mips_regnum (gdbarch
)->fp_implementation_revision
)
1119 return builtin_type (gdbarch
)->builtin_int32
;
1121 /* Use pointer types for registers if we can. For n32 we can not,
1122 since we do not have a 64-bit pointer type. */
1123 if (mips_abi_regsize (gdbarch
)
1124 == TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
))
1126 if (rawnum
== MIPS_SP_REGNUM
1127 || rawnum
== mips_regnum (gdbarch
)->badvaddr
)
1128 return builtin_type (gdbarch
)->builtin_data_ptr
;
1129 else if (rawnum
== mips_regnum (gdbarch
)->pc
)
1130 return builtin_type (gdbarch
)->builtin_func_ptr
;
1133 if (mips_abi_regsize (gdbarch
) == 4 && TYPE_LENGTH (rawtype
) == 8
1134 && ((rawnum
>= MIPS_ZERO_REGNUM
&& rawnum
<= MIPS_PS_REGNUM
)
1135 || rawnum
== mips_regnum (gdbarch
)->lo
1136 || rawnum
== mips_regnum (gdbarch
)->hi
1137 || rawnum
== mips_regnum (gdbarch
)->badvaddr
1138 || rawnum
== mips_regnum (gdbarch
)->cause
1139 || rawnum
== mips_regnum (gdbarch
)->pc
1140 || (mips_regnum (gdbarch
)->dspacc
!= -1
1141 && rawnum
>= mips_regnum (gdbarch
)->dspacc
1142 && rawnum
< mips_regnum (gdbarch
)->dspacc
+ 6)))
1143 return builtin_type (gdbarch
)->builtin_int32
;
1145 /* The pseudo/cooked view of embedded registers is always
1146 32-bit, even if the target transfers 64-bit values for them.
1147 New targets relying on XML descriptions should only transfer
1148 the necessary 32 bits, but older versions of GDB expected 64,
1149 so allow the target to provide 64 bits without interfering
1150 with the displayed type. */
1151 if (gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
1152 && rawnum
>= MIPS_FIRST_EMBED_REGNUM
1153 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
1154 return builtin_type (gdbarch
)->builtin_int32
;
1156 /* For all other registers, pass through the hardware type. */
1160 /* Should the upper word of 64-bit addresses be zeroed? */
1161 static enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
1164 mips_mask_address_p (mips_gdbarch_tdep
*tdep
)
1166 switch (mask_address_var
)
1168 case AUTO_BOOLEAN_TRUE
:
1170 case AUTO_BOOLEAN_FALSE
:
1173 case AUTO_BOOLEAN_AUTO
:
1174 return tdep
->default_mask_address_p
;
1176 internal_error (__FILE__
, __LINE__
,
1177 _("mips_mask_address_p: bad switch"));
1183 show_mask_address (struct ui_file
*file
, int from_tty
,
1184 struct cmd_list_element
*c
, const char *value
)
1186 mips_gdbarch_tdep
*tdep
1187 = (mips_gdbarch_tdep
*) gdbarch_tdep (target_gdbarch ());
1189 deprecated_show_value_hack (file
, from_tty
, c
, value
);
1190 switch (mask_address_var
)
1192 case AUTO_BOOLEAN_TRUE
:
1193 gdb_printf (file
, "The 32 bit mips address mask is enabled\n");
1195 case AUTO_BOOLEAN_FALSE
:
1196 gdb_printf (file
, "The 32 bit mips address mask is disabled\n");
1198 case AUTO_BOOLEAN_AUTO
:
1201 "The 32 bit address mask is set automatically. Currently %s\n",
1202 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
1205 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
1210 /* Tell if the program counter value in MEMADDR is in a standard ISA
1214 mips_pc_is_mips (CORE_ADDR memaddr
)
1216 struct bound_minimal_symbol sym
;
1218 /* Flags indicating that this is a MIPS16 or microMIPS function is
1219 stored by elfread.c in the high bit of the info field. Use this
1220 to decide if the function is standard MIPS. Otherwise if bit 0
1221 of the address is clear, then this is a standard MIPS function. */
1222 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1224 return msymbol_is_mips (sym
.minsym
);
1226 return is_mips_addr (memaddr
);
1229 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
1232 mips_pc_is_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1234 struct bound_minimal_symbol sym
;
1236 /* A flag indicating that this is a MIPS16 function is stored by
1237 elfread.c in the high bit of the info field. Use this to decide
1238 if the function is MIPS16. Otherwise if bit 0 of the address is
1239 set, then ELF file flags will tell if this is a MIPS16 function. */
1240 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1242 return msymbol_is_mips16 (sym
.minsym
);
1244 return is_mips16_addr (gdbarch
, memaddr
);
1247 /* Tell if the program counter value in MEMADDR is in a microMIPS function. */
1250 mips_pc_is_micromips (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1252 struct bound_minimal_symbol sym
;
1254 /* A flag indicating that this is a microMIPS function is stored by
1255 elfread.c in the high bit of the info field. Use this to decide
1256 if the function is microMIPS. Otherwise if bit 0 of the address
1257 is set, then ELF file flags will tell if this is a microMIPS
1259 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1261 return msymbol_is_micromips (sym
.minsym
);
1263 return is_micromips_addr (gdbarch
, memaddr
);
1266 /* Tell the ISA type of the function the program counter value in MEMADDR
1269 static enum mips_isa
1270 mips_pc_isa (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1272 struct bound_minimal_symbol sym
;
1274 /* A flag indicating that this is a MIPS16 or a microMIPS function
1275 is stored by elfread.c in the high bit of the info field. Use
1276 this to decide if the function is MIPS16 or microMIPS or normal
1277 MIPS. Otherwise if bit 0 of the address is set, then ELF file
1278 flags will tell if this is a MIPS16 or a microMIPS function. */
1279 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1282 if (msymbol_is_micromips (sym
.minsym
))
1283 return ISA_MICROMIPS
;
1284 else if (msymbol_is_mips16 (sym
.minsym
))
1291 if (is_mips_addr (memaddr
))
1293 else if (is_micromips_addr (gdbarch
, memaddr
))
1294 return ISA_MICROMIPS
;
1300 /* Set the ISA bit correctly in the PC, used by DWARF-2 machinery.
1301 The need for comes from the ISA bit having been cleared, making
1302 addresses in FDE, range records, etc. referring to compressed code
1303 different to those in line information, the symbol table and finally
1304 the PC register. That in turn confuses many operations. */
1307 mips_adjust_dwarf2_addr (CORE_ADDR pc
)
1309 pc
= unmake_compact_addr (pc
);
1310 return mips_pc_is_mips (pc
) ? pc
: make_compact_addr (pc
);
1313 /* Recalculate the line record requested so that the resulting PC has
1314 the ISA bit set correctly, used by DWARF-2 machinery. The need for
1315 this adjustment comes from some records associated with compressed
1316 code having the ISA bit cleared, most notably at function prologue
1317 ends. The ISA bit is in this context retrieved from the minimal
1318 symbol covering the address requested, which in turn has been
1319 constructed from the binary's symbol table rather than DWARF-2
1320 information. The correct setting of the ISA bit is required for
1321 breakpoint addresses to correctly match against the stop PC.
1323 As line entries can specify relative address adjustments we need to
1324 keep track of the absolute value of the last line address recorded
1325 in line information, so that we can calculate the actual address to
1326 apply the ISA bit adjustment to. We use PC for this tracking and
1327 keep the original address there.
1329 As such relative address adjustments can be odd within compressed
1330 code we need to keep track of the last line address with the ISA
1331 bit adjustment applied too, as the original address may or may not
1332 have had the ISA bit set. We use ADJ_PC for this tracking and keep
1333 the adjusted address there.
1335 For relative address adjustments we then use these variables to
1336 calculate the address intended by line information, which will be
1337 PC-relative, and return an updated adjustment carrying ISA bit
1338 information, which will be ADJ_PC-relative. For absolute address
1339 adjustments we just return the same address that we store in ADJ_PC
1342 As the first line entry can be relative to an implied address value
1343 of 0 we need to have the initial address set up that we store in PC
1344 and ADJ_PC. This is arranged with a call from `dwarf_decode_lines_1'
1345 that sets PC to 0 and ADJ_PC accordingly, usually 0 as well. */
1348 mips_adjust_dwarf2_line (CORE_ADDR addr
, int rel
)
1350 static CORE_ADDR adj_pc
;
1351 static CORE_ADDR pc
;
1354 pc
= rel
? pc
+ addr
: addr
;
1355 isa_pc
= mips_adjust_dwarf2_addr (pc
);
1356 addr
= rel
? isa_pc
- adj_pc
: isa_pc
;
1361 /* Various MIPS16 thunk (aka stub or trampoline) names. */
1363 static const char mips_str_mips16_call_stub
[] = "__mips16_call_stub_";
1364 static const char mips_str_mips16_ret_stub
[] = "__mips16_ret_";
1365 static const char mips_str_call_fp_stub
[] = "__call_stub_fp_";
1366 static const char mips_str_call_stub
[] = "__call_stub_";
1367 static const char mips_str_fn_stub
[] = "__fn_stub_";
1369 /* This is used as a PIC thunk prefix. */
1371 static const char mips_str_pic
[] = ".pic.";
1373 /* Return non-zero if the PC is inside a call thunk (aka stub or
1374 trampoline) that should be treated as a temporary frame. */
1377 mips_in_frame_stub (CORE_ADDR pc
)
1379 CORE_ADDR start_addr
;
1382 /* Find the starting address of the function containing the PC. */
1383 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
1386 /* If the PC is in __mips16_call_stub_*, this is a call/return stub. */
1387 if (startswith (name
, mips_str_mips16_call_stub
))
1389 /* If the PC is in __call_stub_*, this is a call/return or a call stub. */
1390 if (startswith (name
, mips_str_call_stub
))
1392 /* If the PC is in __fn_stub_*, this is a call stub. */
1393 if (startswith (name
, mips_str_fn_stub
))
1396 return 0; /* Not a stub. */
1399 /* MIPS believes that the PC has a sign extended value. Perhaps the
1400 all registers should be sign extended for simplicity? */
1403 mips_read_pc (readable_regcache
*regcache
)
1405 int regnum
= gdbarch_pc_regnum (regcache
->arch ());
1408 regcache
->cooked_read (regnum
, &pc
);
1413 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1417 pc
= frame_unwind_register_signed (next_frame
, gdbarch_pc_regnum (gdbarch
));
1418 /* macro/2012-04-20: This hack skips over MIPS16 call thunks as
1419 intermediate frames. In this case we can get the caller's address
1420 from $ra, or if $ra contains an address within a thunk as well, then
1421 it must be in the return path of __mips16_call_stub_{s,d}{f,c}_{0..10}
1422 and thus the caller's address is in $s2. */
1423 if (frame_relative_level (next_frame
) >= 0 && mips_in_frame_stub (pc
))
1425 pc
= frame_unwind_register_signed
1426 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
1427 if (mips_in_frame_stub (pc
))
1428 pc
= frame_unwind_register_signed
1429 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
1435 mips_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1437 return frame_unwind_register_signed
1438 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
);
1441 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1442 dummy frame. The frame ID's base needs to match the TOS value
1443 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1446 static struct frame_id
1447 mips_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1449 return frame_id_build
1450 (get_frame_register_signed (this_frame
,
1451 gdbarch_num_regs (gdbarch
)
1453 get_frame_pc (this_frame
));
1456 /* Implement the "write_pc" gdbarch method. */
1459 mips_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1461 int regnum
= gdbarch_pc_regnum (regcache
->arch ());
1463 regcache_cooked_write_unsigned (regcache
, regnum
, pc
);
1466 /* Fetch and return instruction from the specified location. Handle
1467 MIPS16/microMIPS as appropriate. */
1470 mips_fetch_instruction (struct gdbarch
*gdbarch
,
1471 enum mips_isa isa
, CORE_ADDR addr
, int *errp
)
1473 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1474 gdb_byte buf
[MIPS_INSN32_SIZE
];
1482 instlen
= MIPS_INSN16_SIZE
;
1483 addr
= unmake_compact_addr (addr
);
1486 instlen
= MIPS_INSN32_SIZE
;
1489 internal_error (__FILE__
, __LINE__
, _("invalid ISA"));
1492 err
= target_read_memory (addr
, buf
, instlen
);
1498 memory_error (TARGET_XFER_E_IO
, addr
);
1501 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1504 /* These are the fields of 32 bit mips instructions. */
1505 #define mips32_op(x) (x >> 26)
1506 #define itype_op(x) (x >> 26)
1507 #define itype_rs(x) ((x >> 21) & 0x1f)
1508 #define itype_rt(x) ((x >> 16) & 0x1f)
1509 #define itype_immediate(x) (x & 0xffff)
1511 #define jtype_op(x) (x >> 26)
1512 #define jtype_target(x) (x & 0x03ffffff)
1514 #define rtype_op(x) (x >> 26)
1515 #define rtype_rs(x) ((x >> 21) & 0x1f)
1516 #define rtype_rt(x) ((x >> 16) & 0x1f)
1517 #define rtype_rd(x) ((x >> 11) & 0x1f)
1518 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1519 #define rtype_funct(x) (x & 0x3f)
1521 /* MicroMIPS instruction fields. */
1522 #define micromips_op(x) ((x) >> 10)
1524 /* 16-bit/32-bit-high-part instruction formats, B and S refer to the lowest
1525 bit and the size respectively of the field extracted. */
1526 #define b0s4_imm(x) ((x) & 0xf)
1527 #define b0s5_imm(x) ((x) & 0x1f)
1528 #define b0s5_reg(x) ((x) & 0x1f)
1529 #define b0s7_imm(x) ((x) & 0x7f)
1530 #define b0s10_imm(x) ((x) & 0x3ff)
1531 #define b1s4_imm(x) (((x) >> 1) & 0xf)
1532 #define b1s9_imm(x) (((x) >> 1) & 0x1ff)
1533 #define b2s3_cc(x) (((x) >> 2) & 0x7)
1534 #define b4s2_regl(x) (((x) >> 4) & 0x3)
1535 #define b5s5_op(x) (((x) >> 5) & 0x1f)
1536 #define b5s5_reg(x) (((x) >> 5) & 0x1f)
1537 #define b6s4_op(x) (((x) >> 6) & 0xf)
1538 #define b7s3_reg(x) (((x) >> 7) & 0x7)
1540 /* 32-bit instruction formats, B and S refer to the lowest bit and the size
1541 respectively of the field extracted. */
1542 #define b0s6_op(x) ((x) & 0x3f)
1543 #define b0s11_op(x) ((x) & 0x7ff)
1544 #define b0s12_imm(x) ((x) & 0xfff)
1545 #define b0s16_imm(x) ((x) & 0xffff)
1546 #define b0s26_imm(x) ((x) & 0x3ffffff)
1547 #define b6s10_ext(x) (((x) >> 6) & 0x3ff)
1548 #define b11s5_reg(x) (((x) >> 11) & 0x1f)
1549 #define b12s4_op(x) (((x) >> 12) & 0xf)
1551 /* Return the size in bytes of the instruction INSN encoded in the ISA
1555 mips_insn_size (enum mips_isa isa
, ULONGEST insn
)
1560 if ((micromips_op (insn
) & 0x4) == 0x4
1561 || (micromips_op (insn
) & 0x7) == 0x0)
1562 return 2 * MIPS_INSN16_SIZE
;
1564 return MIPS_INSN16_SIZE
;
1566 if ((insn
& 0xf800) == 0xf000)
1567 return 2 * MIPS_INSN16_SIZE
;
1569 return MIPS_INSN16_SIZE
;
1571 return MIPS_INSN32_SIZE
;
1573 internal_error (__FILE__
, __LINE__
, _("invalid ISA"));
1577 mips32_relative_offset (ULONGEST inst
)
1579 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
1582 /* Determine the address of the next instruction executed after the INST
1583 floating condition branch instruction at PC. COUNT specifies the
1584 number of the floating condition bits tested by the branch. */
1587 mips32_bc1_pc (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1588 ULONGEST inst
, CORE_ADDR pc
, int count
)
1590 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1591 int cnum
= (itype_rt (inst
) >> 2) & (count
- 1);
1592 int tf
= itype_rt (inst
) & 1;
1593 int mask
= (1 << count
) - 1;
1598 /* No way to handle; it'll most likely trap anyway. */
1601 fcs
= regcache_raw_get_unsigned (regcache
, fcsr
);
1602 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1604 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1605 pc
+= mips32_relative_offset (inst
);
1612 /* Return nonzero if the gdbarch is an Octeon series. */
1615 is_octeon (struct gdbarch
*gdbarch
)
1617 const struct bfd_arch_info
*info
= gdbarch_bfd_arch_info (gdbarch
);
1619 return (info
->mach
== bfd_mach_mips_octeon
1620 || info
->mach
== bfd_mach_mips_octeonp
1621 || info
->mach
== bfd_mach_mips_octeon2
);
1624 /* Return true if the OP represents the Octeon's BBIT instruction. */
1627 is_octeon_bbit_op (int op
, struct gdbarch
*gdbarch
)
1629 if (!is_octeon (gdbarch
))
1631 /* BBIT0 is encoded as LWC2: 110 010. */
1632 /* BBIT032 is encoded as LDC2: 110 110. */
1633 /* BBIT1 is encoded as SWC2: 111 010. */
1634 /* BBIT132 is encoded as SDC2: 111 110. */
1635 if (op
== 50 || op
== 54 || op
== 58 || op
== 62)
1641 /* Determine where to set a single step breakpoint while considering
1642 branch prediction. */
1645 mips32_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1647 struct gdbarch
*gdbarch
= regcache
->arch ();
1650 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
1651 op
= itype_op (inst
);
1652 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch
1656 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1667 goto greater_branch
;
1672 else if (op
== 17 && itype_rs (inst
) == 8)
1673 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1674 pc
= mips32_bc1_pc (gdbarch
, regcache
, inst
, pc
+ 4, 1);
1675 else if (op
== 17 && itype_rs (inst
) == 9
1676 && (itype_rt (inst
) & 2) == 0)
1677 /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */
1678 pc
= mips32_bc1_pc (gdbarch
, regcache
, inst
, pc
+ 4, 2);
1679 else if (op
== 17 && itype_rs (inst
) == 10
1680 && (itype_rt (inst
) & 2) == 0)
1681 /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */
1682 pc
= mips32_bc1_pc (gdbarch
, regcache
, inst
, pc
+ 4, 4);
1685 /* The new PC will be alternate mode. */
1689 reg
= jtype_target (inst
) << 2;
1690 /* Add 1 to indicate 16-bit mode -- invert ISA mode. */
1691 pc
= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + reg
+ 1;
1693 else if (is_octeon_bbit_op (op
, gdbarch
))
1697 branch_if
= op
== 58 || op
== 62;
1698 bit
= itype_rt (inst
);
1700 /* Take into account the *32 instructions. */
1701 if (op
== 54 || op
== 62)
1704 if (((regcache_raw_get_signed (regcache
,
1705 itype_rs (inst
)) >> bit
) & 1)
1707 pc
+= mips32_relative_offset (inst
) + 4;
1709 pc
+= 8; /* After the delay slot. */
1713 pc
+= 4; /* Not a branch, next instruction is easy. */
1716 { /* This gets way messy. */
1718 /* Further subdivide into SPECIAL, REGIMM and other. */
1719 switch (op
& 0x07) /* Extract bits 28,27,26. */
1721 case 0: /* SPECIAL */
1722 op
= rtype_funct (inst
);
1727 /* Set PC to that address. */
1728 pc
= regcache_raw_get_signed (regcache
, rtype_rs (inst
));
1730 case 12: /* SYSCALL */
1732 mips_gdbarch_tdep
*tdep
1733 = (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
1735 if (tdep
->syscall_next_pc
!= NULL
)
1736 pc
= tdep
->syscall_next_pc (get_current_frame ());
1745 break; /* end SPECIAL */
1746 case 1: /* REGIMM */
1748 op
= itype_rt (inst
); /* branch condition */
1753 case 16: /* BLTZAL */
1754 case 18: /* BLTZALL */
1756 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) < 0)
1757 pc
+= mips32_relative_offset (inst
) + 4;
1759 pc
+= 8; /* after the delay slot */
1763 case 17: /* BGEZAL */
1764 case 19: /* BGEZALL */
1765 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) >= 0)
1766 pc
+= mips32_relative_offset (inst
) + 4;
1768 pc
+= 8; /* after the delay slot */
1770 case 0x1c: /* BPOSGE32 */
1771 case 0x1e: /* BPOSGE64 */
1773 if (itype_rs (inst
) == 0)
1775 unsigned int pos
= (op
& 2) ? 64 : 32;
1776 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
1779 /* No way to handle; it'll most likely trap anyway. */
1782 if ((regcache_raw_get_unsigned (regcache
,
1783 dspctl
) & 0x7f) >= pos
)
1784 pc
+= mips32_relative_offset (inst
);
1789 /* All of the other instructions in the REGIMM category */
1794 break; /* end REGIMM */
1799 reg
= jtype_target (inst
) << 2;
1800 /* Upper four bits get never changed... */
1801 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1804 case 4: /* BEQ, BEQL */
1806 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) ==
1807 regcache_raw_get_signed (regcache
, itype_rt (inst
)))
1808 pc
+= mips32_relative_offset (inst
) + 4;
1812 case 5: /* BNE, BNEL */
1814 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) !=
1815 regcache_raw_get_signed (regcache
, itype_rt (inst
)))
1816 pc
+= mips32_relative_offset (inst
) + 4;
1820 case 6: /* BLEZ, BLEZL */
1821 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) <= 0)
1822 pc
+= mips32_relative_offset (inst
) + 4;
1828 greater_branch
: /* BGTZ, BGTZL */
1829 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) > 0)
1830 pc
+= mips32_relative_offset (inst
) + 4;
1837 } /* mips32_next_pc */
1839 /* Extract the 7-bit signed immediate offset from the microMIPS instruction
1843 micromips_relative_offset7 (ULONGEST insn
)
1845 return ((b0s7_imm (insn
) ^ 0x40) - 0x40) << 1;
1848 /* Extract the 10-bit signed immediate offset from the microMIPS instruction
1852 micromips_relative_offset10 (ULONGEST insn
)
1854 return ((b0s10_imm (insn
) ^ 0x200) - 0x200) << 1;
1857 /* Extract the 16-bit signed immediate offset from the microMIPS instruction
1861 micromips_relative_offset16 (ULONGEST insn
)
1863 return ((b0s16_imm (insn
) ^ 0x8000) - 0x8000) << 1;
1866 /* Return the size in bytes of the microMIPS instruction at the address PC. */
1869 micromips_pc_insn_size (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1873 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1874 return mips_insn_size (ISA_MICROMIPS
, insn
);
1877 /* Calculate the address of the next microMIPS instruction to execute
1878 after the INSN coprocessor 1 conditional branch instruction at the
1879 address PC. COUNT denotes the number of coprocessor condition bits
1880 examined by the branch. */
1883 micromips_bc1_pc (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1884 ULONGEST insn
, CORE_ADDR pc
, int count
)
1886 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1887 int cnum
= b2s3_cc (insn
>> 16) & (count
- 1);
1888 int tf
= b5s5_op (insn
>> 16) & 1;
1889 int mask
= (1 << count
) - 1;
1894 /* No way to handle; it'll most likely trap anyway. */
1897 fcs
= regcache_raw_get_unsigned (regcache
, fcsr
);
1898 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1900 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1901 pc
+= micromips_relative_offset16 (insn
);
1903 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1908 /* Calculate the address of the next microMIPS instruction to execute
1909 after the instruction at the address PC. */
1912 micromips_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1914 struct gdbarch
*gdbarch
= regcache
->arch ();
1917 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1918 pc
+= MIPS_INSN16_SIZE
;
1919 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
1921 /* 32-bit instructions. */
1922 case 2 * MIPS_INSN16_SIZE
:
1924 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1925 pc
+= MIPS_INSN16_SIZE
;
1926 switch (micromips_op (insn
>> 16))
1928 case 0x00: /* POOL32A: bits 000000 */
1929 switch (b0s6_op (insn
))
1931 case 0x3c: /* POOL32Axf: bits 000000 ... 111100 */
1932 switch (b6s10_ext (insn
))
1934 case 0x3c: /* JALR: 000000 0000111100 111100 */
1935 case 0x7c: /* JALR.HB: 000000 0001111100 111100 */
1936 case 0x13c: /* JALRS: 000000 0100111100 111100 */
1937 case 0x17c: /* JALRS.HB: 000000 0101111100 111100 */
1938 pc
= regcache_raw_get_signed (regcache
,
1939 b0s5_reg (insn
>> 16));
1941 case 0x22d: /* SYSCALL: 000000 1000101101 111100 */
1943 mips_gdbarch_tdep
*tdep
1944 = (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
1946 if (tdep
->syscall_next_pc
!= NULL
)
1947 pc
= tdep
->syscall_next_pc (get_current_frame ());
1955 case 0x10: /* POOL32I: bits 010000 */
1956 switch (b5s5_op (insn
>> 16))
1958 case 0x00: /* BLTZ: bits 010000 00000 */
1959 case 0x01: /* BLTZAL: bits 010000 00001 */
1960 case 0x11: /* BLTZALS: bits 010000 10001 */
1961 if (regcache_raw_get_signed (regcache
,
1962 b0s5_reg (insn
>> 16)) < 0)
1963 pc
+= micromips_relative_offset16 (insn
);
1965 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1968 case 0x02: /* BGEZ: bits 010000 00010 */
1969 case 0x03: /* BGEZAL: bits 010000 00011 */
1970 case 0x13: /* BGEZALS: bits 010000 10011 */
1971 if (regcache_raw_get_signed (regcache
,
1972 b0s5_reg (insn
>> 16)) >= 0)
1973 pc
+= micromips_relative_offset16 (insn
);
1975 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1978 case 0x04: /* BLEZ: bits 010000 00100 */
1979 if (regcache_raw_get_signed (regcache
,
1980 b0s5_reg (insn
>> 16)) <= 0)
1981 pc
+= micromips_relative_offset16 (insn
);
1983 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1986 case 0x05: /* BNEZC: bits 010000 00101 */
1987 if (regcache_raw_get_signed (regcache
,
1988 b0s5_reg (insn
>> 16)) != 0)
1989 pc
+= micromips_relative_offset16 (insn
);
1992 case 0x06: /* BGTZ: bits 010000 00110 */
1993 if (regcache_raw_get_signed (regcache
,
1994 b0s5_reg (insn
>> 16)) > 0)
1995 pc
+= micromips_relative_offset16 (insn
);
1997 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2000 case 0x07: /* BEQZC: bits 010000 00111 */
2001 if (regcache_raw_get_signed (regcache
,
2002 b0s5_reg (insn
>> 16)) == 0)
2003 pc
+= micromips_relative_offset16 (insn
);
2006 case 0x14: /* BC2F: bits 010000 10100 xxx00 */
2007 case 0x15: /* BC2T: bits 010000 10101 xxx00 */
2008 if (((insn
>> 16) & 0x3) == 0x0)
2009 /* BC2F, BC2T: don't know how to handle these. */
2013 case 0x1a: /* BPOSGE64: bits 010000 11010 */
2014 case 0x1b: /* BPOSGE32: bits 010000 11011 */
2016 unsigned int pos
= (b5s5_op (insn
>> 16) & 1) ? 32 : 64;
2017 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
2020 /* No way to handle; it'll most likely trap anyway. */
2023 if ((regcache_raw_get_unsigned (regcache
,
2024 dspctl
) & 0x7f) >= pos
)
2025 pc
+= micromips_relative_offset16 (insn
);
2027 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2031 case 0x1c: /* BC1F: bits 010000 11100 xxx00 */
2032 /* BC1ANY2F: bits 010000 11100 xxx01 */
2033 case 0x1d: /* BC1T: bits 010000 11101 xxx00 */
2034 /* BC1ANY2T: bits 010000 11101 xxx01 */
2035 if (((insn
>> 16) & 0x2) == 0x0)
2036 pc
= micromips_bc1_pc (gdbarch
, regcache
, insn
, pc
,
2037 ((insn
>> 16) & 0x1) + 1);
2040 case 0x1e: /* BC1ANY4F: bits 010000 11110 xxx01 */
2041 case 0x1f: /* BC1ANY4T: bits 010000 11111 xxx01 */
2042 if (((insn
>> 16) & 0x3) == 0x1)
2043 pc
= micromips_bc1_pc (gdbarch
, regcache
, insn
, pc
, 4);
2048 case 0x1d: /* JALS: bits 011101 */
2049 case 0x35: /* J: bits 110101 */
2050 case 0x3d: /* JAL: bits 111101 */
2051 pc
= ((pc
| 0x7fffffe) ^ 0x7fffffe) | (b0s26_imm (insn
) << 1);
2054 case 0x25: /* BEQ: bits 100101 */
2055 if (regcache_raw_get_signed (regcache
, b0s5_reg (insn
>> 16))
2056 == regcache_raw_get_signed (regcache
, b5s5_reg (insn
>> 16)))
2057 pc
+= micromips_relative_offset16 (insn
);
2059 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2062 case 0x2d: /* BNE: bits 101101 */
2063 if (regcache_raw_get_signed (regcache
, b0s5_reg (insn
>> 16))
2064 != regcache_raw_get_signed (regcache
, b5s5_reg (insn
>> 16)))
2065 pc
+= micromips_relative_offset16 (insn
);
2067 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2070 case 0x3c: /* JALX: bits 111100 */
2071 pc
= ((pc
| 0xfffffff) ^ 0xfffffff) | (b0s26_imm (insn
) << 2);
2076 /* 16-bit instructions. */
2077 case MIPS_INSN16_SIZE
:
2078 switch (micromips_op (insn
))
2080 case 0x11: /* POOL16C: bits 010001 */
2081 if ((b5s5_op (insn
) & 0x1c) == 0xc)
2082 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
2083 pc
= regcache_raw_get_signed (regcache
, b0s5_reg (insn
));
2084 else if (b5s5_op (insn
) == 0x18)
2085 /* JRADDIUSP: bits 010001 11000 */
2086 pc
= regcache_raw_get_signed (regcache
, MIPS_RA_REGNUM
);
2089 case 0x23: /* BEQZ16: bits 100011 */
2091 int rs
= mips_reg3_to_reg
[b7s3_reg (insn
)];
2093 if (regcache_raw_get_signed (regcache
, rs
) == 0)
2094 pc
+= micromips_relative_offset7 (insn
);
2096 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2100 case 0x2b: /* BNEZ16: bits 101011 */
2102 int rs
= mips_reg3_to_reg
[b7s3_reg (insn
)];
2104 if (regcache_raw_get_signed (regcache
, rs
) != 0)
2105 pc
+= micromips_relative_offset7 (insn
);
2107 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2111 case 0x33: /* B16: bits 110011 */
2112 pc
+= micromips_relative_offset10 (insn
);
2121 /* Decoding the next place to set a breakpoint is irregular for the
2122 mips 16 variant, but fortunately, there fewer instructions. We have
2123 to cope ith extensions for 16 bit instructions and a pair of actual
2124 32 bit instructions. We dont want to set a single step instruction
2125 on the extend instruction either. */
2127 /* Lots of mips16 instruction formats */
2128 /* Predicting jumps requires itype,ritype,i8type
2129 and their extensions extItype,extritype,extI8type. */
2130 enum mips16_inst_fmts
2132 itype
, /* 0 immediate 5,10 */
2133 ritype
, /* 1 5,3,8 */
2134 rrtype
, /* 2 5,3,3,5 */
2135 rritype
, /* 3 5,3,3,5 */
2136 rrrtype
, /* 4 5,3,3,3,2 */
2137 rriatype
, /* 5 5,3,3,1,4 */
2138 shifttype
, /* 6 5,3,3,3,2 */
2139 i8type
, /* 7 5,3,8 */
2140 i8movtype
, /* 8 5,3,3,5 */
2141 i8mov32rtype
, /* 9 5,3,5,3 */
2142 i64type
, /* 10 5,3,8 */
2143 ri64type
, /* 11 5,3,3,5 */
2144 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
2145 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
2146 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
2147 extRRItype
, /* 15 5,5,5,5,3,3,5 */
2148 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
2149 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
2150 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
2151 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
2152 extRi64type
, /* 20 5,6,5,5,3,3,5 */
2153 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
2155 /* I am heaping all the fields of the formats into one structure and
2156 then, only the fields which are involved in instruction extension. */
2160 unsigned int regx
; /* Function in i8 type. */
2165 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
2166 for the bits which make up the immediate extension. */
2169 extended_offset (unsigned int extension
)
2173 value
= (extension
>> 16) & 0x1f; /* Extract 15:11. */
2175 value
|= (extension
>> 21) & 0x3f; /* Extract 10:5. */
2177 value
|= extension
& 0x1f; /* Extract 4:0. */
2182 /* Only call this function if you know that this is an extendable
2183 instruction. It won't malfunction, but why make excess remote memory
2184 references? If the immediate operands get sign extended or something,
2185 do it after the extension is performed. */
2186 /* FIXME: Every one of these cases needs to worry about sign extension
2187 when the offset is to be used in relative addressing. */
2190 fetch_mips_16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2192 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2195 pc
= unmake_compact_addr (pc
); /* Clear the low order bit. */
2196 target_read_memory (pc
, buf
, 2);
2197 return extract_unsigned_integer (buf
, 2, byte_order
);
2201 unpack_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
2202 unsigned int extension
,
2204 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
2209 switch (insn_format
)
2216 value
= extended_offset ((extension
<< 16) | inst
);
2217 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
2221 value
= inst
& 0x7ff;
2222 value
= (value
^ 0x400) - 0x400; /* Sign-extend. */
2231 { /* A register identifier and an offset. */
2232 /* Most of the fields are the same as I type but the
2233 immediate value is of a different length. */
2237 value
= extended_offset ((extension
<< 16) | inst
);
2238 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
2242 value
= inst
& 0xff; /* 8 bits */
2243 value
= (value
^ 0x80) - 0x80; /* Sign-extend. */
2246 regx
= (inst
>> 8) & 0x07; /* i8 funct */
2252 unsigned long value
;
2253 unsigned int nexthalf
;
2254 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
2255 value
= value
<< 16;
2256 nexthalf
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, pc
+ 2, NULL
);
2257 /* Low bit still set. */
2265 internal_error (__FILE__
, __LINE__
, _("bad switch"));
2267 upk
->offset
= offset
;
2273 /* Calculate the destination of a branch whose 16-bit opcode word is at PC,
2274 and having a signed 16-bit OFFSET. */
2277 add_offset_16 (CORE_ADDR pc
, int offset
)
2279 return pc
+ (offset
<< 1) + 2;
2283 extended_mips16_next_pc (regcache
*regcache
, CORE_ADDR pc
,
2284 unsigned int extension
, unsigned int insn
)
2286 struct gdbarch
*gdbarch
= regcache
->arch ();
2287 int op
= (insn
>> 11);
2290 case 2: /* Branch */
2292 struct upk_mips16 upk
;
2293 unpack_mips16 (gdbarch
, pc
, extension
, insn
, itype
, &upk
);
2294 pc
= add_offset_16 (pc
, upk
.offset
);
2297 case 3: /* JAL , JALX - Watch out, these are 32 bit
2300 struct upk_mips16 upk
;
2301 unpack_mips16 (gdbarch
, pc
, extension
, insn
, jalxtype
, &upk
);
2302 pc
= ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)) | (upk
.offset
<< 2);
2303 if ((insn
>> 10) & 0x01) /* Exchange mode */
2304 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode. */
2311 struct upk_mips16 upk
;
2313 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
2314 reg
= regcache_raw_get_signed (regcache
, mips_reg3_to_reg
[upk
.regx
]);
2316 pc
= add_offset_16 (pc
, upk
.offset
);
2323 struct upk_mips16 upk
;
2325 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
2326 reg
= regcache_raw_get_signed (regcache
, mips_reg3_to_reg
[upk
.regx
]);
2328 pc
= add_offset_16 (pc
, upk
.offset
);
2333 case 12: /* I8 Formats btez btnez */
2335 struct upk_mips16 upk
;
2337 unpack_mips16 (gdbarch
, pc
, extension
, insn
, i8type
, &upk
);
2338 /* upk.regx contains the opcode */
2339 /* Test register is 24 */
2340 reg
= regcache_raw_get_signed (regcache
, 24);
2341 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
2342 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
2343 pc
= add_offset_16 (pc
, upk
.offset
);
2348 case 29: /* RR Formats JR, JALR, JALR-RA */
2350 struct upk_mips16 upk
;
2351 /* upk.fmt = rrtype; */
2356 upk
.regx
= (insn
>> 8) & 0x07;
2357 upk
.regy
= (insn
>> 5) & 0x07;
2358 if ((upk
.regy
& 1) == 0)
2359 reg
= mips_reg3_to_reg
[upk
.regx
];
2361 reg
= 31; /* Function return instruction. */
2362 pc
= regcache_raw_get_signed (regcache
, reg
);
2369 /* This is an instruction extension. Fetch the real instruction
2370 (which follows the extension) and decode things based on
2374 pc
= extended_mips16_next_pc (regcache
, pc
, insn
,
2375 fetch_mips_16 (gdbarch
, pc
));
2388 mips16_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
2390 struct gdbarch
*gdbarch
= regcache
->arch ();
2391 unsigned int insn
= fetch_mips_16 (gdbarch
, pc
);
2392 return extended_mips16_next_pc (regcache
, pc
, 0, insn
);
2395 /* The mips_next_pc function supports single_step when the remote
2396 target monitor or stub is not developed enough to do a single_step.
2397 It works by decoding the current instruction and predicting where a
2398 branch will go. This isn't hard because all the data is available.
2399 The MIPS32, MIPS16 and microMIPS variants are quite different. */
2401 mips_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
2403 struct gdbarch
*gdbarch
= regcache
->arch ();
2405 if (mips_pc_is_mips16 (gdbarch
, pc
))
2406 return mips16_next_pc (regcache
, pc
);
2407 else if (mips_pc_is_micromips (gdbarch
, pc
))
2408 return micromips_next_pc (regcache
, pc
);
2410 return mips32_next_pc (regcache
, pc
);
2413 /* Return non-zero if the MIPS16 instruction INSN is a compact branch
2417 mips16_instruction_is_compact_branch (unsigned short insn
)
2419 switch (insn
& 0xf800)
2422 return (insn
& 0x009f) == 0x80; /* JALRC/JRC */
2424 return (insn
& 0x0600) == 0; /* BTNEZ/BTEQZ */
2425 case 0x2800: /* BNEZ */
2426 case 0x2000: /* BEQZ */
2427 case 0x1000: /* B */
2434 /* Return non-zero if the microMIPS instruction INSN is a compact branch
2438 micromips_instruction_is_compact_branch (unsigned short insn
)
2440 switch (micromips_op (insn
))
2442 case 0x11: /* POOL16C: bits 010001 */
2443 return (b5s5_op (insn
) == 0x18
2444 /* JRADDIUSP: bits 010001 11000 */
2445 || b5s5_op (insn
) == 0xd);
2446 /* JRC: bits 010011 01101 */
2447 case 0x10: /* POOL32I: bits 010000 */
2448 return (b5s5_op (insn
) & 0x1d) == 0x5;
2449 /* BEQZC/BNEZC: bits 010000 001x1 */
2455 struct mips_frame_cache
2458 trad_frame_saved_reg
*saved_regs
;
2461 /* Set a register's saved stack address in temp_saved_regs. If an
2462 address has already been set for this register, do nothing; this
2463 way we will only recognize the first save of a given register in a
2466 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
2467 [gdbarch_num_regs .. 2*gdbarch_num_regs).
2468 Strictly speaking, only the second range is used as it is only second
2469 range (the ABI instead of ISA registers) that comes into play when finding
2470 saved registers in a frame. */
2473 set_reg_offset (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
,
2474 int regnum
, CORE_ADDR offset
)
2476 if (this_cache
!= NULL
2477 && this_cache
->saved_regs
[regnum
].is_realreg ()
2478 && this_cache
->saved_regs
[regnum
].realreg () == regnum
)
2480 this_cache
->saved_regs
[regnum
+ 0
2481 * gdbarch_num_regs (gdbarch
)].set_addr (offset
);
2482 this_cache
->saved_regs
[regnum
+ 1
2483 * gdbarch_num_regs (gdbarch
)].set_addr (offset
);
2488 /* Fetch the immediate value from a MIPS16 instruction.
2489 If the previous instruction was an EXTEND, use it to extend
2490 the upper bits of the immediate value. This is a helper function
2491 for mips16_scan_prologue. */
2494 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
2495 unsigned short inst
, /* current instruction */
2496 int nbits
, /* number of bits in imm field */
2497 int scale
, /* scale factor to be applied to imm */
2498 int is_signed
) /* is the imm field signed? */
2502 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
2504 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
2505 if (offset
& 0x8000) /* check for negative extend */
2506 offset
= 0 - (0x10000 - (offset
& 0xffff));
2507 return offset
| (inst
& 0x1f);
2511 int max_imm
= 1 << nbits
;
2512 int mask
= max_imm
- 1;
2513 int sign_bit
= max_imm
>> 1;
2515 offset
= inst
& mask
;
2516 if (is_signed
&& (offset
& sign_bit
))
2517 offset
= 0 - (max_imm
- offset
);
2518 return offset
* scale
;
2523 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
2524 the associated FRAME_CACHE if not null.
2525 Return the address of the first instruction past the prologue. */
2528 mips16_scan_prologue (struct gdbarch
*gdbarch
,
2529 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2530 struct frame_info
*this_frame
,
2531 struct mips_frame_cache
*this_cache
)
2533 int prev_non_prologue_insn
= 0;
2534 int this_non_prologue_insn
;
2535 int non_prologue_insns
= 0;
2538 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer. */
2540 long frame_offset
= 0; /* Size of stack frame. */
2541 long frame_adjust
= 0; /* Offset of FP from SP. */
2542 int frame_reg
= MIPS_SP_REGNUM
;
2543 unsigned short prev_inst
= 0; /* saved copy of previous instruction. */
2544 unsigned inst
= 0; /* current instruction */
2545 unsigned entry_inst
= 0; /* the entry instruction */
2546 unsigned save_inst
= 0; /* the save instruction */
2547 int prev_delay_slot
= 0;
2551 int extend_bytes
= 0;
2552 int prev_extend_bytes
= 0;
2553 CORE_ADDR end_prologue_addr
;
2555 /* Can be called when there's no process, and hence when there's no
2557 if (this_frame
!= NULL
)
2558 sp
= get_frame_register_signed (this_frame
,
2559 gdbarch_num_regs (gdbarch
)
2564 if (limit_pc
> start_pc
+ 200)
2565 limit_pc
= start_pc
+ 200;
2568 /* Permit at most one non-prologue non-control-transfer instruction
2569 in the middle which may have been reordered by the compiler for
2571 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
2573 this_non_prologue_insn
= 0;
2576 /* Save the previous instruction. If it's an EXTEND, we'll extract
2577 the immediate offset extension from it in mips16_get_imm. */
2580 /* Fetch and decode the instruction. */
2581 inst
= (unsigned short) mips_fetch_instruction (gdbarch
, ISA_MIPS16
,
2584 /* Normally we ignore extend instructions. However, if it is
2585 not followed by a valid prologue instruction, then this
2586 instruction is not part of the prologue either. We must
2587 remember in this case to adjust the end_prologue_addr back
2589 if ((inst
& 0xf800) == 0xf000) /* extend */
2591 extend_bytes
= MIPS_INSN16_SIZE
;
2595 prev_extend_bytes
= extend_bytes
;
2598 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2599 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2601 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
2602 if (offset
< 0) /* Negative stack adjustment? */
2603 frame_offset
-= offset
;
2605 /* Exit loop if a positive stack adjustment is found, which
2606 usually means that the stack cleanup code in the function
2607 epilogue is reached. */
2610 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
2612 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2613 reg
= mips_reg3_to_reg
[(inst
& 0x700) >> 8];
2614 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2616 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
2618 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2619 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2620 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2622 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
2624 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2625 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2627 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2629 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
2630 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2632 else if (inst
== 0x673d) /* move $s1, $sp */
2637 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
2639 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2640 frame_addr
= sp
+ offset
;
2642 frame_adjust
= offset
;
2644 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2646 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
2647 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2648 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
2650 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2652 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2653 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2654 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
2656 else if ((inst
& 0xf81f) == 0xe809
2657 && (inst
& 0x700) != 0x700) /* entry */
2658 entry_inst
= inst
; /* Save for later processing. */
2659 else if ((inst
& 0xff80) == 0x6480) /* save */
2661 save_inst
= inst
; /* Save for later processing. */
2662 if (prev_extend_bytes
) /* extend */
2663 save_inst
|= prev_inst
<< 16;
2665 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
2667 /* This instruction is part of the prologue, but we don't
2668 need to do anything special to handle it. */
2670 else if (mips16_instruction_has_delay_slot (inst
, 0))
2671 /* JAL/JALR/JALX/JR */
2673 /* The instruction in the delay slot can be a part
2674 of the prologue, so move forward once more. */
2676 if (mips16_instruction_has_delay_slot (inst
, 1))
2679 prev_extend_bytes
= MIPS_INSN16_SIZE
;
2680 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
2685 this_non_prologue_insn
= 1;
2688 non_prologue_insns
+= this_non_prologue_insn
;
2690 /* A jump or branch, or enough non-prologue insns seen? If so,
2691 then we must have reached the end of the prologue by now. */
2692 if (prev_delay_slot
|| non_prologue_insns
> 1
2693 || mips16_instruction_is_compact_branch (inst
))
2696 prev_non_prologue_insn
= this_non_prologue_insn
;
2697 prev_delay_slot
= in_delay_slot
;
2698 prev_pc
= cur_pc
- prev_extend_bytes
;
2701 /* The entry instruction is typically the first instruction in a function,
2702 and it stores registers at offsets relative to the value of the old SP
2703 (before the prologue). But the value of the sp parameter to this
2704 function is the new SP (after the prologue has been executed). So we
2705 can't calculate those offsets until we've seen the entire prologue,
2706 and can calculate what the old SP must have been. */
2707 if (entry_inst
!= 0)
2709 int areg_count
= (entry_inst
>> 8) & 7;
2710 int sreg_count
= (entry_inst
>> 6) & 3;
2712 /* The entry instruction always subtracts 32 from the SP. */
2715 /* Now we can calculate what the SP must have been at the
2716 start of the function prologue. */
2719 /* Check if a0-a3 were saved in the caller's argument save area. */
2720 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
2722 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2723 offset
+= mips_abi_regsize (gdbarch
);
2726 /* Check if the ra register was pushed on the stack. */
2728 if (entry_inst
& 0x20)
2730 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2731 offset
-= mips_abi_regsize (gdbarch
);
2734 /* Check if the s0 and s1 registers were pushed on the stack. */
2735 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2737 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2738 offset
-= mips_abi_regsize (gdbarch
);
2742 /* The SAVE instruction is similar to ENTRY, except that defined by the
2743 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
2744 size of the frame is specified as an immediate field of instruction
2745 and an extended variation exists which lets additional registers and
2746 frame space to be specified. The instruction always treats registers
2747 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
2748 if (save_inst
!= 0 && mips_abi_regsize (gdbarch
) == 4)
2750 static int args_table
[16] = {
2751 0, 0, 0, 0, 1, 1, 1, 1,
2752 2, 2, 2, 0, 3, 3, 4, -1,
2754 static int astatic_table
[16] = {
2755 0, 1, 2, 3, 0, 1, 2, 3,
2756 0, 1, 2, 4, 0, 1, 0, -1,
2758 int aregs
= (save_inst
>> 16) & 0xf;
2759 int xsregs
= (save_inst
>> 24) & 0x7;
2760 int args
= args_table
[aregs
];
2761 int astatic
= astatic_table
[aregs
];
2766 warning (_("Invalid number of argument registers encoded in SAVE."));
2771 warning (_("Invalid number of static registers encoded in SAVE."));
2775 /* For standard SAVE the frame size of 0 means 128. */
2776 frame_size
= ((save_inst
>> 16) & 0xf0) | (save_inst
& 0xf);
2777 if (frame_size
== 0 && (save_inst
>> 16) == 0)
2780 frame_offset
+= frame_size
;
2782 /* Now we can calculate what the SP must have been at the
2783 start of the function prologue. */
2786 /* Check if A0-A3 were saved in the caller's argument save area. */
2787 for (reg
= MIPS_A0_REGNUM
, offset
= 0; reg
< args
+ 4; reg
++)
2789 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2790 offset
+= mips_abi_regsize (gdbarch
);
2795 /* Check if the RA register was pushed on the stack. */
2796 if (save_inst
& 0x40)
2798 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2799 offset
-= mips_abi_regsize (gdbarch
);
2802 /* Check if the S8 register was pushed on the stack. */
2805 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ offset
);
2806 offset
-= mips_abi_regsize (gdbarch
);
2809 /* Check if S2-S7 were pushed on the stack. */
2810 for (reg
= 18 + xsregs
- 1; reg
> 18 - 1; reg
--)
2812 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2813 offset
-= mips_abi_regsize (gdbarch
);
2816 /* Check if the S1 register was pushed on the stack. */
2817 if (save_inst
& 0x10)
2819 set_reg_offset (gdbarch
, this_cache
, 17, sp
+ offset
);
2820 offset
-= mips_abi_regsize (gdbarch
);
2822 /* Check if the S0 register was pushed on the stack. */
2823 if (save_inst
& 0x20)
2825 set_reg_offset (gdbarch
, this_cache
, 16, sp
+ offset
);
2826 offset
-= mips_abi_regsize (gdbarch
);
2829 /* Check if A0-A3 were pushed on the stack. */
2830 for (reg
= MIPS_A0_REGNUM
+ 3; reg
> MIPS_A0_REGNUM
+ 3 - astatic
; reg
--)
2832 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2833 offset
-= mips_abi_regsize (gdbarch
);
2837 if (this_cache
!= NULL
)
2840 (get_frame_register_signed (this_frame
,
2841 gdbarch_num_regs (gdbarch
) + frame_reg
)
2842 + frame_offset
- frame_adjust
);
2843 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
2844 be able to get rid of the assignment below, evetually. But it's
2845 still needed for now. */
2846 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2847 + mips_regnum (gdbarch
)->pc
]
2848 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
2851 /* Set end_prologue_addr to the address of the instruction immediately
2852 after the last one we scanned. Unless the last one looked like a
2853 non-prologue instruction (and we looked ahead), in which case use
2854 its address instead. */
2855 end_prologue_addr
= (prev_non_prologue_insn
|| prev_delay_slot
2856 ? prev_pc
: cur_pc
- prev_extend_bytes
);
2858 return end_prologue_addr
;
2861 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
2862 Procedures that use the 32-bit instruction set are handled by the
2863 mips_insn32 unwinder. */
2865 static struct mips_frame_cache
*
2866 mips_insn16_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2868 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2869 struct mips_frame_cache
*cache
;
2871 if ((*this_cache
) != NULL
)
2872 return (struct mips_frame_cache
*) (*this_cache
);
2873 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2874 (*this_cache
) = cache
;
2875 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2877 /* Analyze the function prologue. */
2879 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2880 CORE_ADDR start_addr
;
2882 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2883 if (start_addr
== 0)
2884 start_addr
= heuristic_proc_start (gdbarch
, pc
);
2885 /* We can't analyze the prologue if we couldn't find the begining
2887 if (start_addr
== 0)
2890 mips16_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
2891 (struct mips_frame_cache
*) *this_cache
);
2894 /* gdbarch_sp_regnum contains the value and not the address. */
2895 cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2896 + MIPS_SP_REGNUM
].set_value (cache
->base
);
2898 return (struct mips_frame_cache
*) (*this_cache
);
2902 mips_insn16_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2903 struct frame_id
*this_id
)
2905 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2907 /* This marks the outermost frame. */
2908 if (info
->base
== 0)
2910 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2913 static struct value
*
2914 mips_insn16_frame_prev_register (struct frame_info
*this_frame
,
2915 void **this_cache
, int regnum
)
2917 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2919 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2923 mips_insn16_frame_sniffer (const struct frame_unwind
*self
,
2924 struct frame_info
*this_frame
, void **this_cache
)
2926 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2927 CORE_ADDR pc
= get_frame_pc (this_frame
);
2928 if (mips_pc_is_mips16 (gdbarch
, pc
))
2933 static const struct frame_unwind mips_insn16_frame_unwind
=
2935 "mips insn16 prologue",
2937 default_frame_unwind_stop_reason
,
2938 mips_insn16_frame_this_id
,
2939 mips_insn16_frame_prev_register
,
2941 mips_insn16_frame_sniffer
2945 mips_insn16_frame_base_address (struct frame_info
*this_frame
,
2948 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2953 static const struct frame_base mips_insn16_frame_base
=
2955 &mips_insn16_frame_unwind
,
2956 mips_insn16_frame_base_address
,
2957 mips_insn16_frame_base_address
,
2958 mips_insn16_frame_base_address
2961 static const struct frame_base
*
2962 mips_insn16_frame_base_sniffer (struct frame_info
*this_frame
)
2964 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2965 CORE_ADDR pc
= get_frame_pc (this_frame
);
2966 if (mips_pc_is_mips16 (gdbarch
, pc
))
2967 return &mips_insn16_frame_base
;
2972 /* Decode a 9-bit signed immediate argument of ADDIUSP -- -2 is mapped
2973 to -258, -1 -- to -257, 0 -- to 256, 1 -- to 257 and other values are
2974 interpreted directly, and then multiplied by 4. */
2977 micromips_decode_imm9 (int imm
)
2979 imm
= (imm
^ 0x100) - 0x100;
2980 if (imm
> -3 && imm
< 2)
2985 /* Analyze the function prologue from START_PC to LIMIT_PC. Return
2986 the address of the first instruction past the prologue. */
2989 micromips_scan_prologue (struct gdbarch
*gdbarch
,
2990 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2991 struct frame_info
*this_frame
,
2992 struct mips_frame_cache
*this_cache
)
2994 CORE_ADDR end_prologue_addr
;
2995 int prev_non_prologue_insn
= 0;
2996 int frame_reg
= MIPS_SP_REGNUM
;
2997 int this_non_prologue_insn
;
2998 int non_prologue_insns
= 0;
2999 long frame_offset
= 0; /* Size of stack frame. */
3000 long frame_adjust
= 0; /* Offset of FP from SP. */
3001 int prev_delay_slot
= 0;
3005 ULONGEST insn
; /* current instruction */
3009 long v1_off
= 0; /* The assumption is LUI will replace it. */
3020 /* Can be called when there's no process, and hence when there's no
3022 if (this_frame
!= NULL
)
3023 sp
= get_frame_register_signed (this_frame
,
3024 gdbarch_num_regs (gdbarch
)
3029 if (limit_pc
> start_pc
+ 200)
3030 limit_pc
= start_pc
+ 200;
3033 /* Permit at most one non-prologue non-control-transfer instruction
3034 in the middle which may have been reordered by the compiler for
3036 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= loc
)
3038 this_non_prologue_insn
= 0;
3042 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, cur_pc
, NULL
);
3043 loc
+= MIPS_INSN16_SIZE
;
3044 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
3046 /* 32-bit instructions. */
3047 case 2 * MIPS_INSN16_SIZE
:
3049 insn
|= mips_fetch_instruction (gdbarch
,
3050 ISA_MICROMIPS
, cur_pc
+ loc
, NULL
);
3051 loc
+= MIPS_INSN16_SIZE
;
3052 switch (micromips_op (insn
>> 16))
3054 /* Record $sp/$fp adjustment. */
3055 /* Discard (D)ADDU $gp,$jp used for PIC code. */
3056 case 0x0: /* POOL32A: bits 000000 */
3057 case 0x16: /* POOL32S: bits 010110 */
3058 op
= b0s11_op (insn
);
3059 sreg
= b0s5_reg (insn
>> 16);
3060 treg
= b5s5_reg (insn
>> 16);
3061 dreg
= b11s5_reg (insn
);
3063 /* SUBU: bits 000000 00111010000 */
3064 /* DSUBU: bits 010110 00111010000 */
3065 && dreg
== MIPS_SP_REGNUM
&& sreg
== MIPS_SP_REGNUM
3067 /* (D)SUBU $sp, $v1 */
3069 else if (op
!= 0x150
3070 /* ADDU: bits 000000 00101010000 */
3071 /* DADDU: bits 010110 00101010000 */
3072 || dreg
!= 28 || sreg
!= 28 || treg
!= MIPS_T9_REGNUM
)
3073 this_non_prologue_insn
= 1;
3076 case 0x8: /* POOL32B: bits 001000 */
3077 op
= b12s4_op (insn
);
3078 breg
= b0s5_reg (insn
>> 16);
3079 reglist
= sreg
= b5s5_reg (insn
>> 16);
3080 offset
= (b0s12_imm (insn
) ^ 0x800) - 0x800;
3081 if ((op
== 0x9 || op
== 0xc)
3082 /* SWP: bits 001000 1001 */
3083 /* SDP: bits 001000 1100 */
3084 && breg
== MIPS_SP_REGNUM
&& sreg
< MIPS_RA_REGNUM
)
3085 /* S[DW]P reg,offset($sp) */
3087 s
= 4 << ((b12s4_op (insn
) & 0x4) == 0x4);
3088 set_reg_offset (gdbarch
, this_cache
,
3090 set_reg_offset (gdbarch
, this_cache
,
3091 sreg
+ 1, sp
+ offset
+ s
);
3093 else if ((op
== 0xd || op
== 0xf)
3094 /* SWM: bits 001000 1101 */
3095 /* SDM: bits 001000 1111 */
3096 && breg
== MIPS_SP_REGNUM
3097 /* SWM reglist,offset($sp) */
3098 && ((reglist
>= 1 && reglist
<= 9)
3099 || (reglist
>= 16 && reglist
<= 25)))
3101 int sreglist
= std::min(reglist
& 0xf, 8);
3103 s
= 4 << ((b12s4_op (insn
) & 0x2) == 0x2);
3104 for (i
= 0; i
< sreglist
; i
++)
3105 set_reg_offset (gdbarch
, this_cache
, 16 + i
, sp
+ s
* i
);
3106 if ((reglist
& 0xf) > 8)
3107 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ s
* i
++);
3108 if ((reglist
& 0x10) == 0x10)
3109 set_reg_offset (gdbarch
, this_cache
,
3110 MIPS_RA_REGNUM
, sp
+ s
* i
++);
3113 this_non_prologue_insn
= 1;
3116 /* Record $sp/$fp adjustment. */
3117 /* Discard (D)ADDIU $gp used for PIC code. */
3118 case 0xc: /* ADDIU: bits 001100 */
3119 case 0x17: /* DADDIU: bits 010111 */
3120 sreg
= b0s5_reg (insn
>> 16);
3121 dreg
= b5s5_reg (insn
>> 16);
3122 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
3123 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
)
3124 /* (D)ADDIU $sp, imm */
3126 else if (sreg
== MIPS_SP_REGNUM
&& dreg
== 30)
3127 /* (D)ADDIU $fp, $sp, imm */
3129 frame_adjust
= offset
;
3132 else if (sreg
!= 28 || dreg
!= 28)
3133 /* (D)ADDIU $gp, imm */
3134 this_non_prologue_insn
= 1;
3137 /* LUI $v1 is used for larger $sp adjustments. */
3138 /* Discard LUI $gp used for PIC code. */
3139 case 0x10: /* POOL32I: bits 010000 */
3140 if (b5s5_op (insn
>> 16) == 0xd
3141 /* LUI: bits 010000 001101 */
3142 && b0s5_reg (insn
>> 16) == 3)
3144 v1_off
= ((b0s16_imm (insn
) << 16) ^ 0x80000000) - 0x80000000;
3145 else if (b5s5_op (insn
>> 16) != 0xd
3146 /* LUI: bits 010000 001101 */
3147 || b0s5_reg (insn
>> 16) != 28)
3149 this_non_prologue_insn
= 1;
3152 /* ORI $v1 is used for larger $sp adjustments. */
3153 case 0x14: /* ORI: bits 010100 */
3154 sreg
= b0s5_reg (insn
>> 16);
3155 dreg
= b5s5_reg (insn
>> 16);
3156 if (sreg
== 3 && dreg
== 3)
3158 v1_off
|= b0s16_imm (insn
);
3160 this_non_prologue_insn
= 1;
3163 case 0x26: /* SWC1: bits 100110 */
3164 case 0x2e: /* SDC1: bits 101110 */
3165 breg
= b0s5_reg (insn
>> 16);
3166 if (breg
!= MIPS_SP_REGNUM
)
3167 /* S[DW]C1 reg,offset($sp) */
3168 this_non_prologue_insn
= 1;
3171 case 0x36: /* SD: bits 110110 */
3172 case 0x3e: /* SW: bits 111110 */
3173 breg
= b0s5_reg (insn
>> 16);
3174 sreg
= b5s5_reg (insn
>> 16);
3175 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
3176 if (breg
== MIPS_SP_REGNUM
)
3177 /* S[DW] reg,offset($sp) */
3178 set_reg_offset (gdbarch
, this_cache
, sreg
, sp
+ offset
);
3180 this_non_prologue_insn
= 1;
3184 /* The instruction in the delay slot can be a part
3185 of the prologue, so move forward once more. */
3186 if (micromips_instruction_has_delay_slot (insn
, 0))
3189 this_non_prologue_insn
= 1;
3195 /* 16-bit instructions. */
3196 case MIPS_INSN16_SIZE
:
3197 switch (micromips_op (insn
))
3199 case 0x3: /* MOVE: bits 000011 */
3200 sreg
= b0s5_reg (insn
);
3201 dreg
= b5s5_reg (insn
);
3202 if (sreg
== MIPS_SP_REGNUM
&& dreg
== 30)
3205 else if ((sreg
& 0x1c) != 0x4)
3206 /* MOVE reg, $a0-$a3 */
3207 this_non_prologue_insn
= 1;
3210 case 0x11: /* POOL16C: bits 010001 */
3211 if (b6s4_op (insn
) == 0x5)
3212 /* SWM: bits 010001 0101 */
3214 offset
= ((b0s4_imm (insn
) << 2) ^ 0x20) - 0x20;
3215 reglist
= b4s2_regl (insn
);
3216 for (i
= 0; i
<= reglist
; i
++)
3217 set_reg_offset (gdbarch
, this_cache
, 16 + i
, sp
+ 4 * i
);
3218 set_reg_offset (gdbarch
, this_cache
,
3219 MIPS_RA_REGNUM
, sp
+ 4 * i
++);
3222 this_non_prologue_insn
= 1;
3225 case 0x13: /* POOL16D: bits 010011 */
3226 if ((insn
& 0x1) == 0x1)
3227 /* ADDIUSP: bits 010011 1 */
3228 sp_adj
= micromips_decode_imm9 (b1s9_imm (insn
));
3229 else if (b5s5_reg (insn
) == MIPS_SP_REGNUM
)
3230 /* ADDIUS5: bits 010011 0 */
3231 /* ADDIUS5 $sp, imm */
3232 sp_adj
= (b1s4_imm (insn
) ^ 8) - 8;
3234 this_non_prologue_insn
= 1;
3237 case 0x32: /* SWSP: bits 110010 */
3238 offset
= b0s5_imm (insn
) << 2;
3239 sreg
= b5s5_reg (insn
);
3240 set_reg_offset (gdbarch
, this_cache
, sreg
, sp
+ offset
);
3244 /* The instruction in the delay slot can be a part
3245 of the prologue, so move forward once more. */
3246 if (micromips_instruction_has_delay_slot (insn
<< 16, 0))
3249 this_non_prologue_insn
= 1;
3255 frame_offset
-= sp_adj
;
3257 non_prologue_insns
+= this_non_prologue_insn
;
3259 /* A jump or branch, enough non-prologue insns seen or positive
3260 stack adjustment? If so, then we must have reached the end
3261 of the prologue by now. */
3262 if (prev_delay_slot
|| non_prologue_insns
> 1 || sp_adj
> 0
3263 || micromips_instruction_is_compact_branch (insn
))
3266 prev_non_prologue_insn
= this_non_prologue_insn
;
3267 prev_delay_slot
= in_delay_slot
;
3271 if (this_cache
!= NULL
)
3274 (get_frame_register_signed (this_frame
,
3275 gdbarch_num_regs (gdbarch
) + frame_reg
)
3276 + frame_offset
- frame_adjust
);
3277 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
3278 be able to get rid of the assignment below, evetually. But it's
3279 still needed for now. */
3280 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3281 + mips_regnum (gdbarch
)->pc
]
3282 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
3285 /* Set end_prologue_addr to the address of the instruction immediately
3286 after the last one we scanned. Unless the last one looked like a
3287 non-prologue instruction (and we looked ahead), in which case use
3288 its address instead. */
3290 = prev_non_prologue_insn
|| prev_delay_slot
? prev_pc
: cur_pc
;
3292 return end_prologue_addr
;
3295 /* Heuristic unwinder for procedures using microMIPS instructions.
3296 Procedures that use the 32-bit instruction set are handled by the
3297 mips_insn32 unwinder. Likewise MIPS16 and the mips_insn16 unwinder. */
3299 static struct mips_frame_cache
*
3300 mips_micro_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3302 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3303 struct mips_frame_cache
*cache
;
3305 if ((*this_cache
) != NULL
)
3306 return (struct mips_frame_cache
*) (*this_cache
);
3308 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
3309 (*this_cache
) = cache
;
3310 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3312 /* Analyze the function prologue. */
3314 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3315 CORE_ADDR start_addr
;
3317 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3318 if (start_addr
== 0)
3319 start_addr
= heuristic_proc_start (get_frame_arch (this_frame
), pc
);
3320 /* We can't analyze the prologue if we couldn't find the begining
3322 if (start_addr
== 0)
3325 micromips_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
3326 (struct mips_frame_cache
*) *this_cache
);
3329 /* gdbarch_sp_regnum contains the value and not the address. */
3330 cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3331 + MIPS_SP_REGNUM
].set_value (cache
->base
);
3333 return (struct mips_frame_cache
*) (*this_cache
);
3337 mips_micro_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3338 struct frame_id
*this_id
)
3340 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3342 /* This marks the outermost frame. */
3343 if (info
->base
== 0)
3345 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3348 static struct value
*
3349 mips_micro_frame_prev_register (struct frame_info
*this_frame
,
3350 void **this_cache
, int regnum
)
3352 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3354 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3358 mips_micro_frame_sniffer (const struct frame_unwind
*self
,
3359 struct frame_info
*this_frame
, void **this_cache
)
3361 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3362 CORE_ADDR pc
= get_frame_pc (this_frame
);
3364 if (mips_pc_is_micromips (gdbarch
, pc
))
3369 static const struct frame_unwind mips_micro_frame_unwind
=
3371 "mips micro prologue",
3373 default_frame_unwind_stop_reason
,
3374 mips_micro_frame_this_id
,
3375 mips_micro_frame_prev_register
,
3377 mips_micro_frame_sniffer
3381 mips_micro_frame_base_address (struct frame_info
*this_frame
,
3384 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3389 static const struct frame_base mips_micro_frame_base
=
3391 &mips_micro_frame_unwind
,
3392 mips_micro_frame_base_address
,
3393 mips_micro_frame_base_address
,
3394 mips_micro_frame_base_address
3397 static const struct frame_base
*
3398 mips_micro_frame_base_sniffer (struct frame_info
*this_frame
)
3400 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3401 CORE_ADDR pc
= get_frame_pc (this_frame
);
3403 if (mips_pc_is_micromips (gdbarch
, pc
))
3404 return &mips_micro_frame_base
;
3409 /* Mark all the registers as unset in the saved_regs array
3410 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
3413 reset_saved_regs (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
)
3415 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
3419 const int num_regs
= gdbarch_num_regs (gdbarch
);
3422 /* Reset the register values to their default state. Register i's value
3423 is in register i. */
3424 for (i
= 0; i
< num_regs
; i
++)
3425 this_cache
->saved_regs
[i
].set_realreg (i
);
3429 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
3430 the associated FRAME_CACHE if not null.
3431 Return the address of the first instruction past the prologue. */
3434 mips32_scan_prologue (struct gdbarch
*gdbarch
,
3435 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
3436 struct frame_info
*this_frame
,
3437 struct mips_frame_cache
*this_cache
)
3439 int prev_non_prologue_insn
;
3440 int this_non_prologue_insn
;
3441 int non_prologue_insns
;
3442 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for
3444 int prev_delay_slot
;
3449 int frame_reg
= MIPS_SP_REGNUM
;
3451 CORE_ADDR end_prologue_addr
;
3452 int seen_sp_adjust
= 0;
3453 int load_immediate_bytes
= 0;
3455 int regsize_is_64_bits
= (mips_abi_regsize (gdbarch
) == 8);
3457 /* Can be called when there's no process, and hence when there's no
3459 if (this_frame
!= NULL
)
3460 sp
= get_frame_register_signed (this_frame
,
3461 gdbarch_num_regs (gdbarch
)
3466 if (limit_pc
> start_pc
+ 200)
3467 limit_pc
= start_pc
+ 200;
3470 prev_non_prologue_insn
= 0;
3471 non_prologue_insns
= 0;
3472 prev_delay_slot
= 0;
3475 /* Permit at most one non-prologue non-control-transfer instruction
3476 in the middle which may have been reordered by the compiler for
3479 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
3481 unsigned long inst
, high_word
;
3485 this_non_prologue_insn
= 0;
3488 /* Fetch the instruction. */
3489 inst
= (unsigned long) mips_fetch_instruction (gdbarch
, ISA_MIPS
,
3492 /* Save some code by pre-extracting some useful fields. */
3493 high_word
= (inst
>> 16) & 0xffff;
3494 offset
= ((inst
& 0xffff) ^ 0x8000) - 0x8000;
3495 reg
= high_word
& 0x1f;
3497 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
3498 || high_word
== 0x23bd /* addi $sp,$sp,-i */
3499 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
3501 if (offset
< 0) /* Negative stack adjustment? */
3502 frame_offset
-= offset
;
3504 /* Exit loop if a positive stack adjustment is found, which
3505 usually means that the stack cleanup code in the function
3506 epilogue is reached. */
3510 else if (((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
3511 && !regsize_is_64_bits
)
3513 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
3515 else if (((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
3516 && regsize_is_64_bits
)
3518 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
3519 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
3521 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
3523 /* Old gcc frame, r30 is virtual frame pointer. */
3524 if (offset
!= frame_offset
)
3525 frame_addr
= sp
+ offset
;
3526 else if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
3528 unsigned alloca_adjust
;
3531 frame_addr
= get_frame_register_signed
3532 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
3535 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ offset
));
3536 if (alloca_adjust
> 0)
3538 /* FP > SP + frame_size. This may be because of
3539 an alloca or somethings similar. Fix sp to
3540 "pre-alloca" value, and try again. */
3541 sp
+= alloca_adjust
;
3542 /* Need to reset the status of all registers. Otherwise,
3543 we will hit a guard that prevents the new address
3544 for each register to be recomputed during the second
3546 reset_saved_regs (gdbarch
, this_cache
);
3551 /* move $30,$sp. With different versions of gas this will be either
3552 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
3553 Accept any one of these. */
3554 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
3556 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
3557 if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
3559 unsigned alloca_adjust
;
3562 frame_addr
= get_frame_register_signed
3563 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
3565 alloca_adjust
= (unsigned) (frame_addr
- sp
);
3566 if (alloca_adjust
> 0)
3568 /* FP > SP + frame_size. This may be because of
3569 an alloca or somethings similar. Fix sp to
3570 "pre-alloca" value, and try again. */
3572 /* Need to reset the status of all registers. Otherwise,
3573 we will hit a guard that prevents the new address
3574 for each register to be recomputed during the second
3576 reset_saved_regs (gdbarch
, this_cache
);
3581 else if ((high_word
& 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
3582 && !regsize_is_64_bits
)
3584 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
3586 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
3587 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
3588 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
3589 || high_word
== 0x3c1c /* lui $gp,n */
3590 || high_word
== 0x279c /* addiu $gp,$gp,n */
3591 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
3592 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
3595 /* These instructions are part of the prologue, but we don't
3596 need to do anything special to handle them. */
3598 /* The instructions below load $at or $t0 with an immediate
3599 value in preparation for a stack adjustment via
3600 subu $sp,$sp,[$at,$t0]. These instructions could also
3601 initialize a local variable, so we accept them only before
3602 a stack adjustment instruction was seen. */
3603 else if (!seen_sp_adjust
3605 && (high_word
== 0x3c01 /* lui $at,n */
3606 || high_word
== 0x3c08 /* lui $t0,n */
3607 || high_word
== 0x3421 /* ori $at,$at,n */
3608 || high_word
== 0x3508 /* ori $t0,$t0,n */
3609 || high_word
== 0x3401 /* ori $at,$zero,n */
3610 || high_word
== 0x3408 /* ori $t0,$zero,n */
3613 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
3615 /* Check for branches and jumps. The instruction in the delay
3616 slot can be a part of the prologue, so move forward once more. */
3617 else if (mips32_instruction_has_delay_slot (gdbarch
, inst
))
3621 /* This instruction is not an instruction typically found
3622 in a prologue, so we must have reached the end of the
3626 this_non_prologue_insn
= 1;
3629 non_prologue_insns
+= this_non_prologue_insn
;
3631 /* A jump or branch, or enough non-prologue insns seen? If so,
3632 then we must have reached the end of the prologue by now. */
3633 if (prev_delay_slot
|| non_prologue_insns
> 1)
3636 prev_non_prologue_insn
= this_non_prologue_insn
;
3637 prev_delay_slot
= in_delay_slot
;
3641 if (this_cache
!= NULL
)
3644 (get_frame_register_signed (this_frame
,
3645 gdbarch_num_regs (gdbarch
) + frame_reg
)
3647 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
3648 this assignment below, eventually. But it's still needed
3650 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3651 + mips_regnum (gdbarch
)->pc
]
3652 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3656 /* Set end_prologue_addr to the address of the instruction immediately
3657 after the last one we scanned. Unless the last one looked like a
3658 non-prologue instruction (and we looked ahead), in which case use
3659 its address instead. */
3661 = prev_non_prologue_insn
|| prev_delay_slot
? prev_pc
: cur_pc
;
3663 /* In a frameless function, we might have incorrectly
3664 skipped some load immediate instructions. Undo the skipping
3665 if the load immediate was not followed by a stack adjustment. */
3666 if (load_immediate_bytes
&& !seen_sp_adjust
)
3667 end_prologue_addr
-= load_immediate_bytes
;
3669 return end_prologue_addr
;
3672 /* Heuristic unwinder for procedures using 32-bit instructions (covers
3673 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
3674 instructions (a.k.a. MIPS16) are handled by the mips_insn16
3675 unwinder. Likewise microMIPS and the mips_micro unwinder. */
3677 static struct mips_frame_cache
*
3678 mips_insn32_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3680 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3681 struct mips_frame_cache
*cache
;
3683 if ((*this_cache
) != NULL
)
3684 return (struct mips_frame_cache
*) (*this_cache
);
3686 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
3687 (*this_cache
) = cache
;
3688 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3690 /* Analyze the function prologue. */
3692 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3693 CORE_ADDR start_addr
;
3695 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3696 if (start_addr
== 0)
3697 start_addr
= heuristic_proc_start (gdbarch
, pc
);
3698 /* We can't analyze the prologue if we couldn't find the begining
3700 if (start_addr
== 0)
3703 mips32_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
3704 (struct mips_frame_cache
*) *this_cache
);
3707 /* gdbarch_sp_regnum contains the value and not the address. */
3708 cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3709 + MIPS_SP_REGNUM
].set_value (cache
->base
);
3711 return (struct mips_frame_cache
*) (*this_cache
);
3715 mips_insn32_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3716 struct frame_id
*this_id
)
3718 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3720 /* This marks the outermost frame. */
3721 if (info
->base
== 0)
3723 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3726 static struct value
*
3727 mips_insn32_frame_prev_register (struct frame_info
*this_frame
,
3728 void **this_cache
, int regnum
)
3730 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3732 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3736 mips_insn32_frame_sniffer (const struct frame_unwind
*self
,
3737 struct frame_info
*this_frame
, void **this_cache
)
3739 CORE_ADDR pc
= get_frame_pc (this_frame
);
3740 if (mips_pc_is_mips (pc
))
3745 static const struct frame_unwind mips_insn32_frame_unwind
=
3747 "mips insn32 prologue",
3749 default_frame_unwind_stop_reason
,
3750 mips_insn32_frame_this_id
,
3751 mips_insn32_frame_prev_register
,
3753 mips_insn32_frame_sniffer
3757 mips_insn32_frame_base_address (struct frame_info
*this_frame
,
3760 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3765 static const struct frame_base mips_insn32_frame_base
=
3767 &mips_insn32_frame_unwind
,
3768 mips_insn32_frame_base_address
,
3769 mips_insn32_frame_base_address
,
3770 mips_insn32_frame_base_address
3773 static const struct frame_base
*
3774 mips_insn32_frame_base_sniffer (struct frame_info
*this_frame
)
3776 CORE_ADDR pc
= get_frame_pc (this_frame
);
3777 if (mips_pc_is_mips (pc
))
3778 return &mips_insn32_frame_base
;
3783 static struct trad_frame_cache
*
3784 mips_stub_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3787 CORE_ADDR start_addr
;
3788 CORE_ADDR stack_addr
;
3789 struct trad_frame_cache
*this_trad_cache
;
3790 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3791 int num_regs
= gdbarch_num_regs (gdbarch
);
3793 if ((*this_cache
) != NULL
)
3794 return (struct trad_frame_cache
*) (*this_cache
);
3795 this_trad_cache
= trad_frame_cache_zalloc (this_frame
);
3796 (*this_cache
) = this_trad_cache
;
3798 /* The return address is in the link register. */
3799 trad_frame_set_reg_realreg (this_trad_cache
,
3800 gdbarch_pc_regnum (gdbarch
),
3801 num_regs
+ MIPS_RA_REGNUM
);
3803 /* Frame ID, since it's a frameless / stackless function, no stack
3804 space is allocated and SP on entry is the current SP. */
3805 pc
= get_frame_pc (this_frame
);
3806 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3807 stack_addr
= get_frame_register_signed (this_frame
,
3808 num_regs
+ MIPS_SP_REGNUM
);
3809 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
3811 /* Assume that the frame's base is the same as the
3813 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
3815 return this_trad_cache
;
3819 mips_stub_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3820 struct frame_id
*this_id
)
3822 struct trad_frame_cache
*this_trad_cache
3823 = mips_stub_frame_cache (this_frame
, this_cache
);
3824 trad_frame_get_id (this_trad_cache
, this_id
);
3827 static struct value
*
3828 mips_stub_frame_prev_register (struct frame_info
*this_frame
,
3829 void **this_cache
, int regnum
)
3831 struct trad_frame_cache
*this_trad_cache
3832 = mips_stub_frame_cache (this_frame
, this_cache
);
3833 return trad_frame_get_register (this_trad_cache
, this_frame
, regnum
);
3837 mips_stub_frame_sniffer (const struct frame_unwind
*self
,
3838 struct frame_info
*this_frame
, void **this_cache
)
3841 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3842 struct bound_minimal_symbol msym
;
3844 /* Use the stub unwinder for unreadable code. */
3845 if (target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
3848 if (in_plt_section (pc
) || in_mips_stubs_section (pc
))
3851 /* Calling a PIC function from a non-PIC function passes through a
3852 stub. The stub for foo is named ".pic.foo". */
3853 msym
= lookup_minimal_symbol_by_pc (pc
);
3854 if (msym
.minsym
!= NULL
3855 && msym
.minsym
->linkage_name () != NULL
3856 && startswith (msym
.minsym
->linkage_name (), ".pic."))
3862 static const struct frame_unwind mips_stub_frame_unwind
=
3866 default_frame_unwind_stop_reason
,
3867 mips_stub_frame_this_id
,
3868 mips_stub_frame_prev_register
,
3870 mips_stub_frame_sniffer
3874 mips_stub_frame_base_address (struct frame_info
*this_frame
,
3877 struct trad_frame_cache
*this_trad_cache
3878 = mips_stub_frame_cache (this_frame
, this_cache
);
3879 return trad_frame_get_this_base (this_trad_cache
);
3882 static const struct frame_base mips_stub_frame_base
=
3884 &mips_stub_frame_unwind
,
3885 mips_stub_frame_base_address
,
3886 mips_stub_frame_base_address
,
3887 mips_stub_frame_base_address
3890 static const struct frame_base
*
3891 mips_stub_frame_base_sniffer (struct frame_info
*this_frame
)
3893 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind
, this_frame
, NULL
))
3894 return &mips_stub_frame_base
;
3899 /* mips_addr_bits_remove - remove useless address bits */
3902 mips_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
3904 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
3906 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
3907 /* This hack is a work-around for existing boards using PMON, the
3908 simulator, and any other 64-bit targets that doesn't have true
3909 64-bit addressing. On these targets, the upper 32 bits of
3910 addresses are ignored by the hardware. Thus, the PC or SP are
3911 likely to have been sign extended to all 1s by instruction
3912 sequences that load 32-bit addresses. For example, a typical
3913 piece of code that loads an address is this:
3915 lui $r2, <upper 16 bits>
3916 ori $r2, <lower 16 bits>
3918 But the lui sign-extends the value such that the upper 32 bits
3919 may be all 1s. The workaround is simply to mask off these
3920 bits. In the future, gcc may be changed to support true 64-bit
3921 addressing, and this masking will have to be disabled. */
3922 return addr
&= 0xffffffffUL
;
3928 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
3929 instruction and ending with a SC/SCD instruction. If such a sequence
3930 is found, attempt to step through it. A breakpoint is placed at the end of
3933 /* Instructions used during single-stepping of atomic sequences, standard
3935 #define LL_OPCODE 0x30
3936 #define LLD_OPCODE 0x34
3937 #define SC_OPCODE 0x38
3938 #define SCD_OPCODE 0x3c
3940 static std::vector
<CORE_ADDR
>
3941 mips_deal_with_atomic_sequence (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3943 CORE_ADDR breaks
[2] = {CORE_ADDR_MAX
, CORE_ADDR_MAX
};
3945 CORE_ADDR branch_bp
; /* Breakpoint at branch instruction's destination. */
3949 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
3950 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
3952 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, loc
, NULL
);
3953 /* Assume all atomic sequences start with a ll/lld instruction. */
3954 if (itype_op (insn
) != LL_OPCODE
&& itype_op (insn
) != LLD_OPCODE
)
3957 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
3959 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
3962 loc
+= MIPS_INSN32_SIZE
;
3963 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, loc
, NULL
);
3965 /* Assume that there is at most one branch in the atomic
3966 sequence. If a branch is found, put a breakpoint in its
3967 destination address. */
3968 switch (itype_op (insn
))
3970 case 0: /* SPECIAL */
3971 if (rtype_funct (insn
) >> 1 == 4) /* JR, JALR */
3972 return {}; /* fallback to the standard single-step code. */
3974 case 1: /* REGIMM */
3975 is_branch
= ((itype_rt (insn
) & 0xc) == 0 /* B{LT,GE}Z* */
3976 || ((itype_rt (insn
) & 0x1e) == 0
3977 && itype_rs (insn
) == 0)); /* BPOSGE* */
3981 return {}; /* fallback to the standard single-step code. */
3988 case 22: /* BLEZL */
3989 case 23: /* BGTTL */
3993 is_branch
= ((itype_rs (insn
) == 9 || itype_rs (insn
) == 10)
3994 && (itype_rt (insn
) & 0x2) == 0);
3995 if (is_branch
) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */
4000 is_branch
= (itype_rs (insn
) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
4005 branch_bp
= loc
+ mips32_relative_offset (insn
) + 4;
4006 if (last_breakpoint
>= 1)
4007 return {}; /* More than one branch found, fallback to the
4008 standard single-step code. */
4009 breaks
[1] = branch_bp
;
4013 if (itype_op (insn
) == SC_OPCODE
|| itype_op (insn
) == SCD_OPCODE
)
4017 /* Assume that the atomic sequence ends with a sc/scd instruction. */
4018 if (itype_op (insn
) != SC_OPCODE
&& itype_op (insn
) != SCD_OPCODE
)
4021 loc
+= MIPS_INSN32_SIZE
;
4023 /* Insert a breakpoint right after the end of the atomic sequence. */
4026 /* Check for duplicated breakpoints. Check also for a breakpoint
4027 placed (branch instruction's destination) in the atomic sequence. */
4028 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
4029 last_breakpoint
= 0;
4031 std::vector
<CORE_ADDR
> next_pcs
;
4033 /* Effectively inserts the breakpoints. */
4034 for (index
= 0; index
<= last_breakpoint
; index
++)
4035 next_pcs
.push_back (breaks
[index
]);
4040 static std::vector
<CORE_ADDR
>
4041 micromips_deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
4044 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
4045 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
4046 CORE_ADDR breaks
[2] = {CORE_ADDR_MAX
, CORE_ADDR_MAX
};
4047 CORE_ADDR branch_bp
= 0; /* Breakpoint at branch instruction's
4055 /* Assume all atomic sequences start with a ll/lld instruction. */
4056 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
4057 if (micromips_op (insn
) != 0x18) /* POOL32C: bits 011000 */
4059 loc
+= MIPS_INSN16_SIZE
;
4061 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
4062 if ((b12s4_op (insn
) & 0xb) != 0x3) /* LL, LLD: bits 011000 0x11 */
4064 loc
+= MIPS_INSN16_SIZE
;
4066 /* Assume all atomic sequences end with an sc/scd instruction. Assume
4067 that no atomic sequence is longer than "atomic_sequence_length"
4069 for (insn_count
= 0;
4070 !sc_found
&& insn_count
< atomic_sequence_length
;
4075 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
4076 loc
+= MIPS_INSN16_SIZE
;
4078 /* Assume that there is at most one conditional branch in the
4079 atomic sequence. If a branch is found, put a breakpoint in
4080 its destination address. */
4081 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
4083 /* 32-bit instructions. */
4084 case 2 * MIPS_INSN16_SIZE
:
4085 switch (micromips_op (insn
))
4087 case 0x10: /* POOL32I: bits 010000 */
4088 if ((b5s5_op (insn
) & 0x18) != 0x0
4089 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
4090 /* BLEZ, BNEZC, BGTZ, BEQZC: 010000 001xx */
4091 && (b5s5_op (insn
) & 0x1d) != 0x11
4092 /* BLTZALS, BGEZALS: bits 010000 100x1 */
4093 && ((b5s5_op (insn
) & 0x1e) != 0x14
4094 || (insn
& 0x3) != 0x0)
4095 /* BC2F, BC2T: bits 010000 1010x xxx00 */
4096 && (b5s5_op (insn
) & 0x1e) != 0x1a
4097 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
4098 && ((b5s5_op (insn
) & 0x1e) != 0x1c
4099 || (insn
& 0x3) != 0x0)
4100 /* BC1F, BC1T: bits 010000 1110x xxx00 */
4101 && ((b5s5_op (insn
) & 0x1c) != 0x1c
4102 || (insn
& 0x3) != 0x1))
4103 /* BC1ANY*: bits 010000 111xx xxx01 */
4107 case 0x25: /* BEQ: bits 100101 */
4108 case 0x2d: /* BNE: bits 101101 */
4110 insn
|= mips_fetch_instruction (gdbarch
,
4111 ISA_MICROMIPS
, loc
, NULL
);
4112 branch_bp
= (loc
+ MIPS_INSN16_SIZE
4113 + micromips_relative_offset16 (insn
));
4117 case 0x00: /* POOL32A: bits 000000 */
4119 insn
|= mips_fetch_instruction (gdbarch
,
4120 ISA_MICROMIPS
, loc
, NULL
);
4121 if (b0s6_op (insn
) != 0x3c
4122 /* POOL32Axf: bits 000000 ... 111100 */
4123 || (b6s10_ext (insn
) & 0x2bf) != 0x3c)
4124 /* JALR, JALR.HB: 000000 000x111100 111100 */
4125 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
4129 case 0x1d: /* JALS: bits 011101 */
4130 case 0x35: /* J: bits 110101 */
4131 case 0x3d: /* JAL: bits 111101 */
4132 case 0x3c: /* JALX: bits 111100 */
4133 return {}; /* Fall back to the standard single-step code. */
4135 case 0x18: /* POOL32C: bits 011000 */
4136 if ((b12s4_op (insn
) & 0xb) == 0xb)
4137 /* SC, SCD: bits 011000 1x11 */
4141 loc
+= MIPS_INSN16_SIZE
;
4144 /* 16-bit instructions. */
4145 case MIPS_INSN16_SIZE
:
4146 switch (micromips_op (insn
))
4148 case 0x23: /* BEQZ16: bits 100011 */
4149 case 0x2b: /* BNEZ16: bits 101011 */
4150 branch_bp
= loc
+ micromips_relative_offset7 (insn
);
4154 case 0x11: /* POOL16C: bits 010001 */
4155 if ((b5s5_op (insn
) & 0x1c) != 0xc
4156 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
4157 && b5s5_op (insn
) != 0x18)
4158 /* JRADDIUSP: bits 010001 11000 */
4160 return {}; /* Fall back to the standard single-step code. */
4162 case 0x33: /* B16: bits 110011 */
4163 return {}; /* Fall back to the standard single-step code. */
4169 if (last_breakpoint
>= 1)
4170 return {}; /* More than one branch found, fallback to the
4171 standard single-step code. */
4172 breaks
[1] = branch_bp
;
4179 /* Insert a breakpoint right after the end of the atomic sequence. */
4182 /* Check for duplicated breakpoints. Check also for a breakpoint
4183 placed (branch instruction's destination) in the atomic sequence */
4184 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
4185 last_breakpoint
= 0;
4187 std::vector
<CORE_ADDR
> next_pcs
;
4189 /* Effectively inserts the breakpoints. */
4190 for (index
= 0; index
<= last_breakpoint
; index
++)
4191 next_pcs
.push_back (breaks
[index
]);
4196 static std::vector
<CORE_ADDR
>
4197 deal_with_atomic_sequence (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4199 if (mips_pc_is_mips (pc
))
4200 return mips_deal_with_atomic_sequence (gdbarch
, pc
);
4201 else if (mips_pc_is_micromips (gdbarch
, pc
))
4202 return micromips_deal_with_atomic_sequence (gdbarch
, pc
);
4207 /* mips_software_single_step() is called just before we want to resume
4208 the inferior, if we want to single-step it but there is no hardware
4209 or kernel single-step support (MIPS on GNU/Linux for example). We find
4210 the target of the coming instruction and breakpoint it. */
4212 std::vector
<CORE_ADDR
>
4213 mips_software_single_step (struct regcache
*regcache
)
4215 struct gdbarch
*gdbarch
= regcache
->arch ();
4216 CORE_ADDR pc
, next_pc
;
4218 pc
= regcache_read_pc (regcache
);
4219 std::vector
<CORE_ADDR
> next_pcs
= deal_with_atomic_sequence (gdbarch
, pc
);
4221 if (!next_pcs
.empty ())
4224 next_pc
= mips_next_pc (regcache
, pc
);
4229 /* Test whether the PC points to the return instruction at the
4230 end of a function. */
4233 mips_about_to_return (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4238 /* This used to check for MIPS16, but this piece of code is never
4239 called for MIPS16 functions. And likewise microMIPS ones. */
4240 gdb_assert (mips_pc_is_mips (pc
));
4242 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
4244 return (insn
& ~hint
) == 0x3e00008; /* jr(.hb) $ra */
4248 /* This fencepost looks highly suspicious to me. Removing it also
4249 seems suspicious as it could affect remote debugging across serial
4253 heuristic_proc_start (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4259 struct inferior
*inf
;
4261 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
4263 fence
= start_pc
- heuristic_fence_post
;
4267 if (heuristic_fence_post
== -1 || fence
< VM_MIN_ADDRESS
)
4268 fence
= VM_MIN_ADDRESS
;
4270 instlen
= mips_pc_is_mips (pc
) ? MIPS_INSN32_SIZE
: MIPS_INSN16_SIZE
;
4272 inf
= current_inferior ();
4274 /* Search back for previous return. */
4275 for (start_pc
-= instlen
;; start_pc
-= instlen
)
4276 if (start_pc
< fence
)
4278 /* It's not clear to me why we reach this point when
4279 stop_soon, but with this test, at least we
4280 don't print out warnings for every child forked (eg, on
4281 decstation). 22apr93 rich@cygnus.com. */
4282 if (inf
->control
.stop_soon
== NO_STOP_QUIETLY
)
4284 static int blurb_printed
= 0;
4286 warning (_("GDB can't find the start of the function at %s."),
4287 paddress (gdbarch
, pc
));
4291 /* This actually happens frequently in embedded
4292 development, when you first connect to a board
4293 and your stack pointer and pc are nowhere in
4294 particular. This message needs to give people
4295 in that situation enough information to
4296 determine that it's no big deal. */
4298 GDB is unable to find the start of the function at %s\n\
4299 and thus can't determine the size of that function's stack frame.\n\
4300 This means that GDB may be unable to access that stack frame, or\n\
4301 the frames below it.\n\
4302 This problem is most likely caused by an invalid program counter or\n\
4304 However, if you think GDB should simply search farther back\n\
4305 from %s for code which looks like the beginning of a\n\
4306 function, you can increase the range of the search using the `set\n\
4307 heuristic-fence-post' command.\n",
4308 paddress (gdbarch
, pc
), paddress (gdbarch
, pc
));
4315 else if (mips_pc_is_mips16 (gdbarch
, start_pc
))
4317 unsigned short inst
;
4319 /* On MIPS16, any one of the following is likely to be the
4320 start of a function:
4326 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */
4327 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, start_pc
, NULL
);
4328 if ((inst
& 0xff80) == 0x6480) /* save */
4330 if (start_pc
- instlen
>= fence
)
4332 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
,
4333 start_pc
- instlen
, NULL
);
4334 if ((inst
& 0xf800) == 0xf000) /* extend */
4335 start_pc
-= instlen
;
4339 else if (((inst
& 0xf81f) == 0xe809
4340 && (inst
& 0x700) != 0x700) /* entry */
4341 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
4342 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
4343 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
4345 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
4346 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
4351 else if (mips_pc_is_micromips (gdbarch
, start_pc
))
4359 /* On microMIPS, any one of the following is likely to be the
4360 start of a function:
4364 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
4365 switch (micromips_op (insn
))
4367 case 0xc: /* ADDIU: bits 001100 */
4368 case 0x17: /* DADDIU: bits 010111 */
4369 sreg
= b0s5_reg (insn
);
4370 dreg
= b5s5_reg (insn
);
4372 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
,
4373 pc
+ MIPS_INSN16_SIZE
, NULL
);
4374 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
4375 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
4376 /* (D)ADDIU $sp, imm */
4381 case 0x10: /* POOL32I: bits 010000 */
4382 if (b5s5_op (insn
) == 0xd
4383 /* LUI: bits 010000 001101 */
4384 && b0s5_reg (insn
>> 16) == 28)
4389 case 0x13: /* POOL16D: bits 010011 */
4390 if ((insn
& 0x1) == 0x1)
4391 /* ADDIUSP: bits 010011 1 */
4393 offset
= micromips_decode_imm9 (b1s9_imm (insn
));
4399 /* ADDIUS5: bits 010011 0 */
4401 dreg
= b5s5_reg (insn
);
4402 offset
= (b1s4_imm (insn
) ^ 8) - 8;
4403 if (dreg
== MIPS_SP_REGNUM
&& offset
< 0)
4404 /* ADDIUS5 $sp, -imm */
4412 else if (mips_about_to_return (gdbarch
, start_pc
))
4414 /* Skip return and its delay slot. */
4415 start_pc
+= 2 * MIPS_INSN32_SIZE
;
4422 struct mips_objfile_private
4428 /* According to the current ABI, should the type be passed in a
4429 floating-point register (assuming that there is space)? When there
4430 is no FPU, FP are not even considered as possible candidates for
4431 FP registers and, consequently this returns false - forces FP
4432 arguments into integer registers. */
4435 fp_register_arg_p (struct gdbarch
*gdbarch
, enum type_code typecode
,
4436 struct type
*arg_type
)
4438 return ((typecode
== TYPE_CODE_FLT
4439 || (mips_eabi (gdbarch
)
4440 && (typecode
== TYPE_CODE_STRUCT
4441 || typecode
== TYPE_CODE_UNION
)
4442 && arg_type
->num_fields () == 1
4443 && check_typedef (arg_type
->field (0).type ())->code ()
4445 && mips_get_fpu_type (gdbarch
) != MIPS_FPU_NONE
);
4448 /* On o32, argument passing in GPRs depends on the alignment of the type being
4449 passed. Return 1 if this type must be aligned to a doubleword boundary. */
4452 mips_type_needs_double_align (struct type
*type
)
4454 enum type_code typecode
= type
->code ();
4456 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
4458 else if (typecode
== TYPE_CODE_STRUCT
)
4460 if (type
->num_fields () < 1)
4462 return mips_type_needs_double_align (type
->field (0).type ());
4464 else if (typecode
== TYPE_CODE_UNION
)
4468 n
= type
->num_fields ();
4469 for (i
= 0; i
< n
; i
++)
4470 if (mips_type_needs_double_align (type
->field (i
).type ()))
4477 /* Adjust the address downward (direction of stack growth) so that it
4478 is correctly aligned for a new stack frame. */
4480 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
4482 return align_down (addr
, 16);
4485 /* Implement the "push_dummy_code" gdbarch method. */
4488 mips_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
4489 CORE_ADDR funaddr
, struct value
**args
,
4490 int nargs
, struct type
*value_type
,
4491 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
4492 struct regcache
*regcache
)
4494 static gdb_byte nop_insn
[] = { 0, 0, 0, 0 };
4498 /* Reserve enough room on the stack for our breakpoint instruction. */
4499 bp_slot
= sp
- sizeof (nop_insn
);
4501 /* Return to microMIPS mode if calling microMIPS code to avoid
4502 triggering an address error exception on processors that only
4503 support microMIPS execution. */
4504 *bp_addr
= (mips_pc_is_micromips (gdbarch
, funaddr
)
4505 ? make_compact_addr (bp_slot
) : bp_slot
);
4507 /* The breakpoint layer automatically adjusts the address of
4508 breakpoints inserted in a branch delay slot. With enough
4509 bad luck, the 4 bytes located just before our breakpoint
4510 instruction could look like a branch instruction, and thus
4511 trigger the adjustement, and break the function call entirely.
4512 So, we reserve those 4 bytes and write a nop instruction
4513 to prevent that from happening. */
4514 nop_addr
= bp_slot
- sizeof (nop_insn
);
4515 write_memory (nop_addr
, nop_insn
, sizeof (nop_insn
));
4516 sp
= mips_frame_align (gdbarch
, nop_addr
);
4518 /* Inferior resumes at the function entry point. */
4525 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4526 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4527 int nargs
, struct value
**args
, CORE_ADDR sp
,
4528 function_call_return_method return_method
,
4529 CORE_ADDR struct_addr
)
4535 int stack_offset
= 0;
4536 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4537 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4538 int abi_regsize
= mips_abi_regsize (gdbarch
);
4540 /* For shared libraries, "t9" needs to point at the function
4542 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4544 /* Set the return address register to point to the entry point of
4545 the program, where a breakpoint lies in wait. */
4546 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4548 /* First ensure that the stack and structure return address (if any)
4549 are properly aligned. The stack has to be at least 64-bit
4550 aligned even on 32-bit machines, because doubles must be 64-bit
4551 aligned. For n32 and n64, stack frames need to be 128-bit
4552 aligned, so we round to this widest known alignment. */
4554 sp
= align_down (sp
, 16);
4555 struct_addr
= align_down (struct_addr
, 16);
4557 /* Now make space on the stack for the args. We allocate more
4558 than necessary for EABI, because the first few arguments are
4559 passed in registers, but that's OK. */
4560 for (argnum
= 0; argnum
< nargs
; argnum
++)
4561 arg_space
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), abi_regsize
);
4562 sp
-= align_up (arg_space
, 16);
4565 gdb_printf (gdb_stdlog
,
4566 "mips_eabi_push_dummy_call: sp=%s allocated %ld\n",
4567 paddress (gdbarch
, sp
),
4568 (long) align_up (arg_space
, 16));
4570 /* Initialize the integer and float register pointers. */
4571 argreg
= MIPS_A0_REGNUM
;
4572 float_argreg
= mips_fpa0_regnum (gdbarch
);
4574 /* The struct_return pointer occupies the first parameter-passing reg. */
4575 if (return_method
== return_method_struct
)
4578 gdb_printf (gdb_stdlog
,
4579 "mips_eabi_push_dummy_call: "
4580 "struct_return reg=%d %s\n",
4581 argreg
, paddress (gdbarch
, struct_addr
));
4582 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4585 /* Now load as many as possible of the first arguments into
4586 registers, and push the rest onto the stack. Loop thru args
4587 from first to last. */
4588 for (argnum
= 0; argnum
< nargs
; argnum
++)
4590 const gdb_byte
*val
;
4591 /* This holds the address of structures that are passed by
4593 gdb_byte ref_valbuf
[MAX_MIPS_ABI_REGSIZE
];
4594 struct value
*arg
= args
[argnum
];
4595 struct type
*arg_type
= check_typedef (value_type (arg
));
4596 int len
= TYPE_LENGTH (arg_type
);
4597 enum type_code typecode
= arg_type
->code ();
4600 gdb_printf (gdb_stdlog
,
4601 "mips_eabi_push_dummy_call: %d len=%d type=%d",
4602 argnum
+ 1, len
, (int) typecode
);
4604 /* The EABI passes structures that do not fit in a register by
4606 if (len
> abi_regsize
4607 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
4609 gdb_assert (abi_regsize
<= ARRAY_SIZE (ref_valbuf
));
4610 store_unsigned_integer (ref_valbuf
, abi_regsize
, byte_order
,
4611 value_address (arg
));
4612 typecode
= TYPE_CODE_PTR
;
4616 gdb_printf (gdb_stdlog
, " push");
4619 val
= value_contents (arg
).data ();
4621 /* 32-bit ABIs always start floating point arguments in an
4622 even-numbered floating point register. Round the FP register
4623 up before the check to see if there are any FP registers
4624 left. Non MIPS_EABI targets also pass the FP in the integer
4625 registers so also round up normal registers. */
4626 if (abi_regsize
< 8 && fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4628 if ((float_argreg
& 1))
4632 /* Floating point arguments passed in registers have to be
4633 treated specially. On 32-bit architectures, doubles
4634 are passed in register pairs; the even register gets
4635 the low word, and the odd register gets the high word.
4636 On non-EABI processors, the first two floating point arguments are
4637 also copied to general registers, because MIPS16 functions
4638 don't use float registers for arguments. This duplication of
4639 arguments in general registers can't hurt non-MIPS16 functions
4640 because those registers are normally skipped. */
4641 /* MIPS_EABI squeezes a struct that contains a single floating
4642 point value into an FP register instead of pushing it onto the
4644 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4645 && float_argreg
<= mips_last_fp_arg_regnum (gdbarch
))
4647 /* EABI32 will pass doubles in consecutive registers, even on
4648 64-bit cores. At one time, we used to check the size of
4649 `float_argreg' to determine whether or not to pass doubles
4650 in consecutive registers, but this is not sufficient for
4651 making the ABI determination. */
4652 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
4654 int low_offset
= gdbarch_byte_order (gdbarch
)
4655 == BFD_ENDIAN_BIG
? 4 : 0;
4658 /* Write the low word of the double to the even register(s). */
4659 regval
= extract_signed_integer (val
+ low_offset
,
4662 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
4663 float_argreg
, phex (regval
, 4));
4664 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4666 /* Write the high word of the double to the odd register(s). */
4667 regval
= extract_signed_integer (val
+ 4 - low_offset
,
4670 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
4671 float_argreg
, phex (regval
, 4));
4672 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4676 /* This is a floating point value that fits entirely
4677 in a single register. */
4678 /* On 32 bit ABI's the float_argreg is further adjusted
4679 above to ensure that it is even register aligned. */
4680 LONGEST regval
= extract_signed_integer (val
, len
, byte_order
);
4682 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
4683 float_argreg
, phex (regval
, len
));
4684 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4689 /* Copy the argument to general registers or the stack in
4690 register-sized pieces. Large arguments are split between
4691 registers and stack. */
4692 /* Note: structs whose size is not a multiple of abi_regsize
4693 are treated specially: Irix cc passes
4694 them in registers where gcc sometimes puts them on the
4695 stack. For maximum compatibility, we will put them in
4697 int odd_sized_struct
= (len
> abi_regsize
&& len
% abi_regsize
!= 0);
4699 /* Note: Floating-point values that didn't fit into an FP
4700 register are only written to memory. */
4703 /* Remember if the argument was written to the stack. */
4704 int stack_used_p
= 0;
4705 int partial_len
= (len
< abi_regsize
? len
: abi_regsize
);
4708 gdb_printf (gdb_stdlog
, " -- partial=%d",
4711 /* Write this portion of the argument to the stack. */
4712 if (argreg
> mips_last_arg_regnum (gdbarch
)
4714 || fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4716 /* Should shorter than int integer values be
4717 promoted to int before being stored? */
4718 int longword_offset
= 0;
4721 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4723 if (abi_regsize
== 8
4724 && (typecode
== TYPE_CODE_INT
4725 || typecode
== TYPE_CODE_PTR
4726 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
4727 longword_offset
= abi_regsize
- len
;
4728 else if ((typecode
== TYPE_CODE_STRUCT
4729 || typecode
== TYPE_CODE_UNION
)
4730 && TYPE_LENGTH (arg_type
) < abi_regsize
)
4731 longword_offset
= abi_regsize
- len
;
4736 gdb_printf (gdb_stdlog
, " - stack_offset=%s",
4737 paddress (gdbarch
, stack_offset
));
4738 gdb_printf (gdb_stdlog
, " longword_offset=%s",
4739 paddress (gdbarch
, longword_offset
));
4742 addr
= sp
+ stack_offset
+ longword_offset
;
4747 gdb_printf (gdb_stdlog
, " @%s ",
4748 paddress (gdbarch
, addr
));
4749 for (i
= 0; i
< partial_len
; i
++)
4751 gdb_printf (gdb_stdlog
, "%02x",
4755 write_memory (addr
, val
, partial_len
);
4758 /* Note!!! This is NOT an else clause. Odd sized
4759 structs may go thru BOTH paths. Floating point
4760 arguments will not. */
4761 /* Write this portion of the argument to a general
4762 purpose register. */
4763 if (argreg
<= mips_last_arg_regnum (gdbarch
)
4764 && !fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4767 extract_signed_integer (val
, partial_len
, byte_order
);
4770 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
4772 phex (regval
, abi_regsize
));
4773 regcache_cooked_write_signed (regcache
, argreg
, regval
);
4780 /* Compute the offset into the stack at which we will
4781 copy the next parameter.
4783 In the new EABI (and the NABI32), the stack_offset
4784 only needs to be adjusted when it has been used. */
4787 stack_offset
+= align_up (partial_len
, abi_regsize
);
4791 gdb_printf (gdb_stdlog
, "\n");
4794 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4796 /* Return adjusted stack pointer. */
4800 /* Determine the return value convention being used. */
4802 static enum return_value_convention
4803 mips_eabi_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
4804 struct type
*type
, struct regcache
*regcache
,
4805 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4807 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
4808 int fp_return_type
= 0;
4809 int offset
, regnum
, xfer
;
4811 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
4812 return RETURN_VALUE_STRUCT_CONVENTION
;
4814 /* Floating point type? */
4815 if (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4817 if (type
->code () == TYPE_CODE_FLT
)
4819 /* Structs with a single field of float type
4820 are returned in a floating point register. */
4821 if ((type
->code () == TYPE_CODE_STRUCT
4822 || type
->code () == TYPE_CODE_UNION
)
4823 && type
->num_fields () == 1)
4825 struct type
*fieldtype
= type
->field (0).type ();
4827 if (check_typedef (fieldtype
)->code () == TYPE_CODE_FLT
)
4834 /* A floating-point value belongs in the least significant part
4837 gdb_printf (gdb_stderr
, "Return float in $fp0\n");
4838 regnum
= mips_regnum (gdbarch
)->fp0
;
4842 /* An integer value goes in V0/V1. */
4844 gdb_printf (gdb_stderr
, "Return scalar in $v0\n");
4845 regnum
= MIPS_V0_REGNUM
;
4848 offset
< TYPE_LENGTH (type
);
4849 offset
+= mips_abi_regsize (gdbarch
), regnum
++)
4851 xfer
= mips_abi_regsize (gdbarch
);
4852 if (offset
+ xfer
> TYPE_LENGTH (type
))
4853 xfer
= TYPE_LENGTH (type
) - offset
;
4854 mips_xfer_register (gdbarch
, regcache
,
4855 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
4856 gdbarch_byte_order (gdbarch
), readbuf
, writebuf
,
4860 return RETURN_VALUE_REGISTER_CONVENTION
;
4864 /* N32/N64 ABI stuff. */
4866 /* Search for a naturally aligned double at OFFSET inside a struct
4867 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
4871 mips_n32n64_fp_arg_chunk_p (struct gdbarch
*gdbarch
, struct type
*arg_type
,
4876 if (arg_type
->code () != TYPE_CODE_STRUCT
)
4879 if (mips_get_fpu_type (gdbarch
) != MIPS_FPU_DOUBLE
)
4882 if (TYPE_LENGTH (arg_type
) < offset
+ MIPS64_REGSIZE
)
4885 for (i
= 0; i
< arg_type
->num_fields (); i
++)
4888 struct type
*field_type
;
4890 /* We're only looking at normal fields. */
4891 if (field_is_static (&arg_type
->field (i
))
4892 || (arg_type
->field (i
).loc_bitpos () % 8) != 0)
4895 /* If we have gone past the offset, there is no double to pass. */
4896 pos
= arg_type
->field (i
).loc_bitpos () / 8;
4900 field_type
= check_typedef (arg_type
->field (i
).type ());
4902 /* If this field is entirely before the requested offset, go
4903 on to the next one. */
4904 if (pos
+ TYPE_LENGTH (field_type
) <= offset
)
4907 /* If this is our special aligned double, we can stop. */
4908 if (field_type
->code () == TYPE_CODE_FLT
4909 && TYPE_LENGTH (field_type
) == MIPS64_REGSIZE
)
4912 /* This field starts at or before the requested offset, and
4913 overlaps it. If it is a structure, recurse inwards. */
4914 return mips_n32n64_fp_arg_chunk_p (gdbarch
, field_type
, offset
- pos
);
4921 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4922 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4923 int nargs
, struct value
**args
, CORE_ADDR sp
,
4924 function_call_return_method return_method
,
4925 CORE_ADDR struct_addr
)
4931 int stack_offset
= 0;
4932 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4933 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4935 /* For shared libraries, "t9" needs to point at the function
4937 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4939 /* Set the return address register to point to the entry point of
4940 the program, where a breakpoint lies in wait. */
4941 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4943 /* First ensure that the stack and structure return address (if any)
4944 are properly aligned. The stack has to be at least 64-bit
4945 aligned even on 32-bit machines, because doubles must be 64-bit
4946 aligned. For n32 and n64, stack frames need to be 128-bit
4947 aligned, so we round to this widest known alignment. */
4949 sp
= align_down (sp
, 16);
4950 struct_addr
= align_down (struct_addr
, 16);
4952 /* Now make space on the stack for the args. */
4953 for (argnum
= 0; argnum
< nargs
; argnum
++)
4954 arg_space
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), MIPS64_REGSIZE
);
4955 sp
-= align_up (arg_space
, 16);
4958 gdb_printf (gdb_stdlog
,
4959 "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n",
4960 paddress (gdbarch
, sp
),
4961 (long) align_up (arg_space
, 16));
4963 /* Initialize the integer and float register pointers. */
4964 argreg
= MIPS_A0_REGNUM
;
4965 float_argreg
= mips_fpa0_regnum (gdbarch
);
4967 /* The struct_return pointer occupies the first parameter-passing reg. */
4968 if (return_method
== return_method_struct
)
4971 gdb_printf (gdb_stdlog
,
4972 "mips_n32n64_push_dummy_call: "
4973 "struct_return reg=%d %s\n",
4974 argreg
, paddress (gdbarch
, struct_addr
));
4975 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4978 /* Now load as many as possible of the first arguments into
4979 registers, and push the rest onto the stack. Loop thru args
4980 from first to last. */
4981 for (argnum
= 0; argnum
< nargs
; argnum
++)
4983 const gdb_byte
*val
;
4984 struct value
*arg
= args
[argnum
];
4985 struct type
*arg_type
= check_typedef (value_type (arg
));
4986 int len
= TYPE_LENGTH (arg_type
);
4987 enum type_code typecode
= arg_type
->code ();
4990 gdb_printf (gdb_stdlog
,
4991 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
4992 argnum
+ 1, len
, (int) typecode
);
4994 val
= value_contents (arg
).data ();
4996 /* A 128-bit long double value requires an even-odd pair of
4997 floating-point registers. */
4999 && fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5000 && (float_argreg
& 1))
5006 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5007 && argreg
<= mips_last_arg_regnum (gdbarch
))
5009 /* This is a floating point value that fits entirely
5010 in a single register or a pair of registers. */
5011 int reglen
= (len
<= MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
5012 LONGEST regval
= extract_unsigned_integer (val
, reglen
, byte_order
);
5014 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
5015 float_argreg
, phex (regval
, reglen
));
5016 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
5019 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
5020 argreg
, phex (regval
, reglen
));
5021 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5026 regval
= extract_unsigned_integer (val
+ reglen
,
5027 reglen
, byte_order
);
5029 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
5030 float_argreg
, phex (regval
, reglen
));
5031 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
5034 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
5035 argreg
, phex (regval
, reglen
));
5036 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5043 /* Copy the argument to general registers or the stack in
5044 register-sized pieces. Large arguments are split between
5045 registers and stack. */
5046 /* For N32/N64, structs, unions, or other composite types are
5047 treated as a sequence of doublewords, and are passed in integer
5048 or floating point registers as though they were simple scalar
5049 parameters to the extent that they fit, with any excess on the
5050 stack packed according to the normal memory layout of the
5052 The caller does not reserve space for the register arguments;
5053 the callee is responsible for reserving it if required. */
5054 /* Note: Floating-point values that didn't fit into an FP
5055 register are only written to memory. */
5058 /* Remember if the argument was written to the stack. */
5059 int stack_used_p
= 0;
5060 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
5063 gdb_printf (gdb_stdlog
, " -- partial=%d",
5066 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
5067 gdb_assert (argreg
> mips_last_arg_regnum (gdbarch
));
5069 /* Write this portion of the argument to the stack. */
5070 if (argreg
> mips_last_arg_regnum (gdbarch
))
5072 /* Should shorter than int integer values be
5073 promoted to int before being stored? */
5074 int longword_offset
= 0;
5077 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5079 if ((typecode
== TYPE_CODE_INT
5080 || typecode
== TYPE_CODE_PTR
)
5082 longword_offset
= MIPS64_REGSIZE
- len
;
5087 gdb_printf (gdb_stdlog
, " - stack_offset=%s",
5088 paddress (gdbarch
, stack_offset
));
5089 gdb_printf (gdb_stdlog
, " longword_offset=%s",
5090 paddress (gdbarch
, longword_offset
));
5093 addr
= sp
+ stack_offset
+ longword_offset
;
5098 gdb_printf (gdb_stdlog
, " @%s ",
5099 paddress (gdbarch
, addr
));
5100 for (i
= 0; i
< partial_len
; i
++)
5102 gdb_printf (gdb_stdlog
, "%02x",
5106 write_memory (addr
, val
, partial_len
);
5109 /* Note!!! This is NOT an else clause. Odd sized
5110 structs may go thru BOTH paths. */
5111 /* Write this portion of the argument to a general
5112 purpose register. */
5113 if (argreg
<= mips_last_arg_regnum (gdbarch
))
5117 /* Sign extend pointers, 32-bit integers and signed
5118 16-bit and 8-bit integers; everything else is taken
5121 if ((partial_len
== 4
5122 && (typecode
== TYPE_CODE_PTR
5123 || typecode
== TYPE_CODE_INT
))
5125 && typecode
== TYPE_CODE_INT
5126 && !arg_type
->is_unsigned ()))
5127 regval
= extract_signed_integer (val
, partial_len
,
5130 regval
= extract_unsigned_integer (val
, partial_len
,
5133 /* A non-floating-point argument being passed in a
5134 general register. If a struct or union, and if
5135 the remaining length is smaller than the register
5136 size, we have to adjust the register value on
5139 It does not seem to be necessary to do the
5140 same for integral types. */
5142 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
5143 && partial_len
< MIPS64_REGSIZE
5144 && (typecode
== TYPE_CODE_STRUCT
5145 || typecode
== TYPE_CODE_UNION
))
5146 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
5150 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
5152 phex (regval
, MIPS64_REGSIZE
));
5153 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5155 if (mips_n32n64_fp_arg_chunk_p (gdbarch
, arg_type
,
5156 TYPE_LENGTH (arg_type
) - len
))
5159 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
5161 phex (regval
, MIPS64_REGSIZE
));
5162 regcache_cooked_write_unsigned (regcache
, float_argreg
,
5173 /* Compute the offset into the stack at which we will
5174 copy the next parameter.
5176 In N32 (N64?), the stack_offset only needs to be
5177 adjusted when it has been used. */
5180 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
5184 gdb_printf (gdb_stdlog
, "\n");
5187 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
5189 /* Return adjusted stack pointer. */
5193 static enum return_value_convention
5194 mips_n32n64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
5195 struct type
*type
, struct regcache
*regcache
,
5196 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5198 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
5200 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
5202 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
5203 if needed), as appropriate for the type. Composite results (struct,
5204 union, or array) are returned in $2/$f0 and $3/$f2 according to the
5207 * A struct with only one or two floating point fields is returned in $f0
5208 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
5211 * Any other composite results of at most 128 bits are returned in
5212 $2 (first 64 bits) and $3 (remainder, if necessary).
5214 * Larger composite results are handled by converting the function to a
5215 procedure with an implicit first parameter, which is a pointer to an area
5216 reserved by the caller to receive the result. [The o32-bit ABI requires
5217 that all composite results be handled by conversion to implicit first
5218 parameters. The MIPS/SGI Fortran implementation has always made a
5219 specific exception to return COMPLEX results in the floating point
5222 From MIPSpro Assembly Language Programmer's Guide, Document Number:
5227 Name fgregdef.h) Use and Linkage
5228 -----------------------------------------------------------------
5229 $f0, $f2 fv0, fv1 Hold results of floating-point type function
5230 ($f0) and complex type function ($f0 has the
5231 real part, $f2 has the imaginary part.) */
5233 if (TYPE_LENGTH (type
) > 2 * MIPS64_REGSIZE
)
5234 return RETURN_VALUE_STRUCT_CONVENTION
;
5235 else if ((type
->code () == TYPE_CODE_COMPLEX
5236 || (type
->code () == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 16))
5237 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5239 /* A complex value of up to 128 bits in width as well as a 128-bit
5240 floating-point value goes in both $f0 and $f2. A single complex
5241 value is held in the lower halves only of the respective registers.
5242 The two registers are used in the same as memory order, so the
5243 bytes with the lower memory address are in $f0. */
5245 gdb_printf (gdb_stderr
, "Return float in $f0 and $f2\n");
5246 mips_xfer_register (gdbarch
, regcache
,
5247 (gdbarch_num_regs (gdbarch
)
5248 + mips_regnum (gdbarch
)->fp0
),
5249 TYPE_LENGTH (type
) / 2, gdbarch_byte_order (gdbarch
),
5250 readbuf
, writebuf
, 0);
5251 mips_xfer_register (gdbarch
, regcache
,
5252 (gdbarch_num_regs (gdbarch
)
5253 + mips_regnum (gdbarch
)->fp0
+ 2),
5254 TYPE_LENGTH (type
) / 2, gdbarch_byte_order (gdbarch
),
5255 readbuf
? readbuf
+ TYPE_LENGTH (type
) / 2 : readbuf
,
5257 ? writebuf
+ TYPE_LENGTH (type
) / 2 : writebuf
), 0);
5258 return RETURN_VALUE_REGISTER_CONVENTION
;
5260 else if (type
->code () == TYPE_CODE_FLT
5261 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5263 /* A single or double floating-point value that fits in FP0. */
5265 gdb_printf (gdb_stderr
, "Return float in $fp0\n");
5266 mips_xfer_register (gdbarch
, regcache
,
5267 (gdbarch_num_regs (gdbarch
)
5268 + mips_regnum (gdbarch
)->fp0
),
5270 gdbarch_byte_order (gdbarch
),
5271 readbuf
, writebuf
, 0);
5272 return RETURN_VALUE_REGISTER_CONVENTION
;
5274 else if (type
->code () == TYPE_CODE_STRUCT
5275 && type
->num_fields () <= 2
5276 && type
->num_fields () >= 1
5277 && ((type
->num_fields () == 1
5278 && (check_typedef (type
->field (0).type ())->code ()
5280 || (type
->num_fields () == 2
5281 && (check_typedef (type
->field (0).type ())->code ()
5283 && (check_typedef (type
->field (1).type ())->code ()
5284 == TYPE_CODE_FLT
))))
5286 /* A struct that contains one or two floats. Each value is part
5287 in the least significant part of their floating point
5288 register (or GPR, for soft float). */
5291 for (field
= 0, regnum
= (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
5292 ? mips_regnum (gdbarch
)->fp0
5294 field
< type
->num_fields (); field
++, regnum
+= 2)
5296 int offset
= type
->field (field
).loc_bitpos () / TARGET_CHAR_BIT
;
5298 gdb_printf (gdb_stderr
, "Return float struct+%d\n",
5300 if (TYPE_LENGTH (type
->field (field
).type ()) == 16)
5302 /* A 16-byte long double field goes in two consecutive
5304 mips_xfer_register (gdbarch
, regcache
,
5305 gdbarch_num_regs (gdbarch
) + regnum
,
5307 gdbarch_byte_order (gdbarch
),
5308 readbuf
, writebuf
, offset
);
5309 mips_xfer_register (gdbarch
, regcache
,
5310 gdbarch_num_regs (gdbarch
) + regnum
+ 1,
5312 gdbarch_byte_order (gdbarch
),
5313 readbuf
, writebuf
, offset
+ 8);
5316 mips_xfer_register (gdbarch
, regcache
,
5317 gdbarch_num_regs (gdbarch
) + regnum
,
5318 TYPE_LENGTH (type
->field (field
).type ()),
5319 gdbarch_byte_order (gdbarch
),
5320 readbuf
, writebuf
, offset
);
5322 return RETURN_VALUE_REGISTER_CONVENTION
;
5324 else if (type
->code () == TYPE_CODE_STRUCT
5325 || type
->code () == TYPE_CODE_UNION
5326 || type
->code () == TYPE_CODE_ARRAY
)
5328 /* A composite type. Extract the left justified value,
5329 regardless of the byte order. I.e. DO NOT USE
5333 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5334 offset
< TYPE_LENGTH (type
);
5335 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5337 int xfer
= register_size (gdbarch
, regnum
);
5338 if (offset
+ xfer
> TYPE_LENGTH (type
))
5339 xfer
= TYPE_LENGTH (type
) - offset
;
5341 gdb_printf (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5342 offset
, xfer
, regnum
);
5343 mips_xfer_register (gdbarch
, regcache
,
5344 gdbarch_num_regs (gdbarch
) + regnum
,
5345 xfer
, BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
,
5348 return RETURN_VALUE_REGISTER_CONVENTION
;
5352 /* A scalar extract each part but least-significant-byte
5356 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5357 offset
< TYPE_LENGTH (type
);
5358 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5360 int xfer
= register_size (gdbarch
, regnum
);
5361 if (offset
+ xfer
> TYPE_LENGTH (type
))
5362 xfer
= TYPE_LENGTH (type
) - offset
;
5364 gdb_printf (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5365 offset
, xfer
, regnum
);
5366 mips_xfer_register (gdbarch
, regcache
,
5367 gdbarch_num_regs (gdbarch
) + regnum
,
5368 xfer
, gdbarch_byte_order (gdbarch
),
5369 readbuf
, writebuf
, offset
);
5371 return RETURN_VALUE_REGISTER_CONVENTION
;
5375 /* Which registers to use for passing floating-point values between
5376 function calls, one of floating-point, general and both kinds of
5377 registers. O32 and O64 use different register kinds for standard
5378 MIPS and MIPS16 code; to make the handling of cases where we may
5379 not know what kind of code is being used (e.g. no debug information)
5380 easier we sometimes use both kinds. */
5389 /* O32 ABI stuff. */
5392 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
5393 struct regcache
*regcache
, CORE_ADDR bp_addr
,
5394 int nargs
, struct value
**args
, CORE_ADDR sp
,
5395 function_call_return_method return_method
,
5396 CORE_ADDR struct_addr
)
5402 int stack_offset
= 0;
5403 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5404 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
5406 /* For shared libraries, "t9" needs to point at the function
5408 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
5410 /* Set the return address register to point to the entry point of
5411 the program, where a breakpoint lies in wait. */
5412 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
5414 /* First ensure that the stack and structure return address (if any)
5415 are properly aligned. The stack has to be at least 64-bit
5416 aligned even on 32-bit machines, because doubles must be 64-bit
5417 aligned. For n32 and n64, stack frames need to be 128-bit
5418 aligned, so we round to this widest known alignment. */
5420 sp
= align_down (sp
, 16);
5421 struct_addr
= align_down (struct_addr
, 16);
5423 /* Now make space on the stack for the args. */
5424 for (argnum
= 0; argnum
< nargs
; argnum
++)
5426 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
5428 /* Align to double-word if necessary. */
5429 if (mips_type_needs_double_align (arg_type
))
5430 arg_space
= align_up (arg_space
, MIPS32_REGSIZE
* 2);
5431 /* Allocate space on the stack. */
5432 arg_space
+= align_up (TYPE_LENGTH (arg_type
), MIPS32_REGSIZE
);
5434 sp
-= align_up (arg_space
, 16);
5437 gdb_printf (gdb_stdlog
,
5438 "mips_o32_push_dummy_call: sp=%s allocated %ld\n",
5439 paddress (gdbarch
, sp
),
5440 (long) align_up (arg_space
, 16));
5442 /* Initialize the integer and float register pointers. */
5443 argreg
= MIPS_A0_REGNUM
;
5444 float_argreg
= mips_fpa0_regnum (gdbarch
);
5446 /* The struct_return pointer occupies the first parameter-passing reg. */
5447 if (return_method
== return_method_struct
)
5450 gdb_printf (gdb_stdlog
,
5451 "mips_o32_push_dummy_call: "
5452 "struct_return reg=%d %s\n",
5453 argreg
, paddress (gdbarch
, struct_addr
));
5454 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
5455 stack_offset
+= MIPS32_REGSIZE
;
5458 /* Now load as many as possible of the first arguments into
5459 registers, and push the rest onto the stack. Loop thru args
5460 from first to last. */
5461 for (argnum
= 0; argnum
< nargs
; argnum
++)
5463 const gdb_byte
*val
;
5464 struct value
*arg
= args
[argnum
];
5465 struct type
*arg_type
= check_typedef (value_type (arg
));
5466 int len
= TYPE_LENGTH (arg_type
);
5467 enum type_code typecode
= arg_type
->code ();
5470 gdb_printf (gdb_stdlog
,
5471 "mips_o32_push_dummy_call: %d len=%d type=%d",
5472 argnum
+ 1, len
, (int) typecode
);
5474 val
= value_contents (arg
).data ();
5476 /* 32-bit ABIs always start floating point arguments in an
5477 even-numbered floating point register. Round the FP register
5478 up before the check to see if there are any FP registers
5479 left. O32 targets also pass the FP in the integer registers
5480 so also round up normal registers. */
5481 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
5483 if ((float_argreg
& 1))
5487 /* Floating point arguments passed in registers have to be
5488 treated specially. On 32-bit architectures, doubles are
5489 passed in register pairs; the even FP register gets the
5490 low word, and the odd FP register gets the high word.
5491 On O32, the first two floating point arguments are also
5492 copied to general registers, following their memory order,
5493 because MIPS16 functions don't use float registers for
5494 arguments. This duplication of arguments in general
5495 registers can't hurt non-MIPS16 functions, because those
5496 registers are normally skipped. */
5498 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5499 && float_argreg
<= mips_last_fp_arg_regnum (gdbarch
))
5501 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
5503 int freg_offset
= gdbarch_byte_order (gdbarch
)
5504 == BFD_ENDIAN_BIG
? 1 : 0;
5505 unsigned long regval
;
5508 regval
= extract_unsigned_integer (val
, 4, byte_order
);
5510 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
5511 float_argreg
+ freg_offset
,
5513 regcache_cooked_write_unsigned (regcache
,
5514 float_argreg
++ + freg_offset
,
5517 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
5518 argreg
, phex (regval
, 4));
5519 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5522 regval
= extract_unsigned_integer (val
+ 4, 4, byte_order
);
5524 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
5525 float_argreg
- freg_offset
,
5527 regcache_cooked_write_unsigned (regcache
,
5528 float_argreg
++ - freg_offset
,
5531 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
5532 argreg
, phex (regval
, 4));
5533 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5537 /* This is a floating point value that fits entirely
5538 in a single register. */
5539 /* On 32 bit ABI's the float_argreg is further adjusted
5540 above to ensure that it is even register aligned. */
5541 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
5543 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
5544 float_argreg
, phex (regval
, len
));
5545 regcache_cooked_write_unsigned (regcache
,
5546 float_argreg
++, regval
);
5547 /* Although two FP registers are reserved for each
5548 argument, only one corresponding integer register is
5551 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
5552 argreg
, phex (regval
, len
));
5553 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5555 /* Reserve space for the FP register. */
5556 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
5560 /* Copy the argument to general registers or the stack in
5561 register-sized pieces. Large arguments are split between
5562 registers and stack. */
5563 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
5564 are treated specially: Irix cc passes
5565 them in registers where gcc sometimes puts them on the
5566 stack. For maximum compatibility, we will put them in
5568 int odd_sized_struct
= (len
> MIPS32_REGSIZE
5569 && len
% MIPS32_REGSIZE
!= 0);
5570 /* Structures should be aligned to eight bytes (even arg registers)
5571 on MIPS_ABI_O32, if their first member has double precision. */
5572 if (mips_type_needs_double_align (arg_type
))
5577 stack_offset
+= MIPS32_REGSIZE
;
5582 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
5585 gdb_printf (gdb_stdlog
, " -- partial=%d",
5588 /* Write this portion of the argument to the stack. */
5589 if (argreg
> mips_last_arg_regnum (gdbarch
)
5590 || odd_sized_struct
)
5592 /* Should shorter than int integer values be
5593 promoted to int before being stored? */
5594 int longword_offset
= 0;
5599 gdb_printf (gdb_stdlog
, " - stack_offset=%s",
5600 paddress (gdbarch
, stack_offset
));
5601 gdb_printf (gdb_stdlog
, " longword_offset=%s",
5602 paddress (gdbarch
, longword_offset
));
5605 addr
= sp
+ stack_offset
+ longword_offset
;
5610 gdb_printf (gdb_stdlog
, " @%s ",
5611 paddress (gdbarch
, addr
));
5612 for (i
= 0; i
< partial_len
; i
++)
5614 gdb_printf (gdb_stdlog
, "%02x",
5618 write_memory (addr
, val
, partial_len
);
5621 /* Note!!! This is NOT an else clause. Odd sized
5622 structs may go thru BOTH paths. */
5623 /* Write this portion of the argument to a general
5624 purpose register. */
5625 if (argreg
<= mips_last_arg_regnum (gdbarch
))
5627 LONGEST regval
= extract_signed_integer (val
, partial_len
,
5629 /* Value may need to be sign extended, because
5630 mips_isa_regsize() != mips_abi_regsize(). */
5632 /* A non-floating-point argument being passed in a
5633 general register. If a struct or union, and if
5634 the remaining length is smaller than the register
5635 size, we have to adjust the register value on
5638 It does not seem to be necessary to do the
5639 same for integral types.
5641 Also don't do this adjustment on O64 binaries.
5643 cagney/2001-07-23: gdb/179: Also, GCC, when
5644 outputting LE O32 with sizeof (struct) <
5645 mips_abi_regsize(), generates a left shift
5646 as part of storing the argument in a register
5647 (the left shift isn't generated when
5648 sizeof (struct) >= mips_abi_regsize()). Since
5649 it is quite possible that this is GCC
5650 contradicting the LE/O32 ABI, GDB has not been
5651 adjusted to accommodate this. Either someone
5652 needs to demonstrate that the LE/O32 ABI
5653 specifies such a left shift OR this new ABI gets
5654 identified as such and GDB gets tweaked
5657 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
5658 && partial_len
< MIPS32_REGSIZE
5659 && (typecode
== TYPE_CODE_STRUCT
5660 || typecode
== TYPE_CODE_UNION
))
5661 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
5665 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
5667 phex (regval
, MIPS32_REGSIZE
));
5668 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5671 /* Prevent subsequent floating point arguments from
5672 being passed in floating point registers. */
5673 float_argreg
= mips_last_fp_arg_regnum (gdbarch
) + 1;
5679 /* Compute the offset into the stack at which we will
5680 copy the next parameter.
5682 In older ABIs, the caller reserved space for
5683 registers that contained arguments. This was loosely
5684 refered to as their "home". Consequently, space is
5685 always allocated. */
5687 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
5691 gdb_printf (gdb_stdlog
, "\n");
5694 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
5696 /* Return adjusted stack pointer. */
5700 static enum return_value_convention
5701 mips_o32_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
5702 struct type
*type
, struct regcache
*regcache
,
5703 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5705 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
5706 int mips16
= mips_pc_is_mips16 (gdbarch
, func_addr
);
5707 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
5708 enum mips_fval_reg fval_reg
;
5710 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
5711 if (type
->code () == TYPE_CODE_STRUCT
5712 || type
->code () == TYPE_CODE_UNION
5713 || type
->code () == TYPE_CODE_ARRAY
)
5714 return RETURN_VALUE_STRUCT_CONVENTION
;
5715 else if (type
->code () == TYPE_CODE_FLT
5716 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5718 /* A single-precision floating-point value. If reading in or copying,
5719 then we get it from/put it to FP0 for standard MIPS code or GPR2
5720 for MIPS16 code. If writing out only, then we put it to both FP0
5721 and GPR2. We do not support reading in with no function known, if
5722 this safety check ever triggers, then we'll have to try harder. */
5723 gdb_assert (function
|| !readbuf
);
5728 gdb_printf (gdb_stderr
, "Return float in $fp0\n");
5731 gdb_printf (gdb_stderr
, "Return float in $2\n");
5733 case mips_fval_both
:
5734 gdb_printf (gdb_stderr
, "Return float in $fp0 and $2\n");
5737 if (fval_reg
!= mips_fval_gpr
)
5738 mips_xfer_register (gdbarch
, regcache
,
5739 (gdbarch_num_regs (gdbarch
)
5740 + mips_regnum (gdbarch
)->fp0
),
5742 gdbarch_byte_order (gdbarch
),
5743 readbuf
, writebuf
, 0);
5744 if (fval_reg
!= mips_fval_fpr
)
5745 mips_xfer_register (gdbarch
, regcache
,
5746 gdbarch_num_regs (gdbarch
) + 2,
5748 gdbarch_byte_order (gdbarch
),
5749 readbuf
, writebuf
, 0);
5750 return RETURN_VALUE_REGISTER_CONVENTION
;
5752 else if (type
->code () == TYPE_CODE_FLT
5753 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5755 /* A double-precision floating-point value. If reading in or copying,
5756 then we get it from/put it to FP1 and FP0 for standard MIPS code or
5757 GPR2 and GPR3 for MIPS16 code. If writing out only, then we put it
5758 to both FP1/FP0 and GPR2/GPR3. We do not support reading in with
5759 no function known, if this safety check ever triggers, then we'll
5760 have to try harder. */
5761 gdb_assert (function
|| !readbuf
);
5766 gdb_printf (gdb_stderr
, "Return float in $fp1/$fp0\n");
5769 gdb_printf (gdb_stderr
, "Return float in $2/$3\n");
5771 case mips_fval_both
:
5772 gdb_printf (gdb_stderr
,
5773 "Return float in $fp1/$fp0 and $2/$3\n");
5776 if (fval_reg
!= mips_fval_gpr
)
5778 /* The most significant part goes in FP1, and the least significant
5780 switch (gdbarch_byte_order (gdbarch
))
5782 case BFD_ENDIAN_LITTLE
:
5783 mips_xfer_register (gdbarch
, regcache
,
5784 (gdbarch_num_regs (gdbarch
)
5785 + mips_regnum (gdbarch
)->fp0
+ 0),
5786 4, gdbarch_byte_order (gdbarch
),
5787 readbuf
, writebuf
, 0);
5788 mips_xfer_register (gdbarch
, regcache
,
5789 (gdbarch_num_regs (gdbarch
)
5790 + mips_regnum (gdbarch
)->fp0
+ 1),
5791 4, gdbarch_byte_order (gdbarch
),
5792 readbuf
, writebuf
, 4);
5794 case BFD_ENDIAN_BIG
:
5795 mips_xfer_register (gdbarch
, regcache
,
5796 (gdbarch_num_regs (gdbarch
)
5797 + mips_regnum (gdbarch
)->fp0
+ 1),
5798 4, gdbarch_byte_order (gdbarch
),
5799 readbuf
, writebuf
, 0);
5800 mips_xfer_register (gdbarch
, regcache
,
5801 (gdbarch_num_regs (gdbarch
)
5802 + mips_regnum (gdbarch
)->fp0
+ 0),
5803 4, gdbarch_byte_order (gdbarch
),
5804 readbuf
, writebuf
, 4);
5807 internal_error (__FILE__
, __LINE__
, _("bad switch"));
5810 if (fval_reg
!= mips_fval_fpr
)
5812 /* The two 32-bit parts are always placed in GPR2 and GPR3
5813 following these registers' memory order. */
5814 mips_xfer_register (gdbarch
, regcache
,
5815 gdbarch_num_regs (gdbarch
) + 2,
5816 4, gdbarch_byte_order (gdbarch
),
5817 readbuf
, writebuf
, 0);
5818 mips_xfer_register (gdbarch
, regcache
,
5819 gdbarch_num_regs (gdbarch
) + 3,
5820 4, gdbarch_byte_order (gdbarch
),
5821 readbuf
, writebuf
, 4);
5823 return RETURN_VALUE_REGISTER_CONVENTION
;
5826 else if (type
->code () == TYPE_CODE_STRUCT
5827 && type
->num_fields () <= 2
5828 && type
->num_fields () >= 1
5829 && ((type
->num_fields () == 1
5830 && (TYPE_CODE (type
->field (0).type ())
5832 || (type
->num_fields () == 2
5833 && (TYPE_CODE (type
->field (0).type ())
5835 && (TYPE_CODE (type
->field (1).type ())
5837 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5839 /* A struct that contains one or two floats. Each value is part
5840 in the least significant part of their floating point
5844 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
5845 field
< type
->num_fields (); field
++, regnum
+= 2)
5847 int offset
= (type
->fields ()[field
].loc_bitpos () / TARGET_CHAR_BIT
);
5849 gdb_printf (gdb_stderr
, "Return float struct+%d\n",
5851 mips_xfer_register (gdbarch
, regcache
,
5852 gdbarch_num_regs (gdbarch
) + regnum
,
5853 TYPE_LENGTH (type
->field (field
).type ()),
5854 gdbarch_byte_order (gdbarch
),
5855 readbuf
, writebuf
, offset
);
5857 return RETURN_VALUE_REGISTER_CONVENTION
;
5861 else if (type
->code () == TYPE_CODE_STRUCT
5862 || type
->code () == TYPE_CODE_UNION
)
5864 /* A structure or union. Extract the left justified value,
5865 regardless of the byte order. I.e. DO NOT USE
5869 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5870 offset
< TYPE_LENGTH (type
);
5871 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5873 int xfer
= register_size (gdbarch
, regnum
);
5874 if (offset
+ xfer
> TYPE_LENGTH (type
))
5875 xfer
= TYPE_LENGTH (type
) - offset
;
5877 gdb_printf (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5878 offset
, xfer
, regnum
);
5879 mips_xfer_register (gdbarch
, regcache
,
5880 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
5881 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
5883 return RETURN_VALUE_REGISTER_CONVENTION
;
5888 /* A scalar extract each part but least-significant-byte
5889 justified. o32 thinks registers are 4 byte, regardless of
5893 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5894 offset
< TYPE_LENGTH (type
);
5895 offset
+= MIPS32_REGSIZE
, regnum
++)
5897 int xfer
= MIPS32_REGSIZE
;
5898 if (offset
+ xfer
> TYPE_LENGTH (type
))
5899 xfer
= TYPE_LENGTH (type
) - offset
;
5901 gdb_printf (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5902 offset
, xfer
, regnum
);
5903 mips_xfer_register (gdbarch
, regcache
,
5904 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
5905 gdbarch_byte_order (gdbarch
),
5906 readbuf
, writebuf
, offset
);
5908 return RETURN_VALUE_REGISTER_CONVENTION
;
5912 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
5916 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
5917 struct regcache
*regcache
, CORE_ADDR bp_addr
,
5919 struct value
**args
, CORE_ADDR sp
,
5920 function_call_return_method return_method
, CORE_ADDR struct_addr
)
5926 int stack_offset
= 0;
5927 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5928 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
5930 /* For shared libraries, "t9" needs to point at the function
5932 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
5934 /* Set the return address register to point to the entry point of
5935 the program, where a breakpoint lies in wait. */
5936 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
5938 /* First ensure that the stack and structure return address (if any)
5939 are properly aligned. The stack has to be at least 64-bit
5940 aligned even on 32-bit machines, because doubles must be 64-bit
5941 aligned. For n32 and n64, stack frames need to be 128-bit
5942 aligned, so we round to this widest known alignment. */
5944 sp
= align_down (sp
, 16);
5945 struct_addr
= align_down (struct_addr
, 16);
5947 /* Now make space on the stack for the args. */
5948 for (argnum
= 0; argnum
< nargs
; argnum
++)
5950 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
5952 /* Allocate space on the stack. */
5953 arg_space
+= align_up (TYPE_LENGTH (arg_type
), MIPS64_REGSIZE
);
5955 sp
-= align_up (arg_space
, 16);
5958 gdb_printf (gdb_stdlog
,
5959 "mips_o64_push_dummy_call: sp=%s allocated %ld\n",
5960 paddress (gdbarch
, sp
),
5961 (long) align_up (arg_space
, 16));
5963 /* Initialize the integer and float register pointers. */
5964 argreg
= MIPS_A0_REGNUM
;
5965 float_argreg
= mips_fpa0_regnum (gdbarch
);
5967 /* The struct_return pointer occupies the first parameter-passing reg. */
5968 if (return_method
== return_method_struct
)
5971 gdb_printf (gdb_stdlog
,
5972 "mips_o64_push_dummy_call: "
5973 "struct_return reg=%d %s\n",
5974 argreg
, paddress (gdbarch
, struct_addr
));
5975 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
5976 stack_offset
+= MIPS64_REGSIZE
;
5979 /* Now load as many as possible of the first arguments into
5980 registers, and push the rest onto the stack. Loop thru args
5981 from first to last. */
5982 for (argnum
= 0; argnum
< nargs
; argnum
++)
5984 const gdb_byte
*val
;
5985 struct value
*arg
= args
[argnum
];
5986 struct type
*arg_type
= check_typedef (value_type (arg
));
5987 int len
= TYPE_LENGTH (arg_type
);
5988 enum type_code typecode
= arg_type
->code ();
5991 gdb_printf (gdb_stdlog
,
5992 "mips_o64_push_dummy_call: %d len=%d type=%d",
5993 argnum
+ 1, len
, (int) typecode
);
5995 val
= value_contents (arg
).data ();
5997 /* Floating point arguments passed in registers have to be
5998 treated specially. On 32-bit architectures, doubles are
5999 passed in register pairs; the even FP register gets the
6000 low word, and the odd FP register gets the high word.
6001 On O64, the first two floating point arguments are also
6002 copied to general registers, because MIPS16 functions
6003 don't use float registers for arguments. This duplication
6004 of arguments in general registers can't hurt non-MIPS16
6005 functions because those registers are normally skipped. */
6007 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
6008 && float_argreg
<= mips_last_fp_arg_regnum (gdbarch
))
6010 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
6012 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
6013 float_argreg
, phex (regval
, len
));
6014 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
6016 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
6017 argreg
, phex (regval
, len
));
6018 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
6020 /* Reserve space for the FP register. */
6021 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
6025 /* Copy the argument to general registers or the stack in
6026 register-sized pieces. Large arguments are split between
6027 registers and stack. */
6028 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
6029 are treated specially: Irix cc passes them in registers
6030 where gcc sometimes puts them on the stack. For maximum
6031 compatibility, we will put them in both places. */
6032 int odd_sized_struct
= (len
> MIPS64_REGSIZE
6033 && len
% MIPS64_REGSIZE
!= 0);
6036 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
6039 gdb_printf (gdb_stdlog
, " -- partial=%d",
6042 /* Write this portion of the argument to the stack. */
6043 if (argreg
> mips_last_arg_regnum (gdbarch
)
6044 || odd_sized_struct
)
6046 /* Should shorter than int integer values be
6047 promoted to int before being stored? */
6048 int longword_offset
= 0;
6050 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6052 if ((typecode
== TYPE_CODE_INT
6053 || typecode
== TYPE_CODE_PTR
6054 || typecode
== TYPE_CODE_FLT
)
6056 longword_offset
= MIPS64_REGSIZE
- len
;
6061 gdb_printf (gdb_stdlog
, " - stack_offset=%s",
6062 paddress (gdbarch
, stack_offset
));
6063 gdb_printf (gdb_stdlog
, " longword_offset=%s",
6064 paddress (gdbarch
, longword_offset
));
6067 addr
= sp
+ stack_offset
+ longword_offset
;
6072 gdb_printf (gdb_stdlog
, " @%s ",
6073 paddress (gdbarch
, addr
));
6074 for (i
= 0; i
< partial_len
; i
++)
6076 gdb_printf (gdb_stdlog
, "%02x",
6080 write_memory (addr
, val
, partial_len
);
6083 /* Note!!! This is NOT an else clause. Odd sized
6084 structs may go thru BOTH paths. */
6085 /* Write this portion of the argument to a general
6086 purpose register. */
6087 if (argreg
<= mips_last_arg_regnum (gdbarch
))
6089 LONGEST regval
= extract_signed_integer (val
, partial_len
,
6091 /* Value may need to be sign extended, because
6092 mips_isa_regsize() != mips_abi_regsize(). */
6094 /* A non-floating-point argument being passed in a
6095 general register. If a struct or union, and if
6096 the remaining length is smaller than the register
6097 size, we have to adjust the register value on
6100 It does not seem to be necessary to do the
6101 same for integral types. */
6103 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
6104 && partial_len
< MIPS64_REGSIZE
6105 && (typecode
== TYPE_CODE_STRUCT
6106 || typecode
== TYPE_CODE_UNION
))
6107 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
6111 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
6113 phex (regval
, MIPS64_REGSIZE
));
6114 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
6117 /* Prevent subsequent floating point arguments from
6118 being passed in floating point registers. */
6119 float_argreg
= mips_last_fp_arg_regnum (gdbarch
) + 1;
6125 /* Compute the offset into the stack at which we will
6126 copy the next parameter.
6128 In older ABIs, the caller reserved space for
6129 registers that contained arguments. This was loosely
6130 refered to as their "home". Consequently, space is
6131 always allocated. */
6133 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
6137 gdb_printf (gdb_stdlog
, "\n");
6140 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
6142 /* Return adjusted stack pointer. */
6146 static enum return_value_convention
6147 mips_o64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
6148 struct type
*type
, struct regcache
*regcache
,
6149 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
6151 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
6152 int mips16
= mips_pc_is_mips16 (gdbarch
, func_addr
);
6153 enum mips_fval_reg fval_reg
;
6155 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
6156 if (type
->code () == TYPE_CODE_STRUCT
6157 || type
->code () == TYPE_CODE_UNION
6158 || type
->code () == TYPE_CODE_ARRAY
)
6159 return RETURN_VALUE_STRUCT_CONVENTION
;
6160 else if (fp_register_arg_p (gdbarch
, type
->code (), type
))
6162 /* A floating-point value. If reading in or copying, then we get it
6163 from/put it to FP0 for standard MIPS code or GPR2 for MIPS16 code.
6164 If writing out only, then we put it to both FP0 and GPR2. We do
6165 not support reading in with no function known, if this safety
6166 check ever triggers, then we'll have to try harder. */
6167 gdb_assert (function
|| !readbuf
);
6172 gdb_printf (gdb_stderr
, "Return float in $fp0\n");
6175 gdb_printf (gdb_stderr
, "Return float in $2\n");
6177 case mips_fval_both
:
6178 gdb_printf (gdb_stderr
, "Return float in $fp0 and $2\n");
6181 if (fval_reg
!= mips_fval_gpr
)
6182 mips_xfer_register (gdbarch
, regcache
,
6183 (gdbarch_num_regs (gdbarch
)
6184 + mips_regnum (gdbarch
)->fp0
),
6186 gdbarch_byte_order (gdbarch
),
6187 readbuf
, writebuf
, 0);
6188 if (fval_reg
!= mips_fval_fpr
)
6189 mips_xfer_register (gdbarch
, regcache
,
6190 gdbarch_num_regs (gdbarch
) + 2,
6192 gdbarch_byte_order (gdbarch
),
6193 readbuf
, writebuf
, 0);
6194 return RETURN_VALUE_REGISTER_CONVENTION
;
6198 /* A scalar extract each part but least-significant-byte
6202 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
6203 offset
< TYPE_LENGTH (type
);
6204 offset
+= MIPS64_REGSIZE
, regnum
++)
6206 int xfer
= MIPS64_REGSIZE
;
6207 if (offset
+ xfer
> TYPE_LENGTH (type
))
6208 xfer
= TYPE_LENGTH (type
) - offset
;
6210 gdb_printf (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
6211 offset
, xfer
, regnum
);
6212 mips_xfer_register (gdbarch
, regcache
,
6213 gdbarch_num_regs (gdbarch
) + regnum
,
6214 xfer
, gdbarch_byte_order (gdbarch
),
6215 readbuf
, writebuf
, offset
);
6217 return RETURN_VALUE_REGISTER_CONVENTION
;
6221 /* Floating point register management.
6223 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
6224 64bit operations, these early MIPS cpus treat fp register pairs
6225 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
6226 registers and offer a compatibility mode that emulates the MIPS2 fp
6227 model. When operating in MIPS2 fp compat mode, later cpu's split
6228 double precision floats into two 32-bit chunks and store them in
6229 consecutive fp regs. To display 64-bit floats stored in this
6230 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
6231 Throw in user-configurable endianness and you have a real mess.
6233 The way this works is:
6234 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
6235 double-precision value will be split across two logical registers.
6236 The lower-numbered logical register will hold the low-order bits,
6237 regardless of the processor's endianness.
6238 - If we are on a 64-bit processor, and we are looking for a
6239 single-precision value, it will be in the low ordered bits
6240 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
6241 save slot in memory.
6242 - If we are in 64-bit mode, everything is straightforward.
6244 Note that this code only deals with "live" registers at the top of the
6245 stack. We will attempt to deal with saved registers later, when
6246 the raw/cooked register interface is in place. (We need a general
6247 interface that can deal with dynamic saved register sizes -- fp
6248 regs could be 32 bits wide in one frame and 64 on the frame above
6251 /* Copy a 32-bit single-precision value from the current frame
6252 into rare_buffer. */
6255 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
6256 gdb_byte
*rare_buffer
)
6258 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6259 int raw_size
= register_size (gdbarch
, regno
);
6260 gdb_byte
*raw_buffer
= (gdb_byte
*) alloca (raw_size
);
6262 if (!deprecated_frame_register_read (frame
, regno
, raw_buffer
))
6263 error (_("can't read register %d (%s)"),
6264 regno
, gdbarch_register_name (gdbarch
, regno
));
6267 /* We have a 64-bit value for this register. Find the low-order
6271 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6276 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
6280 memcpy (rare_buffer
, raw_buffer
, 4);
6284 /* Copy a 64-bit double-precision value from the current frame into
6285 rare_buffer. This may include getting half of it from the next
6289 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
6290 gdb_byte
*rare_buffer
)
6292 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6293 int raw_size
= register_size (gdbarch
, regno
);
6295 if (raw_size
== 8 && !mips2_fp_compat (frame
))
6297 /* We have a 64-bit value for this register, and we should use
6299 if (!deprecated_frame_register_read (frame
, regno
, rare_buffer
))
6300 error (_("can't read register %d (%s)"),
6301 regno
, gdbarch_register_name (gdbarch
, regno
));
6305 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
6307 if ((rawnum
- mips_regnum (gdbarch
)->fp0
) & 1)
6308 internal_error (__FILE__
, __LINE__
,
6309 _("mips_read_fp_register_double: bad access to "
6310 "odd-numbered FP register"));
6312 /* mips_read_fp_register_single will find the correct 32 bits from
6314 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6316 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
6317 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
6321 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
6322 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
6328 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
6330 { /* Do values for FP (float) regs. */
6331 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6332 gdb_byte
*raw_buffer
;
6333 std::string flt_str
, dbl_str
;
6335 const struct type
*flt_type
= builtin_type (gdbarch
)->builtin_float
;
6336 const struct type
*dbl_type
= builtin_type (gdbarch
)->builtin_double
;
6340 alloca (2 * register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
)));
6342 gdb_printf (file
, "%s:", gdbarch_register_name (gdbarch
, regnum
));
6343 gdb_printf (file
, "%*s",
6344 4 - (int) strlen (gdbarch_register_name (gdbarch
, regnum
)),
6347 if (register_size (gdbarch
, regnum
) == 4 || mips2_fp_compat (frame
))
6349 struct value_print_options opts
;
6351 /* 4-byte registers: Print hex and floating. Also print even
6352 numbered registers as doubles. */
6353 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
6354 flt_str
= target_float_to_string (raw_buffer
, flt_type
, "%-17.9g");
6356 get_formatted_print_options (&opts
, 'x');
6357 print_scalar_formatted (raw_buffer
,
6358 builtin_type (gdbarch
)->builtin_uint32
,
6361 gdb_printf (file
, " flt: %s", flt_str
.c_str ());
6363 if ((regnum
- gdbarch_num_regs (gdbarch
)) % 2 == 0)
6365 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
6366 dbl_str
= target_float_to_string (raw_buffer
, dbl_type
, "%-24.17g");
6368 gdb_printf (file
, " dbl: %s", dbl_str
.c_str ());
6373 struct value_print_options opts
;
6375 /* Eight byte registers: print each one as hex, float and double. */
6376 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
6377 flt_str
= target_float_to_string (raw_buffer
, flt_type
, "%-17.9g");
6379 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
6380 dbl_str
= target_float_to_string (raw_buffer
, dbl_type
, "%-24.17g");
6382 get_formatted_print_options (&opts
, 'x');
6383 print_scalar_formatted (raw_buffer
,
6384 builtin_type (gdbarch
)->builtin_uint64
,
6387 gdb_printf (file
, " flt: %s", flt_str
.c_str ());
6388 gdb_printf (file
, " dbl: %s", dbl_str
.c_str ());
6393 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
6396 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6397 struct value_print_options opts
;
6400 if (mips_float_register_p (gdbarch
, regnum
))
6402 mips_print_fp_register (file
, frame
, regnum
);
6406 val
= get_frame_register_value (frame
, regnum
);
6408 gdb_puts (gdbarch_register_name (gdbarch
, regnum
), file
);
6410 /* The problem with printing numeric register names (r26, etc.) is that
6411 the user can't use them on input. Probably the best solution is to
6412 fix it so that either the numeric or the funky (a2, etc.) names
6413 are accepted on input. */
6414 if (regnum
< MIPS_NUMREGS
)
6415 gdb_printf (file
, "(r%d): ", regnum
);
6417 gdb_printf (file
, ": ");
6419 get_formatted_print_options (&opts
, 'x');
6420 value_print_scalar_formatted (val
, &opts
, 0, file
);
6423 /* Print IEEE exception condition bits in FLAGS. */
6426 print_fpu_flags (struct ui_file
*file
, int flags
)
6428 if (flags
& (1 << 0))
6429 gdb_puts (" inexact", file
);
6430 if (flags
& (1 << 1))
6431 gdb_puts (" uflow", file
);
6432 if (flags
& (1 << 2))
6433 gdb_puts (" oflow", file
);
6434 if (flags
& (1 << 3))
6435 gdb_puts (" div0", file
);
6436 if (flags
& (1 << 4))
6437 gdb_puts (" inval", file
);
6438 if (flags
& (1 << 5))
6439 gdb_puts (" unimp", file
);
6440 gdb_putc ('\n', file
);
6443 /* Print interesting information about the floating point processor
6444 (if present) or emulator. */
6447 mips_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
6448 struct frame_info
*frame
, const char *args
)
6450 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
6451 enum mips_fpu_type type
= mips_get_fpu_type (gdbarch
);
6455 if (fcsr
== -1 || !read_frame_register_unsigned (frame
, fcsr
, &fcs
))
6456 type
= MIPS_FPU_NONE
;
6458 gdb_printf (file
, "fpu type: %s\n",
6459 type
== MIPS_FPU_DOUBLE
? "double-precision"
6460 : type
== MIPS_FPU_SINGLE
? "single-precision"
6463 if (type
== MIPS_FPU_NONE
)
6466 gdb_printf (file
, "reg size: %d bits\n",
6467 register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) * 8);
6469 gdb_puts ("cond :", file
);
6470 if (fcs
& (1 << 23))
6471 gdb_puts (" 0", file
);
6472 for (i
= 1; i
<= 7; i
++)
6473 if (fcs
& (1 << (24 + i
)))
6474 gdb_printf (file
, " %d", i
);
6475 gdb_putc ('\n', file
);
6477 gdb_puts ("cause :", file
);
6478 print_fpu_flags (file
, (fcs
>> 12) & 0x3f);
6479 fputs ("mask :", stdout
);
6480 print_fpu_flags (file
, (fcs
>> 7) & 0x1f);
6481 fputs ("flags :", stdout
);
6482 print_fpu_flags (file
, (fcs
>> 2) & 0x1f);
6484 gdb_puts ("rounding: ", file
);
6487 case 0: gdb_puts ("nearest\n", file
); break;
6488 case 1: gdb_puts ("zero\n", file
); break;
6489 case 2: gdb_puts ("+inf\n", file
); break;
6490 case 3: gdb_puts ("-inf\n", file
); break;
6493 gdb_puts ("flush :", file
);
6494 if (fcs
& (1 << 21))
6495 gdb_puts (" nearest", file
);
6496 if (fcs
& (1 << 22))
6497 gdb_puts (" override", file
);
6498 if (fcs
& (1 << 24))
6499 gdb_puts (" zero", file
);
6500 if ((fcs
& (0xb << 21)) == 0)
6501 gdb_puts (" no", file
);
6502 gdb_putc ('\n', file
);
6504 gdb_printf (file
, "nan2008 : %s\n", fcs
& (1 << 18) ? "yes" : "no");
6505 gdb_printf (file
, "abs2008 : %s\n", fcs
& (1 << 19) ? "yes" : "no");
6506 gdb_putc ('\n', file
);
6508 default_print_float_info (gdbarch
, file
, frame
, args
);
6511 /* Replacement for generic do_registers_info.
6512 Print regs in pretty columns. */
6515 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
6518 gdb_printf (file
, " ");
6519 mips_print_fp_register (file
, frame
, regnum
);
6520 gdb_printf (file
, "\n");
6525 /* Print a row's worth of GP (int) registers, with name labels above. */
6528 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
6531 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6532 /* Do values for GP (int) regs. */
6533 const gdb_byte
*raw_buffer
;
6534 struct value
*value
;
6535 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols
6540 /* For GP registers, we print a separate row of names above the vals. */
6541 for (col
= 0, regnum
= start_regnum
;
6542 col
< ncols
&& regnum
< gdbarch_num_cooked_regs (gdbarch
);
6545 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
6546 continue; /* unused register */
6547 if (mips_float_register_p (gdbarch
, regnum
))
6548 break; /* End the row: reached FP register. */
6549 /* Large registers are handled separately. */
6550 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
6553 break; /* End the row before this register. */
6555 /* Print this register on a row by itself. */
6556 mips_print_register (file
, frame
, regnum
);
6557 gdb_printf (file
, "\n");
6561 gdb_printf (file
, " ");
6563 mips_abi_regsize (gdbarch
) == 8 ? "%17s" : "%9s",
6564 gdbarch_register_name (gdbarch
, regnum
));
6571 /* Print the R0 to R31 names. */
6572 if ((start_regnum
% gdbarch_num_regs (gdbarch
)) < MIPS_NUMREGS
)
6573 gdb_printf (file
, "\n R%-4d",
6574 start_regnum
% gdbarch_num_regs (gdbarch
));
6576 gdb_printf (file
, "\n ");
6578 /* Now print the values in hex, 4 or 8 to the row. */
6579 for (col
= 0, regnum
= start_regnum
;
6580 col
< ncols
&& regnum
< gdbarch_num_cooked_regs (gdbarch
);
6583 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
6584 continue; /* unused register */
6585 if (mips_float_register_p (gdbarch
, regnum
))
6586 break; /* End row: reached FP register. */
6587 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
6588 break; /* End row: large register. */
6590 /* OK: get the data in raw format. */
6591 value
= get_frame_register_value (frame
, regnum
);
6592 if (value_optimized_out (value
)
6593 || !value_entirely_available (value
))
6595 gdb_printf (file
, "%*s ",
6596 (int) mips_abi_regsize (gdbarch
) * 2,
6597 (mips_abi_regsize (gdbarch
) == 4 ? "<unavl>"
6598 : "<unavailable>"));
6602 raw_buffer
= value_contents_all (value
).data ();
6603 /* pad small registers */
6605 byte
< (mips_abi_regsize (gdbarch
)
6606 - register_size (gdbarch
, regnum
)); byte
++)
6607 gdb_printf (file
, " ");
6608 /* Now print the register value in hex, endian order. */
6609 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6611 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
6612 byte
< register_size (gdbarch
, regnum
); byte
++)
6613 gdb_printf (file
, "%02x", raw_buffer
[byte
]);
6615 for (byte
= register_size (gdbarch
, regnum
) - 1;
6617 gdb_printf (file
, "%02x", raw_buffer
[byte
]);
6618 gdb_printf (file
, " ");
6621 if (col
> 0) /* ie. if we actually printed anything... */
6622 gdb_printf (file
, "\n");
6627 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */
6630 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
6631 struct frame_info
*frame
, int regnum
, int all
)
6633 if (regnum
!= -1) /* Do one specified register. */
6635 gdb_assert (regnum
>= gdbarch_num_regs (gdbarch
));
6636 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
6637 error (_("Not a valid register for the current processor type"));
6639 mips_print_register (file
, frame
, regnum
);
6640 gdb_printf (file
, "\n");
6643 /* Do all (or most) registers. */
6645 regnum
= gdbarch_num_regs (gdbarch
);
6646 while (regnum
< gdbarch_num_cooked_regs (gdbarch
))
6648 if (mips_float_register_p (gdbarch
, regnum
))
6650 if (all
) /* True for "INFO ALL-REGISTERS" command. */
6651 regnum
= print_fp_register_row (file
, frame
, regnum
);
6653 regnum
+= MIPS_NUMREGS
; /* Skip floating point regs. */
6656 regnum
= print_gp_register_row (file
, frame
, regnum
);
6662 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
6663 struct frame_info
*frame
)
6665 CORE_ADDR pc
= get_frame_pc (frame
);
6670 if ((mips_pc_is_mips (pc
)
6671 && !mips32_insn_at_pc_has_delay_slot (gdbarch
, pc
))
6672 || (mips_pc_is_micromips (gdbarch
, pc
)
6673 && !micromips_insn_at_pc_has_delay_slot (gdbarch
, pc
, 0))
6674 || (mips_pc_is_mips16 (gdbarch
, pc
)
6675 && !mips16_insn_at_pc_has_delay_slot (gdbarch
, pc
, 0)))
6678 isa
= mips_pc_isa (gdbarch
, pc
);
6679 /* _has_delay_slot above will have validated the read. */
6680 insn
= mips_fetch_instruction (gdbarch
, isa
, pc
, NULL
);
6681 size
= mips_insn_size (isa
, insn
);
6683 const address_space
*aspace
= get_frame_address_space (frame
);
6685 return breakpoint_here_p (aspace
, pc
+ size
) != no_breakpoint_here
;
6688 /* To skip prologues, I use this predicate. Returns either PC itself
6689 if the code at PC does not look like a function prologue; otherwise
6690 returns an address that (if we're lucky) follows the prologue. If
6691 LENIENT, then we must skip everything which is involved in setting
6692 up the frame (it's OK to skip more, just so long as we don't skip
6693 anything which might clobber the registers which are being saved.
6694 We must skip more in the case where part of the prologue is in the
6695 delay slot of a non-prologue instruction). */
6698 mips_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6701 CORE_ADDR func_addr
;
6703 /* See if we can determine the end of the prologue via the symbol table.
6704 If so, then return either PC, or the PC after the prologue, whichever
6706 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
6708 CORE_ADDR post_prologue_pc
6709 = skip_prologue_using_sal (gdbarch
, func_addr
);
6710 if (post_prologue_pc
!= 0)
6711 return std::max (pc
, post_prologue_pc
);
6714 /* Can't determine prologue from the symbol table, need to examine
6717 /* Find an upper limit on the function prologue using the debug
6718 information. If the debug information could not be used to provide
6719 that bound, then use an arbitrary large number as the upper bound. */
6720 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
6722 limit_pc
= pc
+ 100; /* Magic. */
6724 if (mips_pc_is_mips16 (gdbarch
, pc
))
6725 return mips16_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6726 else if (mips_pc_is_micromips (gdbarch
, pc
))
6727 return micromips_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6729 return mips32_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6732 /* Implement the stack_frame_destroyed_p gdbarch method (32-bit version).
6733 This is a helper function for mips_stack_frame_destroyed_p. */
6736 mips32_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6738 CORE_ADDR func_addr
= 0, func_end
= 0;
6740 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6742 /* The MIPS epilogue is max. 12 bytes long. */
6743 CORE_ADDR addr
= func_end
- 12;
6745 if (addr
< func_addr
+ 4)
6746 addr
= func_addr
+ 4;
6750 for (; pc
< func_end
; pc
+= MIPS_INSN32_SIZE
)
6752 unsigned long high_word
;
6755 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
6756 high_word
= (inst
>> 16) & 0xffff;
6758 if (high_word
!= 0x27bd /* addiu $sp,$sp,offset */
6759 && high_word
!= 0x67bd /* daddiu $sp,$sp,offset */
6760 && inst
!= 0x03e00008 /* jr $ra */
6761 && inst
!= 0x00000000) /* nop */
6771 /* Implement the stack_frame_destroyed_p gdbarch method (microMIPS version).
6772 This is a helper function for mips_stack_frame_destroyed_p. */
6775 micromips_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6777 CORE_ADDR func_addr
= 0;
6778 CORE_ADDR func_end
= 0;
6786 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6789 /* The microMIPS epilogue is max. 12 bytes long. */
6790 addr
= func_end
- 12;
6792 if (addr
< func_addr
+ 2)
6793 addr
= func_addr
+ 2;
6797 for (; pc
< func_end
; pc
+= loc
)
6800 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
6801 loc
+= MIPS_INSN16_SIZE
;
6802 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
6804 /* 32-bit instructions. */
6805 case 2 * MIPS_INSN16_SIZE
:
6807 insn
|= mips_fetch_instruction (gdbarch
,
6808 ISA_MICROMIPS
, pc
+ loc
, NULL
);
6809 loc
+= MIPS_INSN16_SIZE
;
6810 switch (micromips_op (insn
>> 16))
6812 case 0xc: /* ADDIU: bits 001100 */
6813 case 0x17: /* DADDIU: bits 010111 */
6814 sreg
= b0s5_reg (insn
>> 16);
6815 dreg
= b5s5_reg (insn
>> 16);
6816 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
6817 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
6818 /* (D)ADDIU $sp, imm */
6828 /* 16-bit instructions. */
6829 case MIPS_INSN16_SIZE
:
6830 switch (micromips_op (insn
))
6832 case 0x3: /* MOVE: bits 000011 */
6833 sreg
= b0s5_reg (insn
);
6834 dreg
= b5s5_reg (insn
);
6835 if (sreg
== 0 && dreg
== 0)
6836 /* MOVE $zero, $zero aka NOP */
6840 case 0x11: /* POOL16C: bits 010001 */
6841 if (b5s5_op (insn
) == 0x18
6842 /* JRADDIUSP: bits 010011 11000 */
6843 || (b5s5_op (insn
) == 0xd
6844 /* JRC: bits 010011 01101 */
6845 && b0s5_reg (insn
) == MIPS_RA_REGNUM
))
6850 case 0x13: /* POOL16D: bits 010011 */
6851 offset
= micromips_decode_imm9 (b1s9_imm (insn
));
6852 if ((insn
& 0x1) == 0x1
6853 /* ADDIUSP: bits 010011 1 */
6867 /* Implement the stack_frame_destroyed_p gdbarch method (16-bit version).
6868 This is a helper function for mips_stack_frame_destroyed_p. */
6871 mips16_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6873 CORE_ADDR func_addr
= 0, func_end
= 0;
6875 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6877 /* The MIPS epilogue is max. 12 bytes long. */
6878 CORE_ADDR addr
= func_end
- 12;
6880 if (addr
< func_addr
+ 4)
6881 addr
= func_addr
+ 4;
6885 for (; pc
< func_end
; pc
+= MIPS_INSN16_SIZE
)
6887 unsigned short inst
;
6889 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, pc
, NULL
);
6891 if ((inst
& 0xf800) == 0xf000) /* extend */
6894 if (inst
!= 0x6300 /* addiu $sp,offset */
6895 && inst
!= 0xfb00 /* daddiu $sp,$sp,offset */
6896 && inst
!= 0xe820 /* jr $ra */
6897 && inst
!= 0xe8a0 /* jrc $ra */
6898 && inst
!= 0x6500) /* nop */
6908 /* Implement the stack_frame_destroyed_p gdbarch method.
6910 The epilogue is defined here as the area at the end of a function,
6911 after an instruction which destroys the function's stack frame. */
6914 mips_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6916 if (mips_pc_is_mips16 (gdbarch
, pc
))
6917 return mips16_stack_frame_destroyed_p (gdbarch
, pc
);
6918 else if (mips_pc_is_micromips (gdbarch
, pc
))
6919 return micromips_stack_frame_destroyed_p (gdbarch
, pc
);
6921 return mips32_stack_frame_destroyed_p (gdbarch
, pc
);
6924 /* Commands to show/set the MIPS FPU type. */
6927 show_mipsfpu_command (const char *args
, int from_tty
)
6931 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_mips
)
6934 ("The MIPS floating-point coprocessor is unknown "
6935 "because the current architecture is not MIPS.\n");
6939 switch (mips_get_fpu_type (target_gdbarch ()))
6941 case MIPS_FPU_SINGLE
:
6942 fpu
= "single-precision";
6944 case MIPS_FPU_DOUBLE
:
6945 fpu
= "double-precision";
6948 fpu
= "absent (none)";
6951 internal_error (__FILE__
, __LINE__
, _("bad switch"));
6953 if (mips_fpu_type_auto
)
6954 gdb_printf ("The MIPS floating-point coprocessor "
6955 "is set automatically (currently %s)\n",
6959 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
6964 set_mipsfpu_single_command (const char *args
, int from_tty
)
6966 struct gdbarch_info info
;
6967 mips_fpu_type
= MIPS_FPU_SINGLE
;
6968 mips_fpu_type_auto
= 0;
6969 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6970 instead of relying on globals. Doing that would let generic code
6971 handle the search for this specific architecture. */
6972 if (!gdbarch_update_p (info
))
6973 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6977 set_mipsfpu_double_command (const char *args
, int from_tty
)
6979 struct gdbarch_info info
;
6980 mips_fpu_type
= MIPS_FPU_DOUBLE
;
6981 mips_fpu_type_auto
= 0;
6982 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6983 instead of relying on globals. Doing that would let generic code
6984 handle the search for this specific architecture. */
6985 if (!gdbarch_update_p (info
))
6986 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6990 set_mipsfpu_none_command (const char *args
, int from_tty
)
6992 struct gdbarch_info info
;
6993 mips_fpu_type
= MIPS_FPU_NONE
;
6994 mips_fpu_type_auto
= 0;
6995 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6996 instead of relying on globals. Doing that would let generic code
6997 handle the search for this specific architecture. */
6998 if (!gdbarch_update_p (info
))
6999 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
7003 set_mipsfpu_auto_command (const char *args
, int from_tty
)
7005 mips_fpu_type_auto
= 1;
7008 /* Just like reinit_frame_cache, but with the right arguments to be
7009 callable as an sfunc. */
7012 reinit_frame_cache_sfunc (const char *args
, int from_tty
,
7013 struct cmd_list_element
*c
)
7015 reinit_frame_cache ();
7019 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
7021 gdb_disassembler
*di
7022 = static_cast<gdb_disassembler
*>(info
->application_data
);
7023 struct gdbarch
*gdbarch
= di
->arch ();
7025 /* FIXME: cagney/2003-06-26: Is this even necessary? The
7026 disassembler needs to be able to locally determine the ISA, and
7027 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
7029 if (mips_pc_is_mips16 (gdbarch
, memaddr
))
7030 info
->mach
= bfd_mach_mips16
;
7031 else if (mips_pc_is_micromips (gdbarch
, memaddr
))
7032 info
->mach
= bfd_mach_mips_micromips
;
7034 /* Round down the instruction address to the appropriate boundary. */
7035 memaddr
&= (info
->mach
== bfd_mach_mips16
7036 || info
->mach
== bfd_mach_mips_micromips
) ? ~1 : ~3;
7038 return default_print_insn (memaddr
, info
);
7041 /* Implement the breakpoint_kind_from_pc gdbarch method. */
7044 mips_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
7046 CORE_ADDR pc
= *pcptr
;
7048 if (mips_pc_is_mips16 (gdbarch
, pc
))
7050 *pcptr
= unmake_compact_addr (pc
);
7051 return MIPS_BP_KIND_MIPS16
;
7053 else if (mips_pc_is_micromips (gdbarch
, pc
))
7058 *pcptr
= unmake_compact_addr (pc
);
7059 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, &status
);
7060 if (status
|| (mips_insn_size (ISA_MICROMIPS
, insn
) == 2))
7061 return MIPS_BP_KIND_MICROMIPS16
;
7063 return MIPS_BP_KIND_MICROMIPS32
;
7066 return MIPS_BP_KIND_MIPS32
;
7069 /* Implement the sw_breakpoint_from_kind gdbarch method. */
7071 static const gdb_byte
*
7072 mips_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
7074 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
7078 case MIPS_BP_KIND_MIPS16
:
7080 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
7081 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
7084 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7085 return mips16_big_breakpoint
;
7087 return mips16_little_breakpoint
;
7089 case MIPS_BP_KIND_MICROMIPS16
:
7091 static gdb_byte micromips16_big_breakpoint
[] = { 0x46, 0x85 };
7092 static gdb_byte micromips16_little_breakpoint
[] = { 0x85, 0x46 };
7096 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7097 return micromips16_big_breakpoint
;
7099 return micromips16_little_breakpoint
;
7101 case MIPS_BP_KIND_MICROMIPS32
:
7103 static gdb_byte micromips32_big_breakpoint
[] = { 0, 0x5, 0, 0x7 };
7104 static gdb_byte micromips32_little_breakpoint
[] = { 0x5, 0, 0x7, 0 };
7107 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7108 return micromips32_big_breakpoint
;
7110 return micromips32_little_breakpoint
;
7112 case MIPS_BP_KIND_MIPS32
:
7114 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
7115 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
7118 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7119 return big_breakpoint
;
7121 return little_breakpoint
;
7124 gdb_assert_not_reached ("unexpected mips breakpoint kind");
7128 /* Return non-zero if the standard MIPS instruction INST has a branch
7129 delay slot (i.e. it is a jump or branch instruction). This function
7130 is based on mips32_next_pc. */
7133 mips32_instruction_has_delay_slot (struct gdbarch
*gdbarch
, ULONGEST inst
)
7139 op
= itype_op (inst
);
7140 if ((inst
& 0xe0000000) != 0)
7142 rs
= itype_rs (inst
);
7143 rt
= itype_rt (inst
);
7144 return (is_octeon_bbit_op (op
, gdbarch
)
7145 || op
>> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
7146 || op
== 29 /* JALX: bits 011101 */
7149 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
7150 || (rs
== 9 && (rt
& 0x2) == 0)
7151 /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */
7152 || (rs
== 10 && (rt
& 0x2) == 0))));
7153 /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */
7156 switch (op
& 0x07) /* extract bits 28,27,26 */
7158 case 0: /* SPECIAL */
7159 op
= rtype_funct (inst
);
7160 return (op
== 8 /* JR */
7161 || op
== 9); /* JALR */
7162 break; /* end SPECIAL */
7163 case 1: /* REGIMM */
7164 rs
= itype_rs (inst
);
7165 rt
= itype_rt (inst
); /* branch condition */
7166 return ((rt
& 0xc) == 0
7167 /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */
7168 /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */
7169 || ((rt
& 0x1e) == 0x1c && rs
== 0));
7170 /* BPOSGE32, BPOSGE64: bits 1110x */
7171 break; /* end REGIMM */
7172 default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */
7178 /* Return non-zero if a standard MIPS instruction at ADDR has a branch
7179 delay slot (i.e. it is a jump or branch instruction). */
7182 mips32_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
7187 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, addr
, &status
);
7191 return mips32_instruction_has_delay_slot (gdbarch
, insn
);
7194 /* Return non-zero if the microMIPS instruction INSN, comprising the
7195 16-bit major opcode word in the high 16 bits and any second word
7196 in the low 16 bits, has a branch delay slot (i.e. it is a non-compact
7197 jump or branch instruction). The instruction must be 32-bit if
7198 MUSTBE32 is set or can be any instruction otherwise. */
7201 micromips_instruction_has_delay_slot (ULONGEST insn
, int mustbe32
)
7203 ULONGEST major
= insn
>> 16;
7205 switch (micromips_op (major
))
7207 /* 16-bit instructions. */
7208 case 0x33: /* B16: bits 110011 */
7209 case 0x2b: /* BNEZ16: bits 101011 */
7210 case 0x23: /* BEQZ16: bits 100011 */
7212 case 0x11: /* POOL16C: bits 010001 */
7214 && ((b5s5_op (major
) == 0xc
7215 /* JR16: bits 010001 01100 */
7216 || (b5s5_op (major
) & 0x1e) == 0xe)));
7217 /* JALR16, JALRS16: bits 010001 0111x */
7218 /* 32-bit instructions. */
7219 case 0x3d: /* JAL: bits 111101 */
7220 case 0x3c: /* JALX: bits 111100 */
7221 case 0x35: /* J: bits 110101 */
7222 case 0x2d: /* BNE: bits 101101 */
7223 case 0x25: /* BEQ: bits 100101 */
7224 case 0x1d: /* JALS: bits 011101 */
7226 case 0x10: /* POOL32I: bits 010000 */
7227 return ((b5s5_op (major
) & 0x1c) == 0x0
7228 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
7229 || (b5s5_op (major
) & 0x1d) == 0x4
7230 /* BLEZ, BGTZ: bits 010000 001x0 */
7231 || (b5s5_op (major
) & 0x1d) == 0x11
7232 /* BLTZALS, BGEZALS: bits 010000 100x1 */
7233 || ((b5s5_op (major
) & 0x1e) == 0x14
7234 && (major
& 0x3) == 0x0)
7235 /* BC2F, BC2T: bits 010000 1010x xxx00 */
7236 || (b5s5_op (major
) & 0x1e) == 0x1a
7237 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
7238 || ((b5s5_op (major
) & 0x1e) == 0x1c
7239 && (major
& 0x3) == 0x0)
7240 /* BC1F, BC1T: bits 010000 1110x xxx00 */
7241 || ((b5s5_op (major
) & 0x1c) == 0x1c
7242 && (major
& 0x3) == 0x1));
7243 /* BC1ANY*: bits 010000 111xx xxx01 */
7244 case 0x0: /* POOL32A: bits 000000 */
7245 return (b0s6_op (insn
) == 0x3c
7246 /* POOL32Axf: bits 000000 ... 111100 */
7247 && (b6s10_ext (insn
) & 0x2bf) == 0x3c);
7248 /* JALR, JALR.HB: 000000 000x111100 111100 */
7249 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
7255 /* Return non-zero if a microMIPS instruction at ADDR has a branch delay
7256 slot (i.e. it is a non-compact jump instruction). The instruction
7257 must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */
7260 micromips_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
7261 CORE_ADDR addr
, int mustbe32
)
7267 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, addr
, &status
);
7270 size
= mips_insn_size (ISA_MICROMIPS
, insn
);
7272 if (size
== 2 * MIPS_INSN16_SIZE
)
7274 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, addr
, &status
);
7279 return micromips_instruction_has_delay_slot (insn
, mustbe32
);
7282 /* Return non-zero if the MIPS16 instruction INST, which must be
7283 a 32-bit instruction if MUSTBE32 is set or can be any instruction
7284 otherwise, has a branch delay slot (i.e. it is a non-compact jump
7285 instruction). This function is based on mips16_next_pc. */
7288 mips16_instruction_has_delay_slot (unsigned short inst
, int mustbe32
)
7290 if ((inst
& 0xf89f) == 0xe800) /* JR/JALR (16-bit instruction) */
7292 return (inst
& 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */
7295 /* Return non-zero if a MIPS16 instruction at ADDR has a branch delay
7296 slot (i.e. it is a non-compact jump instruction). The instruction
7297 must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */
7300 mips16_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
7301 CORE_ADDR addr
, int mustbe32
)
7303 unsigned short insn
;
7306 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, addr
, &status
);
7310 return mips16_instruction_has_delay_slot (insn
, mustbe32
);
7313 /* Calculate the starting address of the MIPS memory segment BPADDR is in.
7314 This assumes KSSEG exists. */
7317 mips_segment_boundary (CORE_ADDR bpaddr
)
7319 CORE_ADDR mask
= CORE_ADDR_MAX
;
7322 if (sizeof (CORE_ADDR
) == 8)
7323 /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid
7324 a compiler warning produced where CORE_ADDR is a 32-bit type even
7325 though in that case this is dead code). */
7326 switch (bpaddr
>> ((sizeof (CORE_ADDR
) << 3) - 2) & 3)
7329 if (bpaddr
== (bfd_signed_vma
) (int32_t) bpaddr
)
7330 segsize
= 29; /* 32-bit compatibility segment */
7332 segsize
= 62; /* xkseg */
7334 case 2: /* xkphys */
7337 default: /* xksseg (1), xkuseg/kuseg (0) */
7341 else if (bpaddr
& 0x80000000) /* kernel segment */
7344 segsize
= 31; /* user segment */
7346 return bpaddr
& mask
;
7349 /* Move the breakpoint at BPADDR out of any branch delay slot by shifting
7350 it backwards if necessary. Return the address of the new location. */
7353 mips_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
7355 CORE_ADDR prev_addr
;
7357 CORE_ADDR func_addr
;
7359 /* If a breakpoint is set on the instruction in a branch delay slot,
7360 GDB gets confused. When the breakpoint is hit, the PC isn't on
7361 the instruction in the branch delay slot, the PC will point to
7362 the branch instruction. Since the PC doesn't match any known
7363 breakpoints, GDB reports a trap exception.
7365 There are two possible fixes for this problem.
7367 1) When the breakpoint gets hit, see if the BD bit is set in the
7368 Cause register (which indicates the last exception occurred in a
7369 branch delay slot). If the BD bit is set, fix the PC to point to
7370 the instruction in the branch delay slot.
7372 2) When the user sets the breakpoint, don't allow him to set the
7373 breakpoint on the instruction in the branch delay slot. Instead
7374 move the breakpoint to the branch instruction (which will have
7377 The problem with the first solution is that if the user then
7378 single-steps the processor, the branch instruction will get
7379 skipped (since GDB thinks the PC is on the instruction in the
7382 So, we'll use the second solution. To do this we need to know if
7383 the instruction we're trying to set the breakpoint on is in the
7384 branch delay slot. */
7386 boundary
= mips_segment_boundary (bpaddr
);
7388 /* Make sure we don't scan back before the beginning of the current
7389 function, since we may fetch constant data or insns that look like
7390 a jump. Of course we might do that anyway if the compiler has
7391 moved constants inline. :-( */
7392 if (find_pc_partial_function (bpaddr
, NULL
, &func_addr
, NULL
)
7393 && func_addr
> boundary
&& func_addr
<= bpaddr
)
7394 boundary
= func_addr
;
7396 if (mips_pc_is_mips (bpaddr
))
7398 if (bpaddr
== boundary
)
7401 /* If the previous instruction has a branch delay slot, we have
7402 to move the breakpoint to the branch instruction. */
7403 prev_addr
= bpaddr
- 4;
7404 if (mips32_insn_at_pc_has_delay_slot (gdbarch
, prev_addr
))
7409 int (*insn_at_pc_has_delay_slot
) (struct gdbarch
*, CORE_ADDR
, int);
7410 CORE_ADDR addr
, jmpaddr
;
7413 boundary
= unmake_compact_addr (boundary
);
7415 /* The only MIPS16 instructions with delay slots are JAL, JALX,
7416 JALR and JR. An absolute JAL/JALX is always 4 bytes long,
7417 so try for that first, then try the 2 byte JALR/JR.
7418 The microMIPS ASE has a whole range of jumps and branches
7419 with delay slots, some of which take 4 bytes and some take
7420 2 bytes, so the idea is the same.
7421 FIXME: We have to assume that bpaddr is not the second half
7422 of an extended instruction. */
7423 insn_at_pc_has_delay_slot
= (mips_pc_is_micromips (gdbarch
, bpaddr
)
7424 ? micromips_insn_at_pc_has_delay_slot
7425 : mips16_insn_at_pc_has_delay_slot
);
7429 for (i
= 1; i
< 4; i
++)
7431 if (unmake_compact_addr (addr
) == boundary
)
7433 addr
-= MIPS_INSN16_SIZE
;
7434 if (i
== 1 && insn_at_pc_has_delay_slot (gdbarch
, addr
, 0))
7435 /* Looks like a JR/JALR at [target-1], but it could be
7436 the second word of a previous JAL/JALX, so record it
7437 and check back one more. */
7439 else if (i
> 1 && insn_at_pc_has_delay_slot (gdbarch
, addr
, 1))
7442 /* Looks like a JAL/JALX at [target-2], but it could also
7443 be the second word of a previous JAL/JALX, record it,
7444 and check back one more. */
7447 /* Looks like a JAL/JALX at [target-3], so any previously
7448 recorded JAL/JALX or JR/JALR must be wrong, because:
7451 -2: JAL-ext (can't be JAL/JALX)
7452 -1: bdslot (can't be JR/JALR)
7455 Of course it could be another JAL-ext which looks
7456 like a JAL, but in that case we'd have broken out
7457 of this loop at [target-2]:
7461 -2: bdslot (can't be jmp)
7468 /* Not a jump instruction: if we're at [target-1] this
7469 could be the second word of a JAL/JALX, so continue;
7470 otherwise we're done. */
7483 /* Return non-zero if SUFFIX is one of the numeric suffixes used for MIPS16
7484 call stubs, one of 1, 2, 5, 6, 9, 10, or, if ZERO is non-zero, also 0. */
7487 mips_is_stub_suffix (const char *suffix
, int zero
)
7492 return zero
&& suffix
[1] == '\0';
7494 return suffix
[1] == '\0' || (suffix
[1] == '0' && suffix
[2] == '\0');
7499 return suffix
[1] == '\0';
7505 /* Return non-zero if MODE is one of the mode infixes used for MIPS16
7506 call stubs, one of sf, df, sc, or dc. */
7509 mips_is_stub_mode (const char *mode
)
7511 return ((mode
[0] == 's' || mode
[0] == 'd')
7512 && (mode
[1] == 'f' || mode
[1] == 'c'));
7515 /* Code at PC is a compiler-generated stub. Such a stub for a function
7516 bar might have a name like __fn_stub_bar, and might look like this:
7523 followed by (or interspersed with):
7530 addiu $25, $25, %lo(bar)
7533 ($1 may be used in old code; for robustness we accept any register)
7536 lui $28, %hi(_gp_disp)
7537 addiu $28, $28, %lo(_gp_disp)
7540 addiu $25, $25, %lo(bar)
7543 In the case of a __call_stub_bar stub, the sequence to set up
7544 arguments might look like this:
7551 followed by (or interspersed with) one of the jump sequences above.
7553 In the case of a __call_stub_fp_bar stub, JAL or JALR is used instead
7554 of J or JR, respectively, followed by:
7560 We are at the beginning of the stub here, and scan down and extract
7561 the target address from the jump immediate instruction or, if a jump
7562 register instruction is used, from the register referred. Return
7563 the value of PC calculated or 0 if inconclusive.
7565 The limit on the search is arbitrarily set to 20 instructions. FIXME. */
7568 mips_get_mips16_fn_stub_pc (struct frame_info
*frame
, CORE_ADDR pc
)
7570 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7571 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7572 int addrreg
= MIPS_ZERO_REGNUM
;
7573 CORE_ADDR start_pc
= pc
;
7574 CORE_ADDR target_pc
= 0;
7581 status
== 0 && target_pc
== 0 && i
< 20;
7582 i
++, pc
+= MIPS_INSN32_SIZE
)
7584 ULONGEST inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
7590 switch (itype_op (inst
))
7592 case 0: /* SPECIAL */
7593 switch (rtype_funct (inst
))
7597 rs
= rtype_rs (inst
);
7598 if (rs
== MIPS_GP_REGNUM
)
7599 target_pc
= gp
; /* Hmm... */
7600 else if (rs
== addrreg
)
7604 case 0x21: /* ADDU */
7605 rt
= rtype_rt (inst
);
7606 rs
= rtype_rs (inst
);
7607 rd
= rtype_rd (inst
);
7608 if (rd
== MIPS_GP_REGNUM
7609 && ((rs
== MIPS_GP_REGNUM
&& rt
== MIPS_T9_REGNUM
)
7610 || (rs
== MIPS_T9_REGNUM
&& rt
== MIPS_GP_REGNUM
)))
7618 target_pc
= jtype_target (inst
) << 2;
7619 target_pc
+= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
7623 rt
= itype_rt (inst
);
7624 rs
= itype_rs (inst
);
7627 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
7628 if (rt
== MIPS_GP_REGNUM
)
7630 else if (rt
== addrreg
)
7636 rt
= itype_rt (inst
);
7637 imm
= ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 16;
7638 if (rt
== MIPS_GP_REGNUM
)
7640 else if (rt
!= MIPS_ZERO_REGNUM
)
7648 rt
= itype_rt (inst
);
7649 rs
= itype_rs (inst
);
7650 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
7651 if (gp
!= 0 && rs
== MIPS_GP_REGNUM
)
7655 memset (buf
, 0, sizeof (buf
));
7656 status
= target_read_memory (gp
+ imm
, buf
, sizeof (buf
));
7658 addr
= extract_signed_integer (buf
, sizeof (buf
), byte_order
);
7667 /* If PC is in a MIPS16 call or return stub, return the address of the
7668 target PC, which is either the callee or the caller. There are several
7669 cases which must be handled:
7671 * If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7672 and the target PC is in $31 ($ra).
7673 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7674 and the target PC is in $2.
7675 * If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7676 i.e. before the JALR instruction, this is effectively a call stub
7677 and the target PC is in $2. Otherwise this is effectively
7678 a return stub and the target PC is in $18.
7679 * If the PC is at the start of __call_stub_fp_*, i.e. before the
7680 JAL or JALR instruction, this is effectively a call stub and the
7681 target PC is buried in the instruction stream. Otherwise this
7682 is effectively a return stub and the target PC is in $18.
7683 * If the PC is in __call_stub_* or in __fn_stub_*, this is a call
7684 stub and the target PC is buried in the instruction stream.
7686 See the source code for the stubs in gcc/config/mips/mips16.S, or the
7687 stub builder in gcc/config/mips/mips.c (mips16_build_call_stub) for the
7691 mips_skip_mips16_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7693 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7694 CORE_ADDR start_addr
;
7698 /* Find the starting address and name of the function containing the PC. */
7699 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
7702 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7703 and the target PC is in $31 ($ra). */
7704 prefixlen
= strlen (mips_str_mips16_ret_stub
);
7705 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
7706 && mips_is_stub_mode (name
+ prefixlen
)
7707 && name
[prefixlen
+ 2] == '\0')
7708 return get_frame_register_signed
7709 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
7711 /* If the PC is in __mips16_call_stub_*, this is one of the call
7712 call/return stubs. */
7713 prefixlen
= strlen (mips_str_mips16_call_stub
);
7714 if (strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0)
7716 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7717 and the target PC is in $2. */
7718 if (mips_is_stub_suffix (name
+ prefixlen
, 0))
7719 return get_frame_register_signed
7720 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
7722 /* If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7723 i.e. before the JALR instruction, this is effectively a call stub
7724 and the target PC is in $2. Otherwise this is effectively
7725 a return stub and the target PC is in $18. */
7726 else if (mips_is_stub_mode (name
+ prefixlen
)
7727 && name
[prefixlen
+ 2] == '_'
7728 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 0))
7730 if (pc
== start_addr
)
7731 /* This is the 'call' part of a call stub. The return
7732 address is in $2. */
7733 return get_frame_register_signed
7734 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
7736 /* This is the 'return' part of a call stub. The return
7737 address is in $18. */
7738 return get_frame_register_signed
7739 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
7742 return 0; /* Not a stub. */
7745 /* If the PC is in __call_stub_* or __fn_stub*, this is one of the
7746 compiler-generated call or call/return stubs. */
7747 if (startswith (name
, mips_str_fn_stub
)
7748 || startswith (name
, mips_str_call_stub
))
7750 if (pc
== start_addr
)
7751 /* This is the 'call' part of a call stub. Call this helper
7752 to scan through this code for interesting instructions
7753 and determine the final PC. */
7754 return mips_get_mips16_fn_stub_pc (frame
, pc
);
7756 /* This is the 'return' part of a call stub. The return address
7758 return get_frame_register_signed
7759 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
7762 return 0; /* Not a stub. */
7765 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
7766 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
7769 mips_in_return_stub (struct gdbarch
*gdbarch
, CORE_ADDR pc
, const char *name
)
7771 CORE_ADDR start_addr
;
7774 /* Find the starting address of the function containing the PC. */
7775 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
7778 /* If the PC is in __mips16_call_stub_{s,d}{f,c}_{0..10} but not at
7779 the start, i.e. after the JALR instruction, this is effectively
7781 prefixlen
= strlen (mips_str_mips16_call_stub
);
7782 if (pc
!= start_addr
7783 && strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0
7784 && mips_is_stub_mode (name
+ prefixlen
)
7785 && name
[prefixlen
+ 2] == '_'
7786 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 1))
7789 /* If the PC is in __call_stub_fp_* but not at the start, i.e. after
7790 the JAL or JALR instruction, this is effectively a return stub. */
7791 prefixlen
= strlen (mips_str_call_fp_stub
);
7792 if (pc
!= start_addr
7793 && strncmp (name
, mips_str_call_fp_stub
, prefixlen
) == 0)
7796 /* Consume the .pic. prefix of any PIC stub, this function must return
7797 true when the PC is in a PIC stub of a __mips16_ret_{d,s}{f,c} stub
7798 or the call stub path will trigger in handle_inferior_event causing
7800 prefixlen
= strlen (mips_str_pic
);
7801 if (strncmp (name
, mips_str_pic
, prefixlen
) == 0)
7804 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub. */
7805 prefixlen
= strlen (mips_str_mips16_ret_stub
);
7806 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
7807 && mips_is_stub_mode (name
+ prefixlen
)
7808 && name
[prefixlen
+ 2] == '\0')
7811 return 0; /* Not a stub. */
7814 /* If the current PC is the start of a non-PIC-to-PIC stub, return the
7815 PC of the stub target. The stub just loads $t9 and jumps to it,
7816 so that $t9 has the correct value at function entry. */
7819 mips_skip_pic_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7821 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7822 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7823 struct bound_minimal_symbol msym
;
7825 gdb_byte stub_code
[16];
7826 int32_t stub_words
[4];
7828 /* The stub for foo is named ".pic.foo", and is either two
7829 instructions inserted before foo or a three instruction sequence
7830 which jumps to foo. */
7831 msym
= lookup_minimal_symbol_by_pc (pc
);
7832 if (msym
.minsym
== NULL
7833 || msym
.value_address () != pc
7834 || msym
.minsym
->linkage_name () == NULL
7835 || !startswith (msym
.minsym
->linkage_name (), ".pic."))
7838 /* A two-instruction header. */
7839 if (msym
.minsym
->size () == 8)
7842 /* A three-instruction (plus delay slot) trampoline. */
7843 if (msym
.minsym
->size () == 16)
7845 if (target_read_memory (pc
, stub_code
, 16) != 0)
7847 for (i
= 0; i
< 4; i
++)
7848 stub_words
[i
] = extract_unsigned_integer (stub_code
+ i
* 4,
7851 /* A stub contains these instructions:
7854 addiu t9, t9, %lo(target)
7857 This works even for N64, since stubs are only generated with
7859 if ((stub_words
[0] & 0xffff0000U
) == 0x3c190000
7860 && (stub_words
[1] & 0xfc000000U
) == 0x08000000
7861 && (stub_words
[2] & 0xffff0000U
) == 0x27390000
7862 && stub_words
[3] == 0x00000000)
7863 return ((((stub_words
[0] & 0x0000ffff) << 16)
7864 + (stub_words
[2] & 0x0000ffff)) ^ 0x8000) - 0x8000;
7867 /* Not a recognized stub. */
7872 mips_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7874 CORE_ADDR requested_pc
= pc
;
7875 CORE_ADDR target_pc
;
7882 new_pc
= mips_skip_mips16_trampoline_code (frame
, pc
);
7886 new_pc
= find_solib_trampoline_target (frame
, pc
);
7890 new_pc
= mips_skip_pic_trampoline_code (frame
, pc
);
7894 while (pc
!= target_pc
);
7896 return pc
!= requested_pc
? pc
: 0;
7899 /* Convert a dbx stab register number (from `r' declaration) to a GDB
7900 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7903 mips_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
7906 if (num
>= 0 && num
< 32)
7908 else if (num
>= 38 && num
< 70)
7909 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 38;
7911 regnum
= mips_regnum (gdbarch
)->hi
;
7913 regnum
= mips_regnum (gdbarch
)->lo
;
7914 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 72 && num
< 78)
7915 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 72;
7918 return gdbarch_num_regs (gdbarch
) + regnum
;
7922 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
7923 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7926 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
7929 if (num
>= 0 && num
< 32)
7931 else if (num
>= 32 && num
< 64)
7932 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 32;
7934 regnum
= mips_regnum (gdbarch
)->hi
;
7936 regnum
= mips_regnum (gdbarch
)->lo
;
7937 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 66 && num
< 72)
7938 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 66;
7941 return gdbarch_num_regs (gdbarch
) + regnum
;
7945 mips_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
7947 /* Only makes sense to supply raw registers. */
7948 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
));
7949 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
7950 decide if it is valid. Should instead define a standard sim/gdb
7951 register numbering scheme. */
7952 if (gdbarch_register_name (gdbarch
,
7953 gdbarch_num_regs (gdbarch
) + regnum
) != NULL
7954 && gdbarch_register_name (gdbarch
,
7955 gdbarch_num_regs (gdbarch
)
7956 + regnum
)[0] != '\0')
7959 return LEGACY_SIM_REGNO_IGNORE
;
7963 /* Convert an integer into an address. Extracting the value signed
7964 guarantees a correctly sign extended address. */
7967 mips_integer_to_address (struct gdbarch
*gdbarch
,
7968 struct type
*type
, const gdb_byte
*buf
)
7970 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7971 return extract_signed_integer (buf
, TYPE_LENGTH (type
), byte_order
);
7974 /* Dummy virtual frame pointer method. This is no more or less accurate
7975 than most other architectures; we just need to be explicit about it,
7976 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
7977 an assertion failure. */
7980 mips_virtual_frame_pointer (struct gdbarch
*gdbarch
,
7981 CORE_ADDR pc
, int *reg
, LONGEST
*offset
)
7983 *reg
= MIPS_SP_REGNUM
;
7988 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
7990 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
7991 const char *name
= bfd_section_name (sect
);
7993 if (*abip
!= MIPS_ABI_UNKNOWN
)
7996 if (!startswith (name
, ".mdebug."))
7999 if (strcmp (name
, ".mdebug.abi32") == 0)
8000 *abip
= MIPS_ABI_O32
;
8001 else if (strcmp (name
, ".mdebug.abiN32") == 0)
8002 *abip
= MIPS_ABI_N32
;
8003 else if (strcmp (name
, ".mdebug.abi64") == 0)
8004 *abip
= MIPS_ABI_N64
;
8005 else if (strcmp (name
, ".mdebug.abiO64") == 0)
8006 *abip
= MIPS_ABI_O64
;
8007 else if (strcmp (name
, ".mdebug.eabi32") == 0)
8008 *abip
= MIPS_ABI_EABI32
;
8009 else if (strcmp (name
, ".mdebug.eabi64") == 0)
8010 *abip
= MIPS_ABI_EABI64
;
8012 warning (_("unsupported ABI %s."), name
+ 8);
8016 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
8018 int *lbp
= (int *) obj
;
8019 const char *name
= bfd_section_name (sect
);
8021 if (startswith (name
, ".gcc_compiled_long32"))
8023 else if (startswith (name
, ".gcc_compiled_long64"))
8025 else if (startswith (name
, ".gcc_compiled_long"))
8026 warning (_("unrecognized .gcc_compiled_longXX"));
8029 static enum mips_abi
8030 global_mips_abi (void)
8034 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
8035 if (mips_abi_strings
[i
] == mips_abi_string
)
8036 return (enum mips_abi
) i
;
8038 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
8041 /* Return the default compressed instruction set, either of MIPS16
8042 or microMIPS, selected when none could have been determined from
8043 the ELF header of the binary being executed (or no binary has been
8046 static enum mips_isa
8047 global_mips_compression (void)
8051 for (i
= 0; mips_compression_strings
[i
] != NULL
; i
++)
8052 if (mips_compression_strings
[i
] == mips_compression_string
)
8053 return (enum mips_isa
) i
;
8055 internal_error (__FILE__
, __LINE__
, _("unknown compressed ISA string"));
8059 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
8061 /* If the size matches the set of 32-bit or 64-bit integer registers,
8062 assume that's what we've got. */
8063 register_remote_g_packet_guess (gdbarch
, 38 * 4, mips_tdesc_gp32
);
8064 register_remote_g_packet_guess (gdbarch
, 38 * 8, mips_tdesc_gp64
);
8066 /* If the size matches the full set of registers GDB traditionally
8067 knows about, including floating point, for either 32-bit or
8068 64-bit, assume that's what we've got. */
8069 register_remote_g_packet_guess (gdbarch
, 90 * 4, mips_tdesc_gp32
);
8070 register_remote_g_packet_guess (gdbarch
, 90 * 8, mips_tdesc_gp64
);
8072 /* Otherwise we don't have a useful guess. */
8075 static struct value
*
8076 value_of_mips_user_reg (struct frame_info
*frame
, const void *baton
)
8078 const int *reg_p
= (const int *) baton
;
8079 return value_of_register (*reg_p
, frame
);
8082 static struct gdbarch
*
8083 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
8085 struct gdbarch
*gdbarch
;
8087 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
8089 enum mips_fpu_type fpu_type
;
8090 tdesc_arch_data_up tdesc_data
;
8091 int elf_fpu_type
= Val_GNU_MIPS_ABI_FP_ANY
;
8092 const char * const *reg_names
;
8093 struct mips_regnum mips_regnum
, *regnum
;
8094 enum mips_isa mips_isa
;
8098 /* First of all, extract the elf_flags, if available. */
8099 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
8100 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
8101 else if (arches
!= NULL
)
8103 mips_gdbarch_tdep
*tdep
8104 = (mips_gdbarch_tdep
*) gdbarch_tdep (arches
->gdbarch
);
8105 elf_flags
= tdep
->elf_flags
;
8110 gdb_printf (gdb_stdlog
,
8111 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
8113 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
8114 switch ((elf_flags
& EF_MIPS_ABI
))
8116 case E_MIPS_ABI_O32
:
8117 found_abi
= MIPS_ABI_O32
;
8119 case E_MIPS_ABI_O64
:
8120 found_abi
= MIPS_ABI_O64
;
8122 case E_MIPS_ABI_EABI32
:
8123 found_abi
= MIPS_ABI_EABI32
;
8125 case E_MIPS_ABI_EABI64
:
8126 found_abi
= MIPS_ABI_EABI64
;
8129 if ((elf_flags
& EF_MIPS_ABI2
))
8130 found_abi
= MIPS_ABI_N32
;
8132 found_abi
= MIPS_ABI_UNKNOWN
;
8136 /* GCC creates a pseudo-section whose name describes the ABI. */
8137 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
8138 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
8140 /* If we have no useful BFD information, use the ABI from the last
8141 MIPS architecture (if there is one). */
8142 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
8144 mips_gdbarch_tdep
*tdep
8145 = (mips_gdbarch_tdep
*) gdbarch_tdep (arches
->gdbarch
);
8146 found_abi
= tdep
->found_abi
;
8149 /* Try the architecture for any hint of the correct ABI. */
8150 if (found_abi
== MIPS_ABI_UNKNOWN
8151 && info
.bfd_arch_info
!= NULL
8152 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
8154 switch (info
.bfd_arch_info
->mach
)
8156 case bfd_mach_mips3900
:
8157 found_abi
= MIPS_ABI_EABI32
;
8159 case bfd_mach_mips4100
:
8160 case bfd_mach_mips5000
:
8161 found_abi
= MIPS_ABI_EABI64
;
8163 case bfd_mach_mips8000
:
8164 case bfd_mach_mips10000
:
8165 /* On Irix, ELF64 executables use the N64 ABI. The
8166 pseudo-sections which describe the ABI aren't present
8167 on IRIX. (Even for executables created by gcc.) */
8168 if (info
.abfd
!= NULL
8169 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
8170 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
8171 found_abi
= MIPS_ABI_N64
;
8173 found_abi
= MIPS_ABI_N32
;
8178 /* Default 64-bit objects to N64 instead of O32. */
8179 if (found_abi
== MIPS_ABI_UNKNOWN
8180 && info
.abfd
!= NULL
8181 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
8182 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
8183 found_abi
= MIPS_ABI_N64
;
8186 gdb_printf (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
8189 /* What has the user specified from the command line? */
8190 wanted_abi
= global_mips_abi ();
8192 gdb_printf (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
8195 /* Now that we have found what the ABI for this binary would be,
8196 check whether the user is overriding it. */
8197 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
8198 mips_abi
= wanted_abi
;
8199 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
8200 mips_abi
= found_abi
;
8202 mips_abi
= MIPS_ABI_O32
;
8204 gdb_printf (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
8207 /* Make sure we don't use a 32-bit architecture with a 64-bit ABI. */
8208 if (mips_abi
!= MIPS_ABI_EABI32
8209 && mips_abi
!= MIPS_ABI_O32
8210 && info
.bfd_arch_info
!= NULL
8211 && info
.bfd_arch_info
->arch
== bfd_arch_mips
8212 && info
.bfd_arch_info
->bits_per_word
< 64)
8213 info
.bfd_arch_info
= bfd_lookup_arch (bfd_arch_mips
, bfd_mach_mips4000
);
8215 /* Determine the default compressed ISA. */
8216 if ((elf_flags
& EF_MIPS_ARCH_ASE_MICROMIPS
) != 0
8217 && (elf_flags
& EF_MIPS_ARCH_ASE_M16
) == 0)
8218 mips_isa
= ISA_MICROMIPS
;
8219 else if ((elf_flags
& EF_MIPS_ARCH_ASE_M16
) != 0
8220 && (elf_flags
& EF_MIPS_ARCH_ASE_MICROMIPS
) == 0)
8221 mips_isa
= ISA_MIPS16
;
8223 mips_isa
= global_mips_compression ();
8224 mips_compression_string
= mips_compression_strings
[mips_isa
];
8226 /* Also used when doing an architecture lookup. */
8228 gdb_printf (gdb_stdlog
,
8229 "mips_gdbarch_init: "
8230 "mips64_transfers_32bit_regs_p = %d\n",
8231 mips64_transfers_32bit_regs_p
);
8233 /* Determine the MIPS FPU type. */
8236 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
8237 elf_fpu_type
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
8238 Tag_GNU_MIPS_ABI_FP
);
8239 #endif /* HAVE_ELF */
8241 if (!mips_fpu_type_auto
)
8242 fpu_type
= mips_fpu_type
;
8243 else if (elf_fpu_type
!= Val_GNU_MIPS_ABI_FP_ANY
)
8245 switch (elf_fpu_type
)
8247 case Val_GNU_MIPS_ABI_FP_DOUBLE
:
8248 fpu_type
= MIPS_FPU_DOUBLE
;
8250 case Val_GNU_MIPS_ABI_FP_SINGLE
:
8251 fpu_type
= MIPS_FPU_SINGLE
;
8253 case Val_GNU_MIPS_ABI_FP_SOFT
:
8255 /* Soft float or unknown. */
8256 fpu_type
= MIPS_FPU_NONE
;
8260 else if (info
.bfd_arch_info
!= NULL
8261 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
8262 switch (info
.bfd_arch_info
->mach
)
8264 case bfd_mach_mips3900
:
8265 case bfd_mach_mips4100
:
8266 case bfd_mach_mips4111
:
8267 case bfd_mach_mips4120
:
8268 fpu_type
= MIPS_FPU_NONE
;
8270 case bfd_mach_mips4650
:
8271 fpu_type
= MIPS_FPU_SINGLE
;
8274 fpu_type
= MIPS_FPU_DOUBLE
;
8277 else if (arches
!= NULL
)
8278 fpu_type
= mips_get_fpu_type (arches
->gdbarch
);
8280 fpu_type
= MIPS_FPU_DOUBLE
;
8282 gdb_printf (gdb_stdlog
,
8283 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
8285 /* Check for blatant incompatibilities. */
8287 /* If we have only 32-bit registers, then we can't debug a 64-bit
8289 if (info
.target_desc
8290 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
8291 && mips_abi
!= MIPS_ABI_EABI32
8292 && mips_abi
!= MIPS_ABI_O32
)
8295 /* Fill in the OS dependent register numbers and names. */
8296 if (info
.osabi
== GDB_OSABI_LINUX
)
8298 mips_regnum
.fp0
= 38;
8299 mips_regnum
.pc
= 37;
8300 mips_regnum
.cause
= 36;
8301 mips_regnum
.badvaddr
= 35;
8302 mips_regnum
.hi
= 34;
8303 mips_regnum
.lo
= 33;
8304 mips_regnum
.fp_control_status
= 70;
8305 mips_regnum
.fp_implementation_revision
= 71;
8306 mips_regnum
.dspacc
= -1;
8307 mips_regnum
.dspctl
= -1;
8311 reg_names
= mips_linux_reg_names
;
8315 mips_regnum
.lo
= MIPS_EMBED_LO_REGNUM
;
8316 mips_regnum
.hi
= MIPS_EMBED_HI_REGNUM
;
8317 mips_regnum
.badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
8318 mips_regnum
.cause
= MIPS_EMBED_CAUSE_REGNUM
;
8319 mips_regnum
.pc
= MIPS_EMBED_PC_REGNUM
;
8320 mips_regnum
.fp0
= MIPS_EMBED_FP0_REGNUM
;
8321 mips_regnum
.fp_control_status
= 70;
8322 mips_regnum
.fp_implementation_revision
= 71;
8323 mips_regnum
.dspacc
= dspacc
= -1;
8324 mips_regnum
.dspctl
= dspctl
= -1;
8325 num_regs
= MIPS_LAST_EMBED_REGNUM
+ 1;
8326 if (info
.bfd_arch_info
!= NULL
8327 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
8328 reg_names
= mips_tx39_reg_names
;
8330 reg_names
= mips_generic_reg_names
;
8333 /* Check any target description for validity. */
8334 if (tdesc_has_registers (info
.target_desc
))
8336 static const char *const mips_gprs
[] = {
8337 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
8338 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
8339 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
8340 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
8342 static const char *const mips_fprs
[] = {
8343 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
8344 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
8345 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
8346 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
8349 const struct tdesc_feature
*feature
;
8352 feature
= tdesc_find_feature (info
.target_desc
,
8353 "org.gnu.gdb.mips.cpu");
8354 if (feature
== NULL
)
8357 tdesc_data
= tdesc_data_alloc ();
8360 for (i
= MIPS_ZERO_REGNUM
; i
<= MIPS_RA_REGNUM
; i
++)
8361 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (), i
,
8365 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8366 mips_regnum
.lo
, "lo");
8367 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8368 mips_regnum
.hi
, "hi");
8369 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8370 mips_regnum
.pc
, "pc");
8375 feature
= tdesc_find_feature (info
.target_desc
,
8376 "org.gnu.gdb.mips.cp0");
8377 if (feature
== NULL
)
8381 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8382 mips_regnum
.badvaddr
, "badvaddr");
8383 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8384 MIPS_PS_REGNUM
, "status");
8385 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8386 mips_regnum
.cause
, "cause");
8391 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
8392 backend is not prepared for that, though. */
8393 feature
= tdesc_find_feature (info
.target_desc
,
8394 "org.gnu.gdb.mips.fpu");
8395 if (feature
== NULL
)
8399 for (i
= 0; i
< 32; i
++)
8400 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8401 i
+ mips_regnum
.fp0
, mips_fprs
[i
]);
8403 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8404 mips_regnum
.fp_control_status
,
8407 &= tdesc_numbered_register (feature
, tdesc_data
.get (),
8408 mips_regnum
.fp_implementation_revision
,
8414 num_regs
= mips_regnum
.fp_implementation_revision
+ 1;
8418 feature
= tdesc_find_feature (info
.target_desc
,
8419 "org.gnu.gdb.mips.dsp");
8420 /* The DSP registers are optional; it's OK if they are absent. */
8421 if (feature
!= NULL
)
8425 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8426 dspacc
+ i
++, "hi1");
8427 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8428 dspacc
+ i
++, "lo1");
8429 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8430 dspacc
+ i
++, "hi2");
8431 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8432 dspacc
+ i
++, "lo2");
8433 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8434 dspacc
+ i
++, "hi3");
8435 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8436 dspacc
+ i
++, "lo3");
8438 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8444 mips_regnum
.dspacc
= dspacc
;
8445 mips_regnum
.dspctl
= dspctl
;
8447 num_regs
= mips_regnum
.dspctl
+ 1;
8451 /* It would be nice to detect an attempt to use a 64-bit ABI
8452 when only 32-bit registers are provided. */
8456 /* Try to find a pre-existing architecture. */
8457 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
8459 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
8461 mips_gdbarch_tdep
*tdep
8462 = (mips_gdbarch_tdep
*) gdbarch_tdep (arches
->gdbarch
);
8464 /* MIPS needs to be pedantic about which ABI and the compressed
8465 ISA variation the object is using. */
8466 if (tdep
->elf_flags
!= elf_flags
)
8468 if (tdep
->mips_abi
!= mips_abi
)
8470 if (tdep
->mips_isa
!= mips_isa
)
8472 /* Need to be pedantic about which register virtual size is
8474 if (tdep
->mips64_transfers_32bit_regs_p
8475 != mips64_transfers_32bit_regs_p
)
8477 /* Be pedantic about which FPU is selected. */
8478 if (mips_get_fpu_type (arches
->gdbarch
) != fpu_type
)
8481 return arches
->gdbarch
;
8484 /* Need a new architecture. Fill in a target specific vector. */
8485 mips_gdbarch_tdep
*tdep
= new mips_gdbarch_tdep
;
8486 gdbarch
= gdbarch_alloc (&info
, tdep
);
8487 tdep
->elf_flags
= elf_flags
;
8488 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
8489 tdep
->found_abi
= found_abi
;
8490 tdep
->mips_abi
= mips_abi
;
8491 tdep
->mips_isa
= mips_isa
;
8492 tdep
->mips_fpu_type
= fpu_type
;
8493 tdep
->register_size_valid_p
= 0;
8494 tdep
->register_size
= 0;
8496 if (info
.target_desc
)
8498 /* Some useful properties can be inferred from the target. */
8499 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
8501 tdep
->register_size_valid_p
= 1;
8502 tdep
->register_size
= 4;
8504 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
8506 tdep
->register_size_valid_p
= 1;
8507 tdep
->register_size
= 8;
8511 /* Initially set everything according to the default ABI/ISA. */
8512 set_gdbarch_short_bit (gdbarch
, 16);
8513 set_gdbarch_int_bit (gdbarch
, 32);
8514 set_gdbarch_float_bit (gdbarch
, 32);
8515 set_gdbarch_double_bit (gdbarch
, 64);
8516 set_gdbarch_long_double_bit (gdbarch
, 64);
8517 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
8518 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
8519 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
8521 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
8522 mips_ax_pseudo_register_collect
);
8523 set_gdbarch_ax_pseudo_register_push_stack
8524 (gdbarch
, mips_ax_pseudo_register_push_stack
);
8526 set_gdbarch_elf_make_msymbol_special (gdbarch
,
8527 mips_elf_make_msymbol_special
);
8528 set_gdbarch_make_symbol_special (gdbarch
, mips_make_symbol_special
);
8529 set_gdbarch_adjust_dwarf2_addr (gdbarch
, mips_adjust_dwarf2_addr
);
8530 set_gdbarch_adjust_dwarf2_line (gdbarch
, mips_adjust_dwarf2_line
);
8532 regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
, struct mips_regnum
);
8533 *regnum
= mips_regnum
;
8534 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
8535 set_gdbarch_num_regs (gdbarch
, num_regs
);
8536 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
8537 set_gdbarch_register_name (gdbarch
, mips_register_name
);
8538 set_gdbarch_virtual_frame_pointer (gdbarch
, mips_virtual_frame_pointer
);
8539 tdep
->mips_processor_reg_names
= reg_names
;
8540 tdep
->regnum
= regnum
;
8545 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
8546 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
8547 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
8548 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
8549 tdep
->default_mask_address_p
= 0;
8550 set_gdbarch_long_bit (gdbarch
, 32);
8551 set_gdbarch_ptr_bit (gdbarch
, 32);
8552 set_gdbarch_long_long_bit (gdbarch
, 64);
8555 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
8556 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
8557 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
8558 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
8559 tdep
->default_mask_address_p
= 0;
8560 set_gdbarch_long_bit (gdbarch
, 32);
8561 set_gdbarch_ptr_bit (gdbarch
, 32);
8562 set_gdbarch_long_long_bit (gdbarch
, 64);
8564 case MIPS_ABI_EABI32
:
8565 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
8566 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
8567 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8568 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8569 tdep
->default_mask_address_p
= 0;
8570 set_gdbarch_long_bit (gdbarch
, 32);
8571 set_gdbarch_ptr_bit (gdbarch
, 32);
8572 set_gdbarch_long_long_bit (gdbarch
, 64);
8574 case MIPS_ABI_EABI64
:
8575 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
8576 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
8577 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8578 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8579 tdep
->default_mask_address_p
= 0;
8580 set_gdbarch_long_bit (gdbarch
, 64);
8581 set_gdbarch_ptr_bit (gdbarch
, 64);
8582 set_gdbarch_long_long_bit (gdbarch
, 64);
8585 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
8586 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
8587 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8588 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8589 tdep
->default_mask_address_p
= 0;
8590 set_gdbarch_long_bit (gdbarch
, 32);
8591 set_gdbarch_ptr_bit (gdbarch
, 32);
8592 set_gdbarch_long_long_bit (gdbarch
, 64);
8593 set_gdbarch_long_double_bit (gdbarch
, 128);
8594 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
8597 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
8598 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
8599 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8600 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8601 tdep
->default_mask_address_p
= 0;
8602 set_gdbarch_long_bit (gdbarch
, 64);
8603 set_gdbarch_ptr_bit (gdbarch
, 64);
8604 set_gdbarch_long_long_bit (gdbarch
, 64);
8605 set_gdbarch_long_double_bit (gdbarch
, 128);
8606 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
8609 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
8612 /* GCC creates a pseudo-section whose name specifies the size of
8613 longs, since -mlong32 or -mlong64 may be used independent of
8614 other options. How those options affect pointer sizes is ABI and
8615 architecture dependent, so use them to override the default sizes
8616 set by the ABI. This table shows the relationship between ABI,
8617 -mlongXX, and size of pointers:
8619 ABI -mlongXX ptr bits
8620 --- -------- --------
8634 Note that for o32 and eabi32, pointers are always 32 bits
8635 regardless of any -mlongXX option. For all others, pointers and
8636 longs are the same, as set by -mlongXX or set by defaults. */
8638 if (info
.abfd
!= NULL
)
8642 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
8645 set_gdbarch_long_bit (gdbarch
, long_bit
);
8649 case MIPS_ABI_EABI32
:
8654 case MIPS_ABI_EABI64
:
8655 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
8658 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
8663 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
8664 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
8667 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
8668 flag in object files because to do so would make it impossible to
8669 link with libraries compiled without "-gp32". This is
8670 unnecessarily restrictive.
8672 We could solve this problem by adding "-gp32" multilibs to gcc,
8673 but to set this flag before gcc is built with such multilibs will
8674 break too many systems.''
8676 But even more unhelpfully, the default linker output target for
8677 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
8678 for 64-bit programs - you need to change the ABI to change this,
8679 and not all gcc targets support that currently. Therefore using
8680 this flag to detect 32-bit mode would do the wrong thing given
8681 the current gcc - it would make GDB treat these 64-bit programs
8682 as 32-bit programs by default. */
8684 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
8685 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
8687 /* Add/remove bits from an address. The MIPS needs be careful to
8688 ensure that all 32 bit addresses are sign extended to 64 bits. */
8689 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
8691 /* Unwind the frame. */
8692 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
8693 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
8694 set_gdbarch_dummy_id (gdbarch
, mips_dummy_id
);
8696 /* Map debug register numbers onto internal register numbers. */
8697 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
8698 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
8699 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
8700 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
8701 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
8702 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
8704 /* MIPS version of CALL_DUMMY. */
8706 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
8707 set_gdbarch_push_dummy_code (gdbarch
, mips_push_dummy_code
);
8708 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
8710 set_gdbarch_print_float_info (gdbarch
, mips_print_float_info
);
8712 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
8713 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
8714 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
8716 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
8717 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, mips_breakpoint_kind_from_pc
);
8718 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, mips_sw_breakpoint_from_kind
);
8719 set_gdbarch_adjust_breakpoint_address (gdbarch
,
8720 mips_adjust_breakpoint_address
);
8722 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
8724 set_gdbarch_stack_frame_destroyed_p (gdbarch
, mips_stack_frame_destroyed_p
);
8726 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
8727 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
8728 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
8730 set_gdbarch_register_type (gdbarch
, mips_register_type
);
8732 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
8734 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
8735 if (mips_abi
== MIPS_ABI_N64
)
8736 set_gdbarch_disassembler_options_implicit
8737 (gdbarch
, (const char *) mips_disassembler_options_n64
);
8738 else if (mips_abi
== MIPS_ABI_N32
)
8739 set_gdbarch_disassembler_options_implicit
8740 (gdbarch
, (const char *) mips_disassembler_options_n32
);
8742 set_gdbarch_disassembler_options_implicit
8743 (gdbarch
, (const char *) mips_disassembler_options_o32
);
8744 set_gdbarch_disassembler_options (gdbarch
, &mips_disassembler_options
);
8745 set_gdbarch_valid_disassembler_options (gdbarch
,
8746 disassembler_options_mips ());
8748 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint,
8749 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint
8750 need to all be folded into the target vector. Since they are
8751 being used as guards for target_stopped_by_watchpoint, why not have
8752 target_stopped_by_watchpoint return the type of watchpoint that the code
8754 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
8756 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
8758 /* NOTE drow/2012-04-25: We overload the core solib trampoline code
8759 to support MIPS16. This is a bad thing. Make sure not to do it
8760 if we have an OS ABI that actually supports shared libraries, since
8761 shared library support is more important. If we have an OS someday
8762 that supports both shared libraries and MIPS16, we'll have to find
8763 a better place for these.
8764 macro/2012-04-25: But that applies to return trampolines only and
8765 currently no MIPS OS ABI uses shared libraries that have them. */
8766 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
8768 set_gdbarch_single_step_through_delay (gdbarch
,
8769 mips_single_step_through_delay
);
8771 /* Virtual tables. */
8772 set_gdbarch_vbit_in_delta (gdbarch
, 1);
8774 mips_register_g_packet_guesses (gdbarch
);
8776 /* Hook in OS ABI-specific overrides, if they have been registered. */
8777 info
.tdesc_data
= tdesc_data
.get ();
8778 gdbarch_init_osabi (info
, gdbarch
);
8780 /* The hook may have adjusted num_regs, fetch the final value and
8781 set pc_regnum and sp_regnum now that it has been fixed. */
8782 num_regs
= gdbarch_num_regs (gdbarch
);
8783 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
8784 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
8786 /* Unwind the frame. */
8787 dwarf2_append_unwinders (gdbarch
);
8788 frame_unwind_append_unwinder (gdbarch
, &mips_stub_frame_unwind
);
8789 frame_unwind_append_unwinder (gdbarch
, &mips_insn16_frame_unwind
);
8790 frame_unwind_append_unwinder (gdbarch
, &mips_micro_frame_unwind
);
8791 frame_unwind_append_unwinder (gdbarch
, &mips_insn32_frame_unwind
);
8792 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
8793 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
8794 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
8795 frame_base_append_sniffer (gdbarch
, mips_micro_frame_base_sniffer
);
8796 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
8798 if (tdesc_data
!= nullptr)
8800 set_tdesc_pseudo_register_type (gdbarch
, mips_pseudo_register_type
);
8801 tdesc_use_registers (gdbarch
, info
.target_desc
, std::move (tdesc_data
));
8803 /* Override the normal target description methods to handle our
8804 dual real and pseudo registers. */
8805 set_gdbarch_register_name (gdbarch
, mips_register_name
);
8806 set_gdbarch_register_reggroup_p (gdbarch
,
8807 mips_tdesc_register_reggroup_p
);
8809 num_regs
= gdbarch_num_regs (gdbarch
);
8810 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
8811 set_gdbarch_pc_regnum (gdbarch
, tdep
->regnum
->pc
+ num_regs
);
8812 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
8815 /* Add ABI-specific aliases for the registers. */
8816 if (mips_abi
== MIPS_ABI_N32
|| mips_abi
== MIPS_ABI_N64
)
8817 for (i
= 0; i
< ARRAY_SIZE (mips_n32_n64_aliases
); i
++)
8818 user_reg_add (gdbarch
, mips_n32_n64_aliases
[i
].name
,
8819 value_of_mips_user_reg
, &mips_n32_n64_aliases
[i
].regnum
);
8821 for (i
= 0; i
< ARRAY_SIZE (mips_o32_aliases
); i
++)
8822 user_reg_add (gdbarch
, mips_o32_aliases
[i
].name
,
8823 value_of_mips_user_reg
, &mips_o32_aliases
[i
].regnum
);
8825 /* Add some other standard aliases. */
8826 for (i
= 0; i
< ARRAY_SIZE (mips_register_aliases
); i
++)
8827 user_reg_add (gdbarch
, mips_register_aliases
[i
].name
,
8828 value_of_mips_user_reg
, &mips_register_aliases
[i
].regnum
);
8830 for (i
= 0; i
< ARRAY_SIZE (mips_numeric_register_aliases
); i
++)
8831 user_reg_add (gdbarch
, mips_numeric_register_aliases
[i
].name
,
8832 value_of_mips_user_reg
,
8833 &mips_numeric_register_aliases
[i
].regnum
);
8839 mips_abi_update (const char *ignore_args
,
8840 int from_tty
, struct cmd_list_element
*c
)
8842 struct gdbarch_info info
;
8844 /* Force the architecture to update, and (if it's a MIPS architecture)
8845 mips_gdbarch_init will take care of the rest. */
8846 gdbarch_update_p (info
);
8849 /* Print out which MIPS ABI is in use. */
8852 show_mips_abi (struct ui_file
*file
,
8854 struct cmd_list_element
*ignored_cmd
,
8855 const char *ignored_value
)
8857 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_mips
)
8860 "The MIPS ABI is unknown because the current architecture "
8864 enum mips_abi global_abi
= global_mips_abi ();
8865 enum mips_abi actual_abi
= mips_abi (target_gdbarch ());
8866 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
8868 if (global_abi
== MIPS_ABI_UNKNOWN
)
8871 "The MIPS ABI is set automatically (currently \"%s\").\n",
8873 else if (global_abi
== actual_abi
)
8876 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
8880 /* Probably shouldn't happen... */
8882 "The (auto detected) MIPS ABI \"%s\" is in use "
8883 "even though the user setting was \"%s\".\n",
8884 actual_abi_str
, mips_abi_strings
[global_abi
]);
8889 /* Print out which MIPS compressed ISA encoding is used. */
8892 show_mips_compression (struct ui_file
*file
, int from_tty
,
8893 struct cmd_list_element
*c
, const char *value
)
8895 gdb_printf (file
, _("The compressed ISA encoding used is %s.\n"),
8899 /* Return a textual name for MIPS FPU type FPU_TYPE. */
8902 mips_fpu_type_str (enum mips_fpu_type fpu_type
)
8908 case MIPS_FPU_SINGLE
:
8910 case MIPS_FPU_DOUBLE
:
8918 mips_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
8920 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
8924 int ef_mips_32bitmode
;
8925 /* Determine the ISA. */
8926 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
8944 /* Determine the size of a pointer. */
8945 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
8947 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
8950 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
8953 "mips_dump_tdep: ef_mips_arch = %d\n",
8956 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
8957 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
8960 "mips_mask_address_p() %d (default %d)\n",
8961 mips_mask_address_p (tdep
),
8962 tdep
->default_mask_address_p
);
8965 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
8966 MIPS_DEFAULT_FPU_TYPE
,
8967 mips_fpu_type_str (MIPS_DEFAULT_FPU_TYPE
));
8968 gdb_printf (file
, "mips_dump_tdep: MIPS_EABI = %d\n",
8969 mips_eabi (gdbarch
));
8971 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
8972 mips_get_fpu_type (gdbarch
),
8973 mips_fpu_type_str (mips_get_fpu_type (gdbarch
)));
8976 void _initialize_mips_tdep ();
8978 _initialize_mips_tdep ()
8980 static struct cmd_list_element
*mipsfpulist
= NULL
;
8982 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
8983 if (MIPS_ABI_LAST
+ 1
8984 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
8985 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
8987 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
8989 /* Create feature sets with the appropriate properties. The values
8990 are not important. */
8991 mips_tdesc_gp32
= allocate_target_description ().release ();
8992 set_tdesc_property (mips_tdesc_gp32
, PROPERTY_GP32
, "");
8994 mips_tdesc_gp64
= allocate_target_description ().release ();
8995 set_tdesc_property (mips_tdesc_gp64
, PROPERTY_GP64
, "");
8997 /* Add root prefix command for all "set mips"/"show mips" commands. */
8998 add_setshow_prefix_cmd ("mips", no_class
,
8999 _("Various MIPS specific commands."),
9000 _("Various MIPS specific commands."),
9001 &setmipscmdlist
, &showmipscmdlist
,
9002 &setlist
, &showlist
);
9004 /* Allow the user to override the ABI. */
9005 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
9006 &mips_abi_string
, _("\
9007 Set the MIPS ABI used by this program."), _("\
9008 Show the MIPS ABI used by this program."), _("\
9009 This option can be set to one of:\n\
9010 auto - the default ABI associated with the current binary\n\
9019 &setmipscmdlist
, &showmipscmdlist
);
9021 /* Allow the user to set the ISA to assume for compressed code if ELF
9022 file flags don't tell or there is no program file selected. This
9023 setting is updated whenever unambiguous ELF file flags are interpreted,
9024 and carried over to subsequent sessions. */
9025 add_setshow_enum_cmd ("compression", class_obscure
, mips_compression_strings
,
9026 &mips_compression_string
, _("\
9027 Set the compressed ISA encoding used by MIPS code."), _("\
9028 Show the compressed ISA encoding used by MIPS code."), _("\
9029 Select the compressed ISA encoding used in functions that have no symbol\n\
9030 information available. The encoding can be set to either of:\n\
9033 and is updated automatically from ELF file flags if available."),
9035 show_mips_compression
,
9036 &setmipscmdlist
, &showmipscmdlist
);
9038 /* Let the user turn off floating point and set the fence post for
9039 heuristic_proc_start. */
9041 add_basic_prefix_cmd ("mipsfpu", class_support
,
9042 _("Set use of MIPS floating-point coprocessor."),
9043 &mipsfpulist
, 0, &setlist
);
9044 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
9045 _("Select single-precision MIPS floating-point coprocessor."),
9047 cmd_list_element
*set_mipsfpu_double_cmd
9048 = add_cmd ("double", class_support
, set_mipsfpu_double_command
,
9049 _("Select double-precision MIPS floating-point coprocessor."),
9051 add_alias_cmd ("on", set_mipsfpu_double_cmd
, class_support
, 1, &mipsfpulist
);
9052 add_alias_cmd ("yes", set_mipsfpu_double_cmd
, class_support
, 1, &mipsfpulist
);
9053 add_alias_cmd ("1", set_mipsfpu_double_cmd
, class_support
, 1, &mipsfpulist
);
9055 cmd_list_element
*set_mipsfpu_none_cmd
9056 = add_cmd ("none", class_support
, set_mipsfpu_none_command
,
9057 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
9058 add_alias_cmd ("off", set_mipsfpu_none_cmd
, class_support
, 1, &mipsfpulist
);
9059 add_alias_cmd ("no", set_mipsfpu_none_cmd
, class_support
, 1, &mipsfpulist
);
9060 add_alias_cmd ("0", set_mipsfpu_none_cmd
, class_support
, 1, &mipsfpulist
);
9061 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
9062 _("Select MIPS floating-point coprocessor automatically."),
9064 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
9065 _("Show current use of MIPS floating-point coprocessor target."),
9068 /* We really would like to have both "0" and "unlimited" work, but
9069 command.c doesn't deal with that. So make it a var_zinteger
9070 because the user can always use "999999" or some such for unlimited. */
9071 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
9072 &heuristic_fence_post
, _("\
9073 Set the distance searched for the start of a function."), _("\
9074 Show the distance searched for the start of a function."), _("\
9075 If you are debugging a stripped executable, GDB needs to search through the\n\
9076 program for the start of a function. This command sets the distance of the\n\
9077 search. The only need to set it is when debugging a stripped executable."),
9078 reinit_frame_cache_sfunc
,
9079 NULL
, /* FIXME: i18n: The distance searched for
9080 the start of a function is %s. */
9081 &setlist
, &showlist
);
9083 /* Allow the user to control whether the upper bits of 64-bit
9084 addresses should be zeroed. */
9085 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
9086 &mask_address_var
, _("\
9087 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
9088 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
9089 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\
9090 allow GDB to determine the correct value."),
9091 NULL
, show_mask_address
,
9092 &setmipscmdlist
, &showmipscmdlist
);
9094 /* Allow the user to control the size of 32 bit registers within the
9095 raw remote packet. */
9096 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
9097 &mips64_transfers_32bit_regs_p
, _("\
9098 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
9100 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
9102 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
9103 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
9104 64 bits for others. Use \"off\" to disable compatibility mode"),
9105 set_mips64_transfers_32bit_regs
,
9106 NULL
, /* FIXME: i18n: Compatibility with 64-bit
9107 MIPS target that transfers 32-bit
9108 quantities is %s. */
9109 &setlist
, &showlist
);
9111 /* Debug this files internals. */
9112 add_setshow_zuinteger_cmd ("mips", class_maintenance
,
9114 Set mips debugging."), _("\
9115 Show mips debugging."), _("\
9116 When non-zero, mips specific debugging is enabled."),
9118 NULL
, /* FIXME: i18n: Mips debugging is
9120 &setdebuglist
, &showdebuglist
);