1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software
24 Foundation, Inc., 59 Temple Place - Suite 330,
25 Boston, MA 02111-1307, USA. */
28 #include "gdb_string.h"
29 #include "gdb_assert.h"
41 #include "arch-utils.h"
44 #include "mips-tdep.h"
46 #include "reggroups.h"
47 #include "opcode/mips.h"
51 #include "sim-regno.h"
53 #include "frame-unwind.h"
54 #include "frame-base.h"
55 #include "trad-frame.h"
57 #include "floatformat.h"
59 static const struct objfile_data
*mips_pdr_data
;
61 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
63 /* A useful bit in the CP0 status register (PS_REGNUM). */
64 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
65 #define ST0_FR (1 << 26)
67 /* The sizes of floating point registers. */
71 MIPS_FPU_SINGLE_REGSIZE
= 4,
72 MIPS_FPU_DOUBLE_REGSIZE
= 8
76 static const char *mips_abi_string
;
78 static const char *mips_abi_strings
[] = {
89 struct frame_extra_info
91 mips_extra_func_info_t proc_desc
;
95 /* Various MIPS ISA options (related to stack analysis) can be
96 overridden dynamically. Establish an enum/array for managing
99 static const char size_auto
[] = "auto";
100 static const char size_32
[] = "32";
101 static const char size_64
[] = "64";
103 static const char *size_enums
[] = {
110 /* Some MIPS boards don't support floating point while others only
111 support single-precision floating-point operations. */
115 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
116 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
117 MIPS_FPU_NONE
/* No floating point. */
120 #ifndef MIPS_DEFAULT_FPU_TYPE
121 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
123 static int mips_fpu_type_auto
= 1;
124 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
126 static int mips_debug
= 0;
128 /* MIPS specific per-architecture information */
131 /* from the elf header */
135 enum mips_abi mips_abi
;
136 enum mips_abi found_abi
;
137 enum mips_fpu_type mips_fpu_type
;
138 int mips_last_arg_regnum
;
139 int mips_last_fp_arg_regnum
;
140 int default_mask_address_p
;
141 /* Is the target using 64-bit raw integer registers but only
142 storing a left-aligned 32-bit value in each? */
143 int mips64_transfers_32bit_regs_p
;
144 /* Indexes for various registers. IRIX and embedded have
145 different values. This contains the "public" fields. Don't
146 add any that do not need to be public. */
147 const struct mips_regnum
*regnum
;
148 /* Register names table for the current register set. */
149 const char **mips_processor_reg_names
;
153 n32n64_floatformat_always_valid (const struct floatformat
*fmt
,
159 /* FIXME: brobecker/2004-08-08: Long Double values are 128 bit long.
160 They are implemented as a pair of 64bit doubles where the high
161 part holds the result of the operation rounded to double, and
162 the low double holds the difference between the exact result and
163 the rounded result. So "high" + "low" contains the result with
164 added precision. Unfortunately, the floatformat structure used
165 by GDB is not powerful enough to describe this format. As a temporary
166 measure, we define a 128bit floatformat that only uses the high part.
167 We lose a bit of precision but that's probably the best we can do
168 for now with the current infrastructure. */
170 static const struct floatformat floatformat_n32n64_long_double_big
=
172 floatformat_big
, 128, 0, 1, 11, 1023, 2047, 12, 52,
173 floatformat_intbit_no
,
174 "floatformat_ieee_double_big",
175 n32n64_floatformat_always_valid
178 const struct mips_regnum
*
179 mips_regnum (struct gdbarch
*gdbarch
)
181 return gdbarch_tdep (gdbarch
)->regnum
;
185 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
187 return mips_regnum (gdbarch
)->fp0
+ 12;
190 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
191 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
193 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
195 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
197 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
199 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
200 functions to test, set, or clear bit 0 of addresses. */
203 is_mips16_addr (CORE_ADDR addr
)
209 unmake_mips16_addr (CORE_ADDR addr
)
211 return ((addr
) & ~1);
214 /* Return the contents of register REGNUM as a signed integer. */
217 read_signed_register (int regnum
)
220 regcache_cooked_read_signed (current_regcache
, regnum
, &val
);
225 read_signed_register_pid (int regnum
, ptid_t ptid
)
230 if (ptid_equal (ptid
, inferior_ptid
))
231 return read_signed_register (regnum
);
233 save_ptid
= inferior_ptid
;
235 inferior_ptid
= ptid
;
237 retval
= read_signed_register (regnum
);
239 inferior_ptid
= save_ptid
;
244 /* Return the MIPS ABI associated with GDBARCH. */
246 mips_abi (struct gdbarch
*gdbarch
)
248 return gdbarch_tdep (gdbarch
)->mips_abi
;
252 mips_isa_regsize (struct gdbarch
*gdbarch
)
254 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
255 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
258 /* Return the currently configured (or set) saved register size. */
260 static const char *mips_abi_regsize_string
= size_auto
;
263 mips_abi_regsize (struct gdbarch
*gdbarch
)
265 if (mips_abi_regsize_string
== size_auto
)
266 switch (mips_abi (gdbarch
))
268 case MIPS_ABI_EABI32
:
274 case MIPS_ABI_EABI64
:
276 case MIPS_ABI_UNKNOWN
:
279 internal_error (__FILE__
, __LINE__
, "bad switch");
281 else if (mips_abi_regsize_string
== size_64
)
283 else /* if (mips_abi_regsize_string == size_32) */
287 /* Functions for setting and testing a bit in a minimal symbol that
288 marks it as 16-bit function. The MSB of the minimal symbol's
289 "info" field is used for this purpose.
291 ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special",
292 i.e. refers to a 16-bit function, and sets a "special" bit in a
293 minimal symbol to mark it as a 16-bit function
295 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
298 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
300 if (((elf_symbol_type
*) (sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
302 MSYMBOL_INFO (msym
) = (char *)
303 (((long) MSYMBOL_INFO (msym
)) | 0x80000000);
304 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
309 msymbol_is_special (struct minimal_symbol
*msym
)
311 return (((long) MSYMBOL_INFO (msym
) & 0x80000000) != 0);
314 /* XFER a value from the big/little/left end of the register.
315 Depending on the size of the value it might occupy the entire
316 register or just part of it. Make an allowance for this, aligning
317 things accordingly. */
320 mips_xfer_register (struct regcache
*regcache
, int reg_num
, int length
,
321 enum bfd_endian endian
, bfd_byte
* in
,
322 const bfd_byte
* out
, int buf_offset
)
325 gdb_assert (reg_num
>= NUM_REGS
);
326 /* Need to transfer the left or right part of the register, based on
327 the targets byte order. */
331 reg_offset
= register_size (current_gdbarch
, reg_num
) - length
;
333 case BFD_ENDIAN_LITTLE
:
336 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
340 internal_error (__FILE__
, __LINE__
, "bad switch");
343 fprintf_unfiltered (gdb_stderr
,
344 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
345 reg_num
, reg_offset
, buf_offset
, length
);
346 if (mips_debug
&& out
!= NULL
)
349 fprintf_unfiltered (gdb_stdlog
, "out ");
350 for (i
= 0; i
< length
; i
++)
351 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
354 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
357 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
359 if (mips_debug
&& in
!= NULL
)
362 fprintf_unfiltered (gdb_stdlog
, "in ");
363 for (i
= 0; i
< length
; i
++)
364 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
367 fprintf_unfiltered (gdb_stdlog
, "\n");
370 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
371 compatiblity mode. A return value of 1 means that we have
372 physical 64-bit registers, but should treat them as 32-bit registers. */
375 mips2_fp_compat (void)
377 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
379 if (register_size (current_gdbarch
, mips_regnum (current_gdbarch
)->fp0
) ==
384 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
385 in all the places we deal with FP registers. PR gdb/413. */
386 /* Otherwise check the FR bit in the status register - it controls
387 the FP compatiblity mode. If it is clear we are in compatibility
389 if ((read_register (PS_REGNUM
) & ST0_FR
) == 0)
396 /* The amount of space reserved on the stack for registers. This is
397 different to MIPS_ABI_REGSIZE as it determines the alignment of
398 data allocated after the registers have run out. */
400 static const char *mips_stack_argsize_string
= size_auto
;
403 mips_stack_argsize (struct gdbarch
*gdbarch
)
405 if (mips_stack_argsize_string
== size_auto
)
406 return mips_abi_regsize (gdbarch
);
407 else if (mips_stack_argsize_string
== size_64
)
409 else /* if (mips_stack_argsize_string == size_32) */
413 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
415 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
417 static CORE_ADDR
read_next_frame_reg (struct frame_info
*, int);
419 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
421 static struct type
*mips_float_register_type (void);
422 static struct type
*mips_double_register_type (void);
424 /* The list of available "set mips " and "show mips " commands */
426 static struct cmd_list_element
*setmipscmdlist
= NULL
;
427 static struct cmd_list_element
*showmipscmdlist
= NULL
;
429 /* Integer registers 0 thru 31 are handled explicitly by
430 mips_register_name(). Processor specific registers 32 and above
431 are listed in the followign tables. */
434 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
438 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
439 "sr", "lo", "hi", "bad", "cause", "pc",
440 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
441 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
442 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
443 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
444 "fsr", "fir", "" /*"fp" */ , "",
445 "", "", "", "", "", "", "", "",
446 "", "", "", "", "", "", "", "",
449 /* Names of IDT R3041 registers. */
451 static const char *mips_r3041_reg_names
[] = {
452 "sr", "lo", "hi", "bad", "cause", "pc",
453 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
454 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
455 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
456 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
457 "fsr", "fir", "", /*"fp" */ "",
458 "", "", "bus", "ccfg", "", "", "", "",
459 "", "", "port", "cmp", "", "", "epc", "prid",
462 /* Names of tx39 registers. */
464 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
465 "sr", "lo", "hi", "bad", "cause", "pc",
466 "", "", "", "", "", "", "", "",
467 "", "", "", "", "", "", "", "",
468 "", "", "", "", "", "", "", "",
469 "", "", "", "", "", "", "", "",
471 "", "", "", "", "", "", "", "",
472 "", "", "config", "cache", "debug", "depc", "epc", ""
475 /* Names of IRIX registers. */
476 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
477 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
478 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
479 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
480 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
481 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
485 /* Return the name of the register corresponding to REGNO. */
487 mips_register_name (int regno
)
489 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
490 /* GPR names for all ABIs other than n32/n64. */
491 static char *mips_gpr_names
[] = {
492 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
493 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
494 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
495 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
498 /* GPR names for n32 and n64 ABIs. */
499 static char *mips_n32_n64_gpr_names
[] = {
500 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
501 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
502 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
503 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
506 enum mips_abi abi
= mips_abi (current_gdbarch
);
508 /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then
509 don't make the raw register names visible. */
510 int rawnum
= regno
% NUM_REGS
;
511 if (regno
< NUM_REGS
)
514 /* The MIPS integer registers are always mapped from 0 to 31. The
515 names of the registers (which reflects the conventions regarding
516 register use) vary depending on the ABI. */
517 if (0 <= rawnum
&& rawnum
< 32)
519 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
520 return mips_n32_n64_gpr_names
[rawnum
];
522 return mips_gpr_names
[rawnum
];
524 else if (32 <= rawnum
&& rawnum
< NUM_REGS
)
526 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
527 return tdep
->mips_processor_reg_names
[rawnum
- 32];
530 internal_error (__FILE__
, __LINE__
,
531 "mips_register_name: bad register number %d", rawnum
);
534 /* Return the groups that a MIPS register can be categorised into. */
537 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
538 struct reggroup
*reggroup
)
543 int rawnum
= regnum
% NUM_REGS
;
544 int pseudo
= regnum
/ NUM_REGS
;
545 if (reggroup
== all_reggroup
)
547 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
548 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
549 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
550 (gdbarch), as not all architectures are multi-arch. */
551 raw_p
= rawnum
< NUM_REGS
;
552 if (REGISTER_NAME (regnum
) == NULL
|| REGISTER_NAME (regnum
)[0] == '\0')
554 if (reggroup
== float_reggroup
)
555 return float_p
&& pseudo
;
556 if (reggroup
== vector_reggroup
)
557 return vector_p
&& pseudo
;
558 if (reggroup
== general_reggroup
)
559 return (!vector_p
&& !float_p
) && pseudo
;
560 /* Save the pseudo registers. Need to make certain that any code
561 extracting register values from a saved register cache also uses
563 if (reggroup
== save_reggroup
)
564 return raw_p
&& pseudo
;
565 /* Restore the same pseudo register. */
566 if (reggroup
== restore_reggroup
)
567 return raw_p
&& pseudo
;
571 /* Map the symbol table registers which live in the range [1 *
572 NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw
573 registers. Take care of alignment and size problems. */
576 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
577 int cookednum
, void *buf
)
579 int rawnum
= cookednum
% NUM_REGS
;
580 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
581 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
582 regcache_raw_read (regcache
, rawnum
, buf
);
583 else if (register_size (gdbarch
, rawnum
) >
584 register_size (gdbarch
, cookednum
))
586 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
587 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
588 regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
590 regcache_raw_read_part (regcache
, rawnum
, 4, 4, buf
);
593 internal_error (__FILE__
, __LINE__
, "bad register size");
597 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
598 struct regcache
*regcache
, int cookednum
,
601 int rawnum
= cookednum
% NUM_REGS
;
602 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
603 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
604 regcache_raw_write (regcache
, rawnum
, buf
);
605 else if (register_size (gdbarch
, rawnum
) >
606 register_size (gdbarch
, cookednum
))
608 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
609 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
610 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
612 regcache_raw_write_part (regcache
, rawnum
, 4, 4, buf
);
615 internal_error (__FILE__
, __LINE__
, "bad register size");
618 /* Table to translate MIPS16 register field to actual register number. */
619 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
621 /* Heuristic_proc_start may hunt through the text section for a long
622 time across a 2400 baud serial line. Allows the user to limit this
625 static unsigned int heuristic_fence_post
= 0;
627 /* Number of bytes of storage in the actual machine representation for
628 register N. NOTE: This defines the pseudo register type so need to
629 rebuild the architecture vector. */
631 static int mips64_transfers_32bit_regs_p
= 0;
634 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
635 struct cmd_list_element
*c
)
637 struct gdbarch_info info
;
638 gdbarch_info_init (&info
);
639 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
640 instead of relying on globals. Doing that would let generic code
641 handle the search for this specific architecture. */
642 if (!gdbarch_update_p (info
))
644 mips64_transfers_32bit_regs_p
= 0;
645 error ("32-bit compatibility mode not supported");
649 /* Convert to/from a register and the corresponding memory value. */
652 mips_convert_register_p (int regnum
, struct type
*type
)
654 return (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
655 && register_size (current_gdbarch
, regnum
) == 4
656 && (regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
657 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32
658 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
662 mips_register_to_value (struct frame_info
*frame
, int regnum
,
663 struct type
*type
, void *to
)
665 get_frame_register (frame
, regnum
+ 0, (char *) to
+ 4);
666 get_frame_register (frame
, regnum
+ 1, (char *) to
+ 0);
670 mips_value_to_register (struct frame_info
*frame
, int regnum
,
671 struct type
*type
, const void *from
)
673 put_frame_register (frame
, regnum
+ 0, (const char *) from
+ 4);
674 put_frame_register (frame
, regnum
+ 1, (const char *) from
+ 0);
677 /* Return the GDB type object for the "standard" data type of data in
681 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
683 gdb_assert (regnum
>= 0 && regnum
< 2 * NUM_REGS
);
684 if ((regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
685 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32)
687 /* The floating-point registers raw, or cooked, always match
688 mips_isa_regsize(), and also map 1:1, byte for byte. */
689 switch (gdbarch_byte_order (gdbarch
))
692 if (mips_isa_regsize (gdbarch
) == 4)
693 return builtin_type_ieee_single_big
;
695 return builtin_type_ieee_double_big
;
696 case BFD_ENDIAN_LITTLE
:
697 if (mips_isa_regsize (gdbarch
) == 4)
698 return builtin_type_ieee_single_little
;
700 return builtin_type_ieee_double_little
;
701 case BFD_ENDIAN_UNKNOWN
:
703 internal_error (__FILE__
, __LINE__
, "bad switch");
706 else if (regnum
< NUM_REGS
)
708 /* The raw or ISA registers. These are all sized according to
710 if (mips_isa_regsize (gdbarch
) == 4)
711 return builtin_type_int32
;
713 return builtin_type_int64
;
717 /* The cooked or ABI registers. These are sized according to
718 the ABI (with a few complications). */
719 if (regnum
>= (NUM_REGS
720 + mips_regnum (current_gdbarch
)->fp_control_status
)
721 && regnum
<= NUM_REGS
+ LAST_EMBED_REGNUM
)
722 /* The pseudo/cooked view of the embedded registers is always
723 32-bit. The raw view is handled below. */
724 return builtin_type_int32
;
725 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
726 /* The target, while possibly using a 64-bit register buffer,
727 is only transfering 32-bits of each integer register.
728 Reflect this in the cooked/pseudo (ABI) register value. */
729 return builtin_type_int32
;
730 else if (mips_abi_regsize (gdbarch
) == 4)
731 /* The ABI is restricted to 32-bit registers (the ISA could be
733 return builtin_type_int32
;
736 return builtin_type_int64
;
740 /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */
745 return read_signed_register (MIPS_SP_REGNUM
);
748 /* Should the upper word of 64-bit addresses be zeroed? */
749 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
752 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
754 switch (mask_address_var
)
756 case AUTO_BOOLEAN_TRUE
:
758 case AUTO_BOOLEAN_FALSE
:
761 case AUTO_BOOLEAN_AUTO
:
762 return tdep
->default_mask_address_p
;
764 internal_error (__FILE__
, __LINE__
, "mips_mask_address_p: bad switch");
770 show_mask_address (char *cmd
, int from_tty
, struct cmd_list_element
*c
)
772 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
773 switch (mask_address_var
)
775 case AUTO_BOOLEAN_TRUE
:
776 printf_filtered ("The 32 bit mips address mask is enabled\n");
778 case AUTO_BOOLEAN_FALSE
:
779 printf_filtered ("The 32 bit mips address mask is disabled\n");
781 case AUTO_BOOLEAN_AUTO
:
783 ("The 32 bit address mask is set automatically. Currently %s\n",
784 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
787 internal_error (__FILE__
, __LINE__
, "show_mask_address: bad switch");
792 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
795 mips_pc_is_mips16 (CORE_ADDR memaddr
)
797 struct minimal_symbol
*sym
;
799 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
800 if (is_mips16_addr (memaddr
))
803 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
804 the high bit of the info field. Use this to decide if the function is
805 MIPS16 or normal MIPS. */
806 sym
= lookup_minimal_symbol_by_pc (memaddr
);
808 return msymbol_is_special (sym
);
813 /* MIPS believes that the PC has a sign extended value. Perhaps the
814 all registers should be sign extended for simplicity? */
817 mips_read_pc (ptid_t ptid
)
819 return read_signed_register_pid (mips_regnum (current_gdbarch
)->pc
, ptid
);
823 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
825 return frame_unwind_register_signed (next_frame
,
826 NUM_REGS
+ mips_regnum (gdbarch
)->pc
);
829 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
830 dummy frame. The frame ID's base needs to match the TOS value
831 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
834 static struct frame_id
835 mips_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
837 return frame_id_build (frame_unwind_register_signed (next_frame
, NUM_REGS
+ MIPS_SP_REGNUM
),
838 frame_pc_unwind (next_frame
));
842 mips_write_pc (CORE_ADDR pc
, ptid_t ptid
)
844 write_register_pid (mips_regnum (current_gdbarch
)->pc
, pc
, ptid
);
847 /* Fetch and return instruction from the specified location. If the PC
848 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
851 mips_fetch_instruction (CORE_ADDR addr
)
853 char buf
[MIPS32_INSN_SIZE
];
857 if (mips_pc_is_mips16 (addr
))
859 instlen
= MIPS16_INSN_SIZE
;
860 addr
= unmake_mips16_addr (addr
);
863 instlen
= MIPS32_INSN_SIZE
;
864 status
= deprecated_read_memory_nobpt (addr
, buf
, instlen
);
866 memory_error (status
, addr
);
867 return extract_unsigned_integer (buf
, instlen
);
870 /* These the fields of 32 bit mips instructions */
871 #define mips32_op(x) (x >> 26)
872 #define itype_op(x) (x >> 26)
873 #define itype_rs(x) ((x >> 21) & 0x1f)
874 #define itype_rt(x) ((x >> 16) & 0x1f)
875 #define itype_immediate(x) (x & 0xffff)
877 #define jtype_op(x) (x >> 26)
878 #define jtype_target(x) (x & 0x03ffffff)
880 #define rtype_op(x) (x >> 26)
881 #define rtype_rs(x) ((x >> 21) & 0x1f)
882 #define rtype_rt(x) ((x >> 16) & 0x1f)
883 #define rtype_rd(x) ((x >> 11) & 0x1f)
884 #define rtype_shamt(x) ((x >> 6) & 0x1f)
885 #define rtype_funct(x) (x & 0x3f)
888 mips32_relative_offset (unsigned long inst
)
891 x
= itype_immediate (inst
);
892 if (x
& 0x8000) /* sign bit set */
894 x
|= 0xffff0000; /* sign extension */
900 /* Determine whate to set a single step breakpoint while considering
903 mips32_next_pc (CORE_ADDR pc
)
907 inst
= mips_fetch_instruction (pc
);
908 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
910 if (itype_op (inst
) >> 2 == 5)
911 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
913 op
= (itype_op (inst
) & 0x03);
928 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
929 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
931 int tf
= itype_rt (inst
) & 0x01;
932 int cnum
= itype_rt (inst
) >> 2;
934 read_signed_register (mips_regnum (current_gdbarch
)->
936 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
938 if (((cond
>> cnum
) & 0x01) == tf
)
939 pc
+= mips32_relative_offset (inst
) + 4;
944 pc
+= 4; /* Not a branch, next instruction is easy */
947 { /* This gets way messy */
949 /* Further subdivide into SPECIAL, REGIMM and other */
950 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
952 case 0: /* SPECIAL */
953 op
= rtype_funct (inst
);
958 /* Set PC to that address */
959 pc
= read_signed_register (rtype_rs (inst
));
965 break; /* end SPECIAL */
968 op
= itype_rt (inst
); /* branch condition */
973 case 16: /* BLTZAL */
974 case 18: /* BLTZALL */
976 if (read_signed_register (itype_rs (inst
)) < 0)
977 pc
+= mips32_relative_offset (inst
) + 4;
979 pc
+= 8; /* after the delay slot */
983 case 17: /* BGEZAL */
984 case 19: /* BGEZALL */
985 if (read_signed_register (itype_rs (inst
)) >= 0)
986 pc
+= mips32_relative_offset (inst
) + 4;
988 pc
+= 8; /* after the delay slot */
990 /* All of the other instructions in the REGIMM category */
995 break; /* end REGIMM */
1000 reg
= jtype_target (inst
) << 2;
1001 /* Upper four bits get never changed... */
1002 pc
= reg
+ ((pc
+ 4) & 0xf0000000);
1005 /* FIXME case JALX : */
1008 reg
= jtype_target (inst
) << 2;
1009 pc
= reg
+ ((pc
+ 4) & 0xf0000000) + 1; /* yes, +1 */
1010 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1012 break; /* The new PC will be alternate mode */
1013 case 4: /* BEQ, BEQL */
1015 if (read_signed_register (itype_rs (inst
)) ==
1016 read_signed_register (itype_rt (inst
)))
1017 pc
+= mips32_relative_offset (inst
) + 4;
1021 case 5: /* BNE, BNEL */
1023 if (read_signed_register (itype_rs (inst
)) !=
1024 read_signed_register (itype_rt (inst
)))
1025 pc
+= mips32_relative_offset (inst
) + 4;
1029 case 6: /* BLEZ, BLEZL */
1030 if (read_signed_register (itype_rs (inst
)) <= 0)
1031 pc
+= mips32_relative_offset (inst
) + 4;
1037 greater_branch
: /* BGTZ, BGTZL */
1038 if (read_signed_register (itype_rs (inst
)) > 0)
1039 pc
+= mips32_relative_offset (inst
) + 4;
1046 } /* mips32_next_pc */
1048 /* Decoding the next place to set a breakpoint is irregular for the
1049 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1050 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1051 We dont want to set a single step instruction on the extend instruction
1055 /* Lots of mips16 instruction formats */
1056 /* Predicting jumps requires itype,ritype,i8type
1057 and their extensions extItype,extritype,extI8type
1059 enum mips16_inst_fmts
1061 itype
, /* 0 immediate 5,10 */
1062 ritype
, /* 1 5,3,8 */
1063 rrtype
, /* 2 5,3,3,5 */
1064 rritype
, /* 3 5,3,3,5 */
1065 rrrtype
, /* 4 5,3,3,3,2 */
1066 rriatype
, /* 5 5,3,3,1,4 */
1067 shifttype
, /* 6 5,3,3,3,2 */
1068 i8type
, /* 7 5,3,8 */
1069 i8movtype
, /* 8 5,3,3,5 */
1070 i8mov32rtype
, /* 9 5,3,5,3 */
1071 i64type
, /* 10 5,3,8 */
1072 ri64type
, /* 11 5,3,3,5 */
1073 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1074 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1075 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1076 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1077 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1078 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1079 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1080 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1081 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1082 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1084 /* I am heaping all the fields of the formats into one structure and
1085 then, only the fields which are involved in instruction extension */
1089 unsigned int regx
; /* Function in i8 type */
1094 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1095 for the bits which make up the immediatate extension. */
1098 extended_offset (unsigned int extension
)
1101 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1103 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1105 value
|= extension
& 0x01f; /* extract 4:0 */
1109 /* Only call this function if you know that this is an extendable
1110 instruction, It wont malfunction, but why make excess remote memory references?
1111 If the immediate operands get sign extended or somthing, do it after
1112 the extension is performed.
1114 /* FIXME: Every one of these cases needs to worry about sign extension
1115 when the offset is to be used in relative addressing */
1119 fetch_mips_16 (CORE_ADDR pc
)
1122 pc
&= 0xfffffffe; /* clear the low order bit */
1123 target_read_memory (pc
, buf
, 2);
1124 return extract_unsigned_integer (buf
, 2);
1128 unpack_mips16 (CORE_ADDR pc
,
1129 unsigned int extension
,
1131 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1136 switch (insn_format
)
1143 value
= extended_offset (extension
);
1144 value
= value
<< 11; /* rom for the original value */
1145 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1149 value
= inst
& 0x7ff;
1150 /* FIXME : Consider sign extension */
1159 { /* A register identifier and an offset */
1160 /* Most of the fields are the same as I type but the
1161 immediate value is of a different length */
1165 value
= extended_offset (extension
);
1166 value
= value
<< 8; /* from the original instruction */
1167 value
|= inst
& 0xff; /* eleven bits from instruction */
1168 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1169 if (value
& 0x4000) /* test the sign bit , bit 26 */
1171 value
&= ~0x3fff; /* remove the sign bit */
1177 value
= inst
& 0xff; /* 8 bits */
1178 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1179 /* FIXME: Do sign extension , this format needs it */
1180 if (value
& 0x80) /* THIS CONFUSES ME */
1182 value
&= 0xef; /* remove the sign bit */
1192 unsigned long value
;
1193 unsigned int nexthalf
;
1194 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1195 value
= value
<< 16;
1196 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1204 internal_error (__FILE__
, __LINE__
, "bad switch");
1206 upk
->offset
= offset
;
1213 add_offset_16 (CORE_ADDR pc
, int offset
)
1215 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000)));
1219 extended_mips16_next_pc (CORE_ADDR pc
,
1220 unsigned int extension
, unsigned int insn
)
1222 int op
= (insn
>> 11);
1225 case 2: /* Branch */
1228 struct upk_mips16 upk
;
1229 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1230 offset
= upk
.offset
;
1236 pc
+= (offset
<< 1) + 2;
1239 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1241 struct upk_mips16 upk
;
1242 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1243 pc
= add_offset_16 (pc
, upk
.offset
);
1244 if ((insn
>> 10) & 0x01) /* Exchange mode */
1245 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1252 struct upk_mips16 upk
;
1254 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1255 reg
= read_signed_register (upk
.regx
);
1257 pc
+= (upk
.offset
<< 1) + 2;
1264 struct upk_mips16 upk
;
1266 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1267 reg
= read_signed_register (upk
.regx
);
1269 pc
+= (upk
.offset
<< 1) + 2;
1274 case 12: /* I8 Formats btez btnez */
1276 struct upk_mips16 upk
;
1278 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1279 /* upk.regx contains the opcode */
1280 reg
= read_signed_register (24); /* Test register is 24 */
1281 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1282 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1283 /* pc = add_offset_16(pc,upk.offset) ; */
1284 pc
+= (upk
.offset
<< 1) + 2;
1289 case 29: /* RR Formats JR, JALR, JALR-RA */
1291 struct upk_mips16 upk
;
1292 /* upk.fmt = rrtype; */
1297 upk
.regx
= (insn
>> 8) & 0x07;
1298 upk
.regy
= (insn
>> 5) & 0x07;
1306 break; /* Function return instruction */
1312 break; /* BOGUS Guess */
1314 pc
= read_signed_register (reg
);
1321 /* This is an instruction extension. Fetch the real instruction
1322 (which follows the extension) and decode things based on
1326 pc
= extended_mips16_next_pc (pc
, insn
, fetch_mips_16 (pc
));
1339 mips16_next_pc (CORE_ADDR pc
)
1341 unsigned int insn
= fetch_mips_16 (pc
);
1342 return extended_mips16_next_pc (pc
, 0, insn
);
1345 /* The mips_next_pc function supports single_step when the remote
1346 target monitor or stub is not developed enough to do a single_step.
1347 It works by decoding the current instruction and predicting where a
1348 branch will go. This isnt hard because all the data is available.
1349 The MIPS32 and MIPS16 variants are quite different */
1351 mips_next_pc (CORE_ADDR pc
)
1354 return mips16_next_pc (pc
);
1356 return mips32_next_pc (pc
);
1359 struct mips_frame_cache
1362 struct trad_frame_saved_reg
*saved_regs
;
1365 /* Set a register's saved stack address in temp_saved_regs. If an
1366 address has already been set for this register, do nothing; this
1367 way we will only recognize the first save of a given register in a
1370 For simplicity, save the address in both [0 .. NUM_REGS) and
1371 [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range
1372 is used as it is only second range (the ABI instead of ISA
1373 registers) that comes into play when finding saved registers in a
1377 set_reg_offset (struct mips_frame_cache
*this_cache
, int regnum
,
1380 if (this_cache
!= NULL
1381 && this_cache
->saved_regs
[regnum
].addr
== -1)
1383 this_cache
->saved_regs
[regnum
+ 0 * NUM_REGS
].addr
= offset
;
1384 this_cache
->saved_regs
[regnum
+ 1 * NUM_REGS
].addr
= offset
;
1389 /* Fetch the immediate value from a MIPS16 instruction.
1390 If the previous instruction was an EXTEND, use it to extend
1391 the upper bits of the immediate value. This is a helper function
1392 for mips16_scan_prologue. */
1395 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1396 unsigned short inst
, /* current instruction */
1397 int nbits
, /* number of bits in imm field */
1398 int scale
, /* scale factor to be applied to imm */
1399 int is_signed
) /* is the imm field signed? */
1403 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1405 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1406 if (offset
& 0x8000) /* check for negative extend */
1407 offset
= 0 - (0x10000 - (offset
& 0xffff));
1408 return offset
| (inst
& 0x1f);
1412 int max_imm
= 1 << nbits
;
1413 int mask
= max_imm
- 1;
1414 int sign_bit
= max_imm
>> 1;
1416 offset
= inst
& mask
;
1417 if (is_signed
&& (offset
& sign_bit
))
1418 offset
= 0 - (max_imm
- offset
);
1419 return offset
* scale
;
1424 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1425 the associated FRAME_CACHE if not null.
1426 Return the address of the first instruction past the prologue. */
1429 mips16_scan_prologue (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1430 struct frame_info
*next_frame
,
1431 struct mips_frame_cache
*this_cache
)
1434 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1436 long frame_offset
= 0; /* Size of stack frame. */
1437 long frame_adjust
= 0; /* Offset of FP from SP. */
1438 int frame_reg
= MIPS_SP_REGNUM
;
1439 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1440 unsigned inst
= 0; /* current instruction */
1441 unsigned entry_inst
= 0; /* the entry instruction */
1444 int extend_bytes
= 0;
1445 int prev_extend_bytes
;
1446 CORE_ADDR end_prologue_addr
= 0;
1448 /* Can be called when there's no process, and hence when there's no
1450 if (next_frame
!= NULL
)
1451 sp
= read_next_frame_reg (next_frame
, NUM_REGS
+ MIPS_SP_REGNUM
);
1455 if (limit_pc
> start_pc
+ 200)
1456 limit_pc
= start_pc
+ 200;
1458 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSN_SIZE
)
1460 /* Save the previous instruction. If it's an EXTEND, we'll extract
1461 the immediate offset extension from it in mips16_get_imm. */
1464 /* Fetch and decode the instruction. */
1465 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1467 /* Normally we ignore extend instructions. However, if it is
1468 not followed by a valid prologue instruction, then this
1469 instruction is not part of the prologue either. We must
1470 remember in this case to adjust the end_prologue_addr back
1472 if ((inst
& 0xf800) == 0xf000) /* extend */
1474 extend_bytes
= MIPS16_INSN_SIZE
;
1478 prev_extend_bytes
= extend_bytes
;
1481 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1482 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1484 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1485 if (offset
< 0) /* negative stack adjustment? */
1486 frame_offset
-= offset
;
1488 /* Exit loop if a positive stack adjustment is found, which
1489 usually means that the stack cleanup code in the function
1490 epilogue is reached. */
1493 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1495 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1496 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1497 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1499 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1501 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1502 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1503 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1505 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1507 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1508 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1510 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1512 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1513 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1515 else if (inst
== 0x673d) /* move $s1, $sp */
1520 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1522 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1523 frame_addr
= sp
+ offset
;
1525 frame_adjust
= offset
;
1527 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1529 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1530 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1531 set_reg_offset (this_cache
, reg
, frame_addr
+ offset
);
1533 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1535 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1536 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1537 set_reg_offset (this_cache
, reg
, frame_addr
+ offset
);
1539 else if ((inst
& 0xf81f) == 0xe809
1540 && (inst
& 0x700) != 0x700) /* entry */
1541 entry_inst
= inst
; /* save for later processing */
1542 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1543 cur_pc
+= MIPS16_INSN_SIZE
; /* 32-bit instruction */
1544 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
1546 /* This instruction is part of the prologue, but we don't
1547 need to do anything special to handle it. */
1551 /* This instruction is not an instruction typically found
1552 in a prologue, so we must have reached the end of the
1554 if (end_prologue_addr
== 0)
1555 end_prologue_addr
= cur_pc
- prev_extend_bytes
;
1559 /* The entry instruction is typically the first instruction in a function,
1560 and it stores registers at offsets relative to the value of the old SP
1561 (before the prologue). But the value of the sp parameter to this
1562 function is the new SP (after the prologue has been executed). So we
1563 can't calculate those offsets until we've seen the entire prologue,
1564 and can calculate what the old SP must have been. */
1565 if (entry_inst
!= 0)
1567 int areg_count
= (entry_inst
>> 8) & 7;
1568 int sreg_count
= (entry_inst
>> 6) & 3;
1570 /* The entry instruction always subtracts 32 from the SP. */
1573 /* Now we can calculate what the SP must have been at the
1574 start of the function prologue. */
1577 /* Check if a0-a3 were saved in the caller's argument save area. */
1578 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1580 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1581 offset
+= mips_abi_regsize (current_gdbarch
);
1584 /* Check if the ra register was pushed on the stack. */
1586 if (entry_inst
& 0x20)
1588 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1589 offset
-= mips_abi_regsize (current_gdbarch
);
1592 /* Check if the s0 and s1 registers were pushed on the stack. */
1593 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1595 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1596 offset
-= mips_abi_regsize (current_gdbarch
);
1600 if (this_cache
!= NULL
)
1603 (frame_unwind_register_signed (next_frame
, NUM_REGS
+ frame_reg
)
1604 + frame_offset
- frame_adjust
);
1605 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
1606 be able to get rid of the assignment below, evetually. But it's
1607 still needed for now. */
1608 this_cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
1609 = this_cache
->saved_regs
[NUM_REGS
+ MIPS_RA_REGNUM
];
1612 /* If we didn't reach the end of the prologue when scanning the function
1613 instructions, then set end_prologue_addr to the address of the
1614 instruction immediately after the last one we scanned. */
1615 if (end_prologue_addr
== 0)
1616 end_prologue_addr
= cur_pc
;
1618 return end_prologue_addr
;
1621 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
1622 Procedures that use the 32-bit instruction set are handled by the
1623 mips_insn32 unwinder. */
1625 static struct mips_frame_cache
*
1626 mips_insn16_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1628 struct mips_frame_cache
*cache
;
1630 if ((*this_cache
) != NULL
)
1631 return (*this_cache
);
1632 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1633 (*this_cache
) = cache
;
1634 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1636 /* Analyze the function prologue. */
1638 const CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1639 CORE_ADDR start_addr
;
1641 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
1642 if (start_addr
== 0)
1643 start_addr
= heuristic_proc_start (pc
);
1644 /* We can't analyze the prologue if we couldn't find the begining
1646 if (start_addr
== 0)
1649 mips16_scan_prologue (start_addr
, pc
, next_frame
, *this_cache
);
1652 /* SP_REGNUM, contains the value and not the address. */
1653 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
1655 return (*this_cache
);
1659 mips_insn16_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1660 struct frame_id
*this_id
)
1662 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1664 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
1668 mips_insn16_frame_prev_register (struct frame_info
*next_frame
,
1670 int regnum
, int *optimizedp
,
1671 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1672 int *realnump
, void *valuep
)
1674 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1676 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
1677 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
1680 static const struct frame_unwind mips_insn16_frame_unwind
=
1683 mips_insn16_frame_this_id
,
1684 mips_insn16_frame_prev_register
1687 static const struct frame_unwind
*
1688 mips_insn16_frame_sniffer (struct frame_info
*next_frame
)
1690 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1691 if (mips_pc_is_mips16 (pc
))
1692 return &mips_insn16_frame_unwind
;
1697 mips_insn16_frame_base_address (struct frame_info
*next_frame
,
1700 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1705 static const struct frame_base mips_insn16_frame_base
=
1707 &mips_insn16_frame_unwind
,
1708 mips_insn16_frame_base_address
,
1709 mips_insn16_frame_base_address
,
1710 mips_insn16_frame_base_address
1713 static const struct frame_base
*
1714 mips_insn16_frame_base_sniffer (struct frame_info
*next_frame
)
1716 if (mips_insn16_frame_sniffer (next_frame
) != NULL
)
1717 return &mips_insn16_frame_base
;
1722 /* Mark all the registers as unset in the saved_regs array
1723 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
1726 reset_saved_regs (struct mips_frame_cache
*this_cache
)
1728 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
1732 const int num_regs
= NUM_REGS
;
1735 for (i
= 0; i
< num_regs
; i
++)
1737 this_cache
->saved_regs
[i
].addr
= -1;
1742 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1743 the associated FRAME_CACHE if not null.
1744 Return the address of the first instruction past the prologue. */
1747 mips32_scan_prologue (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1748 struct frame_info
*next_frame
,
1749 struct mips_frame_cache
*this_cache
)
1752 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
1755 int frame_reg
= MIPS_SP_REGNUM
;
1757 CORE_ADDR end_prologue_addr
= 0;
1758 int seen_sp_adjust
= 0;
1759 int load_immediate_bytes
= 0;
1761 /* Can be called when there's no process, and hence when there's no
1763 if (next_frame
!= NULL
)
1764 sp
= read_next_frame_reg (next_frame
, NUM_REGS
+ MIPS_SP_REGNUM
);
1768 if (limit_pc
> start_pc
+ 200)
1769 limit_pc
= start_pc
+ 200;
1774 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS32_INSN_SIZE
)
1776 unsigned long inst
, high_word
, low_word
;
1779 /* Fetch the instruction. */
1780 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
1782 /* Save some code by pre-extracting some useful fields. */
1783 high_word
= (inst
>> 16) & 0xffff;
1784 low_word
= inst
& 0xffff;
1785 reg
= high_word
& 0x1f;
1787 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
1788 || high_word
== 0x23bd /* addi $sp,$sp,-i */
1789 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
1791 if (low_word
& 0x8000) /* negative stack adjustment? */
1792 frame_offset
+= 0x10000 - low_word
;
1794 /* Exit loop if a positive stack adjustment is found, which
1795 usually means that the stack cleanup code in the function
1796 epilogue is reached. */
1800 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1802 set_reg_offset (this_cache
, reg
, sp
+ low_word
);
1804 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1806 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
1807 set_reg_offset (this_cache
, reg
, sp
+ low_word
);
1809 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
1811 /* Old gcc frame, r30 is virtual frame pointer. */
1812 if ((long) low_word
!= frame_offset
)
1813 frame_addr
= sp
+ low_word
;
1814 else if (frame_reg
== MIPS_SP_REGNUM
)
1816 unsigned alloca_adjust
;
1819 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
1820 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
1821 if (alloca_adjust
> 0)
1823 /* FP > SP + frame_size. This may be because of
1824 an alloca or somethings similar. Fix sp to
1825 "pre-alloca" value, and try again. */
1826 sp
+= alloca_adjust
;
1827 /* Need to reset the status of all registers. Otherwise,
1828 we will hit a guard that prevents the new address
1829 for each register to be recomputed during the second
1831 reset_saved_regs (this_cache
);
1836 /* move $30,$sp. With different versions of gas this will be either
1837 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
1838 Accept any one of these. */
1839 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
1841 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
1842 if (frame_reg
== MIPS_SP_REGNUM
)
1844 unsigned alloca_adjust
;
1847 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
1848 alloca_adjust
= (unsigned) (frame_addr
- sp
);
1849 if (alloca_adjust
> 0)
1851 /* FP > SP + frame_size. This may be because of
1852 an alloca or somethings similar. Fix sp to
1853 "pre-alloca" value, and try again. */
1855 /* Need to reset the status of all registers. Otherwise,
1856 we will hit a guard that prevents the new address
1857 for each register to be recomputed during the second
1859 reset_saved_regs (this_cache
);
1864 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
1866 set_reg_offset (this_cache
, reg
, frame_addr
+ low_word
);
1868 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
1869 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
1870 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
1871 || high_word
== 0x3c1c /* lui $gp,n */
1872 || high_word
== 0x279c /* addiu $gp,$gp,n */
1873 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
1874 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
1877 /* These instructions are part of the prologue, but we don't
1878 need to do anything special to handle them. */
1880 /* The instructions below load $at or $t0 with an immediate
1881 value in preparation for a stack adjustment via
1882 subu $sp,$sp,[$at,$t0]. These instructions could also
1883 initialize a local variable, so we accept them only before
1884 a stack adjustment instruction was seen. */
1885 else if (!seen_sp_adjust
1886 && (high_word
== 0x3c01 /* lui $at,n */
1887 || high_word
== 0x3c08 /* lui $t0,n */
1888 || high_word
== 0x3421 /* ori $at,$at,n */
1889 || high_word
== 0x3508 /* ori $t0,$t0,n */
1890 || high_word
== 0x3401 /* ori $at,$zero,n */
1891 || high_word
== 0x3408 /* ori $t0,$zero,n */
1894 load_immediate_bytes
+= MIPS32_INSN_SIZE
; /* FIXME! */
1898 /* This instruction is not an instruction typically found
1899 in a prologue, so we must have reached the end of the
1901 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
1902 loop now? Why would we need to continue scanning the function
1904 if (end_prologue_addr
== 0)
1905 end_prologue_addr
= cur_pc
;
1909 if (this_cache
!= NULL
)
1912 (frame_unwind_register_signed (next_frame
, NUM_REGS
+ frame_reg
)
1914 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
1915 this assignment below, eventually. But it's still needed
1917 this_cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
1918 = this_cache
->saved_regs
[NUM_REGS
+ MIPS_RA_REGNUM
];
1921 /* If we didn't reach the end of the prologue when scanning the function
1922 instructions, then set end_prologue_addr to the address of the
1923 instruction immediately after the last one we scanned. */
1924 /* brobecker/2004-10-10: I don't think this would ever happen, but
1925 we may as well be careful and do our best if we have a null
1926 end_prologue_addr. */
1927 if (end_prologue_addr
== 0)
1928 end_prologue_addr
= cur_pc
;
1930 /* In a frameless function, we might have incorrectly
1931 skipped some load immediate instructions. Undo the skipping
1932 if the load immediate was not followed by a stack adjustment. */
1933 if (load_immediate_bytes
&& !seen_sp_adjust
)
1934 end_prologue_addr
-= load_immediate_bytes
;
1936 return end_prologue_addr
;
1939 /* Heuristic unwinder for procedures using 32-bit instructions (covers
1940 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
1941 instructions (a.k.a. MIPS16) are handled by the mips_insn16
1944 static struct mips_frame_cache
*
1945 mips_insn32_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1947 struct mips_frame_cache
*cache
;
1949 if ((*this_cache
) != NULL
)
1950 return (*this_cache
);
1952 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1953 (*this_cache
) = cache
;
1954 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1956 /* Analyze the function prologue. */
1958 const CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1959 CORE_ADDR start_addr
;
1961 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
1962 if (start_addr
== 0)
1963 start_addr
= heuristic_proc_start (pc
);
1964 /* We can't analyze the prologue if we couldn't find the begining
1966 if (start_addr
== 0)
1969 mips32_scan_prologue (start_addr
, pc
, next_frame
, *this_cache
);
1972 /* SP_REGNUM, contains the value and not the address. */
1973 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
1975 return (*this_cache
);
1979 mips_insn32_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1980 struct frame_id
*this_id
)
1982 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
1984 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
1988 mips_insn32_frame_prev_register (struct frame_info
*next_frame
,
1990 int regnum
, int *optimizedp
,
1991 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1992 int *realnump
, void *valuep
)
1994 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
1996 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
1997 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
2000 static const struct frame_unwind mips_insn32_frame_unwind
=
2003 mips_insn32_frame_this_id
,
2004 mips_insn32_frame_prev_register
2007 static const struct frame_unwind
*
2008 mips_insn32_frame_sniffer (struct frame_info
*next_frame
)
2010 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2011 if (! mips_pc_is_mips16 (pc
))
2012 return &mips_insn32_frame_unwind
;
2017 mips_insn32_frame_base_address (struct frame_info
*next_frame
,
2020 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2025 static const struct frame_base mips_insn32_frame_base
=
2027 &mips_insn32_frame_unwind
,
2028 mips_insn32_frame_base_address
,
2029 mips_insn32_frame_base_address
,
2030 mips_insn32_frame_base_address
2033 static const struct frame_base
*
2034 mips_insn32_frame_base_sniffer (struct frame_info
*next_frame
)
2036 if (mips_insn32_frame_sniffer (next_frame
) != NULL
)
2037 return &mips_insn32_frame_base
;
2042 static struct trad_frame_cache
*
2043 mips_stub_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
2046 CORE_ADDR start_addr
;
2047 CORE_ADDR stack_addr
;
2048 struct trad_frame_cache
*this_trad_cache
;
2050 if ((*this_cache
) != NULL
)
2051 return (*this_cache
);
2052 this_trad_cache
= trad_frame_cache_zalloc (next_frame
);
2053 (*this_cache
) = this_trad_cache
;
2055 /* The return address is in the link register. */
2056 trad_frame_set_reg_realreg (this_trad_cache
, PC_REGNUM
, MIPS_RA_REGNUM
);
2058 /* Frame ID, since it's a frameless / stackless function, no stack
2059 space is allocated and SP on entry is the current SP. */
2060 pc
= frame_pc_unwind (next_frame
);
2061 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2062 stack_addr
= frame_unwind_register_signed (next_frame
, MIPS_SP_REGNUM
);
2063 trad_frame_set_id (this_trad_cache
, frame_id_build (start_addr
, stack_addr
));
2065 /* Assume that the frame's base is the same as the
2067 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
2069 return this_trad_cache
;
2073 mips_stub_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2074 struct frame_id
*this_id
)
2076 struct trad_frame_cache
*this_trad_cache
2077 = mips_stub_frame_cache (next_frame
, this_cache
);
2078 trad_frame_get_id (this_trad_cache
, this_id
);
2082 mips_stub_frame_prev_register (struct frame_info
*next_frame
,
2084 int regnum
, int *optimizedp
,
2085 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2086 int *realnump
, void *valuep
)
2088 struct trad_frame_cache
*this_trad_cache
2089 = mips_stub_frame_cache (next_frame
, this_cache
);
2090 trad_frame_get_register (this_trad_cache
, next_frame
, regnum
, optimizedp
,
2091 lvalp
, addrp
, realnump
, valuep
);
2094 static const struct frame_unwind mips_stub_frame_unwind
=
2097 mips_stub_frame_this_id
,
2098 mips_stub_frame_prev_register
2101 static const struct frame_unwind
*
2102 mips_stub_frame_sniffer (struct frame_info
*next_frame
)
2104 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2105 if (in_plt_section (pc
, NULL
))
2106 return &mips_stub_frame_unwind
;
2112 mips_stub_frame_base_address (struct frame_info
*next_frame
,
2115 struct trad_frame_cache
*this_trad_cache
2116 = mips_stub_frame_cache (next_frame
, this_cache
);
2117 return trad_frame_get_this_base (this_trad_cache
);
2120 static const struct frame_base mips_stub_frame_base
=
2122 &mips_stub_frame_unwind
,
2123 mips_stub_frame_base_address
,
2124 mips_stub_frame_base_address
,
2125 mips_stub_frame_base_address
2128 static const struct frame_base
*
2129 mips_stub_frame_base_sniffer (struct frame_info
*next_frame
)
2131 if (mips_stub_frame_sniffer (next_frame
) != NULL
)
2132 return &mips_stub_frame_base
;
2138 read_next_frame_reg (struct frame_info
*fi
, int regno
)
2140 /* Always a pseudo. */
2141 gdb_assert (regno
>= NUM_REGS
);
2145 regcache_cooked_read_signed (current_regcache
, regno
, &val
);
2149 return frame_unwind_register_signed (fi
, regno
);
2153 /* mips_addr_bits_remove - remove useless address bits */
2156 mips_addr_bits_remove (CORE_ADDR addr
)
2158 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2159 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
2160 /* This hack is a work-around for existing boards using PMON, the
2161 simulator, and any other 64-bit targets that doesn't have true
2162 64-bit addressing. On these targets, the upper 32 bits of
2163 addresses are ignored by the hardware. Thus, the PC or SP are
2164 likely to have been sign extended to all 1s by instruction
2165 sequences that load 32-bit addresses. For example, a typical
2166 piece of code that loads an address is this:
2168 lui $r2, <upper 16 bits>
2169 ori $r2, <lower 16 bits>
2171 But the lui sign-extends the value such that the upper 32 bits
2172 may be all 1s. The workaround is simply to mask off these
2173 bits. In the future, gcc may be changed to support true 64-bit
2174 addressing, and this masking will have to be disabled. */
2175 return addr
&= 0xffffffffUL
;
2180 /* mips_software_single_step() is called just before we want to resume
2181 the inferior, if we want to single-step it but there is no hardware
2182 or kernel single-step support (MIPS on GNU/Linux for example). We find
2183 the target of the coming instruction and breakpoint it.
2185 single_step is also called just after the inferior stops. If we had
2186 set up a simulated single-step, we undo our damage. */
2189 mips_software_single_step (enum target_signal sig
, int insert_breakpoints_p
)
2191 static CORE_ADDR next_pc
;
2192 typedef char binsn_quantum
[BREAKPOINT_MAX
];
2193 static binsn_quantum break_mem
;
2196 if (insert_breakpoints_p
)
2198 pc
= read_register (mips_regnum (current_gdbarch
)->pc
);
2199 next_pc
= mips_next_pc (pc
);
2201 target_insert_breakpoint (next_pc
, break_mem
);
2204 target_remove_breakpoint (next_pc
, break_mem
);
2207 static struct mips_extra_func_info temp_proc_desc
;
2209 /* Test whether the PC points to the return instruction at the
2210 end of a function. */
2213 mips_about_to_return (CORE_ADDR pc
)
2215 if (mips_pc_is_mips16 (pc
))
2216 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2217 generates a "jr $ra"; other times it generates code to load
2218 the return address from the stack to an accessible register (such
2219 as $a3), then a "jr" using that register. This second case
2220 is almost impossible to distinguish from an indirect jump
2221 used for switch statements, so we don't even try. */
2222 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
2224 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
2228 /* This fencepost looks highly suspicious to me. Removing it also
2229 seems suspicious as it could affect remote debugging across serial
2233 heuristic_proc_start (CORE_ADDR pc
)
2240 pc
= ADDR_BITS_REMOVE (pc
);
2242 fence
= start_pc
- heuristic_fence_post
;
2246 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
2247 fence
= VM_MIN_ADDRESS
;
2249 instlen
= mips_pc_is_mips16 (pc
) ? MIPS16_INSN_SIZE
: MIPS32_INSN_SIZE
;
2251 /* search back for previous return */
2252 for (start_pc
-= instlen
;; start_pc
-= instlen
)
2253 if (start_pc
< fence
)
2255 /* It's not clear to me why we reach this point when
2256 stop_soon, but with this test, at least we
2257 don't print out warnings for every child forked (eg, on
2258 decstation). 22apr93 rich@cygnus.com. */
2259 if (stop_soon
== NO_STOP_QUIETLY
)
2261 static int blurb_printed
= 0;
2263 warning ("GDB can't find the start of the function at 0x%s.",
2268 /* This actually happens frequently in embedded
2269 development, when you first connect to a board
2270 and your stack pointer and pc are nowhere in
2271 particular. This message needs to give people
2272 in that situation enough information to
2273 determine that it's no big deal. */
2274 printf_filtered ("\n\
2275 GDB is unable to find the start of the function at 0x%s\n\
2276 and thus can't determine the size of that function's stack frame.\n\
2277 This means that GDB may be unable to access that stack frame, or\n\
2278 the frames below it.\n\
2279 This problem is most likely caused by an invalid program counter or\n\
2281 However, if you think GDB should simply search farther back\n\
2282 from 0x%s for code which looks like the beginning of a\n\
2283 function, you can increase the range of the search using the `set\n\
2284 heuristic-fence-post' command.\n", paddr_nz (pc
), paddr_nz (pc
));
2291 else if (mips_pc_is_mips16 (start_pc
))
2293 unsigned short inst
;
2295 /* On MIPS16, any one of the following is likely to be the
2296 start of a function:
2300 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
2301 inst
= mips_fetch_instruction (start_pc
);
2302 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
2303 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
2304 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
2305 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
2307 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2308 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2313 else if (mips_about_to_return (start_pc
))
2315 /* Skip return and its delay slot. */
2316 start_pc
+= 2 * MIPS32_INSN_SIZE
;
2323 struct mips_objfile_private
2329 /* MIPS stack frames are almost impenetrable. When execution stops,
2330 we basically have to look at symbol information for the function
2331 that we stopped in, which tells us *which* register (if any) is
2332 the base of the frame pointer, and what offset from that register
2333 the frame itself is at.
2335 This presents a problem when trying to examine a stack in memory
2336 (that isn't executing at the moment), using the "frame" command. We
2337 don't have a PC, nor do we have any registers except SP.
2339 This routine takes two arguments, SP and PC, and tries to make the
2340 cached frames look as if these two arguments defined a frame on the
2341 cache. This allows the rest of info frame to extract the important
2342 arguments without difficulty. */
2345 setup_arbitrary_frame (int argc
, CORE_ADDR
*argv
)
2348 error ("MIPS frame specifications require two arguments: sp and pc");
2350 return create_new_frame (argv
[0], argv
[1]);
2353 /* According to the current ABI, should the type be passed in a
2354 floating-point register (assuming that there is space)? When there
2355 is no FPU, FP are not even considered as possibile candidates for
2356 FP registers and, consequently this returns false - forces FP
2357 arguments into integer registers. */
2360 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
2362 return ((typecode
== TYPE_CODE_FLT
2364 && (typecode
== TYPE_CODE_STRUCT
2365 || typecode
== TYPE_CODE_UNION
)
2366 && TYPE_NFIELDS (arg_type
) == 1
2367 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type
, 0)) == TYPE_CODE_FLT
))
2368 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
2371 /* On o32, argument passing in GPRs depends on the alignment of the type being
2372 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2375 mips_type_needs_double_align (struct type
*type
)
2377 enum type_code typecode
= TYPE_CODE (type
);
2379 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2381 else if (typecode
== TYPE_CODE_STRUCT
)
2383 if (TYPE_NFIELDS (type
) < 1)
2385 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2387 else if (typecode
== TYPE_CODE_UNION
)
2391 n
= TYPE_NFIELDS (type
);
2392 for (i
= 0; i
< n
; i
++)
2393 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2400 /* Adjust the address downward (direction of stack growth) so that it
2401 is correctly aligned for a new stack frame. */
2403 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2405 return align_down (addr
, 16);
2409 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2410 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2411 int nargs
, struct value
**args
, CORE_ADDR sp
,
2412 int struct_return
, CORE_ADDR struct_addr
)
2418 int stack_offset
= 0;
2419 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2420 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
2422 /* For shared libraries, "t9" needs to point at the function
2424 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
2426 /* Set the return address register to point to the entry point of
2427 the program, where a breakpoint lies in wait. */
2428 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
2430 /* First ensure that the stack and structure return address (if any)
2431 are properly aligned. The stack has to be at least 64-bit
2432 aligned even on 32-bit machines, because doubles must be 64-bit
2433 aligned. For n32 and n64, stack frames need to be 128-bit
2434 aligned, so we round to this widest known alignment. */
2436 sp
= align_down (sp
, 16);
2437 struct_addr
= align_down (struct_addr
, 16);
2439 /* Now make space on the stack for the args. We allocate more
2440 than necessary for EABI, because the first few arguments are
2441 passed in registers, but that's OK. */
2442 for (argnum
= 0; argnum
< nargs
; argnum
++)
2443 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
2444 mips_stack_argsize (gdbarch
));
2445 sp
-= align_up (len
, 16);
2448 fprintf_unfiltered (gdb_stdlog
,
2449 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
2450 paddr_nz (sp
), (long) align_up (len
, 16));
2452 /* Initialize the integer and float register pointers. */
2453 argreg
= MIPS_A0_REGNUM
;
2454 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
2456 /* The struct_return pointer occupies the first parameter-passing reg. */
2460 fprintf_unfiltered (gdb_stdlog
,
2461 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
2462 argreg
, paddr_nz (struct_addr
));
2463 write_register (argreg
++, struct_addr
);
2466 /* Now load as many as possible of the first arguments into
2467 registers, and push the rest onto the stack. Loop thru args
2468 from first to last. */
2469 for (argnum
= 0; argnum
< nargs
; argnum
++)
2472 char valbuf
[MAX_REGISTER_SIZE
];
2473 struct value
*arg
= args
[argnum
];
2474 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
2475 int len
= TYPE_LENGTH (arg_type
);
2476 enum type_code typecode
= TYPE_CODE (arg_type
);
2479 fprintf_unfiltered (gdb_stdlog
,
2480 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2481 argnum
+ 1, len
, (int) typecode
);
2483 /* The EABI passes structures that do not fit in a register by
2485 if (len
> mips_abi_regsize (gdbarch
)
2486 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2488 store_unsigned_integer (valbuf
, mips_abi_regsize (gdbarch
),
2489 VALUE_ADDRESS (arg
));
2490 typecode
= TYPE_CODE_PTR
;
2491 len
= mips_abi_regsize (gdbarch
);
2494 fprintf_unfiltered (gdb_stdlog
, " push");
2497 val
= (char *) VALUE_CONTENTS (arg
);
2499 /* 32-bit ABIs always start floating point arguments in an
2500 even-numbered floating point register. Round the FP register
2501 up before the check to see if there are any FP registers
2502 left. Non MIPS_EABI targets also pass the FP in the integer
2503 registers so also round up normal registers. */
2504 if (mips_abi_regsize (gdbarch
) < 8
2505 && fp_register_arg_p (typecode
, arg_type
))
2507 if ((float_argreg
& 1))
2511 /* Floating point arguments passed in registers have to be
2512 treated specially. On 32-bit architectures, doubles
2513 are passed in register pairs; the even register gets
2514 the low word, and the odd register gets the high word.
2515 On non-EABI processors, the first two floating point arguments are
2516 also copied to general registers, because MIPS16 functions
2517 don't use float registers for arguments. This duplication of
2518 arguments in general registers can't hurt non-MIPS16 functions
2519 because those registers are normally skipped. */
2520 /* MIPS_EABI squeezes a struct that contains a single floating
2521 point value into an FP register instead of pushing it onto the
2523 if (fp_register_arg_p (typecode
, arg_type
)
2524 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2526 if (mips_abi_regsize (gdbarch
) < 8 && len
== 8)
2528 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
2529 unsigned long regval
;
2531 /* Write the low word of the double to the even register(s). */
2532 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2534 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2535 float_argreg
, phex (regval
, 4));
2536 write_register (float_argreg
++, regval
);
2538 /* Write the high word of the double to the odd register(s). */
2539 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2541 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2542 float_argreg
, phex (regval
, 4));
2543 write_register (float_argreg
++, regval
);
2547 /* This is a floating point value that fits entirely
2548 in a single register. */
2549 /* On 32 bit ABI's the float_argreg is further adjusted
2550 above to ensure that it is even register aligned. */
2551 LONGEST regval
= extract_unsigned_integer (val
, len
);
2553 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2554 float_argreg
, phex (regval
, len
));
2555 write_register (float_argreg
++, regval
);
2560 /* Copy the argument to general registers or the stack in
2561 register-sized pieces. Large arguments are split between
2562 registers and stack. */
2563 /* Note: structs whose size is not a multiple of
2564 mips_abi_regsize() are treated specially: Irix cc passes
2565 them in registers where gcc sometimes puts them on the
2566 stack. For maximum compatibility, we will put them in
2568 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
2569 && (len
% mips_abi_regsize (gdbarch
) != 0));
2571 /* Note: Floating-point values that didn't fit into an FP
2572 register are only written to memory. */
2575 /* Remember if the argument was written to the stack. */
2576 int stack_used_p
= 0;
2577 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
2578 ? len
: mips_abi_regsize (gdbarch
));
2581 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2584 /* Write this portion of the argument to the stack. */
2585 if (argreg
> MIPS_LAST_ARG_REGNUM
2587 || fp_register_arg_p (typecode
, arg_type
))
2589 /* Should shorter than int integer values be
2590 promoted to int before being stored? */
2591 int longword_offset
= 0;
2594 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2596 if (mips_stack_argsize (gdbarch
) == 8
2597 && (typecode
== TYPE_CODE_INT
2598 || typecode
== TYPE_CODE_PTR
2599 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
2600 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
2601 else if ((typecode
== TYPE_CODE_STRUCT
2602 || typecode
== TYPE_CODE_UNION
)
2603 && (TYPE_LENGTH (arg_type
)
2604 < mips_stack_argsize (gdbarch
)))
2605 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
2610 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
2611 paddr_nz (stack_offset
));
2612 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
2613 paddr_nz (longword_offset
));
2616 addr
= sp
+ stack_offset
+ longword_offset
;
2621 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
2623 for (i
= 0; i
< partial_len
; i
++)
2625 fprintf_unfiltered (gdb_stdlog
, "%02x",
2629 write_memory (addr
, val
, partial_len
);
2632 /* Note!!! This is NOT an else clause. Odd sized
2633 structs may go thru BOTH paths. Floating point
2634 arguments will not. */
2635 /* Write this portion of the argument to a general
2636 purpose register. */
2637 if (argreg
<= MIPS_LAST_ARG_REGNUM
2638 && !fp_register_arg_p (typecode
, arg_type
))
2641 extract_unsigned_integer (val
, partial_len
);
2644 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2647 mips_abi_regsize (gdbarch
)));
2648 write_register (argreg
, regval
);
2655 /* Compute the the offset into the stack at which we
2656 will copy the next parameter.
2658 In the new EABI (and the NABI32), the stack_offset
2659 only needs to be adjusted when it has been used. */
2662 stack_offset
+= align_up (partial_len
,
2663 mips_stack_argsize (gdbarch
));
2667 fprintf_unfiltered (gdb_stdlog
, "\n");
2670 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
2672 /* Return adjusted stack pointer. */
2676 /* Determin the return value convention being used. */
2678 static enum return_value_convention
2679 mips_eabi_return_value (struct gdbarch
*gdbarch
,
2680 struct type
*type
, struct regcache
*regcache
,
2681 void *readbuf
, const void *writebuf
)
2683 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
2684 return RETURN_VALUE_STRUCT_CONVENTION
;
2686 memset (readbuf
, 0, TYPE_LENGTH (type
));
2687 return RETURN_VALUE_REGISTER_CONVENTION
;
2691 /* N32/N64 ABI stuff. */
2694 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2695 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2696 int nargs
, struct value
**args
, CORE_ADDR sp
,
2697 int struct_return
, CORE_ADDR struct_addr
)
2703 int stack_offset
= 0;
2704 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2705 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
2707 /* For shared libraries, "t9" needs to point at the function
2709 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
2711 /* Set the return address register to point to the entry point of
2712 the program, where a breakpoint lies in wait. */
2713 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
2715 /* First ensure that the stack and structure return address (if any)
2716 are properly aligned. The stack has to be at least 64-bit
2717 aligned even on 32-bit machines, because doubles must be 64-bit
2718 aligned. For n32 and n64, stack frames need to be 128-bit
2719 aligned, so we round to this widest known alignment. */
2721 sp
= align_down (sp
, 16);
2722 struct_addr
= align_down (struct_addr
, 16);
2724 /* Now make space on the stack for the args. */
2725 for (argnum
= 0; argnum
< nargs
; argnum
++)
2726 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
2727 mips_stack_argsize (gdbarch
));
2728 sp
-= align_up (len
, 16);
2731 fprintf_unfiltered (gdb_stdlog
,
2732 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
2733 paddr_nz (sp
), (long) align_up (len
, 16));
2735 /* Initialize the integer and float register pointers. */
2736 argreg
= MIPS_A0_REGNUM
;
2737 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
2739 /* The struct_return pointer occupies the first parameter-passing reg. */
2743 fprintf_unfiltered (gdb_stdlog
,
2744 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
2745 argreg
, paddr_nz (struct_addr
));
2746 write_register (argreg
++, struct_addr
);
2749 /* Now load as many as possible of the first arguments into
2750 registers, and push the rest onto the stack. Loop thru args
2751 from first to last. */
2752 for (argnum
= 0; argnum
< nargs
; argnum
++)
2755 struct value
*arg
= args
[argnum
];
2756 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
2757 int len
= TYPE_LENGTH (arg_type
);
2758 enum type_code typecode
= TYPE_CODE (arg_type
);
2761 fprintf_unfiltered (gdb_stdlog
,
2762 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
2763 argnum
+ 1, len
, (int) typecode
);
2765 val
= (char *) VALUE_CONTENTS (arg
);
2767 if (fp_register_arg_p (typecode
, arg_type
)
2768 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2770 /* This is a floating point value that fits entirely
2771 in a single register. */
2772 /* On 32 bit ABI's the float_argreg is further adjusted
2773 above to ensure that it is even register aligned. */
2774 LONGEST regval
= extract_unsigned_integer (val
, len
);
2776 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2777 float_argreg
, phex (regval
, len
));
2778 write_register (float_argreg
++, regval
);
2781 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
2782 argreg
, phex (regval
, len
));
2783 write_register (argreg
, regval
);
2788 /* Copy the argument to general registers or the stack in
2789 register-sized pieces. Large arguments are split between
2790 registers and stack. */
2791 /* Note: structs whose size is not a multiple of
2792 mips_abi_regsize() are treated specially: Irix cc passes
2793 them in registers where gcc sometimes puts them on the
2794 stack. For maximum compatibility, we will put them in
2796 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
2797 && (len
% mips_abi_regsize (gdbarch
) != 0));
2798 /* Note: Floating-point values that didn't fit into an FP
2799 register are only written to memory. */
2802 /* Rememer if the argument was written to the stack. */
2803 int stack_used_p
= 0;
2804 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
2805 ? len
: mips_abi_regsize (gdbarch
));
2808 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2811 /* Write this portion of the argument to the stack. */
2812 if (argreg
> MIPS_LAST_ARG_REGNUM
2814 || fp_register_arg_p (typecode
, arg_type
))
2816 /* Should shorter than int integer values be
2817 promoted to int before being stored? */
2818 int longword_offset
= 0;
2821 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2823 if (mips_stack_argsize (gdbarch
) == 8
2824 && (typecode
== TYPE_CODE_INT
2825 || typecode
== TYPE_CODE_PTR
2826 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
2827 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
2832 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
2833 paddr_nz (stack_offset
));
2834 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
2835 paddr_nz (longword_offset
));
2838 addr
= sp
+ stack_offset
+ longword_offset
;
2843 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
2845 for (i
= 0; i
< partial_len
; i
++)
2847 fprintf_unfiltered (gdb_stdlog
, "%02x",
2851 write_memory (addr
, val
, partial_len
);
2854 /* Note!!! This is NOT an else clause. Odd sized
2855 structs may go thru BOTH paths. Floating point
2856 arguments will not. */
2857 /* Write this portion of the argument to a general
2858 purpose register. */
2859 if (argreg
<= MIPS_LAST_ARG_REGNUM
2860 && !fp_register_arg_p (typecode
, arg_type
))
2863 extract_unsigned_integer (val
, partial_len
);
2865 /* A non-floating-point argument being passed in a
2866 general register. If a struct or union, and if
2867 the remaining length is smaller than the register
2868 size, we have to adjust the register value on
2871 It does not seem to be necessary to do the
2872 same for integral types.
2874 cagney/2001-07-23: gdb/179: Also, GCC, when
2875 outputting LE O32 with sizeof (struct) <
2876 mips_abi_regsize(), generates a left shift as
2877 part of storing the argument in a register a
2878 register (the left shift isn't generated when
2879 sizeof (struct) >= mips_abi_regsize()). Since
2880 it is quite possible that this is GCC
2881 contradicting the LE/O32 ABI, GDB has not been
2882 adjusted to accommodate this. Either someone
2883 needs to demonstrate that the LE/O32 ABI
2884 specifies such a left shift OR this new ABI gets
2885 identified as such and GDB gets tweaked
2888 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
2889 && partial_len
< mips_abi_regsize (gdbarch
)
2890 && (typecode
== TYPE_CODE_STRUCT
||
2891 typecode
== TYPE_CODE_UNION
))
2892 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
2896 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2899 mips_abi_regsize (gdbarch
)));
2900 write_register (argreg
, regval
);
2907 /* Compute the the offset into the stack at which we
2908 will copy the next parameter.
2910 In N32 (N64?), the stack_offset only needs to be
2911 adjusted when it has been used. */
2914 stack_offset
+= align_up (partial_len
,
2915 mips_stack_argsize (gdbarch
));
2919 fprintf_unfiltered (gdb_stdlog
, "\n");
2922 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
2924 /* Return adjusted stack pointer. */
2928 static enum return_value_convention
2929 mips_n32n64_return_value (struct gdbarch
*gdbarch
,
2930 struct type
*type
, struct regcache
*regcache
,
2931 void *readbuf
, const void *writebuf
)
2933 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2934 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
2935 || TYPE_CODE (type
) == TYPE_CODE_UNION
2936 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
2937 || TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
2938 return RETURN_VALUE_STRUCT_CONVENTION
;
2939 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
2940 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
2942 /* A floating-point value belongs in the least significant part
2945 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
2946 mips_xfer_register (regcache
,
2947 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
2949 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
2950 return RETURN_VALUE_REGISTER_CONVENTION
;
2952 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
2953 && TYPE_NFIELDS (type
) <= 2
2954 && TYPE_NFIELDS (type
) >= 1
2955 && ((TYPE_NFIELDS (type
) == 1
2956 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
2958 || (TYPE_NFIELDS (type
) == 2
2959 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
2961 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
2963 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
2965 /* A struct that contains one or two floats. Each value is part
2966 in the least significant part of their floating point
2970 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
2971 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
2973 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
2976 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
2978 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
2979 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
2980 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
2982 return RETURN_VALUE_REGISTER_CONVENTION
;
2984 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
2985 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
2987 /* A structure or union. Extract the left justified value,
2988 regardless of the byte order. I.e. DO NOT USE
2992 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
2993 offset
< TYPE_LENGTH (type
);
2994 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
2996 int xfer
= register_size (current_gdbarch
, regnum
);
2997 if (offset
+ xfer
> TYPE_LENGTH (type
))
2998 xfer
= TYPE_LENGTH (type
) - offset
;
3000 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3001 offset
, xfer
, regnum
);
3002 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3003 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
3005 return RETURN_VALUE_REGISTER_CONVENTION
;
3009 /* A scalar extract each part but least-significant-byte
3013 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3014 offset
< TYPE_LENGTH (type
);
3015 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3017 int xfer
= register_size (current_gdbarch
, regnum
);
3018 if (offset
+ xfer
> TYPE_LENGTH (type
))
3019 xfer
= TYPE_LENGTH (type
) - offset
;
3021 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3022 offset
, xfer
, regnum
);
3023 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3024 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3026 return RETURN_VALUE_REGISTER_CONVENTION
;
3030 /* O32 ABI stuff. */
3033 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3034 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3035 int nargs
, struct value
**args
, CORE_ADDR sp
,
3036 int struct_return
, CORE_ADDR struct_addr
)
3042 int stack_offset
= 0;
3043 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3044 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3046 /* For shared libraries, "t9" needs to point at the function
3048 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3050 /* Set the return address register to point to the entry point of
3051 the program, where a breakpoint lies in wait. */
3052 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3054 /* First ensure that the stack and structure return address (if any)
3055 are properly aligned. The stack has to be at least 64-bit
3056 aligned even on 32-bit machines, because doubles must be 64-bit
3057 aligned. For n32 and n64, stack frames need to be 128-bit
3058 aligned, so we round to this widest known alignment. */
3060 sp
= align_down (sp
, 16);
3061 struct_addr
= align_down (struct_addr
, 16);
3063 /* Now make space on the stack for the args. */
3064 for (argnum
= 0; argnum
< nargs
; argnum
++)
3065 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3066 mips_stack_argsize (gdbarch
));
3067 sp
-= align_up (len
, 16);
3070 fprintf_unfiltered (gdb_stdlog
,
3071 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
3072 paddr_nz (sp
), (long) align_up (len
, 16));
3074 /* Initialize the integer and float register pointers. */
3075 argreg
= MIPS_A0_REGNUM
;
3076 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3078 /* The struct_return pointer occupies the first parameter-passing reg. */
3082 fprintf_unfiltered (gdb_stdlog
,
3083 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
3084 argreg
, paddr_nz (struct_addr
));
3085 write_register (argreg
++, struct_addr
);
3086 stack_offset
+= mips_stack_argsize (gdbarch
);
3089 /* Now load as many as possible of the first arguments into
3090 registers, and push the rest onto the stack. Loop thru args
3091 from first to last. */
3092 for (argnum
= 0; argnum
< nargs
; argnum
++)
3095 struct value
*arg
= args
[argnum
];
3096 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3097 int len
= TYPE_LENGTH (arg_type
);
3098 enum type_code typecode
= TYPE_CODE (arg_type
);
3101 fprintf_unfiltered (gdb_stdlog
,
3102 "mips_o32_push_dummy_call: %d len=%d type=%d",
3103 argnum
+ 1, len
, (int) typecode
);
3105 val
= (char *) VALUE_CONTENTS (arg
);
3107 /* 32-bit ABIs always start floating point arguments in an
3108 even-numbered floating point register. Round the FP register
3109 up before the check to see if there are any FP registers
3110 left. O32/O64 targets also pass the FP in the integer
3111 registers so also round up normal registers. */
3112 if (mips_abi_regsize (gdbarch
) < 8
3113 && fp_register_arg_p (typecode
, arg_type
))
3115 if ((float_argreg
& 1))
3119 /* Floating point arguments passed in registers have to be
3120 treated specially. On 32-bit architectures, doubles
3121 are passed in register pairs; the even register gets
3122 the low word, and the odd register gets the high word.
3123 On O32/O64, the first two floating point arguments are
3124 also copied to general registers, because MIPS16 functions
3125 don't use float registers for arguments. This duplication of
3126 arguments in general registers can't hurt non-MIPS16 functions
3127 because those registers are normally skipped. */
3129 if (fp_register_arg_p (typecode
, arg_type
)
3130 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3132 if (mips_abi_regsize (gdbarch
) < 8 && len
== 8)
3134 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3135 unsigned long regval
;
3137 /* Write the low word of the double to the even register(s). */
3138 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3140 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3141 float_argreg
, phex (regval
, 4));
3142 write_register (float_argreg
++, regval
);
3144 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3145 argreg
, phex (regval
, 4));
3146 write_register (argreg
++, regval
);
3148 /* Write the high word of the double to the odd register(s). */
3149 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3151 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3152 float_argreg
, phex (regval
, 4));
3153 write_register (float_argreg
++, regval
);
3156 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3157 argreg
, phex (regval
, 4));
3158 write_register (argreg
++, regval
);
3162 /* This is a floating point value that fits entirely
3163 in a single register. */
3164 /* On 32 bit ABI's the float_argreg is further adjusted
3165 above to ensure that it is even register aligned. */
3166 LONGEST regval
= extract_unsigned_integer (val
, len
);
3168 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3169 float_argreg
, phex (regval
, len
));
3170 write_register (float_argreg
++, regval
);
3171 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3172 registers for each argument. The below is (my
3173 guess) to ensure that the corresponding integer
3174 register has reserved the same space. */
3176 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3177 argreg
, phex (regval
, len
));
3178 write_register (argreg
, regval
);
3179 argreg
+= (mips_abi_regsize (gdbarch
) == 8) ? 1 : 2;
3181 /* Reserve space for the FP register. */
3182 stack_offset
+= align_up (len
, mips_stack_argsize (gdbarch
));
3186 /* Copy the argument to general registers or the stack in
3187 register-sized pieces. Large arguments are split between
3188 registers and stack. */
3189 /* Note: structs whose size is not a multiple of
3190 mips_abi_regsize() are treated specially: Irix cc passes
3191 them in registers where gcc sometimes puts them on the
3192 stack. For maximum compatibility, we will put them in
3194 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
3195 && (len
% mips_abi_regsize (gdbarch
) != 0));
3196 /* Structures should be aligned to eight bytes (even arg registers)
3197 on MIPS_ABI_O32, if their first member has double precision. */
3198 if (mips_abi_regsize (gdbarch
) < 8
3199 && mips_type_needs_double_align (arg_type
))
3204 /* Note: Floating-point values that didn't fit into an FP
3205 register are only written to memory. */
3208 /* Remember if the argument was written to the stack. */
3209 int stack_used_p
= 0;
3210 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
3211 ? len
: mips_abi_regsize (gdbarch
));
3214 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3217 /* Write this portion of the argument to the stack. */
3218 if (argreg
> MIPS_LAST_ARG_REGNUM
3220 || fp_register_arg_p (typecode
, arg_type
))
3222 /* Should shorter than int integer values be
3223 promoted to int before being stored? */
3224 int longword_offset
= 0;
3227 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3229 if (mips_stack_argsize (gdbarch
) == 8
3230 && (typecode
== TYPE_CODE_INT
3231 || typecode
== TYPE_CODE_PTR
3232 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3233 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3238 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3239 paddr_nz (stack_offset
));
3240 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3241 paddr_nz (longword_offset
));
3244 addr
= sp
+ stack_offset
+ longword_offset
;
3249 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3251 for (i
= 0; i
< partial_len
; i
++)
3253 fprintf_unfiltered (gdb_stdlog
, "%02x",
3257 write_memory (addr
, val
, partial_len
);
3260 /* Note!!! This is NOT an else clause. Odd sized
3261 structs may go thru BOTH paths. Floating point
3262 arguments will not. */
3263 /* Write this portion of the argument to a general
3264 purpose register. */
3265 if (argreg
<= MIPS_LAST_ARG_REGNUM
3266 && !fp_register_arg_p (typecode
, arg_type
))
3268 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3269 /* Value may need to be sign extended, because
3270 mips_isa_regsize() != mips_abi_regsize(). */
3272 /* A non-floating-point argument being passed in a
3273 general register. If a struct or union, and if
3274 the remaining length is smaller than the register
3275 size, we have to adjust the register value on
3278 It does not seem to be necessary to do the
3279 same for integral types.
3281 Also don't do this adjustment on O64 binaries.
3283 cagney/2001-07-23: gdb/179: Also, GCC, when
3284 outputting LE O32 with sizeof (struct) <
3285 mips_abi_regsize(), generates a left shift as
3286 part of storing the argument in a register a
3287 register (the left shift isn't generated when
3288 sizeof (struct) >= mips_abi_regsize()). Since
3289 it is quite possible that this is GCC
3290 contradicting the LE/O32 ABI, GDB has not been
3291 adjusted to accommodate this. Either someone
3292 needs to demonstrate that the LE/O32 ABI
3293 specifies such a left shift OR this new ABI gets
3294 identified as such and GDB gets tweaked
3297 if (mips_abi_regsize (gdbarch
) < 8
3298 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3299 && partial_len
< mips_abi_regsize (gdbarch
)
3300 && (typecode
== TYPE_CODE_STRUCT
||
3301 typecode
== TYPE_CODE_UNION
))
3302 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
3306 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3309 mips_abi_regsize (gdbarch
)));
3310 write_register (argreg
, regval
);
3313 /* Prevent subsequent floating point arguments from
3314 being passed in floating point registers. */
3315 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3321 /* Compute the the offset into the stack at which we
3322 will copy the next parameter.
3324 In older ABIs, the caller reserved space for
3325 registers that contained arguments. This was loosely
3326 refered to as their "home". Consequently, space is
3327 always allocated. */
3329 stack_offset
+= align_up (partial_len
,
3330 mips_stack_argsize (gdbarch
));
3334 fprintf_unfiltered (gdb_stdlog
, "\n");
3337 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3339 /* Return adjusted stack pointer. */
3343 static enum return_value_convention
3344 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
3345 struct regcache
*regcache
,
3346 void *readbuf
, const void *writebuf
)
3348 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3350 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3351 || TYPE_CODE (type
) == TYPE_CODE_UNION
3352 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3353 return RETURN_VALUE_STRUCT_CONVENTION
;
3354 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3355 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3357 /* A single-precision floating-point value. It fits in the
3358 least significant part of FP0. */
3360 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3361 mips_xfer_register (regcache
,
3362 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
3364 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3365 return RETURN_VALUE_REGISTER_CONVENTION
;
3367 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3368 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3370 /* A double-precision floating-point value. The most
3371 significant part goes in FP1, and the least significant in
3374 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
3375 switch (TARGET_BYTE_ORDER
)
3377 case BFD_ENDIAN_LITTLE
:
3378 mips_xfer_register (regcache
,
3379 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3380 0, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3381 mips_xfer_register (regcache
,
3382 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3383 1, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
3385 case BFD_ENDIAN_BIG
:
3386 mips_xfer_register (regcache
,
3387 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3388 1, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3389 mips_xfer_register (regcache
,
3390 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3391 0, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
3394 internal_error (__FILE__
, __LINE__
, "bad switch");
3396 return RETURN_VALUE_REGISTER_CONVENTION
;
3399 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3400 && TYPE_NFIELDS (type
) <= 2
3401 && TYPE_NFIELDS (type
) >= 1
3402 && ((TYPE_NFIELDS (type
) == 1
3403 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3405 || (TYPE_NFIELDS (type
) == 2
3406 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3408 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
3410 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3412 /* A struct that contains one or two floats. Each value is part
3413 in the least significant part of their floating point
3415 bfd_byte reg
[MAX_REGISTER_SIZE
];
3418 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
3419 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3421 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3424 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3426 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
3427 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3428 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3430 return RETURN_VALUE_REGISTER_CONVENTION
;
3434 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3435 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3437 /* A structure or union. Extract the left justified value,
3438 regardless of the byte order. I.e. DO NOT USE
3442 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3443 offset
< TYPE_LENGTH (type
);
3444 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3446 int xfer
= register_size (current_gdbarch
, regnum
);
3447 if (offset
+ xfer
> TYPE_LENGTH (type
))
3448 xfer
= TYPE_LENGTH (type
) - offset
;
3450 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3451 offset
, xfer
, regnum
);
3452 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3453 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
3455 return RETURN_VALUE_REGISTER_CONVENTION
;
3460 /* A scalar extract each part but least-significant-byte
3461 justified. o32 thinks registers are 4 byte, regardless of
3462 the ISA. mips_stack_argsize controls this. */
3465 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3466 offset
< TYPE_LENGTH (type
);
3467 offset
+= mips_stack_argsize (gdbarch
), regnum
++)
3469 int xfer
= mips_stack_argsize (gdbarch
);
3470 if (offset
+ xfer
> TYPE_LENGTH (type
))
3471 xfer
= TYPE_LENGTH (type
) - offset
;
3473 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3474 offset
, xfer
, regnum
);
3475 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3476 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3478 return RETURN_VALUE_REGISTER_CONVENTION
;
3482 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
3486 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3487 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3489 struct value
**args
, CORE_ADDR sp
,
3490 int struct_return
, CORE_ADDR struct_addr
)
3496 int stack_offset
= 0;
3497 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3498 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3500 /* For shared libraries, "t9" needs to point at the function
3502 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3504 /* Set the return address register to point to the entry point of
3505 the program, where a breakpoint lies in wait. */
3506 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3508 /* First ensure that the stack and structure return address (if any)
3509 are properly aligned. The stack has to be at least 64-bit
3510 aligned even on 32-bit machines, because doubles must be 64-bit
3511 aligned. For n32 and n64, stack frames need to be 128-bit
3512 aligned, so we round to this widest known alignment. */
3514 sp
= align_down (sp
, 16);
3515 struct_addr
= align_down (struct_addr
, 16);
3517 /* Now make space on the stack for the args. */
3518 for (argnum
= 0; argnum
< nargs
; argnum
++)
3519 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3520 mips_stack_argsize (gdbarch
));
3521 sp
-= align_up (len
, 16);
3524 fprintf_unfiltered (gdb_stdlog
,
3525 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
3526 paddr_nz (sp
), (long) align_up (len
, 16));
3528 /* Initialize the integer and float register pointers. */
3529 argreg
= MIPS_A0_REGNUM
;
3530 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3532 /* The struct_return pointer occupies the first parameter-passing reg. */
3536 fprintf_unfiltered (gdb_stdlog
,
3537 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
3538 argreg
, paddr_nz (struct_addr
));
3539 write_register (argreg
++, struct_addr
);
3540 stack_offset
+= mips_stack_argsize (gdbarch
);
3543 /* Now load as many as possible of the first arguments into
3544 registers, and push the rest onto the stack. Loop thru args
3545 from first to last. */
3546 for (argnum
= 0; argnum
< nargs
; argnum
++)
3549 struct value
*arg
= args
[argnum
];
3550 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3551 int len
= TYPE_LENGTH (arg_type
);
3552 enum type_code typecode
= TYPE_CODE (arg_type
);
3555 fprintf_unfiltered (gdb_stdlog
,
3556 "mips_o64_push_dummy_call: %d len=%d type=%d",
3557 argnum
+ 1, len
, (int) typecode
);
3559 val
= (char *) VALUE_CONTENTS (arg
);
3561 /* 32-bit ABIs always start floating point arguments in an
3562 even-numbered floating point register. Round the FP register
3563 up before the check to see if there are any FP registers
3564 left. O32/O64 targets also pass the FP in the integer
3565 registers so also round up normal registers. */
3566 if (mips_abi_regsize (gdbarch
) < 8
3567 && fp_register_arg_p (typecode
, arg_type
))
3569 if ((float_argreg
& 1))
3573 /* Floating point arguments passed in registers have to be
3574 treated specially. On 32-bit architectures, doubles
3575 are passed in register pairs; the even register gets
3576 the low word, and the odd register gets the high word.
3577 On O32/O64, the first two floating point arguments are
3578 also copied to general registers, because MIPS16 functions
3579 don't use float registers for arguments. This duplication of
3580 arguments in general registers can't hurt non-MIPS16 functions
3581 because those registers are normally skipped. */
3583 if (fp_register_arg_p (typecode
, arg_type
)
3584 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3586 if (mips_abi_regsize (gdbarch
) < 8 && len
== 8)
3588 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3589 unsigned long regval
;
3591 /* Write the low word of the double to the even register(s). */
3592 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3594 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3595 float_argreg
, phex (regval
, 4));
3596 write_register (float_argreg
++, regval
);
3598 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3599 argreg
, phex (regval
, 4));
3600 write_register (argreg
++, regval
);
3602 /* Write the high word of the double to the odd register(s). */
3603 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3605 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3606 float_argreg
, phex (regval
, 4));
3607 write_register (float_argreg
++, regval
);
3610 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3611 argreg
, phex (regval
, 4));
3612 write_register (argreg
++, regval
);
3616 /* This is a floating point value that fits entirely
3617 in a single register. */
3618 /* On 32 bit ABI's the float_argreg is further adjusted
3619 above to ensure that it is even register aligned. */
3620 LONGEST regval
= extract_unsigned_integer (val
, len
);
3622 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3623 float_argreg
, phex (regval
, len
));
3624 write_register (float_argreg
++, regval
);
3625 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3626 registers for each argument. The below is (my
3627 guess) to ensure that the corresponding integer
3628 register has reserved the same space. */
3630 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3631 argreg
, phex (regval
, len
));
3632 write_register (argreg
, regval
);
3633 argreg
+= (mips_abi_regsize (gdbarch
) == 8) ? 1 : 2;
3635 /* Reserve space for the FP register. */
3636 stack_offset
+= align_up (len
, mips_stack_argsize (gdbarch
));
3640 /* Copy the argument to general registers or the stack in
3641 register-sized pieces. Large arguments are split between
3642 registers and stack. */
3643 /* Note: structs whose size is not a multiple of
3644 mips_abi_regsize() are treated specially: Irix cc passes
3645 them in registers where gcc sometimes puts them on the
3646 stack. For maximum compatibility, we will put them in
3648 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
3649 && (len
% mips_abi_regsize (gdbarch
) != 0));
3650 /* Structures should be aligned to eight bytes (even arg registers)
3651 on MIPS_ABI_O32, if their first member has double precision. */
3652 if (mips_abi_regsize (gdbarch
) < 8
3653 && mips_type_needs_double_align (arg_type
))
3658 /* Note: Floating-point values that didn't fit into an FP
3659 register are only written to memory. */
3662 /* Remember if the argument was written to the stack. */
3663 int stack_used_p
= 0;
3664 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
3665 ? len
: mips_abi_regsize (gdbarch
));
3668 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3671 /* Write this portion of the argument to the stack. */
3672 if (argreg
> MIPS_LAST_ARG_REGNUM
3674 || fp_register_arg_p (typecode
, arg_type
))
3676 /* Should shorter than int integer values be
3677 promoted to int before being stored? */
3678 int longword_offset
= 0;
3681 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3683 if (mips_stack_argsize (gdbarch
) == 8
3684 && (typecode
== TYPE_CODE_INT
3685 || typecode
== TYPE_CODE_PTR
3686 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3687 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3692 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3693 paddr_nz (stack_offset
));
3694 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3695 paddr_nz (longword_offset
));
3698 addr
= sp
+ stack_offset
+ longword_offset
;
3703 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3705 for (i
= 0; i
< partial_len
; i
++)
3707 fprintf_unfiltered (gdb_stdlog
, "%02x",
3711 write_memory (addr
, val
, partial_len
);
3714 /* Note!!! This is NOT an else clause. Odd sized
3715 structs may go thru BOTH paths. Floating point
3716 arguments will not. */
3717 /* Write this portion of the argument to a general
3718 purpose register. */
3719 if (argreg
<= MIPS_LAST_ARG_REGNUM
3720 && !fp_register_arg_p (typecode
, arg_type
))
3722 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3723 /* Value may need to be sign extended, because
3724 mips_isa_regsize() != mips_abi_regsize(). */
3726 /* A non-floating-point argument being passed in a
3727 general register. If a struct or union, and if
3728 the remaining length is smaller than the register
3729 size, we have to adjust the register value on
3732 It does not seem to be necessary to do the
3733 same for integral types.
3735 Also don't do this adjustment on O64 binaries.
3737 cagney/2001-07-23: gdb/179: Also, GCC, when
3738 outputting LE O32 with sizeof (struct) <
3739 mips_abi_regsize(), generates a left shift as
3740 part of storing the argument in a register a
3741 register (the left shift isn't generated when
3742 sizeof (struct) >= mips_abi_regsize()). Since
3743 it is quite possible that this is GCC
3744 contradicting the LE/O32 ABI, GDB has not been
3745 adjusted to accommodate this. Either someone
3746 needs to demonstrate that the LE/O32 ABI
3747 specifies such a left shift OR this new ABI gets
3748 identified as such and GDB gets tweaked
3751 if (mips_abi_regsize (gdbarch
) < 8
3752 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3753 && partial_len
< mips_abi_regsize (gdbarch
)
3754 && (typecode
== TYPE_CODE_STRUCT
||
3755 typecode
== TYPE_CODE_UNION
))
3756 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
3760 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3763 mips_abi_regsize (gdbarch
)));
3764 write_register (argreg
, regval
);
3767 /* Prevent subsequent floating point arguments from
3768 being passed in floating point registers. */
3769 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3775 /* Compute the the offset into the stack at which we
3776 will copy the next parameter.
3778 In older ABIs, the caller reserved space for
3779 registers that contained arguments. This was loosely
3780 refered to as their "home". Consequently, space is
3781 always allocated. */
3783 stack_offset
+= align_up (partial_len
,
3784 mips_stack_argsize (gdbarch
));
3788 fprintf_unfiltered (gdb_stdlog
, "\n");
3791 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3793 /* Return adjusted stack pointer. */
3797 static enum return_value_convention
3798 mips_o64_return_value (struct gdbarch
*gdbarch
,
3799 struct type
*type
, struct regcache
*regcache
,
3800 void *readbuf
, const void *writebuf
)
3802 return RETURN_VALUE_STRUCT_CONVENTION
;
3805 /* Floating point register management.
3807 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
3808 64bit operations, these early MIPS cpus treat fp register pairs
3809 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
3810 registers and offer a compatibility mode that emulates the MIPS2 fp
3811 model. When operating in MIPS2 fp compat mode, later cpu's split
3812 double precision floats into two 32-bit chunks and store them in
3813 consecutive fp regs. To display 64-bit floats stored in this
3814 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
3815 Throw in user-configurable endianness and you have a real mess.
3817 The way this works is:
3818 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
3819 double-precision value will be split across two logical registers.
3820 The lower-numbered logical register will hold the low-order bits,
3821 regardless of the processor's endianness.
3822 - If we are on a 64-bit processor, and we are looking for a
3823 single-precision value, it will be in the low ordered bits
3824 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
3825 save slot in memory.
3826 - If we are in 64-bit mode, everything is straightforward.
3828 Note that this code only deals with "live" registers at the top of the
3829 stack. We will attempt to deal with saved registers later, when
3830 the raw/cooked register interface is in place. (We need a general
3831 interface that can deal with dynamic saved register sizes -- fp
3832 regs could be 32 bits wide in one frame and 64 on the frame above
3835 static struct type
*
3836 mips_float_register_type (void)
3838 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3839 return builtin_type_ieee_single_big
;
3841 return builtin_type_ieee_single_little
;
3844 static struct type
*
3845 mips_double_register_type (void)
3847 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3848 return builtin_type_ieee_double_big
;
3850 return builtin_type_ieee_double_little
;
3853 /* Copy a 32-bit single-precision value from the current frame
3854 into rare_buffer. */
3857 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
3860 int raw_size
= register_size (current_gdbarch
, regno
);
3861 char *raw_buffer
= alloca (raw_size
);
3863 if (!frame_register_read (frame
, regno
, raw_buffer
))
3864 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
3867 /* We have a 64-bit value for this register. Find the low-order
3871 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3876 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
3880 memcpy (rare_buffer
, raw_buffer
, 4);
3884 /* Copy a 64-bit double-precision value from the current frame into
3885 rare_buffer. This may include getting half of it from the next
3889 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
3892 int raw_size
= register_size (current_gdbarch
, regno
);
3894 if (raw_size
== 8 && !mips2_fp_compat ())
3896 /* We have a 64-bit value for this register, and we should use
3898 if (!frame_register_read (frame
, regno
, rare_buffer
))
3899 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
3903 if ((regno
- mips_regnum (current_gdbarch
)->fp0
) & 1)
3904 internal_error (__FILE__
, __LINE__
,
3905 "mips_read_fp_register_double: bad access to "
3906 "odd-numbered FP register");
3908 /* mips_read_fp_register_single will find the correct 32 bits from
3910 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3912 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
3913 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
3917 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
3918 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
3924 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
3926 { /* do values for FP (float) regs */
3928 double doub
, flt1
; /* doubles extracted from raw hex data */
3932 (char *) alloca (2 *
3933 register_size (current_gdbarch
,
3934 mips_regnum (current_gdbarch
)->fp0
));
3936 fprintf_filtered (file
, "%s:", REGISTER_NAME (regnum
));
3937 fprintf_filtered (file
, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum
)),
3940 if (register_size (current_gdbarch
, regnum
) == 4 || mips2_fp_compat ())
3942 /* 4-byte registers: Print hex and floating. Also print even
3943 numbered registers as doubles. */
3944 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
3945 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
3947 print_scalar_formatted (raw_buffer
, builtin_type_uint32
, 'x', 'w',
3950 fprintf_filtered (file
, " flt: ");
3952 fprintf_filtered (file
, " <invalid float> ");
3954 fprintf_filtered (file
, "%-17.9g", flt1
);
3956 if (regnum
% 2 == 0)
3958 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
3959 doub
= unpack_double (mips_double_register_type (), raw_buffer
,
3962 fprintf_filtered (file
, " dbl: ");
3964 fprintf_filtered (file
, "<invalid double>");
3966 fprintf_filtered (file
, "%-24.17g", doub
);
3971 /* Eight byte registers: print each one as hex, float and double. */
3972 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
3973 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
3975 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
3976 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv2
);
3979 print_scalar_formatted (raw_buffer
, builtin_type_uint64
, 'x', 'g',
3982 fprintf_filtered (file
, " flt: ");
3984 fprintf_filtered (file
, "<invalid float>");
3986 fprintf_filtered (file
, "%-17.9g", flt1
);
3988 fprintf_filtered (file
, " dbl: ");
3990 fprintf_filtered (file
, "<invalid double>");
3992 fprintf_filtered (file
, "%-24.17g", doub
);
3997 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
3998 int regnum
, int all
)
4000 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4001 char raw_buffer
[MAX_REGISTER_SIZE
];
4004 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4006 mips_print_fp_register (file
, frame
, regnum
);
4010 /* Get the data in raw format. */
4011 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4013 fprintf_filtered (file
, "%s: [Invalid]", REGISTER_NAME (regnum
));
4017 fputs_filtered (REGISTER_NAME (regnum
), file
);
4019 /* The problem with printing numeric register names (r26, etc.) is that
4020 the user can't use them on input. Probably the best solution is to
4021 fix it so that either the numeric or the funky (a2, etc.) names
4022 are accepted on input. */
4023 if (regnum
< MIPS_NUMREGS
)
4024 fprintf_filtered (file
, "(r%d): ", regnum
);
4026 fprintf_filtered (file
, ": ");
4028 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4030 register_size (current_gdbarch
,
4031 regnum
) - register_size (current_gdbarch
, regnum
);
4035 print_scalar_formatted (raw_buffer
+ offset
,
4036 gdbarch_register_type (gdbarch
, regnum
), 'x', 0,
4040 /* Replacement for generic do_registers_info.
4041 Print regs in pretty columns. */
4044 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4047 fprintf_filtered (file
, " ");
4048 mips_print_fp_register (file
, frame
, regnum
);
4049 fprintf_filtered (file
, "\n");
4054 /* Print a row's worth of GP (int) registers, with name labels above */
4057 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4060 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4061 /* do values for GP (int) regs */
4062 char raw_buffer
[MAX_REGISTER_SIZE
];
4063 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols per row */
4067 /* For GP registers, we print a separate row of names above the vals */
4068 fprintf_filtered (file
, " ");
4069 for (col
= 0, regnum
= start_regnum
;
4070 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
4072 if (*REGISTER_NAME (regnum
) == '\0')
4073 continue; /* unused register */
4074 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
4076 break; /* end the row: reached FP register */
4077 fprintf_filtered (file
,
4078 mips_abi_regsize (current_gdbarch
) == 8 ? "%17s" : "%9s",
4079 REGISTER_NAME (regnum
));
4082 /* print the R0 to R31 names */
4083 if ((start_regnum
% NUM_REGS
) < MIPS_NUMREGS
)
4084 fprintf_filtered (file
, "\n R%-4d", start_regnum
% NUM_REGS
);
4086 fprintf_filtered (file
, "\n ");
4088 /* now print the values in hex, 4 or 8 to the row */
4089 for (col
= 0, regnum
= start_regnum
;
4090 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
4092 if (*REGISTER_NAME (regnum
) == '\0')
4093 continue; /* unused register */
4094 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
4096 break; /* end row: reached FP register */
4097 /* OK: get the data in raw format. */
4098 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4099 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
4100 /* pad small registers */
4102 byte
< (mips_abi_regsize (current_gdbarch
)
4103 - register_size (current_gdbarch
, regnum
)); byte
++)
4104 printf_filtered (" ");
4105 /* Now print the register value in hex, endian order. */
4106 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4108 register_size (current_gdbarch
,
4109 regnum
) - register_size (current_gdbarch
, regnum
);
4110 byte
< register_size (current_gdbarch
, regnum
); byte
++)
4111 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
4113 for (byte
= register_size (current_gdbarch
, regnum
) - 1;
4115 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
4116 fprintf_filtered (file
, " ");
4119 if (col
> 0) /* ie. if we actually printed anything... */
4120 fprintf_filtered (file
, "\n");
4125 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4128 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4129 struct frame_info
*frame
, int regnum
, int all
)
4131 if (regnum
!= -1) /* do one specified register */
4133 gdb_assert (regnum
>= NUM_REGS
);
4134 if (*(REGISTER_NAME (regnum
)) == '\0')
4135 error ("Not a valid register for the current processor type");
4137 mips_print_register (file
, frame
, regnum
, 0);
4138 fprintf_filtered (file
, "\n");
4141 /* do all (or most) registers */
4144 while (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
4146 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
4149 if (all
) /* true for "INFO ALL-REGISTERS" command */
4150 regnum
= print_fp_register_row (file
, frame
, regnum
);
4152 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
4155 regnum
= print_gp_register_row (file
, frame
, regnum
);
4160 /* Is this a branch with a delay slot? */
4163 is_delayed (unsigned long insn
)
4166 for (i
= 0; i
< NUMOPCODES
; ++i
)
4167 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4168 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4170 return (i
< NUMOPCODES
4171 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4172 | INSN_COND_BRANCH_DELAY
4173 | INSN_COND_BRANCH_LIKELY
)));
4177 mips_step_skips_delay (CORE_ADDR pc
)
4179 char buf
[MIPS32_INSN_SIZE
];
4181 /* There is no branch delay slot on MIPS16. */
4182 if (mips_pc_is_mips16 (pc
))
4185 if (target_read_memory (pc
, buf
, sizeof buf
) != 0)
4186 /* If error reading memory, guess that it is not a delayed branch. */
4188 return is_delayed (extract_unsigned_integer (buf
, sizeof buf
));
4191 /* To skip prologues, I use this predicate. Returns either PC itself
4192 if the code at PC does not look like a function prologue; otherwise
4193 returns an address that (if we're lucky) follows the prologue. If
4194 LENIENT, then we must skip everything which is involved in setting
4195 up the frame (it's OK to skip more, just so long as we don't skip
4196 anything which might clobber the registers which are being saved.
4197 We must skip more in the case where part of the prologue is in the
4198 delay slot of a non-prologue instruction). */
4201 mips_skip_prologue (CORE_ADDR pc
)
4204 CORE_ADDR func_addr
;
4206 /* See if we can determine the end of the prologue via the symbol table.
4207 If so, then return either PC, or the PC after the prologue, whichever
4209 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
4211 CORE_ADDR post_prologue_pc
= skip_prologue_using_sal (func_addr
);
4212 if (post_prologue_pc
!= 0)
4213 return max (pc
, post_prologue_pc
);
4216 /* Can't determine prologue from the symbol table, need to examine
4219 /* Find an upper limit on the function prologue using the debug
4220 information. If the debug information could not be used to provide
4221 that bound, then use an arbitrary large number as the upper bound. */
4222 limit_pc
= skip_prologue_using_sal (pc
);
4224 limit_pc
= pc
+ 100; /* Magic. */
4226 if (mips_pc_is_mips16 (pc
))
4227 return mips16_scan_prologue (pc
, limit_pc
, NULL
, NULL
);
4229 return mips32_scan_prologue (pc
, limit_pc
, NULL
, NULL
);
4232 /* Root of all "set mips "/"show mips " commands. This will eventually be
4233 used for all MIPS-specific commands. */
4236 show_mips_command (char *args
, int from_tty
)
4238 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
4242 set_mips_command (char *args
, int from_tty
)
4245 ("\"set mips\" must be followed by an appropriate subcommand.\n");
4246 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
4249 /* Commands to show/set the MIPS FPU type. */
4252 show_mipsfpu_command (char *args
, int from_tty
)
4255 switch (MIPS_FPU_TYPE
)
4257 case MIPS_FPU_SINGLE
:
4258 fpu
= "single-precision";
4260 case MIPS_FPU_DOUBLE
:
4261 fpu
= "double-precision";
4264 fpu
= "absent (none)";
4267 internal_error (__FILE__
, __LINE__
, "bad switch");
4269 if (mips_fpu_type_auto
)
4271 ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
4275 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
4280 set_mipsfpu_command (char *args
, int from_tty
)
4283 ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
4284 show_mipsfpu_command (args
, from_tty
);
4288 set_mipsfpu_single_command (char *args
, int from_tty
)
4290 struct gdbarch_info info
;
4291 gdbarch_info_init (&info
);
4292 mips_fpu_type
= MIPS_FPU_SINGLE
;
4293 mips_fpu_type_auto
= 0;
4294 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4295 instead of relying on globals. Doing that would let generic code
4296 handle the search for this specific architecture. */
4297 if (!gdbarch_update_p (info
))
4298 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
4302 set_mipsfpu_double_command (char *args
, int from_tty
)
4304 struct gdbarch_info info
;
4305 gdbarch_info_init (&info
);
4306 mips_fpu_type
= MIPS_FPU_DOUBLE
;
4307 mips_fpu_type_auto
= 0;
4308 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4309 instead of relying on globals. Doing that would let generic code
4310 handle the search for this specific architecture. */
4311 if (!gdbarch_update_p (info
))
4312 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
4316 set_mipsfpu_none_command (char *args
, int from_tty
)
4318 struct gdbarch_info info
;
4319 gdbarch_info_init (&info
);
4320 mips_fpu_type
= MIPS_FPU_NONE
;
4321 mips_fpu_type_auto
= 0;
4322 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4323 instead of relying on globals. Doing that would let generic code
4324 handle the search for this specific architecture. */
4325 if (!gdbarch_update_p (info
))
4326 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
4330 set_mipsfpu_auto_command (char *args
, int from_tty
)
4332 mips_fpu_type_auto
= 1;
4335 /* Attempt to identify the particular processor model by reading the
4336 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
4337 the relevant processor still exists (it dates back to '94) and
4338 secondly this is not the way to do this. The processor type should
4339 be set by forcing an architecture change. */
4342 deprecated_mips_set_processor_regs_hack (void)
4344 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4347 prid
= read_register (PRID_REGNUM
);
4349 if ((prid
& ~0xf) == 0x700)
4350 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
4353 /* Just like reinit_frame_cache, but with the right arguments to be
4354 callable as an sfunc. */
4357 reinit_frame_cache_sfunc (char *args
, int from_tty
,
4358 struct cmd_list_element
*c
)
4360 reinit_frame_cache ();
4364 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
4366 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4368 /* FIXME: cagney/2003-06-26: Is this even necessary? The
4369 disassembler needs to be able to locally determine the ISA, and
4370 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
4372 if (mips_pc_is_mips16 (memaddr
))
4373 info
->mach
= bfd_mach_mips16
;
4375 /* Round down the instruction address to the appropriate boundary. */
4376 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
4378 /* Set the disassembler options. */
4379 if (tdep
->mips_abi
== MIPS_ABI_N32
|| tdep
->mips_abi
== MIPS_ABI_N64
)
4381 /* Set up the disassembler info, so that we get the right
4382 register names from libopcodes. */
4383 if (tdep
->mips_abi
== MIPS_ABI_N32
)
4384 info
->disassembler_options
= "gpr-names=n32";
4386 info
->disassembler_options
= "gpr-names=64";
4387 info
->flavour
= bfd_target_elf_flavour
;
4390 /* This string is not recognized explicitly by the disassembler,
4391 but it tells the disassembler to not try to guess the ABI from
4392 the bfd elf headers, such that, if the user overrides the ABI
4393 of a program linked as NewABI, the disassembly will follow the
4394 register naming conventions specified by the user. */
4395 info
->disassembler_options
= "gpr-names=32";
4397 /* Call the appropriate disassembler based on the target endian-ness. */
4398 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4399 return print_insn_big_mips (memaddr
, info
);
4401 return print_insn_little_mips (memaddr
, info
);
4404 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
4405 counter value to determine whether a 16- or 32-bit breakpoint should be
4406 used. It returns a pointer to a string of bytes that encode a breakpoint
4407 instruction, stores the length of the string to *lenptr, and adjusts pc
4408 (if necessary) to point to the actual memory location where the
4409 breakpoint should be inserted. */
4411 static const unsigned char *
4412 mips_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
4414 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4416 if (mips_pc_is_mips16 (*pcptr
))
4418 static unsigned char mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
4419 *pcptr
= unmake_mips16_addr (*pcptr
);
4420 *lenptr
= sizeof (mips16_big_breakpoint
);
4421 return mips16_big_breakpoint
;
4425 /* The IDT board uses an unusual breakpoint value, and
4426 sometimes gets confused when it sees the usual MIPS
4427 breakpoint instruction. */
4428 static unsigned char big_breakpoint
[] = { 0, 0x5, 0, 0xd };
4429 static unsigned char pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
4430 static unsigned char idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
4432 *lenptr
= sizeof (big_breakpoint
);
4434 if (strcmp (target_shortname
, "mips") == 0)
4435 return idt_big_breakpoint
;
4436 else if (strcmp (target_shortname
, "ddb") == 0
4437 || strcmp (target_shortname
, "pmon") == 0
4438 || strcmp (target_shortname
, "lsi") == 0)
4439 return pmon_big_breakpoint
;
4441 return big_breakpoint
;
4446 if (mips_pc_is_mips16 (*pcptr
))
4448 static unsigned char mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
4449 *pcptr
= unmake_mips16_addr (*pcptr
);
4450 *lenptr
= sizeof (mips16_little_breakpoint
);
4451 return mips16_little_breakpoint
;
4455 static unsigned char little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
4456 static unsigned char pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
4457 static unsigned char idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
4459 *lenptr
= sizeof (little_breakpoint
);
4461 if (strcmp (target_shortname
, "mips") == 0)
4462 return idt_little_breakpoint
;
4463 else if (strcmp (target_shortname
, "ddb") == 0
4464 || strcmp (target_shortname
, "pmon") == 0
4465 || strcmp (target_shortname
, "lsi") == 0)
4466 return pmon_little_breakpoint
;
4468 return little_breakpoint
;
4473 /* If PC is in a mips16 call or return stub, return the address of the target
4474 PC, which is either the callee or the caller. There are several
4475 cases which must be handled:
4477 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
4478 target PC is in $31 ($ra).
4479 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
4480 and the target PC is in $2.
4481 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4482 before the jal instruction, this is effectively a call stub
4483 and the the target PC is in $2. Otherwise this is effectively
4484 a return stub and the target PC is in $18.
4486 See the source code for the stubs in gcc/config/mips/mips16.S for
4490 mips_skip_trampoline_code (CORE_ADDR pc
)
4493 CORE_ADDR start_addr
;
4495 /* Find the starting address and name of the function containing the PC. */
4496 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
4499 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
4500 target PC is in $31 ($ra). */
4501 if (strcmp (name
, "__mips16_ret_sf") == 0
4502 || strcmp (name
, "__mips16_ret_df") == 0)
4503 return read_signed_register (MIPS_RA_REGNUM
);
4505 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
4507 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
4508 and the target PC is in $2. */
4509 if (name
[19] >= '0' && name
[19] <= '9')
4510 return read_signed_register (2);
4512 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4513 before the jal instruction, this is effectively a call stub
4514 and the the target PC is in $2. Otherwise this is effectively
4515 a return stub and the target PC is in $18. */
4516 else if (name
[19] == 's' || name
[19] == 'd')
4518 if (pc
== start_addr
)
4520 /* Check if the target of the stub is a compiler-generated
4521 stub. Such a stub for a function bar might have a name
4522 like __fn_stub_bar, and might look like this:
4527 la $1,bar (becomes a lui/addiu pair)
4529 So scan down to the lui/addi and extract the target
4530 address from those two instructions. */
4532 CORE_ADDR target_pc
= read_signed_register (2);
4536 /* See if the name of the target function is __fn_stub_*. */
4537 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) ==
4540 if (strncmp (name
, "__fn_stub_", 10) != 0
4541 && strcmp (name
, "etext") != 0
4542 && strcmp (name
, "_etext") != 0)
4545 /* Scan through this _fn_stub_ code for the lui/addiu pair.
4546 The limit on the search is arbitrarily set to 20
4547 instructions. FIXME. */
4548 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS32_INSN_SIZE
)
4550 inst
= mips_fetch_instruction (target_pc
);
4551 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
4552 pc
= (inst
<< 16) & 0xffff0000; /* high word */
4553 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
4554 return pc
| (inst
& 0xffff); /* low word */
4557 /* Couldn't find the lui/addui pair, so return stub address. */
4561 /* This is the 'return' part of a call stub. The return
4562 address is in $r18. */
4563 return read_signed_register (18);
4566 return 0; /* not a stub */
4570 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
4571 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
4574 mips_in_call_stub (CORE_ADDR pc
, char *name
)
4576 CORE_ADDR start_addr
;
4578 /* Find the starting address of the function containing the PC. If the
4579 caller didn't give us a name, look it up at the same time. */
4580 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) ==
4584 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
4586 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
4587 if (name
[19] >= '0' && name
[19] <= '9')
4589 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4590 before the jal instruction, this is effectively a call stub. */
4591 else if (name
[19] == 's' || name
[19] == 'd')
4592 return pc
== start_addr
;
4595 return 0; /* not a stub */
4599 /* Return non-zero if the PC is inside a return thunk (aka stub or
4603 mips_in_solib_return_trampoline (CORE_ADDR pc
, char *name
)
4605 CORE_ADDR start_addr
;
4607 /* Find the starting address of the function containing the PC. */
4608 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
4611 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
4612 if (strcmp (name
, "__mips16_ret_sf") == 0
4613 || strcmp (name
, "__mips16_ret_df") == 0)
4616 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
4617 i.e. after the jal instruction, this is effectively a return stub. */
4618 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
4619 && (name
[19] == 's' || name
[19] == 'd') && pc
!= start_addr
)
4622 return 0; /* not a stub */
4626 /* Return non-zero if the PC is in a library helper function that
4627 should be ignored. This implements the
4628 DEPRECATED_IGNORE_HELPER_CALL macro. */
4631 mips_ignore_helper (CORE_ADDR pc
)
4635 /* Find the starting address and name of the function containing the PC. */
4636 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
4639 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
4640 that we want to ignore. */
4641 return (strcmp (name
, "__mips16_ret_sf") == 0
4642 || strcmp (name
, "__mips16_ret_df") == 0);
4646 /* Convert a dbx stab register number (from `r' declaration) to a GDB
4647 [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */
4650 mips_stab_reg_to_regnum (int num
)
4653 if (num
>= 0 && num
< 32)
4655 else if (num
>= 38 && num
< 70)
4656 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 38;
4658 regnum
= mips_regnum (current_gdbarch
)->hi
;
4660 regnum
= mips_regnum (current_gdbarch
)->lo
;
4662 /* This will hopefully (eventually) provoke a warning. Should
4663 we be calling complaint() here? */
4664 return NUM_REGS
+ NUM_PSEUDO_REGS
;
4665 return NUM_REGS
+ regnum
;
4669 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
4670 NUM_REGS .. 2 * NUM_REGS) REGNUM. */
4673 mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num
)
4676 if (num
>= 0 && num
< 32)
4678 else if (num
>= 32 && num
< 64)
4679 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 32;
4681 regnum
= mips_regnum (current_gdbarch
)->hi
;
4683 regnum
= mips_regnum (current_gdbarch
)->lo
;
4685 /* This will hopefully (eventually) provoke a warning. Should we
4686 be calling complaint() here? */
4687 return NUM_REGS
+ NUM_PSEUDO_REGS
;
4688 return NUM_REGS
+ regnum
;
4692 mips_register_sim_regno (int regnum
)
4694 /* Only makes sense to supply raw registers. */
4695 gdb_assert (regnum
>= 0 && regnum
< NUM_REGS
);
4696 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
4697 decide if it is valid. Should instead define a standard sim/gdb
4698 register numbering scheme. */
4699 if (REGISTER_NAME (NUM_REGS
+ regnum
) != NULL
4700 && REGISTER_NAME (NUM_REGS
+ regnum
)[0] != '\0')
4703 return LEGACY_SIM_REGNO_IGNORE
;
4707 /* Convert an integer into an address. By first converting the value
4708 into a pointer and then extracting it signed, the address is
4709 guarenteed to be correctly sign extended. */
4712 mips_integer_to_address (struct type
*type
, void *buf
)
4714 char *tmp
= alloca (TYPE_LENGTH (builtin_type_void_data_ptr
));
4715 LONGEST val
= unpack_long (type
, buf
);
4716 store_signed_integer (tmp
, TYPE_LENGTH (builtin_type_void_data_ptr
), val
);
4717 return extract_signed_integer (tmp
,
4718 TYPE_LENGTH (builtin_type_void_data_ptr
));
4722 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
4724 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
4725 const char *name
= bfd_get_section_name (abfd
, sect
);
4727 if (*abip
!= MIPS_ABI_UNKNOWN
)
4730 if (strncmp (name
, ".mdebug.", 8) != 0)
4733 if (strcmp (name
, ".mdebug.abi32") == 0)
4734 *abip
= MIPS_ABI_O32
;
4735 else if (strcmp (name
, ".mdebug.abiN32") == 0)
4736 *abip
= MIPS_ABI_N32
;
4737 else if (strcmp (name
, ".mdebug.abi64") == 0)
4738 *abip
= MIPS_ABI_N64
;
4739 else if (strcmp (name
, ".mdebug.abiO64") == 0)
4740 *abip
= MIPS_ABI_O64
;
4741 else if (strcmp (name
, ".mdebug.eabi32") == 0)
4742 *abip
= MIPS_ABI_EABI32
;
4743 else if (strcmp (name
, ".mdebug.eabi64") == 0)
4744 *abip
= MIPS_ABI_EABI64
;
4746 warning ("unsupported ABI %s.", name
+ 8);
4749 static enum mips_abi
4750 global_mips_abi (void)
4754 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
4755 if (mips_abi_strings
[i
] == mips_abi_string
)
4756 return (enum mips_abi
) i
;
4758 internal_error (__FILE__
, __LINE__
, "unknown ABI string");
4761 static struct gdbarch
*
4762 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
4764 struct gdbarch
*gdbarch
;
4765 struct gdbarch_tdep
*tdep
;
4767 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
4769 enum mips_fpu_type fpu_type
;
4771 /* First of all, extract the elf_flags, if available. */
4772 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
4773 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
4774 else if (arches
!= NULL
)
4775 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
4779 fprintf_unfiltered (gdb_stdlog
,
4780 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
4782 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
4783 switch ((elf_flags
& EF_MIPS_ABI
))
4785 case E_MIPS_ABI_O32
:
4786 found_abi
= MIPS_ABI_O32
;
4788 case E_MIPS_ABI_O64
:
4789 found_abi
= MIPS_ABI_O64
;
4791 case E_MIPS_ABI_EABI32
:
4792 found_abi
= MIPS_ABI_EABI32
;
4794 case E_MIPS_ABI_EABI64
:
4795 found_abi
= MIPS_ABI_EABI64
;
4798 if ((elf_flags
& EF_MIPS_ABI2
))
4799 found_abi
= MIPS_ABI_N32
;
4801 found_abi
= MIPS_ABI_UNKNOWN
;
4805 /* GCC creates a pseudo-section whose name describes the ABI. */
4806 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
4807 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
4809 /* If we have no useful BFD information, use the ABI from the last
4810 MIPS architecture (if there is one). */
4811 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
4812 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
4814 /* Try the architecture for any hint of the correct ABI. */
4815 if (found_abi
== MIPS_ABI_UNKNOWN
4816 && info
.bfd_arch_info
!= NULL
4817 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
4819 switch (info
.bfd_arch_info
->mach
)
4821 case bfd_mach_mips3900
:
4822 found_abi
= MIPS_ABI_EABI32
;
4824 case bfd_mach_mips4100
:
4825 case bfd_mach_mips5000
:
4826 found_abi
= MIPS_ABI_EABI64
;
4828 case bfd_mach_mips8000
:
4829 case bfd_mach_mips10000
:
4830 /* On Irix, ELF64 executables use the N64 ABI. The
4831 pseudo-sections which describe the ABI aren't present
4832 on IRIX. (Even for executables created by gcc.) */
4833 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
4834 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
4835 found_abi
= MIPS_ABI_N64
;
4837 found_abi
= MIPS_ABI_N32
;
4843 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
4846 /* What has the user specified from the command line? */
4847 wanted_abi
= global_mips_abi ();
4849 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
4852 /* Now that we have found what the ABI for this binary would be,
4853 check whether the user is overriding it. */
4854 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
4855 mips_abi
= wanted_abi
;
4856 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
4857 mips_abi
= found_abi
;
4859 mips_abi
= MIPS_ABI_O32
;
4861 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
4864 /* Also used when doing an architecture lookup. */
4866 fprintf_unfiltered (gdb_stdlog
,
4867 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
4868 mips64_transfers_32bit_regs_p
);
4870 /* Determine the MIPS FPU type. */
4871 if (!mips_fpu_type_auto
)
4872 fpu_type
= mips_fpu_type
;
4873 else if (info
.bfd_arch_info
!= NULL
4874 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
4875 switch (info
.bfd_arch_info
->mach
)
4877 case bfd_mach_mips3900
:
4878 case bfd_mach_mips4100
:
4879 case bfd_mach_mips4111
:
4880 case bfd_mach_mips4120
:
4881 fpu_type
= MIPS_FPU_NONE
;
4883 case bfd_mach_mips4650
:
4884 fpu_type
= MIPS_FPU_SINGLE
;
4887 fpu_type
= MIPS_FPU_DOUBLE
;
4890 else if (arches
!= NULL
)
4891 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
4893 fpu_type
= MIPS_FPU_DOUBLE
;
4895 fprintf_unfiltered (gdb_stdlog
,
4896 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
4898 /* try to find a pre-existing architecture */
4899 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
4901 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
4903 /* MIPS needs to be pedantic about which ABI the object is
4905 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
4907 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
4909 /* Need to be pedantic about which register virtual size is
4911 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
4912 != mips64_transfers_32bit_regs_p
)
4914 /* Be pedantic about which FPU is selected. */
4915 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
4917 return arches
->gdbarch
;
4920 /* Need a new architecture. Fill in a target specific vector. */
4921 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
4922 gdbarch
= gdbarch_alloc (&info
, tdep
);
4923 tdep
->elf_flags
= elf_flags
;
4924 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
4925 tdep
->found_abi
= found_abi
;
4926 tdep
->mips_abi
= mips_abi
;
4927 tdep
->mips_fpu_type
= fpu_type
;
4929 /* Initially set everything according to the default ABI/ISA. */
4930 set_gdbarch_short_bit (gdbarch
, 16);
4931 set_gdbarch_int_bit (gdbarch
, 32);
4932 set_gdbarch_float_bit (gdbarch
, 32);
4933 set_gdbarch_double_bit (gdbarch
, 64);
4934 set_gdbarch_long_double_bit (gdbarch
, 64);
4935 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
4936 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
4937 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
4939 set_gdbarch_elf_make_msymbol_special (gdbarch
,
4940 mips_elf_make_msymbol_special
);
4942 /* Fill in the OS dependant register numbers and names. */
4944 const char **reg_names
;
4945 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
4946 struct mips_regnum
);
4947 if (info
.osabi
== GDB_OSABI_IRIX
)
4952 regnum
->badvaddr
= 66;
4955 regnum
->fp_control_status
= 69;
4956 regnum
->fp_implementation_revision
= 70;
4958 reg_names
= mips_irix_reg_names
;
4962 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
4963 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
4964 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
4965 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
4966 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
4967 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
4968 regnum
->fp_control_status
= 70;
4969 regnum
->fp_implementation_revision
= 71;
4971 if (info
.bfd_arch_info
!= NULL
4972 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
4973 reg_names
= mips_tx39_reg_names
;
4975 reg_names
= mips_generic_reg_names
;
4977 /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been
4978 replaced by read_pc? */
4979 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
4980 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
4981 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
4982 set_gdbarch_num_regs (gdbarch
, num_regs
);
4983 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
4984 set_gdbarch_register_name (gdbarch
, mips_register_name
);
4985 tdep
->mips_processor_reg_names
= reg_names
;
4986 tdep
->regnum
= regnum
;
4992 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
4993 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
4994 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
4995 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
4996 tdep
->default_mask_address_p
= 0;
4997 set_gdbarch_long_bit (gdbarch
, 32);
4998 set_gdbarch_ptr_bit (gdbarch
, 32);
4999 set_gdbarch_long_long_bit (gdbarch
, 64);
5002 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
5003 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
5004 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
5005 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5006 tdep
->default_mask_address_p
= 0;
5007 set_gdbarch_long_bit (gdbarch
, 32);
5008 set_gdbarch_ptr_bit (gdbarch
, 32);
5009 set_gdbarch_long_long_bit (gdbarch
, 64);
5011 case MIPS_ABI_EABI32
:
5012 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5013 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
5014 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5015 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5016 tdep
->default_mask_address_p
= 0;
5017 set_gdbarch_long_bit (gdbarch
, 32);
5018 set_gdbarch_ptr_bit (gdbarch
, 32);
5019 set_gdbarch_long_long_bit (gdbarch
, 64);
5021 case MIPS_ABI_EABI64
:
5022 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5023 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
5024 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5025 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5026 tdep
->default_mask_address_p
= 0;
5027 set_gdbarch_long_bit (gdbarch
, 64);
5028 set_gdbarch_ptr_bit (gdbarch
, 64);
5029 set_gdbarch_long_long_bit (gdbarch
, 64);
5032 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5033 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5034 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5035 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5036 tdep
->default_mask_address_p
= 0;
5037 set_gdbarch_long_bit (gdbarch
, 32);
5038 set_gdbarch_ptr_bit (gdbarch
, 32);
5039 set_gdbarch_long_long_bit (gdbarch
, 64);
5040 set_gdbarch_long_double_bit (gdbarch
, 128);
5041 set_gdbarch_long_double_format (gdbarch
,
5042 &floatformat_n32n64_long_double_big
);
5045 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5046 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5047 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5048 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5049 tdep
->default_mask_address_p
= 0;
5050 set_gdbarch_long_bit (gdbarch
, 64);
5051 set_gdbarch_ptr_bit (gdbarch
, 64);
5052 set_gdbarch_long_long_bit (gdbarch
, 64);
5053 set_gdbarch_long_double_bit (gdbarch
, 128);
5054 set_gdbarch_long_double_format (gdbarch
,
5055 &floatformat_n32n64_long_double_big
);
5058 internal_error (__FILE__
, __LINE__
, "unknown ABI in switch");
5061 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5062 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5065 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
5066 flag in object files because to do so would make it impossible to
5067 link with libraries compiled without "-gp32". This is
5068 unnecessarily restrictive.
5070 We could solve this problem by adding "-gp32" multilibs to gcc,
5071 but to set this flag before gcc is built with such multilibs will
5072 break too many systems.''
5074 But even more unhelpfully, the default linker output target for
5075 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
5076 for 64-bit programs - you need to change the ABI to change this,
5077 and not all gcc targets support that currently. Therefore using
5078 this flag to detect 32-bit mode would do the wrong thing given
5079 the current gcc - it would make GDB treat these 64-bit programs
5080 as 32-bit programs by default. */
5082 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
5083 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
5084 set_gdbarch_read_sp (gdbarch
, mips_read_sp
);
5086 /* Add/remove bits from an address. The MIPS needs be careful to
5087 ensure that all 32 bit addresses are sign extended to 64 bits. */
5088 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
5090 /* Unwind the frame. */
5091 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
5092 set_gdbarch_unwind_dummy_id (gdbarch
, mips_unwind_dummy_id
);
5094 /* Map debug register numbers onto internal register numbers. */
5095 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
5096 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
5097 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5098 set_gdbarch_dwarf_reg_to_regnum (gdbarch
,
5099 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5100 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
5101 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5102 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
5104 /* MIPS version of CALL_DUMMY */
5106 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
5107 replaced by a command, and all targets will default to on stack
5108 (regardless of the stack's execute status). */
5109 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
5110 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
5112 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
5113 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
5114 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
5116 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
5117 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
5119 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
5121 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
5122 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
5123 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
5125 set_gdbarch_register_type (gdbarch
, mips_register_type
);
5127 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
5129 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
5131 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
5132 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
5133 need to all be folded into the target vector. Since they are
5134 being used as guards for STOPPED_BY_WATCHPOINT, why not have
5135 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
5137 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
5139 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
5141 /* NOTE drow/2004-02-11: We overload the core solib trampoline code
5142 to support MIPS16. This is a bad thing. Make sure not to do it
5143 if we have an OS ABI that actually supports shared libraries, since
5144 shared library support is more important. If we have an OS someday
5145 that supports both shared libraries and MIPS16, we'll have to find
5146 a better place for these. */
5147 if (info
.osabi
== GDB_OSABI_UNKNOWN
)
5149 set_gdbarch_in_solib_call_trampoline (gdbarch
, mips_in_call_stub
);
5150 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_solib_return_trampoline
);
5153 /* Hook in OS ABI-specific overrides, if they have been registered. */
5154 gdbarch_init_osabi (info
, gdbarch
);
5156 /* Unwind the frame. */
5157 frame_unwind_append_sniffer (gdbarch
, mips_stub_frame_sniffer
);
5158 frame_unwind_append_sniffer (gdbarch
, mips_insn16_frame_sniffer
);
5159 frame_unwind_append_sniffer (gdbarch
, mips_insn32_frame_sniffer
);
5160 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
5161 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
5162 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
5168 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
5170 struct gdbarch_info info
;
5172 /* Force the architecture to update, and (if it's a MIPS architecture)
5173 mips_gdbarch_init will take care of the rest. */
5174 gdbarch_info_init (&info
);
5175 gdbarch_update_p (info
);
5178 /* Print out which MIPS ABI is in use. */
5181 show_mips_abi (char *ignore_args
, int from_tty
)
5183 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_mips
)
5185 ("The MIPS ABI is unknown because the current architecture is not MIPS.\n");
5188 enum mips_abi global_abi
= global_mips_abi ();
5189 enum mips_abi actual_abi
= mips_abi (current_gdbarch
);
5190 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
5192 if (global_abi
== MIPS_ABI_UNKNOWN
)
5194 ("The MIPS ABI is set automatically (currently \"%s\").\n",
5196 else if (global_abi
== actual_abi
)
5198 ("The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
5202 /* Probably shouldn't happen... */
5204 ("The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
5205 actual_abi_str
, mips_abi_strings
[global_abi
]);
5211 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
5213 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5217 int ef_mips_32bitmode
;
5218 /* determine the ISA */
5219 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
5237 /* determine the size of a pointer */
5238 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
5239 fprintf_unfiltered (file
,
5240 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
5242 fprintf_unfiltered (file
,
5243 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
5245 fprintf_unfiltered (file
,
5246 "mips_dump_tdep: ef_mips_arch = %d\n",
5248 fprintf_unfiltered (file
,
5249 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
5250 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
5251 fprintf_unfiltered (file
,
5252 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
5253 mips_mask_address_p (tdep
),
5254 tdep
->default_mask_address_p
);
5256 fprintf_unfiltered (file
,
5257 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
5258 MIPS_DEFAULT_FPU_TYPE
,
5259 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
5260 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
5261 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
5263 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI
);
5264 fprintf_unfiltered (file
,
5265 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
5267 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
5268 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
5269 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
5271 fprintf_unfiltered (file
,
5272 "mips_dump_tdep: mips_stack_argsize() = %d\n",
5273 mips_stack_argsize (current_gdbarch
));
5274 fprintf_unfiltered (file
,
5275 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
5276 XSTRING (ADDR_BITS_REMOVE (ADDR
)));
5277 fprintf_unfiltered (file
,
5278 "mips_dump_tdep: ATTACH_DETACH # %s\n",
5279 XSTRING (ATTACH_DETACH
));
5280 fprintf_unfiltered (file
,
5281 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
5282 XSTRING (DWARF_REG_TO_REGNUM (REGNUM
)));
5283 fprintf_unfiltered (file
,
5284 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
5285 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM
)));
5286 fprintf_unfiltered (file
,
5287 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
5288 FIRST_EMBED_REGNUM
);
5289 fprintf_unfiltered (file
,
5290 "mips_dump_tdep: DEPRECATED_IGNORE_HELPER_CALL # %s\n",
5291 XSTRING (DEPRECATED_IGNORE_HELPER_CALL (PC
)));
5292 fprintf_unfiltered (file
,
5293 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
5294 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC
, NAME
)));
5295 fprintf_unfiltered (file
,
5296 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
5298 #ifdef MACHINE_CPROC_FP_OFFSET
5299 fprintf_unfiltered (file
,
5300 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
5301 MACHINE_CPROC_FP_OFFSET
);
5303 #ifdef MACHINE_CPROC_PC_OFFSET
5304 fprintf_unfiltered (file
,
5305 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
5306 MACHINE_CPROC_PC_OFFSET
);
5308 #ifdef MACHINE_CPROC_SP_OFFSET
5309 fprintf_unfiltered (file
,
5310 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
5311 MACHINE_CPROC_SP_OFFSET
);
5313 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
5314 fprintf_unfiltered (file
,
5315 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
5316 fprintf_unfiltered (file
,
5317 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
5318 MIPS_LAST_ARG_REGNUM
,
5319 MIPS_LAST_ARG_REGNUM
- MIPS_A0_REGNUM
+ 1);
5320 fprintf_unfiltered (file
,
5321 "mips_dump_tdep: MIPS_NUMREGS = %d\n", MIPS_NUMREGS
);
5322 fprintf_unfiltered (file
,
5323 "mips_dump_tdep: mips_abi_regsize() = %d\n",
5324 mips_abi_regsize (current_gdbarch
));
5325 fprintf_unfiltered (file
,
5326 "mips_dump_tdep: PRID_REGNUM = %d\n", PRID_REGNUM
);
5327 fprintf_unfiltered (file
,
5328 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
5329 fprintf_unfiltered (file
,
5330 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
5331 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FRAME_REG = function?\n");
5332 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FREG_MASK = function?\n");
5333 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
5334 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
5335 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
5336 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_PC_REG = function?\n");
5337 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_REG_MASK = function?\n");
5338 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
5339 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_SYMBOL = function?\n");
5340 fprintf_unfiltered (file
, "mips_dump_tdep: PS_REGNUM = %d\n", PS_REGNUM
);
5342 fprintf_unfiltered (file
,
5343 "mips_dump_tdep: SAVED_BYTES = %d\n", SAVED_BYTES
);
5346 fprintf_unfiltered (file
, "mips_dump_tdep: SAVED_FP = %d\n", SAVED_FP
);
5349 fprintf_unfiltered (file
, "mips_dump_tdep: SAVED_PC = %d\n", SAVED_PC
);
5351 fprintf_unfiltered (file
,
5352 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
5353 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS
, ARGS
)));
5354 fprintf_unfiltered (file
,
5355 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
5356 XSTRING (SOFTWARE_SINGLE_STEP (SIG
, BP_P
)));
5357 fprintf_unfiltered (file
,
5358 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n",
5359 SOFTWARE_SINGLE_STEP_P ());
5360 fprintf_unfiltered (file
,
5361 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
5362 XSTRING (STAB_REG_TO_REGNUM (REGNUM
)));
5363 #ifdef STACK_END_ADDR
5364 fprintf_unfiltered (file
,
5365 "mips_dump_tdep: STACK_END_ADDR = %d\n",
5368 fprintf_unfiltered (file
,
5369 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
5370 XSTRING (STEP_SKIPS_DELAY (PC
)));
5371 fprintf_unfiltered (file
,
5372 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
5373 STEP_SKIPS_DELAY_P
);
5374 fprintf_unfiltered (file
,
5375 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
5376 XSTRING (STOPPED_BY_WATCHPOINT (WS
)));
5377 fprintf_unfiltered (file
,
5378 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
5379 fprintf_unfiltered (file
,
5380 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
5381 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT
5382 (TYPE
, CNT
, OTHERTYPE
)));
5384 fprintf_unfiltered (file
,
5385 "mips_dump_tdep: TRACE_CLEAR # %s\n",
5386 XSTRING (TRACE_CLEAR (THREAD
, STATE
)));
5389 fprintf_unfiltered (file
,
5390 "mips_dump_tdep: TRACE_FLAVOR = %d\n", TRACE_FLAVOR
);
5392 #ifdef TRACE_FLAVOR_SIZE
5393 fprintf_unfiltered (file
,
5394 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
5398 fprintf_unfiltered (file
,
5399 "mips_dump_tdep: TRACE_SET # %s\n",
5400 XSTRING (TRACE_SET (X
, STATE
)));
5402 #ifdef UNUSED_REGNUM
5403 fprintf_unfiltered (file
,
5404 "mips_dump_tdep: UNUSED_REGNUM = %d\n", UNUSED_REGNUM
);
5406 fprintf_unfiltered (file
,
5407 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
5408 (long) VM_MIN_ADDRESS
);
5411 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
5414 _initialize_mips_tdep (void)
5416 static struct cmd_list_element
*mipsfpulist
= NULL
;
5417 struct cmd_list_element
*c
;
5419 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
5420 if (MIPS_ABI_LAST
+ 1
5421 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
5422 internal_error (__FILE__
, __LINE__
, "mips_abi_strings out of sync");
5424 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
5426 mips_pdr_data
= register_objfile_data ();
5428 /* Add root prefix command for all "set mips"/"show mips" commands */
5429 add_prefix_cmd ("mips", no_class
, set_mips_command
,
5430 "Various MIPS specific commands.",
5431 &setmipscmdlist
, "set mips ", 0, &setlist
);
5433 add_prefix_cmd ("mips", no_class
, show_mips_command
,
5434 "Various MIPS specific commands.",
5435 &showmipscmdlist
, "show mips ", 0, &showlist
);
5437 /* Allow the user to override the saved register size. */
5438 add_setshow_enum_cmd ("saved-gpreg-size", class_obscure
,
5439 size_enums
, &mips_abi_regsize_string
, "\
5440 Set size of general purpose registers saved on the stack.\n", "\
5441 Show size of general purpose registers saved on the stack.\n", "\
5442 This option can be set to one of:\n\
5443 32 - Force GDB to treat saved GP registers as 32-bit\n\
5444 64 - Force GDB to treat saved GP registers as 64-bit\n\
5445 auto - Allow GDB to use the target's default setting or autodetect the\n\
5446 saved GP register size from information contained in the executable.\n\
5447 (default: auto)", "\
5448 Size of general purpose registers saved on the stack is %s.\n",
5449 NULL
, NULL
, &setmipscmdlist
, &showmipscmdlist
);
5451 /* Allow the user to override the argument stack size. */
5452 add_setshow_enum_cmd ("stack-arg-size", class_obscure
,
5453 size_enums
, &mips_stack_argsize_string
, "\
5454 Set the amount of stack space reserved for each argument.\n", "\
5455 Show the amount of stack space reserved for each argument.\n", "\
5456 This option can be set to one of:\n\
5457 32 - Force GDB to allocate 32-bit chunks per argument\n\
5458 64 - Force GDB to allocate 64-bit chunks per argument\n\
5459 auto - Allow GDB to determine the correct setting from the current\n\
5460 target and executable (default)", "\
5461 The amount of stack space reserved for each argument is %s.\n",
5462 NULL
, NULL
, &setmipscmdlist
, &showmipscmdlist
);
5464 /* Allow the user to override the ABI. */
5465 c
= add_set_enum_cmd
5466 ("abi", class_obscure
, mips_abi_strings
, &mips_abi_string
,
5467 "Set the ABI used by this program.\n"
5468 "This option can be set to one of:\n"
5469 " auto - the default ABI associated with the current binary\n"
5471 " o64\n" " n32\n" " n64\n" " eabi32\n" " eabi64", &setmipscmdlist
);
5472 set_cmd_sfunc (c
, mips_abi_update
);
5473 add_cmd ("abi", class_obscure
, show_mips_abi
,
5474 "Show ABI in use by MIPS target", &showmipscmdlist
);
5476 /* Let the user turn off floating point and set the fence post for
5477 heuristic_proc_start. */
5479 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
5480 "Set use of MIPS floating-point coprocessor.",
5481 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
5482 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
5483 "Select single-precision MIPS floating-point coprocessor.",
5485 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
5486 "Select double-precision MIPS floating-point coprocessor.",
5488 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
5489 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
5490 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
5491 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
5492 "Select no MIPS floating-point coprocessor.", &mipsfpulist
);
5493 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
5494 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
5495 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
5496 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
5497 "Select MIPS floating-point coprocessor automatically.",
5499 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
5500 "Show current use of MIPS floating-point coprocessor target.",
5503 /* We really would like to have both "0" and "unlimited" work, but
5504 command.c doesn't deal with that. So make it a var_zinteger
5505 because the user can always use "999999" or some such for unlimited. */
5506 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
5507 &heuristic_fence_post
, "\
5508 Set the distance searched for the start of a function.\n", "\
5509 Show the distance searched for the start of a function.\n", "\
5510 If you are debugging a stripped executable, GDB needs to search through the\n\
5511 program for the start of a function. This command sets the distance of the\n\
5512 search. The only need to set it is when debugging a stripped executable.", "\
5513 The distance searched for the start of a function is %s.\n",
5514 reinit_frame_cache_sfunc
, NULL
,
5515 &setlist
, &showlist
);
5517 /* Allow the user to control whether the upper bits of 64-bit
5518 addresses should be zeroed. */
5519 add_setshow_auto_boolean_cmd ("mask-address", no_class
, &mask_address_var
, "\
5520 Set zeroing of upper 32 bits of 64-bit addresses.", "\
5521 Show zeroing of upper 32 bits of 64-bit addresses.", "\
5522 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
5523 allow GDB to determine the correct value.\n", "\
5524 Zerroing of upper 32 bits of 64-bit address is %s.",
5525 NULL
, show_mask_address
, &setmipscmdlist
, &showmipscmdlist
);
5527 /* Allow the user to control the size of 32 bit registers within the
5528 raw remote packet. */
5529 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
5530 &mips64_transfers_32bit_regs_p
, "\
5531 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities.", "\
5532 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities.", "\
5533 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
5534 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
5535 64 bits for others. Use \"off\" to disable compatibility mode", "\
5536 Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s.",
5537 set_mips64_transfers_32bit_regs
, NULL
, &setlist
, &showlist
);
5539 /* Debug this files internals. */
5540 add_setshow_zinteger_cmd ("mips", class_maintenance
,
5542 Set mips debugging.\n", "\
5543 Show mips debugging.\n", "\
5544 When non-zero, mips specific debugging is enabled.\n", "\
5545 Mips debugging is currently %s.\n",
5547 &setdebuglist
, &showdebuglist
);