1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
5 Free Software Foundation, Inc.
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software
24 Foundation, Inc., 51 Franklin Street, Fifth Floor,
25 Boston, MA 02110-1301, USA. */
28 #include "gdb_string.h"
29 #include "gdb_assert.h"
41 #include "arch-utils.h"
44 #include "mips-tdep.h"
46 #include "reggroups.h"
47 #include "opcode/mips.h"
51 #include "sim-regno.h"
53 #include "frame-unwind.h"
54 #include "frame-base.h"
55 #include "trad-frame.h"
57 #include "floatformat.h"
59 #include "target-descriptions.h"
60 #include "dwarf2-frame.h"
62 static const struct objfile_data
*mips_pdr_data
;
64 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
66 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
67 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
68 #define ST0_FR (1 << 26)
70 /* The sizes of floating point registers. */
74 MIPS_FPU_SINGLE_REGSIZE
= 4,
75 MIPS_FPU_DOUBLE_REGSIZE
= 8
84 static const char *mips_abi_string
;
86 static const char *mips_abi_strings
[] = {
97 /* Some MIPS boards don't support floating point while others only
98 support single-precision floating-point operations. */
102 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
103 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
104 MIPS_FPU_NONE
/* No floating point. */
107 #ifndef MIPS_DEFAULT_FPU_TYPE
108 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
110 static int mips_fpu_type_auto
= 1;
111 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
113 static int mips_debug
= 0;
115 /* Properties (for struct target_desc) describing the g/G packet
117 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
118 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
120 /* MIPS specific per-architecture information */
123 /* from the elf header */
127 enum mips_abi mips_abi
;
128 enum mips_abi found_abi
;
129 enum mips_fpu_type mips_fpu_type
;
130 int mips_last_arg_regnum
;
131 int mips_last_fp_arg_regnum
;
132 int default_mask_address_p
;
133 /* Is the target using 64-bit raw integer registers but only
134 storing a left-aligned 32-bit value in each? */
135 int mips64_transfers_32bit_regs_p
;
136 /* Indexes for various registers. IRIX and embedded have
137 different values. This contains the "public" fields. Don't
138 add any that do not need to be public. */
139 const struct mips_regnum
*regnum
;
140 /* Register names table for the current register set. */
141 const char **mips_processor_reg_names
;
143 /* The size of register data available from the target, if known.
144 This doesn't quite obsolete the manual
145 mips64_transfers_32bit_regs_p, since that is documented to force
146 left alignment even for big endian (very strange). */
147 int register_size_valid_p
;
152 n32n64_floatformat_always_valid (const struct floatformat
*fmt
,
158 /* FIXME: brobecker/2004-08-08: Long Double values are 128 bit long.
159 They are implemented as a pair of 64bit doubles where the high
160 part holds the result of the operation rounded to double, and
161 the low double holds the difference between the exact result and
162 the rounded result. So "high" + "low" contains the result with
163 added precision. Unfortunately, the floatformat structure used
164 by GDB is not powerful enough to describe this format. As a temporary
165 measure, we define a 128bit floatformat that only uses the high part.
166 We lose a bit of precision but that's probably the best we can do
167 for now with the current infrastructure. */
169 static const struct floatformat floatformat_n32n64_long_double_big
=
171 floatformat_big
, 128, 0, 1, 11, 1023, 2047, 12, 52,
172 floatformat_intbit_no
,
173 "floatformat_n32n64_long_double_big",
174 n32n64_floatformat_always_valid
177 static const struct floatformat
*floatformats_n32n64_long
[BFD_ENDIAN_UNKNOWN
] =
179 &floatformat_n32n64_long_double_big
,
180 &floatformat_n32n64_long_double_big
183 const struct mips_regnum
*
184 mips_regnum (struct gdbarch
*gdbarch
)
186 return gdbarch_tdep (gdbarch
)->regnum
;
190 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
192 return mips_regnum (gdbarch
)->fp0
+ 12;
195 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
196 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
198 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
200 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
202 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
204 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
205 functions to test, set, or clear bit 0 of addresses. */
208 is_mips16_addr (CORE_ADDR addr
)
214 unmake_mips16_addr (CORE_ADDR addr
)
216 return ((addr
) & ~(CORE_ADDR
) 1);
219 /* Return the contents of register REGNUM as a signed integer. */
222 read_signed_register (int regnum
)
225 regcache_cooked_read_signed (current_regcache
, regnum
, &val
);
230 read_signed_register_pid (int regnum
, ptid_t ptid
)
235 if (ptid_equal (ptid
, inferior_ptid
))
236 return read_signed_register (regnum
);
238 save_ptid
= inferior_ptid
;
240 inferior_ptid
= ptid
;
242 retval
= read_signed_register (regnum
);
244 inferior_ptid
= save_ptid
;
249 /* Return the MIPS ABI associated with GDBARCH. */
251 mips_abi (struct gdbarch
*gdbarch
)
253 return gdbarch_tdep (gdbarch
)->mips_abi
;
257 mips_isa_regsize (struct gdbarch
*gdbarch
)
259 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
261 /* If we know how big the registers are, use that size. */
262 if (tdep
->register_size_valid_p
)
263 return tdep
->register_size
;
265 /* Fall back to the previous behavior. */
266 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
267 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
270 /* Return the currently configured (or set) saved register size. */
273 mips_abi_regsize (struct gdbarch
*gdbarch
)
275 switch (mips_abi (gdbarch
))
277 case MIPS_ABI_EABI32
:
283 case MIPS_ABI_EABI64
:
285 case MIPS_ABI_UNKNOWN
:
288 internal_error (__FILE__
, __LINE__
, _("bad switch"));
292 /* Functions for setting and testing a bit in a minimal symbol that
293 marks it as 16-bit function. The MSB of the minimal symbol's
294 "info" field is used for this purpose.
296 ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special",
297 i.e. refers to a 16-bit function, and sets a "special" bit in a
298 minimal symbol to mark it as a 16-bit function
300 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
303 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
305 if (((elf_symbol_type
*) (sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
307 MSYMBOL_INFO (msym
) = (char *)
308 (((long) MSYMBOL_INFO (msym
)) | 0x80000000);
309 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
314 msymbol_is_special (struct minimal_symbol
*msym
)
316 return (((long) MSYMBOL_INFO (msym
) & 0x80000000) != 0);
319 /* XFER a value from the big/little/left end of the register.
320 Depending on the size of the value it might occupy the entire
321 register or just part of it. Make an allowance for this, aligning
322 things accordingly. */
325 mips_xfer_register (struct regcache
*regcache
, int reg_num
, int length
,
326 enum bfd_endian endian
, gdb_byte
*in
,
327 const gdb_byte
*out
, int buf_offset
)
330 gdb_assert (reg_num
>= NUM_REGS
);
331 /* Need to transfer the left or right part of the register, based on
332 the targets byte order. */
336 reg_offset
= register_size (current_gdbarch
, reg_num
) - length
;
338 case BFD_ENDIAN_LITTLE
:
341 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
345 internal_error (__FILE__
, __LINE__
, _("bad switch"));
348 fprintf_unfiltered (gdb_stderr
,
349 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
350 reg_num
, reg_offset
, buf_offset
, length
);
351 if (mips_debug
&& out
!= NULL
)
354 fprintf_unfiltered (gdb_stdlog
, "out ");
355 for (i
= 0; i
< length
; i
++)
356 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
359 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
362 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
364 if (mips_debug
&& in
!= NULL
)
367 fprintf_unfiltered (gdb_stdlog
, "in ");
368 for (i
= 0; i
< length
; i
++)
369 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
372 fprintf_unfiltered (gdb_stdlog
, "\n");
375 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
376 compatiblity mode. A return value of 1 means that we have
377 physical 64-bit registers, but should treat them as 32-bit registers. */
380 mips2_fp_compat (void)
382 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
384 if (register_size (current_gdbarch
, mips_regnum (current_gdbarch
)->fp0
) ==
389 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
390 in all the places we deal with FP registers. PR gdb/413. */
391 /* Otherwise check the FR bit in the status register - it controls
392 the FP compatiblity mode. If it is clear we are in compatibility
394 if ((read_register (MIPS_PS_REGNUM
) & ST0_FR
) == 0)
401 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
403 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
405 static CORE_ADDR
read_next_frame_reg (struct frame_info
*, int);
407 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
409 static struct type
*mips_float_register_type (void);
410 static struct type
*mips_double_register_type (void);
412 /* The list of available "set mips " and "show mips " commands */
414 static struct cmd_list_element
*setmipscmdlist
= NULL
;
415 static struct cmd_list_element
*showmipscmdlist
= NULL
;
417 /* Integer registers 0 thru 31 are handled explicitly by
418 mips_register_name(). Processor specific registers 32 and above
419 are listed in the following tables. */
422 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
426 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
427 "sr", "lo", "hi", "bad", "cause", "pc",
428 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
429 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
430 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
431 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
432 "fsr", "fir", "" /*"fp" */ , "",
433 "", "", "", "", "", "", "", "",
434 "", "", "", "", "", "", "", "",
437 /* Names of IDT R3041 registers. */
439 static const char *mips_r3041_reg_names
[] = {
440 "sr", "lo", "hi", "bad", "cause", "pc",
441 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
442 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
443 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
444 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
445 "fsr", "fir", "", /*"fp" */ "",
446 "", "", "bus", "ccfg", "", "", "", "",
447 "", "", "port", "cmp", "", "", "epc", "prid",
450 /* Names of tx39 registers. */
452 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
453 "sr", "lo", "hi", "bad", "cause", "pc",
454 "", "", "", "", "", "", "", "",
455 "", "", "", "", "", "", "", "",
456 "", "", "", "", "", "", "", "",
457 "", "", "", "", "", "", "", "",
459 "", "", "", "", "", "", "", "",
460 "", "", "config", "cache", "debug", "depc", "epc", ""
463 /* Names of IRIX registers. */
464 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
465 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
466 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
467 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
468 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
469 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
473 /* Return the name of the register corresponding to REGNO. */
475 mips_register_name (int regno
)
477 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
478 /* GPR names for all ABIs other than n32/n64. */
479 static char *mips_gpr_names
[] = {
480 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
481 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
482 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
483 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
486 /* GPR names for n32 and n64 ABIs. */
487 static char *mips_n32_n64_gpr_names
[] = {
488 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
489 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
490 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
491 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
494 enum mips_abi abi
= mips_abi (current_gdbarch
);
496 /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then
497 don't make the raw register names visible. */
498 int rawnum
= regno
% NUM_REGS
;
499 if (regno
< NUM_REGS
)
502 /* The MIPS integer registers are always mapped from 0 to 31. The
503 names of the registers (which reflects the conventions regarding
504 register use) vary depending on the ABI. */
505 if (0 <= rawnum
&& rawnum
< 32)
507 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
508 return mips_n32_n64_gpr_names
[rawnum
];
510 return mips_gpr_names
[rawnum
];
512 else if (32 <= rawnum
&& rawnum
< NUM_REGS
)
514 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
515 return tdep
->mips_processor_reg_names
[rawnum
- 32];
518 internal_error (__FILE__
, __LINE__
,
519 _("mips_register_name: bad register number %d"), rawnum
);
522 /* Return the groups that a MIPS register can be categorised into. */
525 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
526 struct reggroup
*reggroup
)
531 int rawnum
= regnum
% NUM_REGS
;
532 int pseudo
= regnum
/ NUM_REGS
;
533 if (reggroup
== all_reggroup
)
535 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
536 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
537 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
538 (gdbarch), as not all architectures are multi-arch. */
539 raw_p
= rawnum
< NUM_REGS
;
540 if (REGISTER_NAME (regnum
) == NULL
|| REGISTER_NAME (regnum
)[0] == '\0')
542 if (reggroup
== float_reggroup
)
543 return float_p
&& pseudo
;
544 if (reggroup
== vector_reggroup
)
545 return vector_p
&& pseudo
;
546 if (reggroup
== general_reggroup
)
547 return (!vector_p
&& !float_p
) && pseudo
;
548 /* Save the pseudo registers. Need to make certain that any code
549 extracting register values from a saved register cache also uses
551 if (reggroup
== save_reggroup
)
552 return raw_p
&& pseudo
;
553 /* Restore the same pseudo register. */
554 if (reggroup
== restore_reggroup
)
555 return raw_p
&& pseudo
;
559 /* Map the symbol table registers which live in the range [1 *
560 NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw
561 registers. Take care of alignment and size problems. */
564 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
565 int cookednum
, gdb_byte
*buf
)
567 int rawnum
= cookednum
% NUM_REGS
;
568 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
569 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
570 regcache_raw_read (regcache
, rawnum
, buf
);
571 else if (register_size (gdbarch
, rawnum
) >
572 register_size (gdbarch
, cookednum
))
574 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
575 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
576 regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
578 regcache_raw_read_part (regcache
, rawnum
, 4, 4, buf
);
581 internal_error (__FILE__
, __LINE__
, _("bad register size"));
585 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
586 struct regcache
*regcache
, int cookednum
,
589 int rawnum
= cookednum
% NUM_REGS
;
590 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
591 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
592 regcache_raw_write (regcache
, rawnum
, buf
);
593 else if (register_size (gdbarch
, rawnum
) >
594 register_size (gdbarch
, cookednum
))
596 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
597 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
598 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
600 regcache_raw_write_part (regcache
, rawnum
, 4, 4, buf
);
603 internal_error (__FILE__
, __LINE__
, _("bad register size"));
606 /* Table to translate MIPS16 register field to actual register number. */
607 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
609 /* Heuristic_proc_start may hunt through the text section for a long
610 time across a 2400 baud serial line. Allows the user to limit this
613 static unsigned int heuristic_fence_post
= 0;
615 /* Number of bytes of storage in the actual machine representation for
616 register N. NOTE: This defines the pseudo register type so need to
617 rebuild the architecture vector. */
619 static int mips64_transfers_32bit_regs_p
= 0;
622 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
623 struct cmd_list_element
*c
)
625 struct gdbarch_info info
;
626 gdbarch_info_init (&info
);
627 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
628 instead of relying on globals. Doing that would let generic code
629 handle the search for this specific architecture. */
630 if (!gdbarch_update_p (info
))
632 mips64_transfers_32bit_regs_p
= 0;
633 error (_("32-bit compatibility mode not supported"));
637 /* Convert to/from a register and the corresponding memory value. */
640 mips_convert_register_p (int regnum
, struct type
*type
)
642 return (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
643 && register_size (current_gdbarch
, regnum
) == 4
644 && (regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
645 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32
646 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
650 mips_register_to_value (struct frame_info
*frame
, int regnum
,
651 struct type
*type
, gdb_byte
*to
)
653 get_frame_register (frame
, regnum
+ 0, to
+ 4);
654 get_frame_register (frame
, regnum
+ 1, to
+ 0);
658 mips_value_to_register (struct frame_info
*frame
, int regnum
,
659 struct type
*type
, const gdb_byte
*from
)
661 put_frame_register (frame
, regnum
+ 0, from
+ 4);
662 put_frame_register (frame
, regnum
+ 1, from
+ 0);
665 /* Return the GDB type object for the "standard" data type of data in
669 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
671 gdb_assert (regnum
>= 0 && regnum
< 2 * NUM_REGS
);
672 if ((regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
673 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32)
675 /* The floating-point registers raw, or cooked, always match
676 mips_isa_regsize(), and also map 1:1, byte for byte. */
677 if (mips_isa_regsize (gdbarch
) == 4)
678 return builtin_type_ieee_single
;
680 return builtin_type_ieee_double
;
682 else if (regnum
< NUM_REGS
)
684 /* The raw or ISA registers. These are all sized according to
686 if (mips_isa_regsize (gdbarch
) == 4)
687 return builtin_type_int32
;
689 return builtin_type_int64
;
693 /* The cooked or ABI registers. These are sized according to
694 the ABI (with a few complications). */
695 if (regnum
>= (NUM_REGS
696 + mips_regnum (current_gdbarch
)->fp_control_status
)
697 && regnum
<= NUM_REGS
+ MIPS_LAST_EMBED_REGNUM
)
698 /* The pseudo/cooked view of the embedded registers is always
699 32-bit. The raw view is handled below. */
700 return builtin_type_int32
;
701 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
702 /* The target, while possibly using a 64-bit register buffer,
703 is only transfering 32-bits of each integer register.
704 Reflect this in the cooked/pseudo (ABI) register value. */
705 return builtin_type_int32
;
706 else if (mips_abi_regsize (gdbarch
) == 4)
707 /* The ABI is restricted to 32-bit registers (the ISA could be
709 return builtin_type_int32
;
712 return builtin_type_int64
;
717 /* Should the upper word of 64-bit addresses be zeroed? */
718 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
721 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
723 switch (mask_address_var
)
725 case AUTO_BOOLEAN_TRUE
:
727 case AUTO_BOOLEAN_FALSE
:
730 case AUTO_BOOLEAN_AUTO
:
731 return tdep
->default_mask_address_p
;
733 internal_error (__FILE__
, __LINE__
, _("mips_mask_address_p: bad switch"));
739 show_mask_address (struct ui_file
*file
, int from_tty
,
740 struct cmd_list_element
*c
, const char *value
)
742 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
744 deprecated_show_value_hack (file
, from_tty
, c
, value
);
745 switch (mask_address_var
)
747 case AUTO_BOOLEAN_TRUE
:
748 printf_filtered ("The 32 bit mips address mask is enabled\n");
750 case AUTO_BOOLEAN_FALSE
:
751 printf_filtered ("The 32 bit mips address mask is disabled\n");
753 case AUTO_BOOLEAN_AUTO
:
755 ("The 32 bit address mask is set automatically. Currently %s\n",
756 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
759 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
764 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
767 mips_pc_is_mips16 (CORE_ADDR memaddr
)
769 struct minimal_symbol
*sym
;
771 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
772 if (is_mips16_addr (memaddr
))
775 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
776 the high bit of the info field. Use this to decide if the function is
777 MIPS16 or normal MIPS. */
778 sym
= lookup_minimal_symbol_by_pc (memaddr
);
780 return msymbol_is_special (sym
);
785 /* MIPS believes that the PC has a sign extended value. Perhaps the
786 all registers should be sign extended for simplicity? */
789 mips_read_pc (ptid_t ptid
)
791 return read_signed_register_pid (mips_regnum (current_gdbarch
)->pc
, ptid
);
795 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
797 return frame_unwind_register_signed (next_frame
,
798 NUM_REGS
+ mips_regnum (gdbarch
)->pc
);
802 mips_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
804 return frame_unwind_register_signed (next_frame
, NUM_REGS
+ MIPS_SP_REGNUM
);
807 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
808 dummy frame. The frame ID's base needs to match the TOS value
809 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
812 static struct frame_id
813 mips_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
815 return frame_id_build (frame_unwind_register_signed (next_frame
, NUM_REGS
+ MIPS_SP_REGNUM
),
816 frame_pc_unwind (next_frame
));
820 mips_write_pc (CORE_ADDR pc
, ptid_t ptid
)
822 write_register_pid (mips_regnum (current_gdbarch
)->pc
, pc
, ptid
);
825 /* Fetch and return instruction from the specified location. If the PC
826 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
829 mips_fetch_instruction (CORE_ADDR addr
)
831 gdb_byte buf
[MIPS_INSN32_SIZE
];
835 if (mips_pc_is_mips16 (addr
))
837 instlen
= MIPS_INSN16_SIZE
;
838 addr
= unmake_mips16_addr (addr
);
841 instlen
= MIPS_INSN32_SIZE
;
842 status
= read_memory_nobpt (addr
, buf
, instlen
);
844 memory_error (status
, addr
);
845 return extract_unsigned_integer (buf
, instlen
);
848 /* These the fields of 32 bit mips instructions */
849 #define mips32_op(x) (x >> 26)
850 #define itype_op(x) (x >> 26)
851 #define itype_rs(x) ((x >> 21) & 0x1f)
852 #define itype_rt(x) ((x >> 16) & 0x1f)
853 #define itype_immediate(x) (x & 0xffff)
855 #define jtype_op(x) (x >> 26)
856 #define jtype_target(x) (x & 0x03ffffff)
858 #define rtype_op(x) (x >> 26)
859 #define rtype_rs(x) ((x >> 21) & 0x1f)
860 #define rtype_rt(x) ((x >> 16) & 0x1f)
861 #define rtype_rd(x) ((x >> 11) & 0x1f)
862 #define rtype_shamt(x) ((x >> 6) & 0x1f)
863 #define rtype_funct(x) (x & 0x3f)
866 mips32_relative_offset (ULONGEST inst
)
868 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
871 /* Determine where to set a single step breakpoint while considering
872 branch prediction. */
874 mips32_next_pc (CORE_ADDR pc
)
878 inst
= mips_fetch_instruction (pc
);
879 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
881 if (itype_op (inst
) >> 2 == 5)
882 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
884 op
= (itype_op (inst
) & 0x03);
899 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
900 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
902 int tf
= itype_rt (inst
) & 0x01;
903 int cnum
= itype_rt (inst
) >> 2;
905 read_signed_register (mips_regnum (current_gdbarch
)->
907 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
909 if (((cond
>> cnum
) & 0x01) == tf
)
910 pc
+= mips32_relative_offset (inst
) + 4;
915 pc
+= 4; /* Not a branch, next instruction is easy */
918 { /* This gets way messy */
920 /* Further subdivide into SPECIAL, REGIMM and other */
921 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
923 case 0: /* SPECIAL */
924 op
= rtype_funct (inst
);
929 /* Set PC to that address */
930 pc
= read_signed_register (rtype_rs (inst
));
936 break; /* end SPECIAL */
939 op
= itype_rt (inst
); /* branch condition */
944 case 16: /* BLTZAL */
945 case 18: /* BLTZALL */
947 if (read_signed_register (itype_rs (inst
)) < 0)
948 pc
+= mips32_relative_offset (inst
) + 4;
950 pc
+= 8; /* after the delay slot */
954 case 17: /* BGEZAL */
955 case 19: /* BGEZALL */
956 if (read_signed_register (itype_rs (inst
)) >= 0)
957 pc
+= mips32_relative_offset (inst
) + 4;
959 pc
+= 8; /* after the delay slot */
961 /* All of the other instructions in the REGIMM category */
966 break; /* end REGIMM */
971 reg
= jtype_target (inst
) << 2;
972 /* Upper four bits get never changed... */
973 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
976 /* FIXME case JALX : */
979 reg
= jtype_target (inst
) << 2;
980 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + 1; /* yes, +1 */
981 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
983 break; /* The new PC will be alternate mode */
984 case 4: /* BEQ, BEQL */
986 if (read_signed_register (itype_rs (inst
)) ==
987 read_signed_register (itype_rt (inst
)))
988 pc
+= mips32_relative_offset (inst
) + 4;
992 case 5: /* BNE, BNEL */
994 if (read_signed_register (itype_rs (inst
)) !=
995 read_signed_register (itype_rt (inst
)))
996 pc
+= mips32_relative_offset (inst
) + 4;
1000 case 6: /* BLEZ, BLEZL */
1001 if (read_signed_register (itype_rs (inst
)) <= 0)
1002 pc
+= mips32_relative_offset (inst
) + 4;
1008 greater_branch
: /* BGTZ, BGTZL */
1009 if (read_signed_register (itype_rs (inst
)) > 0)
1010 pc
+= mips32_relative_offset (inst
) + 4;
1017 } /* mips32_next_pc */
1019 /* Decoding the next place to set a breakpoint is irregular for the
1020 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1021 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1022 We dont want to set a single step instruction on the extend instruction
1026 /* Lots of mips16 instruction formats */
1027 /* Predicting jumps requires itype,ritype,i8type
1028 and their extensions extItype,extritype,extI8type
1030 enum mips16_inst_fmts
1032 itype
, /* 0 immediate 5,10 */
1033 ritype
, /* 1 5,3,8 */
1034 rrtype
, /* 2 5,3,3,5 */
1035 rritype
, /* 3 5,3,3,5 */
1036 rrrtype
, /* 4 5,3,3,3,2 */
1037 rriatype
, /* 5 5,3,3,1,4 */
1038 shifttype
, /* 6 5,3,3,3,2 */
1039 i8type
, /* 7 5,3,8 */
1040 i8movtype
, /* 8 5,3,3,5 */
1041 i8mov32rtype
, /* 9 5,3,5,3 */
1042 i64type
, /* 10 5,3,8 */
1043 ri64type
, /* 11 5,3,3,5 */
1044 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1045 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1046 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1047 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1048 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1049 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1050 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1051 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1052 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1053 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1055 /* I am heaping all the fields of the formats into one structure and
1056 then, only the fields which are involved in instruction extension */
1060 unsigned int regx
; /* Function in i8 type */
1065 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1066 for the bits which make up the immediatate extension. */
1069 extended_offset (unsigned int extension
)
1072 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1074 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1076 value
|= extension
& 0x01f; /* extract 4:0 */
1080 /* Only call this function if you know that this is an extendable
1081 instruction, It wont malfunction, but why make excess remote memory references?
1082 If the immediate operands get sign extended or somthing, do it after
1083 the extension is performed.
1085 /* FIXME: Every one of these cases needs to worry about sign extension
1086 when the offset is to be used in relative addressing */
1090 fetch_mips_16 (CORE_ADDR pc
)
1093 pc
&= 0xfffffffe; /* clear the low order bit */
1094 target_read_memory (pc
, buf
, 2);
1095 return extract_unsigned_integer (buf
, 2);
1099 unpack_mips16 (CORE_ADDR pc
,
1100 unsigned int extension
,
1102 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1107 switch (insn_format
)
1114 value
= extended_offset (extension
);
1115 value
= value
<< 11; /* rom for the original value */
1116 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1120 value
= inst
& 0x7ff;
1121 /* FIXME : Consider sign extension */
1130 { /* A register identifier and an offset */
1131 /* Most of the fields are the same as I type but the
1132 immediate value is of a different length */
1136 value
= extended_offset (extension
);
1137 value
= value
<< 8; /* from the original instruction */
1138 value
|= inst
& 0xff; /* eleven bits from instruction */
1139 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1140 if (value
& 0x4000) /* test the sign bit , bit 26 */
1142 value
&= ~0x3fff; /* remove the sign bit */
1148 value
= inst
& 0xff; /* 8 bits */
1149 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1150 /* FIXME: Do sign extension , this format needs it */
1151 if (value
& 0x80) /* THIS CONFUSES ME */
1153 value
&= 0xef; /* remove the sign bit */
1163 unsigned long value
;
1164 unsigned int nexthalf
;
1165 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1166 value
= value
<< 16;
1167 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1175 internal_error (__FILE__
, __LINE__
, _("bad switch"));
1177 upk
->offset
= offset
;
1184 add_offset_16 (CORE_ADDR pc
, int offset
)
1186 return ((offset
<< 2) | ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)));
1190 extended_mips16_next_pc (CORE_ADDR pc
,
1191 unsigned int extension
, unsigned int insn
)
1193 int op
= (insn
>> 11);
1196 case 2: /* Branch */
1199 struct upk_mips16 upk
;
1200 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1201 offset
= upk
.offset
;
1207 pc
+= (offset
<< 1) + 2;
1210 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1212 struct upk_mips16 upk
;
1213 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1214 pc
= add_offset_16 (pc
, upk
.offset
);
1215 if ((insn
>> 10) & 0x01) /* Exchange mode */
1216 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1223 struct upk_mips16 upk
;
1225 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1226 reg
= read_signed_register (upk
.regx
);
1228 pc
+= (upk
.offset
<< 1) + 2;
1235 struct upk_mips16 upk
;
1237 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1238 reg
= read_signed_register (upk
.regx
);
1240 pc
+= (upk
.offset
<< 1) + 2;
1245 case 12: /* I8 Formats btez btnez */
1247 struct upk_mips16 upk
;
1249 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1250 /* upk.regx contains the opcode */
1251 reg
= read_signed_register (24); /* Test register is 24 */
1252 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1253 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1254 /* pc = add_offset_16(pc,upk.offset) ; */
1255 pc
+= (upk
.offset
<< 1) + 2;
1260 case 29: /* RR Formats JR, JALR, JALR-RA */
1262 struct upk_mips16 upk
;
1263 /* upk.fmt = rrtype; */
1268 upk
.regx
= (insn
>> 8) & 0x07;
1269 upk
.regy
= (insn
>> 5) & 0x07;
1277 break; /* Function return instruction */
1283 break; /* BOGUS Guess */
1285 pc
= read_signed_register (reg
);
1292 /* This is an instruction extension. Fetch the real instruction
1293 (which follows the extension) and decode things based on
1297 pc
= extended_mips16_next_pc (pc
, insn
, fetch_mips_16 (pc
));
1310 mips16_next_pc (CORE_ADDR pc
)
1312 unsigned int insn
= fetch_mips_16 (pc
);
1313 return extended_mips16_next_pc (pc
, 0, insn
);
1316 /* The mips_next_pc function supports single_step when the remote
1317 target monitor or stub is not developed enough to do a single_step.
1318 It works by decoding the current instruction and predicting where a
1319 branch will go. This isnt hard because all the data is available.
1320 The MIPS32 and MIPS16 variants are quite different */
1322 mips_next_pc (CORE_ADDR pc
)
1325 return mips16_next_pc (pc
);
1327 return mips32_next_pc (pc
);
1330 struct mips_frame_cache
1333 struct trad_frame_saved_reg
*saved_regs
;
1336 /* Set a register's saved stack address in temp_saved_regs. If an
1337 address has already been set for this register, do nothing; this
1338 way we will only recognize the first save of a given register in a
1341 For simplicity, save the address in both [0 .. NUM_REGS) and
1342 [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range
1343 is used as it is only second range (the ABI instead of ISA
1344 registers) that comes into play when finding saved registers in a
1348 set_reg_offset (struct mips_frame_cache
*this_cache
, int regnum
,
1351 if (this_cache
!= NULL
1352 && this_cache
->saved_regs
[regnum
].addr
== -1)
1354 this_cache
->saved_regs
[regnum
+ 0 * NUM_REGS
].addr
= offset
;
1355 this_cache
->saved_regs
[regnum
+ 1 * NUM_REGS
].addr
= offset
;
1360 /* Fetch the immediate value from a MIPS16 instruction.
1361 If the previous instruction was an EXTEND, use it to extend
1362 the upper bits of the immediate value. This is a helper function
1363 for mips16_scan_prologue. */
1366 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1367 unsigned short inst
, /* current instruction */
1368 int nbits
, /* number of bits in imm field */
1369 int scale
, /* scale factor to be applied to imm */
1370 int is_signed
) /* is the imm field signed? */
1374 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1376 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1377 if (offset
& 0x8000) /* check for negative extend */
1378 offset
= 0 - (0x10000 - (offset
& 0xffff));
1379 return offset
| (inst
& 0x1f);
1383 int max_imm
= 1 << nbits
;
1384 int mask
= max_imm
- 1;
1385 int sign_bit
= max_imm
>> 1;
1387 offset
= inst
& mask
;
1388 if (is_signed
&& (offset
& sign_bit
))
1389 offset
= 0 - (max_imm
- offset
);
1390 return offset
* scale
;
1395 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1396 the associated FRAME_CACHE if not null.
1397 Return the address of the first instruction past the prologue. */
1400 mips16_scan_prologue (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1401 struct frame_info
*next_frame
,
1402 struct mips_frame_cache
*this_cache
)
1405 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1407 long frame_offset
= 0; /* Size of stack frame. */
1408 long frame_adjust
= 0; /* Offset of FP from SP. */
1409 int frame_reg
= MIPS_SP_REGNUM
;
1410 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1411 unsigned inst
= 0; /* current instruction */
1412 unsigned entry_inst
= 0; /* the entry instruction */
1415 int extend_bytes
= 0;
1416 int prev_extend_bytes
;
1417 CORE_ADDR end_prologue_addr
= 0;
1419 /* Can be called when there's no process, and hence when there's no
1421 if (next_frame
!= NULL
)
1422 sp
= read_next_frame_reg (next_frame
, NUM_REGS
+ MIPS_SP_REGNUM
);
1426 if (limit_pc
> start_pc
+ 200)
1427 limit_pc
= start_pc
+ 200;
1429 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
1431 /* Save the previous instruction. If it's an EXTEND, we'll extract
1432 the immediate offset extension from it in mips16_get_imm. */
1435 /* Fetch and decode the instruction. */
1436 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1438 /* Normally we ignore extend instructions. However, if it is
1439 not followed by a valid prologue instruction, then this
1440 instruction is not part of the prologue either. We must
1441 remember in this case to adjust the end_prologue_addr back
1443 if ((inst
& 0xf800) == 0xf000) /* extend */
1445 extend_bytes
= MIPS_INSN16_SIZE
;
1449 prev_extend_bytes
= extend_bytes
;
1452 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1453 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1455 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1456 if (offset
< 0) /* negative stack adjustment? */
1457 frame_offset
-= offset
;
1459 /* Exit loop if a positive stack adjustment is found, which
1460 usually means that the stack cleanup code in the function
1461 epilogue is reached. */
1464 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1466 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1467 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1468 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1470 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1472 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1473 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1474 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1476 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1478 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1479 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1481 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1483 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1484 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1486 else if (inst
== 0x673d) /* move $s1, $sp */
1491 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1493 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1494 frame_addr
= sp
+ offset
;
1496 frame_adjust
= offset
;
1498 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1500 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1501 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1502 set_reg_offset (this_cache
, reg
, frame_addr
+ offset
);
1504 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1506 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1507 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1508 set_reg_offset (this_cache
, reg
, frame_addr
+ offset
);
1510 else if ((inst
& 0xf81f) == 0xe809
1511 && (inst
& 0x700) != 0x700) /* entry */
1512 entry_inst
= inst
; /* save for later processing */
1513 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1514 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
1515 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
1517 /* This instruction is part of the prologue, but we don't
1518 need to do anything special to handle it. */
1522 /* This instruction is not an instruction typically found
1523 in a prologue, so we must have reached the end of the
1525 if (end_prologue_addr
== 0)
1526 end_prologue_addr
= cur_pc
- prev_extend_bytes
;
1530 /* The entry instruction is typically the first instruction in a function,
1531 and it stores registers at offsets relative to the value of the old SP
1532 (before the prologue). But the value of the sp parameter to this
1533 function is the new SP (after the prologue has been executed). So we
1534 can't calculate those offsets until we've seen the entire prologue,
1535 and can calculate what the old SP must have been. */
1536 if (entry_inst
!= 0)
1538 int areg_count
= (entry_inst
>> 8) & 7;
1539 int sreg_count
= (entry_inst
>> 6) & 3;
1541 /* The entry instruction always subtracts 32 from the SP. */
1544 /* Now we can calculate what the SP must have been at the
1545 start of the function prologue. */
1548 /* Check if a0-a3 were saved in the caller's argument save area. */
1549 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1551 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1552 offset
+= mips_abi_regsize (current_gdbarch
);
1555 /* Check if the ra register was pushed on the stack. */
1557 if (entry_inst
& 0x20)
1559 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1560 offset
-= mips_abi_regsize (current_gdbarch
);
1563 /* Check if the s0 and s1 registers were pushed on the stack. */
1564 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1566 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1567 offset
-= mips_abi_regsize (current_gdbarch
);
1571 if (this_cache
!= NULL
)
1574 (frame_unwind_register_signed (next_frame
, NUM_REGS
+ frame_reg
)
1575 + frame_offset
- frame_adjust
);
1576 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
1577 be able to get rid of the assignment below, evetually. But it's
1578 still needed for now. */
1579 this_cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
1580 = this_cache
->saved_regs
[NUM_REGS
+ MIPS_RA_REGNUM
];
1583 /* If we didn't reach the end of the prologue when scanning the function
1584 instructions, then set end_prologue_addr to the address of the
1585 instruction immediately after the last one we scanned. */
1586 if (end_prologue_addr
== 0)
1587 end_prologue_addr
= cur_pc
;
1589 return end_prologue_addr
;
1592 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
1593 Procedures that use the 32-bit instruction set are handled by the
1594 mips_insn32 unwinder. */
1596 static struct mips_frame_cache
*
1597 mips_insn16_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1599 struct mips_frame_cache
*cache
;
1601 if ((*this_cache
) != NULL
)
1602 return (*this_cache
);
1603 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1604 (*this_cache
) = cache
;
1605 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1607 /* Analyze the function prologue. */
1609 const CORE_ADDR pc
=
1610 frame_unwind_address_in_block (next_frame
, NORMAL_FRAME
);
1611 CORE_ADDR start_addr
;
1613 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
1614 if (start_addr
== 0)
1615 start_addr
= heuristic_proc_start (pc
);
1616 /* We can't analyze the prologue if we couldn't find the begining
1618 if (start_addr
== 0)
1621 mips16_scan_prologue (start_addr
, pc
, next_frame
, *this_cache
);
1624 /* SP_REGNUM, contains the value and not the address. */
1625 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
1627 return (*this_cache
);
1631 mips_insn16_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1632 struct frame_id
*this_id
)
1634 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1636 (*this_id
) = frame_id_build (info
->base
,
1637 frame_func_unwind (next_frame
, NORMAL_FRAME
));
1641 mips_insn16_frame_prev_register (struct frame_info
*next_frame
,
1643 int regnum
, int *optimizedp
,
1644 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1645 int *realnump
, gdb_byte
*valuep
)
1647 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1649 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
1650 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
1653 static const struct frame_unwind mips_insn16_frame_unwind
=
1656 mips_insn16_frame_this_id
,
1657 mips_insn16_frame_prev_register
1660 static const struct frame_unwind
*
1661 mips_insn16_frame_sniffer (struct frame_info
*next_frame
)
1663 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1664 if (mips_pc_is_mips16 (pc
))
1665 return &mips_insn16_frame_unwind
;
1670 mips_insn16_frame_base_address (struct frame_info
*next_frame
,
1673 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1678 static const struct frame_base mips_insn16_frame_base
=
1680 &mips_insn16_frame_unwind
,
1681 mips_insn16_frame_base_address
,
1682 mips_insn16_frame_base_address
,
1683 mips_insn16_frame_base_address
1686 static const struct frame_base
*
1687 mips_insn16_frame_base_sniffer (struct frame_info
*next_frame
)
1689 if (mips_insn16_frame_sniffer (next_frame
) != NULL
)
1690 return &mips_insn16_frame_base
;
1695 /* Mark all the registers as unset in the saved_regs array
1696 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
1699 reset_saved_regs (struct mips_frame_cache
*this_cache
)
1701 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
1705 const int num_regs
= NUM_REGS
;
1708 for (i
= 0; i
< num_regs
; i
++)
1710 this_cache
->saved_regs
[i
].addr
= -1;
1715 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1716 the associated FRAME_CACHE if not null.
1717 Return the address of the first instruction past the prologue. */
1720 mips32_scan_prologue (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1721 struct frame_info
*next_frame
,
1722 struct mips_frame_cache
*this_cache
)
1725 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
1728 int frame_reg
= MIPS_SP_REGNUM
;
1730 CORE_ADDR end_prologue_addr
= 0;
1731 int seen_sp_adjust
= 0;
1732 int load_immediate_bytes
= 0;
1734 /* Can be called when there's no process, and hence when there's no
1736 if (next_frame
!= NULL
)
1737 sp
= read_next_frame_reg (next_frame
, NUM_REGS
+ MIPS_SP_REGNUM
);
1741 if (limit_pc
> start_pc
+ 200)
1742 limit_pc
= start_pc
+ 200;
1747 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
1749 unsigned long inst
, high_word
, low_word
;
1752 /* Fetch the instruction. */
1753 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
1755 /* Save some code by pre-extracting some useful fields. */
1756 high_word
= (inst
>> 16) & 0xffff;
1757 low_word
= inst
& 0xffff;
1758 reg
= high_word
& 0x1f;
1760 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
1761 || high_word
== 0x23bd /* addi $sp,$sp,-i */
1762 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
1764 if (low_word
& 0x8000) /* negative stack adjustment? */
1765 frame_offset
+= 0x10000 - low_word
;
1767 /* Exit loop if a positive stack adjustment is found, which
1768 usually means that the stack cleanup code in the function
1769 epilogue is reached. */
1773 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1775 set_reg_offset (this_cache
, reg
, sp
+ low_word
);
1777 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1779 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
1780 set_reg_offset (this_cache
, reg
, sp
+ low_word
);
1782 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
1784 /* Old gcc frame, r30 is virtual frame pointer. */
1785 if ((long) low_word
!= frame_offset
)
1786 frame_addr
= sp
+ low_word
;
1787 else if (frame_reg
== MIPS_SP_REGNUM
)
1789 unsigned alloca_adjust
;
1792 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
1793 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
1794 if (alloca_adjust
> 0)
1796 /* FP > SP + frame_size. This may be because of
1797 an alloca or somethings similar. Fix sp to
1798 "pre-alloca" value, and try again. */
1799 sp
+= alloca_adjust
;
1800 /* Need to reset the status of all registers. Otherwise,
1801 we will hit a guard that prevents the new address
1802 for each register to be recomputed during the second
1804 reset_saved_regs (this_cache
);
1809 /* move $30,$sp. With different versions of gas this will be either
1810 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
1811 Accept any one of these. */
1812 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
1814 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
1815 if (frame_reg
== MIPS_SP_REGNUM
)
1817 unsigned alloca_adjust
;
1820 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
1821 alloca_adjust
= (unsigned) (frame_addr
- sp
);
1822 if (alloca_adjust
> 0)
1824 /* FP > SP + frame_size. This may be because of
1825 an alloca or somethings similar. Fix sp to
1826 "pre-alloca" value, and try again. */
1828 /* Need to reset the status of all registers. Otherwise,
1829 we will hit a guard that prevents the new address
1830 for each register to be recomputed during the second
1832 reset_saved_regs (this_cache
);
1837 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
1839 set_reg_offset (this_cache
, reg
, frame_addr
+ low_word
);
1841 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
1842 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
1843 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
1844 || high_word
== 0x3c1c /* lui $gp,n */
1845 || high_word
== 0x279c /* addiu $gp,$gp,n */
1846 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
1847 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
1850 /* These instructions are part of the prologue, but we don't
1851 need to do anything special to handle them. */
1853 /* The instructions below load $at or $t0 with an immediate
1854 value in preparation for a stack adjustment via
1855 subu $sp,$sp,[$at,$t0]. These instructions could also
1856 initialize a local variable, so we accept them only before
1857 a stack adjustment instruction was seen. */
1858 else if (!seen_sp_adjust
1859 && (high_word
== 0x3c01 /* lui $at,n */
1860 || high_word
== 0x3c08 /* lui $t0,n */
1861 || high_word
== 0x3421 /* ori $at,$at,n */
1862 || high_word
== 0x3508 /* ori $t0,$t0,n */
1863 || high_word
== 0x3401 /* ori $at,$zero,n */
1864 || high_word
== 0x3408 /* ori $t0,$zero,n */
1867 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
1871 /* This instruction is not an instruction typically found
1872 in a prologue, so we must have reached the end of the
1874 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
1875 loop now? Why would we need to continue scanning the function
1877 if (end_prologue_addr
== 0)
1878 end_prologue_addr
= cur_pc
;
1882 if (this_cache
!= NULL
)
1885 (frame_unwind_register_signed (next_frame
, NUM_REGS
+ frame_reg
)
1887 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
1888 this assignment below, eventually. But it's still needed
1890 this_cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
1891 = this_cache
->saved_regs
[NUM_REGS
+ MIPS_RA_REGNUM
];
1894 /* If we didn't reach the end of the prologue when scanning the function
1895 instructions, then set end_prologue_addr to the address of the
1896 instruction immediately after the last one we scanned. */
1897 /* brobecker/2004-10-10: I don't think this would ever happen, but
1898 we may as well be careful and do our best if we have a null
1899 end_prologue_addr. */
1900 if (end_prologue_addr
== 0)
1901 end_prologue_addr
= cur_pc
;
1903 /* In a frameless function, we might have incorrectly
1904 skipped some load immediate instructions. Undo the skipping
1905 if the load immediate was not followed by a stack adjustment. */
1906 if (load_immediate_bytes
&& !seen_sp_adjust
)
1907 end_prologue_addr
-= load_immediate_bytes
;
1909 return end_prologue_addr
;
1912 /* Heuristic unwinder for procedures using 32-bit instructions (covers
1913 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
1914 instructions (a.k.a. MIPS16) are handled by the mips_insn16
1917 static struct mips_frame_cache
*
1918 mips_insn32_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1920 struct mips_frame_cache
*cache
;
1922 if ((*this_cache
) != NULL
)
1923 return (*this_cache
);
1925 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1926 (*this_cache
) = cache
;
1927 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1929 /* Analyze the function prologue. */
1931 const CORE_ADDR pc
=
1932 frame_unwind_address_in_block (next_frame
, NORMAL_FRAME
);
1933 CORE_ADDR start_addr
;
1935 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
1936 if (start_addr
== 0)
1937 start_addr
= heuristic_proc_start (pc
);
1938 /* We can't analyze the prologue if we couldn't find the begining
1940 if (start_addr
== 0)
1943 mips32_scan_prologue (start_addr
, pc
, next_frame
, *this_cache
);
1946 /* SP_REGNUM, contains the value and not the address. */
1947 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
1949 return (*this_cache
);
1953 mips_insn32_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1954 struct frame_id
*this_id
)
1956 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
1958 (*this_id
) = frame_id_build (info
->base
,
1959 frame_func_unwind (next_frame
, NORMAL_FRAME
));
1963 mips_insn32_frame_prev_register (struct frame_info
*next_frame
,
1965 int regnum
, int *optimizedp
,
1966 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1967 int *realnump
, gdb_byte
*valuep
)
1969 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
1971 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
1972 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
1975 static const struct frame_unwind mips_insn32_frame_unwind
=
1978 mips_insn32_frame_this_id
,
1979 mips_insn32_frame_prev_register
1982 static const struct frame_unwind
*
1983 mips_insn32_frame_sniffer (struct frame_info
*next_frame
)
1985 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1986 if (! mips_pc_is_mips16 (pc
))
1987 return &mips_insn32_frame_unwind
;
1992 mips_insn32_frame_base_address (struct frame_info
*next_frame
,
1995 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2000 static const struct frame_base mips_insn32_frame_base
=
2002 &mips_insn32_frame_unwind
,
2003 mips_insn32_frame_base_address
,
2004 mips_insn32_frame_base_address
,
2005 mips_insn32_frame_base_address
2008 static const struct frame_base
*
2009 mips_insn32_frame_base_sniffer (struct frame_info
*next_frame
)
2011 if (mips_insn32_frame_sniffer (next_frame
) != NULL
)
2012 return &mips_insn32_frame_base
;
2017 static struct trad_frame_cache
*
2018 mips_stub_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
2021 CORE_ADDR start_addr
;
2022 CORE_ADDR stack_addr
;
2023 struct trad_frame_cache
*this_trad_cache
;
2025 if ((*this_cache
) != NULL
)
2026 return (*this_cache
);
2027 this_trad_cache
= trad_frame_cache_zalloc (next_frame
);
2028 (*this_cache
) = this_trad_cache
;
2030 /* The return address is in the link register. */
2031 trad_frame_set_reg_realreg (this_trad_cache
, PC_REGNUM
, MIPS_RA_REGNUM
);
2033 /* Frame ID, since it's a frameless / stackless function, no stack
2034 space is allocated and SP on entry is the current SP. */
2035 pc
= frame_pc_unwind (next_frame
);
2036 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2037 stack_addr
= frame_unwind_register_signed (next_frame
, MIPS_SP_REGNUM
);
2038 trad_frame_set_id (this_trad_cache
, frame_id_build (start_addr
, stack_addr
));
2040 /* Assume that the frame's base is the same as the
2042 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
2044 return this_trad_cache
;
2048 mips_stub_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2049 struct frame_id
*this_id
)
2051 struct trad_frame_cache
*this_trad_cache
2052 = mips_stub_frame_cache (next_frame
, this_cache
);
2053 trad_frame_get_id (this_trad_cache
, this_id
);
2057 mips_stub_frame_prev_register (struct frame_info
*next_frame
,
2059 int regnum
, int *optimizedp
,
2060 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2061 int *realnump
, gdb_byte
*valuep
)
2063 struct trad_frame_cache
*this_trad_cache
2064 = mips_stub_frame_cache (next_frame
, this_cache
);
2065 trad_frame_get_register (this_trad_cache
, next_frame
, regnum
, optimizedp
,
2066 lvalp
, addrp
, realnump
, valuep
);
2069 static const struct frame_unwind mips_stub_frame_unwind
=
2072 mips_stub_frame_this_id
,
2073 mips_stub_frame_prev_register
2076 static const struct frame_unwind
*
2077 mips_stub_frame_sniffer (struct frame_info
*next_frame
)
2079 struct obj_section
*s
;
2080 CORE_ADDR pc
= frame_unwind_address_in_block (next_frame
, NORMAL_FRAME
);
2082 if (in_plt_section (pc
, NULL
))
2083 return &mips_stub_frame_unwind
;
2085 /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */
2086 s
= find_pc_section (pc
);
2089 && strcmp (bfd_get_section_name (s
->objfile
->obfd
, s
->the_bfd_section
),
2090 ".MIPS.stubs") == 0)
2091 return &mips_stub_frame_unwind
;
2097 mips_stub_frame_base_address (struct frame_info
*next_frame
,
2100 struct trad_frame_cache
*this_trad_cache
2101 = mips_stub_frame_cache (next_frame
, this_cache
);
2102 return trad_frame_get_this_base (this_trad_cache
);
2105 static const struct frame_base mips_stub_frame_base
=
2107 &mips_stub_frame_unwind
,
2108 mips_stub_frame_base_address
,
2109 mips_stub_frame_base_address
,
2110 mips_stub_frame_base_address
2113 static const struct frame_base
*
2114 mips_stub_frame_base_sniffer (struct frame_info
*next_frame
)
2116 if (mips_stub_frame_sniffer (next_frame
) != NULL
)
2117 return &mips_stub_frame_base
;
2123 read_next_frame_reg (struct frame_info
*fi
, int regno
)
2125 /* Always a pseudo. */
2126 gdb_assert (regno
>= NUM_REGS
);
2130 regcache_cooked_read_signed (current_regcache
, regno
, &val
);
2134 return frame_unwind_register_signed (fi
, regno
);
2138 /* mips_addr_bits_remove - remove useless address bits */
2141 mips_addr_bits_remove (CORE_ADDR addr
)
2143 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2144 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
2145 /* This hack is a work-around for existing boards using PMON, the
2146 simulator, and any other 64-bit targets that doesn't have true
2147 64-bit addressing. On these targets, the upper 32 bits of
2148 addresses are ignored by the hardware. Thus, the PC or SP are
2149 likely to have been sign extended to all 1s by instruction
2150 sequences that load 32-bit addresses. For example, a typical
2151 piece of code that loads an address is this:
2153 lui $r2, <upper 16 bits>
2154 ori $r2, <lower 16 bits>
2156 But the lui sign-extends the value such that the upper 32 bits
2157 may be all 1s. The workaround is simply to mask off these
2158 bits. In the future, gcc may be changed to support true 64-bit
2159 addressing, and this masking will have to be disabled. */
2160 return addr
&= 0xffffffffUL
;
2165 /* mips_software_single_step() is called just before we want to resume
2166 the inferior, if we want to single-step it but there is no hardware
2167 or kernel single-step support (MIPS on GNU/Linux for example). We find
2168 the target of the coming instruction and breakpoint it. */
2171 mips_software_single_step (struct regcache
*regcache
)
2173 CORE_ADDR pc
, next_pc
;
2175 pc
= read_register (mips_regnum (current_gdbarch
)->pc
);
2176 next_pc
= mips_next_pc (pc
);
2178 insert_single_step_breakpoint (next_pc
);
2182 /* Test whether the PC points to the return instruction at the
2183 end of a function. */
2186 mips_about_to_return (CORE_ADDR pc
)
2188 if (mips_pc_is_mips16 (pc
))
2189 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2190 generates a "jr $ra"; other times it generates code to load
2191 the return address from the stack to an accessible register (such
2192 as $a3), then a "jr" using that register. This second case
2193 is almost impossible to distinguish from an indirect jump
2194 used for switch statements, so we don't even try. */
2195 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
2197 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
2201 /* This fencepost looks highly suspicious to me. Removing it also
2202 seems suspicious as it could affect remote debugging across serial
2206 heuristic_proc_start (CORE_ADDR pc
)
2213 pc
= ADDR_BITS_REMOVE (pc
);
2215 fence
= start_pc
- heuristic_fence_post
;
2219 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
2220 fence
= VM_MIN_ADDRESS
;
2222 instlen
= mips_pc_is_mips16 (pc
) ? MIPS_INSN16_SIZE
: MIPS_INSN32_SIZE
;
2224 /* search back for previous return */
2225 for (start_pc
-= instlen
;; start_pc
-= instlen
)
2226 if (start_pc
< fence
)
2228 /* It's not clear to me why we reach this point when
2229 stop_soon, but with this test, at least we
2230 don't print out warnings for every child forked (eg, on
2231 decstation). 22apr93 rich@cygnus.com. */
2232 if (stop_soon
== NO_STOP_QUIETLY
)
2234 static int blurb_printed
= 0;
2236 warning (_("GDB can't find the start of the function at 0x%s."),
2241 /* This actually happens frequently in embedded
2242 development, when you first connect to a board
2243 and your stack pointer and pc are nowhere in
2244 particular. This message needs to give people
2245 in that situation enough information to
2246 determine that it's no big deal. */
2247 printf_filtered ("\n\
2248 GDB is unable to find the start of the function at 0x%s\n\
2249 and thus can't determine the size of that function's stack frame.\n\
2250 This means that GDB may be unable to access that stack frame, or\n\
2251 the frames below it.\n\
2252 This problem is most likely caused by an invalid program counter or\n\
2254 However, if you think GDB should simply search farther back\n\
2255 from 0x%s for code which looks like the beginning of a\n\
2256 function, you can increase the range of the search using the `set\n\
2257 heuristic-fence-post' command.\n", paddr_nz (pc
), paddr_nz (pc
));
2264 else if (mips_pc_is_mips16 (start_pc
))
2266 unsigned short inst
;
2268 /* On MIPS16, any one of the following is likely to be the
2269 start of a function:
2273 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
2274 inst
= mips_fetch_instruction (start_pc
);
2275 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
2276 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
2277 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
2278 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
2280 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2281 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2286 else if (mips_about_to_return (start_pc
))
2288 /* Skip return and its delay slot. */
2289 start_pc
+= 2 * MIPS_INSN32_SIZE
;
2296 struct mips_objfile_private
2302 /* According to the current ABI, should the type be passed in a
2303 floating-point register (assuming that there is space)? When there
2304 is no FPU, FP are not even considered as possible candidates for
2305 FP registers and, consequently this returns false - forces FP
2306 arguments into integer registers. */
2309 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
2311 return ((typecode
== TYPE_CODE_FLT
2313 && (typecode
== TYPE_CODE_STRUCT
2314 || typecode
== TYPE_CODE_UNION
)
2315 && TYPE_NFIELDS (arg_type
) == 1
2316 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type
, 0)))
2318 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
2321 /* On o32, argument passing in GPRs depends on the alignment of the type being
2322 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2325 mips_type_needs_double_align (struct type
*type
)
2327 enum type_code typecode
= TYPE_CODE (type
);
2329 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2331 else if (typecode
== TYPE_CODE_STRUCT
)
2333 if (TYPE_NFIELDS (type
) < 1)
2335 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2337 else if (typecode
== TYPE_CODE_UNION
)
2341 n
= TYPE_NFIELDS (type
);
2342 for (i
= 0; i
< n
; i
++)
2343 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2350 /* Adjust the address downward (direction of stack growth) so that it
2351 is correctly aligned for a new stack frame. */
2353 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2355 return align_down (addr
, 16);
2359 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2360 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2361 int nargs
, struct value
**args
, CORE_ADDR sp
,
2362 int struct_return
, CORE_ADDR struct_addr
)
2368 int stack_offset
= 0;
2369 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2370 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
2371 int regsize
= mips_abi_regsize (gdbarch
);
2373 /* For shared libraries, "t9" needs to point at the function
2375 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
2377 /* Set the return address register to point to the entry point of
2378 the program, where a breakpoint lies in wait. */
2379 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
2381 /* First ensure that the stack and structure return address (if any)
2382 are properly aligned. The stack has to be at least 64-bit
2383 aligned even on 32-bit machines, because doubles must be 64-bit
2384 aligned. For n32 and n64, stack frames need to be 128-bit
2385 aligned, so we round to this widest known alignment. */
2387 sp
= align_down (sp
, 16);
2388 struct_addr
= align_down (struct_addr
, 16);
2390 /* Now make space on the stack for the args. We allocate more
2391 than necessary for EABI, because the first few arguments are
2392 passed in registers, but that's OK. */
2393 for (argnum
= 0; argnum
< nargs
; argnum
++)
2394 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), regsize
);
2395 sp
-= align_up (len
, 16);
2398 fprintf_unfiltered (gdb_stdlog
,
2399 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
2400 paddr_nz (sp
), (long) align_up (len
, 16));
2402 /* Initialize the integer and float register pointers. */
2403 argreg
= MIPS_A0_REGNUM
;
2404 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
2406 /* The struct_return pointer occupies the first parameter-passing reg. */
2410 fprintf_unfiltered (gdb_stdlog
,
2411 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
2412 argreg
, paddr_nz (struct_addr
));
2413 write_register (argreg
++, struct_addr
);
2416 /* Now load as many as possible of the first arguments into
2417 registers, and push the rest onto the stack. Loop thru args
2418 from first to last. */
2419 for (argnum
= 0; argnum
< nargs
; argnum
++)
2421 const gdb_byte
*val
;
2422 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
2423 struct value
*arg
= args
[argnum
];
2424 struct type
*arg_type
= check_typedef (value_type (arg
));
2425 int len
= TYPE_LENGTH (arg_type
);
2426 enum type_code typecode
= TYPE_CODE (arg_type
);
2429 fprintf_unfiltered (gdb_stdlog
,
2430 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2431 argnum
+ 1, len
, (int) typecode
);
2433 /* The EABI passes structures that do not fit in a register by
2436 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2438 store_unsigned_integer (valbuf
, regsize
, VALUE_ADDRESS (arg
));
2439 typecode
= TYPE_CODE_PTR
;
2443 fprintf_unfiltered (gdb_stdlog
, " push");
2446 val
= value_contents (arg
);
2448 /* 32-bit ABIs always start floating point arguments in an
2449 even-numbered floating point register. Round the FP register
2450 up before the check to see if there are any FP registers
2451 left. Non MIPS_EABI targets also pass the FP in the integer
2452 registers so also round up normal registers. */
2453 if (regsize
< 8 && fp_register_arg_p (typecode
, arg_type
))
2455 if ((float_argreg
& 1))
2459 /* Floating point arguments passed in registers have to be
2460 treated specially. On 32-bit architectures, doubles
2461 are passed in register pairs; the even register gets
2462 the low word, and the odd register gets the high word.
2463 On non-EABI processors, the first two floating point arguments are
2464 also copied to general registers, because MIPS16 functions
2465 don't use float registers for arguments. This duplication of
2466 arguments in general registers can't hurt non-MIPS16 functions
2467 because those registers are normally skipped. */
2468 /* MIPS_EABI squeezes a struct that contains a single floating
2469 point value into an FP register instead of pushing it onto the
2471 if (fp_register_arg_p (typecode
, arg_type
)
2472 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2474 /* EABI32 will pass doubles in consecutive registers, even on
2475 64-bit cores. At one time, we used to check the size of
2476 `float_argreg' to determine whether or not to pass doubles
2477 in consecutive registers, but this is not sufficient for
2478 making the ABI determination. */
2479 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
2481 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
2482 unsigned long regval
;
2484 /* Write the low word of the double to the even register(s). */
2485 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2487 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2488 float_argreg
, phex (regval
, 4));
2489 write_register (float_argreg
++, regval
);
2491 /* Write the high word of the double to the odd register(s). */
2492 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2494 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2495 float_argreg
, phex (regval
, 4));
2496 write_register (float_argreg
++, regval
);
2500 /* This is a floating point value that fits entirely
2501 in a single register. */
2502 /* On 32 bit ABI's the float_argreg is further adjusted
2503 above to ensure that it is even register aligned. */
2504 LONGEST regval
= extract_unsigned_integer (val
, len
);
2506 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2507 float_argreg
, phex (regval
, len
));
2508 write_register (float_argreg
++, regval
);
2513 /* Copy the argument to general registers or the stack in
2514 register-sized pieces. Large arguments are split between
2515 registers and stack. */
2516 /* Note: structs whose size is not a multiple of regsize
2517 are treated specially: Irix cc passes
2518 them in registers where gcc sometimes puts them on the
2519 stack. For maximum compatibility, we will put them in
2521 int odd_sized_struct
= (len
> regsize
&& len
% regsize
!= 0);
2523 /* Note: Floating-point values that didn't fit into an FP
2524 register are only written to memory. */
2527 /* Remember if the argument was written to the stack. */
2528 int stack_used_p
= 0;
2529 int partial_len
= (len
< regsize
? len
: regsize
);
2532 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2535 /* Write this portion of the argument to the stack. */
2536 if (argreg
> MIPS_LAST_ARG_REGNUM
2538 || fp_register_arg_p (typecode
, arg_type
))
2540 /* Should shorter than int integer values be
2541 promoted to int before being stored? */
2542 int longword_offset
= 0;
2545 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2548 && (typecode
== TYPE_CODE_INT
2549 || typecode
== TYPE_CODE_PTR
2550 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
2551 longword_offset
= regsize
- len
;
2552 else if ((typecode
== TYPE_CODE_STRUCT
2553 || typecode
== TYPE_CODE_UNION
)
2554 && TYPE_LENGTH (arg_type
) < regsize
)
2555 longword_offset
= regsize
- len
;
2560 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
2561 paddr_nz (stack_offset
));
2562 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
2563 paddr_nz (longword_offset
));
2566 addr
= sp
+ stack_offset
+ longword_offset
;
2571 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
2573 for (i
= 0; i
< partial_len
; i
++)
2575 fprintf_unfiltered (gdb_stdlog
, "%02x",
2579 write_memory (addr
, val
, partial_len
);
2582 /* Note!!! This is NOT an else clause. Odd sized
2583 structs may go thru BOTH paths. Floating point
2584 arguments will not. */
2585 /* Write this portion of the argument to a general
2586 purpose register. */
2587 if (argreg
<= MIPS_LAST_ARG_REGNUM
2588 && !fp_register_arg_p (typecode
, arg_type
))
2591 extract_unsigned_integer (val
, partial_len
);
2594 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2596 phex (regval
, regsize
));
2597 write_register (argreg
, regval
);
2604 /* Compute the the offset into the stack at which we
2605 will copy the next parameter.
2607 In the new EABI (and the NABI32), the stack_offset
2608 only needs to be adjusted when it has been used. */
2611 stack_offset
+= align_up (partial_len
, regsize
);
2615 fprintf_unfiltered (gdb_stdlog
, "\n");
2618 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
2620 /* Return adjusted stack pointer. */
2624 /* Determine the return value convention being used. */
2626 static enum return_value_convention
2627 mips_eabi_return_value (struct gdbarch
*gdbarch
,
2628 struct type
*type
, struct regcache
*regcache
,
2629 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2631 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
2632 return RETURN_VALUE_STRUCT_CONVENTION
;
2634 memset (readbuf
, 0, TYPE_LENGTH (type
));
2635 return RETURN_VALUE_REGISTER_CONVENTION
;
2639 /* N32/N64 ABI stuff. */
2642 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2643 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2644 int nargs
, struct value
**args
, CORE_ADDR sp
,
2645 int struct_return
, CORE_ADDR struct_addr
)
2651 int stack_offset
= 0;
2652 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2653 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
2655 /* For shared libraries, "t9" needs to point at the function
2657 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
2659 /* Set the return address register to point to the entry point of
2660 the program, where a breakpoint lies in wait. */
2661 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
2663 /* First ensure that the stack and structure return address (if any)
2664 are properly aligned. The stack has to be at least 64-bit
2665 aligned even on 32-bit machines, because doubles must be 64-bit
2666 aligned. For n32 and n64, stack frames need to be 128-bit
2667 aligned, so we round to this widest known alignment. */
2669 sp
= align_down (sp
, 16);
2670 struct_addr
= align_down (struct_addr
, 16);
2672 /* Now make space on the stack for the args. */
2673 for (argnum
= 0; argnum
< nargs
; argnum
++)
2674 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), MIPS64_REGSIZE
);
2675 sp
-= align_up (len
, 16);
2678 fprintf_unfiltered (gdb_stdlog
,
2679 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
2680 paddr_nz (sp
), (long) align_up (len
, 16));
2682 /* Initialize the integer and float register pointers. */
2683 argreg
= MIPS_A0_REGNUM
;
2684 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
2686 /* The struct_return pointer occupies the first parameter-passing reg. */
2690 fprintf_unfiltered (gdb_stdlog
,
2691 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
2692 argreg
, paddr_nz (struct_addr
));
2693 write_register (argreg
++, struct_addr
);
2696 /* Now load as many as possible of the first arguments into
2697 registers, and push the rest onto the stack. Loop thru args
2698 from first to last. */
2699 for (argnum
= 0; argnum
< nargs
; argnum
++)
2701 const gdb_byte
*val
;
2702 struct value
*arg
= args
[argnum
];
2703 struct type
*arg_type
= check_typedef (value_type (arg
));
2704 int len
= TYPE_LENGTH (arg_type
);
2705 enum type_code typecode
= TYPE_CODE (arg_type
);
2708 fprintf_unfiltered (gdb_stdlog
,
2709 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
2710 argnum
+ 1, len
, (int) typecode
);
2712 val
= value_contents (arg
);
2714 if (fp_register_arg_p (typecode
, arg_type
)
2715 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2717 /* This is a floating point value that fits entirely
2718 in a single register. */
2719 /* On 32 bit ABI's the float_argreg is further adjusted
2720 above to ensure that it is even register aligned. */
2721 LONGEST regval
= extract_unsigned_integer (val
, len
);
2723 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2724 float_argreg
, phex (regval
, len
));
2725 write_register (float_argreg
++, regval
);
2728 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
2729 argreg
, phex (regval
, len
));
2730 write_register (argreg
, regval
);
2735 /* Copy the argument to general registers or the stack in
2736 register-sized pieces. Large arguments are split between
2737 registers and stack. */
2738 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
2739 are treated specially: Irix cc passes them in registers
2740 where gcc sometimes puts them on the stack. For maximum
2741 compatibility, we will put them in both places. */
2742 int odd_sized_struct
= (len
> MIPS64_REGSIZE
2743 && len
% MIPS64_REGSIZE
!= 0);
2744 /* Note: Floating-point values that didn't fit into an FP
2745 register are only written to memory. */
2748 /* Remember if the argument was written to the stack. */
2749 int stack_used_p
= 0;
2750 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
2753 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2756 /* Write this portion of the argument to the stack. */
2757 if (argreg
> MIPS_LAST_ARG_REGNUM
2759 || fp_register_arg_p (typecode
, arg_type
))
2761 /* Should shorter than int integer values be
2762 promoted to int before being stored? */
2763 int longword_offset
= 0;
2766 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2768 if ((typecode
== TYPE_CODE_INT
2769 || typecode
== TYPE_CODE_PTR
2770 || typecode
== TYPE_CODE_FLT
)
2772 longword_offset
= MIPS64_REGSIZE
- len
;
2777 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
2778 paddr_nz (stack_offset
));
2779 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
2780 paddr_nz (longword_offset
));
2783 addr
= sp
+ stack_offset
+ longword_offset
;
2788 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
2790 for (i
= 0; i
< partial_len
; i
++)
2792 fprintf_unfiltered (gdb_stdlog
, "%02x",
2796 write_memory (addr
, val
, partial_len
);
2799 /* Note!!! This is NOT an else clause. Odd sized
2800 structs may go thru BOTH paths. Floating point
2801 arguments will not. */
2802 /* Write this portion of the argument to a general
2803 purpose register. */
2804 if (argreg
<= MIPS_LAST_ARG_REGNUM
2805 && !fp_register_arg_p (typecode
, arg_type
))
2808 extract_unsigned_integer (val
, partial_len
);
2810 /* A non-floating-point argument being passed in a
2811 general register. If a struct or union, and if
2812 the remaining length is smaller than the register
2813 size, we have to adjust the register value on
2816 It does not seem to be necessary to do the
2817 same for integral types. */
2819 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
2820 && partial_len
< MIPS64_REGSIZE
2821 && (typecode
== TYPE_CODE_STRUCT
2822 || typecode
== TYPE_CODE_UNION
))
2823 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
2827 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2829 phex (regval
, MIPS64_REGSIZE
));
2830 write_register (argreg
, regval
);
2837 /* Compute the the offset into the stack at which we
2838 will copy the next parameter.
2840 In N32 (N64?), the stack_offset only needs to be
2841 adjusted when it has been used. */
2844 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
2848 fprintf_unfiltered (gdb_stdlog
, "\n");
2851 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
2853 /* Return adjusted stack pointer. */
2857 static enum return_value_convention
2858 mips_n32n64_return_value (struct gdbarch
*gdbarch
,
2859 struct type
*type
, struct regcache
*regcache
,
2860 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2862 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2863 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
2864 || TYPE_CODE (type
) == TYPE_CODE_UNION
2865 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
2866 || TYPE_LENGTH (type
) > 2 * MIPS64_REGSIZE
)
2867 return RETURN_VALUE_STRUCT_CONVENTION
;
2868 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
2869 && TYPE_LENGTH (type
) == 16
2870 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
2872 /* A 128-bit floating-point value fills both $f0 and $f2. The
2873 two registers are used in the same as memory order, so the
2874 eight bytes with the lower memory address are in $f0. */
2876 fprintf_unfiltered (gdb_stderr
, "Return float in $f0 and $f2\n");
2877 mips_xfer_register (regcache
,
2878 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
2879 8, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
2880 mips_xfer_register (regcache
,
2881 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ 2,
2882 8, TARGET_BYTE_ORDER
, readbuf
? readbuf
+ 8 : readbuf
,
2883 writebuf
? writebuf
+ 8 : writebuf
, 0);
2884 return RETURN_VALUE_REGISTER_CONVENTION
;
2886 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
2887 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
2889 /* A floating-point value belongs in the least significant part
2892 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
2893 mips_xfer_register (regcache
,
2894 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
2896 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
2897 return RETURN_VALUE_REGISTER_CONVENTION
;
2899 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
2900 && TYPE_NFIELDS (type
) <= 2
2901 && TYPE_NFIELDS (type
) >= 1
2902 && ((TYPE_NFIELDS (type
) == 1
2903 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
2905 || (TYPE_NFIELDS (type
) == 2
2906 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
2908 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
2910 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
2912 /* A struct that contains one or two floats. Each value is part
2913 in the least significant part of their floating point
2917 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
2918 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
2920 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
2923 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
2925 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
2926 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
2927 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
2929 return RETURN_VALUE_REGISTER_CONVENTION
;
2931 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
2932 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
2934 /* A structure or union. Extract the left justified value,
2935 regardless of the byte order. I.e. DO NOT USE
2939 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
2940 offset
< TYPE_LENGTH (type
);
2941 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
2943 int xfer
= register_size (current_gdbarch
, regnum
);
2944 if (offset
+ xfer
> TYPE_LENGTH (type
))
2945 xfer
= TYPE_LENGTH (type
) - offset
;
2947 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
2948 offset
, xfer
, regnum
);
2949 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
2950 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
2952 return RETURN_VALUE_REGISTER_CONVENTION
;
2956 /* A scalar extract each part but least-significant-byte
2960 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
2961 offset
< TYPE_LENGTH (type
);
2962 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
2964 int xfer
= register_size (current_gdbarch
, regnum
);
2965 if (offset
+ xfer
> TYPE_LENGTH (type
))
2966 xfer
= TYPE_LENGTH (type
) - offset
;
2968 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
2969 offset
, xfer
, regnum
);
2970 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
2971 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
2973 return RETURN_VALUE_REGISTER_CONVENTION
;
2977 /* O32 ABI stuff. */
2980 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2981 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2982 int nargs
, struct value
**args
, CORE_ADDR sp
,
2983 int struct_return
, CORE_ADDR struct_addr
)
2989 int stack_offset
= 0;
2990 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2991 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
2993 /* For shared libraries, "t9" needs to point at the function
2995 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
2997 /* Set the return address register to point to the entry point of
2998 the program, where a breakpoint lies in wait. */
2999 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3001 /* First ensure that the stack and structure return address (if any)
3002 are properly aligned. The stack has to be at least 64-bit
3003 aligned even on 32-bit machines, because doubles must be 64-bit
3004 aligned. For n32 and n64, stack frames need to be 128-bit
3005 aligned, so we round to this widest known alignment. */
3007 sp
= align_down (sp
, 16);
3008 struct_addr
= align_down (struct_addr
, 16);
3010 /* Now make space on the stack for the args. */
3011 for (argnum
= 0; argnum
< nargs
; argnum
++)
3013 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
3014 int arglen
= TYPE_LENGTH (arg_type
);
3016 /* Align to double-word if necessary. */
3017 if (mips_type_needs_double_align (arg_type
))
3018 len
= align_up (len
, MIPS32_REGSIZE
* 2);
3019 /* Allocate space on the stack. */
3020 len
+= align_up (arglen
, MIPS32_REGSIZE
);
3022 sp
-= align_up (len
, 16);
3025 fprintf_unfiltered (gdb_stdlog
,
3026 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
3027 paddr_nz (sp
), (long) align_up (len
, 16));
3029 /* Initialize the integer and float register pointers. */
3030 argreg
= MIPS_A0_REGNUM
;
3031 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3033 /* The struct_return pointer occupies the first parameter-passing reg. */
3037 fprintf_unfiltered (gdb_stdlog
,
3038 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
3039 argreg
, paddr_nz (struct_addr
));
3040 write_register (argreg
++, struct_addr
);
3041 stack_offset
+= MIPS32_REGSIZE
;
3044 /* Now load as many as possible of the first arguments into
3045 registers, and push the rest onto the stack. Loop thru args
3046 from first to last. */
3047 for (argnum
= 0; argnum
< nargs
; argnum
++)
3049 const gdb_byte
*val
;
3050 struct value
*arg
= args
[argnum
];
3051 struct type
*arg_type
= check_typedef (value_type (arg
));
3052 int len
= TYPE_LENGTH (arg_type
);
3053 enum type_code typecode
= TYPE_CODE (arg_type
);
3056 fprintf_unfiltered (gdb_stdlog
,
3057 "mips_o32_push_dummy_call: %d len=%d type=%d",
3058 argnum
+ 1, len
, (int) typecode
);
3060 val
= value_contents (arg
);
3062 /* 32-bit ABIs always start floating point arguments in an
3063 even-numbered floating point register. Round the FP register
3064 up before the check to see if there are any FP registers
3065 left. O32/O64 targets also pass the FP in the integer
3066 registers so also round up normal registers. */
3067 if (fp_register_arg_p (typecode
, arg_type
))
3069 if ((float_argreg
& 1))
3073 /* Floating point arguments passed in registers have to be
3074 treated specially. On 32-bit architectures, doubles
3075 are passed in register pairs; the even register gets
3076 the low word, and the odd register gets the high word.
3077 On O32/O64, the first two floating point arguments are
3078 also copied to general registers, because MIPS16 functions
3079 don't use float registers for arguments. This duplication of
3080 arguments in general registers can't hurt non-MIPS16 functions
3081 because those registers are normally skipped. */
3083 if (fp_register_arg_p (typecode
, arg_type
)
3084 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3086 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
3088 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3089 unsigned long regval
;
3091 /* Write the low word of the double to the even register(s). */
3092 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3094 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3095 float_argreg
, phex (regval
, 4));
3096 write_register (float_argreg
++, regval
);
3098 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3099 argreg
, phex (regval
, 4));
3100 write_register (argreg
++, regval
);
3102 /* Write the high word of the double to the odd register(s). */
3103 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3105 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3106 float_argreg
, phex (regval
, 4));
3107 write_register (float_argreg
++, regval
);
3110 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3111 argreg
, phex (regval
, 4));
3112 write_register (argreg
++, regval
);
3116 /* This is a floating point value that fits entirely
3117 in a single register. */
3118 /* On 32 bit ABI's the float_argreg is further adjusted
3119 above to ensure that it is even register aligned. */
3120 LONGEST regval
= extract_unsigned_integer (val
, len
);
3122 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3123 float_argreg
, phex (regval
, len
));
3124 write_register (float_argreg
++, regval
);
3125 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3126 registers for each argument. The below is (my
3127 guess) to ensure that the corresponding integer
3128 register has reserved the same space. */
3130 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3131 argreg
, phex (regval
, len
));
3132 write_register (argreg
, regval
);
3135 /* Reserve space for the FP register. */
3136 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
3140 /* Copy the argument to general registers or the stack in
3141 register-sized pieces. Large arguments are split between
3142 registers and stack. */
3143 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
3144 are treated specially: Irix cc passes
3145 them in registers where gcc sometimes puts them on the
3146 stack. For maximum compatibility, we will put them in
3148 int odd_sized_struct
= (len
> MIPS32_REGSIZE
3149 && len
% MIPS32_REGSIZE
!= 0);
3150 /* Structures should be aligned to eight bytes (even arg registers)
3151 on MIPS_ABI_O32, if their first member has double precision. */
3152 if (mips_type_needs_double_align (arg_type
))
3157 stack_offset
+= MIPS32_REGSIZE
;
3162 /* Remember if the argument was written to the stack. */
3163 int stack_used_p
= 0;
3164 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
3167 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3170 /* Write this portion of the argument to the stack. */
3171 if (argreg
> MIPS_LAST_ARG_REGNUM
3172 || odd_sized_struct
)
3174 /* Should shorter than int integer values be
3175 promoted to int before being stored? */
3176 int longword_offset
= 0;
3182 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3183 paddr_nz (stack_offset
));
3184 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3185 paddr_nz (longword_offset
));
3188 addr
= sp
+ stack_offset
+ longword_offset
;
3193 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3195 for (i
= 0; i
< partial_len
; i
++)
3197 fprintf_unfiltered (gdb_stdlog
, "%02x",
3201 write_memory (addr
, val
, partial_len
);
3204 /* Note!!! This is NOT an else clause. Odd sized
3205 structs may go thru BOTH paths. */
3206 /* Write this portion of the argument to a general
3207 purpose register. */
3208 if (argreg
<= MIPS_LAST_ARG_REGNUM
)
3210 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3211 /* Value may need to be sign extended, because
3212 mips_isa_regsize() != mips_abi_regsize(). */
3214 /* A non-floating-point argument being passed in a
3215 general register. If a struct or union, and if
3216 the remaining length is smaller than the register
3217 size, we have to adjust the register value on
3220 It does not seem to be necessary to do the
3221 same for integral types.
3223 Also don't do this adjustment on O64 binaries.
3225 cagney/2001-07-23: gdb/179: Also, GCC, when
3226 outputting LE O32 with sizeof (struct) <
3227 mips_abi_regsize(), generates a left shift
3228 as part of storing the argument in a register
3229 (the left shift isn't generated when
3230 sizeof (struct) >= mips_abi_regsize()). Since
3231 it is quite possible that this is GCC
3232 contradicting the LE/O32 ABI, GDB has not been
3233 adjusted to accommodate this. Either someone
3234 needs to demonstrate that the LE/O32 ABI
3235 specifies such a left shift OR this new ABI gets
3236 identified as such and GDB gets tweaked
3239 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3240 && partial_len
< MIPS32_REGSIZE
3241 && (typecode
== TYPE_CODE_STRUCT
3242 || typecode
== TYPE_CODE_UNION
))
3243 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
3247 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3249 phex (regval
, MIPS32_REGSIZE
));
3250 write_register (argreg
, regval
);
3253 /* Prevent subsequent floating point arguments from
3254 being passed in floating point registers. */
3255 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3261 /* Compute the the offset into the stack at which we
3262 will copy the next parameter.
3264 In older ABIs, the caller reserved space for
3265 registers that contained arguments. This was loosely
3266 refered to as their "home". Consequently, space is
3267 always allocated. */
3269 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
3273 fprintf_unfiltered (gdb_stdlog
, "\n");
3276 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3278 /* Return adjusted stack pointer. */
3282 static enum return_value_convention
3283 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
3284 struct regcache
*regcache
,
3285 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3287 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3289 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3290 || TYPE_CODE (type
) == TYPE_CODE_UNION
3291 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3292 return RETURN_VALUE_STRUCT_CONVENTION
;
3293 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3294 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3296 /* A single-precision floating-point value. It fits in the
3297 least significant part of FP0. */
3299 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3300 mips_xfer_register (regcache
,
3301 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
3303 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3304 return RETURN_VALUE_REGISTER_CONVENTION
;
3306 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3307 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3309 /* A double-precision floating-point value. The most
3310 significant part goes in FP1, and the least significant in
3313 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
3314 switch (TARGET_BYTE_ORDER
)
3316 case BFD_ENDIAN_LITTLE
:
3317 mips_xfer_register (regcache
,
3318 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3319 0, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3320 mips_xfer_register (regcache
,
3321 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3322 1, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
3324 case BFD_ENDIAN_BIG
:
3325 mips_xfer_register (regcache
,
3326 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3327 1, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3328 mips_xfer_register (regcache
,
3329 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3330 0, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
3333 internal_error (__FILE__
, __LINE__
, _("bad switch"));
3335 return RETURN_VALUE_REGISTER_CONVENTION
;
3338 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3339 && TYPE_NFIELDS (type
) <= 2
3340 && TYPE_NFIELDS (type
) >= 1
3341 && ((TYPE_NFIELDS (type
) == 1
3342 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3344 || (TYPE_NFIELDS (type
) == 2
3345 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3347 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
3349 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3351 /* A struct that contains one or two floats. Each value is part
3352 in the least significant part of their floating point
3354 gdb_byte reg
[MAX_REGISTER_SIZE
];
3357 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
3358 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3360 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3363 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3365 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
3366 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3367 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3369 return RETURN_VALUE_REGISTER_CONVENTION
;
3373 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3374 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3376 /* A structure or union. Extract the left justified value,
3377 regardless of the byte order. I.e. DO NOT USE
3381 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3382 offset
< TYPE_LENGTH (type
);
3383 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3385 int xfer
= register_size (current_gdbarch
, regnum
);
3386 if (offset
+ xfer
> TYPE_LENGTH (type
))
3387 xfer
= TYPE_LENGTH (type
) - offset
;
3389 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3390 offset
, xfer
, regnum
);
3391 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3392 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
3394 return RETURN_VALUE_REGISTER_CONVENTION
;
3399 /* A scalar extract each part but least-significant-byte
3400 justified. o32 thinks registers are 4 byte, regardless of
3404 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3405 offset
< TYPE_LENGTH (type
);
3406 offset
+= MIPS32_REGSIZE
, regnum
++)
3408 int xfer
= MIPS32_REGSIZE
;
3409 if (offset
+ xfer
> TYPE_LENGTH (type
))
3410 xfer
= TYPE_LENGTH (type
) - offset
;
3412 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3413 offset
, xfer
, regnum
);
3414 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3415 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3417 return RETURN_VALUE_REGISTER_CONVENTION
;
3421 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
3425 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3426 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3428 struct value
**args
, CORE_ADDR sp
,
3429 int struct_return
, CORE_ADDR struct_addr
)
3435 int stack_offset
= 0;
3436 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3437 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3439 /* For shared libraries, "t9" needs to point at the function
3441 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3443 /* Set the return address register to point to the entry point of
3444 the program, where a breakpoint lies in wait. */
3445 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3447 /* First ensure that the stack and structure return address (if any)
3448 are properly aligned. The stack has to be at least 64-bit
3449 aligned even on 32-bit machines, because doubles must be 64-bit
3450 aligned. For n32 and n64, stack frames need to be 128-bit
3451 aligned, so we round to this widest known alignment. */
3453 sp
= align_down (sp
, 16);
3454 struct_addr
= align_down (struct_addr
, 16);
3456 /* Now make space on the stack for the args. */
3457 for (argnum
= 0; argnum
< nargs
; argnum
++)
3459 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
3460 int arglen
= TYPE_LENGTH (arg_type
);
3462 /* Allocate space on the stack. */
3463 len
+= align_up (arglen
, MIPS64_REGSIZE
);
3465 sp
-= align_up (len
, 16);
3468 fprintf_unfiltered (gdb_stdlog
,
3469 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
3470 paddr_nz (sp
), (long) align_up (len
, 16));
3472 /* Initialize the integer and float register pointers. */
3473 argreg
= MIPS_A0_REGNUM
;
3474 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3476 /* The struct_return pointer occupies the first parameter-passing reg. */
3480 fprintf_unfiltered (gdb_stdlog
,
3481 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
3482 argreg
, paddr_nz (struct_addr
));
3483 write_register (argreg
++, struct_addr
);
3484 stack_offset
+= MIPS64_REGSIZE
;
3487 /* Now load as many as possible of the first arguments into
3488 registers, and push the rest onto the stack. Loop thru args
3489 from first to last. */
3490 for (argnum
= 0; argnum
< nargs
; argnum
++)
3492 const gdb_byte
*val
;
3493 struct value
*arg
= args
[argnum
];
3494 struct type
*arg_type
= check_typedef (value_type (arg
));
3495 int len
= TYPE_LENGTH (arg_type
);
3496 enum type_code typecode
= TYPE_CODE (arg_type
);
3499 fprintf_unfiltered (gdb_stdlog
,
3500 "mips_o64_push_dummy_call: %d len=%d type=%d",
3501 argnum
+ 1, len
, (int) typecode
);
3503 val
= value_contents (arg
);
3505 /* Floating point arguments passed in registers have to be
3506 treated specially. On 32-bit architectures, doubles
3507 are passed in register pairs; the even register gets
3508 the low word, and the odd register gets the high word.
3509 On O32/O64, the first two floating point arguments are
3510 also copied to general registers, because MIPS16 functions
3511 don't use float registers for arguments. This duplication of
3512 arguments in general registers can't hurt non-MIPS16 functions
3513 because those registers are normally skipped. */
3515 if (fp_register_arg_p (typecode
, arg_type
)
3516 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3518 LONGEST regval
= extract_unsigned_integer (val
, len
);
3520 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3521 float_argreg
, phex (regval
, len
));
3522 write_register (float_argreg
++, regval
);
3524 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3525 argreg
, phex (regval
, len
));
3526 write_register (argreg
, regval
);
3528 /* Reserve space for the FP register. */
3529 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
3533 /* Copy the argument to general registers or the stack in
3534 register-sized pieces. Large arguments are split between
3535 registers and stack. */
3536 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
3537 are treated specially: Irix cc passes them in registers
3538 where gcc sometimes puts them on the stack. For maximum
3539 compatibility, we will put them in both places. */
3540 int odd_sized_struct
= (len
> MIPS64_REGSIZE
3541 && len
% MIPS64_REGSIZE
!= 0);
3544 /* Remember if the argument was written to the stack. */
3545 int stack_used_p
= 0;
3546 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
3549 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3552 /* Write this portion of the argument to the stack. */
3553 if (argreg
> MIPS_LAST_ARG_REGNUM
3554 || odd_sized_struct
)
3556 /* Should shorter than int integer values be
3557 promoted to int before being stored? */
3558 int longword_offset
= 0;
3561 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3563 if ((typecode
== TYPE_CODE_INT
3564 || typecode
== TYPE_CODE_PTR
3565 || typecode
== TYPE_CODE_FLT
)
3567 longword_offset
= MIPS64_REGSIZE
- len
;
3572 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3573 paddr_nz (stack_offset
));
3574 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3575 paddr_nz (longword_offset
));
3578 addr
= sp
+ stack_offset
+ longword_offset
;
3583 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3585 for (i
= 0; i
< partial_len
; i
++)
3587 fprintf_unfiltered (gdb_stdlog
, "%02x",
3591 write_memory (addr
, val
, partial_len
);
3594 /* Note!!! This is NOT an else clause. Odd sized
3595 structs may go thru BOTH paths. */
3596 /* Write this portion of the argument to a general
3597 purpose register. */
3598 if (argreg
<= MIPS_LAST_ARG_REGNUM
)
3600 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3601 /* Value may need to be sign extended, because
3602 mips_isa_regsize() != mips_abi_regsize(). */
3604 /* A non-floating-point argument being passed in a
3605 general register. If a struct or union, and if
3606 the remaining length is smaller than the register
3607 size, we have to adjust the register value on
3610 It does not seem to be necessary to do the
3611 same for integral types. */
3613 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3614 && partial_len
< MIPS64_REGSIZE
3615 && (typecode
== TYPE_CODE_STRUCT
3616 || typecode
== TYPE_CODE_UNION
))
3617 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
3621 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3623 phex (regval
, MIPS64_REGSIZE
));
3624 write_register (argreg
, regval
);
3627 /* Prevent subsequent floating point arguments from
3628 being passed in floating point registers. */
3629 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3635 /* Compute the the offset into the stack at which we
3636 will copy the next parameter.
3638 In older ABIs, the caller reserved space for
3639 registers that contained arguments. This was loosely
3640 refered to as their "home". Consequently, space is
3641 always allocated. */
3643 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
3647 fprintf_unfiltered (gdb_stdlog
, "\n");
3650 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3652 /* Return adjusted stack pointer. */
3656 static enum return_value_convention
3657 mips_o64_return_value (struct gdbarch
*gdbarch
,
3658 struct type
*type
, struct regcache
*regcache
,
3659 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3661 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3663 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3664 || TYPE_CODE (type
) == TYPE_CODE_UNION
3665 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3666 return RETURN_VALUE_STRUCT_CONVENTION
;
3667 else if (fp_register_arg_p (TYPE_CODE (type
), type
))
3669 /* A floating-point value. It fits in the least significant
3672 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3673 mips_xfer_register (regcache
,
3674 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
3676 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3677 return RETURN_VALUE_REGISTER_CONVENTION
;
3681 /* A scalar extract each part but least-significant-byte
3685 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3686 offset
< TYPE_LENGTH (type
);
3687 offset
+= MIPS64_REGSIZE
, regnum
++)
3689 int xfer
= MIPS64_REGSIZE
;
3690 if (offset
+ xfer
> TYPE_LENGTH (type
))
3691 xfer
= TYPE_LENGTH (type
) - offset
;
3693 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3694 offset
, xfer
, regnum
);
3695 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3696 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3698 return RETURN_VALUE_REGISTER_CONVENTION
;
3702 /* Floating point register management.
3704 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
3705 64bit operations, these early MIPS cpus treat fp register pairs
3706 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
3707 registers and offer a compatibility mode that emulates the MIPS2 fp
3708 model. When operating in MIPS2 fp compat mode, later cpu's split
3709 double precision floats into two 32-bit chunks and store them in
3710 consecutive fp regs. To display 64-bit floats stored in this
3711 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
3712 Throw in user-configurable endianness and you have a real mess.
3714 The way this works is:
3715 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
3716 double-precision value will be split across two logical registers.
3717 The lower-numbered logical register will hold the low-order bits,
3718 regardless of the processor's endianness.
3719 - If we are on a 64-bit processor, and we are looking for a
3720 single-precision value, it will be in the low ordered bits
3721 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
3722 save slot in memory.
3723 - If we are in 64-bit mode, everything is straightforward.
3725 Note that this code only deals with "live" registers at the top of the
3726 stack. We will attempt to deal with saved registers later, when
3727 the raw/cooked register interface is in place. (We need a general
3728 interface that can deal with dynamic saved register sizes -- fp
3729 regs could be 32 bits wide in one frame and 64 on the frame above
3732 static struct type
*
3733 mips_float_register_type (void)
3735 return builtin_type_ieee_single
;
3738 static struct type
*
3739 mips_double_register_type (void)
3741 return builtin_type_ieee_double
;
3744 /* Copy a 32-bit single-precision value from the current frame
3745 into rare_buffer. */
3748 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
3749 gdb_byte
*rare_buffer
)
3751 int raw_size
= register_size (current_gdbarch
, regno
);
3752 gdb_byte
*raw_buffer
= alloca (raw_size
);
3754 if (!frame_register_read (frame
, regno
, raw_buffer
))
3755 error (_("can't read register %d (%s)"), regno
, REGISTER_NAME (regno
));
3758 /* We have a 64-bit value for this register. Find the low-order
3762 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3767 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
3771 memcpy (rare_buffer
, raw_buffer
, 4);
3775 /* Copy a 64-bit double-precision value from the current frame into
3776 rare_buffer. This may include getting half of it from the next
3780 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
3781 gdb_byte
*rare_buffer
)
3783 int raw_size
= register_size (current_gdbarch
, regno
);
3785 if (raw_size
== 8 && !mips2_fp_compat ())
3787 /* We have a 64-bit value for this register, and we should use
3789 if (!frame_register_read (frame
, regno
, rare_buffer
))
3790 error (_("can't read register %d (%s)"), regno
, REGISTER_NAME (regno
));
3794 if ((regno
- mips_regnum (current_gdbarch
)->fp0
) & 1)
3795 internal_error (__FILE__
, __LINE__
,
3796 _("mips_read_fp_register_double: bad access to "
3797 "odd-numbered FP register"));
3799 /* mips_read_fp_register_single will find the correct 32 bits from
3801 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3803 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
3804 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
3808 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
3809 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
3815 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
3817 { /* do values for FP (float) regs */
3818 gdb_byte
*raw_buffer
;
3819 double doub
, flt1
; /* doubles extracted from raw hex data */
3822 raw_buffer
= alloca (2 * register_size (current_gdbarch
,
3823 mips_regnum (current_gdbarch
)->fp0
));
3825 fprintf_filtered (file
, "%s:", REGISTER_NAME (regnum
));
3826 fprintf_filtered (file
, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum
)),
3829 if (register_size (current_gdbarch
, regnum
) == 4 || mips2_fp_compat ())
3831 /* 4-byte registers: Print hex and floating. Also print even
3832 numbered registers as doubles. */
3833 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
3834 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
3836 print_scalar_formatted (raw_buffer
, builtin_type_uint32
, 'x', 'w',
3839 fprintf_filtered (file
, " flt: ");
3841 fprintf_filtered (file
, " <invalid float> ");
3843 fprintf_filtered (file
, "%-17.9g", flt1
);
3845 if (regnum
% 2 == 0)
3847 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
3848 doub
= unpack_double (mips_double_register_type (), raw_buffer
,
3851 fprintf_filtered (file
, " dbl: ");
3853 fprintf_filtered (file
, "<invalid double>");
3855 fprintf_filtered (file
, "%-24.17g", doub
);
3860 /* Eight byte registers: print each one as hex, float and double. */
3861 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
3862 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
3864 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
3865 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv2
);
3868 print_scalar_formatted (raw_buffer
, builtin_type_uint64
, 'x', 'g',
3871 fprintf_filtered (file
, " flt: ");
3873 fprintf_filtered (file
, "<invalid float>");
3875 fprintf_filtered (file
, "%-17.9g", flt1
);
3877 fprintf_filtered (file
, " dbl: ");
3879 fprintf_filtered (file
, "<invalid double>");
3881 fprintf_filtered (file
, "%-24.17g", doub
);
3886 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
3887 int regnum
, int all
)
3889 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3890 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
3893 if (TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
3895 mips_print_fp_register (file
, frame
, regnum
);
3899 /* Get the data in raw format. */
3900 if (!frame_register_read (frame
, regnum
, raw_buffer
))
3902 fprintf_filtered (file
, "%s: [Invalid]", REGISTER_NAME (regnum
));
3906 fputs_filtered (REGISTER_NAME (regnum
), file
);
3908 /* The problem with printing numeric register names (r26, etc.) is that
3909 the user can't use them on input. Probably the best solution is to
3910 fix it so that either the numeric or the funky (a2, etc.) names
3911 are accepted on input. */
3912 if (regnum
< MIPS_NUMREGS
)
3913 fprintf_filtered (file
, "(r%d): ", regnum
);
3915 fprintf_filtered (file
, ": ");
3917 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3919 register_size (current_gdbarch
,
3920 regnum
) - register_size (current_gdbarch
, regnum
);
3924 print_scalar_formatted (raw_buffer
+ offset
,
3925 register_type (gdbarch
, regnum
), 'x', 0,
3929 /* Replacement for generic do_registers_info.
3930 Print regs in pretty columns. */
3933 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
3936 fprintf_filtered (file
, " ");
3937 mips_print_fp_register (file
, frame
, regnum
);
3938 fprintf_filtered (file
, "\n");
3943 /* Print a row's worth of GP (int) registers, with name labels above */
3946 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
3949 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3950 /* do values for GP (int) regs */
3951 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
3952 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols per row */
3956 /* For GP registers, we print a separate row of names above the vals */
3957 for (col
= 0, regnum
= start_regnum
;
3958 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
3960 if (*REGISTER_NAME (regnum
) == '\0')
3961 continue; /* unused register */
3962 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
3964 break; /* end the row: reached FP register */
3966 fprintf_filtered (file
, " ");
3967 fprintf_filtered (file
,
3968 mips_abi_regsize (current_gdbarch
) == 8 ? "%17s" : "%9s",
3969 REGISTER_NAME (regnum
));
3976 /* print the R0 to R31 names */
3977 if ((start_regnum
% NUM_REGS
) < MIPS_NUMREGS
)
3978 fprintf_filtered (file
, "\n R%-4d", start_regnum
% NUM_REGS
);
3980 fprintf_filtered (file
, "\n ");
3982 /* now print the values in hex, 4 or 8 to the row */
3983 for (col
= 0, regnum
= start_regnum
;
3984 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
3986 if (*REGISTER_NAME (regnum
) == '\0')
3987 continue; /* unused register */
3988 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
3990 break; /* end row: reached FP register */
3991 /* OK: get the data in raw format. */
3992 if (!frame_register_read (frame
, regnum
, raw_buffer
))
3993 error (_("can't read register %d (%s)"), regnum
, REGISTER_NAME (regnum
));
3994 /* pad small registers */
3996 byte
< (mips_abi_regsize (current_gdbarch
)
3997 - register_size (current_gdbarch
, regnum
)); byte
++)
3998 printf_filtered (" ");
3999 /* Now print the register value in hex, endian order. */
4000 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4002 register_size (current_gdbarch
,
4003 regnum
) - register_size (current_gdbarch
, regnum
);
4004 byte
< register_size (current_gdbarch
, regnum
); byte
++)
4005 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4007 for (byte
= register_size (current_gdbarch
, regnum
) - 1;
4009 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4010 fprintf_filtered (file
, " ");
4013 if (col
> 0) /* ie. if we actually printed anything... */
4014 fprintf_filtered (file
, "\n");
4019 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4022 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4023 struct frame_info
*frame
, int regnum
, int all
)
4025 if (regnum
!= -1) /* do one specified register */
4027 gdb_assert (regnum
>= NUM_REGS
);
4028 if (*(REGISTER_NAME (regnum
)) == '\0')
4029 error (_("Not a valid register for the current processor type"));
4031 mips_print_register (file
, frame
, regnum
, 0);
4032 fprintf_filtered (file
, "\n");
4035 /* do all (or most) registers */
4038 while (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
4040 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4043 if (all
) /* true for "INFO ALL-REGISTERS" command */
4044 regnum
= print_fp_register_row (file
, frame
, regnum
);
4046 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
4049 regnum
= print_gp_register_row (file
, frame
, regnum
);
4054 /* Is this a branch with a delay slot? */
4057 is_delayed (unsigned long insn
)
4060 for (i
= 0; i
< NUMOPCODES
; ++i
)
4061 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4062 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4064 return (i
< NUMOPCODES
4065 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4066 | INSN_COND_BRANCH_DELAY
4067 | INSN_COND_BRANCH_LIKELY
)));
4071 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
4072 struct frame_info
*frame
)
4074 CORE_ADDR pc
= get_frame_pc (frame
);
4075 gdb_byte buf
[MIPS_INSN32_SIZE
];
4077 /* There is no branch delay slot on MIPS16. */
4078 if (mips_pc_is_mips16 (pc
))
4081 if (!breakpoint_here_p (pc
+ 4))
4084 if (!safe_frame_unwind_memory (frame
, pc
, buf
, sizeof buf
))
4085 /* If error reading memory, guess that it is not a delayed
4088 return is_delayed (extract_unsigned_integer (buf
, sizeof buf
));
4091 /* To skip prologues, I use this predicate. Returns either PC itself
4092 if the code at PC does not look like a function prologue; otherwise
4093 returns an address that (if we're lucky) follows the prologue. If
4094 LENIENT, then we must skip everything which is involved in setting
4095 up the frame (it's OK to skip more, just so long as we don't skip
4096 anything which might clobber the registers which are being saved.
4097 We must skip more in the case where part of the prologue is in the
4098 delay slot of a non-prologue instruction). */
4101 mips_skip_prologue (CORE_ADDR pc
)
4104 CORE_ADDR func_addr
;
4106 /* See if we can determine the end of the prologue via the symbol table.
4107 If so, then return either PC, or the PC after the prologue, whichever
4109 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
4111 CORE_ADDR post_prologue_pc
= skip_prologue_using_sal (func_addr
);
4112 if (post_prologue_pc
!= 0)
4113 return max (pc
, post_prologue_pc
);
4116 /* Can't determine prologue from the symbol table, need to examine
4119 /* Find an upper limit on the function prologue using the debug
4120 information. If the debug information could not be used to provide
4121 that bound, then use an arbitrary large number as the upper bound. */
4122 limit_pc
= skip_prologue_using_sal (pc
);
4124 limit_pc
= pc
+ 100; /* Magic. */
4126 if (mips_pc_is_mips16 (pc
))
4127 return mips16_scan_prologue (pc
, limit_pc
, NULL
, NULL
);
4129 return mips32_scan_prologue (pc
, limit_pc
, NULL
, NULL
);
4132 /* Root of all "set mips "/"show mips " commands. This will eventually be
4133 used for all MIPS-specific commands. */
4136 show_mips_command (char *args
, int from_tty
)
4138 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
4142 set_mips_command (char *args
, int from_tty
)
4145 ("\"set mips\" must be followed by an appropriate subcommand.\n");
4146 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
4149 /* Commands to show/set the MIPS FPU type. */
4152 show_mipsfpu_command (char *args
, int from_tty
)
4155 switch (MIPS_FPU_TYPE
)
4157 case MIPS_FPU_SINGLE
:
4158 fpu
= "single-precision";
4160 case MIPS_FPU_DOUBLE
:
4161 fpu
= "double-precision";
4164 fpu
= "absent (none)";
4167 internal_error (__FILE__
, __LINE__
, _("bad switch"));
4169 if (mips_fpu_type_auto
)
4171 ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
4175 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
4180 set_mipsfpu_command (char *args
, int from_tty
)
4183 ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
4184 show_mipsfpu_command (args
, from_tty
);
4188 set_mipsfpu_single_command (char *args
, int from_tty
)
4190 struct gdbarch_info info
;
4191 gdbarch_info_init (&info
);
4192 mips_fpu_type
= MIPS_FPU_SINGLE
;
4193 mips_fpu_type_auto
= 0;
4194 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4195 instead of relying on globals. Doing that would let generic code
4196 handle the search for this specific architecture. */
4197 if (!gdbarch_update_p (info
))
4198 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4202 set_mipsfpu_double_command (char *args
, int from_tty
)
4204 struct gdbarch_info info
;
4205 gdbarch_info_init (&info
);
4206 mips_fpu_type
= MIPS_FPU_DOUBLE
;
4207 mips_fpu_type_auto
= 0;
4208 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4209 instead of relying on globals. Doing that would let generic code
4210 handle the search for this specific architecture. */
4211 if (!gdbarch_update_p (info
))
4212 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4216 set_mipsfpu_none_command (char *args
, int from_tty
)
4218 struct gdbarch_info info
;
4219 gdbarch_info_init (&info
);
4220 mips_fpu_type
= MIPS_FPU_NONE
;
4221 mips_fpu_type_auto
= 0;
4222 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4223 instead of relying on globals. Doing that would let generic code
4224 handle the search for this specific architecture. */
4225 if (!gdbarch_update_p (info
))
4226 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4230 set_mipsfpu_auto_command (char *args
, int from_tty
)
4232 mips_fpu_type_auto
= 1;
4235 /* Attempt to identify the particular processor model by reading the
4236 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
4237 the relevant processor still exists (it dates back to '94) and
4238 secondly this is not the way to do this. The processor type should
4239 be set by forcing an architecture change. */
4242 deprecated_mips_set_processor_regs_hack (void)
4244 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4247 prid
= read_register (MIPS_PRID_REGNUM
);
4249 if ((prid
& ~0xf) == 0x700)
4250 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
4253 /* Just like reinit_frame_cache, but with the right arguments to be
4254 callable as an sfunc. */
4257 reinit_frame_cache_sfunc (char *args
, int from_tty
,
4258 struct cmd_list_element
*c
)
4260 reinit_frame_cache ();
4264 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
4266 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4268 /* FIXME: cagney/2003-06-26: Is this even necessary? The
4269 disassembler needs to be able to locally determine the ISA, and
4270 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
4272 if (mips_pc_is_mips16 (memaddr
))
4273 info
->mach
= bfd_mach_mips16
;
4275 /* Round down the instruction address to the appropriate boundary. */
4276 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
4278 /* Set the disassembler options. */
4279 if (tdep
->mips_abi
== MIPS_ABI_N32
|| tdep
->mips_abi
== MIPS_ABI_N64
)
4281 /* Set up the disassembler info, so that we get the right
4282 register names from libopcodes. */
4283 if (tdep
->mips_abi
== MIPS_ABI_N32
)
4284 info
->disassembler_options
= "gpr-names=n32";
4286 info
->disassembler_options
= "gpr-names=64";
4287 info
->flavour
= bfd_target_elf_flavour
;
4290 /* This string is not recognized explicitly by the disassembler,
4291 but it tells the disassembler to not try to guess the ABI from
4292 the bfd elf headers, such that, if the user overrides the ABI
4293 of a program linked as NewABI, the disassembly will follow the
4294 register naming conventions specified by the user. */
4295 info
->disassembler_options
= "gpr-names=32";
4297 /* Call the appropriate disassembler based on the target endian-ness. */
4298 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4299 return print_insn_big_mips (memaddr
, info
);
4301 return print_insn_little_mips (memaddr
, info
);
4304 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
4305 counter value to determine whether a 16- or 32-bit breakpoint should be
4306 used. It returns a pointer to a string of bytes that encode a breakpoint
4307 instruction, stores the length of the string to *lenptr, and adjusts pc
4308 (if necessary) to point to the actual memory location where the
4309 breakpoint should be inserted. */
4311 static const gdb_byte
*
4312 mips_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
4314 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4316 if (mips_pc_is_mips16 (*pcptr
))
4318 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
4319 *pcptr
= unmake_mips16_addr (*pcptr
);
4320 *lenptr
= sizeof (mips16_big_breakpoint
);
4321 return mips16_big_breakpoint
;
4325 /* The IDT board uses an unusual breakpoint value, and
4326 sometimes gets confused when it sees the usual MIPS
4327 breakpoint instruction. */
4328 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
4329 static gdb_byte pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
4330 static gdb_byte idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
4332 *lenptr
= sizeof (big_breakpoint
);
4334 if (strcmp (target_shortname
, "mips") == 0)
4335 return idt_big_breakpoint
;
4336 else if (strcmp (target_shortname
, "ddb") == 0
4337 || strcmp (target_shortname
, "pmon") == 0
4338 || strcmp (target_shortname
, "lsi") == 0)
4339 return pmon_big_breakpoint
;
4341 return big_breakpoint
;
4346 if (mips_pc_is_mips16 (*pcptr
))
4348 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
4349 *pcptr
= unmake_mips16_addr (*pcptr
);
4350 *lenptr
= sizeof (mips16_little_breakpoint
);
4351 return mips16_little_breakpoint
;
4355 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
4356 static gdb_byte pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
4357 static gdb_byte idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
4359 *lenptr
= sizeof (little_breakpoint
);
4361 if (strcmp (target_shortname
, "mips") == 0)
4362 return idt_little_breakpoint
;
4363 else if (strcmp (target_shortname
, "ddb") == 0
4364 || strcmp (target_shortname
, "pmon") == 0
4365 || strcmp (target_shortname
, "lsi") == 0)
4366 return pmon_little_breakpoint
;
4368 return little_breakpoint
;
4373 /* If PC is in a mips16 call or return stub, return the address of the target
4374 PC, which is either the callee or the caller. There are several
4375 cases which must be handled:
4377 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
4378 target PC is in $31 ($ra).
4379 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
4380 and the target PC is in $2.
4381 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4382 before the jal instruction, this is effectively a call stub
4383 and the the target PC is in $2. Otherwise this is effectively
4384 a return stub and the target PC is in $18.
4386 See the source code for the stubs in gcc/config/mips/mips16.S for
4390 mips_skip_trampoline_code (CORE_ADDR pc
)
4393 CORE_ADDR start_addr
;
4395 /* Find the starting address and name of the function containing the PC. */
4396 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
4399 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
4400 target PC is in $31 ($ra). */
4401 if (strcmp (name
, "__mips16_ret_sf") == 0
4402 || strcmp (name
, "__mips16_ret_df") == 0)
4403 return read_signed_register (MIPS_RA_REGNUM
);
4405 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
4407 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
4408 and the target PC is in $2. */
4409 if (name
[19] >= '0' && name
[19] <= '9')
4410 return read_signed_register (2);
4412 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4413 before the jal instruction, this is effectively a call stub
4414 and the the target PC is in $2. Otherwise this is effectively
4415 a return stub and the target PC is in $18. */
4416 else if (name
[19] == 's' || name
[19] == 'd')
4418 if (pc
== start_addr
)
4420 /* Check if the target of the stub is a compiler-generated
4421 stub. Such a stub for a function bar might have a name
4422 like __fn_stub_bar, and might look like this:
4427 la $1,bar (becomes a lui/addiu pair)
4429 So scan down to the lui/addi and extract the target
4430 address from those two instructions. */
4432 CORE_ADDR target_pc
= read_signed_register (2);
4436 /* See if the name of the target function is __fn_stub_*. */
4437 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) ==
4440 if (strncmp (name
, "__fn_stub_", 10) != 0
4441 && strcmp (name
, "etext") != 0
4442 && strcmp (name
, "_etext") != 0)
4445 /* Scan through this _fn_stub_ code for the lui/addiu pair.
4446 The limit on the search is arbitrarily set to 20
4447 instructions. FIXME. */
4448 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSN32_SIZE
)
4450 inst
= mips_fetch_instruction (target_pc
);
4451 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
4452 pc
= (inst
<< 16) & 0xffff0000; /* high word */
4453 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
4454 return pc
| (inst
& 0xffff); /* low word */
4457 /* Couldn't find the lui/addui pair, so return stub address. */
4461 /* This is the 'return' part of a call stub. The return
4462 address is in $r18. */
4463 return read_signed_register (18);
4466 return 0; /* not a stub */
4469 /* Convert a dbx stab register number (from `r' declaration) to a GDB
4470 [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */
4473 mips_stab_reg_to_regnum (int num
)
4476 if (num
>= 0 && num
< 32)
4478 else if (num
>= 38 && num
< 70)
4479 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 38;
4481 regnum
= mips_regnum (current_gdbarch
)->hi
;
4483 regnum
= mips_regnum (current_gdbarch
)->lo
;
4485 /* This will hopefully (eventually) provoke a warning. Should
4486 we be calling complaint() here? */
4487 return NUM_REGS
+ NUM_PSEUDO_REGS
;
4488 return NUM_REGS
+ regnum
;
4492 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
4493 NUM_REGS .. 2 * NUM_REGS) REGNUM. */
4496 mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num
)
4499 if (num
>= 0 && num
< 32)
4501 else if (num
>= 32 && num
< 64)
4502 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 32;
4504 regnum
= mips_regnum (current_gdbarch
)->hi
;
4506 regnum
= mips_regnum (current_gdbarch
)->lo
;
4508 /* This will hopefully (eventually) provoke a warning. Should we
4509 be calling complaint() here? */
4510 return NUM_REGS
+ NUM_PSEUDO_REGS
;
4511 return NUM_REGS
+ regnum
;
4515 mips_register_sim_regno (int regnum
)
4517 /* Only makes sense to supply raw registers. */
4518 gdb_assert (regnum
>= 0 && regnum
< NUM_REGS
);
4519 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
4520 decide if it is valid. Should instead define a standard sim/gdb
4521 register numbering scheme. */
4522 if (REGISTER_NAME (NUM_REGS
+ regnum
) != NULL
4523 && REGISTER_NAME (NUM_REGS
+ regnum
)[0] != '\0')
4526 return LEGACY_SIM_REGNO_IGNORE
;
4530 /* Convert an integer into an address. Extracting the value signed
4531 guarantees a correctly sign extended address. */
4534 mips_integer_to_address (struct gdbarch
*gdbarch
,
4535 struct type
*type
, const gdb_byte
*buf
)
4537 return (CORE_ADDR
) extract_signed_integer (buf
, TYPE_LENGTH (type
));
4541 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
4543 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
4544 const char *name
= bfd_get_section_name (abfd
, sect
);
4546 if (*abip
!= MIPS_ABI_UNKNOWN
)
4549 if (strncmp (name
, ".mdebug.", 8) != 0)
4552 if (strcmp (name
, ".mdebug.abi32") == 0)
4553 *abip
= MIPS_ABI_O32
;
4554 else if (strcmp (name
, ".mdebug.abiN32") == 0)
4555 *abip
= MIPS_ABI_N32
;
4556 else if (strcmp (name
, ".mdebug.abi64") == 0)
4557 *abip
= MIPS_ABI_N64
;
4558 else if (strcmp (name
, ".mdebug.abiO64") == 0)
4559 *abip
= MIPS_ABI_O64
;
4560 else if (strcmp (name
, ".mdebug.eabi32") == 0)
4561 *abip
= MIPS_ABI_EABI32
;
4562 else if (strcmp (name
, ".mdebug.eabi64") == 0)
4563 *abip
= MIPS_ABI_EABI64
;
4565 warning (_("unsupported ABI %s."), name
+ 8);
4569 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
4571 int *lbp
= (int *) obj
;
4572 const char *name
= bfd_get_section_name (abfd
, sect
);
4574 if (strncmp (name
, ".gcc_compiled_long32", 20) == 0)
4576 else if (strncmp (name
, ".gcc_compiled_long64", 20) == 0)
4578 else if (strncmp (name
, ".gcc_compiled_long", 18) == 0)
4579 warning (_("unrecognized .gcc_compiled_longXX"));
4582 static enum mips_abi
4583 global_mips_abi (void)
4587 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
4588 if (mips_abi_strings
[i
] == mips_abi_string
)
4589 return (enum mips_abi
) i
;
4591 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
4595 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
4597 static struct target_desc
*tdesc_gp32
, *tdesc_gp64
;
4599 if (tdesc_gp32
== NULL
)
4601 /* Create feature sets with the appropriate properties. The values
4602 are not important. */
4604 tdesc_gp32
= allocate_target_description ();
4605 set_tdesc_property (tdesc_gp32
, PROPERTY_GP32
, "");
4607 tdesc_gp64
= allocate_target_description ();
4608 set_tdesc_property (tdesc_gp64
, PROPERTY_GP64
, "");
4611 /* If the size matches the set of 32-bit or 64-bit integer registers,
4612 assume that's what we've got. */
4613 register_remote_g_packet_guess (gdbarch
, 38 * 4, tdesc_gp32
);
4614 register_remote_g_packet_guess (gdbarch
, 38 * 8, tdesc_gp64
);
4616 /* If the size matches the full set of registers GDB traditionally
4617 knows about, including floating point, for either 32-bit or
4618 64-bit, assume that's what we've got. */
4619 register_remote_g_packet_guess (gdbarch
, 90 * 4, tdesc_gp32
);
4620 register_remote_g_packet_guess (gdbarch
, 90 * 8, tdesc_gp64
);
4622 /* Otherwise we don't have a useful guess. */
4625 static struct gdbarch
*
4626 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
4628 struct gdbarch
*gdbarch
;
4629 struct gdbarch_tdep
*tdep
;
4631 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
4633 enum mips_fpu_type fpu_type
;
4635 /* First of all, extract the elf_flags, if available. */
4636 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
4637 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
4638 else if (arches
!= NULL
)
4639 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
4643 fprintf_unfiltered (gdb_stdlog
,
4644 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
4646 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
4647 switch ((elf_flags
& EF_MIPS_ABI
))
4649 case E_MIPS_ABI_O32
:
4650 found_abi
= MIPS_ABI_O32
;
4652 case E_MIPS_ABI_O64
:
4653 found_abi
= MIPS_ABI_O64
;
4655 case E_MIPS_ABI_EABI32
:
4656 found_abi
= MIPS_ABI_EABI32
;
4658 case E_MIPS_ABI_EABI64
:
4659 found_abi
= MIPS_ABI_EABI64
;
4662 if ((elf_flags
& EF_MIPS_ABI2
))
4663 found_abi
= MIPS_ABI_N32
;
4665 found_abi
= MIPS_ABI_UNKNOWN
;
4669 /* GCC creates a pseudo-section whose name describes the ABI. */
4670 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
4671 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
4673 /* If we have no useful BFD information, use the ABI from the last
4674 MIPS architecture (if there is one). */
4675 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
4676 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
4678 /* Try the architecture for any hint of the correct ABI. */
4679 if (found_abi
== MIPS_ABI_UNKNOWN
4680 && info
.bfd_arch_info
!= NULL
4681 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
4683 switch (info
.bfd_arch_info
->mach
)
4685 case bfd_mach_mips3900
:
4686 found_abi
= MIPS_ABI_EABI32
;
4688 case bfd_mach_mips4100
:
4689 case bfd_mach_mips5000
:
4690 found_abi
= MIPS_ABI_EABI64
;
4692 case bfd_mach_mips8000
:
4693 case bfd_mach_mips10000
:
4694 /* On Irix, ELF64 executables use the N64 ABI. The
4695 pseudo-sections which describe the ABI aren't present
4696 on IRIX. (Even for executables created by gcc.) */
4697 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
4698 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
4699 found_abi
= MIPS_ABI_N64
;
4701 found_abi
= MIPS_ABI_N32
;
4706 /* Default 64-bit objects to N64 instead of O32. */
4707 if (found_abi
== MIPS_ABI_UNKNOWN
4708 && info
.abfd
!= NULL
4709 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
4710 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
4711 found_abi
= MIPS_ABI_N64
;
4714 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
4717 /* What has the user specified from the command line? */
4718 wanted_abi
= global_mips_abi ();
4720 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
4723 /* Now that we have found what the ABI for this binary would be,
4724 check whether the user is overriding it. */
4725 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
4726 mips_abi
= wanted_abi
;
4727 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
4728 mips_abi
= found_abi
;
4730 mips_abi
= MIPS_ABI_O32
;
4732 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
4735 /* Also used when doing an architecture lookup. */
4737 fprintf_unfiltered (gdb_stdlog
,
4738 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
4739 mips64_transfers_32bit_regs_p
);
4741 /* Determine the MIPS FPU type. */
4742 if (!mips_fpu_type_auto
)
4743 fpu_type
= mips_fpu_type
;
4744 else if (info
.bfd_arch_info
!= NULL
4745 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
4746 switch (info
.bfd_arch_info
->mach
)
4748 case bfd_mach_mips3900
:
4749 case bfd_mach_mips4100
:
4750 case bfd_mach_mips4111
:
4751 case bfd_mach_mips4120
:
4752 fpu_type
= MIPS_FPU_NONE
;
4754 case bfd_mach_mips4650
:
4755 fpu_type
= MIPS_FPU_SINGLE
;
4758 fpu_type
= MIPS_FPU_DOUBLE
;
4761 else if (arches
!= NULL
)
4762 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
4764 fpu_type
= MIPS_FPU_DOUBLE
;
4766 fprintf_unfiltered (gdb_stdlog
,
4767 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
4769 /* Check for blatant incompatibilities. */
4771 /* If we have only 32-bit registers, then we can't debug a 64-bit
4773 if (info
.target_desc
4774 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
4775 && mips_abi
!= MIPS_ABI_EABI32
4776 && mips_abi
!= MIPS_ABI_O32
)
4779 /* try to find a pre-existing architecture */
4780 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
4782 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
4784 /* MIPS needs to be pedantic about which ABI the object is
4786 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
4788 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
4790 /* Need to be pedantic about which register virtual size is
4792 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
4793 != mips64_transfers_32bit_regs_p
)
4795 /* Be pedantic about which FPU is selected. */
4796 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
4798 return arches
->gdbarch
;
4801 /* Need a new architecture. Fill in a target specific vector. */
4802 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
4803 gdbarch
= gdbarch_alloc (&info
, tdep
);
4804 tdep
->elf_flags
= elf_flags
;
4805 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
4806 tdep
->found_abi
= found_abi
;
4807 tdep
->mips_abi
= mips_abi
;
4808 tdep
->mips_fpu_type
= fpu_type
;
4809 tdep
->register_size_valid_p
= 0;
4810 tdep
->register_size
= 0;
4812 if (info
.target_desc
)
4814 /* Some useful properties can be inferred from the target. */
4815 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
4817 tdep
->register_size_valid_p
= 1;
4818 tdep
->register_size
= 4;
4820 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
4822 tdep
->register_size_valid_p
= 1;
4823 tdep
->register_size
= 8;
4827 /* Initially set everything according to the default ABI/ISA. */
4828 set_gdbarch_short_bit (gdbarch
, 16);
4829 set_gdbarch_int_bit (gdbarch
, 32);
4830 set_gdbarch_float_bit (gdbarch
, 32);
4831 set_gdbarch_double_bit (gdbarch
, 64);
4832 set_gdbarch_long_double_bit (gdbarch
, 64);
4833 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
4834 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
4835 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
4837 set_gdbarch_elf_make_msymbol_special (gdbarch
,
4838 mips_elf_make_msymbol_special
);
4840 /* Fill in the OS dependant register numbers and names. */
4842 const char **reg_names
;
4843 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
4844 struct mips_regnum
);
4845 if (info
.osabi
== GDB_OSABI_IRIX
)
4850 regnum
->badvaddr
= 66;
4853 regnum
->fp_control_status
= 69;
4854 regnum
->fp_implementation_revision
= 70;
4856 reg_names
= mips_irix_reg_names
;
4860 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
4861 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
4862 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
4863 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
4864 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
4865 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
4866 regnum
->fp_control_status
= 70;
4867 regnum
->fp_implementation_revision
= 71;
4869 if (info
.bfd_arch_info
!= NULL
4870 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
4871 reg_names
= mips_tx39_reg_names
;
4873 reg_names
= mips_generic_reg_names
;
4875 /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been
4876 replaced by read_pc? */
4877 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
4878 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
4879 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
4880 set_gdbarch_num_regs (gdbarch
, num_regs
);
4881 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
4882 set_gdbarch_register_name (gdbarch
, mips_register_name
);
4883 tdep
->mips_processor_reg_names
= reg_names
;
4884 tdep
->regnum
= regnum
;
4890 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
4891 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
4892 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
4893 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
4894 tdep
->default_mask_address_p
= 0;
4895 set_gdbarch_long_bit (gdbarch
, 32);
4896 set_gdbarch_ptr_bit (gdbarch
, 32);
4897 set_gdbarch_long_long_bit (gdbarch
, 64);
4900 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
4901 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
4902 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
4903 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
4904 tdep
->default_mask_address_p
= 0;
4905 set_gdbarch_long_bit (gdbarch
, 32);
4906 set_gdbarch_ptr_bit (gdbarch
, 32);
4907 set_gdbarch_long_long_bit (gdbarch
, 64);
4909 case MIPS_ABI_EABI32
:
4910 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
4911 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
4912 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
4913 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
4914 tdep
->default_mask_address_p
= 0;
4915 set_gdbarch_long_bit (gdbarch
, 32);
4916 set_gdbarch_ptr_bit (gdbarch
, 32);
4917 set_gdbarch_long_long_bit (gdbarch
, 64);
4919 case MIPS_ABI_EABI64
:
4920 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
4921 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
4922 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
4923 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
4924 tdep
->default_mask_address_p
= 0;
4925 set_gdbarch_long_bit (gdbarch
, 64);
4926 set_gdbarch_ptr_bit (gdbarch
, 64);
4927 set_gdbarch_long_long_bit (gdbarch
, 64);
4930 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
4931 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
4932 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
4933 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
4934 tdep
->default_mask_address_p
= 0;
4935 set_gdbarch_long_bit (gdbarch
, 32);
4936 set_gdbarch_ptr_bit (gdbarch
, 32);
4937 set_gdbarch_long_long_bit (gdbarch
, 64);
4938 set_gdbarch_long_double_bit (gdbarch
, 128);
4939 set_gdbarch_long_double_format (gdbarch
, floatformats_n32n64_long
);
4942 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
4943 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
4944 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
4945 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
4946 tdep
->default_mask_address_p
= 0;
4947 set_gdbarch_long_bit (gdbarch
, 64);
4948 set_gdbarch_ptr_bit (gdbarch
, 64);
4949 set_gdbarch_long_long_bit (gdbarch
, 64);
4950 set_gdbarch_long_double_bit (gdbarch
, 128);
4951 set_gdbarch_long_double_format (gdbarch
, floatformats_n32n64_long
);
4954 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
4957 /* GCC creates a pseudo-section whose name specifies the size of
4958 longs, since -mlong32 or -mlong64 may be used independent of
4959 other options. How those options affect pointer sizes is ABI and
4960 architecture dependent, so use them to override the default sizes
4961 set by the ABI. This table shows the relationship between ABI,
4962 -mlongXX, and size of pointers:
4964 ABI -mlongXX ptr bits
4965 --- -------- --------
4979 Note that for o32 and eabi32, pointers are always 32 bits
4980 regardless of any -mlongXX option. For all others, pointers and
4981 longs are the same, as set by -mlongXX or set by defaults.
4984 if (info
.abfd
!= NULL
)
4988 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
4991 set_gdbarch_long_bit (gdbarch
, long_bit
);
4995 case MIPS_ABI_EABI32
:
5000 case MIPS_ABI_EABI64
:
5001 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
5004 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
5009 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5010 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5013 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
5014 flag in object files because to do so would make it impossible to
5015 link with libraries compiled without "-gp32". This is
5016 unnecessarily restrictive.
5018 We could solve this problem by adding "-gp32" multilibs to gcc,
5019 but to set this flag before gcc is built with such multilibs will
5020 break too many systems.''
5022 But even more unhelpfully, the default linker output target for
5023 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
5024 for 64-bit programs - you need to change the ABI to change this,
5025 and not all gcc targets support that currently. Therefore using
5026 this flag to detect 32-bit mode would do the wrong thing given
5027 the current gcc - it would make GDB treat these 64-bit programs
5028 as 32-bit programs by default. */
5030 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
5031 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
5033 /* Add/remove bits from an address. The MIPS needs be careful to
5034 ensure that all 32 bit addresses are sign extended to 64 bits. */
5035 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
5037 /* Unwind the frame. */
5038 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
5039 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
5040 set_gdbarch_unwind_dummy_id (gdbarch
, mips_unwind_dummy_id
);
5042 /* Map debug register numbers onto internal register numbers. */
5043 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
5044 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
5045 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5046 set_gdbarch_dwarf_reg_to_regnum (gdbarch
,
5047 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5048 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
5049 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5050 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
5052 /* MIPS version of CALL_DUMMY */
5054 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
5055 replaced by a command, and all targets will default to on stack
5056 (regardless of the stack's execute status). */
5057 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
5058 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
5060 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
5061 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
5062 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
5064 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
5065 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
5067 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
5069 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
5070 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
5071 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
5073 set_gdbarch_register_type (gdbarch
, mips_register_type
);
5075 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
5077 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
5079 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
5080 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
5081 need to all be folded into the target vector. Since they are
5082 being used as guards for STOPPED_BY_WATCHPOINT, why not have
5083 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
5085 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
5087 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
5089 set_gdbarch_single_step_through_delay (gdbarch
, mips_single_step_through_delay
);
5091 /* Virtual tables. */
5092 set_gdbarch_vbit_in_delta (gdbarch
, 1);
5094 mips_register_g_packet_guesses (gdbarch
);
5096 /* Hook in OS ABI-specific overrides, if they have been registered. */
5097 gdbarch_init_osabi (info
, gdbarch
);
5099 /* Unwind the frame. */
5100 frame_unwind_append_sniffer (gdbarch
, dwarf2_frame_sniffer
);
5101 frame_unwind_append_sniffer (gdbarch
, mips_stub_frame_sniffer
);
5102 frame_unwind_append_sniffer (gdbarch
, mips_insn16_frame_sniffer
);
5103 frame_unwind_append_sniffer (gdbarch
, mips_insn32_frame_sniffer
);
5104 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
5105 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
5106 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
5107 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
5113 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
5115 struct gdbarch_info info
;
5117 /* Force the architecture to update, and (if it's a MIPS architecture)
5118 mips_gdbarch_init will take care of the rest. */
5119 gdbarch_info_init (&info
);
5120 gdbarch_update_p (info
);
5123 /* Print out which MIPS ABI is in use. */
5126 show_mips_abi (struct ui_file
*file
,
5128 struct cmd_list_element
*ignored_cmd
,
5129 const char *ignored_value
)
5131 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_mips
)
5134 "The MIPS ABI is unknown because the current architecture "
5138 enum mips_abi global_abi
= global_mips_abi ();
5139 enum mips_abi actual_abi
= mips_abi (current_gdbarch
);
5140 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
5142 if (global_abi
== MIPS_ABI_UNKNOWN
)
5145 "The MIPS ABI is set automatically (currently \"%s\").\n",
5147 else if (global_abi
== actual_abi
)
5150 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
5154 /* Probably shouldn't happen... */
5157 "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
5158 actual_abi_str
, mips_abi_strings
[global_abi
]);
5164 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
5166 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5170 int ef_mips_32bitmode
;
5171 /* Determine the ISA. */
5172 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
5190 /* Determine the size of a pointer. */
5191 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
5192 fprintf_unfiltered (file
,
5193 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
5195 fprintf_unfiltered (file
,
5196 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
5198 fprintf_unfiltered (file
,
5199 "mips_dump_tdep: ef_mips_arch = %d\n",
5201 fprintf_unfiltered (file
,
5202 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
5203 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
5204 fprintf_unfiltered (file
,
5205 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
5206 mips_mask_address_p (tdep
),
5207 tdep
->default_mask_address_p
);
5209 fprintf_unfiltered (file
,
5210 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
5211 MIPS_DEFAULT_FPU_TYPE
,
5212 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
5213 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
5214 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
5216 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI
);
5217 fprintf_unfiltered (file
,
5218 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
5220 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
5221 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
5222 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
5226 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
5229 _initialize_mips_tdep (void)
5231 static struct cmd_list_element
*mipsfpulist
= NULL
;
5232 struct cmd_list_element
*c
;
5234 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
5235 if (MIPS_ABI_LAST
+ 1
5236 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
5237 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
5239 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
5241 mips_pdr_data
= register_objfile_data ();
5243 /* Add root prefix command for all "set mips"/"show mips" commands */
5244 add_prefix_cmd ("mips", no_class
, set_mips_command
,
5245 _("Various MIPS specific commands."),
5246 &setmipscmdlist
, "set mips ", 0, &setlist
);
5248 add_prefix_cmd ("mips", no_class
, show_mips_command
,
5249 _("Various MIPS specific commands."),
5250 &showmipscmdlist
, "show mips ", 0, &showlist
);
5252 /* Allow the user to override the ABI. */
5253 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
5254 &mips_abi_string
, _("\
5255 Set the MIPS ABI used by this program."), _("\
5256 Show the MIPS ABI used by this program."), _("\
5257 This option can be set to one of:\n\
5258 auto - the default ABI associated with the current binary\n\
5267 &setmipscmdlist
, &showmipscmdlist
);
5269 /* Let the user turn off floating point and set the fence post for
5270 heuristic_proc_start. */
5272 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
5273 _("Set use of MIPS floating-point coprocessor."),
5274 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
5275 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
5276 _("Select single-precision MIPS floating-point coprocessor."),
5278 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
5279 _("Select double-precision MIPS floating-point coprocessor."),
5281 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
5282 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
5283 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
5284 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
5285 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
5286 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
5287 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
5288 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
5289 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
5290 _("Select MIPS floating-point coprocessor automatically."),
5292 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
5293 _("Show current use of MIPS floating-point coprocessor target."),
5296 /* We really would like to have both "0" and "unlimited" work, but
5297 command.c doesn't deal with that. So make it a var_zinteger
5298 because the user can always use "999999" or some such for unlimited. */
5299 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
5300 &heuristic_fence_post
, _("\
5301 Set the distance searched for the start of a function."), _("\
5302 Show the distance searched for the start of a function."), _("\
5303 If you are debugging a stripped executable, GDB needs to search through the\n\
5304 program for the start of a function. This command sets the distance of the\n\
5305 search. The only need to set it is when debugging a stripped executable."),
5306 reinit_frame_cache_sfunc
,
5307 NULL
, /* FIXME: i18n: The distance searched for the start of a function is %s. */
5308 &setlist
, &showlist
);
5310 /* Allow the user to control whether the upper bits of 64-bit
5311 addresses should be zeroed. */
5312 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
5313 &mask_address_var
, _("\
5314 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
5315 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
5316 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
5317 allow GDB to determine the correct value."),
5318 NULL
, show_mask_address
,
5319 &setmipscmdlist
, &showmipscmdlist
);
5321 /* Allow the user to control the size of 32 bit registers within the
5322 raw remote packet. */
5323 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
5324 &mips64_transfers_32bit_regs_p
, _("\
5325 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
5327 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
5329 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
5330 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
5331 64 bits for others. Use \"off\" to disable compatibility mode"),
5332 set_mips64_transfers_32bit_regs
,
5333 NULL
, /* FIXME: i18n: Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s. */
5334 &setlist
, &showlist
);
5336 /* Debug this files internals. */
5337 add_setshow_zinteger_cmd ("mips", class_maintenance
,
5339 Set mips debugging."), _("\
5340 Show mips debugging."), _("\
5341 When non-zero, mips specific debugging is enabled."),
5343 NULL
, /* FIXME: i18n: Mips debugging is currently %s. */
5344 &setdebuglist
, &showdebuglist
);