1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
2 Copyright 1988-1999, Free Software Foundation, Inc.
3 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
4 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
24 #include "gdb_string.h"
37 #include "opcode/mips.h"
39 struct frame_extra_info
41 mips_extra_func_info_t proc_desc
;
45 /* Some MIPS boards don't support floating point while others only
46 support single-precision floating-point operations. See also
47 FP_REGISTER_DOUBLE. */
51 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
52 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
53 MIPS_FPU_NONE
/* No floating point. */
56 #ifndef MIPS_DEFAULT_FPU_TYPE
57 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
59 static int mips_fpu_type_auto
= 1;
60 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
61 #define MIPS_FPU_TYPE mips_fpu_type
63 #ifndef MIPS_SAVED_REGSIZE
64 #define MIPS_SAVED_REGSIZE MIPS_REGSIZE
67 /* Do not use "TARGET_IS_MIPS64" to test the size of floating point registers */
68 #ifndef FP_REGISTER_DOUBLE
69 #define FP_REGISTER_DOUBLE (REGISTER_VIRTUAL_SIZE(FP0_REGNUM) == 8)
73 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
76 static int mips_in_lenient_prologue
PARAMS ((CORE_ADDR
, CORE_ADDR
));
79 int gdb_print_insn_mips
PARAMS ((bfd_vma
, disassemble_info
*));
81 static void mips_print_register
PARAMS ((int, int));
83 static mips_extra_func_info_t
84 heuristic_proc_desc
PARAMS ((CORE_ADDR
, CORE_ADDR
, struct frame_info
*));
86 static CORE_ADDR heuristic_proc_start
PARAMS ((CORE_ADDR
));
88 static CORE_ADDR read_next_frame_reg
PARAMS ((struct frame_info
*, int));
90 void mips_set_processor_type_command
PARAMS ((char *, int));
92 int mips_set_processor_type
PARAMS ((char *));
94 static void mips_show_processor_type_command
PARAMS ((char *, int));
96 static void reinit_frame_cache_sfunc
PARAMS ((char *, int,
97 struct cmd_list_element
*));
99 static mips_extra_func_info_t
100 find_proc_desc
PARAMS ((CORE_ADDR pc
, struct frame_info
* next_frame
));
102 static CORE_ADDR after_prologue
PARAMS ((CORE_ADDR pc
,
103 mips_extra_func_info_t proc_desc
));
105 /* This value is the model of MIPS in use. It is derived from the value
106 of the PrID register. */
108 char *mips_processor_type
;
110 char *tmp_mips_processor_type
;
112 /* A set of original names, to be used when restoring back to generic
113 registers from a specific set. */
115 char *mips_generic_reg_names
[] = MIPS_REGISTER_NAMES
;
116 char **mips_processor_reg_names
= mips_generic_reg_names
;
119 mips_register_name (i
)
122 return mips_processor_reg_names
[i
];
125 /* Names of IDT R3041 registers. */
127 char *mips_r3041_reg_names
[] = {
128 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
129 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
130 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
131 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
132 "sr", "lo", "hi", "bad", "cause","pc",
133 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
134 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
135 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
136 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
137 "fsr", "fir", "fp", "",
138 "", "", "bus", "ccfg", "", "", "", "",
139 "", "", "port", "cmp", "", "", "epc", "prid",
142 /* Names of IDT R3051 registers. */
144 char *mips_r3051_reg_names
[] = {
145 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
146 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
147 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
148 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
149 "sr", "lo", "hi", "bad", "cause","pc",
150 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
151 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
152 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
153 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
154 "fsr", "fir", "fp", "",
155 "inx", "rand", "elo", "", "ctxt", "", "", "",
156 "", "", "ehi", "", "", "", "epc", "prid",
159 /* Names of IDT R3081 registers. */
161 char *mips_r3081_reg_names
[] = {
162 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
163 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
164 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
165 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
166 "sr", "lo", "hi", "bad", "cause","pc",
167 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
168 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
169 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
170 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
171 "fsr", "fir", "fp", "",
172 "inx", "rand", "elo", "cfg", "ctxt", "", "", "",
173 "", "", "ehi", "", "", "", "epc", "prid",
176 /* Names of LSI 33k registers. */
178 char *mips_lsi33k_reg_names
[] = {
179 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
180 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
181 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
182 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
183 "epc", "hi", "lo", "sr", "cause","badvaddr",
184 "dcic", "bpc", "bda", "", "", "", "", "",
185 "", "", "", "", "", "", "", "",
186 "", "", "", "", "", "", "", "",
187 "", "", "", "", "", "", "", "",
189 "", "", "", "", "", "", "", "",
190 "", "", "", "", "", "", "", "",
196 } mips_processor_type_table
[] = {
197 { "generic", mips_generic_reg_names
},
198 { "r3041", mips_r3041_reg_names
},
199 { "r3051", mips_r3051_reg_names
},
200 { "r3071", mips_r3081_reg_names
},
201 { "r3081", mips_r3081_reg_names
},
202 { "lsi33k", mips_lsi33k_reg_names
},
210 /* Table to translate MIPS16 register field to actual register number. */
211 static int mips16_to_32_reg
[8] =
212 {16, 17, 2, 3, 4, 5, 6, 7};
214 /* Heuristic_proc_start may hunt through the text section for a long
215 time across a 2400 baud serial line. Allows the user to limit this
218 static unsigned int heuristic_fence_post
= 0;
220 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
221 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
222 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
223 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
224 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
225 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
226 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
227 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
228 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
229 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
230 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
231 #define _PROC_MAGIC_ 0x0F0F0F0F
232 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
233 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
235 struct linked_proc_info
237 struct mips_extra_func_info info
;
238 struct linked_proc_info
*next
;
240 *linked_proc_desc_table
= NULL
;
243 mips_print_extra_frame_info (fi
)
244 struct frame_info
*fi
;
248 && fi
->extra_info
->proc_desc
249 && fi
->extra_info
->proc_desc
->pdr
.framereg
< NUM_REGS
)
250 printf_filtered (" frame pointer is at %s+%d\n",
251 REGISTER_NAME (fi
->extra_info
->proc_desc
->pdr
.framereg
),
252 fi
->extra_info
->proc_desc
->pdr
.frameoffset
);
255 /* Convert between RAW and VIRTUAL registers. The RAW register size
256 defines the remote-gdb packet. */
258 static int mips64_transfers_32bit_regs_p
= 0;
261 mips_register_raw_size (reg_nr
)
264 if (mips64_transfers_32bit_regs_p
)
265 return REGISTER_VIRTUAL_SIZE (reg_nr
);
271 mips_register_convertible (reg_nr
)
274 if (mips64_transfers_32bit_regs_p
)
277 return (REGISTER_RAW_SIZE (reg_nr
) > REGISTER_VIRTUAL_SIZE (reg_nr
));
281 mips_register_convert_to_virtual (n
, virtual_type
, raw_buf
, virt_buf
)
283 struct type
*virtual_type
;
287 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
289 raw_buf
+ (REGISTER_RAW_SIZE (n
) - TYPE_LENGTH (virtual_type
)),
290 TYPE_LENGTH (virtual_type
));
294 TYPE_LENGTH (virtual_type
));
298 mips_register_convert_to_raw (virtual_type
, n
, virt_buf
, raw_buf
)
299 struct type
*virtual_type
;
304 memset (raw_buf
, 0, REGISTER_RAW_SIZE (n
));
305 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
306 memcpy (raw_buf
+ (REGISTER_RAW_SIZE (n
) - TYPE_LENGTH (virtual_type
)),
308 TYPE_LENGTH (virtual_type
));
312 TYPE_LENGTH (virtual_type
));
315 /* Should the upper word of 64-bit addresses be zeroed? */
316 static int mask_address_p
= 1;
318 /* Should call_function allocate stack space for a struct return? */
320 mips_use_struct_convention (gcc_p
, type
)
325 return (TYPE_LENGTH (type
) > 2 * MIPS_SAVED_REGSIZE
);
327 return 1; /* Structures are returned by ref in extra arg0 */
330 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
333 pc_is_mips16 (bfd_vma memaddr
)
335 struct minimal_symbol
*sym
;
337 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
338 if (IS_MIPS16_ADDR (memaddr
))
341 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
342 the high bit of the info field. Use this to decide if the function is
343 MIPS16 or normal MIPS. */
344 sym
= lookup_minimal_symbol_by_pc (memaddr
);
346 return MSYMBOL_IS_SPECIAL (sym
);
352 /* This returns the PC of the first inst after the prologue. If we can't
353 find the prologue, then return 0. */
356 after_prologue (pc
, proc_desc
)
358 mips_extra_func_info_t proc_desc
;
360 struct symtab_and_line sal
;
361 CORE_ADDR func_addr
, func_end
;
364 proc_desc
= find_proc_desc (pc
, NULL
);
368 /* If function is frameless, then we need to do it the hard way. I
369 strongly suspect that frameless always means prologueless... */
370 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
371 && PROC_FRAME_OFFSET (proc_desc
) == 0)
375 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
376 return 0; /* Unknown */
378 sal
= find_pc_line (func_addr
, 0);
380 if (sal
.end
< func_end
)
383 /* The line after the prologue is after the end of the function. In this
384 case, tell the caller to find the prologue the hard way. */
389 /* Decode a MIPS32 instruction that saves a register in the stack, and
390 set the appropriate bit in the general register mask or float register mask
391 to indicate which register is saved. This is a helper function
392 for mips_find_saved_regs. */
395 mips32_decode_reg_save (inst
, gen_mask
, float_mask
)
397 unsigned long *gen_mask
;
398 unsigned long *float_mask
;
402 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
403 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
404 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
406 /* It might be possible to use the instruction to
407 find the offset, rather than the code below which
408 is based on things being in a certain order in the
409 frame, but figuring out what the instruction's offset
410 is relative to might be a little tricky. */
411 reg
= (inst
& 0x001f0000) >> 16;
412 *gen_mask
|= (1 << reg
);
414 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
415 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
416 || (inst
& 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
419 reg
= ((inst
& 0x001f0000) >> 16);
420 *float_mask
|= (1 << reg
);
424 /* Decode a MIPS16 instruction that saves a register in the stack, and
425 set the appropriate bit in the general register or float register mask
426 to indicate which register is saved. This is a helper function
427 for mips_find_saved_regs. */
430 mips16_decode_reg_save (inst
, gen_mask
)
432 unsigned long *gen_mask
;
434 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
436 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
437 *gen_mask
|= (1 << reg
);
439 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
441 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
442 *gen_mask
|= (1 << reg
);
444 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
445 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
446 *gen_mask
|= (1 << RA_REGNUM
);
450 /* Fetch and return instruction from the specified location. If the PC
451 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
454 mips_fetch_instruction (addr
)
457 char buf
[MIPS_INSTLEN
];
461 if (pc_is_mips16 (addr
))
463 instlen
= MIPS16_INSTLEN
;
464 addr
= UNMAKE_MIPS16_ADDR (addr
);
467 instlen
= MIPS_INSTLEN
;
468 status
= read_memory_nobpt (addr
, buf
, instlen
);
470 memory_error (status
, addr
);
471 return extract_unsigned_integer (buf
, instlen
);
475 /* These the fields of 32 bit mips instructions */
476 #define mips32_op(x) (x >> 25)
477 #define itype_op(x) (x >> 25)
478 #define itype_rs(x) ((x >> 21)& 0x1f)
479 #define itype_rt(x) ((x >> 16) & 0x1f)
480 #define itype_immediate(x) ( x & 0xffff)
482 #define jtype_op(x) (x >> 25)
483 #define jtype_target(x) ( x & 0x03fffff)
485 #define rtype_op(x) (x >>25)
486 #define rtype_rs(x) ((x>>21) & 0x1f)
487 #define rtype_rt(x) ((x>>16) & 0x1f)
488 #define rtype_rd(x) ((x>>11) & 0x1f)
489 #define rtype_shamt(x) ((x>>6) & 0x1f)
490 #define rtype_funct(x) (x & 0x3f )
493 mips32_relative_offset (unsigned long inst
)
496 x
= itype_immediate (inst
);
497 if (x
& 0x8000) /* sign bit set */
499 x
|= 0xffff0000; /* sign extension */
505 /* Determine whate to set a single step breakpoint while considering
508 mips32_next_pc (CORE_ADDR pc
)
512 inst
= mips_fetch_instruction (pc
);
513 if ((inst
& 0xe0000000) != 0) /* Not a special, junp or branch instruction */
515 if ((inst
>> 27) == 5) /* BEQL BNEZ BLEZL BGTZE , bits 0101xx */
517 op
= ((inst
>> 25) & 0x03);
521 goto equal_branch
; /* BEQL */
523 goto neq_branch
; /* BNEZ */
525 goto less_branch
; /* BLEZ */
527 goto greater_branch
; /* BGTZ */
533 pc
+= 4; /* Not a branch, next instruction is easy */
536 { /* This gets way messy */
538 /* Further subdivide into SPECIAL, REGIMM and other */
539 switch (op
= ((inst
>> 26) & 0x07)) /* extract bits 28,27,26 */
541 case 0: /* SPECIAL */
542 op
= rtype_funct (inst
);
547 pc
= read_register (rtype_rs (inst
)); /* Set PC to that address */
553 break; /* end special */
556 op
= jtype_op (inst
); /* branch condition */
557 switch (jtype_op (inst
))
561 case 16: /* BLTZALL */
562 case 18: /* BLTZALL */
564 if (read_register (itype_rs (inst
)) < 0)
565 pc
+= mips32_relative_offset (inst
) + 4;
567 pc
+= 8; /* after the delay slot */
571 case 17: /* BGEZAL */
572 case 19: /* BGEZALL */
573 greater_equal_branch
:
574 if (read_register (itype_rs (inst
)) >= 0)
575 pc
+= mips32_relative_offset (inst
) + 4;
577 pc
+= 8; /* after the delay slot */
579 /* All of the other intructions in the REGIMM catagory */
584 break; /* end REGIMM */
589 reg
= jtype_target (inst
) << 2;
590 pc
= reg
+ ((pc
+ 4) & 0xf0000000);
591 /* Whats this mysterious 0xf000000 adjustment ??? */
594 /* FIXME case JALX : */
597 reg
= jtype_target (inst
) << 2;
598 pc
= reg
+ ((pc
+ 4) & 0xf0000000) + 1; /* yes, +1 */
599 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
601 break; /* The new PC will be alternate mode */
602 case 4: /* BEQ , BEQL */
604 if (read_register (itype_rs (inst
)) ==
605 read_register (itype_rt (inst
)))
606 pc
+= mips32_relative_offset (inst
) + 4;
610 case 5: /* BNE , BNEL */
612 if (read_register (itype_rs (inst
)) !=
613 read_register (itype_rs (inst
)))
614 pc
+= mips32_relative_offset (inst
) + 4;
618 case 6: /* BLEZ , BLEZL */
620 if (read_register (itype_rs (inst
) <= 0))
621 pc
+= mips32_relative_offset (inst
) + 4;
626 greater_branch
: /* BGTZ BGTZL */
627 if (read_register (itype_rs (inst
) > 0))
628 pc
+= mips32_relative_offset (inst
) + 4;
637 } /* mips32_next_pc */
639 /* Decoding the next place to set a breakpoint is irregular for the
640 mips 16 variant, but fortunatly, there fewer instructions. We have to cope
641 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
642 We dont want to set a single step instruction on the extend instruction
646 /* Lots of mips16 instruction formats */
647 /* Predicting jumps requires itype,ritype,i8type
648 and their extensions extItype,extritype,extI8type
650 enum mips16_inst_fmts
652 itype
, /* 0 immediate 5,10 */
653 ritype
, /* 1 5,3,8 */
654 rrtype
, /* 2 5,3,3,5 */
655 rritype
, /* 3 5,3,3,5 */
656 rrrtype
, /* 4 5,3,3,3,2 */
657 rriatype
, /* 5 5,3,3,1,4 */
658 shifttype
, /* 6 5,3,3,3,2 */
659 i8type
, /* 7 5,3,8 */
660 i8movtype
, /* 8 5,3,3,5 */
661 i8mov32rtype
, /* 9 5,3,5,3 */
662 i64type
, /* 10 5,3,8 */
663 ri64type
, /* 11 5,3,3,5 */
664 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
665 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
666 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
667 extRRItype
, /* 15 5,5,5,5,3,3,5 */
668 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
669 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
670 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
671 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
672 extRi64type
, /* 20 5,6,5,5,3,3,5 */
673 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
675 /* I am heaping all the fields of the formats into one structure and then,
676 only the fields which are involved in instruction extension */
680 enum mips16_inst_fmts fmt
;
681 unsigned long offset
;
682 unsigned int regx
; /* Function in i8 type */
689 print_unpack (char *comment
,
690 struct upk_mips16
*u
)
692 printf ("%s %04x ,f(%d) off(%08x) (x(%x) y(%x)\n",
693 comment
, u
->inst
, u
->fmt
, u
->offset
, u
->regx
, u
->regy
);
696 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same
697 format for the bits which make up the immediatate extension.
700 extended_offset (unsigned long extension
)
703 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
705 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
707 value
|= extension
& 0x01f; /* extract 4:0 */
711 /* Only call this function if you know that this is an extendable
712 instruction, It wont malfunction, but why make excess remote memory references?
713 If the immediate operands get sign extended or somthing, do it after
714 the extension is performed.
716 /* FIXME: Every one of these cases needs to worry about sign extension
717 when the offset is to be used in relative addressing */
720 static unsigned short
721 fetch_mips_16 (CORE_ADDR pc
)
724 pc
&= 0xfffffffe; /* clear the low order bit */
725 target_read_memory (pc
, buf
, 2);
726 return extract_unsigned_integer (buf
, 2);
730 unpack_mips16 (CORE_ADDR pc
,
731 struct upk_mips16
*upk
)
734 unsigned long extension
;
736 extpc
= (pc
- 4) & ~0x01; /* Extensions are 32 bit instructions */
737 /* Decrement to previous address and loose the 16bit mode flag */
738 /* return if the instruction was extendable, but not actually extended */
739 extended
= ((mips32_op (extension
) == 30) ? 1 : 0);
742 extension
= mips_fetch_instruction (extpc
);
751 value
= extended_offset (extension
);
752 value
= value
<< 11; /* rom for the original value */
753 value
|= upk
->inst
& 0x7ff; /* eleven bits from instruction */
757 value
= upk
->inst
& 0x7ff;
758 /* FIXME : Consider sign extension */
765 { /* A register identifier and an offset */
766 /* Most of the fields are the same as I type but the
767 immediate value is of a different length */
771 value
= extended_offset (extension
);
772 value
= value
<< 8; /* from the original instruction */
773 value
|= upk
->inst
& 0xff; /* eleven bits from instruction */
774 upk
->regx
= (extension
>> 8) & 0x07; /* or i8 funct */
775 if (value
& 0x4000) /* test the sign bit , bit 26 */
777 value
&= ~0x3fff; /* remove the sign bit */
783 value
= upk
->inst
& 0xff; /* 8 bits */
784 upk
->regx
= (upk
->inst
>> 8) & 0x07; /* or i8 funct */
785 /* FIXME: Do sign extension , this format needs it */
786 if (value
& 0x80) /* THIS CONFUSES ME */
788 value
&= 0xef; /* remove the sign bit */
799 unsigned short nexthalf
;
800 value
= ((upk
->inst
& 0x1f) << 5) | ((upk
->inst
>> 5) & 0x1f);
802 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
808 printf_filtered ("Decoding unimplemented instruction format type\n");
811 /* print_unpack("UPK",upk) ; */
815 #define mips16_op(x) (x >> 11)
817 /* This is a map of the opcodes which ae known to perform branches */
818 static unsigned char map16
[32] =
819 {0, 0, 1, 1, 1, 1, 0, 0,
820 0, 0, 0, 0, 1, 0, 0, 0,
821 0, 0, 0, 0, 0, 0, 0, 0,
822 0, 0, 0, 0, 0, 1, 1, 0
826 add_offset_16 (CORE_ADDR pc
, int offset
)
828 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000)));
834 static struct upk_mips16 upk
;
837 mips16_next_pc (CORE_ADDR pc
)
841 /* inst = mips_fetch_instruction(pc) ; - This doesnt always work */
842 inst
= fetch_mips_16 (pc
);
844 op
= mips16_op (upk
.inst
);
852 unpack_mips16 (pc
, &upk
);
861 pc
+= (offset
<< 1) + 2;
864 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
866 unpack_mips16 (pc
, &upk
);
867 pc
= add_offset_16 (pc
, upk
.offset
);
868 if ((upk
.inst
>> 10) & 0x01) /* Exchange mode */
869 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
875 unpack_mips16 (pc
, &upk
);
876 reg
= read_register (upk
.regx
);
878 pc
+= (upk
.offset
<< 1) + 2;
884 unpack_mips16 (pc
, &upk
);
885 reg
= read_register (upk
.regx
);
887 pc
+= (upk
.offset
<< 1) + 2;
891 case 12: /* I8 Formats btez btnez */
893 unpack_mips16 (pc
, &upk
);
894 /* upk.regx contains the opcode */
895 reg
= read_register (24); /* Test register is 24 */
896 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
897 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
898 /* pc = add_offset_16(pc,upk.offset) ; */
899 pc
+= (upk
.offset
<< 1) + 2;
903 case 29: /* RR Formats JR, JALR, JALR-RA */
905 op
= upk
.inst
& 0x1f;
908 upk
.regx
= (upk
.inst
>> 8) & 0x07;
909 upk
.regy
= (upk
.inst
>> 5) & 0x07;
917 break; /* Function return instruction */
923 break; /* BOGUS Guess */
925 pc
= read_register (reg
);
930 case 30: /* This is an extend instruction */
931 pc
+= 4; /* Dont be setting breakpints on the second half */
934 printf ("Filtered - next PC probably incorrrect due to jump inst\n");
940 pc
+= 2; /* just a good old instruction */
941 /* See if we CAN actually break on the next instruction */
942 /* printf("NXTm16PC %08x\n",(unsigned long)pc) ; */
944 } /* mips16_next_pc */
946 /* The mips_next_pc function supports single_tep when the remote target monitor or
947 stub is not developed enough to so a single_step.
948 It works by decoding the current instruction and predicting where a branch
949 will go. This isnt hard because all the data is available.
950 The MIPS32 and MIPS16 variants are quite different
953 mips_next_pc (CORE_ADDR pc
)
956 /* inst = mips_fetch_instruction(pc) ; */
957 /* if (pc_is_mips16) <----- This is failing */
959 return mips16_next_pc (pc
);
961 return mips32_next_pc (pc
);
964 /* Guaranteed to set fci->saved_regs to some values (it never leaves it
968 mips_find_saved_regs (fci
)
969 struct frame_info
*fci
;
972 CORE_ADDR reg_position
;
973 /* r0 bit means kernel trap */
975 /* What registers have been saved? Bitmasks. */
976 unsigned long gen_mask
, float_mask
;
977 mips_extra_func_info_t proc_desc
;
980 frame_saved_regs_zalloc (fci
);
982 /* If it is the frame for sigtramp, the saved registers are located
983 in a sigcontext structure somewhere on the stack.
984 If the stack layout for sigtramp changes we might have to change these
985 constants and the companion fixup_sigtramp in mdebugread.c */
986 #ifndef SIGFRAME_BASE
987 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
988 above the sigtramp frame. */
989 #define SIGFRAME_BASE MIPS_REGSIZE
990 /* FIXME! Are these correct?? */
991 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE)
992 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE)
993 #define SIGFRAME_FPREGSAVE_OFF \
994 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE)
996 #ifndef SIGFRAME_REG_SIZE
997 /* FIXME! Is this correct?? */
998 #define SIGFRAME_REG_SIZE MIPS_REGSIZE
1000 if (fci
->signal_handler_caller
)
1002 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1004 reg_position
= fci
->frame
+ SIGFRAME_REGSAVE_OFF
1005 + ireg
* SIGFRAME_REG_SIZE
;
1006 fci
->saved_regs
[ireg
] = reg_position
;
1008 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1010 reg_position
= fci
->frame
+ SIGFRAME_FPREGSAVE_OFF
1011 + ireg
* SIGFRAME_REG_SIZE
;
1012 fci
->saved_regs
[FP0_REGNUM
+ ireg
] = reg_position
;
1014 fci
->saved_regs
[PC_REGNUM
] = fci
->frame
+ SIGFRAME_PC_OFF
;
1018 proc_desc
= fci
->extra_info
->proc_desc
;
1019 if (proc_desc
== NULL
)
1020 /* I'm not sure how/whether this can happen. Normally when we can't
1021 find a proc_desc, we "synthesize" one using heuristic_proc_desc
1022 and set the saved_regs right away. */
1025 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1026 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1027 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1029 if ( /* In any frame other than the innermost or a frame interrupted by
1030 a signal, we assume that all registers have been saved.
1031 This assumes that all register saves in a function happen before
1032 the first function call. */
1033 (fci
->next
== NULL
|| fci
->next
->signal_handler_caller
)
1035 /* In a dummy frame we know exactly where things are saved. */
1036 && !PROC_DESC_IS_DUMMY (proc_desc
)
1038 /* Don't bother unless we are inside a function prologue. Outside the
1039 prologue, we know where everything is. */
1041 && in_prologue (fci
->pc
, PROC_LOW_ADDR (proc_desc
))
1043 /* Not sure exactly what kernel_trap means, but if it means
1044 the kernel saves the registers without a prologue doing it,
1045 we better not examine the prologue to see whether registers
1046 have been saved yet. */
1049 /* We need to figure out whether the registers that the proc_desc
1050 claims are saved have been saved yet. */
1054 /* Bitmasks; set if we have found a save for the register. */
1055 unsigned long gen_save_found
= 0;
1056 unsigned long float_save_found
= 0;
1059 /* If the address is odd, assume this is MIPS16 code. */
1060 addr
= PROC_LOW_ADDR (proc_desc
);
1061 instlen
= pc_is_mips16 (addr
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1063 /* Scan through this function's instructions preceding the current
1064 PC, and look for those that save registers. */
1065 while (addr
< fci
->pc
)
1067 inst
= mips_fetch_instruction (addr
);
1068 if (pc_is_mips16 (addr
))
1069 mips16_decode_reg_save (inst
, &gen_save_found
);
1071 mips32_decode_reg_save (inst
, &gen_save_found
, &float_save_found
);
1074 gen_mask
= gen_save_found
;
1075 float_mask
= float_save_found
;
1078 /* Fill in the offsets for the registers which gen_mask says
1080 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
1081 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1082 if (gen_mask
& 0x80000000)
1084 fci
->saved_regs
[ireg
] = reg_position
;
1085 reg_position
-= MIPS_SAVED_REGSIZE
;
1088 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order
1089 of that normally used by gcc. Therefore, we have to fetch the first
1090 instruction of the function, and if it's an entry instruction that
1091 saves $s0 or $s1, correct their saved addresses. */
1092 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1094 inst
= mips_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1095 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1098 int sreg_count
= (inst
>> 6) & 3;
1100 /* Check if the ra register was pushed on the stack. */
1101 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
1103 reg_position
-= MIPS_SAVED_REGSIZE
;
1105 /* Check if the s0 and s1 registers were pushed on the stack. */
1106 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1108 fci
->saved_regs
[reg
] = reg_position
;
1109 reg_position
-= MIPS_SAVED_REGSIZE
;
1114 /* Fill in the offsets for the registers which float_mask says
1116 reg_position
= fci
->frame
+ PROC_FREG_OFFSET (proc_desc
);
1118 /* The freg_offset points to where the first *double* register
1119 is saved. So skip to the high-order word. */
1120 if (!GDB_TARGET_IS_MIPS64
)
1121 reg_position
+= MIPS_SAVED_REGSIZE
;
1123 /* Fill in the offsets for the float registers which float_mask says
1125 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1126 if (float_mask
& 0x80000000)
1128 fci
->saved_regs
[FP0_REGNUM
+ ireg
] = reg_position
;
1129 reg_position
-= MIPS_SAVED_REGSIZE
;
1132 fci
->saved_regs
[PC_REGNUM
] = fci
->saved_regs
[RA_REGNUM
];
1136 read_next_frame_reg (fi
, regno
)
1137 struct frame_info
*fi
;
1140 for (; fi
; fi
= fi
->next
)
1142 /* We have to get the saved sp from the sigcontext
1143 if it is a signal handler frame. */
1144 if (regno
== SP_REGNUM
&& !fi
->signal_handler_caller
)
1148 if (fi
->saved_regs
== NULL
)
1149 mips_find_saved_regs (fi
);
1150 if (fi
->saved_regs
[regno
])
1151 return read_memory_integer (fi
->saved_regs
[regno
], MIPS_SAVED_REGSIZE
);
1154 return read_register (regno
);
1157 /* mips_addr_bits_remove - remove useless address bits */
1160 mips_addr_bits_remove (addr
)
1163 #if GDB_TARGET_IS_MIPS64
1164 if (mask_address_p
&& (addr
>> 32 == (CORE_ADDR
) 0xffffffff))
1166 /* This hack is a work-around for existing boards using PMON,
1167 the simulator, and any other 64-bit targets that doesn't have
1168 true 64-bit addressing. On these targets, the upper 32 bits
1169 of addresses are ignored by the hardware. Thus, the PC or SP
1170 are likely to have been sign extended to all 1s by instruction
1171 sequences that load 32-bit addresses. For example, a typical
1172 piece of code that loads an address is this:
1173 lui $r2, <upper 16 bits>
1174 ori $r2, <lower 16 bits>
1175 But the lui sign-extends the value such that the upper 32 bits
1176 may be all 1s. The workaround is simply to mask off these bits.
1177 In the future, gcc may be changed to support true 64-bit
1178 addressing, and this masking will have to be disabled. */
1179 addr
&= (CORE_ADDR
) 0xffffffff;
1182 /* Even when GDB is configured for some 32-bit targets (e.g. mips-elf),
1183 BFD is configured to handle 64-bit targets, so CORE_ADDR is 64 bits.
1184 So we still have to mask off useless bits from addresses. */
1185 addr
&= (CORE_ADDR
) 0xffffffff;
1192 mips_init_frame_pc_first (fromleaf
, prev
)
1194 struct frame_info
*prev
;
1198 pc
= ((fromleaf
) ? SAVED_PC_AFTER_CALL (prev
->next
) :
1199 prev
->next
? FRAME_SAVED_PC (prev
->next
) : read_pc ());
1200 tmp
= mips_skip_stub (pc
);
1201 prev
->pc
= tmp
? tmp
: pc
;
1206 mips_frame_saved_pc (frame
)
1207 struct frame_info
*frame
;
1210 mips_extra_func_info_t proc_desc
= frame
->extra_info
->proc_desc
;
1211 /* We have to get the saved pc from the sigcontext
1212 if it is a signal handler frame. */
1213 int pcreg
= frame
->signal_handler_caller
? PC_REGNUM
1214 : (proc_desc
? PROC_PC_REG (proc_desc
) : RA_REGNUM
);
1216 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
1217 saved_pc
= read_memory_integer (frame
->frame
- MIPS_SAVED_REGSIZE
, MIPS_SAVED_REGSIZE
);
1219 saved_pc
= read_next_frame_reg (frame
, pcreg
);
1221 return ADDR_BITS_REMOVE (saved_pc
);
1224 static struct mips_extra_func_info temp_proc_desc
;
1225 static CORE_ADDR temp_saved_regs
[NUM_REGS
];
1227 /* Set a register's saved stack address in temp_saved_regs. If an address
1228 has already been set for this register, do nothing; this way we will
1229 only recognize the first save of a given register in a function prologue.
1230 This is a helper function for mips{16,32}_heuristic_proc_desc. */
1233 set_reg_offset (regno
, offset
)
1237 if (temp_saved_regs
[regno
] == 0)
1238 temp_saved_regs
[regno
] = offset
;
1242 /* Test whether the PC points to the return instruction at the
1243 end of a function. */
1246 mips_about_to_return (pc
)
1249 if (pc_is_mips16 (pc
))
1250 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1251 generates a "jr $ra"; other times it generates code to load
1252 the return address from the stack to an accessible register (such
1253 as $a3), then a "jr" using that register. This second case
1254 is almost impossible to distinguish from an indirect jump
1255 used for switch statements, so we don't even try. */
1256 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
1258 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
1262 /* This fencepost looks highly suspicious to me. Removing it also
1263 seems suspicious as it could affect remote debugging across serial
1267 heuristic_proc_start (pc
)
1275 pc
= ADDR_BITS_REMOVE (pc
);
1277 fence
= start_pc
- heuristic_fence_post
;
1281 if (heuristic_fence_post
== UINT_MAX
1282 || fence
< VM_MIN_ADDRESS
)
1283 fence
= VM_MIN_ADDRESS
;
1285 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1287 /* search back for previous return */
1288 for (start_pc
-= instlen
;; start_pc
-= instlen
)
1289 if (start_pc
< fence
)
1291 /* It's not clear to me why we reach this point when
1292 stop_soon_quietly, but with this test, at least we
1293 don't print out warnings for every child forked (eg, on
1294 decstation). 22apr93 rich@cygnus.com. */
1295 if (!stop_soon_quietly
)
1297 static int blurb_printed
= 0;
1299 warning ("Warning: GDB can't find the start of the function at 0x%s.",
1304 /* This actually happens frequently in embedded
1305 development, when you first connect to a board
1306 and your stack pointer and pc are nowhere in
1307 particular. This message needs to give people
1308 in that situation enough information to
1309 determine that it's no big deal. */
1310 printf_filtered ("\n\
1311 GDB is unable to find the start of the function at 0x%s\n\
1312 and thus can't determine the size of that function's stack frame.\n\
1313 This means that GDB may be unable to access that stack frame, or\n\
1314 the frames below it.\n\
1315 This problem is most likely caused by an invalid program counter or\n\
1317 However, if you think GDB should simply search farther back\n\
1318 from 0x%s for code which looks like the beginning of a\n\
1319 function, you can increase the range of the search using the `set\n\
1320 heuristic-fence-post' command.\n",
1321 paddr_nz (pc
), paddr_nz (pc
));
1328 else if (pc_is_mips16 (start_pc
))
1330 unsigned short inst
;
1332 /* On MIPS16, any one of the following is likely to be the
1333 start of a function:
1337 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
1338 inst
= mips_fetch_instruction (start_pc
);
1339 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1340 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
1341 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
1342 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
1344 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1345 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1350 else if (mips_about_to_return (start_pc
))
1352 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
1357 /* skip nops (usually 1) 0 - is this */
1358 while (start_pc
< pc
&& read_memory_integer (start_pc
, MIPS_INSTLEN
) == 0)
1359 start_pc
+= MIPS_INSTLEN
;
1364 /* Fetch the immediate value from a MIPS16 instruction.
1365 If the previous instruction was an EXTEND, use it to extend
1366 the upper bits of the immediate value. This is a helper function
1367 for mips16_heuristic_proc_desc. */
1370 mips16_get_imm (prev_inst
, inst
, nbits
, scale
, is_signed
)
1371 unsigned short prev_inst
; /* previous instruction */
1372 unsigned short inst
; /* current instruction */
1373 int nbits
; /* number of bits in imm field */
1374 int scale
; /* scale factor to be applied to imm */
1375 int is_signed
; /* is the imm field signed? */
1379 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1381 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1382 if (offset
& 0x8000) /* check for negative extend */
1383 offset
= 0 - (0x10000 - (offset
& 0xffff));
1384 return offset
| (inst
& 0x1f);
1388 int max_imm
= 1 << nbits
;
1389 int mask
= max_imm
- 1;
1390 int sign_bit
= max_imm
>> 1;
1392 offset
= inst
& mask
;
1393 if (is_signed
&& (offset
& sign_bit
))
1394 offset
= 0 - (max_imm
- offset
);
1395 return offset
* scale
;
1400 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
1401 stream from start_pc to limit_pc. */
1404 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
)
1405 CORE_ADDR start_pc
, limit_pc
;
1406 struct frame_info
*next_frame
;
1410 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1411 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1412 unsigned inst
= 0; /* current instruction */
1413 unsigned entry_inst
= 0; /* the entry instruction */
1416 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0; /* size of stack frame */
1417 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1419 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
1421 /* Save the previous instruction. If it's an EXTEND, we'll extract
1422 the immediate offset extension from it in mips16_get_imm. */
1425 /* Fetch and decode the instruction. */
1426 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1427 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1428 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1430 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1431 if (offset
< 0) /* negative stack adjustment? */
1432 PROC_FRAME_OFFSET (&temp_proc_desc
) -= offset
;
1434 /* Exit loop if a positive stack adjustment is found, which
1435 usually means that the stack cleanup code in the function
1436 epilogue is reached. */
1439 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1441 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1442 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1443 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
1444 set_reg_offset (reg
, sp
+ offset
);
1446 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1448 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1449 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1450 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
1451 set_reg_offset (reg
, sp
+ offset
);
1453 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1455 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1456 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
1457 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1459 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1461 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1462 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
1463 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1465 else if (inst
== 0x673d) /* move $s1, $sp */
1468 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1470 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1472 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1473 frame_addr
= sp
+ offset
;
1474 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1475 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
1477 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1479 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1480 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1481 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1482 set_reg_offset (reg
, frame_addr
+ offset
);
1484 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1486 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1487 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1488 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1489 set_reg_offset (reg
, frame_addr
+ offset
);
1491 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1492 entry_inst
= inst
; /* save for later processing */
1493 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1494 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
1497 /* The entry instruction is typically the first instruction in a function,
1498 and it stores registers at offsets relative to the value of the old SP
1499 (before the prologue). But the value of the sp parameter to this
1500 function is the new SP (after the prologue has been executed). So we
1501 can't calculate those offsets until we've seen the entire prologue,
1502 and can calculate what the old SP must have been. */
1503 if (entry_inst
!= 0)
1505 int areg_count
= (entry_inst
>> 8) & 7;
1506 int sreg_count
= (entry_inst
>> 6) & 3;
1508 /* The entry instruction always subtracts 32 from the SP. */
1509 PROC_FRAME_OFFSET (&temp_proc_desc
) += 32;
1511 /* Now we can calculate what the SP must have been at the
1512 start of the function prologue. */
1513 sp
+= PROC_FRAME_OFFSET (&temp_proc_desc
);
1515 /* Check if a0-a3 were saved in the caller's argument save area. */
1516 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1518 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1519 set_reg_offset (reg
, sp
+ offset
);
1520 offset
+= MIPS_SAVED_REGSIZE
;
1523 /* Check if the ra register was pushed on the stack. */
1525 if (entry_inst
& 0x20)
1527 PROC_REG_MASK (&temp_proc_desc
) |= 1 << RA_REGNUM
;
1528 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1529 offset
-= MIPS_SAVED_REGSIZE
;
1532 /* Check if the s0 and s1 registers were pushed on the stack. */
1533 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1535 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1536 set_reg_offset (reg
, sp
+ offset
);
1537 offset
-= MIPS_SAVED_REGSIZE
;
1543 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
)
1544 CORE_ADDR start_pc
, limit_pc
;
1545 struct frame_info
*next_frame
;
1549 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
1551 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
1552 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0;
1553 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1554 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
1556 unsigned long inst
, high_word
, low_word
;
1559 /* Fetch the instruction. */
1560 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
1562 /* Save some code by pre-extracting some useful fields. */
1563 high_word
= (inst
>> 16) & 0xffff;
1564 low_word
= inst
& 0xffff;
1565 reg
= high_word
& 0x1f;
1567 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
1568 || high_word
== 0x23bd /* addi $sp,$sp,-i */
1569 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
1571 if (low_word
& 0x8000) /* negative stack adjustment? */
1572 PROC_FRAME_OFFSET (&temp_proc_desc
) += 0x10000 - low_word
;
1574 /* Exit loop if a positive stack adjustment is found, which
1575 usually means that the stack cleanup code in the function
1576 epilogue is reached. */
1579 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1581 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1582 set_reg_offset (reg
, sp
+ low_word
);
1584 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1586 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
1587 but the register size used is only 32 bits. Make the address
1588 for the saved register point to the lower 32 bits. */
1589 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1590 set_reg_offset (reg
, sp
+ low_word
+ 8 - MIPS_REGSIZE
);
1592 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
1594 /* Old gcc frame, r30 is virtual frame pointer. */
1595 if ((long) low_word
!= PROC_FRAME_OFFSET (&temp_proc_desc
))
1596 frame_addr
= sp
+ low_word
;
1597 else if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1599 unsigned alloca_adjust
;
1600 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1601 frame_addr
= read_next_frame_reg (next_frame
, 30);
1602 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
1603 if (alloca_adjust
> 0)
1605 /* FP > SP + frame_size. This may be because
1606 * of an alloca or somethings similar.
1607 * Fix sp to "pre-alloca" value, and try again.
1609 sp
+= alloca_adjust
;
1614 /* move $30,$sp. With different versions of gas this will be either
1615 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
1616 Accept any one of these. */
1617 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
1619 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
1620 if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1622 unsigned alloca_adjust
;
1623 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1624 frame_addr
= read_next_frame_reg (next_frame
, 30);
1625 alloca_adjust
= (unsigned) (frame_addr
- sp
);
1626 if (alloca_adjust
> 0)
1628 /* FP > SP + frame_size. This may be because
1629 * of an alloca or somethings similar.
1630 * Fix sp to "pre-alloca" value, and try again.
1632 sp
+= alloca_adjust
;
1637 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
1639 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1640 set_reg_offset (reg
, frame_addr
+ low_word
);
1645 static mips_extra_func_info_t
1646 heuristic_proc_desc (start_pc
, limit_pc
, next_frame
)
1647 CORE_ADDR start_pc
, limit_pc
;
1648 struct frame_info
*next_frame
;
1650 CORE_ADDR sp
= read_next_frame_reg (next_frame
, SP_REGNUM
);
1654 memset (&temp_proc_desc
, '\0', sizeof (temp_proc_desc
));
1655 memset (&temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
1656 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
1657 PROC_FRAME_REG (&temp_proc_desc
) = SP_REGNUM
;
1658 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
1660 if (start_pc
+ 200 < limit_pc
)
1661 limit_pc
= start_pc
+ 200;
1662 if (pc_is_mips16 (start_pc
))
1663 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1665 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1666 return &temp_proc_desc
;
1669 static mips_extra_func_info_t
1670 non_heuristic_proc_desc (pc
, addrptr
)
1674 CORE_ADDR startaddr
;
1675 mips_extra_func_info_t proc_desc
;
1676 struct block
*b
= block_for_pc (pc
);
1679 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
1681 *addrptr
= startaddr
;
1682 if (b
== NULL
|| PC_IN_CALL_DUMMY (pc
, 0, 0))
1686 if (startaddr
> BLOCK_START (b
))
1687 /* This is the "pathological" case referred to in a comment in
1688 print_frame_info. It might be better to move this check into
1692 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_NAMESPACE
, 0, NULL
);
1695 /* If we never found a PDR for this function in symbol reading, then
1696 examine prologues to find the information. */
1699 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
1700 if (PROC_FRAME_REG (proc_desc
) == -1)
1710 static mips_extra_func_info_t
1711 find_proc_desc (pc
, next_frame
)
1713 struct frame_info
*next_frame
;
1715 mips_extra_func_info_t proc_desc
;
1716 CORE_ADDR startaddr
;
1718 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
1722 /* IF this is the topmost frame AND
1723 * (this proc does not have debugging information OR
1724 * the PC is in the procedure prologue)
1725 * THEN create a "heuristic" proc_desc (by analyzing
1726 * the actual code) to replace the "official" proc_desc.
1728 if (next_frame
== NULL
)
1730 struct symtab_and_line val
;
1731 struct symbol
*proc_symbol
=
1732 PROC_DESC_IS_DUMMY (proc_desc
) ? 0 : PROC_SYMBOL (proc_desc
);
1736 val
= find_pc_line (BLOCK_START
1737 (SYMBOL_BLOCK_VALUE (proc_symbol
)),
1739 val
.pc
= val
.end
? val
.end
: pc
;
1741 if (!proc_symbol
|| pc
< val
.pc
)
1743 mips_extra_func_info_t found_heuristic
=
1744 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
),
1746 if (found_heuristic
)
1747 proc_desc
= found_heuristic
;
1753 /* Is linked_proc_desc_table really necessary? It only seems to be used
1754 by procedure call dummys. However, the procedures being called ought
1755 to have their own proc_descs, and even if they don't,
1756 heuristic_proc_desc knows how to create them! */
1758 register struct linked_proc_info
*link
;
1760 for (link
= linked_proc_desc_table
; link
; link
= link
->next
)
1761 if (PROC_LOW_ADDR (&link
->info
) <= pc
1762 && PROC_HIGH_ADDR (&link
->info
) > pc
)
1766 startaddr
= heuristic_proc_start (pc
);
1769 heuristic_proc_desc (startaddr
, pc
, next_frame
);
1775 get_frame_pointer (frame
, proc_desc
)
1776 struct frame_info
*frame
;
1777 mips_extra_func_info_t proc_desc
;
1779 return ADDR_BITS_REMOVE (
1780 read_next_frame_reg (frame
, PROC_FRAME_REG (proc_desc
)) +
1781 PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
1784 mips_extra_func_info_t cached_proc_desc
;
1787 mips_frame_chain (frame
)
1788 struct frame_info
*frame
;
1790 mips_extra_func_info_t proc_desc
;
1792 CORE_ADDR saved_pc
= FRAME_SAVED_PC (frame
);
1794 if (saved_pc
== 0 || inside_entry_file (saved_pc
))
1797 /* Check if the PC is inside a call stub. If it is, fetch the
1798 PC of the caller of that stub. */
1799 if ((tmp
= mips_skip_stub (saved_pc
)) != 0)
1802 /* Look up the procedure descriptor for this PC. */
1803 proc_desc
= find_proc_desc (saved_pc
, frame
);
1807 cached_proc_desc
= proc_desc
;
1809 /* If no frame pointer and frame size is zero, we must be at end
1810 of stack (or otherwise hosed). If we don't check frame size,
1811 we loop forever if we see a zero size frame. */
1812 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
1813 && PROC_FRAME_OFFSET (proc_desc
) == 0
1814 /* The previous frame from a sigtramp frame might be frameless
1815 and have frame size zero. */
1816 && !frame
->signal_handler_caller
)
1819 return get_frame_pointer (frame
, proc_desc
);
1823 mips_init_extra_frame_info (fromleaf
, fci
)
1825 struct frame_info
*fci
;
1829 /* Use proc_desc calculated in frame_chain */
1830 mips_extra_func_info_t proc_desc
=
1831 fci
->next
? cached_proc_desc
: find_proc_desc (fci
->pc
, fci
->next
);
1833 fci
->extra_info
= (struct frame_extra_info
*)
1834 frame_obstack_alloc (sizeof (struct frame_extra_info
));
1836 fci
->saved_regs
= NULL
;
1837 fci
->extra_info
->proc_desc
=
1838 proc_desc
== &temp_proc_desc
? 0 : proc_desc
;
1841 /* Fixup frame-pointer - only needed for top frame */
1842 /* This may not be quite right, if proc has a real frame register.
1843 Get the value of the frame relative sp, procedure might have been
1844 interrupted by a signal at it's very start. */
1845 if (fci
->pc
== PROC_LOW_ADDR (proc_desc
)
1846 && !PROC_DESC_IS_DUMMY (proc_desc
))
1847 fci
->frame
= read_next_frame_reg (fci
->next
, SP_REGNUM
);
1849 fci
->frame
= get_frame_pointer (fci
->next
, proc_desc
);
1851 if (proc_desc
== &temp_proc_desc
)
1855 /* Do not set the saved registers for a sigtramp frame,
1856 mips_find_saved_registers will do that for us.
1857 We can't use fci->signal_handler_caller, it is not yet set. */
1858 find_pc_partial_function (fci
->pc
, &name
,
1859 (CORE_ADDR
*) NULL
, (CORE_ADDR
*) NULL
);
1860 if (!IN_SIGTRAMP (fci
->pc
, name
))
1862 frame_saved_regs_zalloc (fci
);
1863 memcpy (fci
->saved_regs
, temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
1864 fci
->saved_regs
[PC_REGNUM
]
1865 = fci
->saved_regs
[RA_REGNUM
];
1869 /* hack: if argument regs are saved, guess these contain args */
1870 /* assume we can't tell how many args for now */
1871 fci
->extra_info
->num_args
= -1;
1872 for (regnum
= MIPS_LAST_ARG_REGNUM
; regnum
>= A0_REGNUM
; regnum
--)
1874 if (PROC_REG_MASK (proc_desc
) & (1 << regnum
))
1876 fci
->extra_info
->num_args
= regnum
- A0_REGNUM
+ 1;
1883 /* MIPS stack frames are almost impenetrable. When execution stops,
1884 we basically have to look at symbol information for the function
1885 that we stopped in, which tells us *which* register (if any) is
1886 the base of the frame pointer, and what offset from that register
1887 the frame itself is at.
1889 This presents a problem when trying to examine a stack in memory
1890 (that isn't executing at the moment), using the "frame" command. We
1891 don't have a PC, nor do we have any registers except SP.
1893 This routine takes two arguments, SP and PC, and tries to make the
1894 cached frames look as if these two arguments defined a frame on the
1895 cache. This allows the rest of info frame to extract the important
1896 arguments without difficulty. */
1899 setup_arbitrary_frame (argc
, argv
)
1904 error ("MIPS frame specifications require two arguments: sp and pc");
1906 return create_new_frame (argv
[0], argv
[1]);
1910 * STACK_ARGSIZE -- how many bytes does a pushed function arg take up on the stack?
1912 * For n32 ABI, eight.
1913 * For all others, he same as the size of a general register.
1915 #if defined (_MIPS_SIM_NABI32) && _MIPS_SIM == _MIPS_SIM_NABI32
1916 #define MIPS_NABI32 1
1917 #define STACK_ARGSIZE 8
1919 #define MIPS_NABI32 0
1920 #define STACK_ARGSIZE MIPS_SAVED_REGSIZE
1924 mips_push_arguments (nargs
, args
, sp
, struct_return
, struct_addr
)
1929 CORE_ADDR struct_addr
;
1935 int stack_offset
= 0;
1937 /* Macros to round N up or down to the next A boundary; A must be
1939 #define ROUND_DOWN(n,a) ((n) & ~((a)-1))
1940 #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1))
1942 /* First ensure that the stack and structure return address (if any)
1943 are properly aligned. The stack has to be at least 64-bit aligned
1944 even on 32-bit machines, because doubles must be 64-bit aligned.
1945 On at least one MIPS variant, stack frames need to be 128-bit
1946 aligned, so we round to this widest known alignment. */
1947 sp
= ROUND_DOWN (sp
, 16);
1948 struct_addr
= ROUND_DOWN (struct_addr
, MIPS_SAVED_REGSIZE
);
1950 /* Now make space on the stack for the args. We allocate more
1951 than necessary for EABI, because the first few arguments are
1952 passed in registers, but that's OK. */
1953 for (argnum
= 0; argnum
< nargs
; argnum
++)
1954 len
+= ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])), MIPS_SAVED_REGSIZE
);
1955 sp
-= ROUND_UP (len
, 16);
1957 /* Initialize the integer and float register pointers. */
1959 float_argreg
= FPA0_REGNUM
;
1961 /* the struct_return pointer occupies the first parameter-passing reg */
1963 write_register (argreg
++, struct_addr
);
1965 /* Now load as many as possible of the first arguments into
1966 registers, and push the rest onto the stack. Loop thru args
1967 from first to last. */
1968 for (argnum
= 0; argnum
< nargs
; argnum
++)
1971 char valbuf
[MAX_REGISTER_RAW_SIZE
];
1972 value_ptr arg
= args
[argnum
];
1973 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
1974 int len
= TYPE_LENGTH (arg_type
);
1975 enum type_code typecode
= TYPE_CODE (arg_type
);
1977 /* The EABI passes structures that do not fit in a register by
1978 reference. In all other cases, pass the structure by value. */
1979 if (MIPS_EABI
&& len
> MIPS_SAVED_REGSIZE
&&
1980 (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
1982 store_address (valbuf
, MIPS_SAVED_REGSIZE
, VALUE_ADDRESS (arg
));
1983 typecode
= TYPE_CODE_PTR
;
1984 len
= MIPS_SAVED_REGSIZE
;
1988 val
= (char *) VALUE_CONTENTS (arg
);
1990 /* 32-bit ABIs always start floating point arguments in an
1991 even-numbered floating point register. */
1992 if (!FP_REGISTER_DOUBLE
&& typecode
== TYPE_CODE_FLT
1993 && (float_argreg
& 1))
1996 /* Floating point arguments passed in registers have to be
1997 treated specially. On 32-bit architectures, doubles
1998 are passed in register pairs; the even register gets
1999 the low word, and the odd register gets the high word.
2000 On non-EABI processors, the first two floating point arguments are
2001 also copied to general registers, because MIPS16 functions
2002 don't use float registers for arguments. This duplication of
2003 arguments in general registers can't hurt non-MIPS16 functions
2004 because those registers are normally skipped. */
2005 if (typecode
== TYPE_CODE_FLT
2006 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
2007 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
)
2009 if (!FP_REGISTER_DOUBLE
&& len
== 8)
2011 int low_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 4 : 0;
2012 unsigned long regval
;
2014 /* Write the low word of the double to the even register(s). */
2015 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2016 write_register (float_argreg
++, regval
);
2018 write_register (argreg
+ 1, regval
);
2020 /* Write the high word of the double to the odd register(s). */
2021 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2022 write_register (float_argreg
++, regval
);
2025 write_register (argreg
, regval
);
2032 /* This is a floating point value that fits entirely
2033 in a single register. */
2034 /* On 32 bit ABI's the float_argreg is further adjusted
2035 above to ensure that it is even register aligned. */
2036 CORE_ADDR regval
= extract_address (val
, len
);
2037 write_register (float_argreg
++, regval
);
2040 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
2041 registers for each argument. The below is (my
2042 guess) to ensure that the corresponding integer
2043 register has reserved the same space. */
2044 write_register (argreg
, regval
);
2045 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
2051 /* Copy the argument to general registers or the stack in
2052 register-sized pieces. Large arguments are split between
2053 registers and stack. */
2054 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
2055 are treated specially: Irix cc passes them in registers
2056 where gcc sometimes puts them on the stack. For maximum
2057 compatibility, we will put them in both places. */
2059 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
2060 (len
% MIPS_SAVED_REGSIZE
!= 0));
2063 int partial_len
= len
< MIPS_SAVED_REGSIZE
? len
: MIPS_SAVED_REGSIZE
;
2065 if (argreg
> MIPS_LAST_ARG_REGNUM
|| odd_sized_struct
)
2067 /* Write this portion of the argument to the stack. */
2068 /* Should shorter than int integer values be
2069 promoted to int before being stored? */
2071 int longword_offset
= 0;
2072 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2074 if (STACK_ARGSIZE
== 8 &&
2075 (typecode
== TYPE_CODE_INT
||
2076 typecode
== TYPE_CODE_PTR
||
2077 typecode
== TYPE_CODE_FLT
) && len
<= 4)
2078 longword_offset
= STACK_ARGSIZE
- len
;
2079 else if ((typecode
== TYPE_CODE_STRUCT
||
2080 typecode
== TYPE_CODE_UNION
) &&
2081 TYPE_LENGTH (arg_type
) < STACK_ARGSIZE
)
2082 longword_offset
= STACK_ARGSIZE
- len
;
2085 write_memory (sp
+ stack_offset
+ longword_offset
,
2089 /* Note!!! This is NOT an else clause.
2090 Odd sized structs may go thru BOTH paths. */
2091 if (argreg
<= MIPS_LAST_ARG_REGNUM
)
2093 CORE_ADDR regval
= extract_address (val
, partial_len
);
2095 /* A non-floating-point argument being passed in a
2096 general register. If a struct or union, and if
2097 the remaining length is smaller than the register
2098 size, we have to adjust the register value on
2101 It does not seem to be necessary to do the
2102 same for integral types.
2104 Also don't do this adjustment on EABI and O64
2108 && MIPS_SAVED_REGSIZE
< 8
2109 && TARGET_BYTE_ORDER
== BIG_ENDIAN
2110 && partial_len
< MIPS_SAVED_REGSIZE
2111 && (typecode
== TYPE_CODE_STRUCT
||
2112 typecode
== TYPE_CODE_UNION
))
2113 regval
<<= ((MIPS_SAVED_REGSIZE
- partial_len
) *
2116 write_register (argreg
, regval
);
2119 /* If this is the old ABI, prevent subsequent floating
2120 point arguments from being passed in floating point
2123 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
2129 /* The offset onto the stack at which we will start
2130 copying parameters (after the registers are used up)
2131 begins at (4 * MIPS_REGSIZE) in the old ABI. This
2132 leaves room for the "home" area for register parameters.
2134 In the new EABI (and the NABI32), the 8 register parameters
2135 do not have "home" stack space reserved for them, so the
2136 stack offset does not get incremented until after
2137 we have used up the 8 parameter registers. */
2139 if (!(MIPS_EABI
|| MIPS_NABI32
) ||
2141 stack_offset
+= ROUND_UP (partial_len
, STACK_ARGSIZE
);
2146 /* Return adjusted stack pointer. */
2151 mips_push_return_address (pc
, sp
)
2155 /* Set the return address register to point to the entry
2156 point of the program, where a breakpoint lies in wait. */
2157 write_register (RA_REGNUM
, CALL_DUMMY_ADDRESS ());
2162 mips_push_register (CORE_ADDR
* sp
, int regno
)
2164 char buffer
[MAX_REGISTER_RAW_SIZE
];
2167 if (MIPS_SAVED_REGSIZE
< REGISTER_RAW_SIZE (regno
))
2169 regsize
= MIPS_SAVED_REGSIZE
;
2170 offset
= (TARGET_BYTE_ORDER
== BIG_ENDIAN
2171 ? REGISTER_RAW_SIZE (regno
) - MIPS_SAVED_REGSIZE
2176 regsize
= REGISTER_RAW_SIZE (regno
);
2180 read_register_gen (regno
, buffer
);
2181 write_memory (*sp
, buffer
+ offset
, regsize
);
2184 /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */
2185 #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1))
2188 mips_push_dummy_frame ()
2191 struct linked_proc_info
*link
= (struct linked_proc_info
*)
2192 xmalloc (sizeof (struct linked_proc_info
));
2193 mips_extra_func_info_t proc_desc
= &link
->info
;
2194 CORE_ADDR sp
= ADDR_BITS_REMOVE (read_register (SP_REGNUM
));
2195 CORE_ADDR old_sp
= sp
;
2196 link
->next
= linked_proc_desc_table
;
2197 linked_proc_desc_table
= link
;
2199 /* FIXME! are these correct ? */
2200 #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */
2201 #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1))
2202 #define FLOAT_REG_SAVE_MASK MASK(0,19)
2203 #define FLOAT_SINGLE_REG_SAVE_MASK \
2204 ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0))
2206 * The registers we must save are all those not preserved across
2207 * procedure calls. Dest_Reg (see tm-mips.h) must also be saved.
2208 * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI
2209 * and FP Control/Status registers.
2212 * Dummy frame layout:
2215 * Saved MMHI, MMLO, FPC_CSR
2220 * Saved D18 (i.e. F19, F18)
2222 * Saved D0 (i.e. F1, F0)
2223 * Argument build area and stack arguments written via mips_push_arguments
2227 /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */
2228 PROC_FRAME_REG (proc_desc
) = PUSH_FP_REGNUM
;
2229 PROC_FRAME_OFFSET (proc_desc
) = 0;
2230 PROC_FRAME_ADJUST (proc_desc
) = 0;
2231 mips_push_register (&sp
, PC_REGNUM
);
2232 mips_push_register (&sp
, HI_REGNUM
);
2233 mips_push_register (&sp
, LO_REGNUM
);
2234 mips_push_register (&sp
, MIPS_FPU_TYPE
== MIPS_FPU_NONE
? 0 : FCRCS_REGNUM
);
2236 /* Save general CPU registers */
2237 PROC_REG_MASK (proc_desc
) = GEN_REG_SAVE_MASK
;
2238 /* PROC_REG_OFFSET is the offset of the first saved register from FP. */
2239 PROC_REG_OFFSET (proc_desc
) = sp
- old_sp
- MIPS_SAVED_REGSIZE
;
2240 for (ireg
= 32; --ireg
>= 0;)
2241 if (PROC_REG_MASK (proc_desc
) & (1 << ireg
))
2242 mips_push_register (&sp
, ireg
);
2244 /* Save floating point registers starting with high order word */
2245 PROC_FREG_MASK (proc_desc
) =
2246 MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? FLOAT_REG_SAVE_MASK
2247 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? FLOAT_SINGLE_REG_SAVE_MASK
: 0;
2248 /* PROC_FREG_OFFSET is the offset of the first saved *double* register
2250 PROC_FREG_OFFSET (proc_desc
) = sp
- old_sp
- 8;
2251 for (ireg
= 32; --ireg
>= 0;)
2252 if (PROC_FREG_MASK (proc_desc
) & (1 << ireg
))
2253 mips_push_register (&sp
, ireg
+ FP0_REGNUM
);
2255 /* Update the frame pointer for the call dummy and the stack pointer.
2256 Set the procedure's starting and ending addresses to point to the
2257 call dummy address at the entry point. */
2258 write_register (PUSH_FP_REGNUM
, old_sp
);
2259 write_register (SP_REGNUM
, sp
);
2260 PROC_LOW_ADDR (proc_desc
) = CALL_DUMMY_ADDRESS ();
2261 PROC_HIGH_ADDR (proc_desc
) = CALL_DUMMY_ADDRESS () + 4;
2262 SET_PROC_DESC_IS_DUMMY (proc_desc
);
2263 PROC_PC_REG (proc_desc
) = RA_REGNUM
;
2269 register int regnum
;
2270 struct frame_info
*frame
= get_current_frame ();
2271 CORE_ADDR new_sp
= FRAME_FP (frame
);
2273 mips_extra_func_info_t proc_desc
= frame
->extra_info
->proc_desc
;
2275 write_register (PC_REGNUM
, FRAME_SAVED_PC (frame
));
2276 if (frame
->saved_regs
== NULL
)
2277 mips_find_saved_regs (frame
);
2278 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
2280 if (regnum
!= SP_REGNUM
&& regnum
!= PC_REGNUM
2281 && frame
->saved_regs
[regnum
])
2282 write_register (regnum
,
2283 read_memory_integer (frame
->saved_regs
[regnum
],
2284 MIPS_SAVED_REGSIZE
));
2286 write_register (SP_REGNUM
, new_sp
);
2287 flush_cached_frames ();
2289 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
2291 struct linked_proc_info
*pi_ptr
, *prev_ptr
;
2293 for (pi_ptr
= linked_proc_desc_table
, prev_ptr
= NULL
;
2295 prev_ptr
= pi_ptr
, pi_ptr
= pi_ptr
->next
)
2297 if (&pi_ptr
->info
== proc_desc
)
2302 error ("Can't locate dummy extra frame info\n");
2304 if (prev_ptr
!= NULL
)
2305 prev_ptr
->next
= pi_ptr
->next
;
2307 linked_proc_desc_table
= pi_ptr
->next
;
2311 write_register (HI_REGNUM
,
2312 read_memory_integer (new_sp
- 2 * MIPS_SAVED_REGSIZE
,
2313 MIPS_SAVED_REGSIZE
));
2314 write_register (LO_REGNUM
,
2315 read_memory_integer (new_sp
- 3 * MIPS_SAVED_REGSIZE
,
2316 MIPS_SAVED_REGSIZE
));
2317 if (MIPS_FPU_TYPE
!= MIPS_FPU_NONE
)
2318 write_register (FCRCS_REGNUM
,
2319 read_memory_integer (new_sp
- 4 * MIPS_SAVED_REGSIZE
,
2320 MIPS_SAVED_REGSIZE
));
2325 mips_print_register (regnum
, all
)
2328 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2330 /* Get the data in raw format. */
2331 if (read_relative_register_raw_bytes (regnum
, raw_buffer
))
2333 printf_filtered ("%s: [Invalid]", REGISTER_NAME (regnum
));
2337 /* If an even floating point register, also print as double. */
2338 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
2339 && !((regnum
- FP0_REGNUM
) & 1))
2340 if (REGISTER_RAW_SIZE (regnum
) == 4) /* this would be silly on MIPS64 or N32 (Irix 6) */
2342 char dbuffer
[2 * MAX_REGISTER_RAW_SIZE
];
2344 read_relative_register_raw_bytes (regnum
, dbuffer
);
2345 read_relative_register_raw_bytes (regnum
+ 1, dbuffer
+ MIPS_REGSIZE
);
2346 REGISTER_CONVERT_TO_TYPE (regnum
, builtin_type_double
, dbuffer
);
2348 printf_filtered ("(d%d: ", regnum
- FP0_REGNUM
);
2349 val_print (builtin_type_double
, dbuffer
, 0, 0,
2350 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2351 printf_filtered ("); ");
2353 fputs_filtered (REGISTER_NAME (regnum
), gdb_stdout
);
2355 /* The problem with printing numeric register names (r26, etc.) is that
2356 the user can't use them on input. Probably the best solution is to
2357 fix it so that either the numeric or the funky (a2, etc.) names
2358 are accepted on input. */
2359 if (regnum
< MIPS_NUMREGS
)
2360 printf_filtered ("(r%d): ", regnum
);
2362 printf_filtered (": ");
2364 /* If virtual format is floating, print it that way. */
2365 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2366 if (FP_REGISTER_DOUBLE
)
2367 { /* show 8-byte floats as float AND double: */
2368 int offset
= 4 * (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2370 printf_filtered (" (float) ");
2371 val_print (builtin_type_float
, raw_buffer
+ offset
, 0, 0,
2372 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2373 printf_filtered (", (double) ");
2374 val_print (builtin_type_double
, raw_buffer
, 0, 0,
2375 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2378 val_print (REGISTER_VIRTUAL_TYPE (regnum
), raw_buffer
, 0, 0,
2379 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2380 /* Else print as integer in hex. */
2382 print_scalar_formatted (raw_buffer
, REGISTER_VIRTUAL_TYPE (regnum
),
2383 'x', 0, gdb_stdout
);
2386 /* Replacement for generic do_registers_info.
2387 Print regs in pretty columns. */
2390 do_fp_register_row (regnum
)
2392 { /* do values for FP (float) regs */
2393 char *raw_buffer
[2];
2395 /* use HI and LO to control the order of combining two flt regs */
2396 int HI
= (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2397 int LO
= (TARGET_BYTE_ORDER
!= BIG_ENDIAN
);
2398 double doub
, flt1
, flt2
; /* doubles extracted from raw hex data */
2399 int inv1
, inv2
, inv3
;
2401 raw_buffer
[0] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM
));
2402 raw_buffer
[1] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM
));
2403 dbl_buffer
= (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM
));
2405 /* Get the data in raw format. */
2406 if (read_relative_register_raw_bytes (regnum
, raw_buffer
[HI
]))
2407 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
2408 if (REGISTER_RAW_SIZE (regnum
) == 4)
2410 /* 4-byte registers: we can fit two registers per row. */
2411 /* Also print every pair of 4-byte regs as an 8-byte double. */
2412 if (read_relative_register_raw_bytes (regnum
+ 1, raw_buffer
[LO
]))
2413 error ("can't read register %d (%s)",
2414 regnum
+ 1, REGISTER_NAME (regnum
+ 1));
2416 /* copy the two floats into one double, and unpack both */
2417 memcpy (dbl_buffer
, raw_buffer
, sizeof (dbl_buffer
));
2418 flt1
= unpack_double (builtin_type_float
, raw_buffer
[HI
], &inv1
);
2419 flt2
= unpack_double (builtin_type_float
, raw_buffer
[LO
], &inv2
);
2420 doub
= unpack_double (builtin_type_double
, dbl_buffer
, &inv3
);
2422 printf_filtered (inv1
? " %-5s: <invalid float>" :
2423 " %-5s%-17.9g", REGISTER_NAME (regnum
), flt1
);
2424 printf_filtered (inv2
? " %-5s: <invalid float>" :
2425 " %-5s%-17.9g", REGISTER_NAME (regnum
+ 1), flt2
);
2426 printf_filtered (inv3
? " dbl: <invalid double>\n" :
2427 " dbl: %-24.17g\n", doub
);
2428 /* may want to do hex display here (future enhancement) */
2432 { /* eight byte registers: print each one as float AND as double. */
2433 int offset
= 4 * (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2435 memcpy (dbl_buffer
, raw_buffer
[HI
], sizeof (dbl_buffer
));
2436 flt1
= unpack_double (builtin_type_float
,
2437 &raw_buffer
[HI
][offset
], &inv1
);
2438 doub
= unpack_double (builtin_type_double
, dbl_buffer
, &inv3
);
2440 printf_filtered (inv1
? " %-5s: <invalid float>" :
2441 " %-5s flt: %-17.9g", REGISTER_NAME (regnum
), flt1
);
2442 printf_filtered (inv3
? " dbl: <invalid double>\n" :
2443 " dbl: %-24.17g\n", doub
);
2444 /* may want to do hex display here (future enhancement) */
2450 /* Print a row's worth of GP (int) registers, with name labels above */
2453 do_gp_register_row (regnum
)
2456 /* do values for GP (int) regs */
2457 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2458 int ncols
= (MIPS_REGSIZE
== 8 ? 4 : 8); /* display cols per row */
2460 int start_regnum
= regnum
;
2461 int numregs
= NUM_REGS
;
2464 /* For GP registers, we print a separate row of names above the vals */
2465 printf_filtered (" ");
2466 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
2468 if (*REGISTER_NAME (regnum
) == '\0')
2469 continue; /* unused register */
2470 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2471 break; /* end the row: reached FP register */
2472 printf_filtered (MIPS_REGSIZE
== 8 ? "%17s" : "%9s",
2473 REGISTER_NAME (regnum
));
2476 printf_filtered (start_regnum
< MIPS_NUMREGS
? "\n R%-4d" : "\n ",
2477 start_regnum
); /* print the R0 to R31 names */
2479 regnum
= start_regnum
; /* go back to start of row */
2480 /* now print the values in hex, 4 or 8 to the row */
2481 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
2483 if (*REGISTER_NAME (regnum
) == '\0')
2484 continue; /* unused register */
2485 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2486 break; /* end row: reached FP register */
2487 /* OK: get the data in raw format. */
2488 if (read_relative_register_raw_bytes (regnum
, raw_buffer
))
2489 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
2490 /* pad small registers */
2491 for (byte
= 0; byte
< (MIPS_REGSIZE
- REGISTER_VIRTUAL_SIZE (regnum
)); byte
++)
2492 printf_filtered (" ");
2493 /* Now print the register value in hex, endian order. */
2494 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2495 for (byte
= REGISTER_RAW_SIZE (regnum
) - REGISTER_VIRTUAL_SIZE (regnum
);
2496 byte
< REGISTER_RAW_SIZE (regnum
);
2498 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
2500 for (byte
= REGISTER_VIRTUAL_SIZE (regnum
) - 1;
2503 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
2504 printf_filtered (" ");
2507 if (col
> 0) /* ie. if we actually printed anything... */
2508 printf_filtered ("\n");
2513 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
2516 mips_do_registers_info (regnum
, fpregs
)
2520 if (regnum
!= -1) /* do one specified register */
2522 if (*(REGISTER_NAME (regnum
)) == '\0')
2523 error ("Not a valid register for the current processor type");
2525 mips_print_register (regnum
, 0);
2526 printf_filtered ("\n");
2529 /* do all (or most) registers */
2532 while (regnum
< NUM_REGS
)
2534 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2535 if (fpregs
) /* true for "INFO ALL-REGISTERS" command */
2536 regnum
= do_fp_register_row (regnum
); /* FP regs */
2538 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
2540 regnum
= do_gp_register_row (regnum
); /* GP (int) regs */
2545 /* Return number of args passed to a frame. described by FIP.
2546 Can return -1, meaning no way to tell. */
2549 mips_frame_num_args (frame
)
2550 struct frame_info
*frame
;
2552 #if 0 /* FIXME Use or lose this! */
2553 struct chain_info_t
*p
;
2555 p
= mips_find_cached_frame (FRAME_FP (frame
));
2557 return p
->the_info
.numargs
;
2562 /* Is this a branch with a delay slot? */
2564 static int is_delayed
PARAMS ((unsigned long));
2571 for (i
= 0; i
< NUMOPCODES
; ++i
)
2572 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
2573 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
2575 return (i
< NUMOPCODES
2576 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
2577 | INSN_COND_BRANCH_DELAY
2578 | INSN_COND_BRANCH_LIKELY
)));
2582 mips_step_skips_delay (pc
)
2585 char buf
[MIPS_INSTLEN
];
2587 /* There is no branch delay slot on MIPS16. */
2588 if (pc_is_mips16 (pc
))
2591 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
2592 /* If error reading memory, guess that it is not a delayed branch. */
2594 return is_delayed ((unsigned long) extract_unsigned_integer (buf
, MIPS_INSTLEN
));
2598 /* Skip the PC past function prologue instructions (32-bit version).
2599 This is a helper function for mips_skip_prologue. */
2602 mips32_skip_prologue (pc
, lenient
)
2603 CORE_ADDR pc
; /* starting PC to search from */
2608 int seen_sp_adjust
= 0;
2609 int load_immediate_bytes
= 0;
2611 /* Skip the typical prologue instructions. These are the stack adjustment
2612 instruction and the instructions that save registers on the stack
2613 or in the gcc frame. */
2614 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
2616 unsigned long high_word
;
2618 inst
= mips_fetch_instruction (pc
);
2619 high_word
= (inst
>> 16) & 0xffff;
2622 if (lenient
&& is_delayed (inst
))
2626 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
2627 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
2629 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
2630 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
2632 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
2633 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
2634 && (inst
& 0x001F0000)) /* reg != $zero */
2637 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
2639 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
2641 continue; /* reg != $zero */
2643 /* move $s8,$sp. With different versions of gas this will be either
2644 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
2645 Accept any one of these. */
2646 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2649 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
2651 else if (high_word
== 0x3c1c) /* lui $gp,n */
2653 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
2655 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
2656 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
2658 /* The following instructions load $at or $t0 with an immediate
2659 value in preparation for a stack adjustment via
2660 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
2661 a local variable, so we accept them only before a stack adjustment
2662 instruction was seen. */
2663 else if (!seen_sp_adjust
)
2665 if (high_word
== 0x3c01 || /* lui $at,n */
2666 high_word
== 0x3c08) /* lui $t0,n */
2668 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
2671 else if (high_word
== 0x3421 || /* ori $at,$at,n */
2672 high_word
== 0x3508 || /* ori $t0,$t0,n */
2673 high_word
== 0x3401 || /* ori $at,$zero,n */
2674 high_word
== 0x3408) /* ori $t0,$zero,n */
2676 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
2686 /* In a frameless function, we might have incorrectly
2687 skipped some load immediate instructions. Undo the skipping
2688 if the load immediate was not followed by a stack adjustment. */
2689 if (load_immediate_bytes
&& !seen_sp_adjust
)
2690 pc
-= load_immediate_bytes
;
2694 /* Skip the PC past function prologue instructions (16-bit version).
2695 This is a helper function for mips_skip_prologue. */
2698 mips16_skip_prologue (pc
, lenient
)
2699 CORE_ADDR pc
; /* starting PC to search from */
2703 int extend_bytes
= 0;
2704 int prev_extend_bytes
;
2706 /* Table of instructions likely to be found in a function prologue. */
2709 unsigned short inst
;
2710 unsigned short mask
;
2717 , /* addiu $sp,offset */
2721 , /* daddiu $sp,offset */
2725 , /* sw reg,n($sp) */
2729 , /* sd reg,n($sp) */
2733 , /* sw $ra,n($sp) */
2737 , /* sd $ra,n($sp) */
2745 , /* sw $a0-$a3,n($s1) */
2749 , /* move reg,$a0-$a3 */
2753 , /* entry pseudo-op */
2757 , /* addiu $s1,$sp,n */
2760 } /* end of table marker */
2763 /* Skip the typical prologue instructions. These are the stack adjustment
2764 instruction and the instructions that save registers on the stack
2765 or in the gcc frame. */
2766 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
2768 unsigned short inst
;
2771 inst
= mips_fetch_instruction (pc
);
2773 /* Normally we ignore an extend instruction. However, if it is
2774 not followed by a valid prologue instruction, we must adjust
2775 the pc back over the extend so that it won't be considered
2776 part of the prologue. */
2777 if ((inst
& 0xf800) == 0xf000) /* extend */
2779 extend_bytes
= MIPS16_INSTLEN
;
2782 prev_extend_bytes
= extend_bytes
;
2785 /* Check for other valid prologue instructions besides extend. */
2786 for (i
= 0; table
[i
].mask
!= 0; i
++)
2787 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
2789 if (table
[i
].mask
!= 0) /* it was in table? */
2790 continue; /* ignore it */
2794 /* Return the current pc, adjusted backwards by 2 if
2795 the previous instruction was an extend. */
2796 return pc
- prev_extend_bytes
;
2802 /* To skip prologues, I use this predicate. Returns either PC itself
2803 if the code at PC does not look like a function prologue; otherwise
2804 returns an address that (if we're lucky) follows the prologue. If
2805 LENIENT, then we must skip everything which is involved in setting
2806 up the frame (it's OK to skip more, just so long as we don't skip
2807 anything which might clobber the registers which are being saved.
2808 We must skip more in the case where part of the prologue is in the
2809 delay slot of a non-prologue instruction). */
2812 mips_skip_prologue (pc
, lenient
)
2816 /* See if we can determine the end of the prologue via the symbol table.
2817 If so, then return either PC, or the PC after the prologue, whichever
2820 CORE_ADDR post_prologue_pc
= after_prologue (pc
, NULL
);
2822 if (post_prologue_pc
!= 0)
2823 return max (pc
, post_prologue_pc
);
2825 /* Can't determine prologue from the symbol table, need to examine
2828 if (pc_is_mips16 (pc
))
2829 return mips16_skip_prologue (pc
, lenient
);
2831 return mips32_skip_prologue (pc
, lenient
);
2835 /* The lenient prologue stuff should be superseded by the code in
2836 init_extra_frame_info which looks to see whether the stores mentioned
2837 in the proc_desc have actually taken place. */
2839 /* Is address PC in the prologue (loosely defined) for function at
2843 mips_in_lenient_prologue (startaddr
, pc
)
2844 CORE_ADDR startaddr
;
2847 CORE_ADDR end_prologue
= mips_skip_prologue (startaddr
, 1);
2848 return pc
>= startaddr
&& pc
< end_prologue
;
2852 /* Determine how a return value is stored within the MIPS register
2853 file, given the return type `valtype'. */
2855 struct return_value_word
2863 static void return_value_location
PARAMS ((struct type
*, struct return_value_word
*, struct return_value_word
*));
2866 return_value_location (valtype
, hi
, lo
)
2867 struct type
*valtype
;
2868 struct return_value_word
*hi
;
2869 struct return_value_word
*lo
;
2871 int len
= TYPE_LENGTH (valtype
);
2873 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
2874 && ((MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
&& (len
== 4 || len
== 8))
2875 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
&& len
== 4)))
2877 if (!FP_REGISTER_DOUBLE
&& len
== 8)
2879 /* We need to break a 64bit float in two 32 bit halves and
2880 spread them across a floating-point register pair. */
2881 lo
->buf_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 4 : 0;
2882 hi
->buf_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 0 : 4;
2883 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BIG_ENDIAN
2884 && REGISTER_RAW_SIZE (FP0_REGNUM
) == 8)
2886 hi
->reg_offset
= lo
->reg_offset
;
2887 lo
->reg
= FP0_REGNUM
+ 0;
2888 hi
->reg
= FP0_REGNUM
+ 1;
2894 /* The floating point value fits in a single floating-point
2896 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BIG_ENDIAN
2897 && REGISTER_RAW_SIZE (FP0_REGNUM
) == 8
2900 lo
->reg
= FP0_REGNUM
;
2911 /* Locate a result possibly spread across two registers. */
2913 lo
->reg
= regnum
+ 0;
2914 hi
->reg
= regnum
+ 1;
2915 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
2916 && len
< MIPS_SAVED_REGSIZE
)
2918 /* "un-left-justify" the value in the low register */
2919 lo
->reg_offset
= MIPS_SAVED_REGSIZE
- len
;
2924 else if (TARGET_BYTE_ORDER
== BIG_ENDIAN
2925 && len
> MIPS_SAVED_REGSIZE
/* odd-size structs */
2926 && len
< MIPS_SAVED_REGSIZE
* 2
2927 && (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
2928 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
2930 /* "un-left-justify" the value spread across two registers. */
2931 lo
->reg_offset
= 2 * MIPS_SAVED_REGSIZE
- len
;
2932 lo
->len
= MIPS_SAVED_REGSIZE
- lo
->reg_offset
;
2934 hi
->len
= len
- lo
->len
;
2938 /* Only perform a partial copy of the second register. */
2941 if (len
> MIPS_SAVED_REGSIZE
)
2943 lo
->len
= MIPS_SAVED_REGSIZE
;
2944 hi
->len
= len
- MIPS_SAVED_REGSIZE
;
2952 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
2953 && REGISTER_RAW_SIZE (regnum
) == 8
2954 && MIPS_SAVED_REGSIZE
== 4)
2956 /* Account for the fact that only the least-signficant part
2957 of the register is being used */
2958 lo
->reg_offset
+= 4;
2959 hi
->reg_offset
+= 4;
2962 hi
->buf_offset
= lo
->len
;
2966 /* Given a return value in `regbuf' with a type `valtype', extract and
2967 copy its value into `valbuf'. */
2970 mips_extract_return_value (valtype
, regbuf
, valbuf
)
2971 struct type
*valtype
;
2972 char regbuf
[REGISTER_BYTES
];
2975 struct return_value_word lo
;
2976 struct return_value_word hi
;
2977 return_value_location (valtype
, &lo
, &hi
);
2979 memcpy (valbuf
+ lo
.buf_offset
,
2980 regbuf
+ REGISTER_BYTE (lo
.reg
) + lo
.reg_offset
,
2984 memcpy (valbuf
+ hi
.buf_offset
,
2985 regbuf
+ REGISTER_BYTE (hi
.reg
) + hi
.reg_offset
,
2991 int len
= TYPE_LENGTH (valtype
);
2994 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
2995 && (MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
2996 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
2997 && len
<= MIPS_FPU_SINGLE_REGSIZE
)))
2998 regnum
= FP0_REGNUM
;
3000 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
3001 { /* "un-left-justify" the value from the register */
3002 if (len
< REGISTER_RAW_SIZE (regnum
))
3003 offset
= REGISTER_RAW_SIZE (regnum
) - len
;
3004 if (len
> REGISTER_RAW_SIZE (regnum
) && /* odd-size structs */
3005 len
< REGISTER_RAW_SIZE (regnum
) * 2 &&
3006 (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
3007 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
3008 offset
= 2 * REGISTER_RAW_SIZE (regnum
) - len
;
3010 memcpy (valbuf
, regbuf
+ REGISTER_BYTE (regnum
) + offset
, len
);
3011 REGISTER_CONVERT_TO_TYPE (regnum
, valtype
, valbuf
);
3015 /* Given a return value in `valbuf' with a type `valtype', write it's
3016 value into the appropriate register. */
3019 mips_store_return_value (valtype
, valbuf
)
3020 struct type
*valtype
;
3023 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
3024 struct return_value_word lo
;
3025 struct return_value_word hi
;
3026 return_value_location (valtype
, &lo
, &hi
);
3028 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3029 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
3030 write_register_bytes (REGISTER_BYTE (lo
.reg
),
3032 REGISTER_RAW_SIZE (lo
.reg
));
3036 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3037 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
3038 write_register_bytes (REGISTER_BYTE (hi
.reg
),
3040 REGISTER_RAW_SIZE (hi
.reg
));
3046 int len
= TYPE_LENGTH (valtype
);
3047 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
3050 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
3051 && (MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
3052 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
3053 && len
<= MIPS_REGSIZE
)))
3054 regnum
= FP0_REGNUM
;
3056 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
3057 { /* "left-justify" the value in the register */
3058 if (len
< REGISTER_RAW_SIZE (regnum
))
3059 offset
= REGISTER_RAW_SIZE (regnum
) - len
;
3060 if (len
> REGISTER_RAW_SIZE (regnum
) && /* odd-size structs */
3061 len
< REGISTER_RAW_SIZE (regnum
) * 2 &&
3062 (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
3063 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
3064 offset
= 2 * REGISTER_RAW_SIZE (regnum
) - len
;
3066 memcpy (raw_buffer
+ offset
, valbuf
, len
);
3067 REGISTER_CONVERT_FROM_TYPE (regnum
, valtype
, raw_buffer
);
3068 write_register_bytes (REGISTER_BYTE (regnum
), raw_buffer
,
3069 len
> REGISTER_RAW_SIZE (regnum
) ?
3070 len
: REGISTER_RAW_SIZE (regnum
));
3074 /* Exported procedure: Is PC in the signal trampoline code */
3077 in_sigtramp (pc
, ignore
)
3079 char *ignore
; /* function name */
3081 if (sigtramp_address
== 0)
3083 return (pc
>= sigtramp_address
&& pc
< sigtramp_end
);
3086 /* Commands to show/set the MIPS FPU type. */
3088 static void show_mipsfpu_command
PARAMS ((char *, int));
3090 show_mipsfpu_command (args
, from_tty
)
3096 switch (MIPS_FPU_TYPE
)
3098 case MIPS_FPU_SINGLE
:
3099 fpu
= "single-precision";
3101 case MIPS_FPU_DOUBLE
:
3102 fpu
= "double-precision";
3105 fpu
= "absent (none)";
3108 if (mips_fpu_type_auto
)
3109 printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
3112 printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n",
3117 static void set_mipsfpu_command
PARAMS ((char *, int));
3119 set_mipsfpu_command (args
, from_tty
)
3123 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
3124 show_mipsfpu_command (args
, from_tty
);
3127 static void set_mipsfpu_single_command
PARAMS ((char *, int));
3129 set_mipsfpu_single_command (args
, from_tty
)
3133 mips_fpu_type
= MIPS_FPU_SINGLE
;
3134 mips_fpu_type_auto
= 0;
3137 static void set_mipsfpu_double_command
PARAMS ((char *, int));
3139 set_mipsfpu_double_command (args
, from_tty
)
3143 mips_fpu_type
= MIPS_FPU_DOUBLE
;
3144 mips_fpu_type_auto
= 0;
3147 static void set_mipsfpu_none_command
PARAMS ((char *, int));
3149 set_mipsfpu_none_command (args
, from_tty
)
3153 mips_fpu_type
= MIPS_FPU_NONE
;
3154 mips_fpu_type_auto
= 0;
3157 static void set_mipsfpu_auto_command
PARAMS ((char *, int));
3159 set_mipsfpu_auto_command (args
, from_tty
)
3163 mips_fpu_type_auto
= 1;
3166 /* Command to set the processor type. */
3169 mips_set_processor_type_command (args
, from_tty
)
3175 if (tmp_mips_processor_type
== NULL
|| *tmp_mips_processor_type
== '\0')
3177 printf_unfiltered ("The known MIPS processor types are as follows:\n\n");
3178 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
3179 printf_unfiltered ("%s\n", mips_processor_type_table
[i
].name
);
3181 /* Restore the value. */
3182 tmp_mips_processor_type
= strsave (mips_processor_type
);
3187 if (!mips_set_processor_type (tmp_mips_processor_type
))
3189 error ("Unknown processor type `%s'.", tmp_mips_processor_type
);
3190 /* Restore its value. */
3191 tmp_mips_processor_type
= strsave (mips_processor_type
);
3196 mips_show_processor_type_command (args
, from_tty
)
3202 /* Modify the actual processor type. */
3205 mips_set_processor_type (str
)
3213 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
3215 if (strcasecmp (str
, mips_processor_type_table
[i
].name
) == 0)
3217 mips_processor_type
= str
;
3218 mips_processor_reg_names
= mips_processor_type_table
[i
].regnames
;
3220 /* FIXME tweak fpu flag too */
3227 /* Attempt to identify the particular processor model by reading the
3231 mips_read_processor_type ()
3235 prid
= read_register (PRID_REGNUM
);
3237 if ((prid
& ~0xf) == 0x700)
3238 return savestring ("r3041", strlen ("r3041"));
3243 /* Just like reinit_frame_cache, but with the right arguments to be
3244 callable as an sfunc. */
3247 reinit_frame_cache_sfunc (args
, from_tty
, c
)
3250 struct cmd_list_element
*c
;
3252 reinit_frame_cache ();
3256 gdb_print_insn_mips (memaddr
, info
)
3258 disassemble_info
*info
;
3260 mips_extra_func_info_t proc_desc
;
3262 /* Search for the function containing this address. Set the low bit
3263 of the address when searching, in case we were given an even address
3264 that is the start of a 16-bit function. If we didn't do this,
3265 the search would fail because the symbol table says the function
3266 starts at an odd address, i.e. 1 byte past the given address. */
3267 memaddr
= ADDR_BITS_REMOVE (memaddr
);
3268 proc_desc
= non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr
), NULL
);
3270 /* Make an attempt to determine if this is a 16-bit function. If
3271 the procedure descriptor exists and the address therein is odd,
3272 it's definitely a 16-bit function. Otherwise, we have to just
3273 guess that if the address passed in is odd, it's 16-bits. */
3275 info
->mach
= pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)) ? 16 : TM_PRINT_INSN_MACH
;
3277 info
->mach
= pc_is_mips16 (memaddr
) ? 16 : TM_PRINT_INSN_MACH
;
3279 /* Round down the instruction address to the appropriate boundary. */
3280 memaddr
&= (info
->mach
== 16 ? ~1 : ~3);
3282 /* Call the appropriate disassembler based on the target endian-ness. */
3283 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
3284 return print_insn_big_mips (memaddr
, info
);
3286 return print_insn_little_mips (memaddr
, info
);
3289 /* Old-style breakpoint macros.
3290 The IDT board uses an unusual breakpoint value, and sometimes gets
3291 confused when it sees the usual MIPS breakpoint instruction. */
3293 #define BIG_BREAKPOINT {0, 0x5, 0, 0xd}
3294 #define LITTLE_BREAKPOINT {0xd, 0, 0x5, 0}
3295 #define PMON_BIG_BREAKPOINT {0, 0, 0, 0xd}
3296 #define PMON_LITTLE_BREAKPOINT {0xd, 0, 0, 0}
3297 #define IDT_BIG_BREAKPOINT {0, 0, 0x0a, 0xd}
3298 #define IDT_LITTLE_BREAKPOINT {0xd, 0x0a, 0, 0}
3299 #define MIPS16_BIG_BREAKPOINT {0xe8, 0xa5}
3300 #define MIPS16_LITTLE_BREAKPOINT {0xa5, 0xe8}
3302 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
3303 counter value to determine whether a 16- or 32-bit breakpoint should be
3304 used. It returns a pointer to a string of bytes that encode a breakpoint
3305 instruction, stores the length of the string to *lenptr, and adjusts pc
3306 (if necessary) to point to the actual memory location where the
3307 breakpoint should be inserted. */
3310 mips_breakpoint_from_pc (pcptr
, lenptr
)
3314 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
3316 if (pc_is_mips16 (*pcptr
))
3318 static char mips16_big_breakpoint
[] = MIPS16_BIG_BREAKPOINT
;
3319 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
3320 *lenptr
= sizeof (mips16_big_breakpoint
);
3321 return mips16_big_breakpoint
;
3325 static char big_breakpoint
[] = BIG_BREAKPOINT
;
3326 static char pmon_big_breakpoint
[] = PMON_BIG_BREAKPOINT
;
3327 static char idt_big_breakpoint
[] = IDT_BIG_BREAKPOINT
;
3329 *lenptr
= sizeof (big_breakpoint
);
3331 if (strcmp (target_shortname
, "mips") == 0)
3332 return idt_big_breakpoint
;
3333 else if (strcmp (target_shortname
, "ddb") == 0
3334 || strcmp (target_shortname
, "pmon") == 0
3335 || strcmp (target_shortname
, "lsi") == 0)
3336 return pmon_big_breakpoint
;
3338 return big_breakpoint
;
3343 if (pc_is_mips16 (*pcptr
))
3345 static char mips16_little_breakpoint
[] = MIPS16_LITTLE_BREAKPOINT
;
3346 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
3347 *lenptr
= sizeof (mips16_little_breakpoint
);
3348 return mips16_little_breakpoint
;
3352 static char little_breakpoint
[] = LITTLE_BREAKPOINT
;
3353 static char pmon_little_breakpoint
[] = PMON_LITTLE_BREAKPOINT
;
3354 static char idt_little_breakpoint
[] = IDT_LITTLE_BREAKPOINT
;
3356 *lenptr
= sizeof (little_breakpoint
);
3358 if (strcmp (target_shortname
, "mips") == 0)
3359 return idt_little_breakpoint
;
3360 else if (strcmp (target_shortname
, "ddb") == 0
3361 || strcmp (target_shortname
, "pmon") == 0
3362 || strcmp (target_shortname
, "lsi") == 0)
3363 return pmon_little_breakpoint
;
3365 return little_breakpoint
;
3370 /* If PC is in a mips16 call or return stub, return the address of the target
3371 PC, which is either the callee or the caller. There are several
3372 cases which must be handled:
3374 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3375 target PC is in $31 ($ra).
3376 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3377 and the target PC is in $2.
3378 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3379 before the jal instruction, this is effectively a call stub
3380 and the the target PC is in $2. Otherwise this is effectively
3381 a return stub and the target PC is in $18.
3383 See the source code for the stubs in gcc/config/mips/mips16.S for
3386 This function implements the SKIP_TRAMPOLINE_CODE macro.
3394 CORE_ADDR start_addr
;
3396 /* Find the starting address and name of the function containing the PC. */
3397 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
3400 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3401 target PC is in $31 ($ra). */
3402 if (strcmp (name
, "__mips16_ret_sf") == 0
3403 || strcmp (name
, "__mips16_ret_df") == 0)
3404 return read_register (RA_REGNUM
);
3406 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
3408 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3409 and the target PC is in $2. */
3410 if (name
[19] >= '0' && name
[19] <= '9')
3411 return read_register (2);
3413 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3414 before the jal instruction, this is effectively a call stub
3415 and the the target PC is in $2. Otherwise this is effectively
3416 a return stub and the target PC is in $18. */
3417 else if (name
[19] == 's' || name
[19] == 'd')
3419 if (pc
== start_addr
)
3421 /* Check if the target of the stub is a compiler-generated
3422 stub. Such a stub for a function bar might have a name
3423 like __fn_stub_bar, and might look like this:
3428 la $1,bar (becomes a lui/addiu pair)
3430 So scan down to the lui/addi and extract the target
3431 address from those two instructions. */
3433 CORE_ADDR target_pc
= read_register (2);
3437 /* See if the name of the target function is __fn_stub_*. */
3438 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) == 0)
3440 if (strncmp (name
, "__fn_stub_", 10) != 0
3441 && strcmp (name
, "etext") != 0
3442 && strcmp (name
, "_etext") != 0)
3445 /* Scan through this _fn_stub_ code for the lui/addiu pair.
3446 The limit on the search is arbitrarily set to 20
3447 instructions. FIXME. */
3448 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
3450 inst
= mips_fetch_instruction (target_pc
);
3451 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
3452 pc
= (inst
<< 16) & 0xffff0000; /* high word */
3453 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
3454 return pc
| (inst
& 0xffff); /* low word */
3457 /* Couldn't find the lui/addui pair, so return stub address. */
3461 /* This is the 'return' part of a call stub. The return
3462 address is in $r18. */
3463 return read_register (18);
3466 return 0; /* not a stub */
3470 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
3471 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
3474 mips_in_call_stub (pc
, name
)
3478 CORE_ADDR start_addr
;
3480 /* Find the starting address of the function containing the PC. If the
3481 caller didn't give us a name, look it up at the same time. */
3482 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
3485 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
3487 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
3488 if (name
[19] >= '0' && name
[19] <= '9')
3490 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3491 before the jal instruction, this is effectively a call stub. */
3492 else if (name
[19] == 's' || name
[19] == 'd')
3493 return pc
== start_addr
;
3496 return 0; /* not a stub */
3500 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
3501 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
3504 mips_in_return_stub (pc
, name
)
3508 CORE_ADDR start_addr
;
3510 /* Find the starting address of the function containing the PC. */
3511 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
3514 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
3515 if (strcmp (name
, "__mips16_ret_sf") == 0
3516 || strcmp (name
, "__mips16_ret_df") == 0)
3519 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
3520 i.e. after the jal instruction, this is effectively a return stub. */
3521 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
3522 && (name
[19] == 's' || name
[19] == 'd')
3523 && pc
!= start_addr
)
3526 return 0; /* not a stub */
3530 /* Return non-zero if the PC is in a library helper function that should
3531 be ignored. This implements the IGNORE_HELPER_CALL macro. */
3534 mips_ignore_helper (pc
)
3539 /* Find the starting address and name of the function containing the PC. */
3540 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
3543 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
3544 that we want to ignore. */
3545 return (strcmp (name
, "__mips16_ret_sf") == 0
3546 || strcmp (name
, "__mips16_ret_df") == 0);
3550 /* Return a location where we can set a breakpoint that will be hit
3551 when an inferior function call returns. This is normally the
3552 program's entry point. Executables that don't have an entry
3553 point (e.g. programs in ROM) should define a symbol __CALL_DUMMY_ADDRESS
3554 whose address is the location where the breakpoint should be placed. */
3557 mips_call_dummy_address ()
3559 struct minimal_symbol
*sym
;
3561 sym
= lookup_minimal_symbol ("__CALL_DUMMY_ADDRESS", NULL
, NULL
);
3563 return SYMBOL_VALUE_ADDRESS (sym
);
3565 return entry_point_address ();
3570 _initialize_mips_tdep ()
3572 static struct cmd_list_element
*mipsfpulist
= NULL
;
3573 struct cmd_list_element
*c
;
3575 if (!tm_print_insn
) /* Someone may have already set it */
3576 tm_print_insn
= gdb_print_insn_mips
;
3578 /* Let the user turn off floating point and set the fence post for
3579 heuristic_proc_start. */
3581 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
3582 "Set use of MIPS floating-point coprocessor.",
3583 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
3584 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
3585 "Select single-precision MIPS floating-point coprocessor.",
3587 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
3588 "Select double-precision MIPS floating-point coprocessor .",
3590 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
3591 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
3592 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
3593 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
3594 "Select no MIPS floating-point coprocessor.",
3596 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
3597 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
3598 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
3599 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
3600 "Select MIPS floating-point coprocessor automatically.",
3602 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
3603 "Show current use of MIPS floating-point coprocessor target.",
3606 c
= add_set_cmd ("processor", class_support
, var_string_noescape
,
3607 (char *) &tmp_mips_processor_type
,
3608 "Set the type of MIPS processor in use.\n\
3609 Set this to be able to access processor-type-specific registers.\n\
3612 c
->function
.cfunc
= mips_set_processor_type_command
;
3613 c
= add_show_from_set (c
, &showlist
);
3614 c
->function
.cfunc
= mips_show_processor_type_command
;
3616 tmp_mips_processor_type
= strsave (DEFAULT_MIPS_TYPE
);
3617 mips_set_processor_type_command (strsave (DEFAULT_MIPS_TYPE
), 0);
3619 /* We really would like to have both "0" and "unlimited" work, but
3620 command.c doesn't deal with that. So make it a var_zinteger
3621 because the user can always use "999999" or some such for unlimited. */
3622 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
3623 (char *) &heuristic_fence_post
,
3625 Set the distance searched for the start of a function.\n\
3626 If you are debugging a stripped executable, GDB needs to search through the\n\
3627 program for the start of a function. This command sets the distance of the\n\
3628 search. The only need to set it is when debugging a stripped executable.",
3630 /* We need to throw away the frame cache when we set this, since it
3631 might change our ability to get backtraces. */
3632 c
->function
.sfunc
= reinit_frame_cache_sfunc
;
3633 add_show_from_set (c
, &showlist
);
3635 /* Allow the user to control whether the upper bits of 64-bit
3636 addresses should be zeroed. */
3638 (add_set_cmd ("mask-address", no_class
, var_boolean
, (char *) &mask_address_p
,
3639 "Set zeroing of upper 32 bits of 64-bit addresses.\n\
3640 Use \"on\" to enable the masking, and \"off\" to disable it.\n\
3641 Without an argument, zeroing of upper address bits is enabled.", &setlist
),
3644 /* Allow the user to control the size of 32 bit registers within the
3645 raw remote packet. */
3646 add_show_from_set (add_set_cmd ("remote-mips64-transfers-32bit-regs",
3649 (char *)&mips64_transfers_32bit_regs_p
, "\
3650 Set compatibility with MIPS targets that transfers 32 and 64 bit quantities.\n\
3651 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
3652 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
3653 64 bits for others. Use \"off\" to disable compatibility mode",