1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
5 Free Software Foundation, Inc.
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program. If not, see <http://www.gnu.org/licenses/>. */
26 #include "gdb_string.h"
27 #include "gdb_assert.h"
39 #include "arch-utils.h"
42 #include "mips-tdep.h"
44 #include "reggroups.h"
45 #include "opcode/mips.h"
49 #include "sim-regno.h"
51 #include "frame-unwind.h"
52 #include "frame-base.h"
53 #include "trad-frame.h"
55 #include "floatformat.h"
57 #include "target-descriptions.h"
58 #include "dwarf2-frame.h"
59 #include "user-regs.h"
61 static const struct objfile_data
*mips_pdr_data
;
63 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
65 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
66 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
67 #define ST0_FR (1 << 26)
69 /* The sizes of floating point registers. */
73 MIPS_FPU_SINGLE_REGSIZE
= 4,
74 MIPS_FPU_DOUBLE_REGSIZE
= 8
83 static const char *mips_abi_string
;
85 static const char *mips_abi_strings
[] = {
96 /* The standard register names, and all the valid aliases for them. */
103 /* Aliases for o32 and most other ABIs. */
104 const struct register_alias mips_o32_aliases
[] = {
111 /* Aliases for n32 and n64. */
112 const struct register_alias mips_n32_n64_aliases
[] = {
119 /* Aliases for ABI-independent registers. */
120 const struct register_alias mips_register_aliases
[] = {
121 /* The architecture manuals specify these ABI-independent names for
123 #define R(n) { "r" #n, n }
124 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
125 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
126 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
127 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
130 /* k0 and k1 are sometimes called these instead (for "kernel
135 /* This is the traditional GDB name for the CP0 status register. */
136 { "sr", MIPS_PS_REGNUM
},
138 /* This is the traditional GDB name for the CP0 BadVAddr register. */
139 { "bad", MIPS_EMBED_BADVADDR_REGNUM
},
141 /* This is the traditional GDB name for the FCSR. */
142 { "fsr", MIPS_EMBED_FP0_REGNUM
+ 32 }
145 /* Some MIPS boards don't support floating point while others only
146 support single-precision floating-point operations. */
150 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
151 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
152 MIPS_FPU_NONE
/* No floating point. */
155 #ifndef MIPS_DEFAULT_FPU_TYPE
156 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
158 static int mips_fpu_type_auto
= 1;
159 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
161 static int mips_debug
= 0;
163 /* Properties (for struct target_desc) describing the g/G packet
165 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
166 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
168 struct target_desc
*mips_tdesc_gp32
;
169 struct target_desc
*mips_tdesc_gp64
;
171 /* MIPS specific per-architecture information */
174 /* from the elf header */
178 enum mips_abi mips_abi
;
179 enum mips_abi found_abi
;
180 enum mips_fpu_type mips_fpu_type
;
181 int mips_last_arg_regnum
;
182 int mips_last_fp_arg_regnum
;
183 int default_mask_address_p
;
184 /* Is the target using 64-bit raw integer registers but only
185 storing a left-aligned 32-bit value in each? */
186 int mips64_transfers_32bit_regs_p
;
187 /* Indexes for various registers. IRIX and embedded have
188 different values. This contains the "public" fields. Don't
189 add any that do not need to be public. */
190 const struct mips_regnum
*regnum
;
191 /* Register names table for the current register set. */
192 const char **mips_processor_reg_names
;
194 /* The size of register data available from the target, if known.
195 This doesn't quite obsolete the manual
196 mips64_transfers_32bit_regs_p, since that is documented to force
197 left alignment even for big endian (very strange). */
198 int register_size_valid_p
;
202 const struct mips_regnum
*
203 mips_regnum (struct gdbarch
*gdbarch
)
205 return gdbarch_tdep (gdbarch
)->regnum
;
209 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
211 return mips_regnum (gdbarch
)->fp0
+ 12;
214 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
215 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
217 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
219 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
221 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
223 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
224 functions to test, set, or clear bit 0 of addresses. */
227 is_mips16_addr (CORE_ADDR addr
)
233 unmake_mips16_addr (CORE_ADDR addr
)
235 return ((addr
) & ~(CORE_ADDR
) 1);
238 /* Return the MIPS ABI associated with GDBARCH. */
240 mips_abi (struct gdbarch
*gdbarch
)
242 return gdbarch_tdep (gdbarch
)->mips_abi
;
246 mips_isa_regsize (struct gdbarch
*gdbarch
)
248 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
250 /* If we know how big the registers are, use that size. */
251 if (tdep
->register_size_valid_p
)
252 return tdep
->register_size
;
254 /* Fall back to the previous behavior. */
255 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
256 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
259 /* Return the currently configured (or set) saved register size. */
262 mips_abi_regsize (struct gdbarch
*gdbarch
)
264 switch (mips_abi (gdbarch
))
266 case MIPS_ABI_EABI32
:
272 case MIPS_ABI_EABI64
:
274 case MIPS_ABI_UNKNOWN
:
277 internal_error (__FILE__
, __LINE__
, _("bad switch"));
281 /* Functions for setting and testing a bit in a minimal symbol that
282 marks it as 16-bit function. The MSB of the minimal symbol's
283 "info" field is used for this purpose.
285 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special",
286 i.e. refers to a 16-bit function, and sets a "special" bit in a
287 minimal symbol to mark it as a 16-bit function
289 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
292 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
294 if (((elf_symbol_type
*) (sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
296 MSYMBOL_INFO (msym
) = (char *)
297 (((long) MSYMBOL_INFO (msym
)) | 0x80000000);
298 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
303 msymbol_is_special (struct minimal_symbol
*msym
)
305 return (((long) MSYMBOL_INFO (msym
) & 0x80000000) != 0);
308 /* XFER a value from the big/little/left end of the register.
309 Depending on the size of the value it might occupy the entire
310 register or just part of it. Make an allowance for this, aligning
311 things accordingly. */
314 mips_xfer_register (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
315 int reg_num
, int length
,
316 enum bfd_endian endian
, gdb_byte
*in
,
317 const gdb_byte
*out
, int buf_offset
)
321 gdb_assert (reg_num
>= gdbarch_num_regs (gdbarch
));
322 /* Need to transfer the left or right part of the register, based on
323 the targets byte order. */
327 reg_offset
= register_size (gdbarch
, reg_num
) - length
;
329 case BFD_ENDIAN_LITTLE
:
332 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
336 internal_error (__FILE__
, __LINE__
, _("bad switch"));
339 fprintf_unfiltered (gdb_stderr
,
340 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
341 reg_num
, reg_offset
, buf_offset
, length
);
342 if (mips_debug
&& out
!= NULL
)
345 fprintf_unfiltered (gdb_stdlog
, "out ");
346 for (i
= 0; i
< length
; i
++)
347 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
350 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
353 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
355 if (mips_debug
&& in
!= NULL
)
358 fprintf_unfiltered (gdb_stdlog
, "in ");
359 for (i
= 0; i
< length
; i
++)
360 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
363 fprintf_unfiltered (gdb_stdlog
, "\n");
366 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
367 compatiblity mode. A return value of 1 means that we have
368 physical 64-bit registers, but should treat them as 32-bit registers. */
371 mips2_fp_compat (struct frame_info
*frame
)
373 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
374 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
376 if (register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) == 4)
380 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
381 in all the places we deal with FP registers. PR gdb/413. */
382 /* Otherwise check the FR bit in the status register - it controls
383 the FP compatiblity mode. If it is clear we are in compatibility
385 if ((get_frame_register_unsigned (frame
, MIPS_PS_REGNUM
) & ST0_FR
) == 0)
392 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
394 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
396 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
398 static struct type
*mips_float_register_type (void);
399 static struct type
*mips_double_register_type (void);
401 /* The list of available "set mips " and "show mips " commands */
403 static struct cmd_list_element
*setmipscmdlist
= NULL
;
404 static struct cmd_list_element
*showmipscmdlist
= NULL
;
406 /* Integer registers 0 thru 31 are handled explicitly by
407 mips_register_name(). Processor specific registers 32 and above
408 are listed in the following tables. */
411 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
415 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
416 "sr", "lo", "hi", "bad", "cause", "pc",
417 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
418 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
419 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
420 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
421 "fsr", "fir", "" /*"fp" */ , "",
422 "", "", "", "", "", "", "", "",
423 "", "", "", "", "", "", "", "",
426 /* Names of IDT R3041 registers. */
428 static const char *mips_r3041_reg_names
[] = {
429 "sr", "lo", "hi", "bad", "cause", "pc",
430 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
431 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
432 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
433 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
434 "fsr", "fir", "", /*"fp" */ "",
435 "", "", "bus", "ccfg", "", "", "", "",
436 "", "", "port", "cmp", "", "", "epc", "prid",
439 /* Names of tx39 registers. */
441 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
442 "sr", "lo", "hi", "bad", "cause", "pc",
443 "", "", "", "", "", "", "", "",
444 "", "", "", "", "", "", "", "",
445 "", "", "", "", "", "", "", "",
446 "", "", "", "", "", "", "", "",
448 "", "", "", "", "", "", "", "",
449 "", "", "config", "cache", "debug", "depc", "epc", ""
452 /* Names of IRIX registers. */
453 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
454 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
455 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
456 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
457 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
458 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
462 /* Return the name of the register corresponding to REGNO. */
464 mips_register_name (struct gdbarch
*gdbarch
, int regno
)
466 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
467 /* GPR names for all ABIs other than n32/n64. */
468 static char *mips_gpr_names
[] = {
469 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
470 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
471 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
472 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
475 /* GPR names for n32 and n64 ABIs. */
476 static char *mips_n32_n64_gpr_names
[] = {
477 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
478 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
479 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
480 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
483 enum mips_abi abi
= mips_abi (gdbarch
);
485 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
486 but then don't make the raw register names visible. */
487 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
488 if (regno
< gdbarch_num_regs (gdbarch
))
491 /* The MIPS integer registers are always mapped from 0 to 31. The
492 names of the registers (which reflects the conventions regarding
493 register use) vary depending on the ABI. */
494 if (0 <= rawnum
&& rawnum
< 32)
496 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
497 return mips_n32_n64_gpr_names
[rawnum
];
499 return mips_gpr_names
[rawnum
];
501 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
502 return tdesc_register_name (gdbarch
, rawnum
);
503 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (gdbarch
))
505 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
506 return tdep
->mips_processor_reg_names
[rawnum
- 32];
509 internal_error (__FILE__
, __LINE__
,
510 _("mips_register_name: bad register number %d"), rawnum
);
513 /* Return the groups that a MIPS register can be categorised into. */
516 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
517 struct reggroup
*reggroup
)
522 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
523 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
524 if (reggroup
== all_reggroup
)
526 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
527 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
528 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
529 (gdbarch), as not all architectures are multi-arch. */
530 raw_p
= rawnum
< gdbarch_num_regs (gdbarch
);
531 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
532 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
534 if (reggroup
== float_reggroup
)
535 return float_p
&& pseudo
;
536 if (reggroup
== vector_reggroup
)
537 return vector_p
&& pseudo
;
538 if (reggroup
== general_reggroup
)
539 return (!vector_p
&& !float_p
) && pseudo
;
540 /* Save the pseudo registers. Need to make certain that any code
541 extracting register values from a saved register cache also uses
543 if (reggroup
== save_reggroup
)
544 return raw_p
&& pseudo
;
545 /* Restore the same pseudo register. */
546 if (reggroup
== restore_reggroup
)
547 return raw_p
&& pseudo
;
551 /* Return the groups that a MIPS register can be categorised into.
552 This version is only used if we have a target description which
553 describes real registers (and their groups). */
556 mips_tdesc_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
557 struct reggroup
*reggroup
)
559 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
560 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
563 /* Only save, restore, and display the pseudo registers. Need to
564 make certain that any code extracting register values from a
565 saved register cache also uses pseudo registers.
567 Note: saving and restoring the pseudo registers is slightly
568 strange; if we have 64 bits, we should save and restore all
569 64 bits. But this is hard and has little benefit. */
573 ret
= tdesc_register_in_reggroup_p (gdbarch
, rawnum
, reggroup
);
577 return mips_register_reggroup_p (gdbarch
, regnum
, reggroup
);
580 /* Map the symbol table registers which live in the range [1 *
581 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
582 registers. Take care of alignment and size problems. */
585 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
586 int cookednum
, gdb_byte
*buf
)
588 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
589 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
590 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
591 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
592 regcache_raw_read (regcache
, rawnum
, buf
);
593 else if (register_size (gdbarch
, rawnum
) >
594 register_size (gdbarch
, cookednum
))
596 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
597 || gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
598 regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
600 regcache_raw_read_part (regcache
, rawnum
, 4, 4, buf
);
603 internal_error (__FILE__
, __LINE__
, _("bad register size"));
607 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
608 struct regcache
*regcache
, int cookednum
,
611 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
612 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
613 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
614 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
615 regcache_raw_write (regcache
, rawnum
, buf
);
616 else if (register_size (gdbarch
, rawnum
) >
617 register_size (gdbarch
, cookednum
))
619 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
620 || gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
621 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
623 regcache_raw_write_part (regcache
, rawnum
, 4, 4, buf
);
626 internal_error (__FILE__
, __LINE__
, _("bad register size"));
629 /* Table to translate MIPS16 register field to actual register number. */
630 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
632 /* Heuristic_proc_start may hunt through the text section for a long
633 time across a 2400 baud serial line. Allows the user to limit this
636 static unsigned int heuristic_fence_post
= 0;
638 /* Number of bytes of storage in the actual machine representation for
639 register N. NOTE: This defines the pseudo register type so need to
640 rebuild the architecture vector. */
642 static int mips64_transfers_32bit_regs_p
= 0;
645 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
646 struct cmd_list_element
*c
)
648 struct gdbarch_info info
;
649 gdbarch_info_init (&info
);
650 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
651 instead of relying on globals. Doing that would let generic code
652 handle the search for this specific architecture. */
653 if (!gdbarch_update_p (info
))
655 mips64_transfers_32bit_regs_p
= 0;
656 error (_("32-bit compatibility mode not supported"));
660 /* Convert to/from a register and the corresponding memory value. */
663 mips_convert_register_p (struct gdbarch
*gdbarch
, int regnum
, struct type
*type
)
665 return (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
666 && register_size (gdbarch
, regnum
) == 4
667 && (regnum
% gdbarch_num_regs (gdbarch
))
668 >= mips_regnum (gdbarch
)->fp0
669 && (regnum
% gdbarch_num_regs (gdbarch
))
670 < mips_regnum (gdbarch
)->fp0
+ 32
671 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
675 mips_register_to_value (struct frame_info
*frame
, int regnum
,
676 struct type
*type
, gdb_byte
*to
)
678 get_frame_register (frame
, regnum
+ 0, to
+ 4);
679 get_frame_register (frame
, regnum
+ 1, to
+ 0);
683 mips_value_to_register (struct frame_info
*frame
, int regnum
,
684 struct type
*type
, const gdb_byte
*from
)
686 put_frame_register (frame
, regnum
+ 0, from
+ 4);
687 put_frame_register (frame
, regnum
+ 1, from
+ 0);
690 /* Return the GDB type object for the "standard" data type of data in
694 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
696 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (gdbarch
));
697 if ((regnum
% gdbarch_num_regs (gdbarch
)) >= mips_regnum (gdbarch
)->fp0
698 && (regnum
% gdbarch_num_regs (gdbarch
))
699 < mips_regnum (gdbarch
)->fp0
+ 32)
701 /* The floating-point registers raw, or cooked, always match
702 mips_isa_regsize(), and also map 1:1, byte for byte. */
703 if (mips_isa_regsize (gdbarch
) == 4)
704 return builtin_type_ieee_single
;
706 return builtin_type_ieee_double
;
708 else if (regnum
< gdbarch_num_regs (gdbarch
))
710 /* The raw or ISA registers. These are all sized according to
712 if (mips_isa_regsize (gdbarch
) == 4)
713 return builtin_type_int32
;
715 return builtin_type_int64
;
719 /* The cooked or ABI registers. These are sized according to
720 the ABI (with a few complications). */
721 if (regnum
>= (gdbarch_num_regs (gdbarch
)
722 + mips_regnum (gdbarch
)->fp_control_status
)
723 && regnum
<= gdbarch_num_regs (gdbarch
) + MIPS_LAST_EMBED_REGNUM
)
724 /* The pseudo/cooked view of the embedded registers is always
725 32-bit. The raw view is handled below. */
726 return builtin_type_int32
;
727 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
728 /* The target, while possibly using a 64-bit register buffer,
729 is only transfering 32-bits of each integer register.
730 Reflect this in the cooked/pseudo (ABI) register value. */
731 return builtin_type_int32
;
732 else if (mips_abi_regsize (gdbarch
) == 4)
733 /* The ABI is restricted to 32-bit registers (the ISA could be
735 return builtin_type_int32
;
738 return builtin_type_int64
;
742 /* Return the GDB type for the pseudo register REGNUM, which is the
743 ABI-level view. This function is only called if there is a target
744 description which includes registers, so we know precisely the
745 types of hardware registers. */
748 mips_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
750 const int num_regs
= gdbarch_num_regs (gdbarch
);
751 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
752 int rawnum
= regnum
% num_regs
;
753 struct type
*rawtype
;
755 gdb_assert (regnum
>= num_regs
&& regnum
< 2 * num_regs
);
757 /* Absent registers are still absent. */
758 rawtype
= gdbarch_register_type (gdbarch
, rawnum
);
759 if (TYPE_LENGTH (rawtype
) == 0)
762 if (rawnum
>= MIPS_EMBED_FP0_REGNUM
&& rawnum
< MIPS_EMBED_FP0_REGNUM
+ 32)
763 /* Present the floating point registers however the hardware did;
764 do not try to convert between FPU layouts. */
767 if (rawnum
>= MIPS_EMBED_FP0_REGNUM
+ 32 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
769 /* The pseudo/cooked view of embedded registers is always
770 32-bit, even if the target transfers 64-bit values for them.
771 New targets relying on XML descriptions should only transfer
772 the necessary 32 bits, but older versions of GDB expected 64,
773 so allow the target to provide 64 bits without interfering
774 with the displayed type. */
775 return builtin_type_int32
;
778 /* Use pointer types for registers if we can. For n32 we can not,
779 since we do not have a 64-bit pointer type. */
780 if (mips_abi_regsize (gdbarch
) == TYPE_LENGTH (builtin_type_void_data_ptr
))
782 if (rawnum
== MIPS_SP_REGNUM
|| rawnum
== MIPS_EMBED_BADVADDR_REGNUM
)
783 return builtin_type_void_data_ptr
;
784 else if (rawnum
== MIPS_EMBED_PC_REGNUM
)
785 return builtin_type_void_func_ptr
;
788 if (mips_abi_regsize (gdbarch
) == 4 && TYPE_LENGTH (rawtype
) == 8
789 && rawnum
>= MIPS_ZERO_REGNUM
&& rawnum
<= MIPS_EMBED_PC_REGNUM
)
790 return builtin_type_int32
;
792 /* For all other registers, pass through the hardware type. */
796 /* Should the upper word of 64-bit addresses be zeroed? */
797 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
800 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
802 switch (mask_address_var
)
804 case AUTO_BOOLEAN_TRUE
:
806 case AUTO_BOOLEAN_FALSE
:
809 case AUTO_BOOLEAN_AUTO
:
810 return tdep
->default_mask_address_p
;
812 internal_error (__FILE__
, __LINE__
, _("mips_mask_address_p: bad switch"));
818 show_mask_address (struct ui_file
*file
, int from_tty
,
819 struct cmd_list_element
*c
, const char *value
)
821 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
823 deprecated_show_value_hack (file
, from_tty
, c
, value
);
824 switch (mask_address_var
)
826 case AUTO_BOOLEAN_TRUE
:
827 printf_filtered ("The 32 bit mips address mask is enabled\n");
829 case AUTO_BOOLEAN_FALSE
:
830 printf_filtered ("The 32 bit mips address mask is disabled\n");
832 case AUTO_BOOLEAN_AUTO
:
834 ("The 32 bit address mask is set automatically. Currently %s\n",
835 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
838 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
843 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
846 mips_pc_is_mips16 (CORE_ADDR memaddr
)
848 struct minimal_symbol
*sym
;
850 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
851 if (is_mips16_addr (memaddr
))
854 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
855 the high bit of the info field. Use this to decide if the function is
856 MIPS16 or normal MIPS. */
857 sym
= lookup_minimal_symbol_by_pc (memaddr
);
859 return msymbol_is_special (sym
);
864 /* MIPS believes that the PC has a sign extended value. Perhaps the
865 all registers should be sign extended for simplicity? */
868 mips_read_pc (struct regcache
*regcache
)
871 int regnum
= mips_regnum (get_regcache_arch (regcache
))->pc
;
872 regcache_cooked_read_signed (regcache
, regnum
, &pc
);
877 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
879 return frame_unwind_register_signed
880 (next_frame
, gdbarch_num_regs (gdbarch
) + mips_regnum (gdbarch
)->pc
);
884 mips_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
886 return frame_unwind_register_signed
887 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
);
890 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
891 dummy frame. The frame ID's base needs to match the TOS value
892 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
895 static struct frame_id
896 mips_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
898 return frame_id_build
899 (frame_unwind_register_signed (next_frame
,
900 gdbarch_num_regs (gdbarch
)
902 frame_pc_unwind (next_frame
));
906 mips_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
908 int regnum
= mips_regnum (get_regcache_arch (regcache
))->pc
;
909 regcache_cooked_write_unsigned (regcache
, regnum
, pc
);
912 /* Fetch and return instruction from the specified location. If the PC
913 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
916 mips_fetch_instruction (CORE_ADDR addr
)
918 gdb_byte buf
[MIPS_INSN32_SIZE
];
922 if (mips_pc_is_mips16 (addr
))
924 instlen
= MIPS_INSN16_SIZE
;
925 addr
= unmake_mips16_addr (addr
);
928 instlen
= MIPS_INSN32_SIZE
;
929 status
= read_memory_nobpt (addr
, buf
, instlen
);
931 memory_error (status
, addr
);
932 return extract_unsigned_integer (buf
, instlen
);
935 /* These the fields of 32 bit mips instructions */
936 #define mips32_op(x) (x >> 26)
937 #define itype_op(x) (x >> 26)
938 #define itype_rs(x) ((x >> 21) & 0x1f)
939 #define itype_rt(x) ((x >> 16) & 0x1f)
940 #define itype_immediate(x) (x & 0xffff)
942 #define jtype_op(x) (x >> 26)
943 #define jtype_target(x) (x & 0x03ffffff)
945 #define rtype_op(x) (x >> 26)
946 #define rtype_rs(x) ((x >> 21) & 0x1f)
947 #define rtype_rt(x) ((x >> 16) & 0x1f)
948 #define rtype_rd(x) ((x >> 11) & 0x1f)
949 #define rtype_shamt(x) ((x >> 6) & 0x1f)
950 #define rtype_funct(x) (x & 0x3f)
953 mips32_relative_offset (ULONGEST inst
)
955 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
958 /* Determine where to set a single step breakpoint while considering
959 branch prediction. */
961 mips32_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
965 inst
= mips_fetch_instruction (pc
);
966 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
968 if (itype_op (inst
) >> 2 == 5)
969 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
971 op
= (itype_op (inst
) & 0x03);
986 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
987 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
989 int tf
= itype_rt (inst
) & 0x01;
990 int cnum
= itype_rt (inst
) >> 2;
992 get_frame_register_signed (frame
,
993 mips_regnum (get_frame_arch (frame
))->
995 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
997 if (((cond
>> cnum
) & 0x01) == tf
)
998 pc
+= mips32_relative_offset (inst
) + 4;
1003 pc
+= 4; /* Not a branch, next instruction is easy */
1006 { /* This gets way messy */
1008 /* Further subdivide into SPECIAL, REGIMM and other */
1009 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
1011 case 0: /* SPECIAL */
1012 op
= rtype_funct (inst
);
1017 /* Set PC to that address */
1018 pc
= get_frame_register_signed (frame
, rtype_rs (inst
));
1024 break; /* end SPECIAL */
1025 case 1: /* REGIMM */
1027 op
= itype_rt (inst
); /* branch condition */
1032 case 16: /* BLTZAL */
1033 case 18: /* BLTZALL */
1035 if (get_frame_register_signed (frame
, itype_rs (inst
)) < 0)
1036 pc
+= mips32_relative_offset (inst
) + 4;
1038 pc
+= 8; /* after the delay slot */
1042 case 17: /* BGEZAL */
1043 case 19: /* BGEZALL */
1044 if (get_frame_register_signed (frame
, itype_rs (inst
)) >= 0)
1045 pc
+= mips32_relative_offset (inst
) + 4;
1047 pc
+= 8; /* after the delay slot */
1049 /* All of the other instructions in the REGIMM category */
1054 break; /* end REGIMM */
1059 reg
= jtype_target (inst
) << 2;
1060 /* Upper four bits get never changed... */
1061 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1064 /* FIXME case JALX : */
1067 reg
= jtype_target (inst
) << 2;
1068 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + 1; /* yes, +1 */
1069 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1071 break; /* The new PC will be alternate mode */
1072 case 4: /* BEQ, BEQL */
1074 if (get_frame_register_signed (frame
, itype_rs (inst
)) ==
1075 get_frame_register_signed (frame
, itype_rt (inst
)))
1076 pc
+= mips32_relative_offset (inst
) + 4;
1080 case 5: /* BNE, BNEL */
1082 if (get_frame_register_signed (frame
, itype_rs (inst
)) !=
1083 get_frame_register_signed (frame
, itype_rt (inst
)))
1084 pc
+= mips32_relative_offset (inst
) + 4;
1088 case 6: /* BLEZ, BLEZL */
1089 if (get_frame_register_signed (frame
, itype_rs (inst
)) <= 0)
1090 pc
+= mips32_relative_offset (inst
) + 4;
1096 greater_branch
: /* BGTZ, BGTZL */
1097 if (get_frame_register_signed (frame
, itype_rs (inst
)) > 0)
1098 pc
+= mips32_relative_offset (inst
) + 4;
1105 } /* mips32_next_pc */
1107 /* Decoding the next place to set a breakpoint is irregular for the
1108 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1109 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1110 We dont want to set a single step instruction on the extend instruction
1114 /* Lots of mips16 instruction formats */
1115 /* Predicting jumps requires itype,ritype,i8type
1116 and their extensions extItype,extritype,extI8type
1118 enum mips16_inst_fmts
1120 itype
, /* 0 immediate 5,10 */
1121 ritype
, /* 1 5,3,8 */
1122 rrtype
, /* 2 5,3,3,5 */
1123 rritype
, /* 3 5,3,3,5 */
1124 rrrtype
, /* 4 5,3,3,3,2 */
1125 rriatype
, /* 5 5,3,3,1,4 */
1126 shifttype
, /* 6 5,3,3,3,2 */
1127 i8type
, /* 7 5,3,8 */
1128 i8movtype
, /* 8 5,3,3,5 */
1129 i8mov32rtype
, /* 9 5,3,5,3 */
1130 i64type
, /* 10 5,3,8 */
1131 ri64type
, /* 11 5,3,3,5 */
1132 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1133 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1134 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1135 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1136 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1137 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1138 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1139 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1140 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1141 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1143 /* I am heaping all the fields of the formats into one structure and
1144 then, only the fields which are involved in instruction extension */
1148 unsigned int regx
; /* Function in i8 type */
1153 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1154 for the bits which make up the immediatate extension. */
1157 extended_offset (unsigned int extension
)
1160 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1162 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1164 value
|= extension
& 0x01f; /* extract 4:0 */
1168 /* Only call this function if you know that this is an extendable
1169 instruction. It won't malfunction, but why make excess remote memory
1170 references? If the immediate operands get sign extended or something,
1171 do it after the extension is performed. */
1172 /* FIXME: Every one of these cases needs to worry about sign extension
1173 when the offset is to be used in relative addressing. */
1176 fetch_mips_16 (CORE_ADDR pc
)
1179 pc
&= 0xfffffffe; /* clear the low order bit */
1180 target_read_memory (pc
, buf
, 2);
1181 return extract_unsigned_integer (buf
, 2);
1185 unpack_mips16 (CORE_ADDR pc
,
1186 unsigned int extension
,
1188 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1193 switch (insn_format
)
1200 value
= extended_offset (extension
);
1201 value
= value
<< 11; /* rom for the original value */
1202 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1206 value
= inst
& 0x7ff;
1207 /* FIXME : Consider sign extension */
1216 { /* A register identifier and an offset */
1217 /* Most of the fields are the same as I type but the
1218 immediate value is of a different length */
1222 value
= extended_offset (extension
);
1223 value
= value
<< 8; /* from the original instruction */
1224 value
|= inst
& 0xff; /* eleven bits from instruction */
1225 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1226 if (value
& 0x4000) /* test the sign bit , bit 26 */
1228 value
&= ~0x3fff; /* remove the sign bit */
1234 value
= inst
& 0xff; /* 8 bits */
1235 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1236 /* FIXME: Do sign extension , this format needs it */
1237 if (value
& 0x80) /* THIS CONFUSES ME */
1239 value
&= 0xef; /* remove the sign bit */
1249 unsigned long value
;
1250 unsigned int nexthalf
;
1251 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1252 value
= value
<< 16;
1253 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1261 internal_error (__FILE__
, __LINE__
, _("bad switch"));
1263 upk
->offset
= offset
;
1270 add_offset_16 (CORE_ADDR pc
, int offset
)
1272 return ((offset
<< 2) | ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)));
1276 extended_mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
,
1277 unsigned int extension
, unsigned int insn
)
1279 int op
= (insn
>> 11);
1282 case 2: /* Branch */
1285 struct upk_mips16 upk
;
1286 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1287 offset
= upk
.offset
;
1293 pc
+= (offset
<< 1) + 2;
1296 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1298 struct upk_mips16 upk
;
1299 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1300 pc
= add_offset_16 (pc
, upk
.offset
);
1301 if ((insn
>> 10) & 0x01) /* Exchange mode */
1302 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1309 struct upk_mips16 upk
;
1311 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1312 reg
= get_frame_register_signed (frame
, upk
.regx
);
1314 pc
+= (upk
.offset
<< 1) + 2;
1321 struct upk_mips16 upk
;
1323 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1324 reg
= get_frame_register_signed (frame
, upk
.regx
);
1326 pc
+= (upk
.offset
<< 1) + 2;
1331 case 12: /* I8 Formats btez btnez */
1333 struct upk_mips16 upk
;
1335 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1336 /* upk.regx contains the opcode */
1337 reg
= get_frame_register_signed (frame
, 24); /* Test register is 24 */
1338 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1339 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1340 /* pc = add_offset_16(pc,upk.offset) ; */
1341 pc
+= (upk
.offset
<< 1) + 2;
1346 case 29: /* RR Formats JR, JALR, JALR-RA */
1348 struct upk_mips16 upk
;
1349 /* upk.fmt = rrtype; */
1354 upk
.regx
= (insn
>> 8) & 0x07;
1355 upk
.regy
= (insn
>> 5) & 0x07;
1363 break; /* Function return instruction */
1369 break; /* BOGUS Guess */
1371 pc
= get_frame_register_signed (frame
, reg
);
1378 /* This is an instruction extension. Fetch the real instruction
1379 (which follows the extension) and decode things based on
1383 pc
= extended_mips16_next_pc (frame
, pc
, insn
, fetch_mips_16 (pc
));
1396 mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1398 unsigned int insn
= fetch_mips_16 (pc
);
1399 return extended_mips16_next_pc (frame
, pc
, 0, insn
);
1402 /* The mips_next_pc function supports single_step when the remote
1403 target monitor or stub is not developed enough to do a single_step.
1404 It works by decoding the current instruction and predicting where a
1405 branch will go. This isnt hard because all the data is available.
1406 The MIPS32 and MIPS16 variants are quite different. */
1408 mips_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1410 if (is_mips16_addr (pc
))
1411 return mips16_next_pc (frame
, pc
);
1413 return mips32_next_pc (frame
, pc
);
1416 struct mips_frame_cache
1419 struct trad_frame_saved_reg
*saved_regs
;
1422 /* Set a register's saved stack address in temp_saved_regs. If an
1423 address has already been set for this register, do nothing; this
1424 way we will only recognize the first save of a given register in a
1427 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
1428 [gdbarch_num_regs .. 2*gdbarch_num_regs).
1429 Strictly speaking, only the second range is used as it is only second
1430 range (the ABI instead of ISA registers) that comes into play when finding
1431 saved registers in a frame. */
1434 set_reg_offset (struct mips_frame_cache
*this_cache
, int regnum
,
1437 if (this_cache
!= NULL
1438 && this_cache
->saved_regs
[regnum
].addr
== -1)
1440 this_cache
->saved_regs
[regnum
1441 + 0 * gdbarch_num_regs (current_gdbarch
)].addr
1443 this_cache
->saved_regs
[regnum
1444 + 1 * gdbarch_num_regs (current_gdbarch
)].addr
1450 /* Fetch the immediate value from a MIPS16 instruction.
1451 If the previous instruction was an EXTEND, use it to extend
1452 the upper bits of the immediate value. This is a helper function
1453 for mips16_scan_prologue. */
1456 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1457 unsigned short inst
, /* current instruction */
1458 int nbits
, /* number of bits in imm field */
1459 int scale
, /* scale factor to be applied to imm */
1460 int is_signed
) /* is the imm field signed? */
1464 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1466 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1467 if (offset
& 0x8000) /* check for negative extend */
1468 offset
= 0 - (0x10000 - (offset
& 0xffff));
1469 return offset
| (inst
& 0x1f);
1473 int max_imm
= 1 << nbits
;
1474 int mask
= max_imm
- 1;
1475 int sign_bit
= max_imm
>> 1;
1477 offset
= inst
& mask
;
1478 if (is_signed
&& (offset
& sign_bit
))
1479 offset
= 0 - (max_imm
- offset
);
1480 return offset
* scale
;
1485 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1486 the associated FRAME_CACHE if not null.
1487 Return the address of the first instruction past the prologue. */
1490 mips16_scan_prologue (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1491 struct frame_info
*next_frame
,
1492 struct mips_frame_cache
*this_cache
)
1495 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1497 long frame_offset
= 0; /* Size of stack frame. */
1498 long frame_adjust
= 0; /* Offset of FP from SP. */
1499 int frame_reg
= MIPS_SP_REGNUM
;
1500 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1501 unsigned inst
= 0; /* current instruction */
1502 unsigned entry_inst
= 0; /* the entry instruction */
1505 int extend_bytes
= 0;
1506 int prev_extend_bytes
;
1507 CORE_ADDR end_prologue_addr
= 0;
1508 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
1510 /* Can be called when there's no process, and hence when there's no
1512 if (next_frame
!= NULL
)
1513 sp
= frame_unwind_register_signed (next_frame
,
1514 gdbarch_num_regs (gdbarch
)
1519 if (limit_pc
> start_pc
+ 200)
1520 limit_pc
= start_pc
+ 200;
1522 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
1524 /* Save the previous instruction. If it's an EXTEND, we'll extract
1525 the immediate offset extension from it in mips16_get_imm. */
1528 /* Fetch and decode the instruction. */
1529 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1531 /* Normally we ignore extend instructions. However, if it is
1532 not followed by a valid prologue instruction, then this
1533 instruction is not part of the prologue either. We must
1534 remember in this case to adjust the end_prologue_addr back
1536 if ((inst
& 0xf800) == 0xf000) /* extend */
1538 extend_bytes
= MIPS_INSN16_SIZE
;
1542 prev_extend_bytes
= extend_bytes
;
1545 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1546 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1548 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1549 if (offset
< 0) /* negative stack adjustment? */
1550 frame_offset
-= offset
;
1552 /* Exit loop if a positive stack adjustment is found, which
1553 usually means that the stack cleanup code in the function
1554 epilogue is reached. */
1557 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1559 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1560 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1561 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1563 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1565 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1566 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1567 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1569 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1571 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1572 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1574 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1576 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1577 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1579 else if (inst
== 0x673d) /* move $s1, $sp */
1584 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1586 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1587 frame_addr
= sp
+ offset
;
1589 frame_adjust
= offset
;
1591 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1593 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1594 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1595 set_reg_offset (this_cache
, reg
, frame_addr
+ offset
);
1597 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1599 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1600 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1601 set_reg_offset (this_cache
, reg
, frame_addr
+ offset
);
1603 else if ((inst
& 0xf81f) == 0xe809
1604 && (inst
& 0x700) != 0x700) /* entry */
1605 entry_inst
= inst
; /* save for later processing */
1606 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1607 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
1608 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
1610 /* This instruction is part of the prologue, but we don't
1611 need to do anything special to handle it. */
1615 /* This instruction is not an instruction typically found
1616 in a prologue, so we must have reached the end of the
1618 if (end_prologue_addr
== 0)
1619 end_prologue_addr
= cur_pc
- prev_extend_bytes
;
1623 /* The entry instruction is typically the first instruction in a function,
1624 and it stores registers at offsets relative to the value of the old SP
1625 (before the prologue). But the value of the sp parameter to this
1626 function is the new SP (after the prologue has been executed). So we
1627 can't calculate those offsets until we've seen the entire prologue,
1628 and can calculate what the old SP must have been. */
1629 if (entry_inst
!= 0)
1631 int areg_count
= (entry_inst
>> 8) & 7;
1632 int sreg_count
= (entry_inst
>> 6) & 3;
1634 /* The entry instruction always subtracts 32 from the SP. */
1637 /* Now we can calculate what the SP must have been at the
1638 start of the function prologue. */
1641 /* Check if a0-a3 were saved in the caller's argument save area. */
1642 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1644 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1645 offset
+= mips_abi_regsize (gdbarch
);
1648 /* Check if the ra register was pushed on the stack. */
1650 if (entry_inst
& 0x20)
1652 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1653 offset
-= mips_abi_regsize (gdbarch
);
1656 /* Check if the s0 and s1 registers were pushed on the stack. */
1657 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1659 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1660 offset
-= mips_abi_regsize (gdbarch
);
1664 if (this_cache
!= NULL
)
1667 (frame_unwind_register_signed (next_frame
,
1668 gdbarch_num_regs (gdbarch
) + frame_reg
)
1669 + frame_offset
- frame_adjust
);
1670 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
1671 be able to get rid of the assignment below, evetually. But it's
1672 still needed for now. */
1673 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
1674 + mips_regnum (gdbarch
)->pc
]
1675 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
1678 /* If we didn't reach the end of the prologue when scanning the function
1679 instructions, then set end_prologue_addr to the address of the
1680 instruction immediately after the last one we scanned. */
1681 if (end_prologue_addr
== 0)
1682 end_prologue_addr
= cur_pc
;
1684 return end_prologue_addr
;
1687 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
1688 Procedures that use the 32-bit instruction set are handled by the
1689 mips_insn32 unwinder. */
1691 static struct mips_frame_cache
*
1692 mips_insn16_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1694 struct mips_frame_cache
*cache
;
1696 if ((*this_cache
) != NULL
)
1697 return (*this_cache
);
1698 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1699 (*this_cache
) = cache
;
1700 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1702 /* Analyze the function prologue. */
1704 const CORE_ADDR pc
=
1705 frame_unwind_address_in_block (next_frame
, NORMAL_FRAME
);
1706 CORE_ADDR start_addr
;
1708 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
1709 if (start_addr
== 0)
1710 start_addr
= heuristic_proc_start (pc
);
1711 /* We can't analyze the prologue if we couldn't find the begining
1713 if (start_addr
== 0)
1716 mips16_scan_prologue (start_addr
, pc
, next_frame
, *this_cache
);
1719 /* gdbarch_sp_regnum contains the value and not the address. */
1720 trad_frame_set_value (cache
->saved_regs
,
1721 gdbarch_num_regs (get_frame_arch (next_frame
))
1725 return (*this_cache
);
1729 mips_insn16_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1730 struct frame_id
*this_id
)
1732 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1734 (*this_id
) = frame_id_build (info
->base
,
1735 frame_func_unwind (next_frame
, NORMAL_FRAME
));
1739 mips_insn16_frame_prev_register (struct frame_info
*next_frame
,
1741 int regnum
, int *optimizedp
,
1742 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1743 int *realnump
, gdb_byte
*valuep
)
1745 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1747 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
1748 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
1751 static const struct frame_unwind mips_insn16_frame_unwind
=
1754 mips_insn16_frame_this_id
,
1755 mips_insn16_frame_prev_register
1758 static const struct frame_unwind
*
1759 mips_insn16_frame_sniffer (struct frame_info
*next_frame
)
1761 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1762 if (mips_pc_is_mips16 (pc
))
1763 return &mips_insn16_frame_unwind
;
1768 mips_insn16_frame_base_address (struct frame_info
*next_frame
,
1771 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1776 static const struct frame_base mips_insn16_frame_base
=
1778 &mips_insn16_frame_unwind
,
1779 mips_insn16_frame_base_address
,
1780 mips_insn16_frame_base_address
,
1781 mips_insn16_frame_base_address
1784 static const struct frame_base
*
1785 mips_insn16_frame_base_sniffer (struct frame_info
*next_frame
)
1787 if (mips_insn16_frame_sniffer (next_frame
) != NULL
)
1788 return &mips_insn16_frame_base
;
1793 /* Mark all the registers as unset in the saved_regs array
1794 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
1797 reset_saved_regs (struct mips_frame_cache
*this_cache
)
1799 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
1803 const int num_regs
= gdbarch_num_regs (current_gdbarch
);
1806 for (i
= 0; i
< num_regs
; i
++)
1808 this_cache
->saved_regs
[i
].addr
= -1;
1813 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1814 the associated FRAME_CACHE if not null.
1815 Return the address of the first instruction past the prologue. */
1818 mips32_scan_prologue (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1819 struct frame_info
*next_frame
,
1820 struct mips_frame_cache
*this_cache
)
1823 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
1826 int frame_reg
= MIPS_SP_REGNUM
;
1828 CORE_ADDR end_prologue_addr
= 0;
1829 int seen_sp_adjust
= 0;
1830 int load_immediate_bytes
= 0;
1831 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
1833 /* Can be called when there's no process, and hence when there's no
1835 if (next_frame
!= NULL
)
1836 sp
= frame_unwind_register_signed (next_frame
,
1837 gdbarch_num_regs (gdbarch
)
1842 if (limit_pc
> start_pc
+ 200)
1843 limit_pc
= start_pc
+ 200;
1848 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
1850 unsigned long inst
, high_word
, low_word
;
1853 /* Fetch the instruction. */
1854 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
1856 /* Save some code by pre-extracting some useful fields. */
1857 high_word
= (inst
>> 16) & 0xffff;
1858 low_word
= inst
& 0xffff;
1859 reg
= high_word
& 0x1f;
1861 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
1862 || high_word
== 0x23bd /* addi $sp,$sp,-i */
1863 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
1865 if (low_word
& 0x8000) /* negative stack adjustment? */
1866 frame_offset
+= 0x10000 - low_word
;
1868 /* Exit loop if a positive stack adjustment is found, which
1869 usually means that the stack cleanup code in the function
1870 epilogue is reached. */
1874 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1876 set_reg_offset (this_cache
, reg
, sp
+ low_word
);
1878 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1880 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
1881 set_reg_offset (this_cache
, reg
, sp
+ low_word
);
1883 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
1885 /* Old gcc frame, r30 is virtual frame pointer. */
1886 if ((long) low_word
!= frame_offset
)
1887 frame_addr
= sp
+ low_word
;
1888 else if (next_frame
&& frame_reg
== MIPS_SP_REGNUM
)
1890 unsigned alloca_adjust
;
1893 frame_addr
= frame_unwind_register_signed
1894 (next_frame
, gdbarch_num_regs (gdbarch
) + 30);
1896 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
1897 if (alloca_adjust
> 0)
1899 /* FP > SP + frame_size. This may be because of
1900 an alloca or somethings similar. Fix sp to
1901 "pre-alloca" value, and try again. */
1902 sp
+= alloca_adjust
;
1903 /* Need to reset the status of all registers. Otherwise,
1904 we will hit a guard that prevents the new address
1905 for each register to be recomputed during the second
1907 reset_saved_regs (this_cache
);
1912 /* move $30,$sp. With different versions of gas this will be either
1913 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
1914 Accept any one of these. */
1915 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
1917 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
1918 if (next_frame
&& frame_reg
== MIPS_SP_REGNUM
)
1920 unsigned alloca_adjust
;
1923 frame_addr
= frame_unwind_register_signed
1924 (next_frame
, gdbarch_num_regs (gdbarch
) + 30);
1926 alloca_adjust
= (unsigned) (frame_addr
- sp
);
1927 if (alloca_adjust
> 0)
1929 /* FP > SP + frame_size. This may be because of
1930 an alloca or somethings similar. Fix sp to
1931 "pre-alloca" value, and try again. */
1933 /* Need to reset the status of all registers. Otherwise,
1934 we will hit a guard that prevents the new address
1935 for each register to be recomputed during the second
1937 reset_saved_regs (this_cache
);
1942 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
1944 set_reg_offset (this_cache
, reg
, frame_addr
+ low_word
);
1946 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
1947 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
1948 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
1949 || high_word
== 0x3c1c /* lui $gp,n */
1950 || high_word
== 0x279c /* addiu $gp,$gp,n */
1951 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
1952 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
1955 /* These instructions are part of the prologue, but we don't
1956 need to do anything special to handle them. */
1958 /* The instructions below load $at or $t0 with an immediate
1959 value in preparation for a stack adjustment via
1960 subu $sp,$sp,[$at,$t0]. These instructions could also
1961 initialize a local variable, so we accept them only before
1962 a stack adjustment instruction was seen. */
1963 else if (!seen_sp_adjust
1964 && (high_word
== 0x3c01 /* lui $at,n */
1965 || high_word
== 0x3c08 /* lui $t0,n */
1966 || high_word
== 0x3421 /* ori $at,$at,n */
1967 || high_word
== 0x3508 /* ori $t0,$t0,n */
1968 || high_word
== 0x3401 /* ori $at,$zero,n */
1969 || high_word
== 0x3408 /* ori $t0,$zero,n */
1972 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
1976 /* This instruction is not an instruction typically found
1977 in a prologue, so we must have reached the end of the
1979 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
1980 loop now? Why would we need to continue scanning the function
1982 if (end_prologue_addr
== 0)
1983 end_prologue_addr
= cur_pc
;
1987 if (this_cache
!= NULL
)
1990 (frame_unwind_register_signed (next_frame
,
1991 gdbarch_num_regs (gdbarch
) + frame_reg
)
1993 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
1994 this assignment below, eventually. But it's still needed
1996 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
1997 + mips_regnum (gdbarch
)->pc
]
1998 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2002 /* If we didn't reach the end of the prologue when scanning the function
2003 instructions, then set end_prologue_addr to the address of the
2004 instruction immediately after the last one we scanned. */
2005 /* brobecker/2004-10-10: I don't think this would ever happen, but
2006 we may as well be careful and do our best if we have a null
2007 end_prologue_addr. */
2008 if (end_prologue_addr
== 0)
2009 end_prologue_addr
= cur_pc
;
2011 /* In a frameless function, we might have incorrectly
2012 skipped some load immediate instructions. Undo the skipping
2013 if the load immediate was not followed by a stack adjustment. */
2014 if (load_immediate_bytes
&& !seen_sp_adjust
)
2015 end_prologue_addr
-= load_immediate_bytes
;
2017 return end_prologue_addr
;
2020 /* Heuristic unwinder for procedures using 32-bit instructions (covers
2021 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
2022 instructions (a.k.a. MIPS16) are handled by the mips_insn16
2025 static struct mips_frame_cache
*
2026 mips_insn32_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
2028 struct mips_frame_cache
*cache
;
2030 if ((*this_cache
) != NULL
)
2031 return (*this_cache
);
2033 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2034 (*this_cache
) = cache
;
2035 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
2037 /* Analyze the function prologue. */
2039 const CORE_ADDR pc
=
2040 frame_unwind_address_in_block (next_frame
, NORMAL_FRAME
);
2041 CORE_ADDR start_addr
;
2043 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2044 if (start_addr
== 0)
2045 start_addr
= heuristic_proc_start (pc
);
2046 /* We can't analyze the prologue if we couldn't find the begining
2048 if (start_addr
== 0)
2051 mips32_scan_prologue (start_addr
, pc
, next_frame
, *this_cache
);
2054 /* gdbarch_sp_regnum contains the value and not the address. */
2055 trad_frame_set_value (cache
->saved_regs
,
2056 gdbarch_num_regs (get_frame_arch (next_frame
))
2060 return (*this_cache
);
2064 mips_insn32_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2065 struct frame_id
*this_id
)
2067 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2069 (*this_id
) = frame_id_build (info
->base
,
2070 frame_func_unwind (next_frame
, NORMAL_FRAME
));
2074 mips_insn32_frame_prev_register (struct frame_info
*next_frame
,
2076 int regnum
, int *optimizedp
,
2077 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2078 int *realnump
, gdb_byte
*valuep
)
2080 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2082 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
2083 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
2086 static const struct frame_unwind mips_insn32_frame_unwind
=
2089 mips_insn32_frame_this_id
,
2090 mips_insn32_frame_prev_register
2093 static const struct frame_unwind
*
2094 mips_insn32_frame_sniffer (struct frame_info
*next_frame
)
2096 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2097 if (! mips_pc_is_mips16 (pc
))
2098 return &mips_insn32_frame_unwind
;
2103 mips_insn32_frame_base_address (struct frame_info
*next_frame
,
2106 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2111 static const struct frame_base mips_insn32_frame_base
=
2113 &mips_insn32_frame_unwind
,
2114 mips_insn32_frame_base_address
,
2115 mips_insn32_frame_base_address
,
2116 mips_insn32_frame_base_address
2119 static const struct frame_base
*
2120 mips_insn32_frame_base_sniffer (struct frame_info
*next_frame
)
2122 if (mips_insn32_frame_sniffer (next_frame
) != NULL
)
2123 return &mips_insn32_frame_base
;
2128 static struct trad_frame_cache
*
2129 mips_stub_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
2132 CORE_ADDR start_addr
;
2133 CORE_ADDR stack_addr
;
2134 struct trad_frame_cache
*this_trad_cache
;
2135 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
2137 if ((*this_cache
) != NULL
)
2138 return (*this_cache
);
2139 this_trad_cache
= trad_frame_cache_zalloc (next_frame
);
2140 (*this_cache
) = this_trad_cache
;
2142 /* The return address is in the link register. */
2143 trad_frame_set_reg_realreg (this_trad_cache
,
2144 gdbarch_pc_regnum (gdbarch
),
2145 (gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
));
2147 /* Frame ID, since it's a frameless / stackless function, no stack
2148 space is allocated and SP on entry is the current SP. */
2149 pc
= frame_pc_unwind (next_frame
);
2150 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2151 stack_addr
= frame_unwind_register_signed (next_frame
, MIPS_SP_REGNUM
);
2152 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
2154 /* Assume that the frame's base is the same as the
2156 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
2158 return this_trad_cache
;
2162 mips_stub_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2163 struct frame_id
*this_id
)
2165 struct trad_frame_cache
*this_trad_cache
2166 = mips_stub_frame_cache (next_frame
, this_cache
);
2167 trad_frame_get_id (this_trad_cache
, this_id
);
2171 mips_stub_frame_prev_register (struct frame_info
*next_frame
,
2173 int regnum
, int *optimizedp
,
2174 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2175 int *realnump
, gdb_byte
*valuep
)
2177 struct trad_frame_cache
*this_trad_cache
2178 = mips_stub_frame_cache (next_frame
, this_cache
);
2179 trad_frame_get_register (this_trad_cache
, next_frame
, regnum
, optimizedp
,
2180 lvalp
, addrp
, realnump
, valuep
);
2183 static const struct frame_unwind mips_stub_frame_unwind
=
2186 mips_stub_frame_this_id
,
2187 mips_stub_frame_prev_register
2190 static const struct frame_unwind
*
2191 mips_stub_frame_sniffer (struct frame_info
*next_frame
)
2194 struct obj_section
*s
;
2195 CORE_ADDR pc
= frame_unwind_address_in_block (next_frame
, NORMAL_FRAME
);
2197 /* Use the stub unwinder for unreadable code. */
2198 if (target_read_memory (frame_pc_unwind (next_frame
), dummy
, 4) != 0)
2199 return &mips_stub_frame_unwind
;
2201 if (in_plt_section (pc
, NULL
))
2202 return &mips_stub_frame_unwind
;
2204 /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */
2205 s
= find_pc_section (pc
);
2208 && strcmp (bfd_get_section_name (s
->objfile
->obfd
, s
->the_bfd_section
),
2209 ".MIPS.stubs") == 0)
2210 return &mips_stub_frame_unwind
;
2216 mips_stub_frame_base_address (struct frame_info
*next_frame
,
2219 struct trad_frame_cache
*this_trad_cache
2220 = mips_stub_frame_cache (next_frame
, this_cache
);
2221 return trad_frame_get_this_base (this_trad_cache
);
2224 static const struct frame_base mips_stub_frame_base
=
2226 &mips_stub_frame_unwind
,
2227 mips_stub_frame_base_address
,
2228 mips_stub_frame_base_address
,
2229 mips_stub_frame_base_address
2232 static const struct frame_base
*
2233 mips_stub_frame_base_sniffer (struct frame_info
*next_frame
)
2235 if (mips_stub_frame_sniffer (next_frame
) != NULL
)
2236 return &mips_stub_frame_base
;
2241 /* mips_addr_bits_remove - remove useless address bits */
2244 mips_addr_bits_remove (CORE_ADDR addr
)
2246 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2247 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
2248 /* This hack is a work-around for existing boards using PMON, the
2249 simulator, and any other 64-bit targets that doesn't have true
2250 64-bit addressing. On these targets, the upper 32 bits of
2251 addresses are ignored by the hardware. Thus, the PC or SP are
2252 likely to have been sign extended to all 1s by instruction
2253 sequences that load 32-bit addresses. For example, a typical
2254 piece of code that loads an address is this:
2256 lui $r2, <upper 16 bits>
2257 ori $r2, <lower 16 bits>
2259 But the lui sign-extends the value such that the upper 32 bits
2260 may be all 1s. The workaround is simply to mask off these
2261 bits. In the future, gcc may be changed to support true 64-bit
2262 addressing, and this masking will have to be disabled. */
2263 return addr
&= 0xffffffffUL
;
2268 /* Instructions used during single-stepping of atomic sequences. */
2269 #define LL_OPCODE 0x30
2270 #define LLD_OPCODE 0x34
2271 #define SC_OPCODE 0x38
2272 #define SCD_OPCODE 0x3c
2274 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
2275 instruction and ending with a SC/SCD instruction. If such a sequence
2276 is found, attempt to step through it. A breakpoint is placed at the end of
2280 deal_with_atomic_sequence (CORE_ADDR pc
)
2282 CORE_ADDR breaks
[2] = {-1, -1};
2284 CORE_ADDR branch_bp
; /* Breakpoint at branch instruction's destination. */
2288 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
2289 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
2294 insn
= mips_fetch_instruction (loc
);
2295 /* Assume all atomic sequences start with a ll/lld instruction. */
2296 if (itype_op (insn
) != LL_OPCODE
&& itype_op (insn
) != LLD_OPCODE
)
2299 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
2301 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
2304 loc
+= MIPS_INSN32_SIZE
;
2305 insn
= mips_fetch_instruction (loc
);
2307 /* Assume that there is at most one branch in the atomic
2308 sequence. If a branch is found, put a breakpoint in its
2309 destination address. */
2310 switch (itype_op (insn
))
2312 case 0: /* SPECIAL */
2313 if (rtype_funct (insn
) >> 1 == 4) /* JR, JALR */
2314 return 0; /* fallback to the standard single-step code. */
2316 case 1: /* REGIMM */
2317 is_branch
= ((itype_rt (insn
) & 0xc0) == 0); /* B{LT,GE}Z* */
2321 return 0; /* fallback to the standard single-step code. */
2328 case 22: /* BLEZL */
2329 case 23: /* BGTTL */
2335 is_branch
= (itype_rs (insn
) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
2340 branch_bp
= loc
+ mips32_relative_offset (insn
) + 4;
2341 if (last_breakpoint
>= 1)
2342 return 0; /* More than one branch found, fallback to the
2343 standard single-step code. */
2344 breaks
[1] = branch_bp
;
2348 if (itype_op (insn
) == SC_OPCODE
|| itype_op (insn
) == SCD_OPCODE
)
2352 /* Assume that the atomic sequence ends with a sc/scd instruction. */
2353 if (itype_op (insn
) != SC_OPCODE
&& itype_op (insn
) != SCD_OPCODE
)
2356 loc
+= MIPS_INSN32_SIZE
;
2358 /* Insert a breakpoint right after the end of the atomic sequence. */
2361 /* Check for duplicated breakpoints. Check also for a breakpoint
2362 placed (branch instruction's destination) in the atomic sequence */
2363 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
2364 last_breakpoint
= 0;
2366 /* Effectively inserts the breakpoints. */
2367 for (index
= 0; index
<= last_breakpoint
; index
++)
2368 insert_single_step_breakpoint (breaks
[index
]);
2373 /* mips_software_single_step() is called just before we want to resume
2374 the inferior, if we want to single-step it but there is no hardware
2375 or kernel single-step support (MIPS on GNU/Linux for example). We find
2376 the target of the coming instruction and breakpoint it. */
2379 mips_software_single_step (struct frame_info
*frame
)
2381 CORE_ADDR pc
, next_pc
;
2383 pc
= get_frame_pc (frame
);
2384 if (deal_with_atomic_sequence (pc
))
2387 next_pc
= mips_next_pc (frame
, pc
);
2389 insert_single_step_breakpoint (next_pc
);
2393 /* Test whether the PC points to the return instruction at the
2394 end of a function. */
2397 mips_about_to_return (CORE_ADDR pc
)
2399 if (mips_pc_is_mips16 (pc
))
2400 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2401 generates a "jr $ra"; other times it generates code to load
2402 the return address from the stack to an accessible register (such
2403 as $a3), then a "jr" using that register. This second case
2404 is almost impossible to distinguish from an indirect jump
2405 used for switch statements, so we don't even try. */
2406 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
2408 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
2412 /* This fencepost looks highly suspicious to me. Removing it also
2413 seems suspicious as it could affect remote debugging across serial
2417 heuristic_proc_start (CORE_ADDR pc
)
2424 pc
= gdbarch_addr_bits_remove (current_gdbarch
, pc
);
2426 fence
= start_pc
- heuristic_fence_post
;
2430 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
2431 fence
= VM_MIN_ADDRESS
;
2433 instlen
= mips_pc_is_mips16 (pc
) ? MIPS_INSN16_SIZE
: MIPS_INSN32_SIZE
;
2435 /* search back for previous return */
2436 for (start_pc
-= instlen
;; start_pc
-= instlen
)
2437 if (start_pc
< fence
)
2439 /* It's not clear to me why we reach this point when
2440 stop_soon, but with this test, at least we
2441 don't print out warnings for every child forked (eg, on
2442 decstation). 22apr93 rich@cygnus.com. */
2443 if (stop_soon
== NO_STOP_QUIETLY
)
2445 static int blurb_printed
= 0;
2447 warning (_("GDB can't find the start of the function at 0x%s."),
2452 /* This actually happens frequently in embedded
2453 development, when you first connect to a board
2454 and your stack pointer and pc are nowhere in
2455 particular. This message needs to give people
2456 in that situation enough information to
2457 determine that it's no big deal. */
2458 printf_filtered ("\n\
2459 GDB is unable to find the start of the function at 0x%s\n\
2460 and thus can't determine the size of that function's stack frame.\n\
2461 This means that GDB may be unable to access that stack frame, or\n\
2462 the frames below it.\n\
2463 This problem is most likely caused by an invalid program counter or\n\
2465 However, if you think GDB should simply search farther back\n\
2466 from 0x%s for code which looks like the beginning of a\n\
2467 function, you can increase the range of the search using the `set\n\
2468 heuristic-fence-post' command.\n", paddr_nz (pc
), paddr_nz (pc
));
2475 else if (mips_pc_is_mips16 (start_pc
))
2477 unsigned short inst
;
2479 /* On MIPS16, any one of the following is likely to be the
2480 start of a function:
2486 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
2487 inst
= mips_fetch_instruction (start_pc
);
2488 if ((inst
& 0xff80) == 0x6480) /* save */
2490 if (start_pc
- instlen
>= fence
)
2492 inst
= mips_fetch_instruction (start_pc
- instlen
);
2493 if ((inst
& 0xf800) == 0xf000) /* extend */
2494 start_pc
-= instlen
;
2498 else if (((inst
& 0xf81f) == 0xe809
2499 && (inst
& 0x700) != 0x700) /* entry */
2500 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
2501 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
2502 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
2504 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2505 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2510 else if (mips_about_to_return (start_pc
))
2512 /* Skip return and its delay slot. */
2513 start_pc
+= 2 * MIPS_INSN32_SIZE
;
2520 struct mips_objfile_private
2526 /* According to the current ABI, should the type be passed in a
2527 floating-point register (assuming that there is space)? When there
2528 is no FPU, FP are not even considered as possible candidates for
2529 FP registers and, consequently this returns false - forces FP
2530 arguments into integer registers. */
2533 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
2535 return ((typecode
== TYPE_CODE_FLT
2537 && (typecode
== TYPE_CODE_STRUCT
2538 || typecode
== TYPE_CODE_UNION
)
2539 && TYPE_NFIELDS (arg_type
) == 1
2540 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type
, 0)))
2542 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
2545 /* On o32, argument passing in GPRs depends on the alignment of the type being
2546 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2549 mips_type_needs_double_align (struct type
*type
)
2551 enum type_code typecode
= TYPE_CODE (type
);
2553 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2555 else if (typecode
== TYPE_CODE_STRUCT
)
2557 if (TYPE_NFIELDS (type
) < 1)
2559 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2561 else if (typecode
== TYPE_CODE_UNION
)
2565 n
= TYPE_NFIELDS (type
);
2566 for (i
= 0; i
< n
; i
++)
2567 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2574 /* Adjust the address downward (direction of stack growth) so that it
2575 is correctly aligned for a new stack frame. */
2577 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2579 return align_down (addr
, 16);
2583 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2584 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2585 int nargs
, struct value
**args
, CORE_ADDR sp
,
2586 int struct_return
, CORE_ADDR struct_addr
)
2592 int stack_offset
= 0;
2593 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2594 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
2595 int regsize
= mips_abi_regsize (gdbarch
);
2597 /* For shared libraries, "t9" needs to point at the function
2599 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
2601 /* Set the return address register to point to the entry point of
2602 the program, where a breakpoint lies in wait. */
2603 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
2605 /* First ensure that the stack and structure return address (if any)
2606 are properly aligned. The stack has to be at least 64-bit
2607 aligned even on 32-bit machines, because doubles must be 64-bit
2608 aligned. For n32 and n64, stack frames need to be 128-bit
2609 aligned, so we round to this widest known alignment. */
2611 sp
= align_down (sp
, 16);
2612 struct_addr
= align_down (struct_addr
, 16);
2614 /* Now make space on the stack for the args. We allocate more
2615 than necessary for EABI, because the first few arguments are
2616 passed in registers, but that's OK. */
2617 for (argnum
= 0; argnum
< nargs
; argnum
++)
2618 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), regsize
);
2619 sp
-= align_up (len
, 16);
2622 fprintf_unfiltered (gdb_stdlog
,
2623 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
2624 paddr_nz (sp
), (long) align_up (len
, 16));
2626 /* Initialize the integer and float register pointers. */
2627 argreg
= MIPS_A0_REGNUM
;
2628 float_argreg
= mips_fpa0_regnum (gdbarch
);
2630 /* The struct_return pointer occupies the first parameter-passing reg. */
2634 fprintf_unfiltered (gdb_stdlog
,
2635 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
2636 argreg
, paddr_nz (struct_addr
));
2637 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
2640 /* Now load as many as possible of the first arguments into
2641 registers, and push the rest onto the stack. Loop thru args
2642 from first to last. */
2643 for (argnum
= 0; argnum
< nargs
; argnum
++)
2645 const gdb_byte
*val
;
2646 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
2647 struct value
*arg
= args
[argnum
];
2648 struct type
*arg_type
= check_typedef (value_type (arg
));
2649 int len
= TYPE_LENGTH (arg_type
);
2650 enum type_code typecode
= TYPE_CODE (arg_type
);
2653 fprintf_unfiltered (gdb_stdlog
,
2654 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2655 argnum
+ 1, len
, (int) typecode
);
2657 /* The EABI passes structures that do not fit in a register by
2660 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2662 store_unsigned_integer (valbuf
, regsize
, VALUE_ADDRESS (arg
));
2663 typecode
= TYPE_CODE_PTR
;
2667 fprintf_unfiltered (gdb_stdlog
, " push");
2670 val
= value_contents (arg
);
2672 /* 32-bit ABIs always start floating point arguments in an
2673 even-numbered floating point register. Round the FP register
2674 up before the check to see if there are any FP registers
2675 left. Non MIPS_EABI targets also pass the FP in the integer
2676 registers so also round up normal registers. */
2677 if (regsize
< 8 && fp_register_arg_p (typecode
, arg_type
))
2679 if ((float_argreg
& 1))
2683 /* Floating point arguments passed in registers have to be
2684 treated specially. On 32-bit architectures, doubles
2685 are passed in register pairs; the even register gets
2686 the low word, and the odd register gets the high word.
2687 On non-EABI processors, the first two floating point arguments are
2688 also copied to general registers, because MIPS16 functions
2689 don't use float registers for arguments. This duplication of
2690 arguments in general registers can't hurt non-MIPS16 functions
2691 because those registers are normally skipped. */
2692 /* MIPS_EABI squeezes a struct that contains a single floating
2693 point value into an FP register instead of pushing it onto the
2695 if (fp_register_arg_p (typecode
, arg_type
)
2696 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2698 /* EABI32 will pass doubles in consecutive registers, even on
2699 64-bit cores. At one time, we used to check the size of
2700 `float_argreg' to determine whether or not to pass doubles
2701 in consecutive registers, but this is not sufficient for
2702 making the ABI determination. */
2703 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
2705 int low_offset
= gdbarch_byte_order (gdbarch
)
2706 == BFD_ENDIAN_BIG
? 4 : 0;
2707 unsigned long regval
;
2709 /* Write the low word of the double to the even register(s). */
2710 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2712 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2713 float_argreg
, phex (regval
, 4));
2714 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
2716 /* Write the high word of the double to the odd register(s). */
2717 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2719 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2720 float_argreg
, phex (regval
, 4));
2721 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
2725 /* This is a floating point value that fits entirely
2726 in a single register. */
2727 /* On 32 bit ABI's the float_argreg is further adjusted
2728 above to ensure that it is even register aligned. */
2729 LONGEST regval
= extract_unsigned_integer (val
, len
);
2731 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2732 float_argreg
, phex (regval
, len
));
2733 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
2738 /* Copy the argument to general registers or the stack in
2739 register-sized pieces. Large arguments are split between
2740 registers and stack. */
2741 /* Note: structs whose size is not a multiple of regsize
2742 are treated specially: Irix cc passes
2743 them in registers where gcc sometimes puts them on the
2744 stack. For maximum compatibility, we will put them in
2746 int odd_sized_struct
= (len
> regsize
&& len
% regsize
!= 0);
2748 /* Note: Floating-point values that didn't fit into an FP
2749 register are only written to memory. */
2752 /* Remember if the argument was written to the stack. */
2753 int stack_used_p
= 0;
2754 int partial_len
= (len
< regsize
? len
: regsize
);
2757 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2760 /* Write this portion of the argument to the stack. */
2761 if (argreg
> MIPS_LAST_ARG_REGNUM
2763 || fp_register_arg_p (typecode
, arg_type
))
2765 /* Should shorter than int integer values be
2766 promoted to int before being stored? */
2767 int longword_offset
= 0;
2770 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2773 && (typecode
== TYPE_CODE_INT
2774 || typecode
== TYPE_CODE_PTR
2775 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
2776 longword_offset
= regsize
- len
;
2777 else if ((typecode
== TYPE_CODE_STRUCT
2778 || typecode
== TYPE_CODE_UNION
)
2779 && TYPE_LENGTH (arg_type
) < regsize
)
2780 longword_offset
= regsize
- len
;
2785 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
2786 paddr_nz (stack_offset
));
2787 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
2788 paddr_nz (longword_offset
));
2791 addr
= sp
+ stack_offset
+ longword_offset
;
2796 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
2798 for (i
= 0; i
< partial_len
; i
++)
2800 fprintf_unfiltered (gdb_stdlog
, "%02x",
2804 write_memory (addr
, val
, partial_len
);
2807 /* Note!!! This is NOT an else clause. Odd sized
2808 structs may go thru BOTH paths. Floating point
2809 arguments will not. */
2810 /* Write this portion of the argument to a general
2811 purpose register. */
2812 if (argreg
<= MIPS_LAST_ARG_REGNUM
2813 && !fp_register_arg_p (typecode
, arg_type
))
2816 extract_unsigned_integer (val
, partial_len
);
2819 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2821 phex (regval
, regsize
));
2822 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
2829 /* Compute the the offset into the stack at which we
2830 will copy the next parameter.
2832 In the new EABI (and the NABI32), the stack_offset
2833 only needs to be adjusted when it has been used. */
2836 stack_offset
+= align_up (partial_len
, regsize
);
2840 fprintf_unfiltered (gdb_stdlog
, "\n");
2843 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
2845 /* Return adjusted stack pointer. */
2849 /* Determine the return value convention being used. */
2851 static enum return_value_convention
2852 mips_eabi_return_value (struct gdbarch
*gdbarch
,
2853 struct type
*type
, struct regcache
*regcache
,
2854 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2856 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
2857 return RETURN_VALUE_STRUCT_CONVENTION
;
2859 memset (readbuf
, 0, TYPE_LENGTH (type
));
2860 return RETURN_VALUE_REGISTER_CONVENTION
;
2864 /* N32/N64 ABI stuff. */
2866 /* Search for a naturally aligned double at OFFSET inside a struct
2867 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
2871 mips_n32n64_fp_arg_chunk_p (struct type
*arg_type
, int offset
)
2875 if (TYPE_CODE (arg_type
) != TYPE_CODE_STRUCT
)
2878 if (MIPS_FPU_TYPE
!= MIPS_FPU_DOUBLE
)
2881 if (TYPE_LENGTH (arg_type
) < offset
+ MIPS64_REGSIZE
)
2884 for (i
= 0; i
< TYPE_NFIELDS (arg_type
); i
++)
2887 struct type
*field_type
;
2889 /* We're only looking at normal fields. */
2890 if (TYPE_FIELD_STATIC (arg_type
, i
)
2891 || (TYPE_FIELD_BITPOS (arg_type
, i
) % 8) != 0)
2894 /* If we have gone past the offset, there is no double to pass. */
2895 pos
= TYPE_FIELD_BITPOS (arg_type
, i
) / 8;
2899 field_type
= check_typedef (TYPE_FIELD_TYPE (arg_type
, i
));
2901 /* If this field is entirely before the requested offset, go
2902 on to the next one. */
2903 if (pos
+ TYPE_LENGTH (field_type
) <= offset
)
2906 /* If this is our special aligned double, we can stop. */
2907 if (TYPE_CODE (field_type
) == TYPE_CODE_FLT
2908 && TYPE_LENGTH (field_type
) == MIPS64_REGSIZE
)
2911 /* This field starts at or before the requested offset, and
2912 overlaps it. If it is a structure, recurse inwards. */
2913 return mips_n32n64_fp_arg_chunk_p (field_type
, offset
- pos
);
2920 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2921 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2922 int nargs
, struct value
**args
, CORE_ADDR sp
,
2923 int struct_return
, CORE_ADDR struct_addr
)
2929 int stack_offset
= 0;
2930 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2931 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
2933 /* For shared libraries, "t9" needs to point at the function
2935 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
2937 /* Set the return address register to point to the entry point of
2938 the program, where a breakpoint lies in wait. */
2939 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
2941 /* First ensure that the stack and structure return address (if any)
2942 are properly aligned. The stack has to be at least 64-bit
2943 aligned even on 32-bit machines, because doubles must be 64-bit
2944 aligned. For n32 and n64, stack frames need to be 128-bit
2945 aligned, so we round to this widest known alignment. */
2947 sp
= align_down (sp
, 16);
2948 struct_addr
= align_down (struct_addr
, 16);
2950 /* Now make space on the stack for the args. */
2951 for (argnum
= 0; argnum
< nargs
; argnum
++)
2952 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), MIPS64_REGSIZE
);
2953 sp
-= align_up (len
, 16);
2956 fprintf_unfiltered (gdb_stdlog
,
2957 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
2958 paddr_nz (sp
), (long) align_up (len
, 16));
2960 /* Initialize the integer and float register pointers. */
2961 argreg
= MIPS_A0_REGNUM
;
2962 float_argreg
= mips_fpa0_regnum (gdbarch
);
2964 /* The struct_return pointer occupies the first parameter-passing reg. */
2968 fprintf_unfiltered (gdb_stdlog
,
2969 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
2970 argreg
, paddr_nz (struct_addr
));
2971 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
2974 /* Now load as many as possible of the first arguments into
2975 registers, and push the rest onto the stack. Loop thru args
2976 from first to last. */
2977 for (argnum
= 0; argnum
< nargs
; argnum
++)
2979 const gdb_byte
*val
;
2980 struct value
*arg
= args
[argnum
];
2981 struct type
*arg_type
= check_typedef (value_type (arg
));
2982 int len
= TYPE_LENGTH (arg_type
);
2983 enum type_code typecode
= TYPE_CODE (arg_type
);
2986 fprintf_unfiltered (gdb_stdlog
,
2987 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
2988 argnum
+ 1, len
, (int) typecode
);
2990 val
= value_contents (arg
);
2992 if (fp_register_arg_p (typecode
, arg_type
)
2993 && argreg
<= MIPS_LAST_ARG_REGNUM
)
2995 /* This is a floating point value that fits entirely
2996 in a single register. */
2997 LONGEST regval
= extract_unsigned_integer (val
, len
);
2999 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3000 float_argreg
, phex (regval
, len
));
3001 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
3004 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3005 argreg
, phex (regval
, len
));
3006 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3012 /* Copy the argument to general registers or the stack in
3013 register-sized pieces. Large arguments are split between
3014 registers and stack. */
3015 /* For N32/N64, structs, unions, or other composite types are
3016 treated as a sequence of doublewords, and are passed in integer
3017 or floating point registers as though they were simple scalar
3018 parameters to the extent that they fit, with any excess on the
3019 stack packed according to the normal memory layout of the
3021 The caller does not reserve space for the register arguments;
3022 the callee is responsible for reserving it if required. */
3023 /* Note: Floating-point values that didn't fit into an FP
3024 register are only written to memory. */
3027 /* Remember if the argument was written to the stack. */
3028 int stack_used_p
= 0;
3029 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
3032 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3035 if (fp_register_arg_p (typecode
, arg_type
))
3036 gdb_assert (argreg
> MIPS_LAST_ARG_REGNUM
);
3038 /* Write this portion of the argument to the stack. */
3039 if (argreg
> MIPS_LAST_ARG_REGNUM
)
3041 /* Should shorter than int integer values be
3042 promoted to int before being stored? */
3043 int longword_offset
= 0;
3046 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
3048 if ((typecode
== TYPE_CODE_INT
3049 || typecode
== TYPE_CODE_PTR
3050 || typecode
== TYPE_CODE_FLT
)
3052 longword_offset
= MIPS64_REGSIZE
- len
;
3057 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3058 paddr_nz (stack_offset
));
3059 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3060 paddr_nz (longword_offset
));
3063 addr
= sp
+ stack_offset
+ longword_offset
;
3068 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3070 for (i
= 0; i
< partial_len
; i
++)
3072 fprintf_unfiltered (gdb_stdlog
, "%02x",
3076 write_memory (addr
, val
, partial_len
);
3079 /* Note!!! This is NOT an else clause. Odd sized
3080 structs may go thru BOTH paths. */
3081 /* Write this portion of the argument to a general
3082 purpose register. */
3083 if (argreg
<= MIPS_LAST_ARG_REGNUM
)
3086 extract_unsigned_integer (val
, partial_len
);
3088 /* A non-floating-point argument being passed in a
3089 general register. If a struct or union, and if
3090 the remaining length is smaller than the register
3091 size, we have to adjust the register value on
3094 It does not seem to be necessary to do the
3095 same for integral types. */
3097 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
3098 && partial_len
< MIPS64_REGSIZE
3099 && (typecode
== TYPE_CODE_STRUCT
3100 || typecode
== TYPE_CODE_UNION
))
3101 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
3105 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3107 phex (regval
, MIPS64_REGSIZE
));
3108 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3110 if (mips_n32n64_fp_arg_chunk_p (arg_type
,
3111 TYPE_LENGTH (arg_type
) - len
))
3114 fprintf_filtered (gdb_stdlog
, " - fpreg=%d val=%s",
3116 phex (regval
, MIPS64_REGSIZE
));
3117 regcache_cooked_write_unsigned (regcache
, float_argreg
,
3128 /* Compute the the offset into the stack at which we
3129 will copy the next parameter.
3131 In N32 (N64?), the stack_offset only needs to be
3132 adjusted when it has been used. */
3135 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
3139 fprintf_unfiltered (gdb_stdlog
, "\n");
3142 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3144 /* Return adjusted stack pointer. */
3148 static enum return_value_convention
3149 mips_n32n64_return_value (struct gdbarch
*gdbarch
,
3150 struct type
*type
, struct regcache
*regcache
,
3151 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3153 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3155 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
3157 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
3158 if needed), as appropriate for the type. Composite results (struct,
3159 union, or array) are returned in $2/$f0 and $3/$f2 according to the
3162 * A struct with only one or two floating point fields is returned in $f0
3163 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
3166 * Any other struct or union results of at most 128 bits are returned in
3167 $2 (first 64 bits) and $3 (remainder, if necessary).
3169 * Larger composite results are handled by converting the function to a
3170 procedure with an implicit first parameter, which is a pointer to an area
3171 reserved by the caller to receive the result. [The o32-bit ABI requires
3172 that all composite results be handled by conversion to implicit first
3173 parameters. The MIPS/SGI Fortran implementation has always made a
3174 specific exception to return COMPLEX results in the floating point
3177 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
3178 || TYPE_LENGTH (type
) > 2 * MIPS64_REGSIZE
)
3179 return RETURN_VALUE_STRUCT_CONVENTION
;
3180 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3181 && TYPE_LENGTH (type
) == 16
3182 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3184 /* A 128-bit floating-point value fills both $f0 and $f2. The
3185 two registers are used in the same as memory order, so the
3186 eight bytes with the lower memory address are in $f0. */
3188 fprintf_unfiltered (gdb_stderr
, "Return float in $f0 and $f2\n");
3189 mips_xfer_register (gdbarch
, regcache
,
3190 gdbarch_num_regs (gdbarch
)
3191 + mips_regnum (gdbarch
)->fp0
,
3192 8, gdbarch_byte_order (gdbarch
),
3193 readbuf
, writebuf
, 0);
3194 mips_xfer_register (gdbarch
, regcache
,
3195 gdbarch_num_regs (gdbarch
)
3196 + mips_regnum (gdbarch
)->fp0
+ 2,
3197 8, gdbarch_byte_order (gdbarch
),
3198 readbuf
? readbuf
+ 8 : readbuf
,
3199 writebuf
? writebuf
+ 8 : writebuf
, 0);
3200 return RETURN_VALUE_REGISTER_CONVENTION
;
3202 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3203 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3205 /* A single or double floating-point value that fits in FP0. */
3207 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3208 mips_xfer_register (gdbarch
, regcache
,
3209 gdbarch_num_regs (gdbarch
)
3210 + mips_regnum (gdbarch
)->fp0
,
3212 gdbarch_byte_order (gdbarch
),
3213 readbuf
, writebuf
, 0);
3214 return RETURN_VALUE_REGISTER_CONVENTION
;
3216 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3217 && TYPE_NFIELDS (type
) <= 2
3218 && TYPE_NFIELDS (type
) >= 1
3219 && ((TYPE_NFIELDS (type
) == 1
3220 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
3222 || (TYPE_NFIELDS (type
) == 2
3223 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
3225 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 1)))
3227 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3229 /* A struct that contains one or two floats. Each value is part
3230 in the least significant part of their floating point
3234 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
3235 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3237 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3240 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3242 mips_xfer_register (gdbarch
, regcache
,
3243 gdbarch_num_regs (gdbarch
) + regnum
,
3244 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3245 gdbarch_byte_order (gdbarch
),
3246 readbuf
, writebuf
, offset
);
3248 return RETURN_VALUE_REGISTER_CONVENTION
;
3250 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3251 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3253 /* A structure or union. Extract the left justified value,
3254 regardless of the byte order. I.e. DO NOT USE
3258 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3259 offset
< TYPE_LENGTH (type
);
3260 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3262 int xfer
= register_size (gdbarch
, regnum
);
3263 if (offset
+ xfer
> TYPE_LENGTH (type
))
3264 xfer
= TYPE_LENGTH (type
) - offset
;
3266 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3267 offset
, xfer
, regnum
);
3268 mips_xfer_register (gdbarch
, regcache
,
3269 gdbarch_num_regs (gdbarch
) + regnum
,
3270 xfer
, BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
,
3273 return RETURN_VALUE_REGISTER_CONVENTION
;
3277 /* A scalar extract each part but least-significant-byte
3281 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3282 offset
< TYPE_LENGTH (type
);
3283 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3285 int xfer
= register_size (gdbarch
, regnum
);
3286 if (offset
+ xfer
> TYPE_LENGTH (type
))
3287 xfer
= TYPE_LENGTH (type
) - offset
;
3289 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3290 offset
, xfer
, regnum
);
3291 mips_xfer_register (gdbarch
, regcache
,
3292 gdbarch_num_regs (gdbarch
) + regnum
,
3293 xfer
, gdbarch_byte_order (gdbarch
),
3294 readbuf
, writebuf
, offset
);
3296 return RETURN_VALUE_REGISTER_CONVENTION
;
3300 /* O32 ABI stuff. */
3303 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3304 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3305 int nargs
, struct value
**args
, CORE_ADDR sp
,
3306 int struct_return
, CORE_ADDR struct_addr
)
3312 int stack_offset
= 0;
3313 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3314 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3316 /* For shared libraries, "t9" needs to point at the function
3318 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3320 /* Set the return address register to point to the entry point of
3321 the program, where a breakpoint lies in wait. */
3322 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3324 /* First ensure that the stack and structure return address (if any)
3325 are properly aligned. The stack has to be at least 64-bit
3326 aligned even on 32-bit machines, because doubles must be 64-bit
3327 aligned. For n32 and n64, stack frames need to be 128-bit
3328 aligned, so we round to this widest known alignment. */
3330 sp
= align_down (sp
, 16);
3331 struct_addr
= align_down (struct_addr
, 16);
3333 /* Now make space on the stack for the args. */
3334 for (argnum
= 0; argnum
< nargs
; argnum
++)
3336 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
3337 int arglen
= TYPE_LENGTH (arg_type
);
3339 /* Align to double-word if necessary. */
3340 if (mips_type_needs_double_align (arg_type
))
3341 len
= align_up (len
, MIPS32_REGSIZE
* 2);
3342 /* Allocate space on the stack. */
3343 len
+= align_up (arglen
, MIPS32_REGSIZE
);
3345 sp
-= align_up (len
, 16);
3348 fprintf_unfiltered (gdb_stdlog
,
3349 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
3350 paddr_nz (sp
), (long) align_up (len
, 16));
3352 /* Initialize the integer and float register pointers. */
3353 argreg
= MIPS_A0_REGNUM
;
3354 float_argreg
= mips_fpa0_regnum (gdbarch
);
3356 /* The struct_return pointer occupies the first parameter-passing reg. */
3360 fprintf_unfiltered (gdb_stdlog
,
3361 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
3362 argreg
, paddr_nz (struct_addr
));
3363 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3364 stack_offset
+= MIPS32_REGSIZE
;
3367 /* Now load as many as possible of the first arguments into
3368 registers, and push the rest onto the stack. Loop thru args
3369 from first to last. */
3370 for (argnum
= 0; argnum
< nargs
; argnum
++)
3372 const gdb_byte
*val
;
3373 struct value
*arg
= args
[argnum
];
3374 struct type
*arg_type
= check_typedef (value_type (arg
));
3375 int len
= TYPE_LENGTH (arg_type
);
3376 enum type_code typecode
= TYPE_CODE (arg_type
);
3379 fprintf_unfiltered (gdb_stdlog
,
3380 "mips_o32_push_dummy_call: %d len=%d type=%d",
3381 argnum
+ 1, len
, (int) typecode
);
3383 val
= value_contents (arg
);
3385 /* 32-bit ABIs always start floating point arguments in an
3386 even-numbered floating point register. Round the FP register
3387 up before the check to see if there are any FP registers
3388 left. O32/O64 targets also pass the FP in the integer
3389 registers so also round up normal registers. */
3390 if (fp_register_arg_p (typecode
, arg_type
))
3392 if ((float_argreg
& 1))
3396 /* Floating point arguments passed in registers have to be
3397 treated specially. On 32-bit architectures, doubles
3398 are passed in register pairs; the even register gets
3399 the low word, and the odd register gets the high word.
3400 On O32/O64, the first two floating point arguments are
3401 also copied to general registers, because MIPS16 functions
3402 don't use float registers for arguments. This duplication of
3403 arguments in general registers can't hurt non-MIPS16 functions
3404 because those registers are normally skipped. */
3406 if (fp_register_arg_p (typecode
, arg_type
)
3407 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3409 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
3411 int low_offset
= gdbarch_byte_order (gdbarch
)
3412 == BFD_ENDIAN_BIG
? 4 : 0;
3413 unsigned long regval
;
3415 /* Write the low word of the double to the even register(s). */
3416 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3418 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3419 float_argreg
, phex (regval
, 4));
3420 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3422 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3423 argreg
, phex (regval
, 4));
3424 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3426 /* Write the high word of the double to the odd register(s). */
3427 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3429 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3430 float_argreg
, phex (regval
, 4));
3431 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3434 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3435 argreg
, phex (regval
, 4));
3436 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3440 /* This is a floating point value that fits entirely
3441 in a single register. */
3442 /* On 32 bit ABI's the float_argreg is further adjusted
3443 above to ensure that it is even register aligned. */
3444 LONGEST regval
= extract_unsigned_integer (val
, len
);
3446 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3447 float_argreg
, phex (regval
, len
));
3448 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3449 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3450 registers for each argument. The below is (my
3451 guess) to ensure that the corresponding integer
3452 register has reserved the same space. */
3454 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3455 argreg
, phex (regval
, len
));
3456 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3459 /* Reserve space for the FP register. */
3460 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
3464 /* Copy the argument to general registers or the stack in
3465 register-sized pieces. Large arguments are split between
3466 registers and stack. */
3467 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
3468 are treated specially: Irix cc passes
3469 them in registers where gcc sometimes puts them on the
3470 stack. For maximum compatibility, we will put them in
3472 int odd_sized_struct
= (len
> MIPS32_REGSIZE
3473 && len
% MIPS32_REGSIZE
!= 0);
3474 /* Structures should be aligned to eight bytes (even arg registers)
3475 on MIPS_ABI_O32, if their first member has double precision. */
3476 if (mips_type_needs_double_align (arg_type
))
3481 stack_offset
+= MIPS32_REGSIZE
;
3486 /* Remember if the argument was written to the stack. */
3487 int stack_used_p
= 0;
3488 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
3491 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3494 /* Write this portion of the argument to the stack. */
3495 if (argreg
> MIPS_LAST_ARG_REGNUM
3496 || odd_sized_struct
)
3498 /* Should shorter than int integer values be
3499 promoted to int before being stored? */
3500 int longword_offset
= 0;
3506 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3507 paddr_nz (stack_offset
));
3508 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3509 paddr_nz (longword_offset
));
3512 addr
= sp
+ stack_offset
+ longword_offset
;
3517 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3519 for (i
= 0; i
< partial_len
; i
++)
3521 fprintf_unfiltered (gdb_stdlog
, "%02x",
3525 write_memory (addr
, val
, partial_len
);
3528 /* Note!!! This is NOT an else clause. Odd sized
3529 structs may go thru BOTH paths. */
3530 /* Write this portion of the argument to a general
3531 purpose register. */
3532 if (argreg
<= MIPS_LAST_ARG_REGNUM
)
3534 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3535 /* Value may need to be sign extended, because
3536 mips_isa_regsize() != mips_abi_regsize(). */
3538 /* A non-floating-point argument being passed in a
3539 general register. If a struct or union, and if
3540 the remaining length is smaller than the register
3541 size, we have to adjust the register value on
3544 It does not seem to be necessary to do the
3545 same for integral types.
3547 Also don't do this adjustment on O64 binaries.
3549 cagney/2001-07-23: gdb/179: Also, GCC, when
3550 outputting LE O32 with sizeof (struct) <
3551 mips_abi_regsize(), generates a left shift
3552 as part of storing the argument in a register
3553 (the left shift isn't generated when
3554 sizeof (struct) >= mips_abi_regsize()). Since
3555 it is quite possible that this is GCC
3556 contradicting the LE/O32 ABI, GDB has not been
3557 adjusted to accommodate this. Either someone
3558 needs to demonstrate that the LE/O32 ABI
3559 specifies such a left shift OR this new ABI gets
3560 identified as such and GDB gets tweaked
3563 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
3564 && partial_len
< MIPS32_REGSIZE
3565 && (typecode
== TYPE_CODE_STRUCT
3566 || typecode
== TYPE_CODE_UNION
))
3567 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
3571 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3573 phex (regval
, MIPS32_REGSIZE
));
3574 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3577 /* Prevent subsequent floating point arguments from
3578 being passed in floating point registers. */
3579 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3585 /* Compute the the offset into the stack at which we
3586 will copy the next parameter.
3588 In older ABIs, the caller reserved space for
3589 registers that contained arguments. This was loosely
3590 refered to as their "home". Consequently, space is
3591 always allocated. */
3593 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
3597 fprintf_unfiltered (gdb_stdlog
, "\n");
3600 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3602 /* Return adjusted stack pointer. */
3606 static enum return_value_convention
3607 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
3608 struct regcache
*regcache
,
3609 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3611 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3613 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3614 || TYPE_CODE (type
) == TYPE_CODE_UNION
3615 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3616 return RETURN_VALUE_STRUCT_CONVENTION
;
3617 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3618 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3620 /* A single-precision floating-point value. It fits in the
3621 least significant part of FP0. */
3623 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3624 mips_xfer_register (gdbarch
, regcache
,
3625 gdbarch_num_regs (gdbarch
)
3626 + mips_regnum (gdbarch
)->fp0
,
3628 gdbarch_byte_order (gdbarch
),
3629 readbuf
, writebuf
, 0);
3630 return RETURN_VALUE_REGISTER_CONVENTION
;
3632 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3633 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3635 /* A double-precision floating-point value. The most
3636 significant part goes in FP1, and the least significant in
3639 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
3640 switch (gdbarch_byte_order (gdbarch
))
3642 case BFD_ENDIAN_LITTLE
:
3643 mips_xfer_register (gdbarch
, regcache
,
3644 gdbarch_num_regs (gdbarch
)
3645 + mips_regnum (gdbarch
)->fp0
+
3646 0, 4, gdbarch_byte_order (gdbarch
),
3647 readbuf
, writebuf
, 0);
3648 mips_xfer_register (gdbarch
, regcache
,
3649 gdbarch_num_regs (gdbarch
)
3650 + mips_regnum (gdbarch
)->fp0
+ 1,
3651 4, gdbarch_byte_order (gdbarch
),
3652 readbuf
, writebuf
, 4);
3654 case BFD_ENDIAN_BIG
:
3655 mips_xfer_register (gdbarch
, regcache
,
3656 gdbarch_num_regs (gdbarch
)
3657 + mips_regnum (gdbarch
)->fp0
+ 1,
3658 4, gdbarch_byte_order (gdbarch
),
3659 readbuf
, writebuf
, 0);
3660 mips_xfer_register (gdbarch
, regcache
,
3661 gdbarch_num_regs (gdbarch
)
3662 + mips_regnum (gdbarch
)->fp0
+ 0,
3663 4, gdbarch_byte_order (gdbarch
),
3664 readbuf
, writebuf
, 4);
3667 internal_error (__FILE__
, __LINE__
, _("bad switch"));
3669 return RETURN_VALUE_REGISTER_CONVENTION
;
3672 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3673 && TYPE_NFIELDS (type
) <= 2
3674 && TYPE_NFIELDS (type
) >= 1
3675 && ((TYPE_NFIELDS (type
) == 1
3676 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3678 || (TYPE_NFIELDS (type
) == 2
3679 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3681 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
3683 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3685 /* A struct that contains one or two floats. Each value is part
3686 in the least significant part of their floating point
3688 gdb_byte reg
[MAX_REGISTER_SIZE
];
3691 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
3692 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3694 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3697 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3699 mips_xfer_register (gdbarch
, regcache
,
3700 gdbarch_num_regs (gdbarch
) + regnum
,
3701 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3702 gdbarch_byte_order (gdbarch
),
3703 readbuf
, writebuf
, offset
);
3705 return RETURN_VALUE_REGISTER_CONVENTION
;
3709 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3710 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3712 /* A structure or union. Extract the left justified value,
3713 regardless of the byte order. I.e. DO NOT USE
3717 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3718 offset
< TYPE_LENGTH (type
);
3719 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3721 int xfer
= register_size (gdbarch
, regnum
);
3722 if (offset
+ xfer
> TYPE_LENGTH (type
))
3723 xfer
= TYPE_LENGTH (type
) - offset
;
3725 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3726 offset
, xfer
, regnum
);
3727 mips_xfer_register (gdbarch
, regcache
,
3728 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
3729 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
3731 return RETURN_VALUE_REGISTER_CONVENTION
;
3736 /* A scalar extract each part but least-significant-byte
3737 justified. o32 thinks registers are 4 byte, regardless of
3741 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3742 offset
< TYPE_LENGTH (type
);
3743 offset
+= MIPS32_REGSIZE
, regnum
++)
3745 int xfer
= MIPS32_REGSIZE
;
3746 if (offset
+ xfer
> TYPE_LENGTH (type
))
3747 xfer
= TYPE_LENGTH (type
) - offset
;
3749 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3750 offset
, xfer
, regnum
);
3751 mips_xfer_register (gdbarch
, regcache
,
3752 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
3753 gdbarch_byte_order (gdbarch
),
3754 readbuf
, writebuf
, offset
);
3756 return RETURN_VALUE_REGISTER_CONVENTION
;
3760 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
3764 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3765 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3767 struct value
**args
, CORE_ADDR sp
,
3768 int struct_return
, CORE_ADDR struct_addr
)
3774 int stack_offset
= 0;
3775 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3776 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3778 /* For shared libraries, "t9" needs to point at the function
3780 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3782 /* Set the return address register to point to the entry point of
3783 the program, where a breakpoint lies in wait. */
3784 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3786 /* First ensure that the stack and structure return address (if any)
3787 are properly aligned. The stack has to be at least 64-bit
3788 aligned even on 32-bit machines, because doubles must be 64-bit
3789 aligned. For n32 and n64, stack frames need to be 128-bit
3790 aligned, so we round to this widest known alignment. */
3792 sp
= align_down (sp
, 16);
3793 struct_addr
= align_down (struct_addr
, 16);
3795 /* Now make space on the stack for the args. */
3796 for (argnum
= 0; argnum
< nargs
; argnum
++)
3798 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
3799 int arglen
= TYPE_LENGTH (arg_type
);
3801 /* Allocate space on the stack. */
3802 len
+= align_up (arglen
, MIPS64_REGSIZE
);
3804 sp
-= align_up (len
, 16);
3807 fprintf_unfiltered (gdb_stdlog
,
3808 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
3809 paddr_nz (sp
), (long) align_up (len
, 16));
3811 /* Initialize the integer and float register pointers. */
3812 argreg
= MIPS_A0_REGNUM
;
3813 float_argreg
= mips_fpa0_regnum (gdbarch
);
3815 /* The struct_return pointer occupies the first parameter-passing reg. */
3819 fprintf_unfiltered (gdb_stdlog
,
3820 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
3821 argreg
, paddr_nz (struct_addr
));
3822 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3823 stack_offset
+= MIPS64_REGSIZE
;
3826 /* Now load as many as possible of the first arguments into
3827 registers, and push the rest onto the stack. Loop thru args
3828 from first to last. */
3829 for (argnum
= 0; argnum
< nargs
; argnum
++)
3831 const gdb_byte
*val
;
3832 struct value
*arg
= args
[argnum
];
3833 struct type
*arg_type
= check_typedef (value_type (arg
));
3834 int len
= TYPE_LENGTH (arg_type
);
3835 enum type_code typecode
= TYPE_CODE (arg_type
);
3838 fprintf_unfiltered (gdb_stdlog
,
3839 "mips_o64_push_dummy_call: %d len=%d type=%d",
3840 argnum
+ 1, len
, (int) typecode
);
3842 val
= value_contents (arg
);
3844 /* Floating point arguments passed in registers have to be
3845 treated specially. On 32-bit architectures, doubles
3846 are passed in register pairs; the even register gets
3847 the low word, and the odd register gets the high word.
3848 On O32/O64, the first two floating point arguments are
3849 also copied to general registers, because MIPS16 functions
3850 don't use float registers for arguments. This duplication of
3851 arguments in general registers can't hurt non-MIPS16 functions
3852 because those registers are normally skipped. */
3854 if (fp_register_arg_p (typecode
, arg_type
)
3855 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3857 LONGEST regval
= extract_unsigned_integer (val
, len
);
3859 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3860 float_argreg
, phex (regval
, len
));
3861 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3863 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3864 argreg
, phex (regval
, len
));
3865 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3867 /* Reserve space for the FP register. */
3868 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
3872 /* Copy the argument to general registers or the stack in
3873 register-sized pieces. Large arguments are split between
3874 registers and stack. */
3875 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
3876 are treated specially: Irix cc passes them in registers
3877 where gcc sometimes puts them on the stack. For maximum
3878 compatibility, we will put them in both places. */
3879 int odd_sized_struct
= (len
> MIPS64_REGSIZE
3880 && len
% MIPS64_REGSIZE
!= 0);
3883 /* Remember if the argument was written to the stack. */
3884 int stack_used_p
= 0;
3885 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
3888 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3891 /* Write this portion of the argument to the stack. */
3892 if (argreg
> MIPS_LAST_ARG_REGNUM
3893 || odd_sized_struct
)
3895 /* Should shorter than int integer values be
3896 promoted to int before being stored? */
3897 int longword_offset
= 0;
3900 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
3902 if ((typecode
== TYPE_CODE_INT
3903 || typecode
== TYPE_CODE_PTR
3904 || typecode
== TYPE_CODE_FLT
)
3906 longword_offset
= MIPS64_REGSIZE
- len
;
3911 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3912 paddr_nz (stack_offset
));
3913 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3914 paddr_nz (longword_offset
));
3917 addr
= sp
+ stack_offset
+ longword_offset
;
3922 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3924 for (i
= 0; i
< partial_len
; i
++)
3926 fprintf_unfiltered (gdb_stdlog
, "%02x",
3930 write_memory (addr
, val
, partial_len
);
3933 /* Note!!! This is NOT an else clause. Odd sized
3934 structs may go thru BOTH paths. */
3935 /* Write this portion of the argument to a general
3936 purpose register. */
3937 if (argreg
<= MIPS_LAST_ARG_REGNUM
)
3939 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3940 /* Value may need to be sign extended, because
3941 mips_isa_regsize() != mips_abi_regsize(). */
3943 /* A non-floating-point argument being passed in a
3944 general register. If a struct or union, and if
3945 the remaining length is smaller than the register
3946 size, we have to adjust the register value on
3949 It does not seem to be necessary to do the
3950 same for integral types. */
3952 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
3953 && partial_len
< MIPS64_REGSIZE
3954 && (typecode
== TYPE_CODE_STRUCT
3955 || typecode
== TYPE_CODE_UNION
))
3956 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
3960 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3962 phex (regval
, MIPS64_REGSIZE
));
3963 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3966 /* Prevent subsequent floating point arguments from
3967 being passed in floating point registers. */
3968 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3974 /* Compute the the offset into the stack at which we
3975 will copy the next parameter.
3977 In older ABIs, the caller reserved space for
3978 registers that contained arguments. This was loosely
3979 refered to as their "home". Consequently, space is
3980 always allocated. */
3982 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
3986 fprintf_unfiltered (gdb_stdlog
, "\n");
3989 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3991 /* Return adjusted stack pointer. */
3995 static enum return_value_convention
3996 mips_o64_return_value (struct gdbarch
*gdbarch
,
3997 struct type
*type
, struct regcache
*regcache
,
3998 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4000 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4002 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4003 || TYPE_CODE (type
) == TYPE_CODE_UNION
4004 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
4005 return RETURN_VALUE_STRUCT_CONVENTION
;
4006 else if (fp_register_arg_p (TYPE_CODE (type
), type
))
4008 /* A floating-point value. It fits in the least significant
4011 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4012 mips_xfer_register (gdbarch
, regcache
,
4013 gdbarch_num_regs (gdbarch
)
4014 + mips_regnum (gdbarch
)->fp0
,
4016 gdbarch_byte_order (gdbarch
),
4017 readbuf
, writebuf
, 0);
4018 return RETURN_VALUE_REGISTER_CONVENTION
;
4022 /* A scalar extract each part but least-significant-byte
4026 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
4027 offset
< TYPE_LENGTH (type
);
4028 offset
+= MIPS64_REGSIZE
, regnum
++)
4030 int xfer
= MIPS64_REGSIZE
;
4031 if (offset
+ xfer
> TYPE_LENGTH (type
))
4032 xfer
= TYPE_LENGTH (type
) - offset
;
4034 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4035 offset
, xfer
, regnum
);
4036 mips_xfer_register (gdbarch
, regcache
,
4037 gdbarch_num_regs (gdbarch
) + regnum
,
4038 xfer
, gdbarch_byte_order (gdbarch
),
4039 readbuf
, writebuf
, offset
);
4041 return RETURN_VALUE_REGISTER_CONVENTION
;
4045 /* Floating point register management.
4047 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
4048 64bit operations, these early MIPS cpus treat fp register pairs
4049 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
4050 registers and offer a compatibility mode that emulates the MIPS2 fp
4051 model. When operating in MIPS2 fp compat mode, later cpu's split
4052 double precision floats into two 32-bit chunks and store them in
4053 consecutive fp regs. To display 64-bit floats stored in this
4054 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
4055 Throw in user-configurable endianness and you have a real mess.
4057 The way this works is:
4058 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4059 double-precision value will be split across two logical registers.
4060 The lower-numbered logical register will hold the low-order bits,
4061 regardless of the processor's endianness.
4062 - If we are on a 64-bit processor, and we are looking for a
4063 single-precision value, it will be in the low ordered bits
4064 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4065 save slot in memory.
4066 - If we are in 64-bit mode, everything is straightforward.
4068 Note that this code only deals with "live" registers at the top of the
4069 stack. We will attempt to deal with saved registers later, when
4070 the raw/cooked register interface is in place. (We need a general
4071 interface that can deal with dynamic saved register sizes -- fp
4072 regs could be 32 bits wide in one frame and 64 on the frame above
4075 static struct type
*
4076 mips_float_register_type (void)
4078 return builtin_type_ieee_single
;
4081 static struct type
*
4082 mips_double_register_type (void)
4084 return builtin_type_ieee_double
;
4087 /* Copy a 32-bit single-precision value from the current frame
4088 into rare_buffer. */
4091 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
4092 gdb_byte
*rare_buffer
)
4094 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4095 int raw_size
= register_size (gdbarch
, regno
);
4096 gdb_byte
*raw_buffer
= alloca (raw_size
);
4098 if (!frame_register_read (frame
, regno
, raw_buffer
))
4099 error (_("can't read register %d (%s)"),
4100 regno
, gdbarch_register_name (gdbarch
, regno
));
4103 /* We have a 64-bit value for this register. Find the low-order
4107 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4112 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
4116 memcpy (rare_buffer
, raw_buffer
, 4);
4120 /* Copy a 64-bit double-precision value from the current frame into
4121 rare_buffer. This may include getting half of it from the next
4125 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
4126 gdb_byte
*rare_buffer
)
4128 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4129 int raw_size
= register_size (gdbarch
, regno
);
4131 if (raw_size
== 8 && !mips2_fp_compat (frame
))
4133 /* We have a 64-bit value for this register, and we should use
4135 if (!frame_register_read (frame
, regno
, rare_buffer
))
4136 error (_("can't read register %d (%s)"),
4137 regno
, gdbarch_register_name (gdbarch
, regno
));
4141 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
4143 if ((rawnum
- mips_regnum (gdbarch
)->fp0
) & 1)
4144 internal_error (__FILE__
, __LINE__
,
4145 _("mips_read_fp_register_double: bad access to "
4146 "odd-numbered FP register"));
4148 /* mips_read_fp_register_single will find the correct 32 bits from
4150 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4152 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
4153 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
4157 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
4158 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4164 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4166 { /* do values for FP (float) regs */
4167 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4168 gdb_byte
*raw_buffer
;
4169 double doub
, flt1
; /* doubles extracted from raw hex data */
4172 raw_buffer
= alloca (2 * register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
));
4174 fprintf_filtered (file
, "%s:", gdbarch_register_name (gdbarch
, regnum
));
4175 fprintf_filtered (file
, "%*s",
4176 4 - (int) strlen (gdbarch_register_name (gdbarch
, regnum
)),
4179 if (register_size (gdbarch
, regnum
) == 4 || mips2_fp_compat (frame
))
4181 /* 4-byte registers: Print hex and floating. Also print even
4182 numbered registers as doubles. */
4183 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4184 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4186 print_scalar_formatted (raw_buffer
, builtin_type_uint32
, 'x', 'w',
4189 fprintf_filtered (file
, " flt: ");
4191 fprintf_filtered (file
, " <invalid float> ");
4193 fprintf_filtered (file
, "%-17.9g", flt1
);
4195 if ((regnum
- gdbarch_num_regs (gdbarch
)) % 2 == 0)
4197 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4198 doub
= unpack_double (mips_double_register_type (), raw_buffer
,
4201 fprintf_filtered (file
, " dbl: ");
4203 fprintf_filtered (file
, "<invalid double>");
4205 fprintf_filtered (file
, "%-24.17g", doub
);
4210 /* Eight byte registers: print each one as hex, float and double. */
4211 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4212 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4214 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4215 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv2
);
4218 print_scalar_formatted (raw_buffer
, builtin_type_uint64
, 'x', 'g',
4221 fprintf_filtered (file
, " flt: ");
4223 fprintf_filtered (file
, "<invalid float>");
4225 fprintf_filtered (file
, "%-17.9g", flt1
);
4227 fprintf_filtered (file
, " dbl: ");
4229 fprintf_filtered (file
, "<invalid double>");
4231 fprintf_filtered (file
, "%-24.17g", doub
);
4236 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4239 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4240 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
4243 if (TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4245 mips_print_fp_register (file
, frame
, regnum
);
4249 /* Get the data in raw format. */
4250 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4252 fprintf_filtered (file
, "%s: [Invalid]",
4253 gdbarch_register_name (gdbarch
, regnum
));
4257 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
4259 /* The problem with printing numeric register names (r26, etc.) is that
4260 the user can't use them on input. Probably the best solution is to
4261 fix it so that either the numeric or the funky (a2, etc.) names
4262 are accepted on input. */
4263 if (regnum
< MIPS_NUMREGS
)
4264 fprintf_filtered (file
, "(r%d): ", regnum
);
4266 fprintf_filtered (file
, ": ");
4268 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4270 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
4274 print_scalar_formatted (raw_buffer
+ offset
,
4275 register_type (gdbarch
, regnum
), 'x', 0,
4279 /* Replacement for generic do_registers_info.
4280 Print regs in pretty columns. */
4283 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4286 fprintf_filtered (file
, " ");
4287 mips_print_fp_register (file
, frame
, regnum
);
4288 fprintf_filtered (file
, "\n");
4293 /* Print a row's worth of GP (int) registers, with name labels above */
4296 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4299 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4300 /* do values for GP (int) regs */
4301 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
4302 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols per row */
4306 /* For GP registers, we print a separate row of names above the vals */
4307 for (col
= 0, regnum
= start_regnum
;
4308 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
4309 + gdbarch_num_pseudo_regs (gdbarch
);
4312 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
4313 continue; /* unused register */
4314 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4316 break; /* end the row: reached FP register */
4317 /* Large registers are handled separately. */
4318 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
4321 break; /* End the row before this register. */
4323 /* Print this register on a row by itself. */
4324 mips_print_register (file
, frame
, regnum
);
4325 fprintf_filtered (file
, "\n");
4329 fprintf_filtered (file
, " ");
4330 fprintf_filtered (file
,
4331 mips_abi_regsize (gdbarch
) == 8 ? "%17s" : "%9s",
4332 gdbarch_register_name (gdbarch
, regnum
));
4339 /* print the R0 to R31 names */
4340 if ((start_regnum
% gdbarch_num_regs (gdbarch
)) < MIPS_NUMREGS
)
4341 fprintf_filtered (file
, "\n R%-4d",
4342 start_regnum
% gdbarch_num_regs (gdbarch
));
4344 fprintf_filtered (file
, "\n ");
4346 /* now print the values in hex, 4 or 8 to the row */
4347 for (col
= 0, regnum
= start_regnum
;
4348 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
4349 + gdbarch_num_pseudo_regs (gdbarch
);
4352 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
4353 continue; /* unused register */
4354 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4356 break; /* end row: reached FP register */
4357 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
4358 break; /* End row: large register. */
4360 /* OK: get the data in raw format. */
4361 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4362 error (_("can't read register %d (%s)"),
4363 regnum
, gdbarch_register_name (gdbarch
, regnum
));
4364 /* pad small registers */
4366 byte
< (mips_abi_regsize (gdbarch
)
4367 - register_size (gdbarch
, regnum
)); byte
++)
4368 printf_filtered (" ");
4369 /* Now print the register value in hex, endian order. */
4370 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4372 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
4373 byte
< register_size (gdbarch
, regnum
); byte
++)
4374 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4376 for (byte
= register_size (gdbarch
, regnum
) - 1;
4378 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4379 fprintf_filtered (file
, " ");
4382 if (col
> 0) /* ie. if we actually printed anything... */
4383 fprintf_filtered (file
, "\n");
4388 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4391 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4392 struct frame_info
*frame
, int regnum
, int all
)
4394 if (regnum
!= -1) /* do one specified register */
4396 gdb_assert (regnum
>= gdbarch_num_regs (gdbarch
));
4397 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
4398 error (_("Not a valid register for the current processor type"));
4400 mips_print_register (file
, frame
, regnum
);
4401 fprintf_filtered (file
, "\n");
4404 /* do all (or most) registers */
4406 regnum
= gdbarch_num_regs (gdbarch
);
4407 while (regnum
< gdbarch_num_regs (gdbarch
)
4408 + gdbarch_num_pseudo_regs (gdbarch
))
4410 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4413 if (all
) /* true for "INFO ALL-REGISTERS" command */
4414 regnum
= print_fp_register_row (file
, frame
, regnum
);
4416 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
4419 regnum
= print_gp_register_row (file
, frame
, regnum
);
4424 /* Is this a branch with a delay slot? */
4427 is_delayed (unsigned long insn
)
4430 for (i
= 0; i
< NUMOPCODES
; ++i
)
4431 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4432 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4434 return (i
< NUMOPCODES
4435 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4436 | INSN_COND_BRANCH_DELAY
4437 | INSN_COND_BRANCH_LIKELY
)));
4441 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
4442 struct frame_info
*frame
)
4444 CORE_ADDR pc
= get_frame_pc (frame
);
4445 gdb_byte buf
[MIPS_INSN32_SIZE
];
4447 /* There is no branch delay slot on MIPS16. */
4448 if (mips_pc_is_mips16 (pc
))
4451 if (!breakpoint_here_p (pc
+ 4))
4454 if (!safe_frame_unwind_memory (frame
, pc
, buf
, sizeof buf
))
4455 /* If error reading memory, guess that it is not a delayed
4458 return is_delayed (extract_unsigned_integer (buf
, sizeof buf
));
4461 /* To skip prologues, I use this predicate. Returns either PC itself
4462 if the code at PC does not look like a function prologue; otherwise
4463 returns an address that (if we're lucky) follows the prologue. If
4464 LENIENT, then we must skip everything which is involved in setting
4465 up the frame (it's OK to skip more, just so long as we don't skip
4466 anything which might clobber the registers which are being saved.
4467 We must skip more in the case where part of the prologue is in the
4468 delay slot of a non-prologue instruction). */
4471 mips_skip_prologue (CORE_ADDR pc
)
4474 CORE_ADDR func_addr
;
4476 /* See if we can determine the end of the prologue via the symbol table.
4477 If so, then return either PC, or the PC after the prologue, whichever
4479 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
4481 CORE_ADDR post_prologue_pc
= skip_prologue_using_sal (func_addr
);
4482 if (post_prologue_pc
!= 0)
4483 return max (pc
, post_prologue_pc
);
4486 /* Can't determine prologue from the symbol table, need to examine
4489 /* Find an upper limit on the function prologue using the debug
4490 information. If the debug information could not be used to provide
4491 that bound, then use an arbitrary large number as the upper bound. */
4492 limit_pc
= skip_prologue_using_sal (pc
);
4494 limit_pc
= pc
+ 100; /* Magic. */
4496 if (mips_pc_is_mips16 (pc
))
4497 return mips16_scan_prologue (pc
, limit_pc
, NULL
, NULL
);
4499 return mips32_scan_prologue (pc
, limit_pc
, NULL
, NULL
);
4502 /* Check whether the PC is in a function epilogue (32-bit version).
4503 This is a helper function for mips_in_function_epilogue_p. */
4505 mips32_in_function_epilogue_p (CORE_ADDR pc
)
4507 CORE_ADDR func_addr
= 0, func_end
= 0;
4509 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
4511 /* The MIPS epilogue is max. 12 bytes long. */
4512 CORE_ADDR addr
= func_end
- 12;
4514 if (addr
< func_addr
+ 4)
4515 addr
= func_addr
+ 4;
4519 for (; pc
< func_end
; pc
+= MIPS_INSN32_SIZE
)
4521 unsigned long high_word
;
4524 inst
= mips_fetch_instruction (pc
);
4525 high_word
= (inst
>> 16) & 0xffff;
4527 if (high_word
!= 0x27bd /* addiu $sp,$sp,offset */
4528 && high_word
!= 0x67bd /* daddiu $sp,$sp,offset */
4529 && inst
!= 0x03e00008 /* jr $ra */
4530 && inst
!= 0x00000000) /* nop */
4540 /* Check whether the PC is in a function epilogue (16-bit version).
4541 This is a helper function for mips_in_function_epilogue_p. */
4543 mips16_in_function_epilogue_p (CORE_ADDR pc
)
4545 CORE_ADDR func_addr
= 0, func_end
= 0;
4547 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
4549 /* The MIPS epilogue is max. 12 bytes long. */
4550 CORE_ADDR addr
= func_end
- 12;
4552 if (addr
< func_addr
+ 4)
4553 addr
= func_addr
+ 4;
4557 for (; pc
< func_end
; pc
+= MIPS_INSN16_SIZE
)
4559 unsigned short inst
;
4561 inst
= mips_fetch_instruction (pc
);
4563 if ((inst
& 0xf800) == 0xf000) /* extend */
4566 if (inst
!= 0x6300 /* addiu $sp,offset */
4567 && inst
!= 0xfb00 /* daddiu $sp,$sp,offset */
4568 && inst
!= 0xe820 /* jr $ra */
4569 && inst
!= 0xe8a0 /* jrc $ra */
4570 && inst
!= 0x6500) /* nop */
4580 /* The epilogue is defined here as the area at the end of a function,
4581 after an instruction which destroys the function's stack frame. */
4583 mips_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4585 if (mips_pc_is_mips16 (pc
))
4586 return mips16_in_function_epilogue_p (pc
);
4588 return mips32_in_function_epilogue_p (pc
);
4591 /* Root of all "set mips "/"show mips " commands. This will eventually be
4592 used for all MIPS-specific commands. */
4595 show_mips_command (char *args
, int from_tty
)
4597 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
4601 set_mips_command (char *args
, int from_tty
)
4604 ("\"set mips\" must be followed by an appropriate subcommand.\n");
4605 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
4608 /* Commands to show/set the MIPS FPU type. */
4611 show_mipsfpu_command (char *args
, int from_tty
)
4615 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_mips
)
4618 ("The MIPS floating-point coprocessor is unknown "
4619 "because the current architecture is not MIPS.\n");
4623 switch (MIPS_FPU_TYPE
)
4625 case MIPS_FPU_SINGLE
:
4626 fpu
= "single-precision";
4628 case MIPS_FPU_DOUBLE
:
4629 fpu
= "double-precision";
4632 fpu
= "absent (none)";
4635 internal_error (__FILE__
, __LINE__
, _("bad switch"));
4637 if (mips_fpu_type_auto
)
4639 ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
4643 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
4648 set_mipsfpu_command (char *args
, int from_tty
)
4651 ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
4652 show_mipsfpu_command (args
, from_tty
);
4656 set_mipsfpu_single_command (char *args
, int from_tty
)
4658 struct gdbarch_info info
;
4659 gdbarch_info_init (&info
);
4660 mips_fpu_type
= MIPS_FPU_SINGLE
;
4661 mips_fpu_type_auto
= 0;
4662 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4663 instead of relying on globals. Doing that would let generic code
4664 handle the search for this specific architecture. */
4665 if (!gdbarch_update_p (info
))
4666 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4670 set_mipsfpu_double_command (char *args
, int from_tty
)
4672 struct gdbarch_info info
;
4673 gdbarch_info_init (&info
);
4674 mips_fpu_type
= MIPS_FPU_DOUBLE
;
4675 mips_fpu_type_auto
= 0;
4676 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4677 instead of relying on globals. Doing that would let generic code
4678 handle the search for this specific architecture. */
4679 if (!gdbarch_update_p (info
))
4680 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4684 set_mipsfpu_none_command (char *args
, int from_tty
)
4686 struct gdbarch_info info
;
4687 gdbarch_info_init (&info
);
4688 mips_fpu_type
= MIPS_FPU_NONE
;
4689 mips_fpu_type_auto
= 0;
4690 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4691 instead of relying on globals. Doing that would let generic code
4692 handle the search for this specific architecture. */
4693 if (!gdbarch_update_p (info
))
4694 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4698 set_mipsfpu_auto_command (char *args
, int from_tty
)
4700 mips_fpu_type_auto
= 1;
4703 /* Attempt to identify the particular processor model by reading the
4704 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
4705 the relevant processor still exists (it dates back to '94) and
4706 secondly this is not the way to do this. The processor type should
4707 be set by forcing an architecture change. */
4710 deprecated_mips_set_processor_regs_hack (void)
4712 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4715 regcache_cooked_read_unsigned (get_current_regcache (),
4716 MIPS_PRID_REGNUM
, &prid
);
4717 if ((prid
& ~0xf) == 0x700)
4718 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
4721 /* Just like reinit_frame_cache, but with the right arguments to be
4722 callable as an sfunc. */
4725 reinit_frame_cache_sfunc (char *args
, int from_tty
,
4726 struct cmd_list_element
*c
)
4728 reinit_frame_cache ();
4732 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
4734 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4736 /* FIXME: cagney/2003-06-26: Is this even necessary? The
4737 disassembler needs to be able to locally determine the ISA, and
4738 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
4740 if (mips_pc_is_mips16 (memaddr
))
4741 info
->mach
= bfd_mach_mips16
;
4743 /* Round down the instruction address to the appropriate boundary. */
4744 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
4746 /* Set the disassembler options. */
4747 if (tdep
->mips_abi
== MIPS_ABI_N32
|| tdep
->mips_abi
== MIPS_ABI_N64
)
4749 /* Set up the disassembler info, so that we get the right
4750 register names from libopcodes. */
4751 if (tdep
->mips_abi
== MIPS_ABI_N32
)
4752 info
->disassembler_options
= "gpr-names=n32";
4754 info
->disassembler_options
= "gpr-names=64";
4755 info
->flavour
= bfd_target_elf_flavour
;
4758 /* This string is not recognized explicitly by the disassembler,
4759 but it tells the disassembler to not try to guess the ABI from
4760 the bfd elf headers, such that, if the user overrides the ABI
4761 of a program linked as NewABI, the disassembly will follow the
4762 register naming conventions specified by the user. */
4763 info
->disassembler_options
= "gpr-names=32";
4765 /* Call the appropriate disassembler based on the target endian-ness. */
4766 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
4767 return print_insn_big_mips (memaddr
, info
);
4769 return print_insn_little_mips (memaddr
, info
);
4772 /* This function implements gdbarch_breakpoint_from_pc. It uses the program
4773 counter value to determine whether a 16- or 32-bit breakpoint should be used.
4774 It returns a pointer to a string of bytes that encode a breakpoint
4775 instruction, stores the length of the string to *lenptr, and adjusts pc (if
4776 necessary) to point to the actual memory location where the breakpoint
4777 should be inserted. */
4779 static const gdb_byte
*
4780 mips_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
, int *lenptr
)
4782 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4784 if (mips_pc_is_mips16 (*pcptr
))
4786 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
4787 *pcptr
= unmake_mips16_addr (*pcptr
);
4788 *lenptr
= sizeof (mips16_big_breakpoint
);
4789 return mips16_big_breakpoint
;
4793 /* The IDT board uses an unusual breakpoint value, and
4794 sometimes gets confused when it sees the usual MIPS
4795 breakpoint instruction. */
4796 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
4797 static gdb_byte pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
4798 static gdb_byte idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
4800 *lenptr
= sizeof (big_breakpoint
);
4802 if (strcmp (target_shortname
, "mips") == 0)
4803 return idt_big_breakpoint
;
4804 else if (strcmp (target_shortname
, "ddb") == 0
4805 || strcmp (target_shortname
, "pmon") == 0
4806 || strcmp (target_shortname
, "lsi") == 0)
4807 return pmon_big_breakpoint
;
4809 return big_breakpoint
;
4814 if (mips_pc_is_mips16 (*pcptr
))
4816 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
4817 *pcptr
= unmake_mips16_addr (*pcptr
);
4818 *lenptr
= sizeof (mips16_little_breakpoint
);
4819 return mips16_little_breakpoint
;
4823 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
4824 static gdb_byte pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
4825 static gdb_byte idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
4827 *lenptr
= sizeof (little_breakpoint
);
4829 if (strcmp (target_shortname
, "mips") == 0)
4830 return idt_little_breakpoint
;
4831 else if (strcmp (target_shortname
, "ddb") == 0
4832 || strcmp (target_shortname
, "pmon") == 0
4833 || strcmp (target_shortname
, "lsi") == 0)
4834 return pmon_little_breakpoint
;
4836 return little_breakpoint
;
4841 /* If PC is in a mips16 call or return stub, return the address of the target
4842 PC, which is either the callee or the caller. There are several
4843 cases which must be handled:
4845 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
4846 target PC is in $31 ($ra).
4847 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
4848 and the target PC is in $2.
4849 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4850 before the jal instruction, this is effectively a call stub
4851 and the the target PC is in $2. Otherwise this is effectively
4852 a return stub and the target PC is in $18.
4854 See the source code for the stubs in gcc/config/mips/mips16.S for
4858 mips_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
4861 CORE_ADDR start_addr
;
4863 /* Find the starting address and name of the function containing the PC. */
4864 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
4867 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
4868 target PC is in $31 ($ra). */
4869 if (strcmp (name
, "__mips16_ret_sf") == 0
4870 || strcmp (name
, "__mips16_ret_df") == 0)
4871 return get_frame_register_signed (frame
, MIPS_RA_REGNUM
);
4873 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
4875 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
4876 and the target PC is in $2. */
4877 if (name
[19] >= '0' && name
[19] <= '9')
4878 return get_frame_register_signed (frame
, 2);
4880 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4881 before the jal instruction, this is effectively a call stub
4882 and the the target PC is in $2. Otherwise this is effectively
4883 a return stub and the target PC is in $18. */
4884 else if (name
[19] == 's' || name
[19] == 'd')
4886 if (pc
== start_addr
)
4888 /* Check if the target of the stub is a compiler-generated
4889 stub. Such a stub for a function bar might have a name
4890 like __fn_stub_bar, and might look like this:
4895 la $1,bar (becomes a lui/addiu pair)
4897 So scan down to the lui/addi and extract the target
4898 address from those two instructions. */
4900 CORE_ADDR target_pc
= get_frame_register_signed (frame
, 2);
4904 /* See if the name of the target function is __fn_stub_*. */
4905 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) ==
4908 if (strncmp (name
, "__fn_stub_", 10) != 0
4909 && strcmp (name
, "etext") != 0
4910 && strcmp (name
, "_etext") != 0)
4913 /* Scan through this _fn_stub_ code for the lui/addiu pair.
4914 The limit on the search is arbitrarily set to 20
4915 instructions. FIXME. */
4916 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSN32_SIZE
)
4918 inst
= mips_fetch_instruction (target_pc
);
4919 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
4920 pc
= (inst
<< 16) & 0xffff0000; /* high word */
4921 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
4922 return pc
| (inst
& 0xffff); /* low word */
4925 /* Couldn't find the lui/addui pair, so return stub address. */
4929 /* This is the 'return' part of a call stub. The return
4930 address is in $r18. */
4931 return get_frame_register_signed (frame
, 18);
4934 return 0; /* not a stub */
4937 /* Convert a dbx stab register number (from `r' declaration) to a GDB
4938 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
4941 mips_stab_reg_to_regnum (int num
)
4944 if (num
>= 0 && num
< 32)
4946 else if (num
>= 38 && num
< 70)
4947 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 38;
4949 regnum
= mips_regnum (current_gdbarch
)->hi
;
4951 regnum
= mips_regnum (current_gdbarch
)->lo
;
4953 /* This will hopefully (eventually) provoke a warning. Should
4954 we be calling complaint() here? */
4955 return gdbarch_num_regs (current_gdbarch
)
4956 + gdbarch_num_pseudo_regs (current_gdbarch
);
4957 return gdbarch_num_regs (current_gdbarch
) + regnum
;
4961 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
4962 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
4965 mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num
)
4968 if (num
>= 0 && num
< 32)
4970 else if (num
>= 32 && num
< 64)
4971 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 32;
4973 regnum
= mips_regnum (current_gdbarch
)->hi
;
4975 regnum
= mips_regnum (current_gdbarch
)->lo
;
4977 /* This will hopefully (eventually) provoke a warning. Should we
4978 be calling complaint() here? */
4979 return gdbarch_num_regs (current_gdbarch
)
4980 + gdbarch_num_pseudo_regs (current_gdbarch
);
4981 return gdbarch_num_regs (current_gdbarch
) + regnum
;
4985 mips_register_sim_regno (int regnum
)
4987 /* Only makes sense to supply raw registers. */
4988 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (current_gdbarch
));
4989 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
4990 decide if it is valid. Should instead define a standard sim/gdb
4991 register numbering scheme. */
4992 if (gdbarch_register_name (current_gdbarch
,
4994 (current_gdbarch
) + regnum
) != NULL
4995 && gdbarch_register_name (current_gdbarch
,
4997 (current_gdbarch
) + regnum
)[0] != '\0')
5000 return LEGACY_SIM_REGNO_IGNORE
;
5004 /* Convert an integer into an address. Extracting the value signed
5005 guarantees a correctly sign extended address. */
5008 mips_integer_to_address (struct gdbarch
*gdbarch
,
5009 struct type
*type
, const gdb_byte
*buf
)
5011 return (CORE_ADDR
) extract_signed_integer (buf
, TYPE_LENGTH (type
));
5014 /* Dummy virtual frame pointer method. This is no more or less accurate
5015 than most other architectures; we just need to be explicit about it,
5016 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
5017 an assertion failure. */
5020 mips_virtual_frame_pointer (struct gdbarch
*gdbarch
,
5021 CORE_ADDR pc
, int *reg
, LONGEST
*offset
)
5023 *reg
= MIPS_SP_REGNUM
;
5028 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
5030 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
5031 const char *name
= bfd_get_section_name (abfd
, sect
);
5033 if (*abip
!= MIPS_ABI_UNKNOWN
)
5036 if (strncmp (name
, ".mdebug.", 8) != 0)
5039 if (strcmp (name
, ".mdebug.abi32") == 0)
5040 *abip
= MIPS_ABI_O32
;
5041 else if (strcmp (name
, ".mdebug.abiN32") == 0)
5042 *abip
= MIPS_ABI_N32
;
5043 else if (strcmp (name
, ".mdebug.abi64") == 0)
5044 *abip
= MIPS_ABI_N64
;
5045 else if (strcmp (name
, ".mdebug.abiO64") == 0)
5046 *abip
= MIPS_ABI_O64
;
5047 else if (strcmp (name
, ".mdebug.eabi32") == 0)
5048 *abip
= MIPS_ABI_EABI32
;
5049 else if (strcmp (name
, ".mdebug.eabi64") == 0)
5050 *abip
= MIPS_ABI_EABI64
;
5052 warning (_("unsupported ABI %s."), name
+ 8);
5056 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
5058 int *lbp
= (int *) obj
;
5059 const char *name
= bfd_get_section_name (abfd
, sect
);
5061 if (strncmp (name
, ".gcc_compiled_long32", 20) == 0)
5063 else if (strncmp (name
, ".gcc_compiled_long64", 20) == 0)
5065 else if (strncmp (name
, ".gcc_compiled_long", 18) == 0)
5066 warning (_("unrecognized .gcc_compiled_longXX"));
5069 static enum mips_abi
5070 global_mips_abi (void)
5074 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
5075 if (mips_abi_strings
[i
] == mips_abi_string
)
5076 return (enum mips_abi
) i
;
5078 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
5082 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
5084 /* If the size matches the set of 32-bit or 64-bit integer registers,
5085 assume that's what we've got. */
5086 register_remote_g_packet_guess (gdbarch
, 38 * 4, mips_tdesc_gp32
);
5087 register_remote_g_packet_guess (gdbarch
, 38 * 8, mips_tdesc_gp64
);
5089 /* If the size matches the full set of registers GDB traditionally
5090 knows about, including floating point, for either 32-bit or
5091 64-bit, assume that's what we've got. */
5092 register_remote_g_packet_guess (gdbarch
, 90 * 4, mips_tdesc_gp32
);
5093 register_remote_g_packet_guess (gdbarch
, 90 * 8, mips_tdesc_gp64
);
5095 /* Otherwise we don't have a useful guess. */
5098 static struct value
*
5099 value_of_mips_user_reg (struct frame_info
*frame
, const void *baton
)
5101 const int *reg_p
= baton
;
5102 return value_of_register (*reg_p
, frame
);
5105 static struct gdbarch
*
5106 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5108 struct gdbarch
*gdbarch
;
5109 struct gdbarch_tdep
*tdep
;
5111 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
5113 enum mips_fpu_type fpu_type
;
5114 struct tdesc_arch_data
*tdesc_data
= NULL
;
5115 int elf_fpu_type
= 0;
5117 /* Check any target description for validity. */
5118 if (tdesc_has_registers (info
.target_desc
))
5120 static const char *const mips_gprs
[] = {
5121 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5122 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5123 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5124 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
5126 static const char *const mips_fprs
[] = {
5127 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
5128 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
5129 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
5130 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
5133 const struct tdesc_feature
*feature
;
5136 feature
= tdesc_find_feature (info
.target_desc
,
5137 "org.gnu.gdb.mips.cpu");
5138 if (feature
== NULL
)
5141 tdesc_data
= tdesc_data_alloc ();
5144 for (i
= MIPS_ZERO_REGNUM
; i
<= MIPS_RA_REGNUM
; i
++)
5145 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
5149 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5150 MIPS_EMBED_LO_REGNUM
, "lo");
5151 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5152 MIPS_EMBED_HI_REGNUM
, "hi");
5153 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5154 MIPS_EMBED_PC_REGNUM
, "pc");
5158 tdesc_data_cleanup (tdesc_data
);
5162 feature
= tdesc_find_feature (info
.target_desc
,
5163 "org.gnu.gdb.mips.cp0");
5164 if (feature
== NULL
)
5166 tdesc_data_cleanup (tdesc_data
);
5171 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5172 MIPS_EMBED_BADVADDR_REGNUM
,
5174 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5175 MIPS_PS_REGNUM
, "status");
5176 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5177 MIPS_EMBED_CAUSE_REGNUM
, "cause");
5181 tdesc_data_cleanup (tdesc_data
);
5185 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
5186 backend is not prepared for that, though. */
5187 feature
= tdesc_find_feature (info
.target_desc
,
5188 "org.gnu.gdb.mips.fpu");
5189 if (feature
== NULL
)
5191 tdesc_data_cleanup (tdesc_data
);
5196 for (i
= 0; i
< 32; i
++)
5197 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5198 i
+ MIPS_EMBED_FP0_REGNUM
,
5201 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5202 MIPS_EMBED_FP0_REGNUM
+ 32, "fcsr");
5203 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5204 MIPS_EMBED_FP0_REGNUM
+ 33, "fir");
5208 tdesc_data_cleanup (tdesc_data
);
5212 /* It would be nice to detect an attempt to use a 64-bit ABI
5213 when only 32-bit registers are provided. */
5216 /* First of all, extract the elf_flags, if available. */
5217 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5218 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
5219 else if (arches
!= NULL
)
5220 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
5224 fprintf_unfiltered (gdb_stdlog
,
5225 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
5227 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5228 switch ((elf_flags
& EF_MIPS_ABI
))
5230 case E_MIPS_ABI_O32
:
5231 found_abi
= MIPS_ABI_O32
;
5233 case E_MIPS_ABI_O64
:
5234 found_abi
= MIPS_ABI_O64
;
5236 case E_MIPS_ABI_EABI32
:
5237 found_abi
= MIPS_ABI_EABI32
;
5239 case E_MIPS_ABI_EABI64
:
5240 found_abi
= MIPS_ABI_EABI64
;
5243 if ((elf_flags
& EF_MIPS_ABI2
))
5244 found_abi
= MIPS_ABI_N32
;
5246 found_abi
= MIPS_ABI_UNKNOWN
;
5250 /* GCC creates a pseudo-section whose name describes the ABI. */
5251 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
5252 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
5254 /* If we have no useful BFD information, use the ABI from the last
5255 MIPS architecture (if there is one). */
5256 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
5257 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
5259 /* Try the architecture for any hint of the correct ABI. */
5260 if (found_abi
== MIPS_ABI_UNKNOWN
5261 && info
.bfd_arch_info
!= NULL
5262 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5264 switch (info
.bfd_arch_info
->mach
)
5266 case bfd_mach_mips3900
:
5267 found_abi
= MIPS_ABI_EABI32
;
5269 case bfd_mach_mips4100
:
5270 case bfd_mach_mips5000
:
5271 found_abi
= MIPS_ABI_EABI64
;
5273 case bfd_mach_mips8000
:
5274 case bfd_mach_mips10000
:
5275 /* On Irix, ELF64 executables use the N64 ABI. The
5276 pseudo-sections which describe the ABI aren't present
5277 on IRIX. (Even for executables created by gcc.) */
5278 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5279 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5280 found_abi
= MIPS_ABI_N64
;
5282 found_abi
= MIPS_ABI_N32
;
5287 /* Default 64-bit objects to N64 instead of O32. */
5288 if (found_abi
== MIPS_ABI_UNKNOWN
5289 && info
.abfd
!= NULL
5290 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5291 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5292 found_abi
= MIPS_ABI_N64
;
5295 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
5298 /* What has the user specified from the command line? */
5299 wanted_abi
= global_mips_abi ();
5301 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
5304 /* Now that we have found what the ABI for this binary would be,
5305 check whether the user is overriding it. */
5306 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
5307 mips_abi
= wanted_abi
;
5308 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
5309 mips_abi
= found_abi
;
5311 mips_abi
= MIPS_ABI_O32
;
5313 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
5316 /* Also used when doing an architecture lookup. */
5318 fprintf_unfiltered (gdb_stdlog
,
5319 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
5320 mips64_transfers_32bit_regs_p
);
5322 /* Determine the MIPS FPU type. */
5325 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5326 elf_fpu_type
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
5327 Tag_GNU_MIPS_ABI_FP
);
5328 #endif /* HAVE_ELF */
5330 if (!mips_fpu_type_auto
)
5331 fpu_type
= mips_fpu_type
;
5332 else if (elf_fpu_type
!= 0)
5334 switch (elf_fpu_type
)
5337 fpu_type
= MIPS_FPU_DOUBLE
;
5340 fpu_type
= MIPS_FPU_SINGLE
;
5344 /* Soft float or unknown. */
5345 fpu_type
= MIPS_FPU_NONE
;
5349 else if (info
.bfd_arch_info
!= NULL
5350 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5351 switch (info
.bfd_arch_info
->mach
)
5353 case bfd_mach_mips3900
:
5354 case bfd_mach_mips4100
:
5355 case bfd_mach_mips4111
:
5356 case bfd_mach_mips4120
:
5357 fpu_type
= MIPS_FPU_NONE
;
5359 case bfd_mach_mips4650
:
5360 fpu_type
= MIPS_FPU_SINGLE
;
5363 fpu_type
= MIPS_FPU_DOUBLE
;
5366 else if (arches
!= NULL
)
5367 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
5369 fpu_type
= MIPS_FPU_DOUBLE
;
5371 fprintf_unfiltered (gdb_stdlog
,
5372 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
5374 /* Check for blatant incompatibilities. */
5376 /* If we have only 32-bit registers, then we can't debug a 64-bit
5378 if (info
.target_desc
5379 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
5380 && mips_abi
!= MIPS_ABI_EABI32
5381 && mips_abi
!= MIPS_ABI_O32
)
5383 if (tdesc_data
!= NULL
)
5384 tdesc_data_cleanup (tdesc_data
);
5388 /* try to find a pre-existing architecture */
5389 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
5391 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
5393 /* MIPS needs to be pedantic about which ABI the object is
5395 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
5397 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
5399 /* Need to be pedantic about which register virtual size is
5401 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
5402 != mips64_transfers_32bit_regs_p
)
5404 /* Be pedantic about which FPU is selected. */
5405 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
5408 if (tdesc_data
!= NULL
)
5409 tdesc_data_cleanup (tdesc_data
);
5410 return arches
->gdbarch
;
5413 /* Need a new architecture. Fill in a target specific vector. */
5414 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
5415 gdbarch
= gdbarch_alloc (&info
, tdep
);
5416 tdep
->elf_flags
= elf_flags
;
5417 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
5418 tdep
->found_abi
= found_abi
;
5419 tdep
->mips_abi
= mips_abi
;
5420 tdep
->mips_fpu_type
= fpu_type
;
5421 tdep
->register_size_valid_p
= 0;
5422 tdep
->register_size
= 0;
5424 if (info
.target_desc
)
5426 /* Some useful properties can be inferred from the target. */
5427 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
5429 tdep
->register_size_valid_p
= 1;
5430 tdep
->register_size
= 4;
5432 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
5434 tdep
->register_size_valid_p
= 1;
5435 tdep
->register_size
= 8;
5439 /* Initially set everything according to the default ABI/ISA. */
5440 set_gdbarch_short_bit (gdbarch
, 16);
5441 set_gdbarch_int_bit (gdbarch
, 32);
5442 set_gdbarch_float_bit (gdbarch
, 32);
5443 set_gdbarch_double_bit (gdbarch
, 64);
5444 set_gdbarch_long_double_bit (gdbarch
, 64);
5445 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
5446 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
5447 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
5449 set_gdbarch_elf_make_msymbol_special (gdbarch
,
5450 mips_elf_make_msymbol_special
);
5452 /* Fill in the OS dependant register numbers and names. */
5454 const char **reg_names
;
5455 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
5456 struct mips_regnum
);
5457 if (tdesc_has_registers (info
.target_desc
))
5459 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
5460 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
5461 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
5462 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
5463 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
5464 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
5465 regnum
->fp_control_status
= 70;
5466 regnum
->fp_implementation_revision
= 71;
5467 num_regs
= MIPS_LAST_EMBED_REGNUM
+ 1;
5470 else if (info
.osabi
== GDB_OSABI_IRIX
)
5475 regnum
->badvaddr
= 66;
5478 regnum
->fp_control_status
= 69;
5479 regnum
->fp_implementation_revision
= 70;
5481 reg_names
= mips_irix_reg_names
;
5485 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
5486 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
5487 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
5488 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
5489 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
5490 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
5491 regnum
->fp_control_status
= 70;
5492 regnum
->fp_implementation_revision
= 71;
5494 if (info
.bfd_arch_info
!= NULL
5495 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
5496 reg_names
= mips_tx39_reg_names
;
5498 reg_names
= mips_generic_reg_names
;
5500 /* FIXME: cagney/2003-11-15: For MIPS, hasn't gdbarch_pc_regnum been
5501 replaced by read_pc? */
5502 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
5503 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
5504 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
5505 set_gdbarch_num_regs (gdbarch
, num_regs
);
5506 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
5507 set_gdbarch_register_name (gdbarch
, mips_register_name
);
5508 set_gdbarch_virtual_frame_pointer (gdbarch
, mips_virtual_frame_pointer
);
5509 tdep
->mips_processor_reg_names
= reg_names
;
5510 tdep
->regnum
= regnum
;
5516 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
5517 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
5518 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
5519 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5520 tdep
->default_mask_address_p
= 0;
5521 set_gdbarch_long_bit (gdbarch
, 32);
5522 set_gdbarch_ptr_bit (gdbarch
, 32);
5523 set_gdbarch_long_long_bit (gdbarch
, 64);
5526 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
5527 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
5528 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
5529 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5530 tdep
->default_mask_address_p
= 0;
5531 set_gdbarch_long_bit (gdbarch
, 32);
5532 set_gdbarch_ptr_bit (gdbarch
, 32);
5533 set_gdbarch_long_long_bit (gdbarch
, 64);
5535 case MIPS_ABI_EABI32
:
5536 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5537 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
5538 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5539 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5540 tdep
->default_mask_address_p
= 0;
5541 set_gdbarch_long_bit (gdbarch
, 32);
5542 set_gdbarch_ptr_bit (gdbarch
, 32);
5543 set_gdbarch_long_long_bit (gdbarch
, 64);
5545 case MIPS_ABI_EABI64
:
5546 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5547 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
5548 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5549 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5550 tdep
->default_mask_address_p
= 0;
5551 set_gdbarch_long_bit (gdbarch
, 64);
5552 set_gdbarch_ptr_bit (gdbarch
, 64);
5553 set_gdbarch_long_long_bit (gdbarch
, 64);
5556 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5557 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5558 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5559 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5560 tdep
->default_mask_address_p
= 0;
5561 set_gdbarch_long_bit (gdbarch
, 32);
5562 set_gdbarch_ptr_bit (gdbarch
, 32);
5563 set_gdbarch_long_long_bit (gdbarch
, 64);
5564 set_gdbarch_long_double_bit (gdbarch
, 128);
5565 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
5568 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5569 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5570 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5571 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5572 tdep
->default_mask_address_p
= 0;
5573 set_gdbarch_long_bit (gdbarch
, 64);
5574 set_gdbarch_ptr_bit (gdbarch
, 64);
5575 set_gdbarch_long_long_bit (gdbarch
, 64);
5576 set_gdbarch_long_double_bit (gdbarch
, 128);
5577 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
5580 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
5583 /* GCC creates a pseudo-section whose name specifies the size of
5584 longs, since -mlong32 or -mlong64 may be used independent of
5585 other options. How those options affect pointer sizes is ABI and
5586 architecture dependent, so use them to override the default sizes
5587 set by the ABI. This table shows the relationship between ABI,
5588 -mlongXX, and size of pointers:
5590 ABI -mlongXX ptr bits
5591 --- -------- --------
5605 Note that for o32 and eabi32, pointers are always 32 bits
5606 regardless of any -mlongXX option. For all others, pointers and
5607 longs are the same, as set by -mlongXX or set by defaults.
5610 if (info
.abfd
!= NULL
)
5614 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
5617 set_gdbarch_long_bit (gdbarch
, long_bit
);
5621 case MIPS_ABI_EABI32
:
5626 case MIPS_ABI_EABI64
:
5627 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
5630 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
5635 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5636 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5639 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
5640 flag in object files because to do so would make it impossible to
5641 link with libraries compiled without "-gp32". This is
5642 unnecessarily restrictive.
5644 We could solve this problem by adding "-gp32" multilibs to gcc,
5645 but to set this flag before gcc is built with such multilibs will
5646 break too many systems.''
5648 But even more unhelpfully, the default linker output target for
5649 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
5650 for 64-bit programs - you need to change the ABI to change this,
5651 and not all gcc targets support that currently. Therefore using
5652 this flag to detect 32-bit mode would do the wrong thing given
5653 the current gcc - it would make GDB treat these 64-bit programs
5654 as 32-bit programs by default. */
5656 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
5657 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
5659 /* Add/remove bits from an address. The MIPS needs be careful to
5660 ensure that all 32 bit addresses are sign extended to 64 bits. */
5661 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
5663 /* Unwind the frame. */
5664 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
5665 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
5666 set_gdbarch_unwind_dummy_id (gdbarch
, mips_unwind_dummy_id
);
5668 /* Map debug register numbers onto internal register numbers. */
5669 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
5670 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
5671 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5672 set_gdbarch_dwarf_reg_to_regnum (gdbarch
,
5673 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5674 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
5675 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5676 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
5678 /* MIPS version of CALL_DUMMY */
5680 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
5681 replaced by a command, and all targets will default to on stack
5682 (regardless of the stack's execute status). */
5683 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
5684 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
5686 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
5687 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
5688 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
5690 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
5691 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
5693 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
5695 set_gdbarch_in_function_epilogue_p (gdbarch
, mips_in_function_epilogue_p
);
5697 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
5698 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
5699 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
5701 set_gdbarch_register_type (gdbarch
, mips_register_type
);
5703 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
5705 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
5707 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
5708 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
5709 need to all be folded into the target vector. Since they are
5710 being used as guards for STOPPED_BY_WATCHPOINT, why not have
5711 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
5713 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
5715 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
5717 set_gdbarch_single_step_through_delay (gdbarch
, mips_single_step_through_delay
);
5719 /* Virtual tables. */
5720 set_gdbarch_vbit_in_delta (gdbarch
, 1);
5722 mips_register_g_packet_guesses (gdbarch
);
5724 /* Hook in OS ABI-specific overrides, if they have been registered. */
5725 info
.tdep_info
= (void *) tdesc_data
;
5726 gdbarch_init_osabi (info
, gdbarch
);
5728 /* Unwind the frame. */
5729 frame_unwind_append_sniffer (gdbarch
, dwarf2_frame_sniffer
);
5730 frame_unwind_append_sniffer (gdbarch
, mips_stub_frame_sniffer
);
5731 frame_unwind_append_sniffer (gdbarch
, mips_insn16_frame_sniffer
);
5732 frame_unwind_append_sniffer (gdbarch
, mips_insn32_frame_sniffer
);
5733 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
5734 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
5735 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
5736 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
5740 set_tdesc_pseudo_register_type (gdbarch
, mips_pseudo_register_type
);
5741 tdesc_use_registers (gdbarch
, info
.target_desc
, tdesc_data
);
5743 /* Override the normal target description methods to handle our
5744 dual real and pseudo registers. */
5745 set_gdbarch_register_name (gdbarch
, mips_register_name
);
5746 set_gdbarch_register_reggroup_p (gdbarch
, mips_tdesc_register_reggroup_p
);
5748 num_regs
= gdbarch_num_regs (gdbarch
);
5749 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
5750 set_gdbarch_pc_regnum (gdbarch
, tdep
->regnum
->pc
+ num_regs
);
5751 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
5754 /* Add ABI-specific aliases for the registers. */
5755 if (mips_abi
== MIPS_ABI_N32
|| mips_abi
== MIPS_ABI_N64
)
5756 for (i
= 0; i
< ARRAY_SIZE (mips_n32_n64_aliases
); i
++)
5757 user_reg_add (gdbarch
, mips_n32_n64_aliases
[i
].name
,
5758 value_of_mips_user_reg
, &mips_n32_n64_aliases
[i
].regnum
);
5760 for (i
= 0; i
< ARRAY_SIZE (mips_o32_aliases
); i
++)
5761 user_reg_add (gdbarch
, mips_o32_aliases
[i
].name
,
5762 value_of_mips_user_reg
, &mips_o32_aliases
[i
].regnum
);
5764 /* Add some other standard aliases. */
5765 for (i
= 0; i
< ARRAY_SIZE (mips_register_aliases
); i
++)
5766 user_reg_add (gdbarch
, mips_register_aliases
[i
].name
,
5767 value_of_mips_user_reg
, &mips_register_aliases
[i
].regnum
);
5773 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
5775 struct gdbarch_info info
;
5777 /* Force the architecture to update, and (if it's a MIPS architecture)
5778 mips_gdbarch_init will take care of the rest. */
5779 gdbarch_info_init (&info
);
5780 gdbarch_update_p (info
);
5783 /* Print out which MIPS ABI is in use. */
5786 show_mips_abi (struct ui_file
*file
,
5788 struct cmd_list_element
*ignored_cmd
,
5789 const char *ignored_value
)
5791 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_mips
)
5794 "The MIPS ABI is unknown because the current architecture "
5798 enum mips_abi global_abi
= global_mips_abi ();
5799 enum mips_abi actual_abi
= mips_abi (current_gdbarch
);
5800 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
5802 if (global_abi
== MIPS_ABI_UNKNOWN
)
5805 "The MIPS ABI is set automatically (currently \"%s\").\n",
5807 else if (global_abi
== actual_abi
)
5810 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
5814 /* Probably shouldn't happen... */
5817 "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
5818 actual_abi_str
, mips_abi_strings
[global_abi
]);
5824 mips_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
5826 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5830 int ef_mips_32bitmode
;
5831 /* Determine the ISA. */
5832 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
5850 /* Determine the size of a pointer. */
5851 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
5852 fprintf_unfiltered (file
,
5853 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
5855 fprintf_unfiltered (file
,
5856 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
5858 fprintf_unfiltered (file
,
5859 "mips_dump_tdep: ef_mips_arch = %d\n",
5861 fprintf_unfiltered (file
,
5862 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
5863 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
5864 fprintf_unfiltered (file
,
5865 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
5866 mips_mask_address_p (tdep
),
5867 tdep
->default_mask_address_p
);
5869 fprintf_unfiltered (file
,
5870 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
5871 MIPS_DEFAULT_FPU_TYPE
,
5872 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
5873 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
5874 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
5876 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI
);
5877 fprintf_unfiltered (file
,
5878 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
5880 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
5881 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
5882 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
5886 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
5889 _initialize_mips_tdep (void)
5891 static struct cmd_list_element
*mipsfpulist
= NULL
;
5892 struct cmd_list_element
*c
;
5894 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
5895 if (MIPS_ABI_LAST
+ 1
5896 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
5897 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
5899 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
5901 mips_pdr_data
= register_objfile_data ();
5903 /* Create feature sets with the appropriate properties. The values
5904 are not important. */
5905 mips_tdesc_gp32
= allocate_target_description ();
5906 set_tdesc_property (mips_tdesc_gp32
, PROPERTY_GP32
, "");
5908 mips_tdesc_gp64
= allocate_target_description ();
5909 set_tdesc_property (mips_tdesc_gp64
, PROPERTY_GP64
, "");
5911 /* Add root prefix command for all "set mips"/"show mips" commands */
5912 add_prefix_cmd ("mips", no_class
, set_mips_command
,
5913 _("Various MIPS specific commands."),
5914 &setmipscmdlist
, "set mips ", 0, &setlist
);
5916 add_prefix_cmd ("mips", no_class
, show_mips_command
,
5917 _("Various MIPS specific commands."),
5918 &showmipscmdlist
, "show mips ", 0, &showlist
);
5920 /* Allow the user to override the ABI. */
5921 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
5922 &mips_abi_string
, _("\
5923 Set the MIPS ABI used by this program."), _("\
5924 Show the MIPS ABI used by this program."), _("\
5925 This option can be set to one of:\n\
5926 auto - the default ABI associated with the current binary\n\
5935 &setmipscmdlist
, &showmipscmdlist
);
5937 /* Let the user turn off floating point and set the fence post for
5938 heuristic_proc_start. */
5940 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
5941 _("Set use of MIPS floating-point coprocessor."),
5942 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
5943 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
5944 _("Select single-precision MIPS floating-point coprocessor."),
5946 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
5947 _("Select double-precision MIPS floating-point coprocessor."),
5949 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
5950 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
5951 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
5952 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
5953 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
5954 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
5955 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
5956 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
5957 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
5958 _("Select MIPS floating-point coprocessor automatically."),
5960 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
5961 _("Show current use of MIPS floating-point coprocessor target."),
5964 /* We really would like to have both "0" and "unlimited" work, but
5965 command.c doesn't deal with that. So make it a var_zinteger
5966 because the user can always use "999999" or some such for unlimited. */
5967 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
5968 &heuristic_fence_post
, _("\
5969 Set the distance searched for the start of a function."), _("\
5970 Show the distance searched for the start of a function."), _("\
5971 If you are debugging a stripped executable, GDB needs to search through the\n\
5972 program for the start of a function. This command sets the distance of the\n\
5973 search. The only need to set it is when debugging a stripped executable."),
5974 reinit_frame_cache_sfunc
,
5975 NULL
, /* FIXME: i18n: The distance searched for the start of a function is %s. */
5976 &setlist
, &showlist
);
5978 /* Allow the user to control whether the upper bits of 64-bit
5979 addresses should be zeroed. */
5980 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
5981 &mask_address_var
, _("\
5982 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
5983 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
5984 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
5985 allow GDB to determine the correct value."),
5986 NULL
, show_mask_address
,
5987 &setmipscmdlist
, &showmipscmdlist
);
5989 /* Allow the user to control the size of 32 bit registers within the
5990 raw remote packet. */
5991 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
5992 &mips64_transfers_32bit_regs_p
, _("\
5993 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
5995 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
5997 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
5998 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
5999 64 bits for others. Use \"off\" to disable compatibility mode"),
6000 set_mips64_transfers_32bit_regs
,
6001 NULL
, /* FIXME: i18n: Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s. */
6002 &setlist
, &showlist
);
6004 /* Debug this files internals. */
6005 add_setshow_zinteger_cmd ("mips", class_maintenance
,
6007 Set mips debugging."), _("\
6008 Show mips debugging."), _("\
6009 When non-zero, mips specific debugging is enabled."),
6011 NULL
, /* FIXME: i18n: Mips debugging is currently %s. */
6012 &setdebuglist
, &showdebuglist
);