1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software
24 Foundation, Inc., 59 Temple Place - Suite 330,
25 Boston, MA 02111-1307, USA. */
28 #include "gdb_string.h"
29 #include "gdb_assert.h"
41 #include "arch-utils.h"
44 #include "mips-tdep.h"
46 #include "reggroups.h"
47 #include "opcode/mips.h"
51 #include "sim-regno.h"
53 #include "frame-unwind.h"
54 #include "frame-base.h"
55 #include "trad-frame.h"
57 #include "floatformat.h"
59 static const struct objfile_data
*mips_pdr_data
;
61 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
63 /* A useful bit in the CP0 status register (PS_REGNUM). */
64 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
65 #define ST0_FR (1 << 26)
67 /* The sizes of floating point registers. */
71 MIPS_FPU_SINGLE_REGSIZE
= 4,
72 MIPS_FPU_DOUBLE_REGSIZE
= 8
76 static const char *mips_abi_string
;
78 static const char *mips_abi_strings
[] = {
89 struct frame_extra_info
91 mips_extra_func_info_t proc_desc
;
95 /* Various MIPS ISA options (related to stack analysis) can be
96 overridden dynamically. Establish an enum/array for managing
99 static const char size_auto
[] = "auto";
100 static const char size_32
[] = "32";
101 static const char size_64
[] = "64";
103 static const char *size_enums
[] = {
110 /* Some MIPS boards don't support floating point while others only
111 support single-precision floating-point operations. */
115 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
116 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
117 MIPS_FPU_NONE
/* No floating point. */
120 #ifndef MIPS_DEFAULT_FPU_TYPE
121 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
123 static int mips_fpu_type_auto
= 1;
124 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
126 static int mips_debug
= 0;
128 /* MIPS specific per-architecture information */
131 /* from the elf header */
135 enum mips_abi mips_abi
;
136 enum mips_abi found_abi
;
137 enum mips_fpu_type mips_fpu_type
;
138 int mips_last_arg_regnum
;
139 int mips_last_fp_arg_regnum
;
140 int default_mask_address_p
;
141 /* Is the target using 64-bit raw integer registers but only
142 storing a left-aligned 32-bit value in each? */
143 int mips64_transfers_32bit_regs_p
;
144 /* Indexes for various registers. IRIX and embedded have
145 different values. This contains the "public" fields. Don't
146 add any that do not need to be public. */
147 const struct mips_regnum
*regnum
;
148 /* Register names table for the current register set. */
149 const char **mips_processor_reg_names
;
153 n32n64_floatformat_always_valid (const struct floatformat
*fmt
,
159 /* FIXME: brobecker/2004-08-08: Long Double values are 128 bit long.
160 They are implemented as a pair of 64bit doubles where the high
161 part holds the result of the operation rounded to double, and
162 the low double holds the difference between the exact result and
163 the rounded result. So "high" + "low" contains the result with
164 added precision. Unfortunately, the floatformat structure used
165 by GDB is not powerful enough to describe this format. As a temporary
166 measure, we define a 128bit floatformat that only uses the high part.
167 We lose a bit of precision but that's probably the best we can do
168 for now with the current infrastructure. */
170 static const struct floatformat floatformat_n32n64_long_double_big
=
172 floatformat_big
, 128, 0, 1, 11, 1023, 2047, 12, 52,
173 floatformat_intbit_no
,
174 "floatformat_ieee_double_big",
175 n32n64_floatformat_always_valid
178 const struct mips_regnum
*
179 mips_regnum (struct gdbarch
*gdbarch
)
181 return gdbarch_tdep (gdbarch
)->regnum
;
185 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
187 return mips_regnum (gdbarch
)->fp0
+ 12;
190 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
191 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
193 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
195 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
197 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
199 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
200 functions to test, set, or clear bit 0 of addresses. */
203 is_mips16_addr (CORE_ADDR addr
)
209 make_mips16_addr (CORE_ADDR addr
)
215 unmake_mips16_addr (CORE_ADDR addr
)
217 return ((addr
) & ~1);
220 /* Return the contents of register REGNUM as a signed integer. */
223 read_signed_register (int regnum
)
226 regcache_cooked_read_signed (current_regcache
, regnum
, &val
);
231 read_signed_register_pid (int regnum
, ptid_t ptid
)
236 if (ptid_equal (ptid
, inferior_ptid
))
237 return read_signed_register (regnum
);
239 save_ptid
= inferior_ptid
;
241 inferior_ptid
= ptid
;
243 retval
= read_signed_register (regnum
);
245 inferior_ptid
= save_ptid
;
250 /* Return the MIPS ABI associated with GDBARCH. */
252 mips_abi (struct gdbarch
*gdbarch
)
254 return gdbarch_tdep (gdbarch
)->mips_abi
;
258 mips_isa_regsize (struct gdbarch
*gdbarch
)
260 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
261 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
264 /* Return the currently configured (or set) saved register size. */
266 static const char *mips_abi_regsize_string
= size_auto
;
269 mips_abi_regsize (struct gdbarch
*gdbarch
)
271 if (mips_abi_regsize_string
== size_auto
)
272 switch (mips_abi (gdbarch
))
274 case MIPS_ABI_EABI32
:
280 case MIPS_ABI_EABI64
:
282 case MIPS_ABI_UNKNOWN
:
285 internal_error (__FILE__
, __LINE__
, "bad switch");
287 else if (mips_abi_regsize_string
== size_64
)
289 else /* if (mips_abi_regsize_string == size_32) */
293 /* Functions for setting and testing a bit in a minimal symbol that
294 marks it as 16-bit function. The MSB of the minimal symbol's
295 "info" field is used for this purpose.
297 ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special",
298 i.e. refers to a 16-bit function, and sets a "special" bit in a
299 minimal symbol to mark it as a 16-bit function
301 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
304 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
306 if (((elf_symbol_type
*) (sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
308 MSYMBOL_INFO (msym
) = (char *)
309 (((long) MSYMBOL_INFO (msym
)) | 0x80000000);
310 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
315 msymbol_is_special (struct minimal_symbol
*msym
)
317 return (((long) MSYMBOL_INFO (msym
) & 0x80000000) != 0);
320 /* XFER a value from the big/little/left end of the register.
321 Depending on the size of the value it might occupy the entire
322 register or just part of it. Make an allowance for this, aligning
323 things accordingly. */
326 mips_xfer_register (struct regcache
*regcache
, int reg_num
, int length
,
327 enum bfd_endian endian
, bfd_byte
* in
,
328 const bfd_byte
* out
, int buf_offset
)
331 gdb_assert (reg_num
>= NUM_REGS
);
332 /* Need to transfer the left or right part of the register, based on
333 the targets byte order. */
337 reg_offset
= register_size (current_gdbarch
, reg_num
) - length
;
339 case BFD_ENDIAN_LITTLE
:
342 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
346 internal_error (__FILE__
, __LINE__
, "bad switch");
349 fprintf_unfiltered (gdb_stderr
,
350 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
351 reg_num
, reg_offset
, buf_offset
, length
);
352 if (mips_debug
&& out
!= NULL
)
355 fprintf_unfiltered (gdb_stdlog
, "out ");
356 for (i
= 0; i
< length
; i
++)
357 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
360 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
363 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
365 if (mips_debug
&& in
!= NULL
)
368 fprintf_unfiltered (gdb_stdlog
, "in ");
369 for (i
= 0; i
< length
; i
++)
370 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
373 fprintf_unfiltered (gdb_stdlog
, "\n");
376 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
377 compatiblity mode. A return value of 1 means that we have
378 physical 64-bit registers, but should treat them as 32-bit registers. */
381 mips2_fp_compat (void)
383 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
385 if (register_size (current_gdbarch
, mips_regnum (current_gdbarch
)->fp0
) ==
390 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
391 in all the places we deal with FP registers. PR gdb/413. */
392 /* Otherwise check the FR bit in the status register - it controls
393 the FP compatiblity mode. If it is clear we are in compatibility
395 if ((read_register (PS_REGNUM
) & ST0_FR
) == 0)
402 /* The amount of space reserved on the stack for registers. This is
403 different to MIPS_ABI_REGSIZE as it determines the alignment of
404 data allocated after the registers have run out. */
406 static const char *mips_stack_argsize_string
= size_auto
;
409 mips_stack_argsize (struct gdbarch
*gdbarch
)
411 if (mips_stack_argsize_string
== size_auto
)
412 return mips_abi_regsize (gdbarch
);
413 else if (mips_stack_argsize_string
== size_64
)
415 else /* if (mips_stack_argsize_string == size_32) */
419 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
421 struct mips_frame_cache
;
422 static mips_extra_func_info_t
non_heuristic_proc_desc (CORE_ADDR pc
,
425 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
427 static CORE_ADDR
read_next_frame_reg (struct frame_info
*, int);
429 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
431 static struct type
*mips_float_register_type (void);
432 static struct type
*mips_double_register_type (void);
434 /* The list of available "set mips " and "show mips " commands */
436 static struct cmd_list_element
*setmipscmdlist
= NULL
;
437 static struct cmd_list_element
*showmipscmdlist
= NULL
;
439 /* Integer registers 0 thru 31 are handled explicitly by
440 mips_register_name(). Processor specific registers 32 and above
441 are listed in the followign tables. */
444 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
448 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
449 "sr", "lo", "hi", "bad", "cause", "pc",
450 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
451 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
452 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
453 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
454 "fsr", "fir", "" /*"fp" */ , "",
455 "", "", "", "", "", "", "", "",
456 "", "", "", "", "", "", "", "",
459 /* Names of IDT R3041 registers. */
461 static const char *mips_r3041_reg_names
[] = {
462 "sr", "lo", "hi", "bad", "cause", "pc",
463 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
464 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
465 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
466 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
467 "fsr", "fir", "", /*"fp" */ "",
468 "", "", "bus", "ccfg", "", "", "", "",
469 "", "", "port", "cmp", "", "", "epc", "prid",
472 /* Names of tx39 registers. */
474 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
475 "sr", "lo", "hi", "bad", "cause", "pc",
476 "", "", "", "", "", "", "", "",
477 "", "", "", "", "", "", "", "",
478 "", "", "", "", "", "", "", "",
479 "", "", "", "", "", "", "", "",
481 "", "", "", "", "", "", "", "",
482 "", "", "config", "cache", "debug", "depc", "epc", ""
485 /* Names of IRIX registers. */
486 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
487 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
488 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
489 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
490 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
491 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
495 /* Return the name of the register corresponding to REGNO. */
497 mips_register_name (int regno
)
499 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
500 /* GPR names for all ABIs other than n32/n64. */
501 static char *mips_gpr_names
[] = {
502 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
503 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
504 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
505 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
508 /* GPR names for n32 and n64 ABIs. */
509 static char *mips_n32_n64_gpr_names
[] = {
510 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
511 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
512 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
513 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
516 enum mips_abi abi
= mips_abi (current_gdbarch
);
518 /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then
519 don't make the raw register names visible. */
520 int rawnum
= regno
% NUM_REGS
;
521 if (regno
< NUM_REGS
)
524 /* The MIPS integer registers are always mapped from 0 to 31. The
525 names of the registers (which reflects the conventions regarding
526 register use) vary depending on the ABI. */
527 if (0 <= rawnum
&& rawnum
< 32)
529 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
530 return mips_n32_n64_gpr_names
[rawnum
];
532 return mips_gpr_names
[rawnum
];
534 else if (32 <= rawnum
&& rawnum
< NUM_REGS
)
536 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
537 return tdep
->mips_processor_reg_names
[rawnum
- 32];
540 internal_error (__FILE__
, __LINE__
,
541 "mips_register_name: bad register number %d", rawnum
);
544 /* Return the groups that a MIPS register can be categorised into. */
547 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
548 struct reggroup
*reggroup
)
553 int rawnum
= regnum
% NUM_REGS
;
554 int pseudo
= regnum
/ NUM_REGS
;
555 if (reggroup
== all_reggroup
)
557 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
558 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
559 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
560 (gdbarch), as not all architectures are multi-arch. */
561 raw_p
= rawnum
< NUM_REGS
;
562 if (REGISTER_NAME (regnum
) == NULL
|| REGISTER_NAME (regnum
)[0] == '\0')
564 if (reggroup
== float_reggroup
)
565 return float_p
&& pseudo
;
566 if (reggroup
== vector_reggroup
)
567 return vector_p
&& pseudo
;
568 if (reggroup
== general_reggroup
)
569 return (!vector_p
&& !float_p
) && pseudo
;
570 /* Save the pseudo registers. Need to make certain that any code
571 extracting register values from a saved register cache also uses
573 if (reggroup
== save_reggroup
)
574 return raw_p
&& pseudo
;
575 /* Restore the same pseudo register. */
576 if (reggroup
== restore_reggroup
)
577 return raw_p
&& pseudo
;
581 /* Map the symbol table registers which live in the range [1 *
582 NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw
583 registers. Take care of alignment and size problems. */
586 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
587 int cookednum
, void *buf
)
589 int rawnum
= cookednum
% NUM_REGS
;
590 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
591 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
592 regcache_raw_read (regcache
, rawnum
, buf
);
593 else if (register_size (gdbarch
, rawnum
) >
594 register_size (gdbarch
, cookednum
))
596 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
597 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
598 regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
600 regcache_raw_read_part (regcache
, rawnum
, 4, 4, buf
);
603 internal_error (__FILE__
, __LINE__
, "bad register size");
607 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
608 struct regcache
*regcache
, int cookednum
,
611 int rawnum
= cookednum
% NUM_REGS
;
612 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
613 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
614 regcache_raw_write (regcache
, rawnum
, buf
);
615 else if (register_size (gdbarch
, rawnum
) >
616 register_size (gdbarch
, cookednum
))
618 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
619 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
620 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
622 regcache_raw_write_part (regcache
, rawnum
, 4, 4, buf
);
625 internal_error (__FILE__
, __LINE__
, "bad register size");
628 /* Table to translate MIPS16 register field to actual register number. */
629 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
631 /* Heuristic_proc_start may hunt through the text section for a long
632 time across a 2400 baud serial line. Allows the user to limit this
635 static unsigned int heuristic_fence_post
= 0;
637 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
638 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
639 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
640 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
641 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
642 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
643 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
644 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
645 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
646 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
647 /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long,
648 this will corrupt pdr.iline. Fortunately we don't use it. */
649 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
650 #define _PROC_MAGIC_ 0x0F0F0F0F
652 /* Number of bytes of storage in the actual machine representation for
653 register N. NOTE: This defines the pseudo register type so need to
654 rebuild the architecture vector. */
656 static int mips64_transfers_32bit_regs_p
= 0;
659 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
660 struct cmd_list_element
*c
)
662 struct gdbarch_info info
;
663 gdbarch_info_init (&info
);
664 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
665 instead of relying on globals. Doing that would let generic code
666 handle the search for this specific architecture. */
667 if (!gdbarch_update_p (info
))
669 mips64_transfers_32bit_regs_p
= 0;
670 error ("32-bit compatibility mode not supported");
674 /* Convert to/from a register and the corresponding memory value. */
677 mips_convert_register_p (int regnum
, struct type
*type
)
679 return (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
680 && register_size (current_gdbarch
, regnum
) == 4
681 && (regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
682 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32
683 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
687 mips_register_to_value (struct frame_info
*frame
, int regnum
,
688 struct type
*type
, void *to
)
690 get_frame_register (frame
, regnum
+ 0, (char *) to
+ 4);
691 get_frame_register (frame
, regnum
+ 1, (char *) to
+ 0);
695 mips_value_to_register (struct frame_info
*frame
, int regnum
,
696 struct type
*type
, const void *from
)
698 put_frame_register (frame
, regnum
+ 0, (const char *) from
+ 4);
699 put_frame_register (frame
, regnum
+ 1, (const char *) from
+ 0);
702 /* Return the GDB type object for the "standard" data type of data in
706 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
708 gdb_assert (regnum
>= 0 && regnum
< 2 * NUM_REGS
);
709 if ((regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
710 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32)
712 /* The floating-point registers raw, or cooked, always match
713 mips_isa_regsize(), and also map 1:1, byte for byte. */
714 switch (gdbarch_byte_order (gdbarch
))
717 if (mips_isa_regsize (gdbarch
) == 4)
718 return builtin_type_ieee_single_big
;
720 return builtin_type_ieee_double_big
;
721 case BFD_ENDIAN_LITTLE
:
722 if (mips_isa_regsize (gdbarch
) == 4)
723 return builtin_type_ieee_single_little
;
725 return builtin_type_ieee_double_little
;
726 case BFD_ENDIAN_UNKNOWN
:
728 internal_error (__FILE__
, __LINE__
, "bad switch");
731 else if (regnum
< NUM_REGS
)
733 /* The raw or ISA registers. These are all sized according to
735 if (mips_isa_regsize (gdbarch
) == 4)
736 return builtin_type_int32
;
738 return builtin_type_int64
;
742 /* The cooked or ABI registers. These are sized according to
743 the ABI (with a few complications). */
744 if (regnum
>= (NUM_REGS
745 + mips_regnum (current_gdbarch
)->fp_control_status
)
746 && regnum
<= NUM_REGS
+ LAST_EMBED_REGNUM
)
747 /* The pseudo/cooked view of the embedded registers is always
748 32-bit. The raw view is handled below. */
749 return builtin_type_int32
;
750 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
751 /* The target, while possibly using a 64-bit register buffer,
752 is only transfering 32-bits of each integer register.
753 Reflect this in the cooked/pseudo (ABI) register value. */
754 return builtin_type_int32
;
755 else if (mips_abi_regsize (gdbarch
) == 4)
756 /* The ABI is restricted to 32-bit registers (the ISA could be
758 return builtin_type_int32
;
761 return builtin_type_int64
;
765 /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */
770 return read_signed_register (MIPS_SP_REGNUM
);
773 /* Should the upper word of 64-bit addresses be zeroed? */
774 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
777 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
779 switch (mask_address_var
)
781 case AUTO_BOOLEAN_TRUE
:
783 case AUTO_BOOLEAN_FALSE
:
786 case AUTO_BOOLEAN_AUTO
:
787 return tdep
->default_mask_address_p
;
789 internal_error (__FILE__
, __LINE__
, "mips_mask_address_p: bad switch");
795 show_mask_address (char *cmd
, int from_tty
, struct cmd_list_element
*c
)
797 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
798 switch (mask_address_var
)
800 case AUTO_BOOLEAN_TRUE
:
801 printf_filtered ("The 32 bit mips address mask is enabled\n");
803 case AUTO_BOOLEAN_FALSE
:
804 printf_filtered ("The 32 bit mips address mask is disabled\n");
806 case AUTO_BOOLEAN_AUTO
:
808 ("The 32 bit address mask is set automatically. Currently %s\n",
809 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
812 internal_error (__FILE__
, __LINE__
, "show_mask_address: bad switch");
817 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
820 mips_pc_is_mips16 (CORE_ADDR memaddr
)
822 struct minimal_symbol
*sym
;
824 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
825 if (is_mips16_addr (memaddr
))
828 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
829 the high bit of the info field. Use this to decide if the function is
830 MIPS16 or normal MIPS. */
831 sym
= lookup_minimal_symbol_by_pc (memaddr
);
833 return msymbol_is_special (sym
);
838 /* MIPS believes that the PC has a sign extended value. Perhaps the
839 all registers should be sign extended for simplicity? */
842 mips_read_pc (ptid_t ptid
)
844 return read_signed_register_pid (mips_regnum (current_gdbarch
)->pc
, ptid
);
848 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
850 return frame_unwind_register_signed (next_frame
,
851 NUM_REGS
+ mips_regnum (gdbarch
)->pc
);
854 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
855 dummy frame. The frame ID's base needs to match the TOS value
856 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
859 static struct frame_id
860 mips_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
862 return frame_id_build (frame_unwind_register_signed (next_frame
, NUM_REGS
+ MIPS_SP_REGNUM
),
863 frame_pc_unwind (next_frame
));
867 mips_write_pc (CORE_ADDR pc
, ptid_t ptid
)
869 write_register_pid (mips_regnum (current_gdbarch
)->pc
, pc
, ptid
);
872 /* Fetch and return instruction from the specified location. If the PC
873 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
876 mips_fetch_instruction (CORE_ADDR addr
)
878 char buf
[MIPS32_INSN_SIZE
];
882 if (mips_pc_is_mips16 (addr
))
884 instlen
= MIPS16_INSN_SIZE
;
885 addr
= unmake_mips16_addr (addr
);
888 instlen
= MIPS32_INSN_SIZE
;
889 status
= deprecated_read_memory_nobpt (addr
, buf
, instlen
);
891 memory_error (status
, addr
);
892 return extract_unsigned_integer (buf
, instlen
);
896 mips16_fetch_instruction (CORE_ADDR addr
)
898 char buf
[MIPS16_INSN_SIZE
];
901 addr
= unmake_mips16_addr (addr
);
902 status
= deprecated_read_memory_nobpt (addr
, buf
, sizeof (buf
));
904 memory_error (status
, addr
);
905 return extract_unsigned_integer (buf
, sizeof (buf
));
908 /* These the fields of 32 bit mips instructions */
909 #define mips32_op(x) (x >> 26)
910 #define itype_op(x) (x >> 26)
911 #define itype_rs(x) ((x >> 21) & 0x1f)
912 #define itype_rt(x) ((x >> 16) & 0x1f)
913 #define itype_immediate(x) (x & 0xffff)
915 #define jtype_op(x) (x >> 26)
916 #define jtype_target(x) (x & 0x03ffffff)
918 #define rtype_op(x) (x >> 26)
919 #define rtype_rs(x) ((x >> 21) & 0x1f)
920 #define rtype_rt(x) ((x >> 16) & 0x1f)
921 #define rtype_rd(x) ((x >> 11) & 0x1f)
922 #define rtype_shamt(x) ((x >> 6) & 0x1f)
923 #define rtype_funct(x) (x & 0x3f)
926 mips32_relative_offset (unsigned long inst
)
929 x
= itype_immediate (inst
);
930 if (x
& 0x8000) /* sign bit set */
932 x
|= 0xffff0000; /* sign extension */
938 /* Determine whate to set a single step breakpoint while considering
941 mips32_next_pc (CORE_ADDR pc
)
945 inst
= mips_fetch_instruction (pc
);
946 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
948 if (itype_op (inst
) >> 2 == 5)
949 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
951 op
= (itype_op (inst
) & 0x03);
966 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
967 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
969 int tf
= itype_rt (inst
) & 0x01;
970 int cnum
= itype_rt (inst
) >> 2;
972 read_signed_register (mips_regnum (current_gdbarch
)->
974 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
976 if (((cond
>> cnum
) & 0x01) == tf
)
977 pc
+= mips32_relative_offset (inst
) + 4;
982 pc
+= 4; /* Not a branch, next instruction is easy */
985 { /* This gets way messy */
987 /* Further subdivide into SPECIAL, REGIMM and other */
988 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
990 case 0: /* SPECIAL */
991 op
= rtype_funct (inst
);
996 /* Set PC to that address */
997 pc
= read_signed_register (rtype_rs (inst
));
1003 break; /* end SPECIAL */
1004 case 1: /* REGIMM */
1006 op
= itype_rt (inst
); /* branch condition */
1011 case 16: /* BLTZAL */
1012 case 18: /* BLTZALL */
1014 if (read_signed_register (itype_rs (inst
)) < 0)
1015 pc
+= mips32_relative_offset (inst
) + 4;
1017 pc
+= 8; /* after the delay slot */
1021 case 17: /* BGEZAL */
1022 case 19: /* BGEZALL */
1023 if (read_signed_register (itype_rs (inst
)) >= 0)
1024 pc
+= mips32_relative_offset (inst
) + 4;
1026 pc
+= 8; /* after the delay slot */
1028 /* All of the other instructions in the REGIMM category */
1033 break; /* end REGIMM */
1038 reg
= jtype_target (inst
) << 2;
1039 /* Upper four bits get never changed... */
1040 pc
= reg
+ ((pc
+ 4) & 0xf0000000);
1043 /* FIXME case JALX : */
1046 reg
= jtype_target (inst
) << 2;
1047 pc
= reg
+ ((pc
+ 4) & 0xf0000000) + 1; /* yes, +1 */
1048 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1050 break; /* The new PC will be alternate mode */
1051 case 4: /* BEQ, BEQL */
1053 if (read_signed_register (itype_rs (inst
)) ==
1054 read_signed_register (itype_rt (inst
)))
1055 pc
+= mips32_relative_offset (inst
) + 4;
1059 case 5: /* BNE, BNEL */
1061 if (read_signed_register (itype_rs (inst
)) !=
1062 read_signed_register (itype_rt (inst
)))
1063 pc
+= mips32_relative_offset (inst
) + 4;
1067 case 6: /* BLEZ, BLEZL */
1068 if (read_signed_register (itype_rs (inst
)) <= 0)
1069 pc
+= mips32_relative_offset (inst
) + 4;
1075 greater_branch
: /* BGTZ, BGTZL */
1076 if (read_signed_register (itype_rs (inst
)) > 0)
1077 pc
+= mips32_relative_offset (inst
) + 4;
1084 } /* mips32_next_pc */
1086 /* Decoding the next place to set a breakpoint is irregular for the
1087 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1088 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1089 We dont want to set a single step instruction on the extend instruction
1093 /* Lots of mips16 instruction formats */
1094 /* Predicting jumps requires itype,ritype,i8type
1095 and their extensions extItype,extritype,extI8type
1097 enum mips16_inst_fmts
1099 itype
, /* 0 immediate 5,10 */
1100 ritype
, /* 1 5,3,8 */
1101 rrtype
, /* 2 5,3,3,5 */
1102 rritype
, /* 3 5,3,3,5 */
1103 rrrtype
, /* 4 5,3,3,3,2 */
1104 rriatype
, /* 5 5,3,3,1,4 */
1105 shifttype
, /* 6 5,3,3,3,2 */
1106 i8type
, /* 7 5,3,8 */
1107 i8movtype
, /* 8 5,3,3,5 */
1108 i8mov32rtype
, /* 9 5,3,5,3 */
1109 i64type
, /* 10 5,3,8 */
1110 ri64type
, /* 11 5,3,3,5 */
1111 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1112 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1113 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1114 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1115 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1116 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1117 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1118 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1119 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1120 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1122 /* I am heaping all the fields of the formats into one structure and
1123 then, only the fields which are involved in instruction extension */
1127 unsigned int regx
; /* Function in i8 type */
1132 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1133 for the bits which make up the immediatate extension. */
1136 extended_offset (unsigned int extension
)
1139 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1141 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1143 value
|= extension
& 0x01f; /* extract 4:0 */
1147 /* Only call this function if you know that this is an extendable
1148 instruction, It wont malfunction, but why make excess remote memory references?
1149 If the immediate operands get sign extended or somthing, do it after
1150 the extension is performed.
1152 /* FIXME: Every one of these cases needs to worry about sign extension
1153 when the offset is to be used in relative addressing */
1157 fetch_mips_16 (CORE_ADDR pc
)
1160 pc
&= 0xfffffffe; /* clear the low order bit */
1161 target_read_memory (pc
, buf
, 2);
1162 return extract_unsigned_integer (buf
, 2);
1166 unpack_mips16 (CORE_ADDR pc
,
1167 unsigned int extension
,
1169 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1174 switch (insn_format
)
1181 value
= extended_offset (extension
);
1182 value
= value
<< 11; /* rom for the original value */
1183 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1187 value
= inst
& 0x7ff;
1188 /* FIXME : Consider sign extension */
1197 { /* A register identifier and an offset */
1198 /* Most of the fields are the same as I type but the
1199 immediate value is of a different length */
1203 value
= extended_offset (extension
);
1204 value
= value
<< 8; /* from the original instruction */
1205 value
|= inst
& 0xff; /* eleven bits from instruction */
1206 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1207 if (value
& 0x4000) /* test the sign bit , bit 26 */
1209 value
&= ~0x3fff; /* remove the sign bit */
1215 value
= inst
& 0xff; /* 8 bits */
1216 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1217 /* FIXME: Do sign extension , this format needs it */
1218 if (value
& 0x80) /* THIS CONFUSES ME */
1220 value
&= 0xef; /* remove the sign bit */
1230 unsigned long value
;
1231 unsigned int nexthalf
;
1232 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1233 value
= value
<< 16;
1234 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1242 internal_error (__FILE__
, __LINE__
, "bad switch");
1244 upk
->offset
= offset
;
1251 add_offset_16 (CORE_ADDR pc
, int offset
)
1253 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000)));
1257 extended_mips16_next_pc (CORE_ADDR pc
,
1258 unsigned int extension
, unsigned int insn
)
1260 int op
= (insn
>> 11);
1263 case 2: /* Branch */
1266 struct upk_mips16 upk
;
1267 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1268 offset
= upk
.offset
;
1274 pc
+= (offset
<< 1) + 2;
1277 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1279 struct upk_mips16 upk
;
1280 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1281 pc
= add_offset_16 (pc
, upk
.offset
);
1282 if ((insn
>> 10) & 0x01) /* Exchange mode */
1283 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1290 struct upk_mips16 upk
;
1292 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1293 reg
= read_signed_register (upk
.regx
);
1295 pc
+= (upk
.offset
<< 1) + 2;
1302 struct upk_mips16 upk
;
1304 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1305 reg
= read_signed_register (upk
.regx
);
1307 pc
+= (upk
.offset
<< 1) + 2;
1312 case 12: /* I8 Formats btez btnez */
1314 struct upk_mips16 upk
;
1316 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1317 /* upk.regx contains the opcode */
1318 reg
= read_signed_register (24); /* Test register is 24 */
1319 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1320 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1321 /* pc = add_offset_16(pc,upk.offset) ; */
1322 pc
+= (upk
.offset
<< 1) + 2;
1327 case 29: /* RR Formats JR, JALR, JALR-RA */
1329 struct upk_mips16 upk
;
1330 /* upk.fmt = rrtype; */
1335 upk
.regx
= (insn
>> 8) & 0x07;
1336 upk
.regy
= (insn
>> 5) & 0x07;
1344 break; /* Function return instruction */
1350 break; /* BOGUS Guess */
1352 pc
= read_signed_register (reg
);
1359 /* This is an instruction extension. Fetch the real instruction
1360 (which follows the extension) and decode things based on
1364 pc
= extended_mips16_next_pc (pc
, insn
, fetch_mips_16 (pc
));
1377 mips16_next_pc (CORE_ADDR pc
)
1379 unsigned int insn
= fetch_mips_16 (pc
);
1380 return extended_mips16_next_pc (pc
, 0, insn
);
1383 /* The mips_next_pc function supports single_step when the remote
1384 target monitor or stub is not developed enough to do a single_step.
1385 It works by decoding the current instruction and predicting where a
1386 branch will go. This isnt hard because all the data is available.
1387 The MIPS32 and MIPS16 variants are quite different */
1389 mips_next_pc (CORE_ADDR pc
)
1392 return mips16_next_pc (pc
);
1394 return mips32_next_pc (pc
);
1397 struct mips_frame_cache
1400 struct trad_frame_saved_reg
*saved_regs
;
1404 static struct mips_frame_cache
*
1405 mips_mdebug_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1407 CORE_ADDR startaddr
= 0;
1408 mips_extra_func_info_t proc_desc
;
1409 struct mips_frame_cache
*cache
;
1410 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
1411 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1412 /* r0 bit means kernel trap */
1414 /* What registers have been saved? Bitmasks. */
1415 unsigned long gen_mask
, float_mask
;
1417 if ((*this_cache
) != NULL
)
1418 return (*this_cache
);
1419 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1420 (*this_cache
) = cache
;
1421 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1423 /* Get the mdebug proc descriptor. */
1424 proc_desc
= non_heuristic_proc_desc (frame_pc_unwind (next_frame
),
1426 /* Must be true. This is only called when the sniffer detected a
1428 gdb_assert (proc_desc
!= NULL
);
1430 /* Extract the frame's base. */
1431 cache
->base
= (frame_unwind_register_signed (next_frame
, NUM_REGS
+ PROC_FRAME_REG (proc_desc
))
1432 + PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
1434 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1435 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1436 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1438 /* Must be true. The in_prologue case is left for the heuristic
1439 unwinder. This is always used on kernel traps. */
1440 gdb_assert (!in_prologue (frame_pc_unwind (next_frame
), PROC_LOW_ADDR (proc_desc
))
1443 /* Fill in the offsets for the registers which gen_mask says were
1446 CORE_ADDR reg_position
= (cache
->base
+ PROC_REG_OFFSET (proc_desc
));
1449 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1450 if (gen_mask
& 0x80000000)
1452 cache
->saved_regs
[NUM_REGS
+ ireg
].addr
= reg_position
;
1453 reg_position
-= mips_abi_regsize (gdbarch
);
1457 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse
1458 order of that normally used by gcc. Therefore, we have to fetch
1459 the first instruction of the function, and if it's an entry
1460 instruction that saves $s0 or $s1, correct their saved addresses. */
1461 if (mips_pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1463 ULONGEST inst
= mips16_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1464 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700)
1468 int sreg_count
= (inst
>> 6) & 3;
1470 /* Check if the ra register was pushed on the stack. */
1471 CORE_ADDR reg_position
= (cache
->base
1472 + PROC_REG_OFFSET (proc_desc
));
1474 reg_position
-= mips_abi_regsize (gdbarch
);
1476 /* Check if the s0 and s1 registers were pushed on the
1478 /* NOTE: cagney/2004-02-08: Huh? This is doing no such
1480 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1482 cache
->saved_regs
[NUM_REGS
+ reg
].addr
= reg_position
;
1483 reg_position
-= mips_abi_regsize (gdbarch
);
1488 /* Fill in the offsets for the registers which float_mask says were
1491 CORE_ADDR reg_position
= (cache
->base
1492 + PROC_FREG_OFFSET (proc_desc
));
1494 /* Fill in the offsets for the float registers which float_mask
1496 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1497 if (float_mask
& 0x80000000)
1499 if (mips_abi_regsize (gdbarch
) == 4
1500 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1502 /* On a big endian 32 bit ABI, floating point registers
1503 are paired to form doubles such that the most
1504 significant part is in $f[N+1] and the least
1505 significant in $f[N] vis: $f[N+1] ||| $f[N]. The
1506 registers are also spilled as a pair and stored as a
1509 When little-endian the least significant part is
1510 stored first leading to the memory order $f[N] and
1513 Unfortunately, when big-endian the most significant
1514 part of the double is stored first, and the least
1515 significant is stored second. This leads to the
1516 registers being ordered in memory as firt $f[N+1] and
1519 For the big-endian case make certain that the
1520 addresses point at the correct (swapped) locations
1521 $f[N] and $f[N+1] pair (keep in mind that
1522 reg_position is decremented each time through the
1525 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1526 .addr
= reg_position
- mips_abi_regsize (gdbarch
);
1528 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1529 .addr
= reg_position
+ mips_abi_regsize (gdbarch
);
1532 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1533 .addr
= reg_position
;
1534 reg_position
-= mips_abi_regsize (gdbarch
);
1537 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
1538 = cache
->saved_regs
[NUM_REGS
+ MIPS_RA_REGNUM
];
1541 /* SP_REGNUM, contains the value and not the address. */
1542 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
1544 return (*this_cache
);
1548 mips_mdebug_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1549 struct frame_id
*this_id
)
1551 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1553 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
1557 mips_mdebug_frame_prev_register (struct frame_info
*next_frame
,
1559 int regnum
, int *optimizedp
,
1560 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1561 int *realnump
, void *valuep
)
1563 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1565 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
1566 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
1569 static const struct frame_unwind mips_mdebug_frame_unwind
=
1572 mips_mdebug_frame_this_id
,
1573 mips_mdebug_frame_prev_register
1576 static const struct frame_unwind
*
1577 mips_mdebug_frame_sniffer (struct frame_info
*next_frame
)
1579 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1580 CORE_ADDR startaddr
= 0;
1581 mips_extra_func_info_t proc_desc
;
1584 /* Only use the mdebug frame unwinder on mdebug frames where all the
1585 registers have been saved. Leave hard cases such as no mdebug or
1586 in prologue for the heuristic unwinders. */
1588 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
1589 if (proc_desc
== NULL
)
1592 /* Not sure exactly what kernel_trap means, but if it means the
1593 kernel saves the registers without a prologue doing it, we better
1594 not examine the prologue to see whether registers have been saved
1596 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1598 return &mips_mdebug_frame_unwind
;
1600 /* In any frame other than the innermost or a frame interrupted by a
1601 signal, we assume that all registers have been saved. This
1602 assumes that all register saves in a function happen before the
1603 first function call. */
1604 if (!in_prologue (pc
, PROC_LOW_ADDR (proc_desc
)))
1605 return &mips_mdebug_frame_unwind
;
1611 mips_mdebug_frame_base_address (struct frame_info
*next_frame
,
1614 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1619 static const struct frame_base mips_mdebug_frame_base
= {
1620 &mips_mdebug_frame_unwind
,
1621 mips_mdebug_frame_base_address
,
1622 mips_mdebug_frame_base_address
,
1623 mips_mdebug_frame_base_address
1626 static const struct frame_base
*
1627 mips_mdebug_frame_base_sniffer (struct frame_info
*next_frame
)
1629 if (mips_mdebug_frame_sniffer (next_frame
) != NULL
)
1630 return &mips_mdebug_frame_base
;
1635 /* Set a register's saved stack address in temp_saved_regs. If an
1636 address has already been set for this register, do nothing; this
1637 way we will only recognize the first save of a given register in a
1640 For simplicity, save the address in both [0 .. NUM_REGS) and
1641 [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range
1642 is used as it is only second range (the ABI instead of ISA
1643 registers) that comes into play when finding saved registers in a
1647 set_reg_offset (struct mips_frame_cache
*this_cache
, int regnum
,
1650 if (this_cache
!= NULL
1651 && this_cache
->saved_regs
[regnum
].addr
== -1)
1653 this_cache
->saved_regs
[regnum
+ 0 * NUM_REGS
].addr
= offset
;
1654 this_cache
->saved_regs
[regnum
+ 1 * NUM_REGS
].addr
= offset
;
1659 /* Fetch the immediate value from a MIPS16 instruction.
1660 If the previous instruction was an EXTEND, use it to extend
1661 the upper bits of the immediate value. This is a helper function
1662 for mips16_scan_prologue. */
1665 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1666 unsigned short inst
, /* current instruction */
1667 int nbits
, /* number of bits in imm field */
1668 int scale
, /* scale factor to be applied to imm */
1669 int is_signed
) /* is the imm field signed? */
1673 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1675 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1676 if (offset
& 0x8000) /* check for negative extend */
1677 offset
= 0 - (0x10000 - (offset
& 0xffff));
1678 return offset
| (inst
& 0x1f);
1682 int max_imm
= 1 << nbits
;
1683 int mask
= max_imm
- 1;
1684 int sign_bit
= max_imm
>> 1;
1686 offset
= inst
& mask
;
1687 if (is_signed
&& (offset
& sign_bit
))
1688 offset
= 0 - (max_imm
- offset
);
1689 return offset
* scale
;
1694 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1695 the associated FRAME_CACHE if not null.
1696 Return the address of the first instruction past the prologue. */
1699 mips16_scan_prologue (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1700 struct frame_info
*next_frame
,
1701 struct mips_frame_cache
*this_cache
)
1704 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1706 long frame_offset
= 0; /* Size of stack frame. */
1707 long frame_adjust
= 0; /* Offset of FP from SP. */
1708 int frame_reg
= MIPS_SP_REGNUM
;
1709 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1710 unsigned inst
= 0; /* current instruction */
1711 unsigned entry_inst
= 0; /* the entry instruction */
1714 int extend_bytes
= 0;
1715 int prev_extend_bytes
;
1716 CORE_ADDR end_prologue_addr
= 0;
1718 /* Can be called when there's no process, and hence when there's no
1720 if (next_frame
!= NULL
)
1721 sp
= read_next_frame_reg (next_frame
, NUM_REGS
+ MIPS_SP_REGNUM
);
1725 if (limit_pc
> start_pc
+ 200)
1726 limit_pc
= start_pc
+ 200;
1728 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSN_SIZE
)
1730 /* Save the previous instruction. If it's an EXTEND, we'll extract
1731 the immediate offset extension from it in mips16_get_imm. */
1734 /* Fetch and decode the instruction. */
1735 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1737 /* Normally we ignore extend instructions. However, if it is
1738 not followed by a valid prologue instruction, then this
1739 instruction is not part of the prologue either. We must
1740 remember in this case to adjust the end_prologue_addr back
1742 if ((inst
& 0xf800) == 0xf000) /* extend */
1744 extend_bytes
= MIPS16_INSN_SIZE
;
1748 prev_extend_bytes
= extend_bytes
;
1751 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1752 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1754 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1755 if (offset
< 0) /* negative stack adjustment? */
1756 frame_offset
-= offset
;
1758 /* Exit loop if a positive stack adjustment is found, which
1759 usually means that the stack cleanup code in the function
1760 epilogue is reached. */
1763 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1765 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1766 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1767 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1769 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1771 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1772 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1773 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1775 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1777 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1778 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1780 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1782 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1783 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1785 else if (inst
== 0x673d) /* move $s1, $sp */
1790 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1792 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1793 frame_addr
= sp
+ offset
;
1795 frame_adjust
= offset
;
1797 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1799 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1800 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1801 set_reg_offset (this_cache
, reg
, frame_addr
+ offset
);
1803 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1805 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1806 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1807 set_reg_offset (this_cache
, reg
, frame_addr
+ offset
);
1809 else if ((inst
& 0xf81f) == 0xe809
1810 && (inst
& 0x700) != 0x700) /* entry */
1811 entry_inst
= inst
; /* save for later processing */
1812 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1813 cur_pc
+= MIPS16_INSN_SIZE
; /* 32-bit instruction */
1814 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
1816 /* This instruction is part of the prologue, but we don't
1817 need to do anything special to handle it. */
1821 /* This instruction is not an instruction typically found
1822 in a prologue, so we must have reached the end of the
1824 if (end_prologue_addr
== 0)
1825 end_prologue_addr
= cur_pc
- prev_extend_bytes
;
1829 /* The entry instruction is typically the first instruction in a function,
1830 and it stores registers at offsets relative to the value of the old SP
1831 (before the prologue). But the value of the sp parameter to this
1832 function is the new SP (after the prologue has been executed). So we
1833 can't calculate those offsets until we've seen the entire prologue,
1834 and can calculate what the old SP must have been. */
1835 if (entry_inst
!= 0)
1837 int areg_count
= (entry_inst
>> 8) & 7;
1838 int sreg_count
= (entry_inst
>> 6) & 3;
1840 /* The entry instruction always subtracts 32 from the SP. */
1843 /* Now we can calculate what the SP must have been at the
1844 start of the function prologue. */
1847 /* Check if a0-a3 were saved in the caller's argument save area. */
1848 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1850 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1851 offset
+= mips_abi_regsize (current_gdbarch
);
1854 /* Check if the ra register was pushed on the stack. */
1856 if (entry_inst
& 0x20)
1858 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1859 offset
-= mips_abi_regsize (current_gdbarch
);
1862 /* Check if the s0 and s1 registers were pushed on the stack. */
1863 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1865 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1866 offset
-= mips_abi_regsize (current_gdbarch
);
1870 if (this_cache
!= NULL
)
1873 (frame_unwind_register_signed (next_frame
, NUM_REGS
+ frame_reg
)
1874 + frame_offset
- frame_adjust
);
1875 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
1876 be able to get rid of the assignment below, evetually. But it's
1877 still needed for now. */
1878 this_cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
1879 = this_cache
->saved_regs
[NUM_REGS
+ MIPS_RA_REGNUM
];
1882 /* If we didn't reach the end of the prologue when scanning the function
1883 instructions, then set end_prologue_addr to the address of the
1884 instruction immediately after the last one we scanned. */
1885 if (end_prologue_addr
== 0)
1886 end_prologue_addr
= cur_pc
;
1888 return end_prologue_addr
;
1891 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
1892 Procedures that use the 32-bit instruction set are handled by the
1893 mips_insn32 unwinder. */
1895 static struct mips_frame_cache
*
1896 mips_insn16_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1898 struct mips_frame_cache
*cache
;
1900 if ((*this_cache
) != NULL
)
1901 return (*this_cache
);
1902 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1903 (*this_cache
) = cache
;
1904 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1906 /* Analyze the function prologue. */
1908 const CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1909 CORE_ADDR start_addr
;
1911 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
1912 if (start_addr
== 0)
1913 start_addr
= heuristic_proc_start (pc
);
1914 /* We can't analyze the prologue if we couldn't find the begining
1916 if (start_addr
== 0)
1919 mips16_scan_prologue (start_addr
, pc
, next_frame
, *this_cache
);
1922 /* SP_REGNUM, contains the value and not the address. */
1923 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
1925 return (*this_cache
);
1929 mips_insn16_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1930 struct frame_id
*this_id
)
1932 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1934 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
1938 mips_insn16_frame_prev_register (struct frame_info
*next_frame
,
1940 int regnum
, int *optimizedp
,
1941 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1942 int *realnump
, void *valuep
)
1944 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1946 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
1947 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
1950 static const struct frame_unwind mips_insn16_frame_unwind
=
1953 mips_insn16_frame_this_id
,
1954 mips_insn16_frame_prev_register
1957 static const struct frame_unwind
*
1958 mips_insn16_frame_sniffer (struct frame_info
*next_frame
)
1960 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1961 if (mips_pc_is_mips16 (pc
))
1962 return &mips_insn16_frame_unwind
;
1967 mips_insn16_frame_base_address (struct frame_info
*next_frame
,
1970 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1975 static const struct frame_base mips_insn16_frame_base
=
1977 &mips_insn16_frame_unwind
,
1978 mips_insn16_frame_base_address
,
1979 mips_insn16_frame_base_address
,
1980 mips_insn16_frame_base_address
1983 static const struct frame_base
*
1984 mips_insn16_frame_base_sniffer (struct frame_info
*next_frame
)
1986 if (mips_insn16_frame_sniffer (next_frame
) != NULL
)
1987 return &mips_insn16_frame_base
;
1992 /* Mark all the registers as unset in the saved_regs array
1993 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
1996 reset_saved_regs (struct mips_frame_cache
*this_cache
)
1998 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
2002 const int num_regs
= NUM_REGS
;
2005 for (i
= 0; i
< num_regs
; i
++)
2007 this_cache
->saved_regs
[i
].addr
= -1;
2012 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
2013 the associated FRAME_CACHE if not null.
2014 Return the address of the first instruction past the prologue. */
2017 mips32_scan_prologue (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2018 struct frame_info
*next_frame
,
2019 struct mips_frame_cache
*this_cache
)
2022 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
2025 int frame_reg
= MIPS_SP_REGNUM
;
2027 CORE_ADDR end_prologue_addr
= 0;
2028 int seen_sp_adjust
= 0;
2029 int load_immediate_bytes
= 0;
2031 /* Can be called when there's no process, and hence when there's no
2033 if (next_frame
!= NULL
)
2034 sp
= read_next_frame_reg (next_frame
, NUM_REGS
+ MIPS_SP_REGNUM
);
2038 if (limit_pc
> start_pc
+ 200)
2039 limit_pc
= start_pc
+ 200;
2044 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS32_INSN_SIZE
)
2046 unsigned long inst
, high_word
, low_word
;
2049 /* Fetch the instruction. */
2050 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
2052 /* Save some code by pre-extracting some useful fields. */
2053 high_word
= (inst
>> 16) & 0xffff;
2054 low_word
= inst
& 0xffff;
2055 reg
= high_word
& 0x1f;
2057 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
2058 || high_word
== 0x23bd /* addi $sp,$sp,-i */
2059 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
2061 if (low_word
& 0x8000) /* negative stack adjustment? */
2062 frame_offset
+= 0x10000 - low_word
;
2064 /* Exit loop if a positive stack adjustment is found, which
2065 usually means that the stack cleanup code in the function
2066 epilogue is reached. */
2070 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
2072 set_reg_offset (this_cache
, reg
, sp
+ low_word
);
2074 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
2076 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
2077 set_reg_offset (this_cache
, reg
, sp
+ low_word
);
2079 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
2081 /* Old gcc frame, r30 is virtual frame pointer. */
2082 if ((long) low_word
!= frame_offset
)
2083 frame_addr
= sp
+ low_word
;
2084 else if (frame_reg
== MIPS_SP_REGNUM
)
2086 unsigned alloca_adjust
;
2089 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2090 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
2091 if (alloca_adjust
> 0)
2093 /* FP > SP + frame_size. This may be because of
2094 an alloca or somethings similar. Fix sp to
2095 "pre-alloca" value, and try again. */
2096 sp
+= alloca_adjust
;
2097 /* Need to reset the status of all registers. Otherwise,
2098 we will hit a guard that prevents the new address
2099 for each register to be recomputed during the second
2101 reset_saved_regs (this_cache
);
2106 /* move $30,$sp. With different versions of gas this will be either
2107 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2108 Accept any one of these. */
2109 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2111 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2112 if (frame_reg
== MIPS_SP_REGNUM
)
2114 unsigned alloca_adjust
;
2117 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2118 alloca_adjust
= (unsigned) (frame_addr
- sp
);
2119 if (alloca_adjust
> 0)
2121 /* FP > SP + frame_size. This may be because of
2122 an alloca or somethings similar. Fix sp to
2123 "pre-alloca" value, and try again. */
2125 /* Need to reset the status of all registers. Otherwise,
2126 we will hit a guard that prevents the new address
2127 for each register to be recomputed during the second
2129 reset_saved_regs (this_cache
);
2134 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
2136 set_reg_offset (this_cache
, reg
, frame_addr
+ low_word
);
2138 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
2139 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
2140 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
2141 || high_word
== 0x3c1c /* lui $gp,n */
2142 || high_word
== 0x279c /* addiu $gp,$gp,n */
2143 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
2144 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
2147 /* These instructions are part of the prologue, but we don't
2148 need to do anything special to handle them. */
2150 /* The instructions below load $at or $t0 with an immediate
2151 value in preparation for a stack adjustment via
2152 subu $sp,$sp,[$at,$t0]. These instructions could also
2153 initialize a local variable, so we accept them only before
2154 a stack adjustment instruction was seen. */
2155 else if (!seen_sp_adjust
2156 && (high_word
== 0x3c01 /* lui $at,n */
2157 || high_word
== 0x3c08 /* lui $t0,n */
2158 || high_word
== 0x3421 /* ori $at,$at,n */
2159 || high_word
== 0x3508 /* ori $t0,$t0,n */
2160 || high_word
== 0x3401 /* ori $at,$zero,n */
2161 || high_word
== 0x3408 /* ori $t0,$zero,n */
2164 load_immediate_bytes
+= MIPS32_INSN_SIZE
; /* FIXME! */
2168 /* This instruction is not an instruction typically found
2169 in a prologue, so we must have reached the end of the
2171 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
2172 loop now? Why would we need to continue scanning the function
2174 if (end_prologue_addr
== 0)
2175 end_prologue_addr
= cur_pc
;
2179 if (this_cache
!= NULL
)
2182 (frame_unwind_register_signed (next_frame
, NUM_REGS
+ frame_reg
)
2184 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
2185 this assignment below, eventually. But it's still needed
2187 this_cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
2188 = this_cache
->saved_regs
[NUM_REGS
+ MIPS_RA_REGNUM
];
2191 /* If we didn't reach the end of the prologue when scanning the function
2192 instructions, then set end_prologue_addr to the address of the
2193 instruction immediately after the last one we scanned. */
2194 /* brobecker/2004-10-10: I don't think this would ever happen, but
2195 we may as well be careful and do our best if we have a null
2196 end_prologue_addr. */
2197 if (end_prologue_addr
== 0)
2198 end_prologue_addr
= cur_pc
;
2200 /* In a frameless function, we might have incorrectly
2201 skipped some load immediate instructions. Undo the skipping
2202 if the load immediate was not followed by a stack adjustment. */
2203 if (load_immediate_bytes
&& !seen_sp_adjust
)
2204 end_prologue_addr
-= load_immediate_bytes
;
2206 return end_prologue_addr
;
2209 /* Heuristic unwinder for procedures using 32-bit instructions (covers
2210 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
2211 instructions (a.k.a. MIPS16) are handled by the mips_insn16
2214 static struct mips_frame_cache
*
2215 mips_insn32_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
2217 struct mips_frame_cache
*cache
;
2219 if ((*this_cache
) != NULL
)
2220 return (*this_cache
);
2222 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2223 (*this_cache
) = cache
;
2224 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
2226 /* Analyze the function prologue. */
2228 const CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2229 CORE_ADDR start_addr
;
2231 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2232 if (start_addr
== 0)
2233 start_addr
= heuristic_proc_start (pc
);
2234 /* We can't analyze the prologue if we couldn't find the begining
2236 if (start_addr
== 0)
2239 mips32_scan_prologue (start_addr
, pc
, next_frame
, *this_cache
);
2242 /* SP_REGNUM, contains the value and not the address. */
2243 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
2245 return (*this_cache
);
2249 mips_insn32_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2250 struct frame_id
*this_id
)
2252 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2254 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
2258 mips_insn32_frame_prev_register (struct frame_info
*next_frame
,
2260 int regnum
, int *optimizedp
,
2261 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2262 int *realnump
, void *valuep
)
2264 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2266 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
2267 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
2270 static const struct frame_unwind mips_insn32_frame_unwind
=
2273 mips_insn32_frame_this_id
,
2274 mips_insn32_frame_prev_register
2277 static const struct frame_unwind
*
2278 mips_insn32_frame_sniffer (struct frame_info
*next_frame
)
2280 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2281 if (! mips_pc_is_mips16 (pc
))
2282 return &mips_insn32_frame_unwind
;
2287 mips_insn32_frame_base_address (struct frame_info
*next_frame
,
2290 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2295 static const struct frame_base mips_insn32_frame_base
=
2297 &mips_insn32_frame_unwind
,
2298 mips_insn32_frame_base_address
,
2299 mips_insn32_frame_base_address
,
2300 mips_insn32_frame_base_address
2303 static const struct frame_base
*
2304 mips_insn32_frame_base_sniffer (struct frame_info
*next_frame
)
2306 if (mips_insn32_frame_sniffer (next_frame
) != NULL
)
2307 return &mips_insn32_frame_base
;
2312 static struct trad_frame_cache
*
2313 mips_stub_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
2316 CORE_ADDR start_addr
;
2317 CORE_ADDR stack_addr
;
2318 struct trad_frame_cache
*this_trad_cache
;
2320 if ((*this_cache
) != NULL
)
2321 return (*this_cache
);
2322 this_trad_cache
= trad_frame_cache_zalloc (next_frame
);
2323 (*this_cache
) = this_trad_cache
;
2325 /* The return address is in the link register. */
2326 trad_frame_set_reg_realreg (this_trad_cache
, PC_REGNUM
, MIPS_RA_REGNUM
);
2328 /* Frame ID, since it's a frameless / stackless function, no stack
2329 space is allocated and SP on entry is the current SP. */
2330 pc
= frame_pc_unwind (next_frame
);
2331 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2332 stack_addr
= frame_unwind_register_signed (next_frame
, MIPS_SP_REGNUM
);
2333 trad_frame_set_id (this_trad_cache
, frame_id_build (start_addr
, stack_addr
));
2335 /* Assume that the frame's base is the same as the
2337 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
2339 return this_trad_cache
;
2343 mips_stub_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2344 struct frame_id
*this_id
)
2346 struct trad_frame_cache
*this_trad_cache
2347 = mips_stub_frame_cache (next_frame
, this_cache
);
2348 trad_frame_get_id (this_trad_cache
, this_id
);
2352 mips_stub_frame_prev_register (struct frame_info
*next_frame
,
2354 int regnum
, int *optimizedp
,
2355 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2356 int *realnump
, void *valuep
)
2358 struct trad_frame_cache
*this_trad_cache
2359 = mips_stub_frame_cache (next_frame
, this_cache
);
2360 trad_frame_get_register (this_trad_cache
, next_frame
, regnum
, optimizedp
,
2361 lvalp
, addrp
, realnump
, valuep
);
2364 static const struct frame_unwind mips_stub_frame_unwind
=
2367 mips_stub_frame_this_id
,
2368 mips_stub_frame_prev_register
2371 static const struct frame_unwind
*
2372 mips_stub_frame_sniffer (struct frame_info
*next_frame
)
2374 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2375 if (in_plt_section (pc
, NULL
))
2376 return &mips_stub_frame_unwind
;
2382 mips_stub_frame_base_address (struct frame_info
*next_frame
,
2385 struct trad_frame_cache
*this_trad_cache
2386 = mips_stub_frame_cache (next_frame
, this_cache
);
2387 return trad_frame_get_this_base (this_trad_cache
);
2390 static const struct frame_base mips_stub_frame_base
=
2392 &mips_stub_frame_unwind
,
2393 mips_stub_frame_base_address
,
2394 mips_stub_frame_base_address
,
2395 mips_stub_frame_base_address
2398 static const struct frame_base
*
2399 mips_stub_frame_base_sniffer (struct frame_info
*next_frame
)
2401 if (mips_stub_frame_sniffer (next_frame
) != NULL
)
2402 return &mips_stub_frame_base
;
2408 read_next_frame_reg (struct frame_info
*fi
, int regno
)
2410 /* Always a pseudo. */
2411 gdb_assert (regno
>= NUM_REGS
);
2415 regcache_cooked_read_signed (current_regcache
, regno
, &val
);
2419 return frame_unwind_register_signed (fi
, regno
);
2423 /* mips_addr_bits_remove - remove useless address bits */
2426 mips_addr_bits_remove (CORE_ADDR addr
)
2428 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2429 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
2430 /* This hack is a work-around for existing boards using PMON, the
2431 simulator, and any other 64-bit targets that doesn't have true
2432 64-bit addressing. On these targets, the upper 32 bits of
2433 addresses are ignored by the hardware. Thus, the PC or SP are
2434 likely to have been sign extended to all 1s by instruction
2435 sequences that load 32-bit addresses. For example, a typical
2436 piece of code that loads an address is this:
2438 lui $r2, <upper 16 bits>
2439 ori $r2, <lower 16 bits>
2441 But the lui sign-extends the value such that the upper 32 bits
2442 may be all 1s. The workaround is simply to mask off these
2443 bits. In the future, gcc may be changed to support true 64-bit
2444 addressing, and this masking will have to be disabled. */
2445 return addr
&= 0xffffffffUL
;
2450 /* mips_software_single_step() is called just before we want to resume
2451 the inferior, if we want to single-step it but there is no hardware
2452 or kernel single-step support (MIPS on GNU/Linux for example). We find
2453 the target of the coming instruction and breakpoint it.
2455 single_step is also called just after the inferior stops. If we had
2456 set up a simulated single-step, we undo our damage. */
2459 mips_software_single_step (enum target_signal sig
, int insert_breakpoints_p
)
2461 static CORE_ADDR next_pc
;
2462 typedef char binsn_quantum
[BREAKPOINT_MAX
];
2463 static binsn_quantum break_mem
;
2466 if (insert_breakpoints_p
)
2468 pc
= read_register (mips_regnum (current_gdbarch
)->pc
);
2469 next_pc
= mips_next_pc (pc
);
2471 target_insert_breakpoint (next_pc
, break_mem
);
2474 target_remove_breakpoint (next_pc
, break_mem
);
2477 static struct mips_extra_func_info temp_proc_desc
;
2479 /* Test whether the PC points to the return instruction at the
2480 end of a function. */
2483 mips_about_to_return (CORE_ADDR pc
)
2485 if (mips_pc_is_mips16 (pc
))
2486 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2487 generates a "jr $ra"; other times it generates code to load
2488 the return address from the stack to an accessible register (such
2489 as $a3), then a "jr" using that register. This second case
2490 is almost impossible to distinguish from an indirect jump
2491 used for switch statements, so we don't even try. */
2492 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
2494 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
2498 /* This fencepost looks highly suspicious to me. Removing it also
2499 seems suspicious as it could affect remote debugging across serial
2503 heuristic_proc_start (CORE_ADDR pc
)
2510 pc
= ADDR_BITS_REMOVE (pc
);
2512 fence
= start_pc
- heuristic_fence_post
;
2516 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
2517 fence
= VM_MIN_ADDRESS
;
2519 instlen
= mips_pc_is_mips16 (pc
) ? MIPS16_INSN_SIZE
: MIPS32_INSN_SIZE
;
2521 /* search back for previous return */
2522 for (start_pc
-= instlen
;; start_pc
-= instlen
)
2523 if (start_pc
< fence
)
2525 /* It's not clear to me why we reach this point when
2526 stop_soon, but with this test, at least we
2527 don't print out warnings for every child forked (eg, on
2528 decstation). 22apr93 rich@cygnus.com. */
2529 if (stop_soon
== NO_STOP_QUIETLY
)
2531 static int blurb_printed
= 0;
2533 warning ("GDB can't find the start of the function at 0x%s.",
2538 /* This actually happens frequently in embedded
2539 development, when you first connect to a board
2540 and your stack pointer and pc are nowhere in
2541 particular. This message needs to give people
2542 in that situation enough information to
2543 determine that it's no big deal. */
2544 printf_filtered ("\n\
2545 GDB is unable to find the start of the function at 0x%s\n\
2546 and thus can't determine the size of that function's stack frame.\n\
2547 This means that GDB may be unable to access that stack frame, or\n\
2548 the frames below it.\n\
2549 This problem is most likely caused by an invalid program counter or\n\
2551 However, if you think GDB should simply search farther back\n\
2552 from 0x%s for code which looks like the beginning of a\n\
2553 function, you can increase the range of the search using the `set\n\
2554 heuristic-fence-post' command.\n", paddr_nz (pc
), paddr_nz (pc
));
2561 else if (mips_pc_is_mips16 (start_pc
))
2563 unsigned short inst
;
2565 /* On MIPS16, any one of the following is likely to be the
2566 start of a function:
2570 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
2571 inst
= mips_fetch_instruction (start_pc
);
2572 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
2573 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
2574 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
2575 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
2577 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2578 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2583 else if (mips_about_to_return (start_pc
))
2585 /* Skip return and its delay slot. */
2586 start_pc
+= 2 * MIPS32_INSN_SIZE
;
2593 struct mips_objfile_private
2599 /* Global used to communicate between non_heuristic_proc_desc and
2600 compare_pdr_entries within qsort (). */
2601 static bfd
*the_bfd
;
2604 compare_pdr_entries (const void *a
, const void *b
)
2606 CORE_ADDR lhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) a
);
2607 CORE_ADDR rhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) b
);
2611 else if (lhs
== rhs
)
2617 static mips_extra_func_info_t
2618 non_heuristic_proc_desc (CORE_ADDR pc
, CORE_ADDR
*addrptr
)
2620 CORE_ADDR startaddr
;
2621 mips_extra_func_info_t proc_desc
;
2622 struct block
*b
= block_for_pc (pc
);
2624 struct obj_section
*sec
;
2625 struct mips_objfile_private
*priv
;
2627 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
2629 *addrptr
= startaddr
;
2633 sec
= find_pc_section (pc
);
2636 priv
= (struct mips_objfile_private
*) objfile_data (sec
->objfile
, mips_pdr_data
);
2638 /* Search the ".pdr" section generated by GAS. This includes most of
2639 the information normally found in ECOFF PDRs. */
2641 the_bfd
= sec
->objfile
->obfd
;
2643 && (the_bfd
->format
== bfd_object
2644 && bfd_get_flavour (the_bfd
) == bfd_target_elf_flavour
2645 && elf_elfheader (the_bfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
))
2647 /* Right now GAS only outputs the address as a four-byte sequence.
2648 This means that we should not bother with this method on 64-bit
2649 targets (until that is fixed). */
2651 priv
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
2652 sizeof (struct mips_objfile_private
));
2654 set_objfile_data (sec
->objfile
, mips_pdr_data
, priv
);
2656 else if (priv
== NULL
)
2660 priv
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
2661 sizeof (struct mips_objfile_private
));
2663 bfdsec
= bfd_get_section_by_name (sec
->objfile
->obfd
, ".pdr");
2666 priv
->size
= bfd_section_size (sec
->objfile
->obfd
, bfdsec
);
2667 priv
->contents
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
2669 bfd_get_section_contents (sec
->objfile
->obfd
, bfdsec
,
2670 priv
->contents
, 0, priv
->size
);
2672 /* In general, the .pdr section is sorted. However, in the
2673 presence of multiple code sections (and other corner cases)
2674 it can become unsorted. Sort it so that we can use a faster
2676 qsort (priv
->contents
, priv
->size
/ 32, 32,
2677 compare_pdr_entries
);
2682 set_objfile_data (sec
->objfile
, mips_pdr_data
, priv
);
2686 if (priv
->size
!= 0)
2693 high
= priv
->size
/ 32;
2695 /* We've found a .pdr section describing this objfile. We want to
2696 find the entry which describes this code address. The .pdr
2697 information is not very descriptive; we have only a function
2698 start address. We have to look for the closest entry, because
2699 the local symbol at the beginning of this function may have
2700 been stripped - so if we ask the symbol table for the start
2701 address we may get a preceding global function. */
2703 /* First, find the last .pdr entry starting at or before PC. */
2706 mid
= (low
+ high
) / 2;
2708 ptr
= priv
->contents
+ mid
* 32;
2709 pdr_pc
= bfd_get_signed_32 (sec
->objfile
->obfd
, ptr
);
2710 pdr_pc
+= ANOFFSET (sec
->objfile
->section_offsets
,
2711 SECT_OFF_TEXT (sec
->objfile
));
2718 while (low
!= high
);
2720 /* Both low and high point one past the PDR of interest. If
2721 both are zero, that means this PC is before any region
2722 covered by a PDR, i.e. pdr_pc for the first PDR entry is
2726 ptr
= priv
->contents
+ (low
- 1) * 32;
2727 pdr_pc
= bfd_get_signed_32 (sec
->objfile
->obfd
, ptr
);
2728 pdr_pc
+= ANOFFSET (sec
->objfile
->section_offsets
,
2729 SECT_OFF_TEXT (sec
->objfile
));
2732 /* We don't have a range, so we have no way to know for sure
2733 whether we're in the correct PDR or a PDR for a preceding
2734 function and the current function was a stripped local
2735 symbol. But if the PDR's PC is at least as great as the
2736 best guess from the symbol table, assume that it does cover
2737 the right area; if a .pdr section is present at all then
2738 nearly every function will have an entry. The biggest exception
2739 will be the dynamic linker stubs; conveniently these are
2740 placed before .text instead of after. */
2742 if (pc
>= pdr_pc
&& pdr_pc
>= startaddr
)
2744 struct symbol
*sym
= find_pc_function (pc
);
2749 /* Fill in what we need of the proc_desc. */
2750 proc_desc
= (mips_extra_func_info_t
)
2751 obstack_alloc (&sec
->objfile
->objfile_obstack
,
2752 sizeof (struct mips_extra_func_info
));
2753 PROC_LOW_ADDR (proc_desc
) = pdr_pc
;
2755 /* Only used for dummy frames. */
2756 PROC_HIGH_ADDR (proc_desc
) = 0;
2758 PROC_FRAME_OFFSET (proc_desc
)
2759 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 20);
2760 PROC_FRAME_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2762 PROC_FRAME_ADJUST (proc_desc
) = 0;
2763 PROC_REG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2765 PROC_FREG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2767 PROC_REG_OFFSET (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2769 PROC_FREG_OFFSET (proc_desc
)
2770 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 16);
2771 PROC_PC_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2773 proc_desc
->pdr
.isym
= (long) sym
;
2783 if (startaddr
> BLOCK_START (b
))
2785 /* This is the "pathological" case referred to in a comment in
2786 print_frame_info. It might be better to move this check into
2791 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_DOMAIN
, 0, NULL
);
2793 /* If we never found a PDR for this function in symbol reading, then
2794 examine prologues to find the information. */
2797 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
2798 if (PROC_FRAME_REG (proc_desc
) == -1)
2807 /* MIPS stack frames are almost impenetrable. When execution stops,
2808 we basically have to look at symbol information for the function
2809 that we stopped in, which tells us *which* register (if any) is
2810 the base of the frame pointer, and what offset from that register
2811 the frame itself is at.
2813 This presents a problem when trying to examine a stack in memory
2814 (that isn't executing at the moment), using the "frame" command. We
2815 don't have a PC, nor do we have any registers except SP.
2817 This routine takes two arguments, SP and PC, and tries to make the
2818 cached frames look as if these two arguments defined a frame on the
2819 cache. This allows the rest of info frame to extract the important
2820 arguments without difficulty. */
2823 setup_arbitrary_frame (int argc
, CORE_ADDR
*argv
)
2826 error ("MIPS frame specifications require two arguments: sp and pc");
2828 return create_new_frame (argv
[0], argv
[1]);
2831 /* According to the current ABI, should the type be passed in a
2832 floating-point register (assuming that there is space)? When there
2833 is no FPU, FP are not even considered as possibile candidates for
2834 FP registers and, consequently this returns false - forces FP
2835 arguments into integer registers. */
2838 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
2840 return ((typecode
== TYPE_CODE_FLT
2842 && (typecode
== TYPE_CODE_STRUCT
2843 || typecode
== TYPE_CODE_UNION
)
2844 && TYPE_NFIELDS (arg_type
) == 1
2845 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type
, 0)) == TYPE_CODE_FLT
))
2846 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
2849 /* On o32, argument passing in GPRs depends on the alignment of the type being
2850 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2853 mips_type_needs_double_align (struct type
*type
)
2855 enum type_code typecode
= TYPE_CODE (type
);
2857 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2859 else if (typecode
== TYPE_CODE_STRUCT
)
2861 if (TYPE_NFIELDS (type
) < 1)
2863 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2865 else if (typecode
== TYPE_CODE_UNION
)
2869 n
= TYPE_NFIELDS (type
);
2870 for (i
= 0; i
< n
; i
++)
2871 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2878 /* Adjust the address downward (direction of stack growth) so that it
2879 is correctly aligned for a new stack frame. */
2881 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2883 return align_down (addr
, 16);
2887 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2888 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2889 int nargs
, struct value
**args
, CORE_ADDR sp
,
2890 int struct_return
, CORE_ADDR struct_addr
)
2896 int stack_offset
= 0;
2897 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2898 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
2900 /* For shared libraries, "t9" needs to point at the function
2902 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
2904 /* Set the return address register to point to the entry point of
2905 the program, where a breakpoint lies in wait. */
2906 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
2908 /* First ensure that the stack and structure return address (if any)
2909 are properly aligned. The stack has to be at least 64-bit
2910 aligned even on 32-bit machines, because doubles must be 64-bit
2911 aligned. For n32 and n64, stack frames need to be 128-bit
2912 aligned, so we round to this widest known alignment. */
2914 sp
= align_down (sp
, 16);
2915 struct_addr
= align_down (struct_addr
, 16);
2917 /* Now make space on the stack for the args. We allocate more
2918 than necessary for EABI, because the first few arguments are
2919 passed in registers, but that's OK. */
2920 for (argnum
= 0; argnum
< nargs
; argnum
++)
2921 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
2922 mips_stack_argsize (gdbarch
));
2923 sp
-= align_up (len
, 16);
2926 fprintf_unfiltered (gdb_stdlog
,
2927 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
2928 paddr_nz (sp
), (long) align_up (len
, 16));
2930 /* Initialize the integer and float register pointers. */
2931 argreg
= MIPS_A0_REGNUM
;
2932 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
2934 /* The struct_return pointer occupies the first parameter-passing reg. */
2938 fprintf_unfiltered (gdb_stdlog
,
2939 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
2940 argreg
, paddr_nz (struct_addr
));
2941 write_register (argreg
++, struct_addr
);
2944 /* Now load as many as possible of the first arguments into
2945 registers, and push the rest onto the stack. Loop thru args
2946 from first to last. */
2947 for (argnum
= 0; argnum
< nargs
; argnum
++)
2950 char valbuf
[MAX_REGISTER_SIZE
];
2951 struct value
*arg
= args
[argnum
];
2952 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
2953 int len
= TYPE_LENGTH (arg_type
);
2954 enum type_code typecode
= TYPE_CODE (arg_type
);
2957 fprintf_unfiltered (gdb_stdlog
,
2958 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2959 argnum
+ 1, len
, (int) typecode
);
2961 /* The EABI passes structures that do not fit in a register by
2963 if (len
> mips_abi_regsize (gdbarch
)
2964 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2966 store_unsigned_integer (valbuf
, mips_abi_regsize (gdbarch
),
2967 VALUE_ADDRESS (arg
));
2968 typecode
= TYPE_CODE_PTR
;
2969 len
= mips_abi_regsize (gdbarch
);
2972 fprintf_unfiltered (gdb_stdlog
, " push");
2975 val
= (char *) VALUE_CONTENTS (arg
);
2977 /* 32-bit ABIs always start floating point arguments in an
2978 even-numbered floating point register. Round the FP register
2979 up before the check to see if there are any FP registers
2980 left. Non MIPS_EABI targets also pass the FP in the integer
2981 registers so also round up normal registers. */
2982 if (mips_abi_regsize (gdbarch
) < 8
2983 && fp_register_arg_p (typecode
, arg_type
))
2985 if ((float_argreg
& 1))
2989 /* Floating point arguments passed in registers have to be
2990 treated specially. On 32-bit architectures, doubles
2991 are passed in register pairs; the even register gets
2992 the low word, and the odd register gets the high word.
2993 On non-EABI processors, the first two floating point arguments are
2994 also copied to general registers, because MIPS16 functions
2995 don't use float registers for arguments. This duplication of
2996 arguments in general registers can't hurt non-MIPS16 functions
2997 because those registers are normally skipped. */
2998 /* MIPS_EABI squeezes a struct that contains a single floating
2999 point value into an FP register instead of pushing it onto the
3001 if (fp_register_arg_p (typecode
, arg_type
)
3002 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3004 if (mips_abi_regsize (gdbarch
) < 8 && len
== 8)
3006 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3007 unsigned long regval
;
3009 /* Write the low word of the double to the even register(s). */
3010 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3012 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3013 float_argreg
, phex (regval
, 4));
3014 write_register (float_argreg
++, regval
);
3016 /* Write the high word of the double to the odd register(s). */
3017 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3019 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3020 float_argreg
, phex (regval
, 4));
3021 write_register (float_argreg
++, regval
);
3025 /* This is a floating point value that fits entirely
3026 in a single register. */
3027 /* On 32 bit ABI's the float_argreg is further adjusted
3028 above to ensure that it is even register aligned. */
3029 LONGEST regval
= extract_unsigned_integer (val
, len
);
3031 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3032 float_argreg
, phex (regval
, len
));
3033 write_register (float_argreg
++, regval
);
3038 /* Copy the argument to general registers or the stack in
3039 register-sized pieces. Large arguments are split between
3040 registers and stack. */
3041 /* Note: structs whose size is not a multiple of
3042 mips_abi_regsize() are treated specially: Irix cc passes
3043 them in registers where gcc sometimes puts them on the
3044 stack. For maximum compatibility, we will put them in
3046 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
3047 && (len
% mips_abi_regsize (gdbarch
) != 0));
3049 /* Note: Floating-point values that didn't fit into an FP
3050 register are only written to memory. */
3053 /* Remember if the argument was written to the stack. */
3054 int stack_used_p
= 0;
3055 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
3056 ? len
: mips_abi_regsize (gdbarch
));
3059 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3062 /* Write this portion of the argument to the stack. */
3063 if (argreg
> MIPS_LAST_ARG_REGNUM
3065 || fp_register_arg_p (typecode
, arg_type
))
3067 /* Should shorter than int integer values be
3068 promoted to int before being stored? */
3069 int longword_offset
= 0;
3072 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3074 if (mips_stack_argsize (gdbarch
) == 8
3075 && (typecode
== TYPE_CODE_INT
3076 || typecode
== TYPE_CODE_PTR
3077 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3078 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3079 else if ((typecode
== TYPE_CODE_STRUCT
3080 || typecode
== TYPE_CODE_UNION
)
3081 && (TYPE_LENGTH (arg_type
)
3082 < mips_stack_argsize (gdbarch
)))
3083 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3088 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3089 paddr_nz (stack_offset
));
3090 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3091 paddr_nz (longword_offset
));
3094 addr
= sp
+ stack_offset
+ longword_offset
;
3099 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3101 for (i
= 0; i
< partial_len
; i
++)
3103 fprintf_unfiltered (gdb_stdlog
, "%02x",
3107 write_memory (addr
, val
, partial_len
);
3110 /* Note!!! This is NOT an else clause. Odd sized
3111 structs may go thru BOTH paths. Floating point
3112 arguments will not. */
3113 /* Write this portion of the argument to a general
3114 purpose register. */
3115 if (argreg
<= MIPS_LAST_ARG_REGNUM
3116 && !fp_register_arg_p (typecode
, arg_type
))
3119 extract_unsigned_integer (val
, partial_len
);
3122 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3125 mips_abi_regsize (gdbarch
)));
3126 write_register (argreg
, regval
);
3133 /* Compute the the offset into the stack at which we
3134 will copy the next parameter.
3136 In the new EABI (and the NABI32), the stack_offset
3137 only needs to be adjusted when it has been used. */
3140 stack_offset
+= align_up (partial_len
,
3141 mips_stack_argsize (gdbarch
));
3145 fprintf_unfiltered (gdb_stdlog
, "\n");
3148 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3150 /* Return adjusted stack pointer. */
3154 /* Determin the return value convention being used. */
3156 static enum return_value_convention
3157 mips_eabi_return_value (struct gdbarch
*gdbarch
,
3158 struct type
*type
, struct regcache
*regcache
,
3159 void *readbuf
, const void *writebuf
)
3161 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
3162 return RETURN_VALUE_STRUCT_CONVENTION
;
3164 memset (readbuf
, 0, TYPE_LENGTH (type
));
3165 return RETURN_VALUE_REGISTER_CONVENTION
;
3169 /* N32/N64 ABI stuff. */
3172 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3173 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3174 int nargs
, struct value
**args
, CORE_ADDR sp
,
3175 int struct_return
, CORE_ADDR struct_addr
)
3181 int stack_offset
= 0;
3182 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3183 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3185 /* For shared libraries, "t9" needs to point at the function
3187 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3189 /* Set the return address register to point to the entry point of
3190 the program, where a breakpoint lies in wait. */
3191 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3193 /* First ensure that the stack and structure return address (if any)
3194 are properly aligned. The stack has to be at least 64-bit
3195 aligned even on 32-bit machines, because doubles must be 64-bit
3196 aligned. For n32 and n64, stack frames need to be 128-bit
3197 aligned, so we round to this widest known alignment. */
3199 sp
= align_down (sp
, 16);
3200 struct_addr
= align_down (struct_addr
, 16);
3202 /* Now make space on the stack for the args. */
3203 for (argnum
= 0; argnum
< nargs
; argnum
++)
3204 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3205 mips_stack_argsize (gdbarch
));
3206 sp
-= align_up (len
, 16);
3209 fprintf_unfiltered (gdb_stdlog
,
3210 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
3211 paddr_nz (sp
), (long) align_up (len
, 16));
3213 /* Initialize the integer and float register pointers. */
3214 argreg
= MIPS_A0_REGNUM
;
3215 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3217 /* The struct_return pointer occupies the first parameter-passing reg. */
3221 fprintf_unfiltered (gdb_stdlog
,
3222 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
3223 argreg
, paddr_nz (struct_addr
));
3224 write_register (argreg
++, struct_addr
);
3227 /* Now load as many as possible of the first arguments into
3228 registers, and push the rest onto the stack. Loop thru args
3229 from first to last. */
3230 for (argnum
= 0; argnum
< nargs
; argnum
++)
3233 struct value
*arg
= args
[argnum
];
3234 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3235 int len
= TYPE_LENGTH (arg_type
);
3236 enum type_code typecode
= TYPE_CODE (arg_type
);
3239 fprintf_unfiltered (gdb_stdlog
,
3240 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3241 argnum
+ 1, len
, (int) typecode
);
3243 val
= (char *) VALUE_CONTENTS (arg
);
3245 if (fp_register_arg_p (typecode
, arg_type
)
3246 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3248 /* This is a floating point value that fits entirely
3249 in a single register. */
3250 /* On 32 bit ABI's the float_argreg is further adjusted
3251 above to ensure that it is even register aligned. */
3252 LONGEST regval
= extract_unsigned_integer (val
, len
);
3254 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3255 float_argreg
, phex (regval
, len
));
3256 write_register (float_argreg
++, regval
);
3259 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3260 argreg
, phex (regval
, len
));
3261 write_register (argreg
, regval
);
3266 /* Copy the argument to general registers or the stack in
3267 register-sized pieces. Large arguments are split between
3268 registers and stack. */
3269 /* Note: structs whose size is not a multiple of
3270 mips_abi_regsize() are treated specially: Irix cc passes
3271 them in registers where gcc sometimes puts them on the
3272 stack. For maximum compatibility, we will put them in
3274 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
3275 && (len
% mips_abi_regsize (gdbarch
) != 0));
3276 /* Note: Floating-point values that didn't fit into an FP
3277 register are only written to memory. */
3280 /* Rememer if the argument was written to the stack. */
3281 int stack_used_p
= 0;
3282 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
3283 ? len
: mips_abi_regsize (gdbarch
));
3286 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3289 /* Write this portion of the argument to the stack. */
3290 if (argreg
> MIPS_LAST_ARG_REGNUM
3292 || fp_register_arg_p (typecode
, arg_type
))
3294 /* Should shorter than int integer values be
3295 promoted to int before being stored? */
3296 int longword_offset
= 0;
3299 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3301 if (mips_stack_argsize (gdbarch
) == 8
3302 && (typecode
== TYPE_CODE_INT
3303 || typecode
== TYPE_CODE_PTR
3304 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3305 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3310 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3311 paddr_nz (stack_offset
));
3312 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3313 paddr_nz (longword_offset
));
3316 addr
= sp
+ stack_offset
+ longword_offset
;
3321 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3323 for (i
= 0; i
< partial_len
; i
++)
3325 fprintf_unfiltered (gdb_stdlog
, "%02x",
3329 write_memory (addr
, val
, partial_len
);
3332 /* Note!!! This is NOT an else clause. Odd sized
3333 structs may go thru BOTH paths. Floating point
3334 arguments will not. */
3335 /* Write this portion of the argument to a general
3336 purpose register. */
3337 if (argreg
<= MIPS_LAST_ARG_REGNUM
3338 && !fp_register_arg_p (typecode
, arg_type
))
3341 extract_unsigned_integer (val
, partial_len
);
3343 /* A non-floating-point argument being passed in a
3344 general register. If a struct or union, and if
3345 the remaining length is smaller than the register
3346 size, we have to adjust the register value on
3349 It does not seem to be necessary to do the
3350 same for integral types.
3352 cagney/2001-07-23: gdb/179: Also, GCC, when
3353 outputting LE O32 with sizeof (struct) <
3354 mips_abi_regsize(), generates a left shift as
3355 part of storing the argument in a register a
3356 register (the left shift isn't generated when
3357 sizeof (struct) >= mips_abi_regsize()). Since
3358 it is quite possible that this is GCC
3359 contradicting the LE/O32 ABI, GDB has not been
3360 adjusted to accommodate this. Either someone
3361 needs to demonstrate that the LE/O32 ABI
3362 specifies such a left shift OR this new ABI gets
3363 identified as such and GDB gets tweaked
3366 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3367 && partial_len
< mips_abi_regsize (gdbarch
)
3368 && (typecode
== TYPE_CODE_STRUCT
||
3369 typecode
== TYPE_CODE_UNION
))
3370 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
3374 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3377 mips_abi_regsize (gdbarch
)));
3378 write_register (argreg
, regval
);
3385 /* Compute the the offset into the stack at which we
3386 will copy the next parameter.
3388 In N32 (N64?), the stack_offset only needs to be
3389 adjusted when it has been used. */
3392 stack_offset
+= align_up (partial_len
,
3393 mips_stack_argsize (gdbarch
));
3397 fprintf_unfiltered (gdb_stdlog
, "\n");
3400 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3402 /* Return adjusted stack pointer. */
3406 static enum return_value_convention
3407 mips_n32n64_return_value (struct gdbarch
*gdbarch
,
3408 struct type
*type
, struct regcache
*regcache
,
3409 void *readbuf
, const void *writebuf
)
3411 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3412 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3413 || TYPE_CODE (type
) == TYPE_CODE_UNION
3414 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
3415 || TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
3416 return RETURN_VALUE_STRUCT_CONVENTION
;
3417 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3418 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3420 /* A floating-point value belongs in the least significant part
3423 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3424 mips_xfer_register (regcache
,
3425 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
3427 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3428 return RETURN_VALUE_REGISTER_CONVENTION
;
3430 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3431 && TYPE_NFIELDS (type
) <= 2
3432 && TYPE_NFIELDS (type
) >= 1
3433 && ((TYPE_NFIELDS (type
) == 1
3434 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3436 || (TYPE_NFIELDS (type
) == 2
3437 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3439 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
3441 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3443 /* A struct that contains one or two floats. Each value is part
3444 in the least significant part of their floating point
3448 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
3449 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3451 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3454 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3456 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
3457 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3458 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3460 return RETURN_VALUE_REGISTER_CONVENTION
;
3462 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3463 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3465 /* A structure or union. Extract the left justified value,
3466 regardless of the byte order. I.e. DO NOT USE
3470 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3471 offset
< TYPE_LENGTH (type
);
3472 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3474 int xfer
= register_size (current_gdbarch
, regnum
);
3475 if (offset
+ xfer
> TYPE_LENGTH (type
))
3476 xfer
= TYPE_LENGTH (type
) - offset
;
3478 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3479 offset
, xfer
, regnum
);
3480 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3481 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
3483 return RETURN_VALUE_REGISTER_CONVENTION
;
3487 /* A scalar extract each part but least-significant-byte
3491 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3492 offset
< TYPE_LENGTH (type
);
3493 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3495 int xfer
= register_size (current_gdbarch
, regnum
);
3496 if (offset
+ xfer
> TYPE_LENGTH (type
))
3497 xfer
= TYPE_LENGTH (type
) - offset
;
3499 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3500 offset
, xfer
, regnum
);
3501 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3502 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3504 return RETURN_VALUE_REGISTER_CONVENTION
;
3508 /* O32 ABI stuff. */
3511 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3512 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3513 int nargs
, struct value
**args
, CORE_ADDR sp
,
3514 int struct_return
, CORE_ADDR struct_addr
)
3520 int stack_offset
= 0;
3521 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3522 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3524 /* For shared libraries, "t9" needs to point at the function
3526 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3528 /* Set the return address register to point to the entry point of
3529 the program, where a breakpoint lies in wait. */
3530 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3532 /* First ensure that the stack and structure return address (if any)
3533 are properly aligned. The stack has to be at least 64-bit
3534 aligned even on 32-bit machines, because doubles must be 64-bit
3535 aligned. For n32 and n64, stack frames need to be 128-bit
3536 aligned, so we round to this widest known alignment. */
3538 sp
= align_down (sp
, 16);
3539 struct_addr
= align_down (struct_addr
, 16);
3541 /* Now make space on the stack for the args. */
3542 for (argnum
= 0; argnum
< nargs
; argnum
++)
3543 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3544 mips_stack_argsize (gdbarch
));
3545 sp
-= align_up (len
, 16);
3548 fprintf_unfiltered (gdb_stdlog
,
3549 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
3550 paddr_nz (sp
), (long) align_up (len
, 16));
3552 /* Initialize the integer and float register pointers. */
3553 argreg
= MIPS_A0_REGNUM
;
3554 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3556 /* The struct_return pointer occupies the first parameter-passing reg. */
3560 fprintf_unfiltered (gdb_stdlog
,
3561 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
3562 argreg
, paddr_nz (struct_addr
));
3563 write_register (argreg
++, struct_addr
);
3564 stack_offset
+= mips_stack_argsize (gdbarch
);
3567 /* Now load as many as possible of the first arguments into
3568 registers, and push the rest onto the stack. Loop thru args
3569 from first to last. */
3570 for (argnum
= 0; argnum
< nargs
; argnum
++)
3573 struct value
*arg
= args
[argnum
];
3574 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3575 int len
= TYPE_LENGTH (arg_type
);
3576 enum type_code typecode
= TYPE_CODE (arg_type
);
3579 fprintf_unfiltered (gdb_stdlog
,
3580 "mips_o32_push_dummy_call: %d len=%d type=%d",
3581 argnum
+ 1, len
, (int) typecode
);
3583 val
= (char *) VALUE_CONTENTS (arg
);
3585 /* 32-bit ABIs always start floating point arguments in an
3586 even-numbered floating point register. Round the FP register
3587 up before the check to see if there are any FP registers
3588 left. O32/O64 targets also pass the FP in the integer
3589 registers so also round up normal registers. */
3590 if (mips_abi_regsize (gdbarch
) < 8
3591 && fp_register_arg_p (typecode
, arg_type
))
3593 if ((float_argreg
& 1))
3597 /* Floating point arguments passed in registers have to be
3598 treated specially. On 32-bit architectures, doubles
3599 are passed in register pairs; the even register gets
3600 the low word, and the odd register gets the high word.
3601 On O32/O64, the first two floating point arguments are
3602 also copied to general registers, because MIPS16 functions
3603 don't use float registers for arguments. This duplication of
3604 arguments in general registers can't hurt non-MIPS16 functions
3605 because those registers are normally skipped. */
3607 if (fp_register_arg_p (typecode
, arg_type
)
3608 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3610 if (mips_abi_regsize (gdbarch
) < 8 && len
== 8)
3612 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3613 unsigned long regval
;
3615 /* Write the low word of the double to the even register(s). */
3616 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3618 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3619 float_argreg
, phex (regval
, 4));
3620 write_register (float_argreg
++, regval
);
3622 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3623 argreg
, phex (regval
, 4));
3624 write_register (argreg
++, regval
);
3626 /* Write the high word of the double to the odd register(s). */
3627 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3629 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3630 float_argreg
, phex (regval
, 4));
3631 write_register (float_argreg
++, regval
);
3634 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3635 argreg
, phex (regval
, 4));
3636 write_register (argreg
++, regval
);
3640 /* This is a floating point value that fits entirely
3641 in a single register. */
3642 /* On 32 bit ABI's the float_argreg is further adjusted
3643 above to ensure that it is even register aligned. */
3644 LONGEST regval
= extract_unsigned_integer (val
, len
);
3646 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3647 float_argreg
, phex (regval
, len
));
3648 write_register (float_argreg
++, regval
);
3649 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3650 registers for each argument. The below is (my
3651 guess) to ensure that the corresponding integer
3652 register has reserved the same space. */
3654 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3655 argreg
, phex (regval
, len
));
3656 write_register (argreg
, regval
);
3657 argreg
+= (mips_abi_regsize (gdbarch
) == 8) ? 1 : 2;
3659 /* Reserve space for the FP register. */
3660 stack_offset
+= align_up (len
, mips_stack_argsize (gdbarch
));
3664 /* Copy the argument to general registers or the stack in
3665 register-sized pieces. Large arguments are split between
3666 registers and stack. */
3667 /* Note: structs whose size is not a multiple of
3668 mips_abi_regsize() are treated specially: Irix cc passes
3669 them in registers where gcc sometimes puts them on the
3670 stack. For maximum compatibility, we will put them in
3672 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
3673 && (len
% mips_abi_regsize (gdbarch
) != 0));
3674 /* Structures should be aligned to eight bytes (even arg registers)
3675 on MIPS_ABI_O32, if their first member has double precision. */
3676 if (mips_abi_regsize (gdbarch
) < 8
3677 && mips_type_needs_double_align (arg_type
))
3682 /* Note: Floating-point values that didn't fit into an FP
3683 register are only written to memory. */
3686 /* Remember if the argument was written to the stack. */
3687 int stack_used_p
= 0;
3688 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
3689 ? len
: mips_abi_regsize (gdbarch
));
3692 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3695 /* Write this portion of the argument to the stack. */
3696 if (argreg
> MIPS_LAST_ARG_REGNUM
3698 || fp_register_arg_p (typecode
, arg_type
))
3700 /* Should shorter than int integer values be
3701 promoted to int before being stored? */
3702 int longword_offset
= 0;
3705 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3707 if (mips_stack_argsize (gdbarch
) == 8
3708 && (typecode
== TYPE_CODE_INT
3709 || typecode
== TYPE_CODE_PTR
3710 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3711 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3716 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3717 paddr_nz (stack_offset
));
3718 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3719 paddr_nz (longword_offset
));
3722 addr
= sp
+ stack_offset
+ longword_offset
;
3727 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3729 for (i
= 0; i
< partial_len
; i
++)
3731 fprintf_unfiltered (gdb_stdlog
, "%02x",
3735 write_memory (addr
, val
, partial_len
);
3738 /* Note!!! This is NOT an else clause. Odd sized
3739 structs may go thru BOTH paths. Floating point
3740 arguments will not. */
3741 /* Write this portion of the argument to a general
3742 purpose register. */
3743 if (argreg
<= MIPS_LAST_ARG_REGNUM
3744 && !fp_register_arg_p (typecode
, arg_type
))
3746 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3747 /* Value may need to be sign extended, because
3748 mips_isa_regsize() != mips_abi_regsize(). */
3750 /* A non-floating-point argument being passed in a
3751 general register. If a struct or union, and if
3752 the remaining length is smaller than the register
3753 size, we have to adjust the register value on
3756 It does not seem to be necessary to do the
3757 same for integral types.
3759 Also don't do this adjustment on O64 binaries.
3761 cagney/2001-07-23: gdb/179: Also, GCC, when
3762 outputting LE O32 with sizeof (struct) <
3763 mips_abi_regsize(), generates a left shift as
3764 part of storing the argument in a register a
3765 register (the left shift isn't generated when
3766 sizeof (struct) >= mips_abi_regsize()). Since
3767 it is quite possible that this is GCC
3768 contradicting the LE/O32 ABI, GDB has not been
3769 adjusted to accommodate this. Either someone
3770 needs to demonstrate that the LE/O32 ABI
3771 specifies such a left shift OR this new ABI gets
3772 identified as such and GDB gets tweaked
3775 if (mips_abi_regsize (gdbarch
) < 8
3776 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3777 && partial_len
< mips_abi_regsize (gdbarch
)
3778 && (typecode
== TYPE_CODE_STRUCT
||
3779 typecode
== TYPE_CODE_UNION
))
3780 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
3784 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3787 mips_abi_regsize (gdbarch
)));
3788 write_register (argreg
, regval
);
3791 /* Prevent subsequent floating point arguments from
3792 being passed in floating point registers. */
3793 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3799 /* Compute the the offset into the stack at which we
3800 will copy the next parameter.
3802 In older ABIs, the caller reserved space for
3803 registers that contained arguments. This was loosely
3804 refered to as their "home". Consequently, space is
3805 always allocated. */
3807 stack_offset
+= align_up (partial_len
,
3808 mips_stack_argsize (gdbarch
));
3812 fprintf_unfiltered (gdb_stdlog
, "\n");
3815 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3817 /* Return adjusted stack pointer. */
3821 static enum return_value_convention
3822 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
3823 struct regcache
*regcache
,
3824 void *readbuf
, const void *writebuf
)
3826 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3828 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3829 || TYPE_CODE (type
) == TYPE_CODE_UNION
3830 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3831 return RETURN_VALUE_STRUCT_CONVENTION
;
3832 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3833 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3835 /* A single-precision floating-point value. It fits in the
3836 least significant part of FP0. */
3838 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3839 mips_xfer_register (regcache
,
3840 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
3842 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3843 return RETURN_VALUE_REGISTER_CONVENTION
;
3845 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3846 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3848 /* A double-precision floating-point value. The most
3849 significant part goes in FP1, and the least significant in
3852 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
3853 switch (TARGET_BYTE_ORDER
)
3855 case BFD_ENDIAN_LITTLE
:
3856 mips_xfer_register (regcache
,
3857 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3858 0, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3859 mips_xfer_register (regcache
,
3860 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3861 1, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
3863 case BFD_ENDIAN_BIG
:
3864 mips_xfer_register (regcache
,
3865 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3866 1, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3867 mips_xfer_register (regcache
,
3868 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3869 0, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
3872 internal_error (__FILE__
, __LINE__
, "bad switch");
3874 return RETURN_VALUE_REGISTER_CONVENTION
;
3877 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3878 && TYPE_NFIELDS (type
) <= 2
3879 && TYPE_NFIELDS (type
) >= 1
3880 && ((TYPE_NFIELDS (type
) == 1
3881 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3883 || (TYPE_NFIELDS (type
) == 2
3884 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3886 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
3888 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3890 /* A struct that contains one or two floats. Each value is part
3891 in the least significant part of their floating point
3893 bfd_byte reg
[MAX_REGISTER_SIZE
];
3896 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
3897 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3899 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3902 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3904 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
3905 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3906 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3908 return RETURN_VALUE_REGISTER_CONVENTION
;
3912 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3913 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3915 /* A structure or union. Extract the left justified value,
3916 regardless of the byte order. I.e. DO NOT USE
3920 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3921 offset
< TYPE_LENGTH (type
);
3922 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3924 int xfer
= register_size (current_gdbarch
, regnum
);
3925 if (offset
+ xfer
> TYPE_LENGTH (type
))
3926 xfer
= TYPE_LENGTH (type
) - offset
;
3928 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3929 offset
, xfer
, regnum
);
3930 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3931 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
3933 return RETURN_VALUE_REGISTER_CONVENTION
;
3938 /* A scalar extract each part but least-significant-byte
3939 justified. o32 thinks registers are 4 byte, regardless of
3940 the ISA. mips_stack_argsize controls this. */
3943 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3944 offset
< TYPE_LENGTH (type
);
3945 offset
+= mips_stack_argsize (gdbarch
), regnum
++)
3947 int xfer
= mips_stack_argsize (gdbarch
);
3948 if (offset
+ xfer
> TYPE_LENGTH (type
))
3949 xfer
= TYPE_LENGTH (type
) - offset
;
3951 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3952 offset
, xfer
, regnum
);
3953 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3954 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3956 return RETURN_VALUE_REGISTER_CONVENTION
;
3960 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
3964 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3965 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3967 struct value
**args
, CORE_ADDR sp
,
3968 int struct_return
, CORE_ADDR struct_addr
)
3974 int stack_offset
= 0;
3975 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3976 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3978 /* For shared libraries, "t9" needs to point at the function
3980 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3982 /* Set the return address register to point to the entry point of
3983 the program, where a breakpoint lies in wait. */
3984 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3986 /* First ensure that the stack and structure return address (if any)
3987 are properly aligned. The stack has to be at least 64-bit
3988 aligned even on 32-bit machines, because doubles must be 64-bit
3989 aligned. For n32 and n64, stack frames need to be 128-bit
3990 aligned, so we round to this widest known alignment. */
3992 sp
= align_down (sp
, 16);
3993 struct_addr
= align_down (struct_addr
, 16);
3995 /* Now make space on the stack for the args. */
3996 for (argnum
= 0; argnum
< nargs
; argnum
++)
3997 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3998 mips_stack_argsize (gdbarch
));
3999 sp
-= align_up (len
, 16);
4002 fprintf_unfiltered (gdb_stdlog
,
4003 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
4004 paddr_nz (sp
), (long) align_up (len
, 16));
4006 /* Initialize the integer and float register pointers. */
4007 argreg
= MIPS_A0_REGNUM
;
4008 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
4010 /* The struct_return pointer occupies the first parameter-passing reg. */
4014 fprintf_unfiltered (gdb_stdlog
,
4015 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
4016 argreg
, paddr_nz (struct_addr
));
4017 write_register (argreg
++, struct_addr
);
4018 stack_offset
+= mips_stack_argsize (gdbarch
);
4021 /* Now load as many as possible of the first arguments into
4022 registers, and push the rest onto the stack. Loop thru args
4023 from first to last. */
4024 for (argnum
= 0; argnum
< nargs
; argnum
++)
4027 struct value
*arg
= args
[argnum
];
4028 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
4029 int len
= TYPE_LENGTH (arg_type
);
4030 enum type_code typecode
= TYPE_CODE (arg_type
);
4033 fprintf_unfiltered (gdb_stdlog
,
4034 "mips_o64_push_dummy_call: %d len=%d type=%d",
4035 argnum
+ 1, len
, (int) typecode
);
4037 val
= (char *) VALUE_CONTENTS (arg
);
4039 /* 32-bit ABIs always start floating point arguments in an
4040 even-numbered floating point register. Round the FP register
4041 up before the check to see if there are any FP registers
4042 left. O32/O64 targets also pass the FP in the integer
4043 registers so also round up normal registers. */
4044 if (mips_abi_regsize (gdbarch
) < 8
4045 && fp_register_arg_p (typecode
, arg_type
))
4047 if ((float_argreg
& 1))
4051 /* Floating point arguments passed in registers have to be
4052 treated specially. On 32-bit architectures, doubles
4053 are passed in register pairs; the even register gets
4054 the low word, and the odd register gets the high word.
4055 On O32/O64, the first two floating point arguments are
4056 also copied to general registers, because MIPS16 functions
4057 don't use float registers for arguments. This duplication of
4058 arguments in general registers can't hurt non-MIPS16 functions
4059 because those registers are normally skipped. */
4061 if (fp_register_arg_p (typecode
, arg_type
)
4062 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
4064 if (mips_abi_regsize (gdbarch
) < 8 && len
== 8)
4066 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
4067 unsigned long regval
;
4069 /* Write the low word of the double to the even register(s). */
4070 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
4072 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4073 float_argreg
, phex (regval
, 4));
4074 write_register (float_argreg
++, regval
);
4076 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4077 argreg
, phex (regval
, 4));
4078 write_register (argreg
++, regval
);
4080 /* Write the high word of the double to the odd register(s). */
4081 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
4083 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4084 float_argreg
, phex (regval
, 4));
4085 write_register (float_argreg
++, regval
);
4088 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4089 argreg
, phex (regval
, 4));
4090 write_register (argreg
++, regval
);
4094 /* This is a floating point value that fits entirely
4095 in a single register. */
4096 /* On 32 bit ABI's the float_argreg is further adjusted
4097 above to ensure that it is even register aligned. */
4098 LONGEST regval
= extract_unsigned_integer (val
, len
);
4100 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4101 float_argreg
, phex (regval
, len
));
4102 write_register (float_argreg
++, regval
);
4103 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
4104 registers for each argument. The below is (my
4105 guess) to ensure that the corresponding integer
4106 register has reserved the same space. */
4108 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4109 argreg
, phex (regval
, len
));
4110 write_register (argreg
, regval
);
4111 argreg
+= (mips_abi_regsize (gdbarch
) == 8) ? 1 : 2;
4113 /* Reserve space for the FP register. */
4114 stack_offset
+= align_up (len
, mips_stack_argsize (gdbarch
));
4118 /* Copy the argument to general registers or the stack in
4119 register-sized pieces. Large arguments are split between
4120 registers and stack. */
4121 /* Note: structs whose size is not a multiple of
4122 mips_abi_regsize() are treated specially: Irix cc passes
4123 them in registers where gcc sometimes puts them on the
4124 stack. For maximum compatibility, we will put them in
4126 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
4127 && (len
% mips_abi_regsize (gdbarch
) != 0));
4128 /* Structures should be aligned to eight bytes (even arg registers)
4129 on MIPS_ABI_O32, if their first member has double precision. */
4130 if (mips_abi_regsize (gdbarch
) < 8
4131 && mips_type_needs_double_align (arg_type
))
4136 /* Note: Floating-point values that didn't fit into an FP
4137 register are only written to memory. */
4140 /* Remember if the argument was written to the stack. */
4141 int stack_used_p
= 0;
4142 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
4143 ? len
: mips_abi_regsize (gdbarch
));
4146 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4149 /* Write this portion of the argument to the stack. */
4150 if (argreg
> MIPS_LAST_ARG_REGNUM
4152 || fp_register_arg_p (typecode
, arg_type
))
4154 /* Should shorter than int integer values be
4155 promoted to int before being stored? */
4156 int longword_offset
= 0;
4159 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4161 if (mips_stack_argsize (gdbarch
) == 8
4162 && (typecode
== TYPE_CODE_INT
4163 || typecode
== TYPE_CODE_PTR
4164 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
4165 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
4170 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
4171 paddr_nz (stack_offset
));
4172 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
4173 paddr_nz (longword_offset
));
4176 addr
= sp
+ stack_offset
+ longword_offset
;
4181 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
4183 for (i
= 0; i
< partial_len
; i
++)
4185 fprintf_unfiltered (gdb_stdlog
, "%02x",
4189 write_memory (addr
, val
, partial_len
);
4192 /* Note!!! This is NOT an else clause. Odd sized
4193 structs may go thru BOTH paths. Floating point
4194 arguments will not. */
4195 /* Write this portion of the argument to a general
4196 purpose register. */
4197 if (argreg
<= MIPS_LAST_ARG_REGNUM
4198 && !fp_register_arg_p (typecode
, arg_type
))
4200 LONGEST regval
= extract_signed_integer (val
, partial_len
);
4201 /* Value may need to be sign extended, because
4202 mips_isa_regsize() != mips_abi_regsize(). */
4204 /* A non-floating-point argument being passed in a
4205 general register. If a struct or union, and if
4206 the remaining length is smaller than the register
4207 size, we have to adjust the register value on
4210 It does not seem to be necessary to do the
4211 same for integral types.
4213 Also don't do this adjustment on O64 binaries.
4215 cagney/2001-07-23: gdb/179: Also, GCC, when
4216 outputting LE O32 with sizeof (struct) <
4217 mips_abi_regsize(), generates a left shift as
4218 part of storing the argument in a register a
4219 register (the left shift isn't generated when
4220 sizeof (struct) >= mips_abi_regsize()). Since
4221 it is quite possible that this is GCC
4222 contradicting the LE/O32 ABI, GDB has not been
4223 adjusted to accommodate this. Either someone
4224 needs to demonstrate that the LE/O32 ABI
4225 specifies such a left shift OR this new ABI gets
4226 identified as such and GDB gets tweaked
4229 if (mips_abi_regsize (gdbarch
) < 8
4230 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4231 && partial_len
< mips_abi_regsize (gdbarch
)
4232 && (typecode
== TYPE_CODE_STRUCT
||
4233 typecode
== TYPE_CODE_UNION
))
4234 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
4238 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4241 mips_abi_regsize (gdbarch
)));
4242 write_register (argreg
, regval
);
4245 /* Prevent subsequent floating point arguments from
4246 being passed in floating point registers. */
4247 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
4253 /* Compute the the offset into the stack at which we
4254 will copy the next parameter.
4256 In older ABIs, the caller reserved space for
4257 registers that contained arguments. This was loosely
4258 refered to as their "home". Consequently, space is
4259 always allocated. */
4261 stack_offset
+= align_up (partial_len
,
4262 mips_stack_argsize (gdbarch
));
4266 fprintf_unfiltered (gdb_stdlog
, "\n");
4269 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4271 /* Return adjusted stack pointer. */
4275 static enum return_value_convention
4276 mips_o64_return_value (struct gdbarch
*gdbarch
,
4277 struct type
*type
, struct regcache
*regcache
,
4278 void *readbuf
, const void *writebuf
)
4280 return RETURN_VALUE_STRUCT_CONVENTION
;
4283 /* Floating point register management.
4285 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
4286 64bit operations, these early MIPS cpus treat fp register pairs
4287 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
4288 registers and offer a compatibility mode that emulates the MIPS2 fp
4289 model. When operating in MIPS2 fp compat mode, later cpu's split
4290 double precision floats into two 32-bit chunks and store them in
4291 consecutive fp regs. To display 64-bit floats stored in this
4292 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
4293 Throw in user-configurable endianness and you have a real mess.
4295 The way this works is:
4296 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4297 double-precision value will be split across two logical registers.
4298 The lower-numbered logical register will hold the low-order bits,
4299 regardless of the processor's endianness.
4300 - If we are on a 64-bit processor, and we are looking for a
4301 single-precision value, it will be in the low ordered bits
4302 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4303 save slot in memory.
4304 - If we are in 64-bit mode, everything is straightforward.
4306 Note that this code only deals with "live" registers at the top of the
4307 stack. We will attempt to deal with saved registers later, when
4308 the raw/cooked register interface is in place. (We need a general
4309 interface that can deal with dynamic saved register sizes -- fp
4310 regs could be 32 bits wide in one frame and 64 on the frame above
4313 static struct type
*
4314 mips_float_register_type (void)
4316 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4317 return builtin_type_ieee_single_big
;
4319 return builtin_type_ieee_single_little
;
4322 static struct type
*
4323 mips_double_register_type (void)
4325 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4326 return builtin_type_ieee_double_big
;
4328 return builtin_type_ieee_double_little
;
4331 /* Copy a 32-bit single-precision value from the current frame
4332 into rare_buffer. */
4335 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
4338 int raw_size
= register_size (current_gdbarch
, regno
);
4339 char *raw_buffer
= alloca (raw_size
);
4341 if (!frame_register_read (frame
, regno
, raw_buffer
))
4342 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
4345 /* We have a 64-bit value for this register. Find the low-order
4349 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4354 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
4358 memcpy (rare_buffer
, raw_buffer
, 4);
4362 /* Copy a 64-bit double-precision value from the current frame into
4363 rare_buffer. This may include getting half of it from the next
4367 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
4370 int raw_size
= register_size (current_gdbarch
, regno
);
4372 if (raw_size
== 8 && !mips2_fp_compat ())
4374 /* We have a 64-bit value for this register, and we should use
4376 if (!frame_register_read (frame
, regno
, rare_buffer
))
4377 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
4381 if ((regno
- mips_regnum (current_gdbarch
)->fp0
) & 1)
4382 internal_error (__FILE__
, __LINE__
,
4383 "mips_read_fp_register_double: bad access to "
4384 "odd-numbered FP register");
4386 /* mips_read_fp_register_single will find the correct 32 bits from
4388 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4390 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
4391 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
4395 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
4396 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4402 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4404 { /* do values for FP (float) regs */
4406 double doub
, flt1
; /* doubles extracted from raw hex data */
4410 (char *) alloca (2 *
4411 register_size (current_gdbarch
,
4412 mips_regnum (current_gdbarch
)->fp0
));
4414 fprintf_filtered (file
, "%s:", REGISTER_NAME (regnum
));
4415 fprintf_filtered (file
, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum
)),
4418 if (register_size (current_gdbarch
, regnum
) == 4 || mips2_fp_compat ())
4420 /* 4-byte registers: Print hex and floating. Also print even
4421 numbered registers as doubles. */
4422 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4423 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4425 print_scalar_formatted (raw_buffer
, builtin_type_uint32
, 'x', 'w',
4428 fprintf_filtered (file
, " flt: ");
4430 fprintf_filtered (file
, " <invalid float> ");
4432 fprintf_filtered (file
, "%-17.9g", flt1
);
4434 if (regnum
% 2 == 0)
4436 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4437 doub
= unpack_double (mips_double_register_type (), raw_buffer
,
4440 fprintf_filtered (file
, " dbl: ");
4442 fprintf_filtered (file
, "<invalid double>");
4444 fprintf_filtered (file
, "%-24.17g", doub
);
4449 /* Eight byte registers: print each one as hex, float and double. */
4450 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4451 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4453 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4454 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv2
);
4457 print_scalar_formatted (raw_buffer
, builtin_type_uint64
, 'x', 'g',
4460 fprintf_filtered (file
, " flt: ");
4462 fprintf_filtered (file
, "<invalid float>");
4464 fprintf_filtered (file
, "%-17.9g", flt1
);
4466 fprintf_filtered (file
, " dbl: ");
4468 fprintf_filtered (file
, "<invalid double>");
4470 fprintf_filtered (file
, "%-24.17g", doub
);
4475 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4476 int regnum
, int all
)
4478 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4479 char raw_buffer
[MAX_REGISTER_SIZE
];
4482 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4484 mips_print_fp_register (file
, frame
, regnum
);
4488 /* Get the data in raw format. */
4489 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4491 fprintf_filtered (file
, "%s: [Invalid]", REGISTER_NAME (regnum
));
4495 fputs_filtered (REGISTER_NAME (regnum
), file
);
4497 /* The problem with printing numeric register names (r26, etc.) is that
4498 the user can't use them on input. Probably the best solution is to
4499 fix it so that either the numeric or the funky (a2, etc.) names
4500 are accepted on input. */
4501 if (regnum
< MIPS_NUMREGS
)
4502 fprintf_filtered (file
, "(r%d): ", regnum
);
4504 fprintf_filtered (file
, ": ");
4506 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4508 register_size (current_gdbarch
,
4509 regnum
) - register_size (current_gdbarch
, regnum
);
4513 print_scalar_formatted (raw_buffer
+ offset
,
4514 gdbarch_register_type (gdbarch
, regnum
), 'x', 0,
4518 /* Replacement for generic do_registers_info.
4519 Print regs in pretty columns. */
4522 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4525 fprintf_filtered (file
, " ");
4526 mips_print_fp_register (file
, frame
, regnum
);
4527 fprintf_filtered (file
, "\n");
4532 /* Print a row's worth of GP (int) registers, with name labels above */
4535 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4538 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4539 /* do values for GP (int) regs */
4540 char raw_buffer
[MAX_REGISTER_SIZE
];
4541 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols per row */
4545 /* For GP registers, we print a separate row of names above the vals */
4546 fprintf_filtered (file
, " ");
4547 for (col
= 0, regnum
= start_regnum
;
4548 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
4550 if (*REGISTER_NAME (regnum
) == '\0')
4551 continue; /* unused register */
4552 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
4554 break; /* end the row: reached FP register */
4555 fprintf_filtered (file
,
4556 mips_abi_regsize (current_gdbarch
) == 8 ? "%17s" : "%9s",
4557 REGISTER_NAME (regnum
));
4560 /* print the R0 to R31 names */
4561 if ((start_regnum
% NUM_REGS
) < MIPS_NUMREGS
)
4562 fprintf_filtered (file
, "\n R%-4d", start_regnum
% NUM_REGS
);
4564 fprintf_filtered (file
, "\n ");
4566 /* now print the values in hex, 4 or 8 to the row */
4567 for (col
= 0, regnum
= start_regnum
;
4568 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
4570 if (*REGISTER_NAME (regnum
) == '\0')
4571 continue; /* unused register */
4572 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
4574 break; /* end row: reached FP register */
4575 /* OK: get the data in raw format. */
4576 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4577 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
4578 /* pad small registers */
4580 byte
< (mips_abi_regsize (current_gdbarch
)
4581 - register_size (current_gdbarch
, regnum
)); byte
++)
4582 printf_filtered (" ");
4583 /* Now print the register value in hex, endian order. */
4584 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4586 register_size (current_gdbarch
,
4587 regnum
) - register_size (current_gdbarch
, regnum
);
4588 byte
< register_size (current_gdbarch
, regnum
); byte
++)
4589 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
4591 for (byte
= register_size (current_gdbarch
, regnum
) - 1;
4593 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
4594 fprintf_filtered (file
, " ");
4597 if (col
> 0) /* ie. if we actually printed anything... */
4598 fprintf_filtered (file
, "\n");
4603 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4606 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4607 struct frame_info
*frame
, int regnum
, int all
)
4609 if (regnum
!= -1) /* do one specified register */
4611 gdb_assert (regnum
>= NUM_REGS
);
4612 if (*(REGISTER_NAME (regnum
)) == '\0')
4613 error ("Not a valid register for the current processor type");
4615 mips_print_register (file
, frame
, regnum
, 0);
4616 fprintf_filtered (file
, "\n");
4619 /* do all (or most) registers */
4622 while (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
4624 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
4627 if (all
) /* true for "INFO ALL-REGISTERS" command */
4628 regnum
= print_fp_register_row (file
, frame
, regnum
);
4630 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
4633 regnum
= print_gp_register_row (file
, frame
, regnum
);
4638 /* Is this a branch with a delay slot? */
4641 is_delayed (unsigned long insn
)
4644 for (i
= 0; i
< NUMOPCODES
; ++i
)
4645 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4646 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4648 return (i
< NUMOPCODES
4649 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4650 | INSN_COND_BRANCH_DELAY
4651 | INSN_COND_BRANCH_LIKELY
)));
4655 mips_step_skips_delay (CORE_ADDR pc
)
4657 char buf
[MIPS32_INSN_SIZE
];
4659 /* There is no branch delay slot on MIPS16. */
4660 if (mips_pc_is_mips16 (pc
))
4663 if (target_read_memory (pc
, buf
, sizeof buf
) != 0)
4664 /* If error reading memory, guess that it is not a delayed branch. */
4666 return is_delayed (extract_unsigned_integer (buf
, sizeof buf
));
4669 /* To skip prologues, I use this predicate. Returns either PC itself
4670 if the code at PC does not look like a function prologue; otherwise
4671 returns an address that (if we're lucky) follows the prologue. If
4672 LENIENT, then we must skip everything which is involved in setting
4673 up the frame (it's OK to skip more, just so long as we don't skip
4674 anything which might clobber the registers which are being saved.
4675 We must skip more in the case where part of the prologue is in the
4676 delay slot of a non-prologue instruction). */
4679 mips_skip_prologue (CORE_ADDR pc
)
4682 CORE_ADDR func_addr
;
4684 /* See if we can determine the end of the prologue via the symbol table.
4685 If so, then return either PC, or the PC after the prologue, whichever
4687 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
4689 CORE_ADDR post_prologue_pc
= skip_prologue_using_sal (func_addr
);
4690 if (post_prologue_pc
!= 0)
4691 return max (pc
, post_prologue_pc
);
4694 /* Can't determine prologue from the symbol table, need to examine
4697 /* Find an upper limit on the function prologue using the debug
4698 information. If the debug information could not be used to provide
4699 that bound, then use an arbitrary large number as the upper bound. */
4700 limit_pc
= skip_prologue_using_sal (pc
);
4702 limit_pc
= pc
+ 100; /* Magic. */
4704 if (mips_pc_is_mips16 (pc
))
4705 return mips16_scan_prologue (pc
, limit_pc
, NULL
, NULL
);
4707 return mips32_scan_prologue (pc
, limit_pc
, NULL
, NULL
);
4710 /* Root of all "set mips "/"show mips " commands. This will eventually be
4711 used for all MIPS-specific commands. */
4714 show_mips_command (char *args
, int from_tty
)
4716 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
4720 set_mips_command (char *args
, int from_tty
)
4723 ("\"set mips\" must be followed by an appropriate subcommand.\n");
4724 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
4727 /* Commands to show/set the MIPS FPU type. */
4730 show_mipsfpu_command (char *args
, int from_tty
)
4733 switch (MIPS_FPU_TYPE
)
4735 case MIPS_FPU_SINGLE
:
4736 fpu
= "single-precision";
4738 case MIPS_FPU_DOUBLE
:
4739 fpu
= "double-precision";
4742 fpu
= "absent (none)";
4745 internal_error (__FILE__
, __LINE__
, "bad switch");
4747 if (mips_fpu_type_auto
)
4749 ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
4753 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
4758 set_mipsfpu_command (char *args
, int from_tty
)
4761 ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
4762 show_mipsfpu_command (args
, from_tty
);
4766 set_mipsfpu_single_command (char *args
, int from_tty
)
4768 struct gdbarch_info info
;
4769 gdbarch_info_init (&info
);
4770 mips_fpu_type
= MIPS_FPU_SINGLE
;
4771 mips_fpu_type_auto
= 0;
4772 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4773 instead of relying on globals. Doing that would let generic code
4774 handle the search for this specific architecture. */
4775 if (!gdbarch_update_p (info
))
4776 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
4780 set_mipsfpu_double_command (char *args
, int from_tty
)
4782 struct gdbarch_info info
;
4783 gdbarch_info_init (&info
);
4784 mips_fpu_type
= MIPS_FPU_DOUBLE
;
4785 mips_fpu_type_auto
= 0;
4786 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4787 instead of relying on globals. Doing that would let generic code
4788 handle the search for this specific architecture. */
4789 if (!gdbarch_update_p (info
))
4790 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
4794 set_mipsfpu_none_command (char *args
, int from_tty
)
4796 struct gdbarch_info info
;
4797 gdbarch_info_init (&info
);
4798 mips_fpu_type
= MIPS_FPU_NONE
;
4799 mips_fpu_type_auto
= 0;
4800 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4801 instead of relying on globals. Doing that would let generic code
4802 handle the search for this specific architecture. */
4803 if (!gdbarch_update_p (info
))
4804 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
4808 set_mipsfpu_auto_command (char *args
, int from_tty
)
4810 mips_fpu_type_auto
= 1;
4813 /* Attempt to identify the particular processor model by reading the
4814 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
4815 the relevant processor still exists (it dates back to '94) and
4816 secondly this is not the way to do this. The processor type should
4817 be set by forcing an architecture change. */
4820 deprecated_mips_set_processor_regs_hack (void)
4822 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4825 prid
= read_register (PRID_REGNUM
);
4827 if ((prid
& ~0xf) == 0x700)
4828 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
4831 /* Just like reinit_frame_cache, but with the right arguments to be
4832 callable as an sfunc. */
4835 reinit_frame_cache_sfunc (char *args
, int from_tty
,
4836 struct cmd_list_element
*c
)
4838 reinit_frame_cache ();
4842 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
4844 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4845 mips_extra_func_info_t proc_desc
;
4847 /* Search for the function containing this address. Set the low bit
4848 of the address when searching, in case we were given an even address
4849 that is the start of a 16-bit function. If we didn't do this,
4850 the search would fail because the symbol table says the function
4851 starts at an odd address, i.e. 1 byte past the given address. */
4852 memaddr
= ADDR_BITS_REMOVE (memaddr
);
4853 proc_desc
= non_heuristic_proc_desc (make_mips16_addr (memaddr
), NULL
);
4855 /* Make an attempt to determine if this is a 16-bit function. If
4856 the procedure descriptor exists and the address therein is odd,
4857 it's definitely a 16-bit function. Otherwise, we have to just
4858 guess that if the address passed in is odd, it's 16-bits. */
4859 /* FIXME: cagney/2003-06-26: Is this even necessary? The
4860 disassembler needs to be able to locally determine the ISA, and
4861 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
4865 if (mips_pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
4866 info
->mach
= bfd_mach_mips16
;
4870 if (mips_pc_is_mips16 (memaddr
))
4871 info
->mach
= bfd_mach_mips16
;
4874 /* Round down the instruction address to the appropriate boundary. */
4875 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
4877 /* Set the disassembler options. */
4878 if (tdep
->mips_abi
== MIPS_ABI_N32
|| tdep
->mips_abi
== MIPS_ABI_N64
)
4880 /* Set up the disassembler info, so that we get the right
4881 register names from libopcodes. */
4882 if (tdep
->mips_abi
== MIPS_ABI_N32
)
4883 info
->disassembler_options
= "gpr-names=n32";
4885 info
->disassembler_options
= "gpr-names=64";
4886 info
->flavour
= bfd_target_elf_flavour
;
4889 /* This string is not recognized explicitly by the disassembler,
4890 but it tells the disassembler to not try to guess the ABI from
4891 the bfd elf headers, such that, if the user overrides the ABI
4892 of a program linked as NewABI, the disassembly will follow the
4893 register naming conventions specified by the user. */
4894 info
->disassembler_options
= "gpr-names=32";
4896 /* Call the appropriate disassembler based on the target endian-ness. */
4897 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4898 return print_insn_big_mips (memaddr
, info
);
4900 return print_insn_little_mips (memaddr
, info
);
4903 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
4904 counter value to determine whether a 16- or 32-bit breakpoint should be
4905 used. It returns a pointer to a string of bytes that encode a breakpoint
4906 instruction, stores the length of the string to *lenptr, and adjusts pc
4907 (if necessary) to point to the actual memory location where the
4908 breakpoint should be inserted. */
4910 static const unsigned char *
4911 mips_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
4913 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4915 if (mips_pc_is_mips16 (*pcptr
))
4917 static unsigned char mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
4918 *pcptr
= unmake_mips16_addr (*pcptr
);
4919 *lenptr
= sizeof (mips16_big_breakpoint
);
4920 return mips16_big_breakpoint
;
4924 /* The IDT board uses an unusual breakpoint value, and
4925 sometimes gets confused when it sees the usual MIPS
4926 breakpoint instruction. */
4927 static unsigned char big_breakpoint
[] = { 0, 0x5, 0, 0xd };
4928 static unsigned char pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
4929 static unsigned char idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
4931 *lenptr
= sizeof (big_breakpoint
);
4933 if (strcmp (target_shortname
, "mips") == 0)
4934 return idt_big_breakpoint
;
4935 else if (strcmp (target_shortname
, "ddb") == 0
4936 || strcmp (target_shortname
, "pmon") == 0
4937 || strcmp (target_shortname
, "lsi") == 0)
4938 return pmon_big_breakpoint
;
4940 return big_breakpoint
;
4945 if (mips_pc_is_mips16 (*pcptr
))
4947 static unsigned char mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
4948 *pcptr
= unmake_mips16_addr (*pcptr
);
4949 *lenptr
= sizeof (mips16_little_breakpoint
);
4950 return mips16_little_breakpoint
;
4954 static unsigned char little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
4955 static unsigned char pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
4956 static unsigned char idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
4958 *lenptr
= sizeof (little_breakpoint
);
4960 if (strcmp (target_shortname
, "mips") == 0)
4961 return idt_little_breakpoint
;
4962 else if (strcmp (target_shortname
, "ddb") == 0
4963 || strcmp (target_shortname
, "pmon") == 0
4964 || strcmp (target_shortname
, "lsi") == 0)
4965 return pmon_little_breakpoint
;
4967 return little_breakpoint
;
4972 /* If PC is in a mips16 call or return stub, return the address of the target
4973 PC, which is either the callee or the caller. There are several
4974 cases which must be handled:
4976 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
4977 target PC is in $31 ($ra).
4978 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
4979 and the target PC is in $2.
4980 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4981 before the jal instruction, this is effectively a call stub
4982 and the the target PC is in $2. Otherwise this is effectively
4983 a return stub and the target PC is in $18.
4985 See the source code for the stubs in gcc/config/mips/mips16.S for
4989 mips_skip_trampoline_code (CORE_ADDR pc
)
4992 CORE_ADDR start_addr
;
4994 /* Find the starting address and name of the function containing the PC. */
4995 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
4998 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
4999 target PC is in $31 ($ra). */
5000 if (strcmp (name
, "__mips16_ret_sf") == 0
5001 || strcmp (name
, "__mips16_ret_df") == 0)
5002 return read_signed_register (MIPS_RA_REGNUM
);
5004 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5006 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5007 and the target PC is in $2. */
5008 if (name
[19] >= '0' && name
[19] <= '9')
5009 return read_signed_register (2);
5011 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5012 before the jal instruction, this is effectively a call stub
5013 and the the target PC is in $2. Otherwise this is effectively
5014 a return stub and the target PC is in $18. */
5015 else if (name
[19] == 's' || name
[19] == 'd')
5017 if (pc
== start_addr
)
5019 /* Check if the target of the stub is a compiler-generated
5020 stub. Such a stub for a function bar might have a name
5021 like __fn_stub_bar, and might look like this:
5026 la $1,bar (becomes a lui/addiu pair)
5028 So scan down to the lui/addi and extract the target
5029 address from those two instructions. */
5031 CORE_ADDR target_pc
= read_signed_register (2);
5035 /* See if the name of the target function is __fn_stub_*. */
5036 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) ==
5039 if (strncmp (name
, "__fn_stub_", 10) != 0
5040 && strcmp (name
, "etext") != 0
5041 && strcmp (name
, "_etext") != 0)
5044 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5045 The limit on the search is arbitrarily set to 20
5046 instructions. FIXME. */
5047 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS32_INSN_SIZE
)
5049 inst
= mips_fetch_instruction (target_pc
);
5050 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
5051 pc
= (inst
<< 16) & 0xffff0000; /* high word */
5052 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
5053 return pc
| (inst
& 0xffff); /* low word */
5056 /* Couldn't find the lui/addui pair, so return stub address. */
5060 /* This is the 'return' part of a call stub. The return
5061 address is in $r18. */
5062 return read_signed_register (18);
5065 return 0; /* not a stub */
5069 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
5070 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
5073 mips_in_call_stub (CORE_ADDR pc
, char *name
)
5075 CORE_ADDR start_addr
;
5077 /* Find the starting address of the function containing the PC. If the
5078 caller didn't give us a name, look it up at the same time. */
5079 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) ==
5083 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5085 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
5086 if (name
[19] >= '0' && name
[19] <= '9')
5088 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5089 before the jal instruction, this is effectively a call stub. */
5090 else if (name
[19] == 's' || name
[19] == 'd')
5091 return pc
== start_addr
;
5094 return 0; /* not a stub */
5098 /* Return non-zero if the PC is inside a return thunk (aka stub or
5102 mips_in_solib_return_trampoline (CORE_ADDR pc
, char *name
)
5104 CORE_ADDR start_addr
;
5106 /* Find the starting address of the function containing the PC. */
5107 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
5110 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
5111 if (strcmp (name
, "__mips16_ret_sf") == 0
5112 || strcmp (name
, "__mips16_ret_df") == 0)
5115 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
5116 i.e. after the jal instruction, this is effectively a return stub. */
5117 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
5118 && (name
[19] == 's' || name
[19] == 'd') && pc
!= start_addr
)
5121 return 0; /* not a stub */
5125 /* Return non-zero if the PC is in a library helper function that
5126 should be ignored. This implements the
5127 DEPRECATED_IGNORE_HELPER_CALL macro. */
5130 mips_ignore_helper (CORE_ADDR pc
)
5134 /* Find the starting address and name of the function containing the PC. */
5135 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
5138 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
5139 that we want to ignore. */
5140 return (strcmp (name
, "__mips16_ret_sf") == 0
5141 || strcmp (name
, "__mips16_ret_df") == 0);
5145 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5146 [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5149 mips_stab_reg_to_regnum (int num
)
5152 if (num
>= 0 && num
< 32)
5154 else if (num
>= 38 && num
< 70)
5155 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 38;
5157 regnum
= mips_regnum (current_gdbarch
)->hi
;
5159 regnum
= mips_regnum (current_gdbarch
)->lo
;
5161 /* This will hopefully (eventually) provoke a warning. Should
5162 we be calling complaint() here? */
5163 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5164 return NUM_REGS
+ regnum
;
5168 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5169 NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5172 mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num
)
5175 if (num
>= 0 && num
< 32)
5177 else if (num
>= 32 && num
< 64)
5178 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 32;
5180 regnum
= mips_regnum (current_gdbarch
)->hi
;
5182 regnum
= mips_regnum (current_gdbarch
)->lo
;
5184 /* This will hopefully (eventually) provoke a warning. Should we
5185 be calling complaint() here? */
5186 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5187 return NUM_REGS
+ regnum
;
5191 mips_register_sim_regno (int regnum
)
5193 /* Only makes sense to supply raw registers. */
5194 gdb_assert (regnum
>= 0 && regnum
< NUM_REGS
);
5195 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5196 decide if it is valid. Should instead define a standard sim/gdb
5197 register numbering scheme. */
5198 if (REGISTER_NAME (NUM_REGS
+ regnum
) != NULL
5199 && REGISTER_NAME (NUM_REGS
+ regnum
)[0] != '\0')
5202 return LEGACY_SIM_REGNO_IGNORE
;
5206 /* Convert an integer into an address. By first converting the value
5207 into a pointer and then extracting it signed, the address is
5208 guarenteed to be correctly sign extended. */
5211 mips_integer_to_address (struct type
*type
, void *buf
)
5213 char *tmp
= alloca (TYPE_LENGTH (builtin_type_void_data_ptr
));
5214 LONGEST val
= unpack_long (type
, buf
);
5215 store_signed_integer (tmp
, TYPE_LENGTH (builtin_type_void_data_ptr
), val
);
5216 return extract_signed_integer (tmp
,
5217 TYPE_LENGTH (builtin_type_void_data_ptr
));
5221 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
5223 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
5224 const char *name
= bfd_get_section_name (abfd
, sect
);
5226 if (*abip
!= MIPS_ABI_UNKNOWN
)
5229 if (strncmp (name
, ".mdebug.", 8) != 0)
5232 if (strcmp (name
, ".mdebug.abi32") == 0)
5233 *abip
= MIPS_ABI_O32
;
5234 else if (strcmp (name
, ".mdebug.abiN32") == 0)
5235 *abip
= MIPS_ABI_N32
;
5236 else if (strcmp (name
, ".mdebug.abi64") == 0)
5237 *abip
= MIPS_ABI_N64
;
5238 else if (strcmp (name
, ".mdebug.abiO64") == 0)
5239 *abip
= MIPS_ABI_O64
;
5240 else if (strcmp (name
, ".mdebug.eabi32") == 0)
5241 *abip
= MIPS_ABI_EABI32
;
5242 else if (strcmp (name
, ".mdebug.eabi64") == 0)
5243 *abip
= MIPS_ABI_EABI64
;
5245 warning ("unsupported ABI %s.", name
+ 8);
5248 static enum mips_abi
5249 global_mips_abi (void)
5253 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
5254 if (mips_abi_strings
[i
] == mips_abi_string
)
5255 return (enum mips_abi
) i
;
5257 internal_error (__FILE__
, __LINE__
, "unknown ABI string");
5260 static struct gdbarch
*
5261 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5263 struct gdbarch
*gdbarch
;
5264 struct gdbarch_tdep
*tdep
;
5266 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
5268 enum mips_fpu_type fpu_type
;
5270 /* First of all, extract the elf_flags, if available. */
5271 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5272 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
5273 else if (arches
!= NULL
)
5274 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
5278 fprintf_unfiltered (gdb_stdlog
,
5279 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
5281 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5282 switch ((elf_flags
& EF_MIPS_ABI
))
5284 case E_MIPS_ABI_O32
:
5285 found_abi
= MIPS_ABI_O32
;
5287 case E_MIPS_ABI_O64
:
5288 found_abi
= MIPS_ABI_O64
;
5290 case E_MIPS_ABI_EABI32
:
5291 found_abi
= MIPS_ABI_EABI32
;
5293 case E_MIPS_ABI_EABI64
:
5294 found_abi
= MIPS_ABI_EABI64
;
5297 if ((elf_flags
& EF_MIPS_ABI2
))
5298 found_abi
= MIPS_ABI_N32
;
5300 found_abi
= MIPS_ABI_UNKNOWN
;
5304 /* GCC creates a pseudo-section whose name describes the ABI. */
5305 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
5306 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
5308 /* If we have no useful BFD information, use the ABI from the last
5309 MIPS architecture (if there is one). */
5310 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
5311 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
5313 /* Try the architecture for any hint of the correct ABI. */
5314 if (found_abi
== MIPS_ABI_UNKNOWN
5315 && info
.bfd_arch_info
!= NULL
5316 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5318 switch (info
.bfd_arch_info
->mach
)
5320 case bfd_mach_mips3900
:
5321 found_abi
= MIPS_ABI_EABI32
;
5323 case bfd_mach_mips4100
:
5324 case bfd_mach_mips5000
:
5325 found_abi
= MIPS_ABI_EABI64
;
5327 case bfd_mach_mips8000
:
5328 case bfd_mach_mips10000
:
5329 /* On Irix, ELF64 executables use the N64 ABI. The
5330 pseudo-sections which describe the ABI aren't present
5331 on IRIX. (Even for executables created by gcc.) */
5332 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5333 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5334 found_abi
= MIPS_ABI_N64
;
5336 found_abi
= MIPS_ABI_N32
;
5342 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
5345 /* What has the user specified from the command line? */
5346 wanted_abi
= global_mips_abi ();
5348 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
5351 /* Now that we have found what the ABI for this binary would be,
5352 check whether the user is overriding it. */
5353 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
5354 mips_abi
= wanted_abi
;
5355 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
5356 mips_abi
= found_abi
;
5358 mips_abi
= MIPS_ABI_O32
;
5360 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
5363 /* Also used when doing an architecture lookup. */
5365 fprintf_unfiltered (gdb_stdlog
,
5366 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
5367 mips64_transfers_32bit_regs_p
);
5369 /* Determine the MIPS FPU type. */
5370 if (!mips_fpu_type_auto
)
5371 fpu_type
= mips_fpu_type
;
5372 else if (info
.bfd_arch_info
!= NULL
5373 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5374 switch (info
.bfd_arch_info
->mach
)
5376 case bfd_mach_mips3900
:
5377 case bfd_mach_mips4100
:
5378 case bfd_mach_mips4111
:
5379 case bfd_mach_mips4120
:
5380 fpu_type
= MIPS_FPU_NONE
;
5382 case bfd_mach_mips4650
:
5383 fpu_type
= MIPS_FPU_SINGLE
;
5386 fpu_type
= MIPS_FPU_DOUBLE
;
5389 else if (arches
!= NULL
)
5390 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
5392 fpu_type
= MIPS_FPU_DOUBLE
;
5394 fprintf_unfiltered (gdb_stdlog
,
5395 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
5397 /* try to find a pre-existing architecture */
5398 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
5400 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
5402 /* MIPS needs to be pedantic about which ABI the object is
5404 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
5406 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
5408 /* Need to be pedantic about which register virtual size is
5410 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
5411 != mips64_transfers_32bit_regs_p
)
5413 /* Be pedantic about which FPU is selected. */
5414 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
5416 return arches
->gdbarch
;
5419 /* Need a new architecture. Fill in a target specific vector. */
5420 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
5421 gdbarch
= gdbarch_alloc (&info
, tdep
);
5422 tdep
->elf_flags
= elf_flags
;
5423 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
5424 tdep
->found_abi
= found_abi
;
5425 tdep
->mips_abi
= mips_abi
;
5426 tdep
->mips_fpu_type
= fpu_type
;
5428 /* Initially set everything according to the default ABI/ISA. */
5429 set_gdbarch_short_bit (gdbarch
, 16);
5430 set_gdbarch_int_bit (gdbarch
, 32);
5431 set_gdbarch_float_bit (gdbarch
, 32);
5432 set_gdbarch_double_bit (gdbarch
, 64);
5433 set_gdbarch_long_double_bit (gdbarch
, 64);
5434 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
5435 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
5436 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
5438 set_gdbarch_elf_make_msymbol_special (gdbarch
,
5439 mips_elf_make_msymbol_special
);
5441 /* Fill in the OS dependant register numbers and names. */
5443 const char **reg_names
;
5444 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
5445 struct mips_regnum
);
5446 if (info
.osabi
== GDB_OSABI_IRIX
)
5451 regnum
->badvaddr
= 66;
5454 regnum
->fp_control_status
= 69;
5455 regnum
->fp_implementation_revision
= 70;
5457 reg_names
= mips_irix_reg_names
;
5461 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
5462 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
5463 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
5464 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
5465 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
5466 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
5467 regnum
->fp_control_status
= 70;
5468 regnum
->fp_implementation_revision
= 71;
5470 if (info
.bfd_arch_info
!= NULL
5471 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
5472 reg_names
= mips_tx39_reg_names
;
5474 reg_names
= mips_generic_reg_names
;
5476 /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been
5477 replaced by read_pc? */
5478 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
5479 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
5480 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
5481 set_gdbarch_num_regs (gdbarch
, num_regs
);
5482 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
5483 set_gdbarch_register_name (gdbarch
, mips_register_name
);
5484 tdep
->mips_processor_reg_names
= reg_names
;
5485 tdep
->regnum
= regnum
;
5491 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
5492 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
5493 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
5494 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5495 tdep
->default_mask_address_p
= 0;
5496 set_gdbarch_long_bit (gdbarch
, 32);
5497 set_gdbarch_ptr_bit (gdbarch
, 32);
5498 set_gdbarch_long_long_bit (gdbarch
, 64);
5501 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
5502 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
5503 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
5504 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5505 tdep
->default_mask_address_p
= 0;
5506 set_gdbarch_long_bit (gdbarch
, 32);
5507 set_gdbarch_ptr_bit (gdbarch
, 32);
5508 set_gdbarch_long_long_bit (gdbarch
, 64);
5510 case MIPS_ABI_EABI32
:
5511 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5512 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
5513 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5514 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5515 tdep
->default_mask_address_p
= 0;
5516 set_gdbarch_long_bit (gdbarch
, 32);
5517 set_gdbarch_ptr_bit (gdbarch
, 32);
5518 set_gdbarch_long_long_bit (gdbarch
, 64);
5520 case MIPS_ABI_EABI64
:
5521 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5522 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
5523 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5524 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5525 tdep
->default_mask_address_p
= 0;
5526 set_gdbarch_long_bit (gdbarch
, 64);
5527 set_gdbarch_ptr_bit (gdbarch
, 64);
5528 set_gdbarch_long_long_bit (gdbarch
, 64);
5531 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5532 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5533 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5534 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5535 tdep
->default_mask_address_p
= 0;
5536 set_gdbarch_long_bit (gdbarch
, 32);
5537 set_gdbarch_ptr_bit (gdbarch
, 32);
5538 set_gdbarch_long_long_bit (gdbarch
, 64);
5539 set_gdbarch_long_double_bit (gdbarch
, 128);
5540 set_gdbarch_long_double_format (gdbarch
,
5541 &floatformat_n32n64_long_double_big
);
5544 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5545 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5546 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5547 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5548 tdep
->default_mask_address_p
= 0;
5549 set_gdbarch_long_bit (gdbarch
, 64);
5550 set_gdbarch_ptr_bit (gdbarch
, 64);
5551 set_gdbarch_long_long_bit (gdbarch
, 64);
5552 set_gdbarch_long_double_bit (gdbarch
, 128);
5553 set_gdbarch_long_double_format (gdbarch
,
5554 &floatformat_n32n64_long_double_big
);
5557 internal_error (__FILE__
, __LINE__
, "unknown ABI in switch");
5560 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5561 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5564 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
5565 flag in object files because to do so would make it impossible to
5566 link with libraries compiled without "-gp32". This is
5567 unnecessarily restrictive.
5569 We could solve this problem by adding "-gp32" multilibs to gcc,
5570 but to set this flag before gcc is built with such multilibs will
5571 break too many systems.''
5573 But even more unhelpfully, the default linker output target for
5574 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
5575 for 64-bit programs - you need to change the ABI to change this,
5576 and not all gcc targets support that currently. Therefore using
5577 this flag to detect 32-bit mode would do the wrong thing given
5578 the current gcc - it would make GDB treat these 64-bit programs
5579 as 32-bit programs by default. */
5581 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
5582 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
5583 set_gdbarch_read_sp (gdbarch
, mips_read_sp
);
5585 /* Add/remove bits from an address. The MIPS needs be careful to
5586 ensure that all 32 bit addresses are sign extended to 64 bits. */
5587 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
5589 /* Unwind the frame. */
5590 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
5591 set_gdbarch_unwind_dummy_id (gdbarch
, mips_unwind_dummy_id
);
5593 /* Map debug register numbers onto internal register numbers. */
5594 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
5595 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
5596 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5597 set_gdbarch_dwarf_reg_to_regnum (gdbarch
,
5598 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5599 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
5600 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5601 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
5603 /* MIPS version of CALL_DUMMY */
5605 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
5606 replaced by a command, and all targets will default to on stack
5607 (regardless of the stack's execute status). */
5608 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
5609 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
5611 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
5612 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
5613 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
5615 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
5616 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
5618 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
5620 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
5621 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
5622 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
5624 set_gdbarch_register_type (gdbarch
, mips_register_type
);
5626 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
5628 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
5630 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
5631 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
5632 need to all be folded into the target vector. Since they are
5633 being used as guards for STOPPED_BY_WATCHPOINT, why not have
5634 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
5636 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
5638 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
5640 /* NOTE drow/2004-02-11: We overload the core solib trampoline code
5641 to support MIPS16. This is a bad thing. Make sure not to do it
5642 if we have an OS ABI that actually supports shared libraries, since
5643 shared library support is more important. If we have an OS someday
5644 that supports both shared libraries and MIPS16, we'll have to find
5645 a better place for these. */
5646 if (info
.osabi
== GDB_OSABI_UNKNOWN
)
5648 set_gdbarch_in_solib_call_trampoline (gdbarch
, mips_in_call_stub
);
5649 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_solib_return_trampoline
);
5652 /* Hook in OS ABI-specific overrides, if they have been registered. */
5653 gdbarch_init_osabi (info
, gdbarch
);
5655 /* Unwind the frame. */
5656 frame_unwind_append_sniffer (gdbarch
, mips_stub_frame_sniffer
);
5657 frame_unwind_append_sniffer (gdbarch
, mips_mdebug_frame_sniffer
);
5658 frame_unwind_append_sniffer (gdbarch
, mips_insn16_frame_sniffer
);
5659 frame_unwind_append_sniffer (gdbarch
, mips_insn32_frame_sniffer
);
5660 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
5661 frame_base_append_sniffer (gdbarch
, mips_mdebug_frame_base_sniffer
);
5662 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
5663 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
5669 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
5671 struct gdbarch_info info
;
5673 /* Force the architecture to update, and (if it's a MIPS architecture)
5674 mips_gdbarch_init will take care of the rest. */
5675 gdbarch_info_init (&info
);
5676 gdbarch_update_p (info
);
5679 /* Print out which MIPS ABI is in use. */
5682 show_mips_abi (char *ignore_args
, int from_tty
)
5684 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_mips
)
5686 ("The MIPS ABI is unknown because the current architecture is not MIPS.\n");
5689 enum mips_abi global_abi
= global_mips_abi ();
5690 enum mips_abi actual_abi
= mips_abi (current_gdbarch
);
5691 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
5693 if (global_abi
== MIPS_ABI_UNKNOWN
)
5695 ("The MIPS ABI is set automatically (currently \"%s\").\n",
5697 else if (global_abi
== actual_abi
)
5699 ("The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
5703 /* Probably shouldn't happen... */
5705 ("The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
5706 actual_abi_str
, mips_abi_strings
[global_abi
]);
5712 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
5714 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5718 int ef_mips_32bitmode
;
5719 /* determine the ISA */
5720 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
5738 /* determine the size of a pointer */
5739 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
5740 fprintf_unfiltered (file
,
5741 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
5743 fprintf_unfiltered (file
,
5744 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
5746 fprintf_unfiltered (file
,
5747 "mips_dump_tdep: ef_mips_arch = %d\n",
5749 fprintf_unfiltered (file
,
5750 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
5751 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
5752 fprintf_unfiltered (file
,
5753 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
5754 mips_mask_address_p (tdep
),
5755 tdep
->default_mask_address_p
);
5757 fprintf_unfiltered (file
,
5758 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
5759 MIPS_DEFAULT_FPU_TYPE
,
5760 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
5761 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
5762 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
5764 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI
);
5765 fprintf_unfiltered (file
,
5766 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
5768 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
5769 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
5770 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
5772 fprintf_unfiltered (file
,
5773 "mips_dump_tdep: mips_stack_argsize() = %d\n",
5774 mips_stack_argsize (current_gdbarch
));
5775 fprintf_unfiltered (file
,
5776 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
5777 XSTRING (ADDR_BITS_REMOVE (ADDR
)));
5778 fprintf_unfiltered (file
,
5779 "mips_dump_tdep: ATTACH_DETACH # %s\n",
5780 XSTRING (ATTACH_DETACH
));
5781 fprintf_unfiltered (file
,
5782 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
5783 XSTRING (DWARF_REG_TO_REGNUM (REGNUM
)));
5784 fprintf_unfiltered (file
,
5785 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
5786 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM
)));
5787 fprintf_unfiltered (file
,
5788 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
5789 FIRST_EMBED_REGNUM
);
5790 fprintf_unfiltered (file
,
5791 "mips_dump_tdep: DEPRECATED_IGNORE_HELPER_CALL # %s\n",
5792 XSTRING (DEPRECATED_IGNORE_HELPER_CALL (PC
)));
5793 fprintf_unfiltered (file
,
5794 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
5795 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC
, NAME
)));
5796 fprintf_unfiltered (file
,
5797 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
5799 #ifdef MACHINE_CPROC_FP_OFFSET
5800 fprintf_unfiltered (file
,
5801 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
5802 MACHINE_CPROC_FP_OFFSET
);
5804 #ifdef MACHINE_CPROC_PC_OFFSET
5805 fprintf_unfiltered (file
,
5806 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
5807 MACHINE_CPROC_PC_OFFSET
);
5809 #ifdef MACHINE_CPROC_SP_OFFSET
5810 fprintf_unfiltered (file
,
5811 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
5812 MACHINE_CPROC_SP_OFFSET
);
5814 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
5815 fprintf_unfiltered (file
,
5816 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
5817 fprintf_unfiltered (file
,
5818 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
5819 MIPS_LAST_ARG_REGNUM
,
5820 MIPS_LAST_ARG_REGNUM
- MIPS_A0_REGNUM
+ 1);
5821 fprintf_unfiltered (file
,
5822 "mips_dump_tdep: MIPS_NUMREGS = %d\n", MIPS_NUMREGS
);
5823 fprintf_unfiltered (file
,
5824 "mips_dump_tdep: mips_abi_regsize() = %d\n",
5825 mips_abi_regsize (current_gdbarch
));
5826 fprintf_unfiltered (file
,
5827 "mips_dump_tdep: PRID_REGNUM = %d\n", PRID_REGNUM
);
5828 fprintf_unfiltered (file
,
5829 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
5830 fprintf_unfiltered (file
,
5831 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
5832 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FRAME_REG = function?\n");
5833 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FREG_MASK = function?\n");
5834 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
5835 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
5836 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
5837 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_PC_REG = function?\n");
5838 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_REG_MASK = function?\n");
5839 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
5840 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_SYMBOL = function?\n");
5841 fprintf_unfiltered (file
, "mips_dump_tdep: PS_REGNUM = %d\n", PS_REGNUM
);
5843 fprintf_unfiltered (file
,
5844 "mips_dump_tdep: SAVED_BYTES = %d\n", SAVED_BYTES
);
5847 fprintf_unfiltered (file
, "mips_dump_tdep: SAVED_FP = %d\n", SAVED_FP
);
5850 fprintf_unfiltered (file
, "mips_dump_tdep: SAVED_PC = %d\n", SAVED_PC
);
5852 fprintf_unfiltered (file
,
5853 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
5854 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS
, ARGS
)));
5855 fprintf_unfiltered (file
,
5856 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
5857 XSTRING (SOFTWARE_SINGLE_STEP (SIG
, BP_P
)));
5858 fprintf_unfiltered (file
,
5859 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n",
5860 SOFTWARE_SINGLE_STEP_P ());
5861 fprintf_unfiltered (file
,
5862 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
5863 XSTRING (STAB_REG_TO_REGNUM (REGNUM
)));
5864 #ifdef STACK_END_ADDR
5865 fprintf_unfiltered (file
,
5866 "mips_dump_tdep: STACK_END_ADDR = %d\n",
5869 fprintf_unfiltered (file
,
5870 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
5871 XSTRING (STEP_SKIPS_DELAY (PC
)));
5872 fprintf_unfiltered (file
,
5873 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
5874 STEP_SKIPS_DELAY_P
);
5875 fprintf_unfiltered (file
,
5876 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
5877 XSTRING (STOPPED_BY_WATCHPOINT (WS
)));
5878 fprintf_unfiltered (file
,
5879 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
5880 fprintf_unfiltered (file
,
5881 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
5882 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT
5883 (TYPE
, CNT
, OTHERTYPE
)));
5885 fprintf_unfiltered (file
,
5886 "mips_dump_tdep: TRACE_CLEAR # %s\n",
5887 XSTRING (TRACE_CLEAR (THREAD
, STATE
)));
5890 fprintf_unfiltered (file
,
5891 "mips_dump_tdep: TRACE_FLAVOR = %d\n", TRACE_FLAVOR
);
5893 #ifdef TRACE_FLAVOR_SIZE
5894 fprintf_unfiltered (file
,
5895 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
5899 fprintf_unfiltered (file
,
5900 "mips_dump_tdep: TRACE_SET # %s\n",
5901 XSTRING (TRACE_SET (X
, STATE
)));
5903 #ifdef UNUSED_REGNUM
5904 fprintf_unfiltered (file
,
5905 "mips_dump_tdep: UNUSED_REGNUM = %d\n", UNUSED_REGNUM
);
5907 fprintf_unfiltered (file
,
5908 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
5909 (long) VM_MIN_ADDRESS
);
5912 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
5915 _initialize_mips_tdep (void)
5917 static struct cmd_list_element
*mipsfpulist
= NULL
;
5918 struct cmd_list_element
*c
;
5920 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
5921 if (MIPS_ABI_LAST
+ 1
5922 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
5923 internal_error (__FILE__
, __LINE__
, "mips_abi_strings out of sync");
5925 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
5927 mips_pdr_data
= register_objfile_data ();
5929 /* Add root prefix command for all "set mips"/"show mips" commands */
5930 add_prefix_cmd ("mips", no_class
, set_mips_command
,
5931 "Various MIPS specific commands.",
5932 &setmipscmdlist
, "set mips ", 0, &setlist
);
5934 add_prefix_cmd ("mips", no_class
, show_mips_command
,
5935 "Various MIPS specific commands.",
5936 &showmipscmdlist
, "show mips ", 0, &showlist
);
5938 /* Allow the user to override the saved register size. */
5939 add_setshow_enum_cmd ("saved-gpreg-size", class_obscure
,
5940 size_enums
, &mips_abi_regsize_string
, "\
5941 Set size of general purpose registers saved on the stack.\n", "\
5942 Show size of general purpose registers saved on the stack.\n", "\
5943 This option can be set to one of:\n\
5944 32 - Force GDB to treat saved GP registers as 32-bit\n\
5945 64 - Force GDB to treat saved GP registers as 64-bit\n\
5946 auto - Allow GDB to use the target's default setting or autodetect the\n\
5947 saved GP register size from information contained in the executable.\n\
5948 (default: auto)", "\
5949 Size of general purpose registers saved on the stack is %s.\n",
5950 NULL
, NULL
, &setmipscmdlist
, &showmipscmdlist
);
5952 /* Allow the user to override the argument stack size. */
5953 add_setshow_enum_cmd ("stack-arg-size", class_obscure
,
5954 size_enums
, &mips_stack_argsize_string
, "\
5955 Set the amount of stack space reserved for each argument.\n", "\
5956 Show the amount of stack space reserved for each argument.\n", "\
5957 This option can be set to one of:\n\
5958 32 - Force GDB to allocate 32-bit chunks per argument\n\
5959 64 - Force GDB to allocate 64-bit chunks per argument\n\
5960 auto - Allow GDB to determine the correct setting from the current\n\
5961 target and executable (default)", "\
5962 The amount of stack space reserved for each argument is %s.\n",
5963 NULL
, NULL
, &setmipscmdlist
, &showmipscmdlist
);
5965 /* Allow the user to override the ABI. */
5966 c
= add_set_enum_cmd
5967 ("abi", class_obscure
, mips_abi_strings
, &mips_abi_string
,
5968 "Set the ABI used by this program.\n"
5969 "This option can be set to one of:\n"
5970 " auto - the default ABI associated with the current binary\n"
5972 " o64\n" " n32\n" " n64\n" " eabi32\n" " eabi64", &setmipscmdlist
);
5973 set_cmd_sfunc (c
, mips_abi_update
);
5974 add_cmd ("abi", class_obscure
, show_mips_abi
,
5975 "Show ABI in use by MIPS target", &showmipscmdlist
);
5977 /* Let the user turn off floating point and set the fence post for
5978 heuristic_proc_start. */
5980 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
5981 "Set use of MIPS floating-point coprocessor.",
5982 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
5983 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
5984 "Select single-precision MIPS floating-point coprocessor.",
5986 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
5987 "Select double-precision MIPS floating-point coprocessor.",
5989 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
5990 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
5991 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
5992 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
5993 "Select no MIPS floating-point coprocessor.", &mipsfpulist
);
5994 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
5995 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
5996 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
5997 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
5998 "Select MIPS floating-point coprocessor automatically.",
6000 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
6001 "Show current use of MIPS floating-point coprocessor target.",
6004 /* We really would like to have both "0" and "unlimited" work, but
6005 command.c doesn't deal with that. So make it a var_zinteger
6006 because the user can always use "999999" or some such for unlimited. */
6007 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
6008 &heuristic_fence_post
, "\
6009 Set the distance searched for the start of a function.\n", "\
6010 Show the distance searched for the start of a function.\n", "\
6011 If you are debugging a stripped executable, GDB needs to search through the\n\
6012 program for the start of a function. This command sets the distance of the\n\
6013 search. The only need to set it is when debugging a stripped executable.", "\
6014 The distance searched for the start of a function is %s.\n",
6015 reinit_frame_cache_sfunc
, NULL
,
6016 &setlist
, &showlist
);
6018 /* Allow the user to control whether the upper bits of 64-bit
6019 addresses should be zeroed. */
6020 add_setshow_auto_boolean_cmd ("mask-address", no_class
, &mask_address_var
, "\
6021 Set zeroing of upper 32 bits of 64-bit addresses.", "\
6022 Show zeroing of upper 32 bits of 64-bit addresses.", "\
6023 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
6024 allow GDB to determine the correct value.\n", "\
6025 Zerroing of upper 32 bits of 64-bit address is %s.",
6026 NULL
, show_mask_address
, &setmipscmdlist
, &showmipscmdlist
);
6028 /* Allow the user to control the size of 32 bit registers within the
6029 raw remote packet. */
6030 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
6031 &mips64_transfers_32bit_regs_p
, "\
6032 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities.", "\
6033 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities.", "\
6034 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6035 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6036 64 bits for others. Use \"off\" to disable compatibility mode", "\
6037 Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s.",
6038 set_mips64_transfers_32bit_regs
, NULL
, &setlist
, &showlist
);
6040 /* Debug this files internals. */
6041 add_setshow_zinteger_cmd ("mips", class_maintenance
,
6043 Set mips debugging.\n", "\
6044 Show mips debugging.\n", "\
6045 When non-zero, mips specific debugging is enabled.\n", "\
6046 Mips debugging is currently %s.\n",
6048 &setdebuglist
, &showdebuglist
);