1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
5 Free Software Foundation, Inc.
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program. If not, see <http://www.gnu.org/licenses/>. */
26 #include "gdb_string.h"
27 #include "gdb_assert.h"
39 #include "arch-utils.h"
42 #include "mips-tdep.h"
44 #include "reggroups.h"
45 #include "opcode/mips.h"
49 #include "sim-regno.h"
51 #include "frame-unwind.h"
52 #include "frame-base.h"
53 #include "trad-frame.h"
55 #include "floatformat.h"
57 #include "target-descriptions.h"
58 #include "dwarf2-frame.h"
59 #include "user-regs.h"
61 static const struct objfile_data
*mips_pdr_data
;
63 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
65 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
66 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
67 #define ST0_FR (1 << 26)
69 /* The sizes of floating point registers. */
73 MIPS_FPU_SINGLE_REGSIZE
= 4,
74 MIPS_FPU_DOUBLE_REGSIZE
= 8
83 static const char *mips_abi_string
;
85 static const char *mips_abi_strings
[] = {
96 /* The standard register names, and all the valid aliases for them. */
103 /* Aliases for o32 and most other ABIs. */
104 const struct register_alias mips_o32_aliases
[] = {
111 /* Aliases for n32 and n64. */
112 const struct register_alias mips_n32_n64_aliases
[] = {
119 /* Aliases for ABI-independent registers. */
120 const struct register_alias mips_register_aliases
[] = {
121 /* The architecture manuals specify these ABI-independent names for
123 #define R(n) { "r" #n, n }
124 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
125 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
126 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
127 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
130 /* k0 and k1 are sometimes called these instead (for "kernel
135 /* This is the traditional GDB name for the CP0 status register. */
136 { "sr", MIPS_PS_REGNUM
},
138 /* This is the traditional GDB name for the CP0 BadVAddr register. */
139 { "bad", MIPS_EMBED_BADVADDR_REGNUM
},
141 /* This is the traditional GDB name for the FCSR. */
142 { "fsr", MIPS_EMBED_FP0_REGNUM
+ 32 }
145 /* Some MIPS boards don't support floating point while others only
146 support single-precision floating-point operations. */
150 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
151 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
152 MIPS_FPU_NONE
/* No floating point. */
155 #ifndef MIPS_DEFAULT_FPU_TYPE
156 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
158 static int mips_fpu_type_auto
= 1;
159 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
161 static int mips_debug
= 0;
163 /* Properties (for struct target_desc) describing the g/G packet
165 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
166 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
168 struct target_desc
*mips_tdesc_gp32
;
169 struct target_desc
*mips_tdesc_gp64
;
171 /* MIPS specific per-architecture information */
174 /* from the elf header */
178 enum mips_abi mips_abi
;
179 enum mips_abi found_abi
;
180 enum mips_fpu_type mips_fpu_type
;
181 int mips_last_arg_regnum
;
182 int mips_last_fp_arg_regnum
;
183 int default_mask_address_p
;
184 /* Is the target using 64-bit raw integer registers but only
185 storing a left-aligned 32-bit value in each? */
186 int mips64_transfers_32bit_regs_p
;
187 /* Indexes for various registers. IRIX and embedded have
188 different values. This contains the "public" fields. Don't
189 add any that do not need to be public. */
190 const struct mips_regnum
*regnum
;
191 /* Register names table for the current register set. */
192 const char **mips_processor_reg_names
;
194 /* The size of register data available from the target, if known.
195 This doesn't quite obsolete the manual
196 mips64_transfers_32bit_regs_p, since that is documented to force
197 left alignment even for big endian (very strange). */
198 int register_size_valid_p
;
203 n32n64_floatformat_always_valid (const struct floatformat
*fmt
,
209 /* FIXME: brobecker/2004-08-08: Long Double values are 128 bit long.
210 They are implemented as a pair of 64bit doubles where the high
211 part holds the result of the operation rounded to double, and
212 the low double holds the difference between the exact result and
213 the rounded result. So "high" + "low" contains the result with
214 added precision. Unfortunately, the floatformat structure used
215 by GDB is not powerful enough to describe this format. As a temporary
216 measure, we define a 128bit floatformat that only uses the high part.
217 We lose a bit of precision but that's probably the best we can do
218 for now with the current infrastructure. */
220 static const struct floatformat floatformat_n32n64_long_double_big
=
222 floatformat_big
, 128, 0, 1, 11, 1023, 2047, 12, 52,
223 floatformat_intbit_no
,
224 "floatformat_n32n64_long_double_big",
225 n32n64_floatformat_always_valid
228 static const struct floatformat
*floatformats_n32n64_long
[BFD_ENDIAN_UNKNOWN
] =
230 &floatformat_n32n64_long_double_big
,
231 &floatformat_n32n64_long_double_big
234 const struct mips_regnum
*
235 mips_regnum (struct gdbarch
*gdbarch
)
237 return gdbarch_tdep (gdbarch
)->regnum
;
241 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
243 return mips_regnum (gdbarch
)->fp0
+ 12;
246 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
247 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
249 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
251 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
253 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
255 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
256 functions to test, set, or clear bit 0 of addresses. */
259 is_mips16_addr (CORE_ADDR addr
)
265 unmake_mips16_addr (CORE_ADDR addr
)
267 return ((addr
) & ~(CORE_ADDR
) 1);
270 /* Return the MIPS ABI associated with GDBARCH. */
272 mips_abi (struct gdbarch
*gdbarch
)
274 return gdbarch_tdep (gdbarch
)->mips_abi
;
278 mips_isa_regsize (struct gdbarch
*gdbarch
)
280 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
282 /* If we know how big the registers are, use that size. */
283 if (tdep
->register_size_valid_p
)
284 return tdep
->register_size
;
286 /* Fall back to the previous behavior. */
287 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
288 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
291 /* Return the currently configured (or set) saved register size. */
294 mips_abi_regsize (struct gdbarch
*gdbarch
)
296 switch (mips_abi (gdbarch
))
298 case MIPS_ABI_EABI32
:
304 case MIPS_ABI_EABI64
:
306 case MIPS_ABI_UNKNOWN
:
309 internal_error (__FILE__
, __LINE__
, _("bad switch"));
313 /* Functions for setting and testing a bit in a minimal symbol that
314 marks it as 16-bit function. The MSB of the minimal symbol's
315 "info" field is used for this purpose.
317 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special",
318 i.e. refers to a 16-bit function, and sets a "special" bit in a
319 minimal symbol to mark it as a 16-bit function
321 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
324 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
326 if (((elf_symbol_type
*) (sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
328 MSYMBOL_INFO (msym
) = (char *)
329 (((long) MSYMBOL_INFO (msym
)) | 0x80000000);
330 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
335 msymbol_is_special (struct minimal_symbol
*msym
)
337 return (((long) MSYMBOL_INFO (msym
) & 0x80000000) != 0);
340 /* XFER a value from the big/little/left end of the register.
341 Depending on the size of the value it might occupy the entire
342 register or just part of it. Make an allowance for this, aligning
343 things accordingly. */
346 mips_xfer_register (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
347 int reg_num
, int length
,
348 enum bfd_endian endian
, gdb_byte
*in
,
349 const gdb_byte
*out
, int buf_offset
)
353 gdb_assert (reg_num
>= gdbarch_num_regs (gdbarch
));
354 /* Need to transfer the left or right part of the register, based on
355 the targets byte order. */
359 reg_offset
= register_size (gdbarch
, reg_num
) - length
;
361 case BFD_ENDIAN_LITTLE
:
364 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
368 internal_error (__FILE__
, __LINE__
, _("bad switch"));
371 fprintf_unfiltered (gdb_stderr
,
372 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
373 reg_num
, reg_offset
, buf_offset
, length
);
374 if (mips_debug
&& out
!= NULL
)
377 fprintf_unfiltered (gdb_stdlog
, "out ");
378 for (i
= 0; i
< length
; i
++)
379 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
382 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
385 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
387 if (mips_debug
&& in
!= NULL
)
390 fprintf_unfiltered (gdb_stdlog
, "in ");
391 for (i
= 0; i
< length
; i
++)
392 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
395 fprintf_unfiltered (gdb_stdlog
, "\n");
398 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
399 compatiblity mode. A return value of 1 means that we have
400 physical 64-bit registers, but should treat them as 32-bit registers. */
403 mips2_fp_compat (struct frame_info
*frame
)
405 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
406 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
408 if (register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) == 4)
412 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
413 in all the places we deal with FP registers. PR gdb/413. */
414 /* Otherwise check the FR bit in the status register - it controls
415 the FP compatiblity mode. If it is clear we are in compatibility
417 if ((get_frame_register_unsigned (frame
, MIPS_PS_REGNUM
) & ST0_FR
) == 0)
424 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
426 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
428 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
430 static struct type
*mips_float_register_type (void);
431 static struct type
*mips_double_register_type (void);
433 /* The list of available "set mips " and "show mips " commands */
435 static struct cmd_list_element
*setmipscmdlist
= NULL
;
436 static struct cmd_list_element
*showmipscmdlist
= NULL
;
438 /* Integer registers 0 thru 31 are handled explicitly by
439 mips_register_name(). Processor specific registers 32 and above
440 are listed in the following tables. */
443 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
447 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
448 "sr", "lo", "hi", "bad", "cause", "pc",
449 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
450 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
451 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
452 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
453 "fsr", "fir", "" /*"fp" */ , "",
454 "", "", "", "", "", "", "", "",
455 "", "", "", "", "", "", "", "",
458 /* Names of IDT R3041 registers. */
460 static const char *mips_r3041_reg_names
[] = {
461 "sr", "lo", "hi", "bad", "cause", "pc",
462 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
463 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
464 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
465 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
466 "fsr", "fir", "", /*"fp" */ "",
467 "", "", "bus", "ccfg", "", "", "", "",
468 "", "", "port", "cmp", "", "", "epc", "prid",
471 /* Names of tx39 registers. */
473 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
474 "sr", "lo", "hi", "bad", "cause", "pc",
475 "", "", "", "", "", "", "", "",
476 "", "", "", "", "", "", "", "",
477 "", "", "", "", "", "", "", "",
478 "", "", "", "", "", "", "", "",
480 "", "", "", "", "", "", "", "",
481 "", "", "config", "cache", "debug", "depc", "epc", ""
484 /* Names of IRIX registers. */
485 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
486 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
487 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
488 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
489 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
490 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
494 /* Return the name of the register corresponding to REGNO. */
496 mips_register_name (struct gdbarch
*gdbarch
, int regno
)
498 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
499 /* GPR names for all ABIs other than n32/n64. */
500 static char *mips_gpr_names
[] = {
501 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
502 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
503 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
504 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
507 /* GPR names for n32 and n64 ABIs. */
508 static char *mips_n32_n64_gpr_names
[] = {
509 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
510 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
511 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
512 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
515 enum mips_abi abi
= mips_abi (gdbarch
);
517 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
518 but then don't make the raw register names visible. */
519 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
520 if (regno
< gdbarch_num_regs (gdbarch
))
523 /* The MIPS integer registers are always mapped from 0 to 31. The
524 names of the registers (which reflects the conventions regarding
525 register use) vary depending on the ABI. */
526 if (0 <= rawnum
&& rawnum
< 32)
528 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
529 return mips_n32_n64_gpr_names
[rawnum
];
531 return mips_gpr_names
[rawnum
];
533 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
534 return tdesc_register_name (gdbarch
, rawnum
);
535 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (gdbarch
))
537 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
538 return tdep
->mips_processor_reg_names
[rawnum
- 32];
541 internal_error (__FILE__
, __LINE__
,
542 _("mips_register_name: bad register number %d"), rawnum
);
545 /* Return the groups that a MIPS register can be categorised into. */
548 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
549 struct reggroup
*reggroup
)
554 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
555 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
556 if (reggroup
== all_reggroup
)
558 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
559 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
560 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
561 (gdbarch), as not all architectures are multi-arch. */
562 raw_p
= rawnum
< gdbarch_num_regs (gdbarch
);
563 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
564 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
566 if (reggroup
== float_reggroup
)
567 return float_p
&& pseudo
;
568 if (reggroup
== vector_reggroup
)
569 return vector_p
&& pseudo
;
570 if (reggroup
== general_reggroup
)
571 return (!vector_p
&& !float_p
) && pseudo
;
572 /* Save the pseudo registers. Need to make certain that any code
573 extracting register values from a saved register cache also uses
575 if (reggroup
== save_reggroup
)
576 return raw_p
&& pseudo
;
577 /* Restore the same pseudo register. */
578 if (reggroup
== restore_reggroup
)
579 return raw_p
&& pseudo
;
583 /* Return the groups that a MIPS register can be categorised into.
584 This version is only used if we have a target description which
585 describes real registers (and their groups). */
588 mips_tdesc_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
589 struct reggroup
*reggroup
)
591 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
592 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
595 /* Only save, restore, and display the pseudo registers. Need to
596 make certain that any code extracting register values from a
597 saved register cache also uses pseudo registers.
599 Note: saving and restoring the pseudo registers is slightly
600 strange; if we have 64 bits, we should save and restore all
601 64 bits. But this is hard and has little benefit. */
605 ret
= tdesc_register_in_reggroup_p (gdbarch
, rawnum
, reggroup
);
609 return mips_register_reggroup_p (gdbarch
, regnum
, reggroup
);
612 /* Map the symbol table registers which live in the range [1 *
613 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
614 registers. Take care of alignment and size problems. */
617 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
618 int cookednum
, gdb_byte
*buf
)
620 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
621 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
622 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
623 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
624 regcache_raw_read (regcache
, rawnum
, buf
);
625 else if (register_size (gdbarch
, rawnum
) >
626 register_size (gdbarch
, cookednum
))
628 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
629 || gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
630 regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
632 regcache_raw_read_part (regcache
, rawnum
, 4, 4, buf
);
635 internal_error (__FILE__
, __LINE__
, _("bad register size"));
639 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
640 struct regcache
*regcache
, int cookednum
,
643 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
644 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
645 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
646 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
647 regcache_raw_write (regcache
, rawnum
, buf
);
648 else if (register_size (gdbarch
, rawnum
) >
649 register_size (gdbarch
, cookednum
))
651 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
652 || gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
653 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
655 regcache_raw_write_part (regcache
, rawnum
, 4, 4, buf
);
658 internal_error (__FILE__
, __LINE__
, _("bad register size"));
661 /* Table to translate MIPS16 register field to actual register number. */
662 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
664 /* Heuristic_proc_start may hunt through the text section for a long
665 time across a 2400 baud serial line. Allows the user to limit this
668 static unsigned int heuristic_fence_post
= 0;
670 /* Number of bytes of storage in the actual machine representation for
671 register N. NOTE: This defines the pseudo register type so need to
672 rebuild the architecture vector. */
674 static int mips64_transfers_32bit_regs_p
= 0;
677 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
678 struct cmd_list_element
*c
)
680 struct gdbarch_info info
;
681 gdbarch_info_init (&info
);
682 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
683 instead of relying on globals. Doing that would let generic code
684 handle the search for this specific architecture. */
685 if (!gdbarch_update_p (info
))
687 mips64_transfers_32bit_regs_p
= 0;
688 error (_("32-bit compatibility mode not supported"));
692 /* Convert to/from a register and the corresponding memory value. */
695 mips_convert_register_p (int regnum
, struct type
*type
)
697 return (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
698 && register_size (current_gdbarch
, regnum
) == 4
699 && (regnum
% gdbarch_num_regs (current_gdbarch
))
700 >= mips_regnum (current_gdbarch
)->fp0
701 && (regnum
% gdbarch_num_regs (current_gdbarch
))
702 < mips_regnum (current_gdbarch
)->fp0
+ 32
703 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
707 mips_register_to_value (struct frame_info
*frame
, int regnum
,
708 struct type
*type
, gdb_byte
*to
)
710 get_frame_register (frame
, regnum
+ 0, to
+ 4);
711 get_frame_register (frame
, regnum
+ 1, to
+ 0);
715 mips_value_to_register (struct frame_info
*frame
, int regnum
,
716 struct type
*type
, const gdb_byte
*from
)
718 put_frame_register (frame
, regnum
+ 0, from
+ 4);
719 put_frame_register (frame
, regnum
+ 1, from
+ 0);
722 /* Return the GDB type object for the "standard" data type of data in
726 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
728 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (gdbarch
));
729 if ((regnum
% gdbarch_num_regs (gdbarch
)) >= mips_regnum (gdbarch
)->fp0
730 && (regnum
% gdbarch_num_regs (gdbarch
))
731 < mips_regnum (gdbarch
)->fp0
+ 32)
733 /* The floating-point registers raw, or cooked, always match
734 mips_isa_regsize(), and also map 1:1, byte for byte. */
735 if (mips_isa_regsize (gdbarch
) == 4)
736 return builtin_type_ieee_single
;
738 return builtin_type_ieee_double
;
740 else if (regnum
< gdbarch_num_regs (gdbarch
))
742 /* The raw or ISA registers. These are all sized according to
744 if (mips_isa_regsize (gdbarch
) == 4)
745 return builtin_type_int32
;
747 return builtin_type_int64
;
751 /* The cooked or ABI registers. These are sized according to
752 the ABI (with a few complications). */
753 if (regnum
>= (gdbarch_num_regs (gdbarch
)
754 + mips_regnum (gdbarch
)->fp_control_status
)
755 && regnum
<= gdbarch_num_regs (gdbarch
) + MIPS_LAST_EMBED_REGNUM
)
756 /* The pseudo/cooked view of the embedded registers is always
757 32-bit. The raw view is handled below. */
758 return builtin_type_int32
;
759 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
760 /* The target, while possibly using a 64-bit register buffer,
761 is only transfering 32-bits of each integer register.
762 Reflect this in the cooked/pseudo (ABI) register value. */
763 return builtin_type_int32
;
764 else if (mips_abi_regsize (gdbarch
) == 4)
765 /* The ABI is restricted to 32-bit registers (the ISA could be
767 return builtin_type_int32
;
770 return builtin_type_int64
;
774 /* Return the GDB type for the pseudo register REGNUM, which is the
775 ABI-level view. This function is only called if there is a target
776 description which includes registers, so we know precisely the
777 types of hardware registers. */
780 mips_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
782 const int num_regs
= gdbarch_num_regs (gdbarch
);
783 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
784 int rawnum
= regnum
% num_regs
;
785 struct type
*rawtype
;
787 gdb_assert (regnum
>= num_regs
&& regnum
< 2 * num_regs
);
789 /* Absent registers are still absent. */
790 rawtype
= gdbarch_register_type (gdbarch
, rawnum
);
791 if (TYPE_LENGTH (rawtype
) == 0)
794 if (rawnum
>= MIPS_EMBED_FP0_REGNUM
&& rawnum
< MIPS_EMBED_FP0_REGNUM
+ 32)
795 /* Present the floating point registers however the hardware did;
796 do not try to convert between FPU layouts. */
799 if (rawnum
>= MIPS_EMBED_FP0_REGNUM
+ 32 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
801 /* The pseudo/cooked view of embedded registers is always
802 32-bit, even if the target transfers 64-bit values for them.
803 New targets relying on XML descriptions should only transfer
804 the necessary 32 bits, but older versions of GDB expected 64,
805 so allow the target to provide 64 bits without interfering
806 with the displayed type. */
807 return builtin_type_int32
;
810 /* Use pointer types for registers if we can. For n32 we can not,
811 since we do not have a 64-bit pointer type. */
812 if (mips_abi_regsize (gdbarch
) == TYPE_LENGTH (builtin_type_void_data_ptr
))
814 if (rawnum
== MIPS_SP_REGNUM
|| rawnum
== MIPS_EMBED_BADVADDR_REGNUM
)
815 return builtin_type_void_data_ptr
;
816 else if (rawnum
== MIPS_EMBED_PC_REGNUM
)
817 return builtin_type_void_func_ptr
;
820 if (mips_abi_regsize (gdbarch
) == 4 && TYPE_LENGTH (rawtype
) == 8
821 && rawnum
>= MIPS_ZERO_REGNUM
&& rawnum
<= MIPS_EMBED_PC_REGNUM
)
822 return builtin_type_int32
;
824 /* For all other registers, pass through the hardware type. */
828 /* Should the upper word of 64-bit addresses be zeroed? */
829 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
832 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
834 switch (mask_address_var
)
836 case AUTO_BOOLEAN_TRUE
:
838 case AUTO_BOOLEAN_FALSE
:
841 case AUTO_BOOLEAN_AUTO
:
842 return tdep
->default_mask_address_p
;
844 internal_error (__FILE__
, __LINE__
, _("mips_mask_address_p: bad switch"));
850 show_mask_address (struct ui_file
*file
, int from_tty
,
851 struct cmd_list_element
*c
, const char *value
)
853 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
855 deprecated_show_value_hack (file
, from_tty
, c
, value
);
856 switch (mask_address_var
)
858 case AUTO_BOOLEAN_TRUE
:
859 printf_filtered ("The 32 bit mips address mask is enabled\n");
861 case AUTO_BOOLEAN_FALSE
:
862 printf_filtered ("The 32 bit mips address mask is disabled\n");
864 case AUTO_BOOLEAN_AUTO
:
866 ("The 32 bit address mask is set automatically. Currently %s\n",
867 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
870 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
875 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
878 mips_pc_is_mips16 (CORE_ADDR memaddr
)
880 struct minimal_symbol
*sym
;
882 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
883 if (is_mips16_addr (memaddr
))
886 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
887 the high bit of the info field. Use this to decide if the function is
888 MIPS16 or normal MIPS. */
889 sym
= lookup_minimal_symbol_by_pc (memaddr
);
891 return msymbol_is_special (sym
);
896 /* MIPS believes that the PC has a sign extended value. Perhaps the
897 all registers should be sign extended for simplicity? */
900 mips_read_pc (struct regcache
*regcache
)
903 int regnum
= mips_regnum (get_regcache_arch (regcache
))->pc
;
904 regcache_cooked_read_signed (regcache
, regnum
, &pc
);
909 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
911 return frame_unwind_register_signed
912 (next_frame
, gdbarch_num_regs (gdbarch
) + mips_regnum (gdbarch
)->pc
);
916 mips_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
918 return frame_unwind_register_signed
919 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
);
922 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
923 dummy frame. The frame ID's base needs to match the TOS value
924 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
927 static struct frame_id
928 mips_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
930 return frame_id_build
931 (frame_unwind_register_signed (next_frame
,
932 gdbarch_num_regs (gdbarch
)
934 frame_pc_unwind (next_frame
));
938 mips_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
940 int regnum
= mips_regnum (get_regcache_arch (regcache
))->pc
;
941 regcache_cooked_write_unsigned (regcache
, regnum
, pc
);
944 /* Fetch and return instruction from the specified location. If the PC
945 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
948 mips_fetch_instruction (CORE_ADDR addr
)
950 gdb_byte buf
[MIPS_INSN32_SIZE
];
954 if (mips_pc_is_mips16 (addr
))
956 instlen
= MIPS_INSN16_SIZE
;
957 addr
= unmake_mips16_addr (addr
);
960 instlen
= MIPS_INSN32_SIZE
;
961 status
= read_memory_nobpt (addr
, buf
, instlen
);
963 memory_error (status
, addr
);
964 return extract_unsigned_integer (buf
, instlen
);
967 /* These the fields of 32 bit mips instructions */
968 #define mips32_op(x) (x >> 26)
969 #define itype_op(x) (x >> 26)
970 #define itype_rs(x) ((x >> 21) & 0x1f)
971 #define itype_rt(x) ((x >> 16) & 0x1f)
972 #define itype_immediate(x) (x & 0xffff)
974 #define jtype_op(x) (x >> 26)
975 #define jtype_target(x) (x & 0x03ffffff)
977 #define rtype_op(x) (x >> 26)
978 #define rtype_rs(x) ((x >> 21) & 0x1f)
979 #define rtype_rt(x) ((x >> 16) & 0x1f)
980 #define rtype_rd(x) ((x >> 11) & 0x1f)
981 #define rtype_shamt(x) ((x >> 6) & 0x1f)
982 #define rtype_funct(x) (x & 0x3f)
985 mips32_relative_offset (ULONGEST inst
)
987 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
990 /* Determine where to set a single step breakpoint while considering
991 branch prediction. */
993 mips32_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
997 inst
= mips_fetch_instruction (pc
);
998 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
1000 if (itype_op (inst
) >> 2 == 5)
1001 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1003 op
= (itype_op (inst
) & 0x03);
1013 goto greater_branch
;
1018 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
1019 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1021 int tf
= itype_rt (inst
) & 0x01;
1022 int cnum
= itype_rt (inst
) >> 2;
1024 get_frame_register_signed (frame
,
1025 mips_regnum (get_frame_arch (frame
))->
1027 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
1029 if (((cond
>> cnum
) & 0x01) == tf
)
1030 pc
+= mips32_relative_offset (inst
) + 4;
1035 pc
+= 4; /* Not a branch, next instruction is easy */
1038 { /* This gets way messy */
1040 /* Further subdivide into SPECIAL, REGIMM and other */
1041 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
1043 case 0: /* SPECIAL */
1044 op
= rtype_funct (inst
);
1049 /* Set PC to that address */
1050 pc
= get_frame_register_signed (frame
, rtype_rs (inst
));
1056 break; /* end SPECIAL */
1057 case 1: /* REGIMM */
1059 op
= itype_rt (inst
); /* branch condition */
1064 case 16: /* BLTZAL */
1065 case 18: /* BLTZALL */
1067 if (get_frame_register_signed (frame
, itype_rs (inst
)) < 0)
1068 pc
+= mips32_relative_offset (inst
) + 4;
1070 pc
+= 8; /* after the delay slot */
1074 case 17: /* BGEZAL */
1075 case 19: /* BGEZALL */
1076 if (get_frame_register_signed (frame
, itype_rs (inst
)) >= 0)
1077 pc
+= mips32_relative_offset (inst
) + 4;
1079 pc
+= 8; /* after the delay slot */
1081 /* All of the other instructions in the REGIMM category */
1086 break; /* end REGIMM */
1091 reg
= jtype_target (inst
) << 2;
1092 /* Upper four bits get never changed... */
1093 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1096 /* FIXME case JALX : */
1099 reg
= jtype_target (inst
) << 2;
1100 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + 1; /* yes, +1 */
1101 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1103 break; /* The new PC will be alternate mode */
1104 case 4: /* BEQ, BEQL */
1106 if (get_frame_register_signed (frame
, itype_rs (inst
)) ==
1107 get_frame_register_signed (frame
, itype_rt (inst
)))
1108 pc
+= mips32_relative_offset (inst
) + 4;
1112 case 5: /* BNE, BNEL */
1114 if (get_frame_register_signed (frame
, itype_rs (inst
)) !=
1115 get_frame_register_signed (frame
, itype_rt (inst
)))
1116 pc
+= mips32_relative_offset (inst
) + 4;
1120 case 6: /* BLEZ, BLEZL */
1121 if (get_frame_register_signed (frame
, itype_rs (inst
)) <= 0)
1122 pc
+= mips32_relative_offset (inst
) + 4;
1128 greater_branch
: /* BGTZ, BGTZL */
1129 if (get_frame_register_signed (frame
, itype_rs (inst
)) > 0)
1130 pc
+= mips32_relative_offset (inst
) + 4;
1137 } /* mips32_next_pc */
1139 /* Decoding the next place to set a breakpoint is irregular for the
1140 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1141 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1142 We dont want to set a single step instruction on the extend instruction
1146 /* Lots of mips16 instruction formats */
1147 /* Predicting jumps requires itype,ritype,i8type
1148 and their extensions extItype,extritype,extI8type
1150 enum mips16_inst_fmts
1152 itype
, /* 0 immediate 5,10 */
1153 ritype
, /* 1 5,3,8 */
1154 rrtype
, /* 2 5,3,3,5 */
1155 rritype
, /* 3 5,3,3,5 */
1156 rrrtype
, /* 4 5,3,3,3,2 */
1157 rriatype
, /* 5 5,3,3,1,4 */
1158 shifttype
, /* 6 5,3,3,3,2 */
1159 i8type
, /* 7 5,3,8 */
1160 i8movtype
, /* 8 5,3,3,5 */
1161 i8mov32rtype
, /* 9 5,3,5,3 */
1162 i64type
, /* 10 5,3,8 */
1163 ri64type
, /* 11 5,3,3,5 */
1164 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1165 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1166 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1167 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1168 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1169 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1170 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1171 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1172 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1173 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1175 /* I am heaping all the fields of the formats into one structure and
1176 then, only the fields which are involved in instruction extension */
1180 unsigned int regx
; /* Function in i8 type */
1185 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1186 for the bits which make up the immediatate extension. */
1189 extended_offset (unsigned int extension
)
1192 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1194 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1196 value
|= extension
& 0x01f; /* extract 4:0 */
1200 /* Only call this function if you know that this is an extendable
1201 instruction. It won't malfunction, but why make excess remote memory
1202 references? If the immediate operands get sign extended or something,
1203 do it after the extension is performed. */
1204 /* FIXME: Every one of these cases needs to worry about sign extension
1205 when the offset is to be used in relative addressing. */
1208 fetch_mips_16 (CORE_ADDR pc
)
1211 pc
&= 0xfffffffe; /* clear the low order bit */
1212 target_read_memory (pc
, buf
, 2);
1213 return extract_unsigned_integer (buf
, 2);
1217 unpack_mips16 (CORE_ADDR pc
,
1218 unsigned int extension
,
1220 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1225 switch (insn_format
)
1232 value
= extended_offset (extension
);
1233 value
= value
<< 11; /* rom for the original value */
1234 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1238 value
= inst
& 0x7ff;
1239 /* FIXME : Consider sign extension */
1248 { /* A register identifier and an offset */
1249 /* Most of the fields are the same as I type but the
1250 immediate value is of a different length */
1254 value
= extended_offset (extension
);
1255 value
= value
<< 8; /* from the original instruction */
1256 value
|= inst
& 0xff; /* eleven bits from instruction */
1257 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1258 if (value
& 0x4000) /* test the sign bit , bit 26 */
1260 value
&= ~0x3fff; /* remove the sign bit */
1266 value
= inst
& 0xff; /* 8 bits */
1267 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1268 /* FIXME: Do sign extension , this format needs it */
1269 if (value
& 0x80) /* THIS CONFUSES ME */
1271 value
&= 0xef; /* remove the sign bit */
1281 unsigned long value
;
1282 unsigned int nexthalf
;
1283 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1284 value
= value
<< 16;
1285 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1293 internal_error (__FILE__
, __LINE__
, _("bad switch"));
1295 upk
->offset
= offset
;
1302 add_offset_16 (CORE_ADDR pc
, int offset
)
1304 return ((offset
<< 2) | ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)));
1308 extended_mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
,
1309 unsigned int extension
, unsigned int insn
)
1311 int op
= (insn
>> 11);
1314 case 2: /* Branch */
1317 struct upk_mips16 upk
;
1318 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1319 offset
= upk
.offset
;
1325 pc
+= (offset
<< 1) + 2;
1328 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1330 struct upk_mips16 upk
;
1331 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1332 pc
= add_offset_16 (pc
, upk
.offset
);
1333 if ((insn
>> 10) & 0x01) /* Exchange mode */
1334 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1341 struct upk_mips16 upk
;
1343 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1344 reg
= get_frame_register_signed (frame
, upk
.regx
);
1346 pc
+= (upk
.offset
<< 1) + 2;
1353 struct upk_mips16 upk
;
1355 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1356 reg
= get_frame_register_signed (frame
, upk
.regx
);
1358 pc
+= (upk
.offset
<< 1) + 2;
1363 case 12: /* I8 Formats btez btnez */
1365 struct upk_mips16 upk
;
1367 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1368 /* upk.regx contains the opcode */
1369 reg
= get_frame_register_signed (frame
, 24); /* Test register is 24 */
1370 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1371 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1372 /* pc = add_offset_16(pc,upk.offset) ; */
1373 pc
+= (upk
.offset
<< 1) + 2;
1378 case 29: /* RR Formats JR, JALR, JALR-RA */
1380 struct upk_mips16 upk
;
1381 /* upk.fmt = rrtype; */
1386 upk
.regx
= (insn
>> 8) & 0x07;
1387 upk
.regy
= (insn
>> 5) & 0x07;
1395 break; /* Function return instruction */
1401 break; /* BOGUS Guess */
1403 pc
= get_frame_register_signed (frame
, reg
);
1410 /* This is an instruction extension. Fetch the real instruction
1411 (which follows the extension) and decode things based on
1415 pc
= extended_mips16_next_pc (frame
, pc
, insn
, fetch_mips_16 (pc
));
1428 mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1430 unsigned int insn
= fetch_mips_16 (pc
);
1431 return extended_mips16_next_pc (frame
, pc
, 0, insn
);
1434 /* The mips_next_pc function supports single_step when the remote
1435 target monitor or stub is not developed enough to do a single_step.
1436 It works by decoding the current instruction and predicting where a
1437 branch will go. This isnt hard because all the data is available.
1438 The MIPS32 and MIPS16 variants are quite different. */
1440 mips_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1442 if (is_mips16_addr (pc
))
1443 return mips16_next_pc (frame
, pc
);
1445 return mips32_next_pc (frame
, pc
);
1448 struct mips_frame_cache
1451 struct trad_frame_saved_reg
*saved_regs
;
1454 /* Set a register's saved stack address in temp_saved_regs. If an
1455 address has already been set for this register, do nothing; this
1456 way we will only recognize the first save of a given register in a
1459 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
1460 [gdbarch_num_regs .. 2*gdbarch_num_regs).
1461 Strictly speaking, only the second range is used as it is only second
1462 range (the ABI instead of ISA registers) that comes into play when finding
1463 saved registers in a frame. */
1466 set_reg_offset (struct mips_frame_cache
*this_cache
, int regnum
,
1469 if (this_cache
!= NULL
1470 && this_cache
->saved_regs
[regnum
].addr
== -1)
1472 this_cache
->saved_regs
[regnum
1473 + 0 * gdbarch_num_regs (current_gdbarch
)].addr
1475 this_cache
->saved_regs
[regnum
1476 + 1 * gdbarch_num_regs (current_gdbarch
)].addr
1482 /* Fetch the immediate value from a MIPS16 instruction.
1483 If the previous instruction was an EXTEND, use it to extend
1484 the upper bits of the immediate value. This is a helper function
1485 for mips16_scan_prologue. */
1488 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1489 unsigned short inst
, /* current instruction */
1490 int nbits
, /* number of bits in imm field */
1491 int scale
, /* scale factor to be applied to imm */
1492 int is_signed
) /* is the imm field signed? */
1496 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1498 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1499 if (offset
& 0x8000) /* check for negative extend */
1500 offset
= 0 - (0x10000 - (offset
& 0xffff));
1501 return offset
| (inst
& 0x1f);
1505 int max_imm
= 1 << nbits
;
1506 int mask
= max_imm
- 1;
1507 int sign_bit
= max_imm
>> 1;
1509 offset
= inst
& mask
;
1510 if (is_signed
&& (offset
& sign_bit
))
1511 offset
= 0 - (max_imm
- offset
);
1512 return offset
* scale
;
1517 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1518 the associated FRAME_CACHE if not null.
1519 Return the address of the first instruction past the prologue. */
1522 mips16_scan_prologue (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1523 struct frame_info
*next_frame
,
1524 struct mips_frame_cache
*this_cache
)
1527 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1529 long frame_offset
= 0; /* Size of stack frame. */
1530 long frame_adjust
= 0; /* Offset of FP from SP. */
1531 int frame_reg
= MIPS_SP_REGNUM
;
1532 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1533 unsigned inst
= 0; /* current instruction */
1534 unsigned entry_inst
= 0; /* the entry instruction */
1537 int extend_bytes
= 0;
1538 int prev_extend_bytes
;
1539 CORE_ADDR end_prologue_addr
= 0;
1540 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
1542 /* Can be called when there's no process, and hence when there's no
1544 if (next_frame
!= NULL
)
1545 sp
= frame_unwind_register_signed (next_frame
,
1546 gdbarch_num_regs (gdbarch
)
1551 if (limit_pc
> start_pc
+ 200)
1552 limit_pc
= start_pc
+ 200;
1554 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
1556 /* Save the previous instruction. If it's an EXTEND, we'll extract
1557 the immediate offset extension from it in mips16_get_imm. */
1560 /* Fetch and decode the instruction. */
1561 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1563 /* Normally we ignore extend instructions. However, if it is
1564 not followed by a valid prologue instruction, then this
1565 instruction is not part of the prologue either. We must
1566 remember in this case to adjust the end_prologue_addr back
1568 if ((inst
& 0xf800) == 0xf000) /* extend */
1570 extend_bytes
= MIPS_INSN16_SIZE
;
1574 prev_extend_bytes
= extend_bytes
;
1577 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1578 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1580 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1581 if (offset
< 0) /* negative stack adjustment? */
1582 frame_offset
-= offset
;
1584 /* Exit loop if a positive stack adjustment is found, which
1585 usually means that the stack cleanup code in the function
1586 epilogue is reached. */
1589 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1591 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1592 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1593 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1595 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1597 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1598 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1599 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1601 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1603 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1604 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1606 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1608 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1609 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1611 else if (inst
== 0x673d) /* move $s1, $sp */
1616 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1618 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1619 frame_addr
= sp
+ offset
;
1621 frame_adjust
= offset
;
1623 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1625 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1626 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1627 set_reg_offset (this_cache
, reg
, frame_addr
+ offset
);
1629 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1631 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1632 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1633 set_reg_offset (this_cache
, reg
, frame_addr
+ offset
);
1635 else if ((inst
& 0xf81f) == 0xe809
1636 && (inst
& 0x700) != 0x700) /* entry */
1637 entry_inst
= inst
; /* save for later processing */
1638 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1639 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
1640 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
1642 /* This instruction is part of the prologue, but we don't
1643 need to do anything special to handle it. */
1647 /* This instruction is not an instruction typically found
1648 in a prologue, so we must have reached the end of the
1650 if (end_prologue_addr
== 0)
1651 end_prologue_addr
= cur_pc
- prev_extend_bytes
;
1655 /* The entry instruction is typically the first instruction in a function,
1656 and it stores registers at offsets relative to the value of the old SP
1657 (before the prologue). But the value of the sp parameter to this
1658 function is the new SP (after the prologue has been executed). So we
1659 can't calculate those offsets until we've seen the entire prologue,
1660 and can calculate what the old SP must have been. */
1661 if (entry_inst
!= 0)
1663 int areg_count
= (entry_inst
>> 8) & 7;
1664 int sreg_count
= (entry_inst
>> 6) & 3;
1666 /* The entry instruction always subtracts 32 from the SP. */
1669 /* Now we can calculate what the SP must have been at the
1670 start of the function prologue. */
1673 /* Check if a0-a3 were saved in the caller's argument save area. */
1674 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1676 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1677 offset
+= mips_abi_regsize (gdbarch
);
1680 /* Check if the ra register was pushed on the stack. */
1682 if (entry_inst
& 0x20)
1684 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1685 offset
-= mips_abi_regsize (gdbarch
);
1688 /* Check if the s0 and s1 registers were pushed on the stack. */
1689 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1691 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1692 offset
-= mips_abi_regsize (gdbarch
);
1696 if (this_cache
!= NULL
)
1699 (frame_unwind_register_signed (next_frame
,
1700 gdbarch_num_regs (gdbarch
) + frame_reg
)
1701 + frame_offset
- frame_adjust
);
1702 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
1703 be able to get rid of the assignment below, evetually. But it's
1704 still needed for now. */
1705 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
1706 + mips_regnum (gdbarch
)->pc
]
1707 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
1710 /* If we didn't reach the end of the prologue when scanning the function
1711 instructions, then set end_prologue_addr to the address of the
1712 instruction immediately after the last one we scanned. */
1713 if (end_prologue_addr
== 0)
1714 end_prologue_addr
= cur_pc
;
1716 return end_prologue_addr
;
1719 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
1720 Procedures that use the 32-bit instruction set are handled by the
1721 mips_insn32 unwinder. */
1723 static struct mips_frame_cache
*
1724 mips_insn16_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1726 struct mips_frame_cache
*cache
;
1728 if ((*this_cache
) != NULL
)
1729 return (*this_cache
);
1730 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1731 (*this_cache
) = cache
;
1732 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1734 /* Analyze the function prologue. */
1736 const CORE_ADDR pc
=
1737 frame_unwind_address_in_block (next_frame
, NORMAL_FRAME
);
1738 CORE_ADDR start_addr
;
1740 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
1741 if (start_addr
== 0)
1742 start_addr
= heuristic_proc_start (pc
);
1743 /* We can't analyze the prologue if we couldn't find the begining
1745 if (start_addr
== 0)
1748 mips16_scan_prologue (start_addr
, pc
, next_frame
, *this_cache
);
1751 /* gdbarch_sp_regnum contains the value and not the address. */
1752 trad_frame_set_value (cache
->saved_regs
,
1753 gdbarch_num_regs (get_frame_arch (next_frame
))
1757 return (*this_cache
);
1761 mips_insn16_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1762 struct frame_id
*this_id
)
1764 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1766 (*this_id
) = frame_id_build (info
->base
,
1767 frame_func_unwind (next_frame
, NORMAL_FRAME
));
1771 mips_insn16_frame_prev_register (struct frame_info
*next_frame
,
1773 int regnum
, int *optimizedp
,
1774 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1775 int *realnump
, gdb_byte
*valuep
)
1777 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1779 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
1780 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
1783 static const struct frame_unwind mips_insn16_frame_unwind
=
1786 mips_insn16_frame_this_id
,
1787 mips_insn16_frame_prev_register
1790 static const struct frame_unwind
*
1791 mips_insn16_frame_sniffer (struct frame_info
*next_frame
)
1793 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1794 if (mips_pc_is_mips16 (pc
))
1795 return &mips_insn16_frame_unwind
;
1800 mips_insn16_frame_base_address (struct frame_info
*next_frame
,
1803 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1808 static const struct frame_base mips_insn16_frame_base
=
1810 &mips_insn16_frame_unwind
,
1811 mips_insn16_frame_base_address
,
1812 mips_insn16_frame_base_address
,
1813 mips_insn16_frame_base_address
1816 static const struct frame_base
*
1817 mips_insn16_frame_base_sniffer (struct frame_info
*next_frame
)
1819 if (mips_insn16_frame_sniffer (next_frame
) != NULL
)
1820 return &mips_insn16_frame_base
;
1825 /* Mark all the registers as unset in the saved_regs array
1826 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
1829 reset_saved_regs (struct mips_frame_cache
*this_cache
)
1831 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
1835 const int num_regs
= gdbarch_num_regs (current_gdbarch
);
1838 for (i
= 0; i
< num_regs
; i
++)
1840 this_cache
->saved_regs
[i
].addr
= -1;
1845 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1846 the associated FRAME_CACHE if not null.
1847 Return the address of the first instruction past the prologue. */
1850 mips32_scan_prologue (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1851 struct frame_info
*next_frame
,
1852 struct mips_frame_cache
*this_cache
)
1855 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
1858 int frame_reg
= MIPS_SP_REGNUM
;
1860 CORE_ADDR end_prologue_addr
= 0;
1861 int seen_sp_adjust
= 0;
1862 int load_immediate_bytes
= 0;
1863 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
1865 /* Can be called when there's no process, and hence when there's no
1867 if (next_frame
!= NULL
)
1868 sp
= frame_unwind_register_signed (next_frame
,
1869 gdbarch_num_regs (gdbarch
)
1874 if (limit_pc
> start_pc
+ 200)
1875 limit_pc
= start_pc
+ 200;
1880 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
1882 unsigned long inst
, high_word
, low_word
;
1885 /* Fetch the instruction. */
1886 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
1888 /* Save some code by pre-extracting some useful fields. */
1889 high_word
= (inst
>> 16) & 0xffff;
1890 low_word
= inst
& 0xffff;
1891 reg
= high_word
& 0x1f;
1893 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
1894 || high_word
== 0x23bd /* addi $sp,$sp,-i */
1895 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
1897 if (low_word
& 0x8000) /* negative stack adjustment? */
1898 frame_offset
+= 0x10000 - low_word
;
1900 /* Exit loop if a positive stack adjustment is found, which
1901 usually means that the stack cleanup code in the function
1902 epilogue is reached. */
1906 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1908 set_reg_offset (this_cache
, reg
, sp
+ low_word
);
1910 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1912 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
1913 set_reg_offset (this_cache
, reg
, sp
+ low_word
);
1915 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
1917 /* Old gcc frame, r30 is virtual frame pointer. */
1918 if ((long) low_word
!= frame_offset
)
1919 frame_addr
= sp
+ low_word
;
1920 else if (next_frame
&& frame_reg
== MIPS_SP_REGNUM
)
1922 unsigned alloca_adjust
;
1925 frame_addr
= frame_unwind_register_signed
1926 (next_frame
, gdbarch_num_regs (gdbarch
) + 30);
1928 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
1929 if (alloca_adjust
> 0)
1931 /* FP > SP + frame_size. This may be because of
1932 an alloca or somethings similar. Fix sp to
1933 "pre-alloca" value, and try again. */
1934 sp
+= alloca_adjust
;
1935 /* Need to reset the status of all registers. Otherwise,
1936 we will hit a guard that prevents the new address
1937 for each register to be recomputed during the second
1939 reset_saved_regs (this_cache
);
1944 /* move $30,$sp. With different versions of gas this will be either
1945 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
1946 Accept any one of these. */
1947 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
1949 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
1950 if (next_frame
&& frame_reg
== MIPS_SP_REGNUM
)
1952 unsigned alloca_adjust
;
1955 frame_addr
= frame_unwind_register_signed
1956 (next_frame
, gdbarch_num_regs (gdbarch
) + 30);
1958 alloca_adjust
= (unsigned) (frame_addr
- sp
);
1959 if (alloca_adjust
> 0)
1961 /* FP > SP + frame_size. This may be because of
1962 an alloca or somethings similar. Fix sp to
1963 "pre-alloca" value, and try again. */
1965 /* Need to reset the status of all registers. Otherwise,
1966 we will hit a guard that prevents the new address
1967 for each register to be recomputed during the second
1969 reset_saved_regs (this_cache
);
1974 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
1976 set_reg_offset (this_cache
, reg
, frame_addr
+ low_word
);
1978 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
1979 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
1980 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
1981 || high_word
== 0x3c1c /* lui $gp,n */
1982 || high_word
== 0x279c /* addiu $gp,$gp,n */
1983 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
1984 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
1987 /* These instructions are part of the prologue, but we don't
1988 need to do anything special to handle them. */
1990 /* The instructions below load $at or $t0 with an immediate
1991 value in preparation for a stack adjustment via
1992 subu $sp,$sp,[$at,$t0]. These instructions could also
1993 initialize a local variable, so we accept them only before
1994 a stack adjustment instruction was seen. */
1995 else if (!seen_sp_adjust
1996 && (high_word
== 0x3c01 /* lui $at,n */
1997 || high_word
== 0x3c08 /* lui $t0,n */
1998 || high_word
== 0x3421 /* ori $at,$at,n */
1999 || high_word
== 0x3508 /* ori $t0,$t0,n */
2000 || high_word
== 0x3401 /* ori $at,$zero,n */
2001 || high_word
== 0x3408 /* ori $t0,$zero,n */
2004 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
2008 /* This instruction is not an instruction typically found
2009 in a prologue, so we must have reached the end of the
2011 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
2012 loop now? Why would we need to continue scanning the function
2014 if (end_prologue_addr
== 0)
2015 end_prologue_addr
= cur_pc
;
2019 if (this_cache
!= NULL
)
2022 (frame_unwind_register_signed (next_frame
,
2023 gdbarch_num_regs (gdbarch
) + frame_reg
)
2025 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
2026 this assignment below, eventually. But it's still needed
2028 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2029 + mips_regnum (gdbarch
)->pc
]
2030 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2034 /* If we didn't reach the end of the prologue when scanning the function
2035 instructions, then set end_prologue_addr to the address of the
2036 instruction immediately after the last one we scanned. */
2037 /* brobecker/2004-10-10: I don't think this would ever happen, but
2038 we may as well be careful and do our best if we have a null
2039 end_prologue_addr. */
2040 if (end_prologue_addr
== 0)
2041 end_prologue_addr
= cur_pc
;
2043 /* In a frameless function, we might have incorrectly
2044 skipped some load immediate instructions. Undo the skipping
2045 if the load immediate was not followed by a stack adjustment. */
2046 if (load_immediate_bytes
&& !seen_sp_adjust
)
2047 end_prologue_addr
-= load_immediate_bytes
;
2049 return end_prologue_addr
;
2052 /* Heuristic unwinder for procedures using 32-bit instructions (covers
2053 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
2054 instructions (a.k.a. MIPS16) are handled by the mips_insn16
2057 static struct mips_frame_cache
*
2058 mips_insn32_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
2060 struct mips_frame_cache
*cache
;
2062 if ((*this_cache
) != NULL
)
2063 return (*this_cache
);
2065 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2066 (*this_cache
) = cache
;
2067 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
2069 /* Analyze the function prologue. */
2071 const CORE_ADDR pc
=
2072 frame_unwind_address_in_block (next_frame
, NORMAL_FRAME
);
2073 CORE_ADDR start_addr
;
2075 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2076 if (start_addr
== 0)
2077 start_addr
= heuristic_proc_start (pc
);
2078 /* We can't analyze the prologue if we couldn't find the begining
2080 if (start_addr
== 0)
2083 mips32_scan_prologue (start_addr
, pc
, next_frame
, *this_cache
);
2086 /* gdbarch_sp_regnum contains the value and not the address. */
2087 trad_frame_set_value (cache
->saved_regs
,
2088 gdbarch_num_regs (get_frame_arch (next_frame
))
2092 return (*this_cache
);
2096 mips_insn32_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2097 struct frame_id
*this_id
)
2099 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2101 (*this_id
) = frame_id_build (info
->base
,
2102 frame_func_unwind (next_frame
, NORMAL_FRAME
));
2106 mips_insn32_frame_prev_register (struct frame_info
*next_frame
,
2108 int regnum
, int *optimizedp
,
2109 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2110 int *realnump
, gdb_byte
*valuep
)
2112 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2114 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
2115 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
2118 static const struct frame_unwind mips_insn32_frame_unwind
=
2121 mips_insn32_frame_this_id
,
2122 mips_insn32_frame_prev_register
2125 static const struct frame_unwind
*
2126 mips_insn32_frame_sniffer (struct frame_info
*next_frame
)
2128 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2129 if (! mips_pc_is_mips16 (pc
))
2130 return &mips_insn32_frame_unwind
;
2135 mips_insn32_frame_base_address (struct frame_info
*next_frame
,
2138 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2143 static const struct frame_base mips_insn32_frame_base
=
2145 &mips_insn32_frame_unwind
,
2146 mips_insn32_frame_base_address
,
2147 mips_insn32_frame_base_address
,
2148 mips_insn32_frame_base_address
2151 static const struct frame_base
*
2152 mips_insn32_frame_base_sniffer (struct frame_info
*next_frame
)
2154 if (mips_insn32_frame_sniffer (next_frame
) != NULL
)
2155 return &mips_insn32_frame_base
;
2160 static struct trad_frame_cache
*
2161 mips_stub_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
2164 CORE_ADDR start_addr
;
2165 CORE_ADDR stack_addr
;
2166 struct trad_frame_cache
*this_trad_cache
;
2167 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
2169 if ((*this_cache
) != NULL
)
2170 return (*this_cache
);
2171 this_trad_cache
= trad_frame_cache_zalloc (next_frame
);
2172 (*this_cache
) = this_trad_cache
;
2174 /* The return address is in the link register. */
2175 trad_frame_set_reg_realreg (this_trad_cache
,
2176 gdbarch_pc_regnum (gdbarch
),
2177 (gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
));
2179 /* Frame ID, since it's a frameless / stackless function, no stack
2180 space is allocated and SP on entry is the current SP. */
2181 pc
= frame_pc_unwind (next_frame
);
2182 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2183 stack_addr
= frame_unwind_register_signed (next_frame
, MIPS_SP_REGNUM
);
2184 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
2186 /* Assume that the frame's base is the same as the
2188 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
2190 return this_trad_cache
;
2194 mips_stub_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2195 struct frame_id
*this_id
)
2197 struct trad_frame_cache
*this_trad_cache
2198 = mips_stub_frame_cache (next_frame
, this_cache
);
2199 trad_frame_get_id (this_trad_cache
, this_id
);
2203 mips_stub_frame_prev_register (struct frame_info
*next_frame
,
2205 int regnum
, int *optimizedp
,
2206 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2207 int *realnump
, gdb_byte
*valuep
)
2209 struct trad_frame_cache
*this_trad_cache
2210 = mips_stub_frame_cache (next_frame
, this_cache
);
2211 trad_frame_get_register (this_trad_cache
, next_frame
, regnum
, optimizedp
,
2212 lvalp
, addrp
, realnump
, valuep
);
2215 static const struct frame_unwind mips_stub_frame_unwind
=
2218 mips_stub_frame_this_id
,
2219 mips_stub_frame_prev_register
2222 static const struct frame_unwind
*
2223 mips_stub_frame_sniffer (struct frame_info
*next_frame
)
2226 struct obj_section
*s
;
2227 CORE_ADDR pc
= frame_unwind_address_in_block (next_frame
, NORMAL_FRAME
);
2229 /* Use the stub unwinder for unreadable code. */
2230 if (target_read_memory (frame_pc_unwind (next_frame
), dummy
, 4) != 0)
2231 return &mips_stub_frame_unwind
;
2233 if (in_plt_section (pc
, NULL
))
2234 return &mips_stub_frame_unwind
;
2236 /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */
2237 s
= find_pc_section (pc
);
2240 && strcmp (bfd_get_section_name (s
->objfile
->obfd
, s
->the_bfd_section
),
2241 ".MIPS.stubs") == 0)
2242 return &mips_stub_frame_unwind
;
2248 mips_stub_frame_base_address (struct frame_info
*next_frame
,
2251 struct trad_frame_cache
*this_trad_cache
2252 = mips_stub_frame_cache (next_frame
, this_cache
);
2253 return trad_frame_get_this_base (this_trad_cache
);
2256 static const struct frame_base mips_stub_frame_base
=
2258 &mips_stub_frame_unwind
,
2259 mips_stub_frame_base_address
,
2260 mips_stub_frame_base_address
,
2261 mips_stub_frame_base_address
2264 static const struct frame_base
*
2265 mips_stub_frame_base_sniffer (struct frame_info
*next_frame
)
2267 if (mips_stub_frame_sniffer (next_frame
) != NULL
)
2268 return &mips_stub_frame_base
;
2273 /* mips_addr_bits_remove - remove useless address bits */
2276 mips_addr_bits_remove (CORE_ADDR addr
)
2278 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2279 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
2280 /* This hack is a work-around for existing boards using PMON, the
2281 simulator, and any other 64-bit targets that doesn't have true
2282 64-bit addressing. On these targets, the upper 32 bits of
2283 addresses are ignored by the hardware. Thus, the PC or SP are
2284 likely to have been sign extended to all 1s by instruction
2285 sequences that load 32-bit addresses. For example, a typical
2286 piece of code that loads an address is this:
2288 lui $r2, <upper 16 bits>
2289 ori $r2, <lower 16 bits>
2291 But the lui sign-extends the value such that the upper 32 bits
2292 may be all 1s. The workaround is simply to mask off these
2293 bits. In the future, gcc may be changed to support true 64-bit
2294 addressing, and this masking will have to be disabled. */
2295 return addr
&= 0xffffffffUL
;
2300 /* Instructions used during single-stepping of atomic sequences. */
2301 #define LL_OPCODE 0x30
2302 #define LLD_OPCODE 0x34
2303 #define SC_OPCODE 0x38
2304 #define SCD_OPCODE 0x3c
2306 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
2307 instruction and ending with a SC/SCD instruction. If such a sequence
2308 is found, attempt to step through it. A breakpoint is placed at the end of
2312 deal_with_atomic_sequence (CORE_ADDR pc
)
2314 CORE_ADDR breaks
[2] = {-1, -1};
2316 CORE_ADDR branch_bp
; /* Breakpoint at branch instruction's destination. */
2320 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
2321 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
2326 insn
= mips_fetch_instruction (loc
);
2327 /* Assume all atomic sequences start with a ll/lld instruction. */
2328 if (itype_op (insn
) != LL_OPCODE
&& itype_op (insn
) != LLD_OPCODE
)
2331 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
2333 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
2336 loc
+= MIPS_INSN32_SIZE
;
2337 insn
= mips_fetch_instruction (loc
);
2339 /* Assume that there is at most one branch in the atomic
2340 sequence. If a branch is found, put a breakpoint in its
2341 destination address. */
2342 switch (itype_op (insn
))
2344 case 0: /* SPECIAL */
2345 if (rtype_funct (insn
) >> 1 == 4) /* JR, JALR */
2346 return 0; /* fallback to the standard single-step code. */
2348 case 1: /* REGIMM */
2349 is_branch
= ((itype_rt (insn
) & 0xc0) == 0); /* B{LT,GE}Z* */
2353 return 0; /* fallback to the standard single-step code. */
2360 case 22: /* BLEZL */
2361 case 23: /* BGTTL */
2367 is_branch
= (itype_rs (insn
) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
2372 branch_bp
= loc
+ mips32_relative_offset (insn
) + 4;
2373 if (last_breakpoint
>= 1)
2374 return 0; /* More than one branch found, fallback to the
2375 standard single-step code. */
2376 breaks
[1] = branch_bp
;
2380 if (itype_op (insn
) == SC_OPCODE
|| itype_op (insn
) == SCD_OPCODE
)
2384 /* Assume that the atomic sequence ends with a sc/scd instruction. */
2385 if (itype_op (insn
) != SC_OPCODE
&& itype_op (insn
) != SCD_OPCODE
)
2388 loc
+= MIPS_INSN32_SIZE
;
2390 /* Insert a breakpoint right after the end of the atomic sequence. */
2393 /* Check for duplicated breakpoints. Check also for a breakpoint
2394 placed (branch instruction's destination) in the atomic sequence */
2395 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
2396 last_breakpoint
= 0;
2398 /* Effectively inserts the breakpoints. */
2399 for (index
= 0; index
<= last_breakpoint
; index
++)
2400 insert_single_step_breakpoint (breaks
[index
]);
2405 /* mips_software_single_step() is called just before we want to resume
2406 the inferior, if we want to single-step it but there is no hardware
2407 or kernel single-step support (MIPS on GNU/Linux for example). We find
2408 the target of the coming instruction and breakpoint it. */
2411 mips_software_single_step (struct frame_info
*frame
)
2413 CORE_ADDR pc
, next_pc
;
2415 pc
= get_frame_pc (frame
);
2416 if (deal_with_atomic_sequence (pc
))
2419 next_pc
= mips_next_pc (frame
, pc
);
2421 insert_single_step_breakpoint (next_pc
);
2425 /* Test whether the PC points to the return instruction at the
2426 end of a function. */
2429 mips_about_to_return (CORE_ADDR pc
)
2431 if (mips_pc_is_mips16 (pc
))
2432 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2433 generates a "jr $ra"; other times it generates code to load
2434 the return address from the stack to an accessible register (such
2435 as $a3), then a "jr" using that register. This second case
2436 is almost impossible to distinguish from an indirect jump
2437 used for switch statements, so we don't even try. */
2438 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
2440 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
2444 /* This fencepost looks highly suspicious to me. Removing it also
2445 seems suspicious as it could affect remote debugging across serial
2449 heuristic_proc_start (CORE_ADDR pc
)
2456 pc
= gdbarch_addr_bits_remove (current_gdbarch
, pc
);
2458 fence
= start_pc
- heuristic_fence_post
;
2462 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
2463 fence
= VM_MIN_ADDRESS
;
2465 instlen
= mips_pc_is_mips16 (pc
) ? MIPS_INSN16_SIZE
: MIPS_INSN32_SIZE
;
2467 /* search back for previous return */
2468 for (start_pc
-= instlen
;; start_pc
-= instlen
)
2469 if (start_pc
< fence
)
2471 /* It's not clear to me why we reach this point when
2472 stop_soon, but with this test, at least we
2473 don't print out warnings for every child forked (eg, on
2474 decstation). 22apr93 rich@cygnus.com. */
2475 if (stop_soon
== NO_STOP_QUIETLY
)
2477 static int blurb_printed
= 0;
2479 warning (_("GDB can't find the start of the function at 0x%s."),
2484 /* This actually happens frequently in embedded
2485 development, when you first connect to a board
2486 and your stack pointer and pc are nowhere in
2487 particular. This message needs to give people
2488 in that situation enough information to
2489 determine that it's no big deal. */
2490 printf_filtered ("\n\
2491 GDB is unable to find the start of the function at 0x%s\n\
2492 and thus can't determine the size of that function's stack frame.\n\
2493 This means that GDB may be unable to access that stack frame, or\n\
2494 the frames below it.\n\
2495 This problem is most likely caused by an invalid program counter or\n\
2497 However, if you think GDB should simply search farther back\n\
2498 from 0x%s for code which looks like the beginning of a\n\
2499 function, you can increase the range of the search using the `set\n\
2500 heuristic-fence-post' command.\n", paddr_nz (pc
), paddr_nz (pc
));
2507 else if (mips_pc_is_mips16 (start_pc
))
2509 unsigned short inst
;
2511 /* On MIPS16, any one of the following is likely to be the
2512 start of a function:
2518 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
2519 inst
= mips_fetch_instruction (start_pc
);
2520 if ((inst
& 0xff80) == 0x6480) /* save */
2522 if (start_pc
- instlen
>= fence
)
2524 inst
= mips_fetch_instruction (start_pc
- instlen
);
2525 if ((inst
& 0xf800) == 0xf000) /* extend */
2526 start_pc
-= instlen
;
2530 else if (((inst
& 0xf81f) == 0xe809
2531 && (inst
& 0x700) != 0x700) /* entry */
2532 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
2533 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
2534 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
2536 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2537 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2542 else if (mips_about_to_return (start_pc
))
2544 /* Skip return and its delay slot. */
2545 start_pc
+= 2 * MIPS_INSN32_SIZE
;
2552 struct mips_objfile_private
2558 /* According to the current ABI, should the type be passed in a
2559 floating-point register (assuming that there is space)? When there
2560 is no FPU, FP are not even considered as possible candidates for
2561 FP registers and, consequently this returns false - forces FP
2562 arguments into integer registers. */
2565 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
2567 return ((typecode
== TYPE_CODE_FLT
2569 && (typecode
== TYPE_CODE_STRUCT
2570 || typecode
== TYPE_CODE_UNION
)
2571 && TYPE_NFIELDS (arg_type
) == 1
2572 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type
, 0)))
2574 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
2577 /* On o32, argument passing in GPRs depends on the alignment of the type being
2578 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2581 mips_type_needs_double_align (struct type
*type
)
2583 enum type_code typecode
= TYPE_CODE (type
);
2585 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2587 else if (typecode
== TYPE_CODE_STRUCT
)
2589 if (TYPE_NFIELDS (type
) < 1)
2591 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2593 else if (typecode
== TYPE_CODE_UNION
)
2597 n
= TYPE_NFIELDS (type
);
2598 for (i
= 0; i
< n
; i
++)
2599 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2606 /* Adjust the address downward (direction of stack growth) so that it
2607 is correctly aligned for a new stack frame. */
2609 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2611 return align_down (addr
, 16);
2615 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2616 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2617 int nargs
, struct value
**args
, CORE_ADDR sp
,
2618 int struct_return
, CORE_ADDR struct_addr
)
2624 int stack_offset
= 0;
2625 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2626 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
2627 int regsize
= mips_abi_regsize (gdbarch
);
2629 /* For shared libraries, "t9" needs to point at the function
2631 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
2633 /* Set the return address register to point to the entry point of
2634 the program, where a breakpoint lies in wait. */
2635 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
2637 /* First ensure that the stack and structure return address (if any)
2638 are properly aligned. The stack has to be at least 64-bit
2639 aligned even on 32-bit machines, because doubles must be 64-bit
2640 aligned. For n32 and n64, stack frames need to be 128-bit
2641 aligned, so we round to this widest known alignment. */
2643 sp
= align_down (sp
, 16);
2644 struct_addr
= align_down (struct_addr
, 16);
2646 /* Now make space on the stack for the args. We allocate more
2647 than necessary for EABI, because the first few arguments are
2648 passed in registers, but that's OK. */
2649 for (argnum
= 0; argnum
< nargs
; argnum
++)
2650 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), regsize
);
2651 sp
-= align_up (len
, 16);
2654 fprintf_unfiltered (gdb_stdlog
,
2655 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
2656 paddr_nz (sp
), (long) align_up (len
, 16));
2658 /* Initialize the integer and float register pointers. */
2659 argreg
= MIPS_A0_REGNUM
;
2660 float_argreg
= mips_fpa0_regnum (gdbarch
);
2662 /* The struct_return pointer occupies the first parameter-passing reg. */
2666 fprintf_unfiltered (gdb_stdlog
,
2667 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
2668 argreg
, paddr_nz (struct_addr
));
2669 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
2672 /* Now load as many as possible of the first arguments into
2673 registers, and push the rest onto the stack. Loop thru args
2674 from first to last. */
2675 for (argnum
= 0; argnum
< nargs
; argnum
++)
2677 const gdb_byte
*val
;
2678 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
2679 struct value
*arg
= args
[argnum
];
2680 struct type
*arg_type
= check_typedef (value_type (arg
));
2681 int len
= TYPE_LENGTH (arg_type
);
2682 enum type_code typecode
= TYPE_CODE (arg_type
);
2685 fprintf_unfiltered (gdb_stdlog
,
2686 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2687 argnum
+ 1, len
, (int) typecode
);
2689 /* The EABI passes structures that do not fit in a register by
2692 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2694 store_unsigned_integer (valbuf
, regsize
, VALUE_ADDRESS (arg
));
2695 typecode
= TYPE_CODE_PTR
;
2699 fprintf_unfiltered (gdb_stdlog
, " push");
2702 val
= value_contents (arg
);
2704 /* 32-bit ABIs always start floating point arguments in an
2705 even-numbered floating point register. Round the FP register
2706 up before the check to see if there are any FP registers
2707 left. Non MIPS_EABI targets also pass the FP in the integer
2708 registers so also round up normal registers. */
2709 if (regsize
< 8 && fp_register_arg_p (typecode
, arg_type
))
2711 if ((float_argreg
& 1))
2715 /* Floating point arguments passed in registers have to be
2716 treated specially. On 32-bit architectures, doubles
2717 are passed in register pairs; the even register gets
2718 the low word, and the odd register gets the high word.
2719 On non-EABI processors, the first two floating point arguments are
2720 also copied to general registers, because MIPS16 functions
2721 don't use float registers for arguments. This duplication of
2722 arguments in general registers can't hurt non-MIPS16 functions
2723 because those registers are normally skipped. */
2724 /* MIPS_EABI squeezes a struct that contains a single floating
2725 point value into an FP register instead of pushing it onto the
2727 if (fp_register_arg_p (typecode
, arg_type
)
2728 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2730 /* EABI32 will pass doubles in consecutive registers, even on
2731 64-bit cores. At one time, we used to check the size of
2732 `float_argreg' to determine whether or not to pass doubles
2733 in consecutive registers, but this is not sufficient for
2734 making the ABI determination. */
2735 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
2737 int low_offset
= gdbarch_byte_order (gdbarch
)
2738 == BFD_ENDIAN_BIG
? 4 : 0;
2739 unsigned long regval
;
2741 /* Write the low word of the double to the even register(s). */
2742 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2744 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2745 float_argreg
, phex (regval
, 4));
2746 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
2748 /* Write the high word of the double to the odd register(s). */
2749 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2751 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2752 float_argreg
, phex (regval
, 4));
2753 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
2757 /* This is a floating point value that fits entirely
2758 in a single register. */
2759 /* On 32 bit ABI's the float_argreg is further adjusted
2760 above to ensure that it is even register aligned. */
2761 LONGEST regval
= extract_unsigned_integer (val
, len
);
2763 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2764 float_argreg
, phex (regval
, len
));
2765 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
2770 /* Copy the argument to general registers or the stack in
2771 register-sized pieces. Large arguments are split between
2772 registers and stack. */
2773 /* Note: structs whose size is not a multiple of regsize
2774 are treated specially: Irix cc passes
2775 them in registers where gcc sometimes puts them on the
2776 stack. For maximum compatibility, we will put them in
2778 int odd_sized_struct
= (len
> regsize
&& len
% regsize
!= 0);
2780 /* Note: Floating-point values that didn't fit into an FP
2781 register are only written to memory. */
2784 /* Remember if the argument was written to the stack. */
2785 int stack_used_p
= 0;
2786 int partial_len
= (len
< regsize
? len
: regsize
);
2789 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2792 /* Write this portion of the argument to the stack. */
2793 if (argreg
> MIPS_LAST_ARG_REGNUM
2795 || fp_register_arg_p (typecode
, arg_type
))
2797 /* Should shorter than int integer values be
2798 promoted to int before being stored? */
2799 int longword_offset
= 0;
2802 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2805 && (typecode
== TYPE_CODE_INT
2806 || typecode
== TYPE_CODE_PTR
2807 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
2808 longword_offset
= regsize
- len
;
2809 else if ((typecode
== TYPE_CODE_STRUCT
2810 || typecode
== TYPE_CODE_UNION
)
2811 && TYPE_LENGTH (arg_type
) < regsize
)
2812 longword_offset
= regsize
- len
;
2817 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
2818 paddr_nz (stack_offset
));
2819 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
2820 paddr_nz (longword_offset
));
2823 addr
= sp
+ stack_offset
+ longword_offset
;
2828 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
2830 for (i
= 0; i
< partial_len
; i
++)
2832 fprintf_unfiltered (gdb_stdlog
, "%02x",
2836 write_memory (addr
, val
, partial_len
);
2839 /* Note!!! This is NOT an else clause. Odd sized
2840 structs may go thru BOTH paths. Floating point
2841 arguments will not. */
2842 /* Write this portion of the argument to a general
2843 purpose register. */
2844 if (argreg
<= MIPS_LAST_ARG_REGNUM
2845 && !fp_register_arg_p (typecode
, arg_type
))
2848 extract_unsigned_integer (val
, partial_len
);
2851 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2853 phex (regval
, regsize
));
2854 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
2861 /* Compute the the offset into the stack at which we
2862 will copy the next parameter.
2864 In the new EABI (and the NABI32), the stack_offset
2865 only needs to be adjusted when it has been used. */
2868 stack_offset
+= align_up (partial_len
, regsize
);
2872 fprintf_unfiltered (gdb_stdlog
, "\n");
2875 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
2877 /* Return adjusted stack pointer. */
2881 /* Determine the return value convention being used. */
2883 static enum return_value_convention
2884 mips_eabi_return_value (struct gdbarch
*gdbarch
,
2885 struct type
*type
, struct regcache
*regcache
,
2886 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2888 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
2889 return RETURN_VALUE_STRUCT_CONVENTION
;
2891 memset (readbuf
, 0, TYPE_LENGTH (type
));
2892 return RETURN_VALUE_REGISTER_CONVENTION
;
2896 /* N32/N64 ABI stuff. */
2898 /* Search for a naturally aligned double at OFFSET inside a struct
2899 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
2903 mips_n32n64_fp_arg_chunk_p (struct type
*arg_type
, int offset
)
2907 if (TYPE_CODE (arg_type
) != TYPE_CODE_STRUCT
)
2910 if (MIPS_FPU_TYPE
!= MIPS_FPU_DOUBLE
)
2913 if (TYPE_LENGTH (arg_type
) < offset
+ MIPS64_REGSIZE
)
2916 for (i
= 0; i
< TYPE_NFIELDS (arg_type
); i
++)
2919 struct type
*field_type
;
2921 /* We're only looking at normal fields. */
2922 if (TYPE_FIELD_STATIC (arg_type
, i
)
2923 || (TYPE_FIELD_BITPOS (arg_type
, i
) % 8) != 0)
2926 /* If we have gone past the offset, there is no double to pass. */
2927 pos
= TYPE_FIELD_BITPOS (arg_type
, i
) / 8;
2931 field_type
= check_typedef (TYPE_FIELD_TYPE (arg_type
, i
));
2933 /* If this field is entirely before the requested offset, go
2934 on to the next one. */
2935 if (pos
+ TYPE_LENGTH (field_type
) <= offset
)
2938 /* If this is our special aligned double, we can stop. */
2939 if (TYPE_CODE (field_type
) == TYPE_CODE_FLT
2940 && TYPE_LENGTH (field_type
) == MIPS64_REGSIZE
)
2943 /* This field starts at or before the requested offset, and
2944 overlaps it. If it is a structure, recurse inwards. */
2945 return mips_n32n64_fp_arg_chunk_p (field_type
, offset
- pos
);
2952 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2953 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2954 int nargs
, struct value
**args
, CORE_ADDR sp
,
2955 int struct_return
, CORE_ADDR struct_addr
)
2961 int stack_offset
= 0;
2962 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2963 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
2965 /* For shared libraries, "t9" needs to point at the function
2967 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
2969 /* Set the return address register to point to the entry point of
2970 the program, where a breakpoint lies in wait. */
2971 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
2973 /* First ensure that the stack and structure return address (if any)
2974 are properly aligned. The stack has to be at least 64-bit
2975 aligned even on 32-bit machines, because doubles must be 64-bit
2976 aligned. For n32 and n64, stack frames need to be 128-bit
2977 aligned, so we round to this widest known alignment. */
2979 sp
= align_down (sp
, 16);
2980 struct_addr
= align_down (struct_addr
, 16);
2982 /* Now make space on the stack for the args. */
2983 for (argnum
= 0; argnum
< nargs
; argnum
++)
2984 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), MIPS64_REGSIZE
);
2985 sp
-= align_up (len
, 16);
2988 fprintf_unfiltered (gdb_stdlog
,
2989 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
2990 paddr_nz (sp
), (long) align_up (len
, 16));
2992 /* Initialize the integer and float register pointers. */
2993 argreg
= MIPS_A0_REGNUM
;
2994 float_argreg
= mips_fpa0_regnum (gdbarch
);
2996 /* The struct_return pointer occupies the first parameter-passing reg. */
3000 fprintf_unfiltered (gdb_stdlog
,
3001 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
3002 argreg
, paddr_nz (struct_addr
));
3003 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3006 /* Now load as many as possible of the first arguments into
3007 registers, and push the rest onto the stack. Loop thru args
3008 from first to last. */
3009 for (argnum
= 0; argnum
< nargs
; argnum
++)
3011 const gdb_byte
*val
;
3012 struct value
*arg
= args
[argnum
];
3013 struct type
*arg_type
= check_typedef (value_type (arg
));
3014 int len
= TYPE_LENGTH (arg_type
);
3015 enum type_code typecode
= TYPE_CODE (arg_type
);
3018 fprintf_unfiltered (gdb_stdlog
,
3019 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3020 argnum
+ 1, len
, (int) typecode
);
3022 val
= value_contents (arg
);
3024 if (fp_register_arg_p (typecode
, arg_type
)
3025 && argreg
<= MIPS_LAST_ARG_REGNUM
)
3027 /* This is a floating point value that fits entirely
3028 in a single register. */
3029 LONGEST regval
= extract_unsigned_integer (val
, len
);
3031 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3032 float_argreg
, phex (regval
, len
));
3033 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
3036 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3037 argreg
, phex (regval
, len
));
3038 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3044 /* Copy the argument to general registers or the stack in
3045 register-sized pieces. Large arguments are split between
3046 registers and stack. */
3047 /* For N32/N64, structs, unions, or other composite types are
3048 treated as a sequence of doublewords, and are passed in integer
3049 or floating point registers as though they were simple scalar
3050 parameters to the extent that they fit, with any excess on the
3051 stack packed according to the normal memory layout of the
3053 The caller does not reserve space for the register arguments;
3054 the callee is responsible for reserving it if required. */
3055 /* Note: Floating-point values that didn't fit into an FP
3056 register are only written to memory. */
3059 /* Remember if the argument was written to the stack. */
3060 int stack_used_p
= 0;
3061 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
3064 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3067 if (fp_register_arg_p (typecode
, arg_type
))
3068 gdb_assert (argreg
> MIPS_LAST_ARG_REGNUM
);
3070 /* Write this portion of the argument to the stack. */
3071 if (argreg
> MIPS_LAST_ARG_REGNUM
)
3073 /* Should shorter than int integer values be
3074 promoted to int before being stored? */
3075 int longword_offset
= 0;
3078 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
3080 if ((typecode
== TYPE_CODE_INT
3081 || typecode
== TYPE_CODE_PTR
3082 || typecode
== TYPE_CODE_FLT
)
3084 longword_offset
= MIPS64_REGSIZE
- len
;
3089 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3090 paddr_nz (stack_offset
));
3091 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3092 paddr_nz (longword_offset
));
3095 addr
= sp
+ stack_offset
+ longword_offset
;
3100 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3102 for (i
= 0; i
< partial_len
; i
++)
3104 fprintf_unfiltered (gdb_stdlog
, "%02x",
3108 write_memory (addr
, val
, partial_len
);
3111 /* Note!!! This is NOT an else clause. Odd sized
3112 structs may go thru BOTH paths. */
3113 /* Write this portion of the argument to a general
3114 purpose register. */
3115 if (argreg
<= MIPS_LAST_ARG_REGNUM
)
3118 extract_unsigned_integer (val
, partial_len
);
3120 /* A non-floating-point argument being passed in a
3121 general register. If a struct or union, and if
3122 the remaining length is smaller than the register
3123 size, we have to adjust the register value on
3126 It does not seem to be necessary to do the
3127 same for integral types. */
3129 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
3130 && partial_len
< MIPS64_REGSIZE
3131 && (typecode
== TYPE_CODE_STRUCT
3132 || typecode
== TYPE_CODE_UNION
))
3133 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
3137 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3139 phex (regval
, MIPS64_REGSIZE
));
3140 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3142 if (mips_n32n64_fp_arg_chunk_p (arg_type
,
3143 TYPE_LENGTH (arg_type
) - len
))
3146 fprintf_filtered (gdb_stdlog
, " - fpreg=%d val=%s",
3148 phex (regval
, MIPS64_REGSIZE
));
3149 regcache_cooked_write_unsigned (regcache
, float_argreg
,
3160 /* Compute the the offset into the stack at which we
3161 will copy the next parameter.
3163 In N32 (N64?), the stack_offset only needs to be
3164 adjusted when it has been used. */
3167 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
3171 fprintf_unfiltered (gdb_stdlog
, "\n");
3174 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3176 /* Return adjusted stack pointer. */
3180 static enum return_value_convention
3181 mips_n32n64_return_value (struct gdbarch
*gdbarch
,
3182 struct type
*type
, struct regcache
*regcache
,
3183 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3185 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3187 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
3189 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
3190 if needed), as appropriate for the type. Composite results (struct,
3191 union, or array) are returned in $2/$f0 and $3/$f2 according to the
3194 * A struct with only one or two floating point fields is returned in $f0
3195 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
3198 * Any other struct or union results of at most 128 bits are returned in
3199 $2 (first 64 bits) and $3 (remainder, if necessary).
3201 * Larger composite results are handled by converting the function to a
3202 procedure with an implicit first parameter, which is a pointer to an area
3203 reserved by the caller to receive the result. [The o32-bit ABI requires
3204 that all composite results be handled by conversion to implicit first
3205 parameters. The MIPS/SGI Fortran implementation has always made a
3206 specific exception to return COMPLEX results in the floating point
3209 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
3210 || TYPE_LENGTH (type
) > 2 * MIPS64_REGSIZE
)
3211 return RETURN_VALUE_STRUCT_CONVENTION
;
3212 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3213 && TYPE_LENGTH (type
) == 16
3214 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3216 /* A 128-bit floating-point value fills both $f0 and $f2. The
3217 two registers are used in the same as memory order, so the
3218 eight bytes with the lower memory address are in $f0. */
3220 fprintf_unfiltered (gdb_stderr
, "Return float in $f0 and $f2\n");
3221 mips_xfer_register (gdbarch
, regcache
,
3222 gdbarch_num_regs (gdbarch
)
3223 + mips_regnum (gdbarch
)->fp0
,
3224 8, gdbarch_byte_order (gdbarch
),
3225 readbuf
, writebuf
, 0);
3226 mips_xfer_register (gdbarch
, regcache
,
3227 gdbarch_num_regs (gdbarch
)
3228 + mips_regnum (gdbarch
)->fp0
+ 2,
3229 8, gdbarch_byte_order (gdbarch
),
3230 readbuf
? readbuf
+ 8 : readbuf
,
3231 writebuf
? writebuf
+ 8 : writebuf
, 0);
3232 return RETURN_VALUE_REGISTER_CONVENTION
;
3234 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3235 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3237 /* A single or double floating-point value that fits in FP0. */
3239 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3240 mips_xfer_register (gdbarch
, regcache
,
3241 gdbarch_num_regs (gdbarch
)
3242 + mips_regnum (gdbarch
)->fp0
,
3244 gdbarch_byte_order (gdbarch
),
3245 readbuf
, writebuf
, 0);
3246 return RETURN_VALUE_REGISTER_CONVENTION
;
3248 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3249 && TYPE_NFIELDS (type
) <= 2
3250 && TYPE_NFIELDS (type
) >= 1
3251 && ((TYPE_NFIELDS (type
) == 1
3252 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
3254 || (TYPE_NFIELDS (type
) == 2
3255 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
3257 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 1)))
3259 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3261 /* A struct that contains one or two floats. Each value is part
3262 in the least significant part of their floating point
3266 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
3267 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3269 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3272 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3274 mips_xfer_register (gdbarch
, regcache
,
3275 gdbarch_num_regs (gdbarch
) + regnum
,
3276 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3277 gdbarch_byte_order (gdbarch
),
3278 readbuf
, writebuf
, offset
);
3280 return RETURN_VALUE_REGISTER_CONVENTION
;
3282 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3283 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3285 /* A structure or union. Extract the left justified value,
3286 regardless of the byte order. I.e. DO NOT USE
3290 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3291 offset
< TYPE_LENGTH (type
);
3292 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3294 int xfer
= register_size (gdbarch
, regnum
);
3295 if (offset
+ xfer
> TYPE_LENGTH (type
))
3296 xfer
= TYPE_LENGTH (type
) - offset
;
3298 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3299 offset
, xfer
, regnum
);
3300 mips_xfer_register (gdbarch
, regcache
,
3301 gdbarch_num_regs (gdbarch
) + regnum
,
3302 xfer
, BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
,
3305 return RETURN_VALUE_REGISTER_CONVENTION
;
3309 /* A scalar extract each part but least-significant-byte
3313 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3314 offset
< TYPE_LENGTH (type
);
3315 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3317 int xfer
= register_size (gdbarch
, regnum
);
3318 if (offset
+ xfer
> TYPE_LENGTH (type
))
3319 xfer
= TYPE_LENGTH (type
) - offset
;
3321 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3322 offset
, xfer
, regnum
);
3323 mips_xfer_register (gdbarch
, regcache
,
3324 gdbarch_num_regs (gdbarch
) + regnum
,
3325 xfer
, gdbarch_byte_order (gdbarch
),
3326 readbuf
, writebuf
, offset
);
3328 return RETURN_VALUE_REGISTER_CONVENTION
;
3332 /* O32 ABI stuff. */
3335 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3336 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3337 int nargs
, struct value
**args
, CORE_ADDR sp
,
3338 int struct_return
, CORE_ADDR struct_addr
)
3344 int stack_offset
= 0;
3345 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3346 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3348 /* For shared libraries, "t9" needs to point at the function
3350 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3352 /* Set the return address register to point to the entry point of
3353 the program, where a breakpoint lies in wait. */
3354 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3356 /* First ensure that the stack and structure return address (if any)
3357 are properly aligned. The stack has to be at least 64-bit
3358 aligned even on 32-bit machines, because doubles must be 64-bit
3359 aligned. For n32 and n64, stack frames need to be 128-bit
3360 aligned, so we round to this widest known alignment. */
3362 sp
= align_down (sp
, 16);
3363 struct_addr
= align_down (struct_addr
, 16);
3365 /* Now make space on the stack for the args. */
3366 for (argnum
= 0; argnum
< nargs
; argnum
++)
3368 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
3369 int arglen
= TYPE_LENGTH (arg_type
);
3371 /* Align to double-word if necessary. */
3372 if (mips_type_needs_double_align (arg_type
))
3373 len
= align_up (len
, MIPS32_REGSIZE
* 2);
3374 /* Allocate space on the stack. */
3375 len
+= align_up (arglen
, MIPS32_REGSIZE
);
3377 sp
-= align_up (len
, 16);
3380 fprintf_unfiltered (gdb_stdlog
,
3381 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
3382 paddr_nz (sp
), (long) align_up (len
, 16));
3384 /* Initialize the integer and float register pointers. */
3385 argreg
= MIPS_A0_REGNUM
;
3386 float_argreg
= mips_fpa0_regnum (gdbarch
);
3388 /* The struct_return pointer occupies the first parameter-passing reg. */
3392 fprintf_unfiltered (gdb_stdlog
,
3393 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
3394 argreg
, paddr_nz (struct_addr
));
3395 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3396 stack_offset
+= MIPS32_REGSIZE
;
3399 /* Now load as many as possible of the first arguments into
3400 registers, and push the rest onto the stack. Loop thru args
3401 from first to last. */
3402 for (argnum
= 0; argnum
< nargs
; argnum
++)
3404 const gdb_byte
*val
;
3405 struct value
*arg
= args
[argnum
];
3406 struct type
*arg_type
= check_typedef (value_type (arg
));
3407 int len
= TYPE_LENGTH (arg_type
);
3408 enum type_code typecode
= TYPE_CODE (arg_type
);
3411 fprintf_unfiltered (gdb_stdlog
,
3412 "mips_o32_push_dummy_call: %d len=%d type=%d",
3413 argnum
+ 1, len
, (int) typecode
);
3415 val
= value_contents (arg
);
3417 /* 32-bit ABIs always start floating point arguments in an
3418 even-numbered floating point register. Round the FP register
3419 up before the check to see if there are any FP registers
3420 left. O32/O64 targets also pass the FP in the integer
3421 registers so also round up normal registers. */
3422 if (fp_register_arg_p (typecode
, arg_type
))
3424 if ((float_argreg
& 1))
3428 /* Floating point arguments passed in registers have to be
3429 treated specially. On 32-bit architectures, doubles
3430 are passed in register pairs; the even register gets
3431 the low word, and the odd register gets the high word.
3432 On O32/O64, the first two floating point arguments are
3433 also copied to general registers, because MIPS16 functions
3434 don't use float registers for arguments. This duplication of
3435 arguments in general registers can't hurt non-MIPS16 functions
3436 because those registers are normally skipped. */
3438 if (fp_register_arg_p (typecode
, arg_type
)
3439 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3441 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
3443 int low_offset
= gdbarch_byte_order (gdbarch
)
3444 == BFD_ENDIAN_BIG
? 4 : 0;
3445 unsigned long regval
;
3447 /* Write the low word of the double to the even register(s). */
3448 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3450 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3451 float_argreg
, phex (regval
, 4));
3452 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3454 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3455 argreg
, phex (regval
, 4));
3456 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3458 /* Write the high word of the double to the odd register(s). */
3459 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3461 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3462 float_argreg
, phex (regval
, 4));
3463 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3466 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3467 argreg
, phex (regval
, 4));
3468 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3472 /* This is a floating point value that fits entirely
3473 in a single register. */
3474 /* On 32 bit ABI's the float_argreg is further adjusted
3475 above to ensure that it is even register aligned. */
3476 LONGEST regval
= extract_unsigned_integer (val
, len
);
3478 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3479 float_argreg
, phex (regval
, len
));
3480 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3481 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3482 registers for each argument. The below is (my
3483 guess) to ensure that the corresponding integer
3484 register has reserved the same space. */
3486 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3487 argreg
, phex (regval
, len
));
3488 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3491 /* Reserve space for the FP register. */
3492 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
3496 /* Copy the argument to general registers or the stack in
3497 register-sized pieces. Large arguments are split between
3498 registers and stack. */
3499 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
3500 are treated specially: Irix cc passes
3501 them in registers where gcc sometimes puts them on the
3502 stack. For maximum compatibility, we will put them in
3504 int odd_sized_struct
= (len
> MIPS32_REGSIZE
3505 && len
% MIPS32_REGSIZE
!= 0);
3506 /* Structures should be aligned to eight bytes (even arg registers)
3507 on MIPS_ABI_O32, if their first member has double precision. */
3508 if (mips_type_needs_double_align (arg_type
))
3513 stack_offset
+= MIPS32_REGSIZE
;
3518 /* Remember if the argument was written to the stack. */
3519 int stack_used_p
= 0;
3520 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
3523 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3526 /* Write this portion of the argument to the stack. */
3527 if (argreg
> MIPS_LAST_ARG_REGNUM
3528 || odd_sized_struct
)
3530 /* Should shorter than int integer values be
3531 promoted to int before being stored? */
3532 int longword_offset
= 0;
3538 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3539 paddr_nz (stack_offset
));
3540 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3541 paddr_nz (longword_offset
));
3544 addr
= sp
+ stack_offset
+ longword_offset
;
3549 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3551 for (i
= 0; i
< partial_len
; i
++)
3553 fprintf_unfiltered (gdb_stdlog
, "%02x",
3557 write_memory (addr
, val
, partial_len
);
3560 /* Note!!! This is NOT an else clause. Odd sized
3561 structs may go thru BOTH paths. */
3562 /* Write this portion of the argument to a general
3563 purpose register. */
3564 if (argreg
<= MIPS_LAST_ARG_REGNUM
)
3566 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3567 /* Value may need to be sign extended, because
3568 mips_isa_regsize() != mips_abi_regsize(). */
3570 /* A non-floating-point argument being passed in a
3571 general register. If a struct or union, and if
3572 the remaining length is smaller than the register
3573 size, we have to adjust the register value on
3576 It does not seem to be necessary to do the
3577 same for integral types.
3579 Also don't do this adjustment on O64 binaries.
3581 cagney/2001-07-23: gdb/179: Also, GCC, when
3582 outputting LE O32 with sizeof (struct) <
3583 mips_abi_regsize(), generates a left shift
3584 as part of storing the argument in a register
3585 (the left shift isn't generated when
3586 sizeof (struct) >= mips_abi_regsize()). Since
3587 it is quite possible that this is GCC
3588 contradicting the LE/O32 ABI, GDB has not been
3589 adjusted to accommodate this. Either someone
3590 needs to demonstrate that the LE/O32 ABI
3591 specifies such a left shift OR this new ABI gets
3592 identified as such and GDB gets tweaked
3595 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
3596 && partial_len
< MIPS32_REGSIZE
3597 && (typecode
== TYPE_CODE_STRUCT
3598 || typecode
== TYPE_CODE_UNION
))
3599 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
3603 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3605 phex (regval
, MIPS32_REGSIZE
));
3606 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3609 /* Prevent subsequent floating point arguments from
3610 being passed in floating point registers. */
3611 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3617 /* Compute the the offset into the stack at which we
3618 will copy the next parameter.
3620 In older ABIs, the caller reserved space for
3621 registers that contained arguments. This was loosely
3622 refered to as their "home". Consequently, space is
3623 always allocated. */
3625 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
3629 fprintf_unfiltered (gdb_stdlog
, "\n");
3632 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3634 /* Return adjusted stack pointer. */
3638 static enum return_value_convention
3639 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
3640 struct regcache
*regcache
,
3641 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3643 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3645 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3646 || TYPE_CODE (type
) == TYPE_CODE_UNION
3647 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3648 return RETURN_VALUE_STRUCT_CONVENTION
;
3649 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3650 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3652 /* A single-precision floating-point value. It fits in the
3653 least significant part of FP0. */
3655 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3656 mips_xfer_register (gdbarch
, regcache
,
3657 gdbarch_num_regs (gdbarch
)
3658 + mips_regnum (gdbarch
)->fp0
,
3660 gdbarch_byte_order (gdbarch
),
3661 readbuf
, writebuf
, 0);
3662 return RETURN_VALUE_REGISTER_CONVENTION
;
3664 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3665 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3667 /* A double-precision floating-point value. The most
3668 significant part goes in FP1, and the least significant in
3671 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
3672 switch (gdbarch_byte_order (gdbarch
))
3674 case BFD_ENDIAN_LITTLE
:
3675 mips_xfer_register (gdbarch
, regcache
,
3676 gdbarch_num_regs (gdbarch
)
3677 + mips_regnum (gdbarch
)->fp0
+
3678 0, 4, gdbarch_byte_order (gdbarch
),
3679 readbuf
, writebuf
, 0);
3680 mips_xfer_register (gdbarch
, regcache
,
3681 gdbarch_num_regs (gdbarch
)
3682 + mips_regnum (gdbarch
)->fp0
+ 1,
3683 4, gdbarch_byte_order (gdbarch
),
3684 readbuf
, writebuf
, 4);
3686 case BFD_ENDIAN_BIG
:
3687 mips_xfer_register (gdbarch
, regcache
,
3688 gdbarch_num_regs (gdbarch
)
3689 + mips_regnum (gdbarch
)->fp0
+ 1,
3690 4, gdbarch_byte_order (gdbarch
),
3691 readbuf
, writebuf
, 0);
3692 mips_xfer_register (gdbarch
, regcache
,
3693 gdbarch_num_regs (gdbarch
)
3694 + mips_regnum (gdbarch
)->fp0
+ 0,
3695 4, gdbarch_byte_order (gdbarch
),
3696 readbuf
, writebuf
, 4);
3699 internal_error (__FILE__
, __LINE__
, _("bad switch"));
3701 return RETURN_VALUE_REGISTER_CONVENTION
;
3704 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3705 && TYPE_NFIELDS (type
) <= 2
3706 && TYPE_NFIELDS (type
) >= 1
3707 && ((TYPE_NFIELDS (type
) == 1
3708 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3710 || (TYPE_NFIELDS (type
) == 2
3711 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3713 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
3715 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3717 /* A struct that contains one or two floats. Each value is part
3718 in the least significant part of their floating point
3720 gdb_byte reg
[MAX_REGISTER_SIZE
];
3723 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
3724 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3726 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3729 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3731 mips_xfer_register (gdbarch
, regcache
,
3732 gdbarch_num_regs (gdbarch
) + regnum
,
3733 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3734 gdbarch_byte_order (gdbarch
),
3735 readbuf
, writebuf
, offset
);
3737 return RETURN_VALUE_REGISTER_CONVENTION
;
3741 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3742 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3744 /* A structure or union. Extract the left justified value,
3745 regardless of the byte order. I.e. DO NOT USE
3749 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3750 offset
< TYPE_LENGTH (type
);
3751 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3753 int xfer
= register_size (gdbarch
, regnum
);
3754 if (offset
+ xfer
> TYPE_LENGTH (type
))
3755 xfer
= TYPE_LENGTH (type
) - offset
;
3757 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3758 offset
, xfer
, regnum
);
3759 mips_xfer_register (gdbarch
, regcache
,
3760 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
3761 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
3763 return RETURN_VALUE_REGISTER_CONVENTION
;
3768 /* A scalar extract each part but least-significant-byte
3769 justified. o32 thinks registers are 4 byte, regardless of
3773 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3774 offset
< TYPE_LENGTH (type
);
3775 offset
+= MIPS32_REGSIZE
, regnum
++)
3777 int xfer
= MIPS32_REGSIZE
;
3778 if (offset
+ xfer
> TYPE_LENGTH (type
))
3779 xfer
= TYPE_LENGTH (type
) - offset
;
3781 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3782 offset
, xfer
, regnum
);
3783 mips_xfer_register (gdbarch
, regcache
,
3784 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
3785 gdbarch_byte_order (gdbarch
),
3786 readbuf
, writebuf
, offset
);
3788 return RETURN_VALUE_REGISTER_CONVENTION
;
3792 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
3796 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3797 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3799 struct value
**args
, CORE_ADDR sp
,
3800 int struct_return
, CORE_ADDR struct_addr
)
3806 int stack_offset
= 0;
3807 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3808 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3810 /* For shared libraries, "t9" needs to point at the function
3812 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3814 /* Set the return address register to point to the entry point of
3815 the program, where a breakpoint lies in wait. */
3816 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3818 /* First ensure that the stack and structure return address (if any)
3819 are properly aligned. The stack has to be at least 64-bit
3820 aligned even on 32-bit machines, because doubles must be 64-bit
3821 aligned. For n32 and n64, stack frames need to be 128-bit
3822 aligned, so we round to this widest known alignment. */
3824 sp
= align_down (sp
, 16);
3825 struct_addr
= align_down (struct_addr
, 16);
3827 /* Now make space on the stack for the args. */
3828 for (argnum
= 0; argnum
< nargs
; argnum
++)
3830 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
3831 int arglen
= TYPE_LENGTH (arg_type
);
3833 /* Allocate space on the stack. */
3834 len
+= align_up (arglen
, MIPS64_REGSIZE
);
3836 sp
-= align_up (len
, 16);
3839 fprintf_unfiltered (gdb_stdlog
,
3840 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
3841 paddr_nz (sp
), (long) align_up (len
, 16));
3843 /* Initialize the integer and float register pointers. */
3844 argreg
= MIPS_A0_REGNUM
;
3845 float_argreg
= mips_fpa0_regnum (gdbarch
);
3847 /* The struct_return pointer occupies the first parameter-passing reg. */
3851 fprintf_unfiltered (gdb_stdlog
,
3852 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
3853 argreg
, paddr_nz (struct_addr
));
3854 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3855 stack_offset
+= MIPS64_REGSIZE
;
3858 /* Now load as many as possible of the first arguments into
3859 registers, and push the rest onto the stack. Loop thru args
3860 from first to last. */
3861 for (argnum
= 0; argnum
< nargs
; argnum
++)
3863 const gdb_byte
*val
;
3864 struct value
*arg
= args
[argnum
];
3865 struct type
*arg_type
= check_typedef (value_type (arg
));
3866 int len
= TYPE_LENGTH (arg_type
);
3867 enum type_code typecode
= TYPE_CODE (arg_type
);
3870 fprintf_unfiltered (gdb_stdlog
,
3871 "mips_o64_push_dummy_call: %d len=%d type=%d",
3872 argnum
+ 1, len
, (int) typecode
);
3874 val
= value_contents (arg
);
3876 /* Floating point arguments passed in registers have to be
3877 treated specially. On 32-bit architectures, doubles
3878 are passed in register pairs; the even register gets
3879 the low word, and the odd register gets the high word.
3880 On O32/O64, the first two floating point arguments are
3881 also copied to general registers, because MIPS16 functions
3882 don't use float registers for arguments. This duplication of
3883 arguments in general registers can't hurt non-MIPS16 functions
3884 because those registers are normally skipped. */
3886 if (fp_register_arg_p (typecode
, arg_type
)
3887 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3889 LONGEST regval
= extract_unsigned_integer (val
, len
);
3891 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3892 float_argreg
, phex (regval
, len
));
3893 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3895 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3896 argreg
, phex (regval
, len
));
3897 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3899 /* Reserve space for the FP register. */
3900 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
3904 /* Copy the argument to general registers or the stack in
3905 register-sized pieces. Large arguments are split between
3906 registers and stack. */
3907 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
3908 are treated specially: Irix cc passes them in registers
3909 where gcc sometimes puts them on the stack. For maximum
3910 compatibility, we will put them in both places. */
3911 int odd_sized_struct
= (len
> MIPS64_REGSIZE
3912 && len
% MIPS64_REGSIZE
!= 0);
3915 /* Remember if the argument was written to the stack. */
3916 int stack_used_p
= 0;
3917 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
3920 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3923 /* Write this portion of the argument to the stack. */
3924 if (argreg
> MIPS_LAST_ARG_REGNUM
3925 || odd_sized_struct
)
3927 /* Should shorter than int integer values be
3928 promoted to int before being stored? */
3929 int longword_offset
= 0;
3932 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
3934 if ((typecode
== TYPE_CODE_INT
3935 || typecode
== TYPE_CODE_PTR
3936 || typecode
== TYPE_CODE_FLT
)
3938 longword_offset
= MIPS64_REGSIZE
- len
;
3943 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3944 paddr_nz (stack_offset
));
3945 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3946 paddr_nz (longword_offset
));
3949 addr
= sp
+ stack_offset
+ longword_offset
;
3954 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3956 for (i
= 0; i
< partial_len
; i
++)
3958 fprintf_unfiltered (gdb_stdlog
, "%02x",
3962 write_memory (addr
, val
, partial_len
);
3965 /* Note!!! This is NOT an else clause. Odd sized
3966 structs may go thru BOTH paths. */
3967 /* Write this portion of the argument to a general
3968 purpose register. */
3969 if (argreg
<= MIPS_LAST_ARG_REGNUM
)
3971 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3972 /* Value may need to be sign extended, because
3973 mips_isa_regsize() != mips_abi_regsize(). */
3975 /* A non-floating-point argument being passed in a
3976 general register. If a struct or union, and if
3977 the remaining length is smaller than the register
3978 size, we have to adjust the register value on
3981 It does not seem to be necessary to do the
3982 same for integral types. */
3984 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
3985 && partial_len
< MIPS64_REGSIZE
3986 && (typecode
== TYPE_CODE_STRUCT
3987 || typecode
== TYPE_CODE_UNION
))
3988 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
3992 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3994 phex (regval
, MIPS64_REGSIZE
));
3995 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3998 /* Prevent subsequent floating point arguments from
3999 being passed in floating point registers. */
4000 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
4006 /* Compute the the offset into the stack at which we
4007 will copy the next parameter.
4009 In older ABIs, the caller reserved space for
4010 registers that contained arguments. This was loosely
4011 refered to as their "home". Consequently, space is
4012 always allocated. */
4014 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
4018 fprintf_unfiltered (gdb_stdlog
, "\n");
4021 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4023 /* Return adjusted stack pointer. */
4027 static enum return_value_convention
4028 mips_o64_return_value (struct gdbarch
*gdbarch
,
4029 struct type
*type
, struct regcache
*regcache
,
4030 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4032 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4034 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4035 || TYPE_CODE (type
) == TYPE_CODE_UNION
4036 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
4037 return RETURN_VALUE_STRUCT_CONVENTION
;
4038 else if (fp_register_arg_p (TYPE_CODE (type
), type
))
4040 /* A floating-point value. It fits in the least significant
4043 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4044 mips_xfer_register (gdbarch
, regcache
,
4045 gdbarch_num_regs (gdbarch
)
4046 + mips_regnum (gdbarch
)->fp0
,
4048 gdbarch_byte_order (gdbarch
),
4049 readbuf
, writebuf
, 0);
4050 return RETURN_VALUE_REGISTER_CONVENTION
;
4054 /* A scalar extract each part but least-significant-byte
4058 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
4059 offset
< TYPE_LENGTH (type
);
4060 offset
+= MIPS64_REGSIZE
, regnum
++)
4062 int xfer
= MIPS64_REGSIZE
;
4063 if (offset
+ xfer
> TYPE_LENGTH (type
))
4064 xfer
= TYPE_LENGTH (type
) - offset
;
4066 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4067 offset
, xfer
, regnum
);
4068 mips_xfer_register (gdbarch
, regcache
,
4069 gdbarch_num_regs (gdbarch
) + regnum
,
4070 xfer
, gdbarch_byte_order (gdbarch
),
4071 readbuf
, writebuf
, offset
);
4073 return RETURN_VALUE_REGISTER_CONVENTION
;
4077 /* Floating point register management.
4079 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
4080 64bit operations, these early MIPS cpus treat fp register pairs
4081 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
4082 registers and offer a compatibility mode that emulates the MIPS2 fp
4083 model. When operating in MIPS2 fp compat mode, later cpu's split
4084 double precision floats into two 32-bit chunks and store them in
4085 consecutive fp regs. To display 64-bit floats stored in this
4086 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
4087 Throw in user-configurable endianness and you have a real mess.
4089 The way this works is:
4090 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4091 double-precision value will be split across two logical registers.
4092 The lower-numbered logical register will hold the low-order bits,
4093 regardless of the processor's endianness.
4094 - If we are on a 64-bit processor, and we are looking for a
4095 single-precision value, it will be in the low ordered bits
4096 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4097 save slot in memory.
4098 - If we are in 64-bit mode, everything is straightforward.
4100 Note that this code only deals with "live" registers at the top of the
4101 stack. We will attempt to deal with saved registers later, when
4102 the raw/cooked register interface is in place. (We need a general
4103 interface that can deal with dynamic saved register sizes -- fp
4104 regs could be 32 bits wide in one frame and 64 on the frame above
4107 static struct type
*
4108 mips_float_register_type (void)
4110 return builtin_type_ieee_single
;
4113 static struct type
*
4114 mips_double_register_type (void)
4116 return builtin_type_ieee_double
;
4119 /* Copy a 32-bit single-precision value from the current frame
4120 into rare_buffer. */
4123 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
4124 gdb_byte
*rare_buffer
)
4126 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4127 int raw_size
= register_size (gdbarch
, regno
);
4128 gdb_byte
*raw_buffer
= alloca (raw_size
);
4130 if (!frame_register_read (frame
, regno
, raw_buffer
))
4131 error (_("can't read register %d (%s)"),
4132 regno
, gdbarch_register_name (gdbarch
, regno
));
4135 /* We have a 64-bit value for this register. Find the low-order
4139 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4144 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
4148 memcpy (rare_buffer
, raw_buffer
, 4);
4152 /* Copy a 64-bit double-precision value from the current frame into
4153 rare_buffer. This may include getting half of it from the next
4157 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
4158 gdb_byte
*rare_buffer
)
4160 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4161 int raw_size
= register_size (gdbarch
, regno
);
4163 if (raw_size
== 8 && !mips2_fp_compat (frame
))
4165 /* We have a 64-bit value for this register, and we should use
4167 if (!frame_register_read (frame
, regno
, rare_buffer
))
4168 error (_("can't read register %d (%s)"),
4169 regno
, gdbarch_register_name (gdbarch
, regno
));
4173 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
4175 if ((rawnum
- mips_regnum (gdbarch
)->fp0
) & 1)
4176 internal_error (__FILE__
, __LINE__
,
4177 _("mips_read_fp_register_double: bad access to "
4178 "odd-numbered FP register"));
4180 /* mips_read_fp_register_single will find the correct 32 bits from
4182 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4184 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
4185 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
4189 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
4190 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4196 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4198 { /* do values for FP (float) regs */
4199 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4200 gdb_byte
*raw_buffer
;
4201 double doub
, flt1
; /* doubles extracted from raw hex data */
4204 raw_buffer
= alloca (2 * register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
));
4206 fprintf_filtered (file
, "%s:", gdbarch_register_name (gdbarch
, regnum
));
4207 fprintf_filtered (file
, "%*s",
4208 4 - (int) strlen (gdbarch_register_name (gdbarch
, regnum
)),
4211 if (register_size (gdbarch
, regnum
) == 4 || mips2_fp_compat (frame
))
4213 /* 4-byte registers: Print hex and floating. Also print even
4214 numbered registers as doubles. */
4215 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4216 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4218 print_scalar_formatted (raw_buffer
, builtin_type_uint32
, 'x', 'w',
4221 fprintf_filtered (file
, " flt: ");
4223 fprintf_filtered (file
, " <invalid float> ");
4225 fprintf_filtered (file
, "%-17.9g", flt1
);
4227 if ((regnum
- gdbarch_num_regs (gdbarch
)) % 2 == 0)
4229 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4230 doub
= unpack_double (mips_double_register_type (), raw_buffer
,
4233 fprintf_filtered (file
, " dbl: ");
4235 fprintf_filtered (file
, "<invalid double>");
4237 fprintf_filtered (file
, "%-24.17g", doub
);
4242 /* Eight byte registers: print each one as hex, float and double. */
4243 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4244 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4246 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4247 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv2
);
4250 print_scalar_formatted (raw_buffer
, builtin_type_uint64
, 'x', 'g',
4253 fprintf_filtered (file
, " flt: ");
4255 fprintf_filtered (file
, "<invalid float>");
4257 fprintf_filtered (file
, "%-17.9g", flt1
);
4259 fprintf_filtered (file
, " dbl: ");
4261 fprintf_filtered (file
, "<invalid double>");
4263 fprintf_filtered (file
, "%-24.17g", doub
);
4268 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4271 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4272 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
4275 if (TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4277 mips_print_fp_register (file
, frame
, regnum
);
4281 /* Get the data in raw format. */
4282 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4284 fprintf_filtered (file
, "%s: [Invalid]",
4285 gdbarch_register_name (gdbarch
, regnum
));
4289 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
4291 /* The problem with printing numeric register names (r26, etc.) is that
4292 the user can't use them on input. Probably the best solution is to
4293 fix it so that either the numeric or the funky (a2, etc.) names
4294 are accepted on input. */
4295 if (regnum
< MIPS_NUMREGS
)
4296 fprintf_filtered (file
, "(r%d): ", regnum
);
4298 fprintf_filtered (file
, ": ");
4300 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4302 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
4306 print_scalar_formatted (raw_buffer
+ offset
,
4307 register_type (gdbarch
, regnum
), 'x', 0,
4311 /* Replacement for generic do_registers_info.
4312 Print regs in pretty columns. */
4315 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4318 fprintf_filtered (file
, " ");
4319 mips_print_fp_register (file
, frame
, regnum
);
4320 fprintf_filtered (file
, "\n");
4325 /* Print a row's worth of GP (int) registers, with name labels above */
4328 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4331 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4332 /* do values for GP (int) regs */
4333 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
4334 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols per row */
4338 /* For GP registers, we print a separate row of names above the vals */
4339 for (col
= 0, regnum
= start_regnum
;
4340 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
4341 + gdbarch_num_pseudo_regs (gdbarch
);
4344 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
4345 continue; /* unused register */
4346 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4348 break; /* end the row: reached FP register */
4349 /* Large registers are handled separately. */
4350 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
4353 break; /* End the row before this register. */
4355 /* Print this register on a row by itself. */
4356 mips_print_register (file
, frame
, regnum
);
4357 fprintf_filtered (file
, "\n");
4361 fprintf_filtered (file
, " ");
4362 fprintf_filtered (file
,
4363 mips_abi_regsize (gdbarch
) == 8 ? "%17s" : "%9s",
4364 gdbarch_register_name (gdbarch
, regnum
));
4371 /* print the R0 to R31 names */
4372 if ((start_regnum
% gdbarch_num_regs (gdbarch
)) < MIPS_NUMREGS
)
4373 fprintf_filtered (file
, "\n R%-4d",
4374 start_regnum
% gdbarch_num_regs (gdbarch
));
4376 fprintf_filtered (file
, "\n ");
4378 /* now print the values in hex, 4 or 8 to the row */
4379 for (col
= 0, regnum
= start_regnum
;
4380 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
4381 + gdbarch_num_pseudo_regs (gdbarch
);
4384 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
4385 continue; /* unused register */
4386 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4388 break; /* end row: reached FP register */
4389 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
4390 break; /* End row: large register. */
4392 /* OK: get the data in raw format. */
4393 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4394 error (_("can't read register %d (%s)"),
4395 regnum
, gdbarch_register_name (gdbarch
, regnum
));
4396 /* pad small registers */
4398 byte
< (mips_abi_regsize (gdbarch
)
4399 - register_size (gdbarch
, regnum
)); byte
++)
4400 printf_filtered (" ");
4401 /* Now print the register value in hex, endian order. */
4402 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4404 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
4405 byte
< register_size (gdbarch
, regnum
); byte
++)
4406 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4408 for (byte
= register_size (gdbarch
, regnum
) - 1;
4410 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4411 fprintf_filtered (file
, " ");
4414 if (col
> 0) /* ie. if we actually printed anything... */
4415 fprintf_filtered (file
, "\n");
4420 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4423 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4424 struct frame_info
*frame
, int regnum
, int all
)
4426 if (regnum
!= -1) /* do one specified register */
4428 gdb_assert (regnum
>= gdbarch_num_regs (gdbarch
));
4429 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
4430 error (_("Not a valid register for the current processor type"));
4432 mips_print_register (file
, frame
, regnum
);
4433 fprintf_filtered (file
, "\n");
4436 /* do all (or most) registers */
4438 regnum
= gdbarch_num_regs (gdbarch
);
4439 while (regnum
< gdbarch_num_regs (gdbarch
)
4440 + gdbarch_num_pseudo_regs (gdbarch
))
4442 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4445 if (all
) /* true for "INFO ALL-REGISTERS" command */
4446 regnum
= print_fp_register_row (file
, frame
, regnum
);
4448 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
4451 regnum
= print_gp_register_row (file
, frame
, regnum
);
4456 /* Is this a branch with a delay slot? */
4459 is_delayed (unsigned long insn
)
4462 for (i
= 0; i
< NUMOPCODES
; ++i
)
4463 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4464 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4466 return (i
< NUMOPCODES
4467 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4468 | INSN_COND_BRANCH_DELAY
4469 | INSN_COND_BRANCH_LIKELY
)));
4473 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
4474 struct frame_info
*frame
)
4476 CORE_ADDR pc
= get_frame_pc (frame
);
4477 gdb_byte buf
[MIPS_INSN32_SIZE
];
4479 /* There is no branch delay slot on MIPS16. */
4480 if (mips_pc_is_mips16 (pc
))
4483 if (!breakpoint_here_p (pc
+ 4))
4486 if (!safe_frame_unwind_memory (frame
, pc
, buf
, sizeof buf
))
4487 /* If error reading memory, guess that it is not a delayed
4490 return is_delayed (extract_unsigned_integer (buf
, sizeof buf
));
4493 /* To skip prologues, I use this predicate. Returns either PC itself
4494 if the code at PC does not look like a function prologue; otherwise
4495 returns an address that (if we're lucky) follows the prologue. If
4496 LENIENT, then we must skip everything which is involved in setting
4497 up the frame (it's OK to skip more, just so long as we don't skip
4498 anything which might clobber the registers which are being saved.
4499 We must skip more in the case where part of the prologue is in the
4500 delay slot of a non-prologue instruction). */
4503 mips_skip_prologue (CORE_ADDR pc
)
4506 CORE_ADDR func_addr
;
4508 /* See if we can determine the end of the prologue via the symbol table.
4509 If so, then return either PC, or the PC after the prologue, whichever
4511 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
4513 CORE_ADDR post_prologue_pc
= skip_prologue_using_sal (func_addr
);
4514 if (post_prologue_pc
!= 0)
4515 return max (pc
, post_prologue_pc
);
4518 /* Can't determine prologue from the symbol table, need to examine
4521 /* Find an upper limit on the function prologue using the debug
4522 information. If the debug information could not be used to provide
4523 that bound, then use an arbitrary large number as the upper bound. */
4524 limit_pc
= skip_prologue_using_sal (pc
);
4526 limit_pc
= pc
+ 100; /* Magic. */
4528 if (mips_pc_is_mips16 (pc
))
4529 return mips16_scan_prologue (pc
, limit_pc
, NULL
, NULL
);
4531 return mips32_scan_prologue (pc
, limit_pc
, NULL
, NULL
);
4534 /* Check whether the PC is in a function epilogue (32-bit version).
4535 This is a helper function for mips_in_function_epilogue_p. */
4537 mips32_in_function_epilogue_p (CORE_ADDR pc
)
4539 CORE_ADDR func_addr
= 0, func_end
= 0;
4541 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
4543 /* The MIPS epilogue is max. 12 bytes long. */
4544 CORE_ADDR addr
= func_end
- 12;
4546 if (addr
< func_addr
+ 4)
4547 addr
= func_addr
+ 4;
4551 for (; pc
< func_end
; pc
+= MIPS_INSN32_SIZE
)
4553 unsigned long high_word
;
4556 inst
= mips_fetch_instruction (pc
);
4557 high_word
= (inst
>> 16) & 0xffff;
4559 if (high_word
!= 0x27bd /* addiu $sp,$sp,offset */
4560 && high_word
!= 0x67bd /* daddiu $sp,$sp,offset */
4561 && inst
!= 0x03e00008 /* jr $ra */
4562 && inst
!= 0x00000000) /* nop */
4572 /* Check whether the PC is in a function epilogue (16-bit version).
4573 This is a helper function for mips_in_function_epilogue_p. */
4575 mips16_in_function_epilogue_p (CORE_ADDR pc
)
4577 CORE_ADDR func_addr
= 0, func_end
= 0;
4579 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
4581 /* The MIPS epilogue is max. 12 bytes long. */
4582 CORE_ADDR addr
= func_end
- 12;
4584 if (addr
< func_addr
+ 4)
4585 addr
= func_addr
+ 4;
4589 for (; pc
< func_end
; pc
+= MIPS_INSN16_SIZE
)
4591 unsigned short inst
;
4593 inst
= mips_fetch_instruction (pc
);
4595 if ((inst
& 0xf800) == 0xf000) /* extend */
4598 if (inst
!= 0x6300 /* addiu $sp,offset */
4599 && inst
!= 0xfb00 /* daddiu $sp,$sp,offset */
4600 && inst
!= 0xe820 /* jr $ra */
4601 && inst
!= 0xe8a0 /* jrc $ra */
4602 && inst
!= 0x6500) /* nop */
4612 /* The epilogue is defined here as the area at the end of a function,
4613 after an instruction which destroys the function's stack frame. */
4615 mips_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4617 if (mips_pc_is_mips16 (pc
))
4618 return mips16_in_function_epilogue_p (pc
);
4620 return mips32_in_function_epilogue_p (pc
);
4623 /* Root of all "set mips "/"show mips " commands. This will eventually be
4624 used for all MIPS-specific commands. */
4627 show_mips_command (char *args
, int from_tty
)
4629 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
4633 set_mips_command (char *args
, int from_tty
)
4636 ("\"set mips\" must be followed by an appropriate subcommand.\n");
4637 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
4640 /* Commands to show/set the MIPS FPU type. */
4643 show_mipsfpu_command (char *args
, int from_tty
)
4646 switch (MIPS_FPU_TYPE
)
4648 case MIPS_FPU_SINGLE
:
4649 fpu
= "single-precision";
4651 case MIPS_FPU_DOUBLE
:
4652 fpu
= "double-precision";
4655 fpu
= "absent (none)";
4658 internal_error (__FILE__
, __LINE__
, _("bad switch"));
4660 if (mips_fpu_type_auto
)
4662 ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
4666 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
4671 set_mipsfpu_command (char *args
, int from_tty
)
4674 ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
4675 show_mipsfpu_command (args
, from_tty
);
4679 set_mipsfpu_single_command (char *args
, int from_tty
)
4681 struct gdbarch_info info
;
4682 gdbarch_info_init (&info
);
4683 mips_fpu_type
= MIPS_FPU_SINGLE
;
4684 mips_fpu_type_auto
= 0;
4685 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4686 instead of relying on globals. Doing that would let generic code
4687 handle the search for this specific architecture. */
4688 if (!gdbarch_update_p (info
))
4689 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4693 set_mipsfpu_double_command (char *args
, int from_tty
)
4695 struct gdbarch_info info
;
4696 gdbarch_info_init (&info
);
4697 mips_fpu_type
= MIPS_FPU_DOUBLE
;
4698 mips_fpu_type_auto
= 0;
4699 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4700 instead of relying on globals. Doing that would let generic code
4701 handle the search for this specific architecture. */
4702 if (!gdbarch_update_p (info
))
4703 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4707 set_mipsfpu_none_command (char *args
, int from_tty
)
4709 struct gdbarch_info info
;
4710 gdbarch_info_init (&info
);
4711 mips_fpu_type
= MIPS_FPU_NONE
;
4712 mips_fpu_type_auto
= 0;
4713 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4714 instead of relying on globals. Doing that would let generic code
4715 handle the search for this specific architecture. */
4716 if (!gdbarch_update_p (info
))
4717 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4721 set_mipsfpu_auto_command (char *args
, int from_tty
)
4723 mips_fpu_type_auto
= 1;
4726 /* Attempt to identify the particular processor model by reading the
4727 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
4728 the relevant processor still exists (it dates back to '94) and
4729 secondly this is not the way to do this. The processor type should
4730 be set by forcing an architecture change. */
4733 deprecated_mips_set_processor_regs_hack (void)
4735 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4738 regcache_cooked_read_unsigned (get_current_regcache (),
4739 MIPS_PRID_REGNUM
, &prid
);
4740 if ((prid
& ~0xf) == 0x700)
4741 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
4744 /* Just like reinit_frame_cache, but with the right arguments to be
4745 callable as an sfunc. */
4748 reinit_frame_cache_sfunc (char *args
, int from_tty
,
4749 struct cmd_list_element
*c
)
4751 reinit_frame_cache ();
4755 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
4757 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4759 /* FIXME: cagney/2003-06-26: Is this even necessary? The
4760 disassembler needs to be able to locally determine the ISA, and
4761 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
4763 if (mips_pc_is_mips16 (memaddr
))
4764 info
->mach
= bfd_mach_mips16
;
4766 /* Round down the instruction address to the appropriate boundary. */
4767 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
4769 /* Set the disassembler options. */
4770 if (tdep
->mips_abi
== MIPS_ABI_N32
|| tdep
->mips_abi
== MIPS_ABI_N64
)
4772 /* Set up the disassembler info, so that we get the right
4773 register names from libopcodes. */
4774 if (tdep
->mips_abi
== MIPS_ABI_N32
)
4775 info
->disassembler_options
= "gpr-names=n32";
4777 info
->disassembler_options
= "gpr-names=64";
4778 info
->flavour
= bfd_target_elf_flavour
;
4781 /* This string is not recognized explicitly by the disassembler,
4782 but it tells the disassembler to not try to guess the ABI from
4783 the bfd elf headers, such that, if the user overrides the ABI
4784 of a program linked as NewABI, the disassembly will follow the
4785 register naming conventions specified by the user. */
4786 info
->disassembler_options
= "gpr-names=32";
4788 /* Call the appropriate disassembler based on the target endian-ness. */
4789 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
4790 return print_insn_big_mips (memaddr
, info
);
4792 return print_insn_little_mips (memaddr
, info
);
4795 /* This function implements gdbarch_breakpoint_from_pc. It uses the program
4796 counter value to determine whether a 16- or 32-bit breakpoint should be used.
4797 It returns a pointer to a string of bytes that encode a breakpoint
4798 instruction, stores the length of the string to *lenptr, and adjusts pc (if
4799 necessary) to point to the actual memory location where the breakpoint
4800 should be inserted. */
4802 static const gdb_byte
*
4803 mips_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
, int *lenptr
)
4805 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4807 if (mips_pc_is_mips16 (*pcptr
))
4809 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
4810 *pcptr
= unmake_mips16_addr (*pcptr
);
4811 *lenptr
= sizeof (mips16_big_breakpoint
);
4812 return mips16_big_breakpoint
;
4816 /* The IDT board uses an unusual breakpoint value, and
4817 sometimes gets confused when it sees the usual MIPS
4818 breakpoint instruction. */
4819 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
4820 static gdb_byte pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
4821 static gdb_byte idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
4823 *lenptr
= sizeof (big_breakpoint
);
4825 if (strcmp (target_shortname
, "mips") == 0)
4826 return idt_big_breakpoint
;
4827 else if (strcmp (target_shortname
, "ddb") == 0
4828 || strcmp (target_shortname
, "pmon") == 0
4829 || strcmp (target_shortname
, "lsi") == 0)
4830 return pmon_big_breakpoint
;
4832 return big_breakpoint
;
4837 if (mips_pc_is_mips16 (*pcptr
))
4839 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
4840 *pcptr
= unmake_mips16_addr (*pcptr
);
4841 *lenptr
= sizeof (mips16_little_breakpoint
);
4842 return mips16_little_breakpoint
;
4846 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
4847 static gdb_byte pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
4848 static gdb_byte idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
4850 *lenptr
= sizeof (little_breakpoint
);
4852 if (strcmp (target_shortname
, "mips") == 0)
4853 return idt_little_breakpoint
;
4854 else if (strcmp (target_shortname
, "ddb") == 0
4855 || strcmp (target_shortname
, "pmon") == 0
4856 || strcmp (target_shortname
, "lsi") == 0)
4857 return pmon_little_breakpoint
;
4859 return little_breakpoint
;
4864 /* If PC is in a mips16 call or return stub, return the address of the target
4865 PC, which is either the callee or the caller. There are several
4866 cases which must be handled:
4868 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
4869 target PC is in $31 ($ra).
4870 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
4871 and the target PC is in $2.
4872 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4873 before the jal instruction, this is effectively a call stub
4874 and the the target PC is in $2. Otherwise this is effectively
4875 a return stub and the target PC is in $18.
4877 See the source code for the stubs in gcc/config/mips/mips16.S for
4881 mips_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
4884 CORE_ADDR start_addr
;
4886 /* Find the starting address and name of the function containing the PC. */
4887 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
4890 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
4891 target PC is in $31 ($ra). */
4892 if (strcmp (name
, "__mips16_ret_sf") == 0
4893 || strcmp (name
, "__mips16_ret_df") == 0)
4894 return get_frame_register_signed (frame
, MIPS_RA_REGNUM
);
4896 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
4898 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
4899 and the target PC is in $2. */
4900 if (name
[19] >= '0' && name
[19] <= '9')
4901 return get_frame_register_signed (frame
, 2);
4903 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4904 before the jal instruction, this is effectively a call stub
4905 and the the target PC is in $2. Otherwise this is effectively
4906 a return stub and the target PC is in $18. */
4907 else if (name
[19] == 's' || name
[19] == 'd')
4909 if (pc
== start_addr
)
4911 /* Check if the target of the stub is a compiler-generated
4912 stub. Such a stub for a function bar might have a name
4913 like __fn_stub_bar, and might look like this:
4918 la $1,bar (becomes a lui/addiu pair)
4920 So scan down to the lui/addi and extract the target
4921 address from those two instructions. */
4923 CORE_ADDR target_pc
= get_frame_register_signed (frame
, 2);
4927 /* See if the name of the target function is __fn_stub_*. */
4928 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) ==
4931 if (strncmp (name
, "__fn_stub_", 10) != 0
4932 && strcmp (name
, "etext") != 0
4933 && strcmp (name
, "_etext") != 0)
4936 /* Scan through this _fn_stub_ code for the lui/addiu pair.
4937 The limit on the search is arbitrarily set to 20
4938 instructions. FIXME. */
4939 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSN32_SIZE
)
4941 inst
= mips_fetch_instruction (target_pc
);
4942 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
4943 pc
= (inst
<< 16) & 0xffff0000; /* high word */
4944 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
4945 return pc
| (inst
& 0xffff); /* low word */
4948 /* Couldn't find the lui/addui pair, so return stub address. */
4952 /* This is the 'return' part of a call stub. The return
4953 address is in $r18. */
4954 return get_frame_register_signed (frame
, 18);
4957 return 0; /* not a stub */
4960 /* Convert a dbx stab register number (from `r' declaration) to a GDB
4961 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
4964 mips_stab_reg_to_regnum (int num
)
4967 if (num
>= 0 && num
< 32)
4969 else if (num
>= 38 && num
< 70)
4970 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 38;
4972 regnum
= mips_regnum (current_gdbarch
)->hi
;
4974 regnum
= mips_regnum (current_gdbarch
)->lo
;
4976 /* This will hopefully (eventually) provoke a warning. Should
4977 we be calling complaint() here? */
4978 return gdbarch_num_regs (current_gdbarch
)
4979 + gdbarch_num_pseudo_regs (current_gdbarch
);
4980 return gdbarch_num_regs (current_gdbarch
) + regnum
;
4984 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
4985 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
4988 mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num
)
4991 if (num
>= 0 && num
< 32)
4993 else if (num
>= 32 && num
< 64)
4994 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 32;
4996 regnum
= mips_regnum (current_gdbarch
)->hi
;
4998 regnum
= mips_regnum (current_gdbarch
)->lo
;
5000 /* This will hopefully (eventually) provoke a warning. Should we
5001 be calling complaint() here? */
5002 return gdbarch_num_regs (current_gdbarch
)
5003 + gdbarch_num_pseudo_regs (current_gdbarch
);
5004 return gdbarch_num_regs (current_gdbarch
) + regnum
;
5008 mips_register_sim_regno (int regnum
)
5010 /* Only makes sense to supply raw registers. */
5011 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (current_gdbarch
));
5012 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5013 decide if it is valid. Should instead define a standard sim/gdb
5014 register numbering scheme. */
5015 if (gdbarch_register_name (current_gdbarch
,
5017 (current_gdbarch
) + regnum
) != NULL
5018 && gdbarch_register_name (current_gdbarch
,
5020 (current_gdbarch
) + regnum
)[0] != '\0')
5023 return LEGACY_SIM_REGNO_IGNORE
;
5027 /* Convert an integer into an address. Extracting the value signed
5028 guarantees a correctly sign extended address. */
5031 mips_integer_to_address (struct gdbarch
*gdbarch
,
5032 struct type
*type
, const gdb_byte
*buf
)
5034 return (CORE_ADDR
) extract_signed_integer (buf
, TYPE_LENGTH (type
));
5037 /* Dummy virtual frame pointer method. This is no more or less accurate
5038 than most other architectures; we just need to be explicit about it,
5039 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
5040 an assertion failure. */
5043 mips_virtual_frame_pointer (struct gdbarch
*gdbarch
,
5044 CORE_ADDR pc
, int *reg
, LONGEST
*offset
)
5046 *reg
= MIPS_SP_REGNUM
;
5051 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
5053 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
5054 const char *name
= bfd_get_section_name (abfd
, sect
);
5056 if (*abip
!= MIPS_ABI_UNKNOWN
)
5059 if (strncmp (name
, ".mdebug.", 8) != 0)
5062 if (strcmp (name
, ".mdebug.abi32") == 0)
5063 *abip
= MIPS_ABI_O32
;
5064 else if (strcmp (name
, ".mdebug.abiN32") == 0)
5065 *abip
= MIPS_ABI_N32
;
5066 else if (strcmp (name
, ".mdebug.abi64") == 0)
5067 *abip
= MIPS_ABI_N64
;
5068 else if (strcmp (name
, ".mdebug.abiO64") == 0)
5069 *abip
= MIPS_ABI_O64
;
5070 else if (strcmp (name
, ".mdebug.eabi32") == 0)
5071 *abip
= MIPS_ABI_EABI32
;
5072 else if (strcmp (name
, ".mdebug.eabi64") == 0)
5073 *abip
= MIPS_ABI_EABI64
;
5075 warning (_("unsupported ABI %s."), name
+ 8);
5079 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
5081 int *lbp
= (int *) obj
;
5082 const char *name
= bfd_get_section_name (abfd
, sect
);
5084 if (strncmp (name
, ".gcc_compiled_long32", 20) == 0)
5086 else if (strncmp (name
, ".gcc_compiled_long64", 20) == 0)
5088 else if (strncmp (name
, ".gcc_compiled_long", 18) == 0)
5089 warning (_("unrecognized .gcc_compiled_longXX"));
5092 static enum mips_abi
5093 global_mips_abi (void)
5097 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
5098 if (mips_abi_strings
[i
] == mips_abi_string
)
5099 return (enum mips_abi
) i
;
5101 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
5105 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
5107 /* If the size matches the set of 32-bit or 64-bit integer registers,
5108 assume that's what we've got. */
5109 register_remote_g_packet_guess (gdbarch
, 38 * 4, mips_tdesc_gp32
);
5110 register_remote_g_packet_guess (gdbarch
, 38 * 8, mips_tdesc_gp64
);
5112 /* If the size matches the full set of registers GDB traditionally
5113 knows about, including floating point, for either 32-bit or
5114 64-bit, assume that's what we've got. */
5115 register_remote_g_packet_guess (gdbarch
, 90 * 4, mips_tdesc_gp32
);
5116 register_remote_g_packet_guess (gdbarch
, 90 * 8, mips_tdesc_gp64
);
5118 /* Otherwise we don't have a useful guess. */
5121 static struct value
*
5122 value_of_mips_user_reg (struct frame_info
*frame
, const void *baton
)
5124 const int *reg_p
= baton
;
5125 return value_of_register (*reg_p
, frame
);
5128 static struct gdbarch
*
5129 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5131 struct gdbarch
*gdbarch
;
5132 struct gdbarch_tdep
*tdep
;
5134 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
5136 enum mips_fpu_type fpu_type
;
5137 struct tdesc_arch_data
*tdesc_data
= NULL
;
5138 int elf_fpu_type
= 0;
5140 /* Check any target description for validity. */
5141 if (tdesc_has_registers (info
.target_desc
))
5143 static const char *const mips_gprs
[] = {
5144 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5145 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5146 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5147 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
5149 static const char *const mips_fprs
[] = {
5150 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
5151 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
5152 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
5153 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
5156 const struct tdesc_feature
*feature
;
5159 feature
= tdesc_find_feature (info
.target_desc
,
5160 "org.gnu.gdb.mips.cpu");
5161 if (feature
== NULL
)
5164 tdesc_data
= tdesc_data_alloc ();
5167 for (i
= MIPS_ZERO_REGNUM
; i
<= MIPS_RA_REGNUM
; i
++)
5168 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
5172 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5173 MIPS_EMBED_LO_REGNUM
, "lo");
5174 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5175 MIPS_EMBED_HI_REGNUM
, "hi");
5176 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5177 MIPS_EMBED_PC_REGNUM
, "pc");
5181 tdesc_data_cleanup (tdesc_data
);
5185 feature
= tdesc_find_feature (info
.target_desc
,
5186 "org.gnu.gdb.mips.cp0");
5187 if (feature
== NULL
)
5189 tdesc_data_cleanup (tdesc_data
);
5194 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5195 MIPS_EMBED_BADVADDR_REGNUM
,
5197 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5198 MIPS_PS_REGNUM
, "status");
5199 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5200 MIPS_EMBED_CAUSE_REGNUM
, "cause");
5204 tdesc_data_cleanup (tdesc_data
);
5208 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
5209 backend is not prepared for that, though. */
5210 feature
= tdesc_find_feature (info
.target_desc
,
5211 "org.gnu.gdb.mips.fpu");
5212 if (feature
== NULL
)
5214 tdesc_data_cleanup (tdesc_data
);
5219 for (i
= 0; i
< 32; i
++)
5220 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5221 i
+ MIPS_EMBED_FP0_REGNUM
,
5224 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5225 MIPS_EMBED_FP0_REGNUM
+ 32, "fcsr");
5226 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5227 MIPS_EMBED_FP0_REGNUM
+ 33, "fir");
5231 tdesc_data_cleanup (tdesc_data
);
5235 /* It would be nice to detect an attempt to use a 64-bit ABI
5236 when only 32-bit registers are provided. */
5239 /* First of all, extract the elf_flags, if available. */
5240 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5241 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
5242 else if (arches
!= NULL
)
5243 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
5247 fprintf_unfiltered (gdb_stdlog
,
5248 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
5250 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5251 switch ((elf_flags
& EF_MIPS_ABI
))
5253 case E_MIPS_ABI_O32
:
5254 found_abi
= MIPS_ABI_O32
;
5256 case E_MIPS_ABI_O64
:
5257 found_abi
= MIPS_ABI_O64
;
5259 case E_MIPS_ABI_EABI32
:
5260 found_abi
= MIPS_ABI_EABI32
;
5262 case E_MIPS_ABI_EABI64
:
5263 found_abi
= MIPS_ABI_EABI64
;
5266 if ((elf_flags
& EF_MIPS_ABI2
))
5267 found_abi
= MIPS_ABI_N32
;
5269 found_abi
= MIPS_ABI_UNKNOWN
;
5273 /* GCC creates a pseudo-section whose name describes the ABI. */
5274 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
5275 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
5277 /* If we have no useful BFD information, use the ABI from the last
5278 MIPS architecture (if there is one). */
5279 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
5280 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
5282 /* Try the architecture for any hint of the correct ABI. */
5283 if (found_abi
== MIPS_ABI_UNKNOWN
5284 && info
.bfd_arch_info
!= NULL
5285 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5287 switch (info
.bfd_arch_info
->mach
)
5289 case bfd_mach_mips3900
:
5290 found_abi
= MIPS_ABI_EABI32
;
5292 case bfd_mach_mips4100
:
5293 case bfd_mach_mips5000
:
5294 found_abi
= MIPS_ABI_EABI64
;
5296 case bfd_mach_mips8000
:
5297 case bfd_mach_mips10000
:
5298 /* On Irix, ELF64 executables use the N64 ABI. The
5299 pseudo-sections which describe the ABI aren't present
5300 on IRIX. (Even for executables created by gcc.) */
5301 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5302 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5303 found_abi
= MIPS_ABI_N64
;
5305 found_abi
= MIPS_ABI_N32
;
5310 /* Default 64-bit objects to N64 instead of O32. */
5311 if (found_abi
== MIPS_ABI_UNKNOWN
5312 && info
.abfd
!= NULL
5313 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5314 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5315 found_abi
= MIPS_ABI_N64
;
5318 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
5321 /* What has the user specified from the command line? */
5322 wanted_abi
= global_mips_abi ();
5324 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
5327 /* Now that we have found what the ABI for this binary would be,
5328 check whether the user is overriding it. */
5329 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
5330 mips_abi
= wanted_abi
;
5331 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
5332 mips_abi
= found_abi
;
5334 mips_abi
= MIPS_ABI_O32
;
5336 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
5339 /* Also used when doing an architecture lookup. */
5341 fprintf_unfiltered (gdb_stdlog
,
5342 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
5343 mips64_transfers_32bit_regs_p
);
5345 /* Determine the MIPS FPU type. */
5348 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5349 elf_fpu_type
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
5350 Tag_GNU_MIPS_ABI_FP
);
5351 #endif /* HAVE_ELF */
5353 if (!mips_fpu_type_auto
)
5354 fpu_type
= mips_fpu_type
;
5355 else if (elf_fpu_type
!= 0)
5357 switch (elf_fpu_type
)
5360 fpu_type
= MIPS_FPU_DOUBLE
;
5363 fpu_type
= MIPS_FPU_SINGLE
;
5367 /* Soft float or unknown. */
5368 fpu_type
= MIPS_FPU_NONE
;
5372 else if (info
.bfd_arch_info
!= NULL
5373 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5374 switch (info
.bfd_arch_info
->mach
)
5376 case bfd_mach_mips3900
:
5377 case bfd_mach_mips4100
:
5378 case bfd_mach_mips4111
:
5379 case bfd_mach_mips4120
:
5380 fpu_type
= MIPS_FPU_NONE
;
5382 case bfd_mach_mips4650
:
5383 fpu_type
= MIPS_FPU_SINGLE
;
5386 fpu_type
= MIPS_FPU_DOUBLE
;
5389 else if (arches
!= NULL
)
5390 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
5392 fpu_type
= MIPS_FPU_DOUBLE
;
5394 fprintf_unfiltered (gdb_stdlog
,
5395 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
5397 /* Check for blatant incompatibilities. */
5399 /* If we have only 32-bit registers, then we can't debug a 64-bit
5401 if (info
.target_desc
5402 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
5403 && mips_abi
!= MIPS_ABI_EABI32
5404 && mips_abi
!= MIPS_ABI_O32
)
5406 if (tdesc_data
!= NULL
)
5407 tdesc_data_cleanup (tdesc_data
);
5411 /* try to find a pre-existing architecture */
5412 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
5414 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
5416 /* MIPS needs to be pedantic about which ABI the object is
5418 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
5420 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
5422 /* Need to be pedantic about which register virtual size is
5424 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
5425 != mips64_transfers_32bit_regs_p
)
5427 /* Be pedantic about which FPU is selected. */
5428 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
5431 if (tdesc_data
!= NULL
)
5432 tdesc_data_cleanup (tdesc_data
);
5433 return arches
->gdbarch
;
5436 /* Need a new architecture. Fill in a target specific vector. */
5437 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
5438 gdbarch
= gdbarch_alloc (&info
, tdep
);
5439 tdep
->elf_flags
= elf_flags
;
5440 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
5441 tdep
->found_abi
= found_abi
;
5442 tdep
->mips_abi
= mips_abi
;
5443 tdep
->mips_fpu_type
= fpu_type
;
5444 tdep
->register_size_valid_p
= 0;
5445 tdep
->register_size
= 0;
5447 if (info
.target_desc
)
5449 /* Some useful properties can be inferred from the target. */
5450 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
5452 tdep
->register_size_valid_p
= 1;
5453 tdep
->register_size
= 4;
5455 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
5457 tdep
->register_size_valid_p
= 1;
5458 tdep
->register_size
= 8;
5462 /* Initially set everything according to the default ABI/ISA. */
5463 set_gdbarch_short_bit (gdbarch
, 16);
5464 set_gdbarch_int_bit (gdbarch
, 32);
5465 set_gdbarch_float_bit (gdbarch
, 32);
5466 set_gdbarch_double_bit (gdbarch
, 64);
5467 set_gdbarch_long_double_bit (gdbarch
, 64);
5468 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
5469 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
5470 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
5472 set_gdbarch_elf_make_msymbol_special (gdbarch
,
5473 mips_elf_make_msymbol_special
);
5475 /* Fill in the OS dependant register numbers and names. */
5477 const char **reg_names
;
5478 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
5479 struct mips_regnum
);
5480 if (tdesc_has_registers (info
.target_desc
))
5482 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
5483 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
5484 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
5485 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
5486 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
5487 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
5488 regnum
->fp_control_status
= 70;
5489 regnum
->fp_implementation_revision
= 71;
5490 num_regs
= MIPS_LAST_EMBED_REGNUM
+ 1;
5493 else if (info
.osabi
== GDB_OSABI_IRIX
)
5498 regnum
->badvaddr
= 66;
5501 regnum
->fp_control_status
= 69;
5502 regnum
->fp_implementation_revision
= 70;
5504 reg_names
= mips_irix_reg_names
;
5508 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
5509 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
5510 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
5511 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
5512 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
5513 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
5514 regnum
->fp_control_status
= 70;
5515 regnum
->fp_implementation_revision
= 71;
5517 if (info
.bfd_arch_info
!= NULL
5518 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
5519 reg_names
= mips_tx39_reg_names
;
5521 reg_names
= mips_generic_reg_names
;
5523 /* FIXME: cagney/2003-11-15: For MIPS, hasn't gdbarch_pc_regnum been
5524 replaced by read_pc? */
5525 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
5526 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
5527 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
5528 set_gdbarch_num_regs (gdbarch
, num_regs
);
5529 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
5530 set_gdbarch_register_name (gdbarch
, mips_register_name
);
5531 set_gdbarch_virtual_frame_pointer (gdbarch
, mips_virtual_frame_pointer
);
5532 tdep
->mips_processor_reg_names
= reg_names
;
5533 tdep
->regnum
= regnum
;
5539 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
5540 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
5541 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
5542 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5543 tdep
->default_mask_address_p
= 0;
5544 set_gdbarch_long_bit (gdbarch
, 32);
5545 set_gdbarch_ptr_bit (gdbarch
, 32);
5546 set_gdbarch_long_long_bit (gdbarch
, 64);
5549 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
5550 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
5551 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
5552 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5553 tdep
->default_mask_address_p
= 0;
5554 set_gdbarch_long_bit (gdbarch
, 32);
5555 set_gdbarch_ptr_bit (gdbarch
, 32);
5556 set_gdbarch_long_long_bit (gdbarch
, 64);
5558 case MIPS_ABI_EABI32
:
5559 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5560 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
5561 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5562 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5563 tdep
->default_mask_address_p
= 0;
5564 set_gdbarch_long_bit (gdbarch
, 32);
5565 set_gdbarch_ptr_bit (gdbarch
, 32);
5566 set_gdbarch_long_long_bit (gdbarch
, 64);
5568 case MIPS_ABI_EABI64
:
5569 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5570 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
5571 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5572 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5573 tdep
->default_mask_address_p
= 0;
5574 set_gdbarch_long_bit (gdbarch
, 64);
5575 set_gdbarch_ptr_bit (gdbarch
, 64);
5576 set_gdbarch_long_long_bit (gdbarch
, 64);
5579 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5580 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5581 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5582 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5583 tdep
->default_mask_address_p
= 0;
5584 set_gdbarch_long_bit (gdbarch
, 32);
5585 set_gdbarch_ptr_bit (gdbarch
, 32);
5586 set_gdbarch_long_long_bit (gdbarch
, 64);
5587 set_gdbarch_long_double_bit (gdbarch
, 128);
5588 set_gdbarch_long_double_format (gdbarch
, floatformats_n32n64_long
);
5591 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5592 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5593 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5594 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5595 tdep
->default_mask_address_p
= 0;
5596 set_gdbarch_long_bit (gdbarch
, 64);
5597 set_gdbarch_ptr_bit (gdbarch
, 64);
5598 set_gdbarch_long_long_bit (gdbarch
, 64);
5599 set_gdbarch_long_double_bit (gdbarch
, 128);
5600 set_gdbarch_long_double_format (gdbarch
, floatformats_n32n64_long
);
5603 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
5606 /* GCC creates a pseudo-section whose name specifies the size of
5607 longs, since -mlong32 or -mlong64 may be used independent of
5608 other options. How those options affect pointer sizes is ABI and
5609 architecture dependent, so use them to override the default sizes
5610 set by the ABI. This table shows the relationship between ABI,
5611 -mlongXX, and size of pointers:
5613 ABI -mlongXX ptr bits
5614 --- -------- --------
5628 Note that for o32 and eabi32, pointers are always 32 bits
5629 regardless of any -mlongXX option. For all others, pointers and
5630 longs are the same, as set by -mlongXX or set by defaults.
5633 if (info
.abfd
!= NULL
)
5637 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
5640 set_gdbarch_long_bit (gdbarch
, long_bit
);
5644 case MIPS_ABI_EABI32
:
5649 case MIPS_ABI_EABI64
:
5650 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
5653 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
5658 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5659 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5662 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
5663 flag in object files because to do so would make it impossible to
5664 link with libraries compiled without "-gp32". This is
5665 unnecessarily restrictive.
5667 We could solve this problem by adding "-gp32" multilibs to gcc,
5668 but to set this flag before gcc is built with such multilibs will
5669 break too many systems.''
5671 But even more unhelpfully, the default linker output target for
5672 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
5673 for 64-bit programs - you need to change the ABI to change this,
5674 and not all gcc targets support that currently. Therefore using
5675 this flag to detect 32-bit mode would do the wrong thing given
5676 the current gcc - it would make GDB treat these 64-bit programs
5677 as 32-bit programs by default. */
5679 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
5680 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
5682 /* Add/remove bits from an address. The MIPS needs be careful to
5683 ensure that all 32 bit addresses are sign extended to 64 bits. */
5684 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
5686 /* Unwind the frame. */
5687 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
5688 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
5689 set_gdbarch_unwind_dummy_id (gdbarch
, mips_unwind_dummy_id
);
5691 /* Map debug register numbers onto internal register numbers. */
5692 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
5693 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
5694 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5695 set_gdbarch_dwarf_reg_to_regnum (gdbarch
,
5696 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5697 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
5698 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5699 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
5701 /* MIPS version of CALL_DUMMY */
5703 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
5704 replaced by a command, and all targets will default to on stack
5705 (regardless of the stack's execute status). */
5706 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
5707 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
5709 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
5710 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
5711 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
5713 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
5714 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
5716 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
5718 set_gdbarch_in_function_epilogue_p (gdbarch
, mips_in_function_epilogue_p
);
5720 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
5721 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
5722 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
5724 set_gdbarch_register_type (gdbarch
, mips_register_type
);
5726 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
5728 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
5730 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
5731 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
5732 need to all be folded into the target vector. Since they are
5733 being used as guards for STOPPED_BY_WATCHPOINT, why not have
5734 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
5736 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
5738 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
5740 set_gdbarch_single_step_through_delay (gdbarch
, mips_single_step_through_delay
);
5742 /* Virtual tables. */
5743 set_gdbarch_vbit_in_delta (gdbarch
, 1);
5745 mips_register_g_packet_guesses (gdbarch
);
5747 /* Hook in OS ABI-specific overrides, if they have been registered. */
5748 info
.tdep_info
= (void *) tdesc_data
;
5749 gdbarch_init_osabi (info
, gdbarch
);
5751 /* Unwind the frame. */
5752 frame_unwind_append_sniffer (gdbarch
, dwarf2_frame_sniffer
);
5753 frame_unwind_append_sniffer (gdbarch
, mips_stub_frame_sniffer
);
5754 frame_unwind_append_sniffer (gdbarch
, mips_insn16_frame_sniffer
);
5755 frame_unwind_append_sniffer (gdbarch
, mips_insn32_frame_sniffer
);
5756 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
5757 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
5758 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
5759 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
5763 set_tdesc_pseudo_register_type (gdbarch
, mips_pseudo_register_type
);
5764 tdesc_use_registers (gdbarch
, info
.target_desc
, tdesc_data
);
5766 /* Override the normal target description methods to handle our
5767 dual real and pseudo registers. */
5768 set_gdbarch_register_name (gdbarch
, mips_register_name
);
5769 set_gdbarch_register_reggroup_p (gdbarch
, mips_tdesc_register_reggroup_p
);
5771 num_regs
= gdbarch_num_regs (gdbarch
);
5772 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
5773 set_gdbarch_pc_regnum (gdbarch
, tdep
->regnum
->pc
+ num_regs
);
5774 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
5777 /* Add ABI-specific aliases for the registers. */
5778 if (mips_abi
== MIPS_ABI_N32
|| mips_abi
== MIPS_ABI_N64
)
5779 for (i
= 0; i
< ARRAY_SIZE (mips_n32_n64_aliases
); i
++)
5780 user_reg_add (gdbarch
, mips_n32_n64_aliases
[i
].name
,
5781 value_of_mips_user_reg
, &mips_n32_n64_aliases
[i
].regnum
);
5783 for (i
= 0; i
< ARRAY_SIZE (mips_o32_aliases
); i
++)
5784 user_reg_add (gdbarch
, mips_o32_aliases
[i
].name
,
5785 value_of_mips_user_reg
, &mips_o32_aliases
[i
].regnum
);
5787 /* Add some other standard aliases. */
5788 for (i
= 0; i
< ARRAY_SIZE (mips_register_aliases
); i
++)
5789 user_reg_add (gdbarch
, mips_register_aliases
[i
].name
,
5790 value_of_mips_user_reg
, &mips_register_aliases
[i
].regnum
);
5796 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
5798 struct gdbarch_info info
;
5800 /* Force the architecture to update, and (if it's a MIPS architecture)
5801 mips_gdbarch_init will take care of the rest. */
5802 gdbarch_info_init (&info
);
5803 gdbarch_update_p (info
);
5806 /* Print out which MIPS ABI is in use. */
5809 show_mips_abi (struct ui_file
*file
,
5811 struct cmd_list_element
*ignored_cmd
,
5812 const char *ignored_value
)
5814 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_mips
)
5817 "The MIPS ABI is unknown because the current architecture "
5821 enum mips_abi global_abi
= global_mips_abi ();
5822 enum mips_abi actual_abi
= mips_abi (current_gdbarch
);
5823 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
5825 if (global_abi
== MIPS_ABI_UNKNOWN
)
5828 "The MIPS ABI is set automatically (currently \"%s\").\n",
5830 else if (global_abi
== actual_abi
)
5833 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
5837 /* Probably shouldn't happen... */
5840 "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
5841 actual_abi_str
, mips_abi_strings
[global_abi
]);
5847 mips_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
5849 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5853 int ef_mips_32bitmode
;
5854 /* Determine the ISA. */
5855 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
5873 /* Determine the size of a pointer. */
5874 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
5875 fprintf_unfiltered (file
,
5876 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
5878 fprintf_unfiltered (file
,
5879 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
5881 fprintf_unfiltered (file
,
5882 "mips_dump_tdep: ef_mips_arch = %d\n",
5884 fprintf_unfiltered (file
,
5885 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
5886 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
5887 fprintf_unfiltered (file
,
5888 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
5889 mips_mask_address_p (tdep
),
5890 tdep
->default_mask_address_p
);
5892 fprintf_unfiltered (file
,
5893 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
5894 MIPS_DEFAULT_FPU_TYPE
,
5895 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
5896 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
5897 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
5899 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI
);
5900 fprintf_unfiltered (file
,
5901 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
5903 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
5904 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
5905 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
5909 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
5912 _initialize_mips_tdep (void)
5914 static struct cmd_list_element
*mipsfpulist
= NULL
;
5915 struct cmd_list_element
*c
;
5917 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
5918 if (MIPS_ABI_LAST
+ 1
5919 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
5920 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
5922 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
5924 mips_pdr_data
= register_objfile_data ();
5926 /* Create feature sets with the appropriate properties. The values
5927 are not important. */
5928 mips_tdesc_gp32
= allocate_target_description ();
5929 set_tdesc_property (mips_tdesc_gp32
, PROPERTY_GP32
, "");
5931 mips_tdesc_gp64
= allocate_target_description ();
5932 set_tdesc_property (mips_tdesc_gp64
, PROPERTY_GP64
, "");
5934 /* Add root prefix command for all "set mips"/"show mips" commands */
5935 add_prefix_cmd ("mips", no_class
, set_mips_command
,
5936 _("Various MIPS specific commands."),
5937 &setmipscmdlist
, "set mips ", 0, &setlist
);
5939 add_prefix_cmd ("mips", no_class
, show_mips_command
,
5940 _("Various MIPS specific commands."),
5941 &showmipscmdlist
, "show mips ", 0, &showlist
);
5943 /* Allow the user to override the ABI. */
5944 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
5945 &mips_abi_string
, _("\
5946 Set the MIPS ABI used by this program."), _("\
5947 Show the MIPS ABI used by this program."), _("\
5948 This option can be set to one of:\n\
5949 auto - the default ABI associated with the current binary\n\
5958 &setmipscmdlist
, &showmipscmdlist
);
5960 /* Let the user turn off floating point and set the fence post for
5961 heuristic_proc_start. */
5963 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
5964 _("Set use of MIPS floating-point coprocessor."),
5965 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
5966 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
5967 _("Select single-precision MIPS floating-point coprocessor."),
5969 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
5970 _("Select double-precision MIPS floating-point coprocessor."),
5972 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
5973 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
5974 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
5975 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
5976 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
5977 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
5978 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
5979 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
5980 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
5981 _("Select MIPS floating-point coprocessor automatically."),
5983 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
5984 _("Show current use of MIPS floating-point coprocessor target."),
5987 /* We really would like to have both "0" and "unlimited" work, but
5988 command.c doesn't deal with that. So make it a var_zinteger
5989 because the user can always use "999999" or some such for unlimited. */
5990 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
5991 &heuristic_fence_post
, _("\
5992 Set the distance searched for the start of a function."), _("\
5993 Show the distance searched for the start of a function."), _("\
5994 If you are debugging a stripped executable, GDB needs to search through the\n\
5995 program for the start of a function. This command sets the distance of the\n\
5996 search. The only need to set it is when debugging a stripped executable."),
5997 reinit_frame_cache_sfunc
,
5998 NULL
, /* FIXME: i18n: The distance searched for the start of a function is %s. */
5999 &setlist
, &showlist
);
6001 /* Allow the user to control whether the upper bits of 64-bit
6002 addresses should be zeroed. */
6003 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
6004 &mask_address_var
, _("\
6005 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
6006 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
6007 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
6008 allow GDB to determine the correct value."),
6009 NULL
, show_mask_address
,
6010 &setmipscmdlist
, &showmipscmdlist
);
6012 /* Allow the user to control the size of 32 bit registers within the
6013 raw remote packet. */
6014 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
6015 &mips64_transfers_32bit_regs_p
, _("\
6016 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
6018 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
6020 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6021 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6022 64 bits for others. Use \"off\" to disable compatibility mode"),
6023 set_mips64_transfers_32bit_regs
,
6024 NULL
, /* FIXME: i18n: Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s. */
6025 &setlist
, &showlist
);
6027 /* Debug this files internals. */
6028 add_setshow_zinteger_cmd ("mips", class_maintenance
,
6030 Set mips debugging."), _("\
6031 Show mips debugging."), _("\
6032 When non-zero, mips specific debugging is enabled."),
6034 NULL
, /* FIXME: i18n: Mips debugging is currently %s. */
6035 &setdebuglist
, &showdebuglist
);