1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988-2014 Free Software Foundation, Inc.
5 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
6 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
35 #include "arch-utils.h"
38 #include "mips-tdep.h"
40 #include "reggroups.h"
41 #include "opcode/mips.h"
45 #include "sim-regno.h"
47 #include "frame-unwind.h"
48 #include "frame-base.h"
49 #include "trad-frame.h"
51 #include "floatformat.h"
53 #include "target-descriptions.h"
54 #include "dwarf2-frame.h"
55 #include "user-regs.h"
59 static const struct objfile_data
*mips_pdr_data
;
61 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
63 static int mips32_instruction_has_delay_slot (struct gdbarch
*gdbarch
,
65 static int micromips_instruction_has_delay_slot (ULONGEST insn
, int mustbe32
);
66 static int mips16_instruction_has_delay_slot (unsigned short inst
,
69 static int mips32_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
71 static int micromips_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
72 CORE_ADDR addr
, int mustbe32
);
73 static int mips16_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
74 CORE_ADDR addr
, int mustbe32
);
76 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
77 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
78 #define ST0_FR (1 << 26)
80 /* The sizes of floating point registers. */
84 MIPS_FPU_SINGLE_REGSIZE
= 4,
85 MIPS_FPU_DOUBLE_REGSIZE
= 8
94 static const char *mips_abi_string
;
96 static const char *const mips_abi_strings
[] = {
107 /* For backwards compatibility we default to MIPS16. This flag is
108 overridden as soon as unambiguous ELF file flags tell us the
109 compressed ISA encoding used. */
110 static const char mips_compression_mips16
[] = "mips16";
111 static const char mips_compression_micromips
[] = "micromips";
112 static const char *const mips_compression_strings
[] =
114 mips_compression_mips16
,
115 mips_compression_micromips
,
119 static const char *mips_compression_string
= mips_compression_mips16
;
121 /* The standard register names, and all the valid aliases for them. */
122 struct register_alias
128 /* Aliases for o32 and most other ABIs. */
129 const struct register_alias mips_o32_aliases
[] = {
136 /* Aliases for n32 and n64. */
137 const struct register_alias mips_n32_n64_aliases
[] = {
144 /* Aliases for ABI-independent registers. */
145 const struct register_alias mips_register_aliases
[] = {
146 /* The architecture manuals specify these ABI-independent names for
148 #define R(n) { "r" #n, n }
149 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
150 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
151 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
152 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
155 /* k0 and k1 are sometimes called these instead (for "kernel
160 /* This is the traditional GDB name for the CP0 status register. */
161 { "sr", MIPS_PS_REGNUM
},
163 /* This is the traditional GDB name for the CP0 BadVAddr register. */
164 { "bad", MIPS_EMBED_BADVADDR_REGNUM
},
166 /* This is the traditional GDB name for the FCSR. */
167 { "fsr", MIPS_EMBED_FP0_REGNUM
+ 32 }
170 const struct register_alias mips_numeric_register_aliases
[] = {
171 #define R(n) { #n, n }
172 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
173 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
174 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
175 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
179 #ifndef MIPS_DEFAULT_FPU_TYPE
180 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
182 static int mips_fpu_type_auto
= 1;
183 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
185 static unsigned int mips_debug
= 0;
187 /* Properties (for struct target_desc) describing the g/G packet
189 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
190 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
192 struct target_desc
*mips_tdesc_gp32
;
193 struct target_desc
*mips_tdesc_gp64
;
195 const struct mips_regnum
*
196 mips_regnum (struct gdbarch
*gdbarch
)
198 return gdbarch_tdep (gdbarch
)->regnum
;
202 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
204 return mips_regnum (gdbarch
)->fp0
+ 12;
207 /* Return 1 if REGNUM refers to a floating-point general register, raw
208 or cooked. Otherwise return 0. */
211 mips_float_register_p (struct gdbarch
*gdbarch
, int regnum
)
213 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
215 return (rawnum
>= mips_regnum (gdbarch
)->fp0
216 && rawnum
< mips_regnum (gdbarch
)->fp0
+ 32);
219 #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \
221 || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64)
223 #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \
224 (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum)
226 #define MIPS_LAST_ARG_REGNUM(gdbarch) \
227 (gdbarch_tdep (gdbarch)->mips_last_arg_regnum)
229 #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type)
231 /* Return the MIPS ABI associated with GDBARCH. */
233 mips_abi (struct gdbarch
*gdbarch
)
235 return gdbarch_tdep (gdbarch
)->mips_abi
;
239 mips_isa_regsize (struct gdbarch
*gdbarch
)
241 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
243 /* If we know how big the registers are, use that size. */
244 if (tdep
->register_size_valid_p
)
245 return tdep
->register_size
;
247 /* Fall back to the previous behavior. */
248 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
249 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
252 /* Return the currently configured (or set) saved register size. */
255 mips_abi_regsize (struct gdbarch
*gdbarch
)
257 switch (mips_abi (gdbarch
))
259 case MIPS_ABI_EABI32
:
265 case MIPS_ABI_EABI64
:
267 case MIPS_ABI_UNKNOWN
:
270 internal_error (__FILE__
, __LINE__
, _("bad switch"));
274 /* MIPS16/microMIPS function addresses are odd (bit 0 is set). Here
275 are some functions to handle addresses associated with compressed
276 code including but not limited to testing, setting, or clearing
277 bit 0 of such addresses. */
279 /* Return one iff compressed code is the MIPS16 instruction set. */
282 is_mips16_isa (struct gdbarch
*gdbarch
)
284 return gdbarch_tdep (gdbarch
)->mips_isa
== ISA_MIPS16
;
287 /* Return one iff compressed code is the microMIPS instruction set. */
290 is_micromips_isa (struct gdbarch
*gdbarch
)
292 return gdbarch_tdep (gdbarch
)->mips_isa
== ISA_MICROMIPS
;
295 /* Return one iff ADDR denotes compressed code. */
298 is_compact_addr (CORE_ADDR addr
)
303 /* Return one iff ADDR denotes standard ISA code. */
306 is_mips_addr (CORE_ADDR addr
)
308 return !is_compact_addr (addr
);
311 /* Return one iff ADDR denotes MIPS16 code. */
314 is_mips16_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
316 return is_compact_addr (addr
) && is_mips16_isa (gdbarch
);
319 /* Return one iff ADDR denotes microMIPS code. */
322 is_micromips_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
324 return is_compact_addr (addr
) && is_micromips_isa (gdbarch
);
327 /* Strip the ISA (compression) bit off from ADDR. */
330 unmake_compact_addr (CORE_ADDR addr
)
332 return ((addr
) & ~(CORE_ADDR
) 1);
335 /* Add the ISA (compression) bit to ADDR. */
338 make_compact_addr (CORE_ADDR addr
)
340 return ((addr
) | (CORE_ADDR
) 1);
343 /* Functions for setting and testing a bit in a minimal symbol that
344 marks it as MIPS16 or microMIPS function. The MSB of the minimal
345 symbol's "info" field is used for this purpose.
347 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is
348 "special", i.e. refers to a MIPS16 or microMIPS function, and sets
349 one of the "special" bits in a minimal symbol to mark it accordingly.
350 The test checks an ELF-private flag that is valid for true function
351 symbols only; for synthetic symbols such as for PLT stubs that have
352 no ELF-private part at all the MIPS BFD backend arranges for this
353 information to be carried in the asymbol's udata field instead.
355 msymbol_is_mips16 and msymbol_is_micromips test the "special" bit
356 in a minimal symbol. */
359 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
361 elf_symbol_type
*elfsym
= (elf_symbol_type
*) sym
;
362 unsigned char st_other
;
364 if ((sym
->flags
& BSF_SYNTHETIC
) == 0)
365 st_other
= elfsym
->internal_elf_sym
.st_other
;
366 else if ((sym
->flags
& BSF_FUNCTION
) != 0)
367 st_other
= sym
->udata
.i
;
371 if (ELF_ST_IS_MICROMIPS (st_other
))
372 MSYMBOL_TARGET_FLAG_2 (msym
) = 1;
373 else if (ELF_ST_IS_MIPS16 (st_other
))
374 MSYMBOL_TARGET_FLAG_1 (msym
) = 1;
377 /* Return one iff MSYM refers to standard ISA code. */
380 msymbol_is_mips (struct minimal_symbol
*msym
)
382 return !(MSYMBOL_TARGET_FLAG_1 (msym
) | MSYMBOL_TARGET_FLAG_2 (msym
));
385 /* Return one iff MSYM refers to MIPS16 code. */
388 msymbol_is_mips16 (struct minimal_symbol
*msym
)
390 return MSYMBOL_TARGET_FLAG_1 (msym
);
393 /* Return one iff MSYM refers to microMIPS code. */
396 msymbol_is_micromips (struct minimal_symbol
*msym
)
398 return MSYMBOL_TARGET_FLAG_2 (msym
);
401 /* XFER a value from the big/little/left end of the register.
402 Depending on the size of the value it might occupy the entire
403 register or just part of it. Make an allowance for this, aligning
404 things accordingly. */
407 mips_xfer_register (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
408 int reg_num
, int length
,
409 enum bfd_endian endian
, gdb_byte
*in
,
410 const gdb_byte
*out
, int buf_offset
)
414 gdb_assert (reg_num
>= gdbarch_num_regs (gdbarch
));
415 /* Need to transfer the left or right part of the register, based on
416 the targets byte order. */
420 reg_offset
= register_size (gdbarch
, reg_num
) - length
;
422 case BFD_ENDIAN_LITTLE
:
425 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
429 internal_error (__FILE__
, __LINE__
, _("bad switch"));
432 fprintf_unfiltered (gdb_stderr
,
433 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
434 reg_num
, reg_offset
, buf_offset
, length
);
435 if (mips_debug
&& out
!= NULL
)
438 fprintf_unfiltered (gdb_stdlog
, "out ");
439 for (i
= 0; i
< length
; i
++)
440 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
443 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
446 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
448 if (mips_debug
&& in
!= NULL
)
451 fprintf_unfiltered (gdb_stdlog
, "in ");
452 for (i
= 0; i
< length
; i
++)
453 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
456 fprintf_unfiltered (gdb_stdlog
, "\n");
459 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
460 compatiblity mode. A return value of 1 means that we have
461 physical 64-bit registers, but should treat them as 32-bit registers. */
464 mips2_fp_compat (struct frame_info
*frame
)
466 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
467 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
469 if (register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) == 4)
473 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
474 in all the places we deal with FP registers. PR gdb/413. */
475 /* Otherwise check the FR bit in the status register - it controls
476 the FP compatiblity mode. If it is clear we are in compatibility
478 if ((get_frame_register_unsigned (frame
, MIPS_PS_REGNUM
) & ST0_FR
) == 0)
485 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
487 static CORE_ADDR
heuristic_proc_start (struct gdbarch
*, CORE_ADDR
);
489 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
491 /* The list of available "set mips " and "show mips " commands. */
493 static struct cmd_list_element
*setmipscmdlist
= NULL
;
494 static struct cmd_list_element
*showmipscmdlist
= NULL
;
496 /* Integer registers 0 thru 31 are handled explicitly by
497 mips_register_name(). Processor specific registers 32 and above
498 are listed in the following tables. */
501 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
505 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
506 "sr", "lo", "hi", "bad", "cause", "pc",
507 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
508 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
509 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
510 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
514 /* Names of IDT R3041 registers. */
516 static const char *mips_r3041_reg_names
[] = {
517 "sr", "lo", "hi", "bad", "cause", "pc",
518 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
519 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
520 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
521 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
522 "fsr", "fir", "", /*"fp" */ "",
523 "", "", "bus", "ccfg", "", "", "", "",
524 "", "", "port", "cmp", "", "", "epc", "prid",
527 /* Names of tx39 registers. */
529 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
530 "sr", "lo", "hi", "bad", "cause", "pc",
531 "", "", "", "", "", "", "", "",
532 "", "", "", "", "", "", "", "",
533 "", "", "", "", "", "", "", "",
534 "", "", "", "", "", "", "", "",
536 "", "", "", "", "", "", "", "",
537 "", "", "config", "cache", "debug", "depc", "epc",
540 /* Names of IRIX registers. */
541 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
542 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
543 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
544 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
545 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
546 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
549 /* Names of registers with Linux kernels. */
550 static const char *mips_linux_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
551 "sr", "lo", "hi", "bad", "cause", "pc",
552 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
553 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
554 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
555 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
560 /* Return the name of the register corresponding to REGNO. */
562 mips_register_name (struct gdbarch
*gdbarch
, int regno
)
564 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
565 /* GPR names for all ABIs other than n32/n64. */
566 static char *mips_gpr_names
[] = {
567 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
568 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
569 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
570 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
573 /* GPR names for n32 and n64 ABIs. */
574 static char *mips_n32_n64_gpr_names
[] = {
575 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
576 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
577 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
578 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
581 enum mips_abi abi
= mips_abi (gdbarch
);
583 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
584 but then don't make the raw register names visible. This (upper)
585 range of user visible register numbers are the pseudo-registers.
587 This approach was adopted accommodate the following scenario:
588 It is possible to debug a 64-bit device using a 32-bit
589 programming model. In such instances, the raw registers are
590 configured to be 64-bits wide, while the pseudo registers are
591 configured to be 32-bits wide. The registers that the user
592 sees - the pseudo registers - match the users expectations
593 given the programming model being used. */
594 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
595 if (regno
< gdbarch_num_regs (gdbarch
))
598 /* The MIPS integer registers are always mapped from 0 to 31. The
599 names of the registers (which reflects the conventions regarding
600 register use) vary depending on the ABI. */
601 if (0 <= rawnum
&& rawnum
< 32)
603 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
604 return mips_n32_n64_gpr_names
[rawnum
];
606 return mips_gpr_names
[rawnum
];
608 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
609 return tdesc_register_name (gdbarch
, rawnum
);
610 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (gdbarch
))
612 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
613 if (tdep
->mips_processor_reg_names
[rawnum
- 32])
614 return tdep
->mips_processor_reg_names
[rawnum
- 32];
618 internal_error (__FILE__
, __LINE__
,
619 _("mips_register_name: bad register number %d"), rawnum
);
622 /* Return the groups that a MIPS register can be categorised into. */
625 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
626 struct reggroup
*reggroup
)
631 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
632 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
633 if (reggroup
== all_reggroup
)
635 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
636 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
637 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
638 (gdbarch), as not all architectures are multi-arch. */
639 raw_p
= rawnum
< gdbarch_num_regs (gdbarch
);
640 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
641 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
643 if (reggroup
== float_reggroup
)
644 return float_p
&& pseudo
;
645 if (reggroup
== vector_reggroup
)
646 return vector_p
&& pseudo
;
647 if (reggroup
== general_reggroup
)
648 return (!vector_p
&& !float_p
) && pseudo
;
649 /* Save the pseudo registers. Need to make certain that any code
650 extracting register values from a saved register cache also uses
652 if (reggroup
== save_reggroup
)
653 return raw_p
&& pseudo
;
654 /* Restore the same pseudo register. */
655 if (reggroup
== restore_reggroup
)
656 return raw_p
&& pseudo
;
660 /* Return the groups that a MIPS register can be categorised into.
661 This version is only used if we have a target description which
662 describes real registers (and their groups). */
665 mips_tdesc_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
666 struct reggroup
*reggroup
)
668 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
669 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
672 /* Only save, restore, and display the pseudo registers. Need to
673 make certain that any code extracting register values from a
674 saved register cache also uses pseudo registers.
676 Note: saving and restoring the pseudo registers is slightly
677 strange; if we have 64 bits, we should save and restore all
678 64 bits. But this is hard and has little benefit. */
682 ret
= tdesc_register_in_reggroup_p (gdbarch
, rawnum
, reggroup
);
686 return mips_register_reggroup_p (gdbarch
, regnum
, reggroup
);
689 /* Map the symbol table registers which live in the range [1 *
690 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
691 registers. Take care of alignment and size problems. */
693 static enum register_status
694 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
695 int cookednum
, gdb_byte
*buf
)
697 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
698 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
699 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
700 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
701 return regcache_raw_read (regcache
, rawnum
, buf
);
702 else if (register_size (gdbarch
, rawnum
) >
703 register_size (gdbarch
, cookednum
))
705 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
706 return regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
709 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
711 enum register_status status
;
713 status
= regcache_raw_read_signed (regcache
, rawnum
, ®val
);
714 if (status
== REG_VALID
)
715 store_signed_integer (buf
, 4, byte_order
, regval
);
720 internal_error (__FILE__
, __LINE__
, _("bad register size"));
724 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
725 struct regcache
*regcache
, int cookednum
,
728 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
729 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
730 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
731 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
732 regcache_raw_write (regcache
, rawnum
, buf
);
733 else if (register_size (gdbarch
, rawnum
) >
734 register_size (gdbarch
, cookednum
))
736 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
737 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
740 /* Sign extend the shortened version of the register prior
741 to placing it in the raw register. This is required for
742 some mips64 parts in order to avoid unpredictable behavior. */
743 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
744 LONGEST regval
= extract_signed_integer (buf
, 4, byte_order
);
745 regcache_raw_write_signed (regcache
, rawnum
, regval
);
749 internal_error (__FILE__
, __LINE__
, _("bad register size"));
753 mips_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
754 struct agent_expr
*ax
, int reg
)
756 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
757 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
758 && reg
< 2 * gdbarch_num_regs (gdbarch
));
760 ax_reg_mask (ax
, rawnum
);
766 mips_ax_pseudo_register_push_stack (struct gdbarch
*gdbarch
,
767 struct agent_expr
*ax
, int reg
)
769 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
770 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
771 && reg
< 2 * gdbarch_num_regs (gdbarch
));
772 if (register_size (gdbarch
, rawnum
) >= register_size (gdbarch
, reg
))
776 if (register_size (gdbarch
, rawnum
) > register_size (gdbarch
, reg
))
778 if (!gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
779 || gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_BIG
)
782 ax_simple (ax
, aop_lsh
);
785 ax_simple (ax
, aop_rsh_signed
);
789 internal_error (__FILE__
, __LINE__
, _("bad register size"));
794 /* Table to translate 3-bit register field to actual register number. */
795 static const signed char mips_reg3_to_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
797 /* Heuristic_proc_start may hunt through the text section for a long
798 time across a 2400 baud serial line. Allows the user to limit this
801 static int heuristic_fence_post
= 0;
803 /* Number of bytes of storage in the actual machine representation for
804 register N. NOTE: This defines the pseudo register type so need to
805 rebuild the architecture vector. */
807 static int mips64_transfers_32bit_regs_p
= 0;
810 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
811 struct cmd_list_element
*c
)
813 struct gdbarch_info info
;
814 gdbarch_info_init (&info
);
815 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
816 instead of relying on globals. Doing that would let generic code
817 handle the search for this specific architecture. */
818 if (!gdbarch_update_p (info
))
820 mips64_transfers_32bit_regs_p
= 0;
821 error (_("32-bit compatibility mode not supported"));
825 /* Convert to/from a register and the corresponding memory value. */
827 /* This predicate tests for the case of an 8 byte floating point
828 value that is being transferred to or from a pair of floating point
829 registers each of which are (or are considered to be) only 4 bytes
832 mips_convert_register_float_case_p (struct gdbarch
*gdbarch
, int regnum
,
835 return (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
836 && register_size (gdbarch
, regnum
) == 4
837 && mips_float_register_p (gdbarch
, regnum
)
838 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
841 /* This predicate tests for the case of a value of less than 8
842 bytes in width that is being transfered to or from an 8 byte
843 general purpose register. */
845 mips_convert_register_gpreg_case_p (struct gdbarch
*gdbarch
, int regnum
,
848 int num_regs
= gdbarch_num_regs (gdbarch
);
850 return (register_size (gdbarch
, regnum
) == 8
851 && regnum
% num_regs
> 0 && regnum
% num_regs
< 32
852 && TYPE_LENGTH (type
) < 8);
856 mips_convert_register_p (struct gdbarch
*gdbarch
,
857 int regnum
, struct type
*type
)
859 return (mips_convert_register_float_case_p (gdbarch
, regnum
, type
)
860 || mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
));
864 mips_register_to_value (struct frame_info
*frame
, int regnum
,
865 struct type
*type
, gdb_byte
*to
,
866 int *optimizedp
, int *unavailablep
)
868 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
870 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
872 get_frame_register (frame
, regnum
+ 0, to
+ 4);
873 get_frame_register (frame
, regnum
+ 1, to
+ 0);
875 if (!get_frame_register_bytes (frame
, regnum
+ 0, 0, 4, to
+ 4,
876 optimizedp
, unavailablep
))
879 if (!get_frame_register_bytes (frame
, regnum
+ 1, 0, 4, to
+ 0,
880 optimizedp
, unavailablep
))
882 *optimizedp
= *unavailablep
= 0;
885 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
887 int len
= TYPE_LENGTH (type
);
890 offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 8 - len
: 0;
891 if (!get_frame_register_bytes (frame
, regnum
, offset
, len
, to
,
892 optimizedp
, unavailablep
))
895 *optimizedp
= *unavailablep
= 0;
900 internal_error (__FILE__
, __LINE__
,
901 _("mips_register_to_value: unrecognized case"));
906 mips_value_to_register (struct frame_info
*frame
, int regnum
,
907 struct type
*type
, const gdb_byte
*from
)
909 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
911 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
913 put_frame_register (frame
, regnum
+ 0, from
+ 4);
914 put_frame_register (frame
, regnum
+ 1, from
+ 0);
916 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
919 int len
= TYPE_LENGTH (type
);
921 /* Sign extend values, irrespective of type, that are stored to
922 a 64-bit general purpose register. (32-bit unsigned values
923 are stored as signed quantities within a 64-bit register.
924 When performing an operation, in compiled code, that combines
925 a 32-bit unsigned value with a signed 64-bit value, a type
926 conversion is first performed that zeroes out the high 32 bits.) */
927 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
930 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, -1);
932 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, 0);
933 put_frame_register_bytes (frame
, regnum
, 0, 8 - len
, fill
);
934 put_frame_register_bytes (frame
, regnum
, 8 - len
, len
, from
);
938 if (from
[len
-1] & 0x80)
939 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, -1);
941 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, 0);
942 put_frame_register_bytes (frame
, regnum
, 0, len
, from
);
943 put_frame_register_bytes (frame
, regnum
, len
, 8 - len
, fill
);
948 internal_error (__FILE__
, __LINE__
,
949 _("mips_value_to_register: unrecognized case"));
953 /* Return the GDB type object for the "standard" data type of data in
957 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
959 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (gdbarch
));
960 if (mips_float_register_p (gdbarch
, regnum
))
962 /* The floating-point registers raw, or cooked, always match
963 mips_isa_regsize(), and also map 1:1, byte for byte. */
964 if (mips_isa_regsize (gdbarch
) == 4)
965 return builtin_type (gdbarch
)->builtin_float
;
967 return builtin_type (gdbarch
)->builtin_double
;
969 else if (regnum
< gdbarch_num_regs (gdbarch
))
971 /* The raw or ISA registers. These are all sized according to
973 if (mips_isa_regsize (gdbarch
) == 4)
974 return builtin_type (gdbarch
)->builtin_int32
;
976 return builtin_type (gdbarch
)->builtin_int64
;
980 int rawnum
= regnum
- gdbarch_num_regs (gdbarch
);
982 /* The cooked or ABI registers. These are sized according to
983 the ABI (with a few complications). */
984 if (rawnum
== mips_regnum (gdbarch
)->fp_control_status
985 || rawnum
== mips_regnum (gdbarch
)->fp_implementation_revision
)
986 return builtin_type (gdbarch
)->builtin_int32
;
987 else if (gdbarch_osabi (gdbarch
) != GDB_OSABI_IRIX
988 && gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
989 && rawnum
>= MIPS_FIRST_EMBED_REGNUM
990 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
991 /* The pseudo/cooked view of the embedded registers is always
992 32-bit. The raw view is handled below. */
993 return builtin_type (gdbarch
)->builtin_int32
;
994 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
995 /* The target, while possibly using a 64-bit register buffer,
996 is only transfering 32-bits of each integer register.
997 Reflect this in the cooked/pseudo (ABI) register value. */
998 return builtin_type (gdbarch
)->builtin_int32
;
999 else if (mips_abi_regsize (gdbarch
) == 4)
1000 /* The ABI is restricted to 32-bit registers (the ISA could be
1002 return builtin_type (gdbarch
)->builtin_int32
;
1005 return builtin_type (gdbarch
)->builtin_int64
;
1009 /* Return the GDB type for the pseudo register REGNUM, which is the
1010 ABI-level view. This function is only called if there is a target
1011 description which includes registers, so we know precisely the
1012 types of hardware registers. */
1014 static struct type
*
1015 mips_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
1017 const int num_regs
= gdbarch_num_regs (gdbarch
);
1018 int rawnum
= regnum
% num_regs
;
1019 struct type
*rawtype
;
1021 gdb_assert (regnum
>= num_regs
&& regnum
< 2 * num_regs
);
1023 /* Absent registers are still absent. */
1024 rawtype
= gdbarch_register_type (gdbarch
, rawnum
);
1025 if (TYPE_LENGTH (rawtype
) == 0)
1028 if (mips_float_register_p (gdbarch
, rawnum
))
1029 /* Present the floating point registers however the hardware did;
1030 do not try to convert between FPU layouts. */
1033 /* Use pointer types for registers if we can. For n32 we can not,
1034 since we do not have a 64-bit pointer type. */
1035 if (mips_abi_regsize (gdbarch
)
1036 == TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
))
1038 if (rawnum
== MIPS_SP_REGNUM
1039 || rawnum
== mips_regnum (gdbarch
)->badvaddr
)
1040 return builtin_type (gdbarch
)->builtin_data_ptr
;
1041 else if (rawnum
== mips_regnum (gdbarch
)->pc
)
1042 return builtin_type (gdbarch
)->builtin_func_ptr
;
1045 if (mips_abi_regsize (gdbarch
) == 4 && TYPE_LENGTH (rawtype
) == 8
1046 && ((rawnum
>= MIPS_ZERO_REGNUM
&& rawnum
<= MIPS_PS_REGNUM
)
1047 || rawnum
== mips_regnum (gdbarch
)->lo
1048 || rawnum
== mips_regnum (gdbarch
)->hi
1049 || rawnum
== mips_regnum (gdbarch
)->badvaddr
1050 || rawnum
== mips_regnum (gdbarch
)->cause
1051 || rawnum
== mips_regnum (gdbarch
)->pc
1052 || (mips_regnum (gdbarch
)->dspacc
!= -1
1053 && rawnum
>= mips_regnum (gdbarch
)->dspacc
1054 && rawnum
< mips_regnum (gdbarch
)->dspacc
+ 6)))
1055 return builtin_type (gdbarch
)->builtin_int32
;
1057 if (gdbarch_osabi (gdbarch
) != GDB_OSABI_IRIX
1058 && gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
1059 && rawnum
>= MIPS_EMBED_FP0_REGNUM
+ 32
1060 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
1062 /* The pseudo/cooked view of embedded registers is always
1063 32-bit, even if the target transfers 64-bit values for them.
1064 New targets relying on XML descriptions should only transfer
1065 the necessary 32 bits, but older versions of GDB expected 64,
1066 so allow the target to provide 64 bits without interfering
1067 with the displayed type. */
1068 return builtin_type (gdbarch
)->builtin_int32
;
1071 /* For all other registers, pass through the hardware type. */
1075 /* Should the upper word of 64-bit addresses be zeroed? */
1076 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
1079 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
1081 switch (mask_address_var
)
1083 case AUTO_BOOLEAN_TRUE
:
1085 case AUTO_BOOLEAN_FALSE
:
1088 case AUTO_BOOLEAN_AUTO
:
1089 return tdep
->default_mask_address_p
;
1091 internal_error (__FILE__
, __LINE__
,
1092 _("mips_mask_address_p: bad switch"));
1098 show_mask_address (struct ui_file
*file
, int from_tty
,
1099 struct cmd_list_element
*c
, const char *value
)
1101 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch ());
1103 deprecated_show_value_hack (file
, from_tty
, c
, value
);
1104 switch (mask_address_var
)
1106 case AUTO_BOOLEAN_TRUE
:
1107 printf_filtered ("The 32 bit mips address mask is enabled\n");
1109 case AUTO_BOOLEAN_FALSE
:
1110 printf_filtered ("The 32 bit mips address mask is disabled\n");
1112 case AUTO_BOOLEAN_AUTO
:
1114 ("The 32 bit address mask is set automatically. Currently %s\n",
1115 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
1118 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
1123 /* Tell if the program counter value in MEMADDR is in a standard ISA
1127 mips_pc_is_mips (CORE_ADDR memaddr
)
1129 struct bound_minimal_symbol sym
;
1131 /* Flags indicating that this is a MIPS16 or microMIPS function is
1132 stored by elfread.c in the high bit of the info field. Use this
1133 to decide if the function is standard MIPS. Otherwise if bit 0
1134 of the address is clear, then this is a standard MIPS function. */
1135 sym
= lookup_minimal_symbol_by_pc (memaddr
);
1137 return msymbol_is_mips (sym
.minsym
);
1139 return is_mips_addr (memaddr
);
1142 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
1145 mips_pc_is_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1147 struct bound_minimal_symbol sym
;
1149 /* A flag indicating that this is a MIPS16 function is stored by
1150 elfread.c in the high bit of the info field. Use this to decide
1151 if the function is MIPS16. Otherwise if bit 0 of the address is
1152 set, then ELF file flags will tell if this is a MIPS16 function. */
1153 sym
= lookup_minimal_symbol_by_pc (memaddr
);
1155 return msymbol_is_mips16 (sym
.minsym
);
1157 return is_mips16_addr (gdbarch
, memaddr
);
1160 /* Tell if the program counter value in MEMADDR is in a microMIPS function. */
1163 mips_pc_is_micromips (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1165 struct bound_minimal_symbol sym
;
1167 /* A flag indicating that this is a microMIPS function is stored by
1168 elfread.c in the high bit of the info field. Use this to decide
1169 if the function is microMIPS. Otherwise if bit 0 of the address
1170 is set, then ELF file flags will tell if this is a microMIPS
1172 sym
= lookup_minimal_symbol_by_pc (memaddr
);
1174 return msymbol_is_micromips (sym
.minsym
);
1176 return is_micromips_addr (gdbarch
, memaddr
);
1179 /* Tell the ISA type of the function the program counter value in MEMADDR
1182 static enum mips_isa
1183 mips_pc_isa (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1185 struct bound_minimal_symbol sym
;
1187 /* A flag indicating that this is a MIPS16 or a microMIPS function
1188 is stored by elfread.c in the high bit of the info field. Use
1189 this to decide if the function is MIPS16 or microMIPS or normal
1190 MIPS. Otherwise if bit 0 of the address is set, then ELF file
1191 flags will tell if this is a MIPS16 or a microMIPS function. */
1192 sym
= lookup_minimal_symbol_by_pc (memaddr
);
1195 if (msymbol_is_micromips (sym
.minsym
))
1196 return ISA_MICROMIPS
;
1197 else if (msymbol_is_mips16 (sym
.minsym
))
1204 if (is_mips_addr (memaddr
))
1206 else if (is_micromips_addr (gdbarch
, memaddr
))
1207 return ISA_MICROMIPS
;
1213 /* Various MIPS16 thunk (aka stub or trampoline) names. */
1215 static const char mips_str_mips16_call_stub
[] = "__mips16_call_stub_";
1216 static const char mips_str_mips16_ret_stub
[] = "__mips16_ret_";
1217 static const char mips_str_call_fp_stub
[] = "__call_stub_fp_";
1218 static const char mips_str_call_stub
[] = "__call_stub_";
1219 static const char mips_str_fn_stub
[] = "__fn_stub_";
1221 /* This is used as a PIC thunk prefix. */
1223 static const char mips_str_pic
[] = ".pic.";
1225 /* Return non-zero if the PC is inside a call thunk (aka stub or
1226 trampoline) that should be treated as a temporary frame. */
1229 mips_in_frame_stub (CORE_ADDR pc
)
1231 CORE_ADDR start_addr
;
1234 /* Find the starting address of the function containing the PC. */
1235 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
1238 /* If the PC is in __mips16_call_stub_*, this is a call/return stub. */
1239 if (strncmp (name
, mips_str_mips16_call_stub
,
1240 strlen (mips_str_mips16_call_stub
)) == 0)
1242 /* If the PC is in __call_stub_*, this is a call/return or a call stub. */
1243 if (strncmp (name
, mips_str_call_stub
, strlen (mips_str_call_stub
)) == 0)
1245 /* If the PC is in __fn_stub_*, this is a call stub. */
1246 if (strncmp (name
, mips_str_fn_stub
, strlen (mips_str_fn_stub
)) == 0)
1249 return 0; /* Not a stub. */
1252 /* MIPS believes that the PC has a sign extended value. Perhaps the
1253 all registers should be sign extended for simplicity? */
1256 mips_read_pc (struct regcache
*regcache
)
1258 int regnum
= gdbarch_pc_regnum (get_regcache_arch (regcache
));
1261 regcache_cooked_read_signed (regcache
, regnum
, &pc
);
1262 if (is_compact_addr (pc
))
1263 pc
= unmake_compact_addr (pc
);
1268 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1272 pc
= frame_unwind_register_signed (next_frame
, gdbarch_pc_regnum (gdbarch
));
1273 if (is_compact_addr (pc
))
1274 pc
= unmake_compact_addr (pc
);
1275 /* macro/2012-04-20: This hack skips over MIPS16 call thunks as
1276 intermediate frames. In this case we can get the caller's address
1277 from $ra, or if $ra contains an address within a thunk as well, then
1278 it must be in the return path of __mips16_call_stub_{s,d}{f,c}_{0..10}
1279 and thus the caller's address is in $s2. */
1280 if (frame_relative_level (next_frame
) >= 0 && mips_in_frame_stub (pc
))
1282 pc
= frame_unwind_register_signed
1283 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
1284 if (is_compact_addr (pc
))
1285 pc
= unmake_compact_addr (pc
);
1286 if (mips_in_frame_stub (pc
))
1288 pc
= frame_unwind_register_signed
1289 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
1290 if (is_compact_addr (pc
))
1291 pc
= unmake_compact_addr (pc
);
1298 mips_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1300 return frame_unwind_register_signed
1301 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
);
1304 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1305 dummy frame. The frame ID's base needs to match the TOS value
1306 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1309 static struct frame_id
1310 mips_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1312 return frame_id_build
1313 (get_frame_register_signed (this_frame
,
1314 gdbarch_num_regs (gdbarch
)
1316 get_frame_pc (this_frame
));
1319 /* Implement the "write_pc" gdbarch method. */
1322 mips_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1324 int regnum
= gdbarch_pc_regnum (get_regcache_arch (regcache
));
1326 if (mips_pc_is_mips (pc
))
1327 regcache_cooked_write_unsigned (regcache
, regnum
, pc
);
1329 regcache_cooked_write_unsigned (regcache
, regnum
, make_compact_addr (pc
));
1332 /* Fetch and return instruction from the specified location. Handle
1333 MIPS16/microMIPS as appropriate. */
1336 mips_fetch_instruction (struct gdbarch
*gdbarch
,
1337 enum mips_isa isa
, CORE_ADDR addr
, int *statusp
)
1339 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1340 gdb_byte buf
[MIPS_INSN32_SIZE
];
1348 instlen
= MIPS_INSN16_SIZE
;
1349 addr
= unmake_compact_addr (addr
);
1352 instlen
= MIPS_INSN32_SIZE
;
1355 internal_error (__FILE__
, __LINE__
, _("invalid ISA"));
1358 status
= target_read_memory (addr
, buf
, instlen
);
1359 if (statusp
!= NULL
)
1363 if (statusp
== NULL
)
1364 memory_error (status
, addr
);
1367 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1370 /* These are the fields of 32 bit mips instructions. */
1371 #define mips32_op(x) (x >> 26)
1372 #define itype_op(x) (x >> 26)
1373 #define itype_rs(x) ((x >> 21) & 0x1f)
1374 #define itype_rt(x) ((x >> 16) & 0x1f)
1375 #define itype_immediate(x) (x & 0xffff)
1377 #define jtype_op(x) (x >> 26)
1378 #define jtype_target(x) (x & 0x03ffffff)
1380 #define rtype_op(x) (x >> 26)
1381 #define rtype_rs(x) ((x >> 21) & 0x1f)
1382 #define rtype_rt(x) ((x >> 16) & 0x1f)
1383 #define rtype_rd(x) ((x >> 11) & 0x1f)
1384 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1385 #define rtype_funct(x) (x & 0x3f)
1387 /* MicroMIPS instruction fields. */
1388 #define micromips_op(x) ((x) >> 10)
1390 /* 16-bit/32-bit-high-part instruction formats, B and S refer to the lowest
1391 bit and the size respectively of the field extracted. */
1392 #define b0s4_imm(x) ((x) & 0xf)
1393 #define b0s5_imm(x) ((x) & 0x1f)
1394 #define b0s5_reg(x) ((x) & 0x1f)
1395 #define b0s7_imm(x) ((x) & 0x7f)
1396 #define b0s10_imm(x) ((x) & 0x3ff)
1397 #define b1s4_imm(x) (((x) >> 1) & 0xf)
1398 #define b1s9_imm(x) (((x) >> 1) & 0x1ff)
1399 #define b2s3_cc(x) (((x) >> 2) & 0x7)
1400 #define b4s2_regl(x) (((x) >> 4) & 0x3)
1401 #define b5s5_op(x) (((x) >> 5) & 0x1f)
1402 #define b5s5_reg(x) (((x) >> 5) & 0x1f)
1403 #define b6s4_op(x) (((x) >> 6) & 0xf)
1404 #define b7s3_reg(x) (((x) >> 7) & 0x7)
1406 /* 32-bit instruction formats, B and S refer to the lowest bit and the size
1407 respectively of the field extracted. */
1408 #define b0s6_op(x) ((x) & 0x3f)
1409 #define b0s11_op(x) ((x) & 0x7ff)
1410 #define b0s12_imm(x) ((x) & 0xfff)
1411 #define b0s16_imm(x) ((x) & 0xffff)
1412 #define b0s26_imm(x) ((x) & 0x3ffffff)
1413 #define b6s10_ext(x) (((x) >> 6) & 0x3ff)
1414 #define b11s5_reg(x) (((x) >> 11) & 0x1f)
1415 #define b12s4_op(x) (((x) >> 12) & 0xf)
1417 /* Return the size in bytes of the instruction INSN encoded in the ISA
1421 mips_insn_size (enum mips_isa isa
, ULONGEST insn
)
1426 if (micromips_op (insn
) == 0x1f)
1427 return 3 * MIPS_INSN16_SIZE
;
1428 else if (((micromips_op (insn
) & 0x4) == 0x4)
1429 || ((micromips_op (insn
) & 0x7) == 0x0))
1430 return 2 * MIPS_INSN16_SIZE
;
1432 return MIPS_INSN16_SIZE
;
1434 if ((insn
& 0xf800) == 0xf000)
1435 return 2 * MIPS_INSN16_SIZE
;
1437 return MIPS_INSN16_SIZE
;
1439 return MIPS_INSN32_SIZE
;
1441 internal_error (__FILE__
, __LINE__
, _("invalid ISA"));
1445 mips32_relative_offset (ULONGEST inst
)
1447 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
1450 /* Determine the address of the next instruction executed after the INST
1451 floating condition branch instruction at PC. COUNT specifies the
1452 number of the floating condition bits tested by the branch. */
1455 mips32_bc1_pc (struct gdbarch
*gdbarch
, struct frame_info
*frame
,
1456 ULONGEST inst
, CORE_ADDR pc
, int count
)
1458 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1459 int cnum
= (itype_rt (inst
) >> 2) & (count
- 1);
1460 int tf
= itype_rt (inst
) & 1;
1461 int mask
= (1 << count
) - 1;
1466 /* No way to handle; it'll most likely trap anyway. */
1469 fcs
= get_frame_register_unsigned (frame
, fcsr
);
1470 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1472 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1473 pc
+= mips32_relative_offset (inst
);
1480 /* Return nonzero if the gdbarch is an Octeon series. */
1483 is_octeon (struct gdbarch
*gdbarch
)
1485 const struct bfd_arch_info
*info
= gdbarch_bfd_arch_info (gdbarch
);
1487 return (info
->mach
== bfd_mach_mips_octeon
1488 || info
->mach
== bfd_mach_mips_octeonp
1489 || info
->mach
== bfd_mach_mips_octeon2
);
1492 /* Return true if the OP represents the Octeon's BBIT instruction. */
1495 is_octeon_bbit_op (int op
, struct gdbarch
*gdbarch
)
1497 if (!is_octeon (gdbarch
))
1499 /* BBIT0 is encoded as LWC2: 110 010. */
1500 /* BBIT032 is encoded as LDC2: 110 110. */
1501 /* BBIT1 is encoded as SWC2: 111 010. */
1502 /* BBIT132 is encoded as SDC2: 111 110. */
1503 if (op
== 50 || op
== 54 || op
== 58 || op
== 62)
1509 /* Determine where to set a single step breakpoint while considering
1510 branch prediction. */
1513 mips32_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1515 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1518 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
1519 op
= itype_op (inst
);
1520 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch
1524 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1535 goto greater_branch
;
1540 else if (op
== 17 && itype_rs (inst
) == 8)
1541 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1542 pc
= mips32_bc1_pc (gdbarch
, frame
, inst
, pc
+ 4, 1);
1543 else if (op
== 17 && itype_rs (inst
) == 9
1544 && (itype_rt (inst
) & 2) == 0)
1545 /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */
1546 pc
= mips32_bc1_pc (gdbarch
, frame
, inst
, pc
+ 4, 2);
1547 else if (op
== 17 && itype_rs (inst
) == 10
1548 && (itype_rt (inst
) & 2) == 0)
1549 /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */
1550 pc
= mips32_bc1_pc (gdbarch
, frame
, inst
, pc
+ 4, 4);
1553 /* The new PC will be alternate mode. */
1557 reg
= jtype_target (inst
) << 2;
1558 /* Add 1 to indicate 16-bit mode -- invert ISA mode. */
1559 pc
= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + reg
+ 1;
1561 else if (is_octeon_bbit_op (op
, gdbarch
))
1565 branch_if
= op
== 58 || op
== 62;
1566 bit
= itype_rt (inst
);
1568 /* Take into account the *32 instructions. */
1569 if (op
== 54 || op
== 62)
1572 if (((get_frame_register_signed (frame
,
1573 itype_rs (inst
)) >> bit
) & 1)
1575 pc
+= mips32_relative_offset (inst
) + 4;
1577 pc
+= 8; /* After the delay slot. */
1581 pc
+= 4; /* Not a branch, next instruction is easy. */
1584 { /* This gets way messy. */
1586 /* Further subdivide into SPECIAL, REGIMM and other. */
1587 switch (op
& 0x07) /* Extract bits 28,27,26. */
1589 case 0: /* SPECIAL */
1590 op
= rtype_funct (inst
);
1595 /* Set PC to that address. */
1596 pc
= get_frame_register_signed (frame
, rtype_rs (inst
));
1598 case 12: /* SYSCALL */
1600 struct gdbarch_tdep
*tdep
;
1602 tdep
= gdbarch_tdep (get_frame_arch (frame
));
1603 if (tdep
->syscall_next_pc
!= NULL
)
1604 pc
= tdep
->syscall_next_pc (frame
);
1613 break; /* end SPECIAL */
1614 case 1: /* REGIMM */
1616 op
= itype_rt (inst
); /* branch condition */
1621 case 16: /* BLTZAL */
1622 case 18: /* BLTZALL */
1624 if (get_frame_register_signed (frame
, itype_rs (inst
)) < 0)
1625 pc
+= mips32_relative_offset (inst
) + 4;
1627 pc
+= 8; /* after the delay slot */
1631 case 17: /* BGEZAL */
1632 case 19: /* BGEZALL */
1633 if (get_frame_register_signed (frame
, itype_rs (inst
)) >= 0)
1634 pc
+= mips32_relative_offset (inst
) + 4;
1636 pc
+= 8; /* after the delay slot */
1638 case 0x1c: /* BPOSGE32 */
1639 case 0x1e: /* BPOSGE64 */
1641 if (itype_rs (inst
) == 0)
1643 unsigned int pos
= (op
& 2) ? 64 : 32;
1644 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
1647 /* No way to handle; it'll most likely trap anyway. */
1650 if ((get_frame_register_unsigned (frame
,
1651 dspctl
) & 0x7f) >= pos
)
1652 pc
+= mips32_relative_offset (inst
);
1657 /* All of the other instructions in the REGIMM category */
1662 break; /* end REGIMM */
1667 reg
= jtype_target (inst
) << 2;
1668 /* Upper four bits get never changed... */
1669 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1672 case 4: /* BEQ, BEQL */
1674 if (get_frame_register_signed (frame
, itype_rs (inst
)) ==
1675 get_frame_register_signed (frame
, itype_rt (inst
)))
1676 pc
+= mips32_relative_offset (inst
) + 4;
1680 case 5: /* BNE, BNEL */
1682 if (get_frame_register_signed (frame
, itype_rs (inst
)) !=
1683 get_frame_register_signed (frame
, itype_rt (inst
)))
1684 pc
+= mips32_relative_offset (inst
) + 4;
1688 case 6: /* BLEZ, BLEZL */
1689 if (get_frame_register_signed (frame
, itype_rs (inst
)) <= 0)
1690 pc
+= mips32_relative_offset (inst
) + 4;
1696 greater_branch
: /* BGTZ, BGTZL */
1697 if (get_frame_register_signed (frame
, itype_rs (inst
)) > 0)
1698 pc
+= mips32_relative_offset (inst
) + 4;
1705 } /* mips32_next_pc */
1707 /* Extract the 7-bit signed immediate offset from the microMIPS instruction
1711 micromips_relative_offset7 (ULONGEST insn
)
1713 return ((b0s7_imm (insn
) ^ 0x40) - 0x40) << 1;
1716 /* Extract the 10-bit signed immediate offset from the microMIPS instruction
1720 micromips_relative_offset10 (ULONGEST insn
)
1722 return ((b0s10_imm (insn
) ^ 0x200) - 0x200) << 1;
1725 /* Extract the 16-bit signed immediate offset from the microMIPS instruction
1729 micromips_relative_offset16 (ULONGEST insn
)
1731 return ((b0s16_imm (insn
) ^ 0x8000) - 0x8000) << 1;
1734 /* Return the size in bytes of the microMIPS instruction at the address PC. */
1737 micromips_pc_insn_size (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1741 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1742 return mips_insn_size (ISA_MICROMIPS
, insn
);
1745 /* Calculate the address of the next microMIPS instruction to execute
1746 after the INSN coprocessor 1 conditional branch instruction at the
1747 address PC. COUNT denotes the number of coprocessor condition bits
1748 examined by the branch. */
1751 micromips_bc1_pc (struct gdbarch
*gdbarch
, struct frame_info
*frame
,
1752 ULONGEST insn
, CORE_ADDR pc
, int count
)
1754 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1755 int cnum
= b2s3_cc (insn
>> 16) & (count
- 1);
1756 int tf
= b5s5_op (insn
>> 16) & 1;
1757 int mask
= (1 << count
) - 1;
1762 /* No way to handle; it'll most likely trap anyway. */
1765 fcs
= get_frame_register_unsigned (frame
, fcsr
);
1766 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1768 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1769 pc
+= micromips_relative_offset16 (insn
);
1771 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1776 /* Calculate the address of the next microMIPS instruction to execute
1777 after the instruction at the address PC. */
1780 micromips_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1782 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1785 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1786 pc
+= MIPS_INSN16_SIZE
;
1787 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
1789 /* 48-bit instructions. */
1790 case 3 * MIPS_INSN16_SIZE
: /* POOL48A: bits 011111 */
1791 /* No branch or jump instructions in this category. */
1792 pc
+= 2 * MIPS_INSN16_SIZE
;
1795 /* 32-bit instructions. */
1796 case 2 * MIPS_INSN16_SIZE
:
1798 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1799 pc
+= MIPS_INSN16_SIZE
;
1800 switch (micromips_op (insn
>> 16))
1802 case 0x00: /* POOL32A: bits 000000 */
1803 if (b0s6_op (insn
) == 0x3c
1804 /* POOL32Axf: bits 000000 ... 111100 */
1805 && (b6s10_ext (insn
) & 0x2bf) == 0x3c)
1806 /* JALR, JALR.HB: 000000 000x111100 111100 */
1807 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
1808 pc
= get_frame_register_signed (frame
, b0s5_reg (insn
>> 16));
1811 case 0x10: /* POOL32I: bits 010000 */
1812 switch (b5s5_op (insn
>> 16))
1814 case 0x00: /* BLTZ: bits 010000 00000 */
1815 case 0x01: /* BLTZAL: bits 010000 00001 */
1816 case 0x11: /* BLTZALS: bits 010000 10001 */
1817 if (get_frame_register_signed (frame
,
1818 b0s5_reg (insn
>> 16)) < 0)
1819 pc
+= micromips_relative_offset16 (insn
);
1821 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1824 case 0x02: /* BGEZ: bits 010000 00010 */
1825 case 0x03: /* BGEZAL: bits 010000 00011 */
1826 case 0x13: /* BGEZALS: bits 010000 10011 */
1827 if (get_frame_register_signed (frame
,
1828 b0s5_reg (insn
>> 16)) >= 0)
1829 pc
+= micromips_relative_offset16 (insn
);
1831 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1834 case 0x04: /* BLEZ: bits 010000 00100 */
1835 if (get_frame_register_signed (frame
,
1836 b0s5_reg (insn
>> 16)) <= 0)
1837 pc
+= micromips_relative_offset16 (insn
);
1839 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1842 case 0x05: /* BNEZC: bits 010000 00101 */
1843 if (get_frame_register_signed (frame
,
1844 b0s5_reg (insn
>> 16)) != 0)
1845 pc
+= micromips_relative_offset16 (insn
);
1848 case 0x06: /* BGTZ: bits 010000 00110 */
1849 if (get_frame_register_signed (frame
,
1850 b0s5_reg (insn
>> 16)) > 0)
1851 pc
+= micromips_relative_offset16 (insn
);
1853 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1856 case 0x07: /* BEQZC: bits 010000 00111 */
1857 if (get_frame_register_signed (frame
,
1858 b0s5_reg (insn
>> 16)) == 0)
1859 pc
+= micromips_relative_offset16 (insn
);
1862 case 0x14: /* BC2F: bits 010000 10100 xxx00 */
1863 case 0x15: /* BC2T: bits 010000 10101 xxx00 */
1864 if (((insn
>> 16) & 0x3) == 0x0)
1865 /* BC2F, BC2T: don't know how to handle these. */
1869 case 0x1a: /* BPOSGE64: bits 010000 11010 */
1870 case 0x1b: /* BPOSGE32: bits 010000 11011 */
1872 unsigned int pos
= (b5s5_op (insn
>> 16) & 1) ? 32 : 64;
1873 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
1876 /* No way to handle; it'll most likely trap anyway. */
1879 if ((get_frame_register_unsigned (frame
,
1880 dspctl
) & 0x7f) >= pos
)
1881 pc
+= micromips_relative_offset16 (insn
);
1883 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1887 case 0x1c: /* BC1F: bits 010000 11100 xxx00 */
1888 /* BC1ANY2F: bits 010000 11100 xxx01 */
1889 case 0x1d: /* BC1T: bits 010000 11101 xxx00 */
1890 /* BC1ANY2T: bits 010000 11101 xxx01 */
1891 if (((insn
>> 16) & 0x2) == 0x0)
1892 pc
= micromips_bc1_pc (gdbarch
, frame
, insn
, pc
,
1893 ((insn
>> 16) & 0x1) + 1);
1896 case 0x1e: /* BC1ANY4F: bits 010000 11110 xxx01 */
1897 case 0x1f: /* BC1ANY4T: bits 010000 11111 xxx01 */
1898 if (((insn
>> 16) & 0x3) == 0x1)
1899 pc
= micromips_bc1_pc (gdbarch
, frame
, insn
, pc
, 4);
1904 case 0x1d: /* JALS: bits 011101 */
1905 case 0x35: /* J: bits 110101 */
1906 case 0x3d: /* JAL: bits 111101 */
1907 pc
= ((pc
| 0x7fffffe) ^ 0x7fffffe) | (b0s26_imm (insn
) << 1);
1910 case 0x25: /* BEQ: bits 100101 */
1911 if (get_frame_register_signed (frame
, b0s5_reg (insn
>> 16))
1912 == get_frame_register_signed (frame
, b5s5_reg (insn
>> 16)))
1913 pc
+= micromips_relative_offset16 (insn
);
1915 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1918 case 0x2d: /* BNE: bits 101101 */
1919 if (get_frame_register_signed (frame
, b0s5_reg (insn
>> 16))
1920 != get_frame_register_signed (frame
, b5s5_reg (insn
>> 16)))
1921 pc
+= micromips_relative_offset16 (insn
);
1923 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1926 case 0x3c: /* JALX: bits 111100 */
1927 pc
= ((pc
| 0xfffffff) ^ 0xfffffff) | (b0s26_imm (insn
) << 2);
1932 /* 16-bit instructions. */
1933 case MIPS_INSN16_SIZE
:
1934 switch (micromips_op (insn
))
1936 case 0x11: /* POOL16C: bits 010001 */
1937 if ((b5s5_op (insn
) & 0x1c) == 0xc)
1938 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
1939 pc
= get_frame_register_signed (frame
, b0s5_reg (insn
));
1940 else if (b5s5_op (insn
) == 0x18)
1941 /* JRADDIUSP: bits 010001 11000 */
1942 pc
= get_frame_register_signed (frame
, MIPS_RA_REGNUM
);
1945 case 0x23: /* BEQZ16: bits 100011 */
1947 int rs
= mips_reg3_to_reg
[b7s3_reg (insn
)];
1949 if (get_frame_register_signed (frame
, rs
) == 0)
1950 pc
+= micromips_relative_offset7 (insn
);
1952 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1956 case 0x2b: /* BNEZ16: bits 101011 */
1958 int rs
= mips_reg3_to_reg
[b7s3_reg (insn
)];
1960 if (get_frame_register_signed (frame
, rs
) != 0)
1961 pc
+= micromips_relative_offset7 (insn
);
1963 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1967 case 0x33: /* B16: bits 110011 */
1968 pc
+= micromips_relative_offset10 (insn
);
1977 /* Decoding the next place to set a breakpoint is irregular for the
1978 mips 16 variant, but fortunately, there fewer instructions. We have
1979 to cope ith extensions for 16 bit instructions and a pair of actual
1980 32 bit instructions. We dont want to set a single step instruction
1981 on the extend instruction either. */
1983 /* Lots of mips16 instruction formats */
1984 /* Predicting jumps requires itype,ritype,i8type
1985 and their extensions extItype,extritype,extI8type. */
1986 enum mips16_inst_fmts
1988 itype
, /* 0 immediate 5,10 */
1989 ritype
, /* 1 5,3,8 */
1990 rrtype
, /* 2 5,3,3,5 */
1991 rritype
, /* 3 5,3,3,5 */
1992 rrrtype
, /* 4 5,3,3,3,2 */
1993 rriatype
, /* 5 5,3,3,1,4 */
1994 shifttype
, /* 6 5,3,3,3,2 */
1995 i8type
, /* 7 5,3,8 */
1996 i8movtype
, /* 8 5,3,3,5 */
1997 i8mov32rtype
, /* 9 5,3,5,3 */
1998 i64type
, /* 10 5,3,8 */
1999 ri64type
, /* 11 5,3,3,5 */
2000 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
2001 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
2002 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
2003 extRRItype
, /* 15 5,5,5,5,3,3,5 */
2004 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
2005 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
2006 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
2007 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
2008 extRi64type
, /* 20 5,6,5,5,3,3,5 */
2009 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
2011 /* I am heaping all the fields of the formats into one structure and
2012 then, only the fields which are involved in instruction extension. */
2016 unsigned int regx
; /* Function in i8 type. */
2021 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
2022 for the bits which make up the immediate extension. */
2025 extended_offset (unsigned int extension
)
2029 value
= (extension
>> 16) & 0x1f; /* Extract 15:11. */
2031 value
|= (extension
>> 21) & 0x3f; /* Extract 10:5. */
2033 value
|= extension
& 0x1f; /* Extract 4:0. */
2038 /* Only call this function if you know that this is an extendable
2039 instruction. It won't malfunction, but why make excess remote memory
2040 references? If the immediate operands get sign extended or something,
2041 do it after the extension is performed. */
2042 /* FIXME: Every one of these cases needs to worry about sign extension
2043 when the offset is to be used in relative addressing. */
2046 fetch_mips_16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2048 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2051 pc
= unmake_compact_addr (pc
); /* Clear the low order bit. */
2052 target_read_memory (pc
, buf
, 2);
2053 return extract_unsigned_integer (buf
, 2, byte_order
);
2057 unpack_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
2058 unsigned int extension
,
2060 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
2065 switch (insn_format
)
2072 value
= extended_offset ((extension
<< 16) | inst
);
2073 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
2077 value
= inst
& 0x7ff;
2078 value
= (value
^ 0x400) - 0x400; /* Sign-extend. */
2087 { /* A register identifier and an offset. */
2088 /* Most of the fields are the same as I type but the
2089 immediate value is of a different length. */
2093 value
= extended_offset ((extension
<< 16) | inst
);
2094 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
2098 value
= inst
& 0xff; /* 8 bits */
2099 value
= (value
^ 0x80) - 0x80; /* Sign-extend. */
2102 regx
= (inst
>> 8) & 0x07; /* i8 funct */
2108 unsigned long value
;
2109 unsigned int nexthalf
;
2110 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
2111 value
= value
<< 16;
2112 nexthalf
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, pc
+ 2, NULL
);
2113 /* Low bit still set. */
2121 internal_error (__FILE__
, __LINE__
, _("bad switch"));
2123 upk
->offset
= offset
;
2130 add_offset_16 (CORE_ADDR pc
, int offset
)
2132 return ((offset
<< 2) | ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)));
2136 extended_mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
,
2137 unsigned int extension
, unsigned int insn
)
2139 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2140 int op
= (insn
>> 11);
2143 case 2: /* Branch */
2145 struct upk_mips16 upk
;
2146 unpack_mips16 (gdbarch
, pc
, extension
, insn
, itype
, &upk
);
2147 pc
+= (upk
.offset
<< 1) + 2;
2150 case 3: /* JAL , JALX - Watch out, these are 32 bit
2153 struct upk_mips16 upk
;
2154 unpack_mips16 (gdbarch
, pc
, extension
, insn
, jalxtype
, &upk
);
2155 pc
= add_offset_16 (pc
, upk
.offset
);
2156 if ((insn
>> 10) & 0x01) /* Exchange mode */
2157 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode. */
2164 struct upk_mips16 upk
;
2166 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
2167 reg
= get_frame_register_signed (frame
, mips_reg3_to_reg
[upk
.regx
]);
2169 pc
+= (upk
.offset
<< 1) + 2;
2176 struct upk_mips16 upk
;
2178 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
2179 reg
= get_frame_register_signed (frame
, mips_reg3_to_reg
[upk
.regx
]);
2181 pc
+= (upk
.offset
<< 1) + 2;
2186 case 12: /* I8 Formats btez btnez */
2188 struct upk_mips16 upk
;
2190 unpack_mips16 (gdbarch
, pc
, extension
, insn
, i8type
, &upk
);
2191 /* upk.regx contains the opcode */
2192 reg
= get_frame_register_signed (frame
, 24); /* Test register is 24 */
2193 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
2194 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
2195 /* pc = add_offset_16(pc,upk.offset) ; */
2196 pc
+= (upk
.offset
<< 1) + 2;
2201 case 29: /* RR Formats JR, JALR, JALR-RA */
2203 struct upk_mips16 upk
;
2204 /* upk.fmt = rrtype; */
2209 upk
.regx
= (insn
>> 8) & 0x07;
2210 upk
.regy
= (insn
>> 5) & 0x07;
2211 if ((upk
.regy
& 1) == 0)
2212 reg
= mips_reg3_to_reg
[upk
.regx
];
2214 reg
= 31; /* Function return instruction. */
2215 pc
= get_frame_register_signed (frame
, reg
);
2222 /* This is an instruction extension. Fetch the real instruction
2223 (which follows the extension) and decode things based on
2227 pc
= extended_mips16_next_pc (frame
, pc
, insn
,
2228 fetch_mips_16 (gdbarch
, pc
));
2241 mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
2243 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2244 unsigned int insn
= fetch_mips_16 (gdbarch
, pc
);
2245 return extended_mips16_next_pc (frame
, pc
, 0, insn
);
2248 /* The mips_next_pc function supports single_step when the remote
2249 target monitor or stub is not developed enough to do a single_step.
2250 It works by decoding the current instruction and predicting where a
2251 branch will go. This isn't hard because all the data is available.
2252 The MIPS32, MIPS16 and microMIPS variants are quite different. */
2254 mips_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
2256 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2258 if (mips_pc_is_mips16 (gdbarch
, pc
))
2259 return mips16_next_pc (frame
, pc
);
2260 else if (mips_pc_is_micromips (gdbarch
, pc
))
2261 return micromips_next_pc (frame
, pc
);
2263 return mips32_next_pc (frame
, pc
);
2266 /* Return non-zero if the MIPS16 instruction INSN is a compact branch
2270 mips16_instruction_is_compact_branch (unsigned short insn
)
2272 switch (insn
& 0xf800)
2275 return (insn
& 0x009f) == 0x80; /* JALRC/JRC */
2277 return (insn
& 0x0600) == 0; /* BTNEZ/BTEQZ */
2278 case 0x2800: /* BNEZ */
2279 case 0x2000: /* BEQZ */
2280 case 0x1000: /* B */
2287 /* Return non-zero if the microMIPS instruction INSN is a compact branch
2291 micromips_instruction_is_compact_branch (unsigned short insn
)
2293 switch (micromips_op (insn
))
2295 case 0x11: /* POOL16C: bits 010001 */
2296 return (b5s5_op (insn
) == 0x18
2297 /* JRADDIUSP: bits 010001 11000 */
2298 || b5s5_op (insn
) == 0xd);
2299 /* JRC: bits 010011 01101 */
2300 case 0x10: /* POOL32I: bits 010000 */
2301 return (b5s5_op (insn
) & 0x1d) == 0x5;
2302 /* BEQZC/BNEZC: bits 010000 001x1 */
2308 struct mips_frame_cache
2311 struct trad_frame_saved_reg
*saved_regs
;
2314 /* Set a register's saved stack address in temp_saved_regs. If an
2315 address has already been set for this register, do nothing; this
2316 way we will only recognize the first save of a given register in a
2319 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
2320 [gdbarch_num_regs .. 2*gdbarch_num_regs).
2321 Strictly speaking, only the second range is used as it is only second
2322 range (the ABI instead of ISA registers) that comes into play when finding
2323 saved registers in a frame. */
2326 set_reg_offset (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
,
2327 int regnum
, CORE_ADDR offset
)
2329 if (this_cache
!= NULL
2330 && this_cache
->saved_regs
[regnum
].addr
== -1)
2332 this_cache
->saved_regs
[regnum
+ 0 * gdbarch_num_regs (gdbarch
)].addr
2334 this_cache
->saved_regs
[regnum
+ 1 * gdbarch_num_regs (gdbarch
)].addr
2340 /* Fetch the immediate value from a MIPS16 instruction.
2341 If the previous instruction was an EXTEND, use it to extend
2342 the upper bits of the immediate value. This is a helper function
2343 for mips16_scan_prologue. */
2346 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
2347 unsigned short inst
, /* current instruction */
2348 int nbits
, /* number of bits in imm field */
2349 int scale
, /* scale factor to be applied to imm */
2350 int is_signed
) /* is the imm field signed? */
2354 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
2356 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
2357 if (offset
& 0x8000) /* check for negative extend */
2358 offset
= 0 - (0x10000 - (offset
& 0xffff));
2359 return offset
| (inst
& 0x1f);
2363 int max_imm
= 1 << nbits
;
2364 int mask
= max_imm
- 1;
2365 int sign_bit
= max_imm
>> 1;
2367 offset
= inst
& mask
;
2368 if (is_signed
&& (offset
& sign_bit
))
2369 offset
= 0 - (max_imm
- offset
);
2370 return offset
* scale
;
2375 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
2376 the associated FRAME_CACHE if not null.
2377 Return the address of the first instruction past the prologue. */
2380 mips16_scan_prologue (struct gdbarch
*gdbarch
,
2381 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2382 struct frame_info
*this_frame
,
2383 struct mips_frame_cache
*this_cache
)
2385 int prev_non_prologue_insn
= 0;
2386 int this_non_prologue_insn
;
2387 int non_prologue_insns
= 0;
2390 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer. */
2392 long frame_offset
= 0; /* Size of stack frame. */
2393 long frame_adjust
= 0; /* Offset of FP from SP. */
2394 int frame_reg
= MIPS_SP_REGNUM
;
2395 unsigned short prev_inst
= 0; /* saved copy of previous instruction. */
2396 unsigned inst
= 0; /* current instruction */
2397 unsigned entry_inst
= 0; /* the entry instruction */
2398 unsigned save_inst
= 0; /* the save instruction */
2399 int prev_delay_slot
= 0;
2403 int extend_bytes
= 0;
2404 int prev_extend_bytes
= 0;
2405 CORE_ADDR end_prologue_addr
;
2407 /* Can be called when there's no process, and hence when there's no
2409 if (this_frame
!= NULL
)
2410 sp
= get_frame_register_signed (this_frame
,
2411 gdbarch_num_regs (gdbarch
)
2416 if (limit_pc
> start_pc
+ 200)
2417 limit_pc
= start_pc
+ 200;
2420 /* Permit at most one non-prologue non-control-transfer instruction
2421 in the middle which may have been reordered by the compiler for
2423 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
2425 this_non_prologue_insn
= 0;
2428 /* Save the previous instruction. If it's an EXTEND, we'll extract
2429 the immediate offset extension from it in mips16_get_imm. */
2432 /* Fetch and decode the instruction. */
2433 inst
= (unsigned short) mips_fetch_instruction (gdbarch
, ISA_MIPS16
,
2436 /* Normally we ignore extend instructions. However, if it is
2437 not followed by a valid prologue instruction, then this
2438 instruction is not part of the prologue either. We must
2439 remember in this case to adjust the end_prologue_addr back
2441 if ((inst
& 0xf800) == 0xf000) /* extend */
2443 extend_bytes
= MIPS_INSN16_SIZE
;
2447 prev_extend_bytes
= extend_bytes
;
2450 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2451 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2453 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
2454 if (offset
< 0) /* Negative stack adjustment? */
2455 frame_offset
-= offset
;
2457 /* Exit loop if a positive stack adjustment is found, which
2458 usually means that the stack cleanup code in the function
2459 epilogue is reached. */
2462 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
2464 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2465 reg
= mips_reg3_to_reg
[(inst
& 0x700) >> 8];
2466 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2468 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
2470 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2471 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2472 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2474 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
2476 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2477 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2479 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2481 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
2482 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2484 else if (inst
== 0x673d) /* move $s1, $sp */
2489 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
2491 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2492 frame_addr
= sp
+ offset
;
2494 frame_adjust
= offset
;
2496 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2498 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
2499 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2500 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
2502 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2504 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2505 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2506 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
2508 else if ((inst
& 0xf81f) == 0xe809
2509 && (inst
& 0x700) != 0x700) /* entry */
2510 entry_inst
= inst
; /* Save for later processing. */
2511 else if ((inst
& 0xff80) == 0x6480) /* save */
2513 save_inst
= inst
; /* Save for later processing. */
2514 if (prev_extend_bytes
) /* extend */
2515 save_inst
|= prev_inst
<< 16;
2517 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
2519 /* This instruction is part of the prologue, but we don't
2520 need to do anything special to handle it. */
2522 else if (mips16_instruction_has_delay_slot (inst
, 0))
2523 /* JAL/JALR/JALX/JR */
2525 /* The instruction in the delay slot can be a part
2526 of the prologue, so move forward once more. */
2528 if (mips16_instruction_has_delay_slot (inst
, 1))
2531 prev_extend_bytes
= MIPS_INSN16_SIZE
;
2532 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
2537 this_non_prologue_insn
= 1;
2540 non_prologue_insns
+= this_non_prologue_insn
;
2542 /* A jump or branch, or enough non-prologue insns seen? If so,
2543 then we must have reached the end of the prologue by now. */
2544 if (prev_delay_slot
|| non_prologue_insns
> 1
2545 || mips16_instruction_is_compact_branch (inst
))
2548 prev_non_prologue_insn
= this_non_prologue_insn
;
2549 prev_delay_slot
= in_delay_slot
;
2550 prev_pc
= cur_pc
- prev_extend_bytes
;
2553 /* The entry instruction is typically the first instruction in a function,
2554 and it stores registers at offsets relative to the value of the old SP
2555 (before the prologue). But the value of the sp parameter to this
2556 function is the new SP (after the prologue has been executed). So we
2557 can't calculate those offsets until we've seen the entire prologue,
2558 and can calculate what the old SP must have been. */
2559 if (entry_inst
!= 0)
2561 int areg_count
= (entry_inst
>> 8) & 7;
2562 int sreg_count
= (entry_inst
>> 6) & 3;
2564 /* The entry instruction always subtracts 32 from the SP. */
2567 /* Now we can calculate what the SP must have been at the
2568 start of the function prologue. */
2571 /* Check if a0-a3 were saved in the caller's argument save area. */
2572 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
2574 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2575 offset
+= mips_abi_regsize (gdbarch
);
2578 /* Check if the ra register was pushed on the stack. */
2580 if (entry_inst
& 0x20)
2582 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2583 offset
-= mips_abi_regsize (gdbarch
);
2586 /* Check if the s0 and s1 registers were pushed on the stack. */
2587 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2589 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2590 offset
-= mips_abi_regsize (gdbarch
);
2594 /* The SAVE instruction is similar to ENTRY, except that defined by the
2595 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
2596 size of the frame is specified as an immediate field of instruction
2597 and an extended variation exists which lets additional registers and
2598 frame space to be specified. The instruction always treats registers
2599 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
2600 if (save_inst
!= 0 && mips_abi_regsize (gdbarch
) == 4)
2602 static int args_table
[16] = {
2603 0, 0, 0, 0, 1, 1, 1, 1,
2604 2, 2, 2, 0, 3, 3, 4, -1,
2606 static int astatic_table
[16] = {
2607 0, 1, 2, 3, 0, 1, 2, 3,
2608 0, 1, 2, 4, 0, 1, 0, -1,
2610 int aregs
= (save_inst
>> 16) & 0xf;
2611 int xsregs
= (save_inst
>> 24) & 0x7;
2612 int args
= args_table
[aregs
];
2613 int astatic
= astatic_table
[aregs
];
2618 warning (_("Invalid number of argument registers encoded in SAVE."));
2623 warning (_("Invalid number of static registers encoded in SAVE."));
2627 /* For standard SAVE the frame size of 0 means 128. */
2628 frame_size
= ((save_inst
>> 16) & 0xf0) | (save_inst
& 0xf);
2629 if (frame_size
== 0 && (save_inst
>> 16) == 0)
2632 frame_offset
+= frame_size
;
2634 /* Now we can calculate what the SP must have been at the
2635 start of the function prologue. */
2638 /* Check if A0-A3 were saved in the caller's argument save area. */
2639 for (reg
= MIPS_A0_REGNUM
, offset
= 0; reg
< args
+ 4; reg
++)
2641 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2642 offset
+= mips_abi_regsize (gdbarch
);
2647 /* Check if the RA register was pushed on the stack. */
2648 if (save_inst
& 0x40)
2650 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2651 offset
-= mips_abi_regsize (gdbarch
);
2654 /* Check if the S8 register was pushed on the stack. */
2657 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ offset
);
2658 offset
-= mips_abi_regsize (gdbarch
);
2661 /* Check if S2-S7 were pushed on the stack. */
2662 for (reg
= 18 + xsregs
- 1; reg
> 18 - 1; reg
--)
2664 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2665 offset
-= mips_abi_regsize (gdbarch
);
2668 /* Check if the S1 register was pushed on the stack. */
2669 if (save_inst
& 0x10)
2671 set_reg_offset (gdbarch
, this_cache
, 17, sp
+ offset
);
2672 offset
-= mips_abi_regsize (gdbarch
);
2674 /* Check if the S0 register was pushed on the stack. */
2675 if (save_inst
& 0x20)
2677 set_reg_offset (gdbarch
, this_cache
, 16, sp
+ offset
);
2678 offset
-= mips_abi_regsize (gdbarch
);
2681 /* Check if A0-A3 were pushed on the stack. */
2682 for (reg
= MIPS_A0_REGNUM
+ 3; reg
> MIPS_A0_REGNUM
+ 3 - astatic
; reg
--)
2684 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2685 offset
-= mips_abi_regsize (gdbarch
);
2689 if (this_cache
!= NULL
)
2692 (get_frame_register_signed (this_frame
,
2693 gdbarch_num_regs (gdbarch
) + frame_reg
)
2694 + frame_offset
- frame_adjust
);
2695 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
2696 be able to get rid of the assignment below, evetually. But it's
2697 still needed for now. */
2698 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2699 + mips_regnum (gdbarch
)->pc
]
2700 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
2703 /* Set end_prologue_addr to the address of the instruction immediately
2704 after the last one we scanned. Unless the last one looked like a
2705 non-prologue instruction (and we looked ahead), in which case use
2706 its address instead. */
2707 end_prologue_addr
= (prev_non_prologue_insn
|| prev_delay_slot
2708 ? prev_pc
: cur_pc
- prev_extend_bytes
);
2710 return end_prologue_addr
;
2713 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
2714 Procedures that use the 32-bit instruction set are handled by the
2715 mips_insn32 unwinder. */
2717 static struct mips_frame_cache
*
2718 mips_insn16_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2720 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2721 struct mips_frame_cache
*cache
;
2723 if ((*this_cache
) != NULL
)
2724 return (*this_cache
);
2725 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2726 (*this_cache
) = cache
;
2727 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2729 /* Analyze the function prologue. */
2731 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2732 CORE_ADDR start_addr
;
2734 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2735 if (start_addr
== 0)
2736 start_addr
= heuristic_proc_start (gdbarch
, pc
);
2737 /* We can't analyze the prologue if we couldn't find the begining
2739 if (start_addr
== 0)
2742 mips16_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
, *this_cache
);
2745 /* gdbarch_sp_regnum contains the value and not the address. */
2746 trad_frame_set_value (cache
->saved_regs
,
2747 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
2750 return (*this_cache
);
2754 mips_insn16_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2755 struct frame_id
*this_id
)
2757 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2759 /* This marks the outermost frame. */
2760 if (info
->base
== 0)
2762 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2765 static struct value
*
2766 mips_insn16_frame_prev_register (struct frame_info
*this_frame
,
2767 void **this_cache
, int regnum
)
2769 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2771 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2775 mips_insn16_frame_sniffer (const struct frame_unwind
*self
,
2776 struct frame_info
*this_frame
, void **this_cache
)
2778 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2779 CORE_ADDR pc
= get_frame_pc (this_frame
);
2780 if (mips_pc_is_mips16 (gdbarch
, pc
))
2785 static const struct frame_unwind mips_insn16_frame_unwind
=
2788 default_frame_unwind_stop_reason
,
2789 mips_insn16_frame_this_id
,
2790 mips_insn16_frame_prev_register
,
2792 mips_insn16_frame_sniffer
2796 mips_insn16_frame_base_address (struct frame_info
*this_frame
,
2799 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2804 static const struct frame_base mips_insn16_frame_base
=
2806 &mips_insn16_frame_unwind
,
2807 mips_insn16_frame_base_address
,
2808 mips_insn16_frame_base_address
,
2809 mips_insn16_frame_base_address
2812 static const struct frame_base
*
2813 mips_insn16_frame_base_sniffer (struct frame_info
*this_frame
)
2815 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2816 CORE_ADDR pc
= get_frame_pc (this_frame
);
2817 if (mips_pc_is_mips16 (gdbarch
, pc
))
2818 return &mips_insn16_frame_base
;
2823 /* Decode a 9-bit signed immediate argument of ADDIUSP -- -2 is mapped
2824 to -258, -1 -- to -257, 0 -- to 256, 1 -- to 257 and other values are
2825 interpreted directly, and then multiplied by 4. */
2828 micromips_decode_imm9 (int imm
)
2830 imm
= (imm
^ 0x100) - 0x100;
2831 if (imm
> -3 && imm
< 2)
2836 /* Analyze the function prologue from START_PC to LIMIT_PC. Return
2837 the address of the first instruction past the prologue. */
2840 micromips_scan_prologue (struct gdbarch
*gdbarch
,
2841 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2842 struct frame_info
*this_frame
,
2843 struct mips_frame_cache
*this_cache
)
2845 CORE_ADDR end_prologue_addr
;
2846 int prev_non_prologue_insn
= 0;
2847 int frame_reg
= MIPS_SP_REGNUM
;
2848 int this_non_prologue_insn
;
2849 int non_prologue_insns
= 0;
2850 long frame_offset
= 0; /* Size of stack frame. */
2851 long frame_adjust
= 0; /* Offset of FP from SP. */
2852 CORE_ADDR frame_addr
= 0; /* Value of $30, used as frame pointer. */
2853 int prev_delay_slot
= 0;
2857 ULONGEST insn
; /* current instruction */
2861 long v1_off
= 0; /* The assumption is LUI will replace it. */
2872 /* Can be called when there's no process, and hence when there's no
2874 if (this_frame
!= NULL
)
2875 sp
= get_frame_register_signed (this_frame
,
2876 gdbarch_num_regs (gdbarch
)
2881 if (limit_pc
> start_pc
+ 200)
2882 limit_pc
= start_pc
+ 200;
2885 /* Permit at most one non-prologue non-control-transfer instruction
2886 in the middle which may have been reordered by the compiler for
2888 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= loc
)
2890 this_non_prologue_insn
= 0;
2894 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, cur_pc
, NULL
);
2895 loc
+= MIPS_INSN16_SIZE
;
2896 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
2898 /* 48-bit instructions. */
2899 case 3 * MIPS_INSN16_SIZE
:
2900 /* No prologue instructions in this category. */
2901 this_non_prologue_insn
= 1;
2902 loc
+= 2 * MIPS_INSN16_SIZE
;
2905 /* 32-bit instructions. */
2906 case 2 * MIPS_INSN16_SIZE
:
2908 insn
|= mips_fetch_instruction (gdbarch
,
2909 ISA_MICROMIPS
, cur_pc
+ loc
, NULL
);
2910 loc
+= MIPS_INSN16_SIZE
;
2911 switch (micromips_op (insn
>> 16))
2913 /* Record $sp/$fp adjustment. */
2914 /* Discard (D)ADDU $gp,$jp used for PIC code. */
2915 case 0x0: /* POOL32A: bits 000000 */
2916 case 0x16: /* POOL32S: bits 010110 */
2917 op
= b0s11_op (insn
);
2918 sreg
= b0s5_reg (insn
>> 16);
2919 treg
= b5s5_reg (insn
>> 16);
2920 dreg
= b11s5_reg (insn
);
2922 /* SUBU: bits 000000 00111010000 */
2923 /* DSUBU: bits 010110 00111010000 */
2924 && dreg
== MIPS_SP_REGNUM
&& sreg
== MIPS_SP_REGNUM
2926 /* (D)SUBU $sp, $v1 */
2928 else if (op
!= 0x150
2929 /* ADDU: bits 000000 00101010000 */
2930 /* DADDU: bits 010110 00101010000 */
2931 || dreg
!= 28 || sreg
!= 28 || treg
!= MIPS_T9_REGNUM
)
2932 this_non_prologue_insn
= 1;
2935 case 0x8: /* POOL32B: bits 001000 */
2936 op
= b12s4_op (insn
);
2937 breg
= b0s5_reg (insn
>> 16);
2938 reglist
= sreg
= b5s5_reg (insn
>> 16);
2939 offset
= (b0s12_imm (insn
) ^ 0x800) - 0x800;
2940 if ((op
== 0x9 || op
== 0xc)
2941 /* SWP: bits 001000 1001 */
2942 /* SDP: bits 001000 1100 */
2943 && breg
== MIPS_SP_REGNUM
&& sreg
< MIPS_RA_REGNUM
)
2944 /* S[DW]P reg,offset($sp) */
2946 s
= 4 << ((b12s4_op (insn
) & 0x4) == 0x4);
2947 set_reg_offset (gdbarch
, this_cache
,
2949 set_reg_offset (gdbarch
, this_cache
,
2950 sreg
+ 1, sp
+ offset
+ s
);
2952 else if ((op
== 0xd || op
== 0xf)
2953 /* SWM: bits 001000 1101 */
2954 /* SDM: bits 001000 1111 */
2955 && breg
== MIPS_SP_REGNUM
2956 /* SWM reglist,offset($sp) */
2957 && ((reglist
>= 1 && reglist
<= 9)
2958 || (reglist
>= 16 && reglist
<= 25)))
2960 int sreglist
= min(reglist
& 0xf, 8);
2962 s
= 4 << ((b12s4_op (insn
) & 0x2) == 0x2);
2963 for (i
= 0; i
< sreglist
; i
++)
2964 set_reg_offset (gdbarch
, this_cache
, 16 + i
, sp
+ s
* i
);
2965 if ((reglist
& 0xf) > 8)
2966 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ s
* i
++);
2967 if ((reglist
& 0x10) == 0x10)
2968 set_reg_offset (gdbarch
, this_cache
,
2969 MIPS_RA_REGNUM
, sp
+ s
* i
++);
2972 this_non_prologue_insn
= 1;
2975 /* Record $sp/$fp adjustment. */
2976 /* Discard (D)ADDIU $gp used for PIC code. */
2977 case 0xc: /* ADDIU: bits 001100 */
2978 case 0x17: /* DADDIU: bits 010111 */
2979 sreg
= b0s5_reg (insn
>> 16);
2980 dreg
= b5s5_reg (insn
>> 16);
2981 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
2982 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
)
2983 /* (D)ADDIU $sp, imm */
2985 else if (sreg
== MIPS_SP_REGNUM
&& dreg
== 30)
2986 /* (D)ADDIU $fp, $sp, imm */
2988 frame_addr
= sp
+ offset
;
2989 frame_adjust
= offset
;
2992 else if (sreg
!= 28 || dreg
!= 28)
2993 /* (D)ADDIU $gp, imm */
2994 this_non_prologue_insn
= 1;
2997 /* LUI $v1 is used for larger $sp adjustments. */
2998 /* Discard LUI $gp used for PIC code. */
2999 case 0x10: /* POOL32I: bits 010000 */
3000 if (b5s5_op (insn
>> 16) == 0xd
3001 /* LUI: bits 010000 001101 */
3002 && b0s5_reg (insn
>> 16) == 3)
3004 v1_off
= ((b0s16_imm (insn
) << 16) ^ 0x80000000) - 0x80000000;
3005 else if (b5s5_op (insn
>> 16) != 0xd
3006 /* LUI: bits 010000 001101 */
3007 || b0s5_reg (insn
>> 16) != 28)
3009 this_non_prologue_insn
= 1;
3012 /* ORI $v1 is used for larger $sp adjustments. */
3013 case 0x14: /* ORI: bits 010100 */
3014 sreg
= b0s5_reg (insn
>> 16);
3015 dreg
= b5s5_reg (insn
>> 16);
3016 if (sreg
== 3 && dreg
== 3)
3018 v1_off
|= b0s16_imm (insn
);
3020 this_non_prologue_insn
= 1;
3023 case 0x26: /* SWC1: bits 100110 */
3024 case 0x2e: /* SDC1: bits 101110 */
3025 breg
= b0s5_reg (insn
>> 16);
3026 if (breg
!= MIPS_SP_REGNUM
)
3027 /* S[DW]C1 reg,offset($sp) */
3028 this_non_prologue_insn
= 1;
3031 case 0x36: /* SD: bits 110110 */
3032 case 0x3e: /* SW: bits 111110 */
3033 breg
= b0s5_reg (insn
>> 16);
3034 sreg
= b5s5_reg (insn
>> 16);
3035 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
3036 if (breg
== MIPS_SP_REGNUM
)
3037 /* S[DW] reg,offset($sp) */
3038 set_reg_offset (gdbarch
, this_cache
, sreg
, sp
+ offset
);
3040 this_non_prologue_insn
= 1;
3044 /* The instruction in the delay slot can be a part
3045 of the prologue, so move forward once more. */
3046 if (micromips_instruction_has_delay_slot (insn
, 0))
3049 this_non_prologue_insn
= 1;
3055 /* 16-bit instructions. */
3056 case MIPS_INSN16_SIZE
:
3057 switch (micromips_op (insn
))
3059 case 0x3: /* MOVE: bits 000011 */
3060 sreg
= b0s5_reg (insn
);
3061 dreg
= b5s5_reg (insn
);
3062 if (sreg
== MIPS_SP_REGNUM
&& dreg
== 30)
3068 else if ((sreg
& 0x1c) != 0x4)
3069 /* MOVE reg, $a0-$a3 */
3070 this_non_prologue_insn
= 1;
3073 case 0x11: /* POOL16C: bits 010001 */
3074 if (b6s4_op (insn
) == 0x5)
3075 /* SWM: bits 010001 0101 */
3077 offset
= ((b0s4_imm (insn
) << 2) ^ 0x20) - 0x20;
3078 reglist
= b4s2_regl (insn
);
3079 for (i
= 0; i
<= reglist
; i
++)
3080 set_reg_offset (gdbarch
, this_cache
, 16 + i
, sp
+ 4 * i
);
3081 set_reg_offset (gdbarch
, this_cache
,
3082 MIPS_RA_REGNUM
, sp
+ 4 * i
++);
3085 this_non_prologue_insn
= 1;
3088 case 0x13: /* POOL16D: bits 010011 */
3089 if ((insn
& 0x1) == 0x1)
3090 /* ADDIUSP: bits 010011 1 */
3091 sp_adj
= micromips_decode_imm9 (b1s9_imm (insn
));
3092 else if (b5s5_reg (insn
) == MIPS_SP_REGNUM
)
3093 /* ADDIUS5: bits 010011 0 */
3094 /* ADDIUS5 $sp, imm */
3095 sp_adj
= (b1s4_imm (insn
) ^ 8) - 8;
3097 this_non_prologue_insn
= 1;
3100 case 0x32: /* SWSP: bits 110010 */
3101 offset
= b0s5_imm (insn
) << 2;
3102 sreg
= b5s5_reg (insn
);
3103 set_reg_offset (gdbarch
, this_cache
, sreg
, sp
+ offset
);
3107 /* The instruction in the delay slot can be a part
3108 of the prologue, so move forward once more. */
3109 if (micromips_instruction_has_delay_slot (insn
<< 16, 0))
3112 this_non_prologue_insn
= 1;
3118 frame_offset
-= sp_adj
;
3120 non_prologue_insns
+= this_non_prologue_insn
;
3122 /* A jump or branch, enough non-prologue insns seen or positive
3123 stack adjustment? If so, then we must have reached the end
3124 of the prologue by now. */
3125 if (prev_delay_slot
|| non_prologue_insns
> 1 || sp_adj
> 0
3126 || micromips_instruction_is_compact_branch (insn
))
3129 prev_non_prologue_insn
= this_non_prologue_insn
;
3130 prev_delay_slot
= in_delay_slot
;
3134 if (this_cache
!= NULL
)
3137 (get_frame_register_signed (this_frame
,
3138 gdbarch_num_regs (gdbarch
) + frame_reg
)
3139 + frame_offset
- frame_adjust
);
3140 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
3141 be able to get rid of the assignment below, evetually. But it's
3142 still needed for now. */
3143 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3144 + mips_regnum (gdbarch
)->pc
]
3145 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
3148 /* Set end_prologue_addr to the address of the instruction immediately
3149 after the last one we scanned. Unless the last one looked like a
3150 non-prologue instruction (and we looked ahead), in which case use
3151 its address instead. */
3153 = prev_non_prologue_insn
|| prev_delay_slot
? prev_pc
: cur_pc
;
3155 return end_prologue_addr
;
3158 /* Heuristic unwinder for procedures using microMIPS instructions.
3159 Procedures that use the 32-bit instruction set are handled by the
3160 mips_insn32 unwinder. Likewise MIPS16 and the mips_insn16 unwinder. */
3162 static struct mips_frame_cache
*
3163 mips_micro_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3165 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3166 struct mips_frame_cache
*cache
;
3168 if ((*this_cache
) != NULL
)
3169 return (*this_cache
);
3171 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
3172 (*this_cache
) = cache
;
3173 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3175 /* Analyze the function prologue. */
3177 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3178 CORE_ADDR start_addr
;
3180 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3181 if (start_addr
== 0)
3182 start_addr
= heuristic_proc_start (get_frame_arch (this_frame
), pc
);
3183 /* We can't analyze the prologue if we couldn't find the begining
3185 if (start_addr
== 0)
3188 micromips_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
, *this_cache
);
3191 /* gdbarch_sp_regnum contains the value and not the address. */
3192 trad_frame_set_value (cache
->saved_regs
,
3193 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
3196 return (*this_cache
);
3200 mips_micro_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3201 struct frame_id
*this_id
)
3203 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3205 /* This marks the outermost frame. */
3206 if (info
->base
== 0)
3208 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3211 static struct value
*
3212 mips_micro_frame_prev_register (struct frame_info
*this_frame
,
3213 void **this_cache
, int regnum
)
3215 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3217 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3221 mips_micro_frame_sniffer (const struct frame_unwind
*self
,
3222 struct frame_info
*this_frame
, void **this_cache
)
3224 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3225 CORE_ADDR pc
= get_frame_pc (this_frame
);
3227 if (mips_pc_is_micromips (gdbarch
, pc
))
3232 static const struct frame_unwind mips_micro_frame_unwind
=
3235 default_frame_unwind_stop_reason
,
3236 mips_micro_frame_this_id
,
3237 mips_micro_frame_prev_register
,
3239 mips_micro_frame_sniffer
3243 mips_micro_frame_base_address (struct frame_info
*this_frame
,
3246 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3251 static const struct frame_base mips_micro_frame_base
=
3253 &mips_micro_frame_unwind
,
3254 mips_micro_frame_base_address
,
3255 mips_micro_frame_base_address
,
3256 mips_micro_frame_base_address
3259 static const struct frame_base
*
3260 mips_micro_frame_base_sniffer (struct frame_info
*this_frame
)
3262 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3263 CORE_ADDR pc
= get_frame_pc (this_frame
);
3265 if (mips_pc_is_micromips (gdbarch
, pc
))
3266 return &mips_micro_frame_base
;
3271 /* Mark all the registers as unset in the saved_regs array
3272 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
3275 reset_saved_regs (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
)
3277 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
3281 const int num_regs
= gdbarch_num_regs (gdbarch
);
3284 for (i
= 0; i
< num_regs
; i
++)
3286 this_cache
->saved_regs
[i
].addr
= -1;
3291 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
3292 the associated FRAME_CACHE if not null.
3293 Return the address of the first instruction past the prologue. */
3296 mips32_scan_prologue (struct gdbarch
*gdbarch
,
3297 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
3298 struct frame_info
*this_frame
,
3299 struct mips_frame_cache
*this_cache
)
3301 int prev_non_prologue_insn
;
3302 int this_non_prologue_insn
;
3303 int non_prologue_insns
;
3304 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for
3306 int prev_delay_slot
;
3311 int frame_reg
= MIPS_SP_REGNUM
;
3313 CORE_ADDR end_prologue_addr
;
3314 int seen_sp_adjust
= 0;
3315 int load_immediate_bytes
= 0;
3317 int regsize_is_64_bits
= (mips_abi_regsize (gdbarch
) == 8);
3319 /* Can be called when there's no process, and hence when there's no
3321 if (this_frame
!= NULL
)
3322 sp
= get_frame_register_signed (this_frame
,
3323 gdbarch_num_regs (gdbarch
)
3328 if (limit_pc
> start_pc
+ 200)
3329 limit_pc
= start_pc
+ 200;
3332 prev_non_prologue_insn
= 0;
3333 non_prologue_insns
= 0;
3334 prev_delay_slot
= 0;
3337 /* Permit at most one non-prologue non-control-transfer instruction
3338 in the middle which may have been reordered by the compiler for
3341 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
3343 unsigned long inst
, high_word
, low_word
;
3346 this_non_prologue_insn
= 0;
3349 /* Fetch the instruction. */
3350 inst
= (unsigned long) mips_fetch_instruction (gdbarch
, ISA_MIPS
,
3353 /* Save some code by pre-extracting some useful fields. */
3354 high_word
= (inst
>> 16) & 0xffff;
3355 low_word
= inst
& 0xffff;
3356 reg
= high_word
& 0x1f;
3358 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
3359 || high_word
== 0x23bd /* addi $sp,$sp,-i */
3360 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
3362 if (low_word
& 0x8000) /* Negative stack adjustment? */
3363 frame_offset
+= 0x10000 - low_word
;
3365 /* Exit loop if a positive stack adjustment is found, which
3366 usually means that the stack cleanup code in the function
3367 epilogue is reached. */
3371 else if (((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
3372 && !regsize_is_64_bits
)
3374 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ low_word
);
3376 else if (((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
3377 && regsize_is_64_bits
)
3379 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
3380 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ low_word
);
3382 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
3384 /* Old gcc frame, r30 is virtual frame pointer. */
3385 if ((long) low_word
!= frame_offset
)
3386 frame_addr
= sp
+ low_word
;
3387 else if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
3389 unsigned alloca_adjust
;
3392 frame_addr
= get_frame_register_signed
3393 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
3396 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
3397 if (alloca_adjust
> 0)
3399 /* FP > SP + frame_size. This may be because of
3400 an alloca or somethings similar. Fix sp to
3401 "pre-alloca" value, and try again. */
3402 sp
+= alloca_adjust
;
3403 /* Need to reset the status of all registers. Otherwise,
3404 we will hit a guard that prevents the new address
3405 for each register to be recomputed during the second
3407 reset_saved_regs (gdbarch
, this_cache
);
3412 /* move $30,$sp. With different versions of gas this will be either
3413 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
3414 Accept any one of these. */
3415 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
3417 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
3418 if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
3420 unsigned alloca_adjust
;
3423 frame_addr
= get_frame_register_signed
3424 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
3426 alloca_adjust
= (unsigned) (frame_addr
- sp
);
3427 if (alloca_adjust
> 0)
3429 /* FP > SP + frame_size. This may be because of
3430 an alloca or somethings similar. Fix sp to
3431 "pre-alloca" value, and try again. */
3433 /* Need to reset the status of all registers. Otherwise,
3434 we will hit a guard that prevents the new address
3435 for each register to be recomputed during the second
3437 reset_saved_regs (gdbarch
, this_cache
);
3442 else if ((high_word
& 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
3443 && !regsize_is_64_bits
)
3445 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ low_word
);
3447 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
3448 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
3449 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
3450 || high_word
== 0x3c1c /* lui $gp,n */
3451 || high_word
== 0x279c /* addiu $gp,$gp,n */
3452 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
3453 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
3456 /* These instructions are part of the prologue, but we don't
3457 need to do anything special to handle them. */
3459 /* The instructions below load $at or $t0 with an immediate
3460 value in preparation for a stack adjustment via
3461 subu $sp,$sp,[$at,$t0]. These instructions could also
3462 initialize a local variable, so we accept them only before
3463 a stack adjustment instruction was seen. */
3464 else if (!seen_sp_adjust
3466 && (high_word
== 0x3c01 /* lui $at,n */
3467 || high_word
== 0x3c08 /* lui $t0,n */
3468 || high_word
== 0x3421 /* ori $at,$at,n */
3469 || high_word
== 0x3508 /* ori $t0,$t0,n */
3470 || high_word
== 0x3401 /* ori $at,$zero,n */
3471 || high_word
== 0x3408 /* ori $t0,$zero,n */
3474 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
3476 /* Check for branches and jumps. The instruction in the delay
3477 slot can be a part of the prologue, so move forward once more. */
3478 else if (mips32_instruction_has_delay_slot (gdbarch
, inst
))
3482 /* This instruction is not an instruction typically found
3483 in a prologue, so we must have reached the end of the
3487 this_non_prologue_insn
= 1;
3490 non_prologue_insns
+= this_non_prologue_insn
;
3492 /* A jump or branch, or enough non-prologue insns seen? If so,
3493 then we must have reached the end of the prologue by now. */
3494 if (prev_delay_slot
|| non_prologue_insns
> 1)
3497 prev_non_prologue_insn
= this_non_prologue_insn
;
3498 prev_delay_slot
= in_delay_slot
;
3502 if (this_cache
!= NULL
)
3505 (get_frame_register_signed (this_frame
,
3506 gdbarch_num_regs (gdbarch
) + frame_reg
)
3508 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
3509 this assignment below, eventually. But it's still needed
3511 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3512 + mips_regnum (gdbarch
)->pc
]
3513 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3517 /* Set end_prologue_addr to the address of the instruction immediately
3518 after the last one we scanned. Unless the last one looked like a
3519 non-prologue instruction (and we looked ahead), in which case use
3520 its address instead. */
3522 = prev_non_prologue_insn
|| prev_delay_slot
? prev_pc
: cur_pc
;
3524 /* In a frameless function, we might have incorrectly
3525 skipped some load immediate instructions. Undo the skipping
3526 if the load immediate was not followed by a stack adjustment. */
3527 if (load_immediate_bytes
&& !seen_sp_adjust
)
3528 end_prologue_addr
-= load_immediate_bytes
;
3530 return end_prologue_addr
;
3533 /* Heuristic unwinder for procedures using 32-bit instructions (covers
3534 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
3535 instructions (a.k.a. MIPS16) are handled by the mips_insn16
3536 unwinder. Likewise microMIPS and the mips_micro unwinder. */
3538 static struct mips_frame_cache
*
3539 mips_insn32_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3541 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3542 struct mips_frame_cache
*cache
;
3544 if ((*this_cache
) != NULL
)
3545 return (*this_cache
);
3547 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
3548 (*this_cache
) = cache
;
3549 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3551 /* Analyze the function prologue. */
3553 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3554 CORE_ADDR start_addr
;
3556 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3557 if (start_addr
== 0)
3558 start_addr
= heuristic_proc_start (gdbarch
, pc
);
3559 /* We can't analyze the prologue if we couldn't find the begining
3561 if (start_addr
== 0)
3564 mips32_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
, *this_cache
);
3567 /* gdbarch_sp_regnum contains the value and not the address. */
3568 trad_frame_set_value (cache
->saved_regs
,
3569 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
3572 return (*this_cache
);
3576 mips_insn32_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3577 struct frame_id
*this_id
)
3579 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3581 /* This marks the outermost frame. */
3582 if (info
->base
== 0)
3584 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3587 static struct value
*
3588 mips_insn32_frame_prev_register (struct frame_info
*this_frame
,
3589 void **this_cache
, int regnum
)
3591 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3593 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3597 mips_insn32_frame_sniffer (const struct frame_unwind
*self
,
3598 struct frame_info
*this_frame
, void **this_cache
)
3600 CORE_ADDR pc
= get_frame_pc (this_frame
);
3601 if (mips_pc_is_mips (pc
))
3606 static const struct frame_unwind mips_insn32_frame_unwind
=
3609 default_frame_unwind_stop_reason
,
3610 mips_insn32_frame_this_id
,
3611 mips_insn32_frame_prev_register
,
3613 mips_insn32_frame_sniffer
3617 mips_insn32_frame_base_address (struct frame_info
*this_frame
,
3620 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3625 static const struct frame_base mips_insn32_frame_base
=
3627 &mips_insn32_frame_unwind
,
3628 mips_insn32_frame_base_address
,
3629 mips_insn32_frame_base_address
,
3630 mips_insn32_frame_base_address
3633 static const struct frame_base
*
3634 mips_insn32_frame_base_sniffer (struct frame_info
*this_frame
)
3636 CORE_ADDR pc
= get_frame_pc (this_frame
);
3637 if (mips_pc_is_mips (pc
))
3638 return &mips_insn32_frame_base
;
3643 static struct trad_frame_cache
*
3644 mips_stub_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3647 CORE_ADDR start_addr
;
3648 CORE_ADDR stack_addr
;
3649 struct trad_frame_cache
*this_trad_cache
;
3650 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3651 int num_regs
= gdbarch_num_regs (gdbarch
);
3653 if ((*this_cache
) != NULL
)
3654 return (*this_cache
);
3655 this_trad_cache
= trad_frame_cache_zalloc (this_frame
);
3656 (*this_cache
) = this_trad_cache
;
3658 /* The return address is in the link register. */
3659 trad_frame_set_reg_realreg (this_trad_cache
,
3660 gdbarch_pc_regnum (gdbarch
),
3661 num_regs
+ MIPS_RA_REGNUM
);
3663 /* Frame ID, since it's a frameless / stackless function, no stack
3664 space is allocated and SP on entry is the current SP. */
3665 pc
= get_frame_pc (this_frame
);
3666 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3667 stack_addr
= get_frame_register_signed (this_frame
,
3668 num_regs
+ MIPS_SP_REGNUM
);
3669 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
3671 /* Assume that the frame's base is the same as the
3673 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
3675 return this_trad_cache
;
3679 mips_stub_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3680 struct frame_id
*this_id
)
3682 struct trad_frame_cache
*this_trad_cache
3683 = mips_stub_frame_cache (this_frame
, this_cache
);
3684 trad_frame_get_id (this_trad_cache
, this_id
);
3687 static struct value
*
3688 mips_stub_frame_prev_register (struct frame_info
*this_frame
,
3689 void **this_cache
, int regnum
)
3691 struct trad_frame_cache
*this_trad_cache
3692 = mips_stub_frame_cache (this_frame
, this_cache
);
3693 return trad_frame_get_register (this_trad_cache
, this_frame
, regnum
);
3697 mips_stub_frame_sniffer (const struct frame_unwind
*self
,
3698 struct frame_info
*this_frame
, void **this_cache
)
3701 struct obj_section
*s
;
3702 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3703 struct bound_minimal_symbol msym
;
3705 /* Use the stub unwinder for unreadable code. */
3706 if (target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
3709 if (in_plt_section (pc
) || in_mips_stubs_section (pc
))
3712 /* Calling a PIC function from a non-PIC function passes through a
3713 stub. The stub for foo is named ".pic.foo". */
3714 msym
= lookup_minimal_symbol_by_pc (pc
);
3715 if (msym
.minsym
!= NULL
3716 && MSYMBOL_LINKAGE_NAME (msym
.minsym
) != NULL
3717 && strncmp (MSYMBOL_LINKAGE_NAME (msym
.minsym
), ".pic.", 5) == 0)
3723 static const struct frame_unwind mips_stub_frame_unwind
=
3726 default_frame_unwind_stop_reason
,
3727 mips_stub_frame_this_id
,
3728 mips_stub_frame_prev_register
,
3730 mips_stub_frame_sniffer
3734 mips_stub_frame_base_address (struct frame_info
*this_frame
,
3737 struct trad_frame_cache
*this_trad_cache
3738 = mips_stub_frame_cache (this_frame
, this_cache
);
3739 return trad_frame_get_this_base (this_trad_cache
);
3742 static const struct frame_base mips_stub_frame_base
=
3744 &mips_stub_frame_unwind
,
3745 mips_stub_frame_base_address
,
3746 mips_stub_frame_base_address
,
3747 mips_stub_frame_base_address
3750 static const struct frame_base
*
3751 mips_stub_frame_base_sniffer (struct frame_info
*this_frame
)
3753 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind
, this_frame
, NULL
))
3754 return &mips_stub_frame_base
;
3759 /* mips_addr_bits_remove - remove useless address bits */
3762 mips_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
3764 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3766 if (is_compact_addr (addr
))
3767 addr
= unmake_compact_addr (addr
);
3769 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
3770 /* This hack is a work-around for existing boards using PMON, the
3771 simulator, and any other 64-bit targets that doesn't have true
3772 64-bit addressing. On these targets, the upper 32 bits of
3773 addresses are ignored by the hardware. Thus, the PC or SP are
3774 likely to have been sign extended to all 1s by instruction
3775 sequences that load 32-bit addresses. For example, a typical
3776 piece of code that loads an address is this:
3778 lui $r2, <upper 16 bits>
3779 ori $r2, <lower 16 bits>
3781 But the lui sign-extends the value such that the upper 32 bits
3782 may be all 1s. The workaround is simply to mask off these
3783 bits. In the future, gcc may be changed to support true 64-bit
3784 addressing, and this masking will have to be disabled. */
3785 return addr
&= 0xffffffffUL
;
3791 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
3792 instruction and ending with a SC/SCD instruction. If such a sequence
3793 is found, attempt to step through it. A breakpoint is placed at the end of
3796 /* Instructions used during single-stepping of atomic sequences, standard
3798 #define LL_OPCODE 0x30
3799 #define LLD_OPCODE 0x34
3800 #define SC_OPCODE 0x38
3801 #define SCD_OPCODE 0x3c
3804 mips_deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
3805 struct address_space
*aspace
, CORE_ADDR pc
)
3807 CORE_ADDR breaks
[2] = {-1, -1};
3809 CORE_ADDR branch_bp
; /* Breakpoint at branch instruction's destination. */
3813 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
3814 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
3816 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, loc
, NULL
);
3817 /* Assume all atomic sequences start with a ll/lld instruction. */
3818 if (itype_op (insn
) != LL_OPCODE
&& itype_op (insn
) != LLD_OPCODE
)
3821 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
3823 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
3826 loc
+= MIPS_INSN32_SIZE
;
3827 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, loc
, NULL
);
3829 /* Assume that there is at most one branch in the atomic
3830 sequence. If a branch is found, put a breakpoint in its
3831 destination address. */
3832 switch (itype_op (insn
))
3834 case 0: /* SPECIAL */
3835 if (rtype_funct (insn
) >> 1 == 4) /* JR, JALR */
3836 return 0; /* fallback to the standard single-step code. */
3838 case 1: /* REGIMM */
3839 is_branch
= ((itype_rt (insn
) & 0xc) == 0 /* B{LT,GE}Z* */
3840 || ((itype_rt (insn
) & 0x1e) == 0
3841 && itype_rs (insn
) == 0)); /* BPOSGE* */
3845 return 0; /* fallback to the standard single-step code. */
3852 case 22: /* BLEZL */
3853 case 23: /* BGTTL */
3857 is_branch
= ((itype_rs (insn
) == 9 || itype_rs (insn
) == 10)
3858 && (itype_rt (insn
) & 0x2) == 0);
3859 if (is_branch
) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */
3864 is_branch
= (itype_rs (insn
) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
3869 branch_bp
= loc
+ mips32_relative_offset (insn
) + 4;
3870 if (last_breakpoint
>= 1)
3871 return 0; /* More than one branch found, fallback to the
3872 standard single-step code. */
3873 breaks
[1] = branch_bp
;
3877 if (itype_op (insn
) == SC_OPCODE
|| itype_op (insn
) == SCD_OPCODE
)
3881 /* Assume that the atomic sequence ends with a sc/scd instruction. */
3882 if (itype_op (insn
) != SC_OPCODE
&& itype_op (insn
) != SCD_OPCODE
)
3885 loc
+= MIPS_INSN32_SIZE
;
3887 /* Insert a breakpoint right after the end of the atomic sequence. */
3890 /* Check for duplicated breakpoints. Check also for a breakpoint
3891 placed (branch instruction's destination) in the atomic sequence. */
3892 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
3893 last_breakpoint
= 0;
3895 /* Effectively inserts the breakpoints. */
3896 for (index
= 0; index
<= last_breakpoint
; index
++)
3897 insert_single_step_breakpoint (gdbarch
, aspace
, breaks
[index
]);
3903 micromips_deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
3904 struct address_space
*aspace
,
3907 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
3908 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
3909 CORE_ADDR breaks
[2] = {-1, -1};
3910 CORE_ADDR branch_bp
= 0; /* Breakpoint at branch instruction's
3918 /* Assume all atomic sequences start with a ll/lld instruction. */
3919 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
3920 if (micromips_op (insn
) != 0x18) /* POOL32C: bits 011000 */
3922 loc
+= MIPS_INSN16_SIZE
;
3924 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
3925 if ((b12s4_op (insn
) & 0xb) != 0x3) /* LL, LLD: bits 011000 0x11 */
3927 loc
+= MIPS_INSN16_SIZE
;
3929 /* Assume all atomic sequences end with an sc/scd instruction. Assume
3930 that no atomic sequence is longer than "atomic_sequence_length"
3932 for (insn_count
= 0;
3933 !sc_found
&& insn_count
< atomic_sequence_length
;
3938 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
3939 loc
+= MIPS_INSN16_SIZE
;
3941 /* Assume that there is at most one conditional branch in the
3942 atomic sequence. If a branch is found, put a breakpoint in
3943 its destination address. */
3944 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
3946 /* 48-bit instructions. */
3947 case 3 * MIPS_INSN16_SIZE
: /* POOL48A: bits 011111 */
3948 loc
+= 2 * MIPS_INSN16_SIZE
;
3951 /* 32-bit instructions. */
3952 case 2 * MIPS_INSN16_SIZE
:
3953 switch (micromips_op (insn
))
3955 case 0x10: /* POOL32I: bits 010000 */
3956 if ((b5s5_op (insn
) & 0x18) != 0x0
3957 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
3958 /* BLEZ, BNEZC, BGTZ, BEQZC: 010000 001xx */
3959 && (b5s5_op (insn
) & 0x1d) != 0x11
3960 /* BLTZALS, BGEZALS: bits 010000 100x1 */
3961 && ((b5s5_op (insn
) & 0x1e) != 0x14
3962 || (insn
& 0x3) != 0x0)
3963 /* BC2F, BC2T: bits 010000 1010x xxx00 */
3964 && (b5s5_op (insn
) & 0x1e) != 0x1a
3965 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
3966 && ((b5s5_op (insn
) & 0x1e) != 0x1c
3967 || (insn
& 0x3) != 0x0)
3968 /* BC1F, BC1T: bits 010000 1110x xxx00 */
3969 && ((b5s5_op (insn
) & 0x1c) != 0x1c
3970 || (insn
& 0x3) != 0x1))
3971 /* BC1ANY*: bits 010000 111xx xxx01 */
3975 case 0x25: /* BEQ: bits 100101 */
3976 case 0x2d: /* BNE: bits 101101 */
3978 insn
|= mips_fetch_instruction (gdbarch
,
3979 ISA_MICROMIPS
, loc
, NULL
);
3980 branch_bp
= (loc
+ MIPS_INSN16_SIZE
3981 + micromips_relative_offset16 (insn
));
3985 case 0x00: /* POOL32A: bits 000000 */
3987 insn
|= mips_fetch_instruction (gdbarch
,
3988 ISA_MICROMIPS
, loc
, NULL
);
3989 if (b0s6_op (insn
) != 0x3c
3990 /* POOL32Axf: bits 000000 ... 111100 */
3991 || (b6s10_ext (insn
) & 0x2bf) != 0x3c)
3992 /* JALR, JALR.HB: 000000 000x111100 111100 */
3993 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
3997 case 0x1d: /* JALS: bits 011101 */
3998 case 0x35: /* J: bits 110101 */
3999 case 0x3d: /* JAL: bits 111101 */
4000 case 0x3c: /* JALX: bits 111100 */
4001 return 0; /* Fall back to the standard single-step code. */
4003 case 0x18: /* POOL32C: bits 011000 */
4004 if ((b12s4_op (insn
) & 0xb) == 0xb)
4005 /* SC, SCD: bits 011000 1x11 */
4009 loc
+= MIPS_INSN16_SIZE
;
4012 /* 16-bit instructions. */
4013 case MIPS_INSN16_SIZE
:
4014 switch (micromips_op (insn
))
4016 case 0x23: /* BEQZ16: bits 100011 */
4017 case 0x2b: /* BNEZ16: bits 101011 */
4018 branch_bp
= loc
+ micromips_relative_offset7 (insn
);
4022 case 0x11: /* POOL16C: bits 010001 */
4023 if ((b5s5_op (insn
) & 0x1c) != 0xc
4024 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
4025 && b5s5_op (insn
) != 0x18)
4026 /* JRADDIUSP: bits 010001 11000 */
4028 return 0; /* Fall back to the standard single-step code. */
4030 case 0x33: /* B16: bits 110011 */
4031 return 0; /* Fall back to the standard single-step code. */
4037 if (last_breakpoint
>= 1)
4038 return 0; /* More than one branch found, fallback to the
4039 standard single-step code. */
4040 breaks
[1] = branch_bp
;
4047 /* Insert a breakpoint right after the end of the atomic sequence. */
4050 /* Check for duplicated breakpoints. Check also for a breakpoint
4051 placed (branch instruction's destination) in the atomic sequence */
4052 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
4053 last_breakpoint
= 0;
4055 /* Effectively inserts the breakpoints. */
4056 for (index
= 0; index
<= last_breakpoint
; index
++)
4057 insert_single_step_breakpoint (gdbarch
, aspace
, breaks
[index
]);
4063 deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
4064 struct address_space
*aspace
, CORE_ADDR pc
)
4066 if (mips_pc_is_mips (pc
))
4067 return mips_deal_with_atomic_sequence (gdbarch
, aspace
, pc
);
4068 else if (mips_pc_is_micromips (gdbarch
, pc
))
4069 return micromips_deal_with_atomic_sequence (gdbarch
, aspace
, pc
);
4074 /* mips_software_single_step() is called just before we want to resume
4075 the inferior, if we want to single-step it but there is no hardware
4076 or kernel single-step support (MIPS on GNU/Linux for example). We find
4077 the target of the coming instruction and breakpoint it. */
4080 mips_software_single_step (struct frame_info
*frame
)
4082 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4083 struct address_space
*aspace
= get_frame_address_space (frame
);
4084 CORE_ADDR pc
, next_pc
;
4086 pc
= get_frame_pc (frame
);
4087 if (deal_with_atomic_sequence (gdbarch
, aspace
, pc
))
4090 next_pc
= mips_next_pc (frame
, pc
);
4092 insert_single_step_breakpoint (gdbarch
, aspace
, next_pc
);
4096 /* Test whether the PC points to the return instruction at the
4097 end of a function. */
4100 mips_about_to_return (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4105 /* This used to check for MIPS16, but this piece of code is never
4106 called for MIPS16 functions. And likewise microMIPS ones. */
4107 gdb_assert (mips_pc_is_mips (pc
));
4109 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
4111 return (insn
& ~hint
) == 0x3e00008; /* jr(.hb) $ra */
4115 /* This fencepost looks highly suspicious to me. Removing it also
4116 seems suspicious as it could affect remote debugging across serial
4120 heuristic_proc_start (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4126 struct inferior
*inf
;
4128 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
4130 fence
= start_pc
- heuristic_fence_post
;
4134 if (heuristic_fence_post
== -1 || fence
< VM_MIN_ADDRESS
)
4135 fence
= VM_MIN_ADDRESS
;
4137 instlen
= mips_pc_is_mips (pc
) ? MIPS_INSN32_SIZE
: MIPS_INSN16_SIZE
;
4139 inf
= current_inferior ();
4141 /* Search back for previous return. */
4142 for (start_pc
-= instlen
;; start_pc
-= instlen
)
4143 if (start_pc
< fence
)
4145 /* It's not clear to me why we reach this point when
4146 stop_soon, but with this test, at least we
4147 don't print out warnings for every child forked (eg, on
4148 decstation). 22apr93 rich@cygnus.com. */
4149 if (inf
->control
.stop_soon
== NO_STOP_QUIETLY
)
4151 static int blurb_printed
= 0;
4153 warning (_("GDB can't find the start of the function at %s."),
4154 paddress (gdbarch
, pc
));
4158 /* This actually happens frequently in embedded
4159 development, when you first connect to a board
4160 and your stack pointer and pc are nowhere in
4161 particular. This message needs to give people
4162 in that situation enough information to
4163 determine that it's no big deal. */
4164 printf_filtered ("\n\
4165 GDB is unable to find the start of the function at %s\n\
4166 and thus can't determine the size of that function's stack frame.\n\
4167 This means that GDB may be unable to access that stack frame, or\n\
4168 the frames below it.\n\
4169 This problem is most likely caused by an invalid program counter or\n\
4171 However, if you think GDB should simply search farther back\n\
4172 from %s for code which looks like the beginning of a\n\
4173 function, you can increase the range of the search using the `set\n\
4174 heuristic-fence-post' command.\n",
4175 paddress (gdbarch
, pc
), paddress (gdbarch
, pc
));
4182 else if (mips_pc_is_mips16 (gdbarch
, start_pc
))
4184 unsigned short inst
;
4186 /* On MIPS16, any one of the following is likely to be the
4187 start of a function:
4193 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */
4194 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, start_pc
, NULL
);
4195 if ((inst
& 0xff80) == 0x6480) /* save */
4197 if (start_pc
- instlen
>= fence
)
4199 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
,
4200 start_pc
- instlen
, NULL
);
4201 if ((inst
& 0xf800) == 0xf000) /* extend */
4202 start_pc
-= instlen
;
4206 else if (((inst
& 0xf81f) == 0xe809
4207 && (inst
& 0x700) != 0x700) /* entry */
4208 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
4209 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
4210 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
4212 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
4213 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
4218 else if (mips_pc_is_micromips (gdbarch
, start_pc
))
4226 /* On microMIPS, any one of the following is likely to be the
4227 start of a function:
4231 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
4232 switch (micromips_op (insn
))
4234 case 0xc: /* ADDIU: bits 001100 */
4235 case 0x17: /* DADDIU: bits 010111 */
4236 sreg
= b0s5_reg (insn
);
4237 dreg
= b5s5_reg (insn
);
4239 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
,
4240 pc
+ MIPS_INSN16_SIZE
, NULL
);
4241 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
4242 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
4243 /* (D)ADDIU $sp, imm */
4248 case 0x10: /* POOL32I: bits 010000 */
4249 if (b5s5_op (insn
) == 0xd
4250 /* LUI: bits 010000 001101 */
4251 && b0s5_reg (insn
>> 16) == 28)
4256 case 0x13: /* POOL16D: bits 010011 */
4257 if ((insn
& 0x1) == 0x1)
4258 /* ADDIUSP: bits 010011 1 */
4260 offset
= micromips_decode_imm9 (b1s9_imm (insn
));
4266 /* ADDIUS5: bits 010011 0 */
4268 dreg
= b5s5_reg (insn
);
4269 offset
= (b1s4_imm (insn
) ^ 8) - 8;
4270 if (dreg
== MIPS_SP_REGNUM
&& offset
< 0)
4271 /* ADDIUS5 $sp, -imm */
4279 else if (mips_about_to_return (gdbarch
, start_pc
))
4281 /* Skip return and its delay slot. */
4282 start_pc
+= 2 * MIPS_INSN32_SIZE
;
4289 struct mips_objfile_private
4295 /* According to the current ABI, should the type be passed in a
4296 floating-point register (assuming that there is space)? When there
4297 is no FPU, FP are not even considered as possible candidates for
4298 FP registers and, consequently this returns false - forces FP
4299 arguments into integer registers. */
4302 fp_register_arg_p (struct gdbarch
*gdbarch
, enum type_code typecode
,
4303 struct type
*arg_type
)
4305 return ((typecode
== TYPE_CODE_FLT
4306 || (MIPS_EABI (gdbarch
)
4307 && (typecode
== TYPE_CODE_STRUCT
4308 || typecode
== TYPE_CODE_UNION
)
4309 && TYPE_NFIELDS (arg_type
) == 1
4310 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type
, 0)))
4312 && MIPS_FPU_TYPE(gdbarch
) != MIPS_FPU_NONE
);
4315 /* On o32, argument passing in GPRs depends on the alignment of the type being
4316 passed. Return 1 if this type must be aligned to a doubleword boundary. */
4319 mips_type_needs_double_align (struct type
*type
)
4321 enum type_code typecode
= TYPE_CODE (type
);
4323 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
4325 else if (typecode
== TYPE_CODE_STRUCT
)
4327 if (TYPE_NFIELDS (type
) < 1)
4329 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
4331 else if (typecode
== TYPE_CODE_UNION
)
4335 n
= TYPE_NFIELDS (type
);
4336 for (i
= 0; i
< n
; i
++)
4337 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
4344 /* Adjust the address downward (direction of stack growth) so that it
4345 is correctly aligned for a new stack frame. */
4347 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
4349 return align_down (addr
, 16);
4352 /* Implement the "push_dummy_code" gdbarch method. */
4355 mips_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
4356 CORE_ADDR funaddr
, struct value
**args
,
4357 int nargs
, struct type
*value_type
,
4358 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
4359 struct regcache
*regcache
)
4361 static gdb_byte nop_insn
[] = { 0, 0, 0, 0 };
4365 /* Reserve enough room on the stack for our breakpoint instruction. */
4366 bp_slot
= sp
- sizeof (nop_insn
);
4368 /* Return to microMIPS mode if calling microMIPS code to avoid
4369 triggering an address error exception on processors that only
4370 support microMIPS execution. */
4371 *bp_addr
= (mips_pc_is_micromips (gdbarch
, funaddr
)
4372 ? make_compact_addr (bp_slot
) : bp_slot
);
4374 /* The breakpoint layer automatically adjusts the address of
4375 breakpoints inserted in a branch delay slot. With enough
4376 bad luck, the 4 bytes located just before our breakpoint
4377 instruction could look like a branch instruction, and thus
4378 trigger the adjustement, and break the function call entirely.
4379 So, we reserve those 4 bytes and write a nop instruction
4380 to prevent that from happening. */
4381 nop_addr
= bp_slot
- sizeof (nop_insn
);
4382 write_memory (nop_addr
, nop_insn
, sizeof (nop_insn
));
4383 sp
= mips_frame_align (gdbarch
, nop_addr
);
4385 /* Inferior resumes at the function entry point. */
4392 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4393 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4394 int nargs
, struct value
**args
, CORE_ADDR sp
,
4395 int struct_return
, CORE_ADDR struct_addr
)
4401 int stack_offset
= 0;
4402 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4403 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4404 int regsize
= mips_abi_regsize (gdbarch
);
4406 /* For shared libraries, "t9" needs to point at the function
4408 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4410 /* Set the return address register to point to the entry point of
4411 the program, where a breakpoint lies in wait. */
4412 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4414 /* First ensure that the stack and structure return address (if any)
4415 are properly aligned. The stack has to be at least 64-bit
4416 aligned even on 32-bit machines, because doubles must be 64-bit
4417 aligned. For n32 and n64, stack frames need to be 128-bit
4418 aligned, so we round to this widest known alignment. */
4420 sp
= align_down (sp
, 16);
4421 struct_addr
= align_down (struct_addr
, 16);
4423 /* Now make space on the stack for the args. We allocate more
4424 than necessary for EABI, because the first few arguments are
4425 passed in registers, but that's OK. */
4426 for (argnum
= 0; argnum
< nargs
; argnum
++)
4427 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), regsize
);
4428 sp
-= align_up (len
, 16);
4431 fprintf_unfiltered (gdb_stdlog
,
4432 "mips_eabi_push_dummy_call: sp=%s allocated %ld\n",
4433 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
4435 /* Initialize the integer and float register pointers. */
4436 argreg
= MIPS_A0_REGNUM
;
4437 float_argreg
= mips_fpa0_regnum (gdbarch
);
4439 /* The struct_return pointer occupies the first parameter-passing reg. */
4443 fprintf_unfiltered (gdb_stdlog
,
4444 "mips_eabi_push_dummy_call: "
4445 "struct_return reg=%d %s\n",
4446 argreg
, paddress (gdbarch
, struct_addr
));
4447 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4450 /* Now load as many as possible of the first arguments into
4451 registers, and push the rest onto the stack. Loop thru args
4452 from first to last. */
4453 for (argnum
= 0; argnum
< nargs
; argnum
++)
4455 const gdb_byte
*val
;
4456 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
4457 struct value
*arg
= args
[argnum
];
4458 struct type
*arg_type
= check_typedef (value_type (arg
));
4459 int len
= TYPE_LENGTH (arg_type
);
4460 enum type_code typecode
= TYPE_CODE (arg_type
);
4463 fprintf_unfiltered (gdb_stdlog
,
4464 "mips_eabi_push_dummy_call: %d len=%d type=%d",
4465 argnum
+ 1, len
, (int) typecode
);
4467 /* Function pointer arguments to mips16 code need to be made into
4469 if (typecode
== TYPE_CODE_PTR
4470 && TYPE_CODE (TYPE_TARGET_TYPE (arg_type
)) == TYPE_CODE_FUNC
)
4472 CORE_ADDR addr
= extract_signed_integer (value_contents (arg
),
4474 if (mips_pc_is_mips (addr
))
4475 val
= value_contents (arg
);
4478 store_signed_integer (valbuf
, len
, byte_order
,
4479 make_compact_addr (addr
));
4483 /* The EABI passes structures that do not fit in a register by
4485 else if (len
> regsize
4486 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
4488 store_unsigned_integer (valbuf
, regsize
, byte_order
,
4489 value_address (arg
));
4490 typecode
= TYPE_CODE_PTR
;
4494 fprintf_unfiltered (gdb_stdlog
, " push");
4497 val
= value_contents (arg
);
4499 /* 32-bit ABIs always start floating point arguments in an
4500 even-numbered floating point register. Round the FP register
4501 up before the check to see if there are any FP registers
4502 left. Non MIPS_EABI targets also pass the FP in the integer
4503 registers so also round up normal registers. */
4504 if (regsize
< 8 && fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4506 if ((float_argreg
& 1))
4510 /* Floating point arguments passed in registers have to be
4511 treated specially. On 32-bit architectures, doubles
4512 are passed in register pairs; the even register gets
4513 the low word, and the odd register gets the high word.
4514 On non-EABI processors, the first two floating point arguments are
4515 also copied to general registers, because MIPS16 functions
4516 don't use float registers for arguments. This duplication of
4517 arguments in general registers can't hurt non-MIPS16 functions
4518 because those registers are normally skipped. */
4519 /* MIPS_EABI squeezes a struct that contains a single floating
4520 point value into an FP register instead of pushing it onto the
4522 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4523 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
4525 /* EABI32 will pass doubles in consecutive registers, even on
4526 64-bit cores. At one time, we used to check the size of
4527 `float_argreg' to determine whether or not to pass doubles
4528 in consecutive registers, but this is not sufficient for
4529 making the ABI determination. */
4530 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
4532 int low_offset
= gdbarch_byte_order (gdbarch
)
4533 == BFD_ENDIAN_BIG
? 4 : 0;
4536 /* Write the low word of the double to the even register(s). */
4537 regval
= extract_signed_integer (val
+ low_offset
,
4540 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4541 float_argreg
, phex (regval
, 4));
4542 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4544 /* Write the high word of the double to the odd register(s). */
4545 regval
= extract_signed_integer (val
+ 4 - low_offset
,
4548 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4549 float_argreg
, phex (regval
, 4));
4550 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4554 /* This is a floating point value that fits entirely
4555 in a single register. */
4556 /* On 32 bit ABI's the float_argreg is further adjusted
4557 above to ensure that it is even register aligned. */
4558 LONGEST regval
= extract_signed_integer (val
, len
, byte_order
);
4560 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4561 float_argreg
, phex (regval
, len
));
4562 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4567 /* Copy the argument to general registers or the stack in
4568 register-sized pieces. Large arguments are split between
4569 registers and stack. */
4570 /* Note: structs whose size is not a multiple of regsize
4571 are treated specially: Irix cc passes
4572 them in registers where gcc sometimes puts them on the
4573 stack. For maximum compatibility, we will put them in
4575 int odd_sized_struct
= (len
> regsize
&& len
% regsize
!= 0);
4577 /* Note: Floating-point values that didn't fit into an FP
4578 register are only written to memory. */
4581 /* Remember if the argument was written to the stack. */
4582 int stack_used_p
= 0;
4583 int partial_len
= (len
< regsize
? len
: regsize
);
4586 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4589 /* Write this portion of the argument to the stack. */
4590 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
4592 || fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4594 /* Should shorter than int integer values be
4595 promoted to int before being stored? */
4596 int longword_offset
= 0;
4599 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4602 && (typecode
== TYPE_CODE_INT
4603 || typecode
== TYPE_CODE_PTR
4604 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
4605 longword_offset
= regsize
- len
;
4606 else if ((typecode
== TYPE_CODE_STRUCT
4607 || typecode
== TYPE_CODE_UNION
)
4608 && TYPE_LENGTH (arg_type
) < regsize
)
4609 longword_offset
= regsize
- len
;
4614 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
4615 paddress (gdbarch
, stack_offset
));
4616 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
4617 paddress (gdbarch
, longword_offset
));
4620 addr
= sp
+ stack_offset
+ longword_offset
;
4625 fprintf_unfiltered (gdb_stdlog
, " @%s ",
4626 paddress (gdbarch
, addr
));
4627 for (i
= 0; i
< partial_len
; i
++)
4629 fprintf_unfiltered (gdb_stdlog
, "%02x",
4633 write_memory (addr
, val
, partial_len
);
4636 /* Note!!! This is NOT an else clause. Odd sized
4637 structs may go thru BOTH paths. Floating point
4638 arguments will not. */
4639 /* Write this portion of the argument to a general
4640 purpose register. */
4641 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
)
4642 && !fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4645 extract_signed_integer (val
, partial_len
, byte_order
);
4648 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4650 phex (regval
, regsize
));
4651 regcache_cooked_write_signed (regcache
, argreg
, regval
);
4658 /* Compute the offset into the stack at which we will
4659 copy the next parameter.
4661 In the new EABI (and the NABI32), the stack_offset
4662 only needs to be adjusted when it has been used. */
4665 stack_offset
+= align_up (partial_len
, regsize
);
4669 fprintf_unfiltered (gdb_stdlog
, "\n");
4672 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4674 /* Return adjusted stack pointer. */
4678 /* Determine the return value convention being used. */
4680 static enum return_value_convention
4681 mips_eabi_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
4682 struct type
*type
, struct regcache
*regcache
,
4683 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4685 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4686 int fp_return_type
= 0;
4687 int offset
, regnum
, xfer
;
4689 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
4690 return RETURN_VALUE_STRUCT_CONVENTION
;
4692 /* Floating point type? */
4693 if (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4695 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
4697 /* Structs with a single field of float type
4698 are returned in a floating point register. */
4699 if ((TYPE_CODE (type
) == TYPE_CODE_STRUCT
4700 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4701 && TYPE_NFIELDS (type
) == 1)
4703 struct type
*fieldtype
= TYPE_FIELD_TYPE (type
, 0);
4705 if (TYPE_CODE (check_typedef (fieldtype
)) == TYPE_CODE_FLT
)
4712 /* A floating-point value belongs in the least significant part
4715 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4716 regnum
= mips_regnum (gdbarch
)->fp0
;
4720 /* An integer value goes in V0/V1. */
4722 fprintf_unfiltered (gdb_stderr
, "Return scalar in $v0\n");
4723 regnum
= MIPS_V0_REGNUM
;
4726 offset
< TYPE_LENGTH (type
);
4727 offset
+= mips_abi_regsize (gdbarch
), regnum
++)
4729 xfer
= mips_abi_regsize (gdbarch
);
4730 if (offset
+ xfer
> TYPE_LENGTH (type
))
4731 xfer
= TYPE_LENGTH (type
) - offset
;
4732 mips_xfer_register (gdbarch
, regcache
,
4733 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
4734 gdbarch_byte_order (gdbarch
), readbuf
, writebuf
,
4738 return RETURN_VALUE_REGISTER_CONVENTION
;
4742 /* N32/N64 ABI stuff. */
4744 /* Search for a naturally aligned double at OFFSET inside a struct
4745 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
4749 mips_n32n64_fp_arg_chunk_p (struct gdbarch
*gdbarch
, struct type
*arg_type
,
4754 if (TYPE_CODE (arg_type
) != TYPE_CODE_STRUCT
)
4757 if (MIPS_FPU_TYPE (gdbarch
) != MIPS_FPU_DOUBLE
)
4760 if (TYPE_LENGTH (arg_type
) < offset
+ MIPS64_REGSIZE
)
4763 for (i
= 0; i
< TYPE_NFIELDS (arg_type
); i
++)
4766 struct type
*field_type
;
4768 /* We're only looking at normal fields. */
4769 if (field_is_static (&TYPE_FIELD (arg_type
, i
))
4770 || (TYPE_FIELD_BITPOS (arg_type
, i
) % 8) != 0)
4773 /* If we have gone past the offset, there is no double to pass. */
4774 pos
= TYPE_FIELD_BITPOS (arg_type
, i
) / 8;
4778 field_type
= check_typedef (TYPE_FIELD_TYPE (arg_type
, i
));
4780 /* If this field is entirely before the requested offset, go
4781 on to the next one. */
4782 if (pos
+ TYPE_LENGTH (field_type
) <= offset
)
4785 /* If this is our special aligned double, we can stop. */
4786 if (TYPE_CODE (field_type
) == TYPE_CODE_FLT
4787 && TYPE_LENGTH (field_type
) == MIPS64_REGSIZE
)
4790 /* This field starts at or before the requested offset, and
4791 overlaps it. If it is a structure, recurse inwards. */
4792 return mips_n32n64_fp_arg_chunk_p (gdbarch
, field_type
, offset
- pos
);
4799 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4800 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4801 int nargs
, struct value
**args
, CORE_ADDR sp
,
4802 int struct_return
, CORE_ADDR struct_addr
)
4808 int stack_offset
= 0;
4809 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4810 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4812 /* For shared libraries, "t9" needs to point at the function
4814 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4816 /* Set the return address register to point to the entry point of
4817 the program, where a breakpoint lies in wait. */
4818 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4820 /* First ensure that the stack and structure return address (if any)
4821 are properly aligned. The stack has to be at least 64-bit
4822 aligned even on 32-bit machines, because doubles must be 64-bit
4823 aligned. For n32 and n64, stack frames need to be 128-bit
4824 aligned, so we round to this widest known alignment. */
4826 sp
= align_down (sp
, 16);
4827 struct_addr
= align_down (struct_addr
, 16);
4829 /* Now make space on the stack for the args. */
4830 for (argnum
= 0; argnum
< nargs
; argnum
++)
4831 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), MIPS64_REGSIZE
);
4832 sp
-= align_up (len
, 16);
4835 fprintf_unfiltered (gdb_stdlog
,
4836 "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n",
4837 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
4839 /* Initialize the integer and float register pointers. */
4840 argreg
= MIPS_A0_REGNUM
;
4841 float_argreg
= mips_fpa0_regnum (gdbarch
);
4843 /* The struct_return pointer occupies the first parameter-passing reg. */
4847 fprintf_unfiltered (gdb_stdlog
,
4848 "mips_n32n64_push_dummy_call: "
4849 "struct_return reg=%d %s\n",
4850 argreg
, paddress (gdbarch
, struct_addr
));
4851 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4854 /* Now load as many as possible of the first arguments into
4855 registers, and push the rest onto the stack. Loop thru args
4856 from first to last. */
4857 for (argnum
= 0; argnum
< nargs
; argnum
++)
4859 const gdb_byte
*val
;
4860 struct value
*arg
= args
[argnum
];
4861 struct type
*arg_type
= check_typedef (value_type (arg
));
4862 int len
= TYPE_LENGTH (arg_type
);
4863 enum type_code typecode
= TYPE_CODE (arg_type
);
4866 fprintf_unfiltered (gdb_stdlog
,
4867 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
4868 argnum
+ 1, len
, (int) typecode
);
4870 val
= value_contents (arg
);
4872 /* A 128-bit long double value requires an even-odd pair of
4873 floating-point registers. */
4875 && fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4876 && (float_argreg
& 1))
4882 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4883 && argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
4885 /* This is a floating point value that fits entirely
4886 in a single register or a pair of registers. */
4887 int reglen
= (len
<= MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
4888 LONGEST regval
= extract_unsigned_integer (val
, reglen
, byte_order
);
4890 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4891 float_argreg
, phex (regval
, reglen
));
4892 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
4895 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4896 argreg
, phex (regval
, reglen
));
4897 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4902 regval
= extract_unsigned_integer (val
+ reglen
,
4903 reglen
, byte_order
);
4905 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4906 float_argreg
, phex (regval
, reglen
));
4907 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
4910 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4911 argreg
, phex (regval
, reglen
));
4912 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4919 /* Copy the argument to general registers or the stack in
4920 register-sized pieces. Large arguments are split between
4921 registers and stack. */
4922 /* For N32/N64, structs, unions, or other composite types are
4923 treated as a sequence of doublewords, and are passed in integer
4924 or floating point registers as though they were simple scalar
4925 parameters to the extent that they fit, with any excess on the
4926 stack packed according to the normal memory layout of the
4928 The caller does not reserve space for the register arguments;
4929 the callee is responsible for reserving it if required. */
4930 /* Note: Floating-point values that didn't fit into an FP
4931 register are only written to memory. */
4934 /* Remember if the argument was written to the stack. */
4935 int stack_used_p
= 0;
4936 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
4939 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4942 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4943 gdb_assert (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
));
4945 /* Write this portion of the argument to the stack. */
4946 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
))
4948 /* Should shorter than int integer values be
4949 promoted to int before being stored? */
4950 int longword_offset
= 0;
4953 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4955 if ((typecode
== TYPE_CODE_INT
4956 || typecode
== TYPE_CODE_PTR
)
4958 longword_offset
= MIPS64_REGSIZE
- len
;
4963 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
4964 paddress (gdbarch
, stack_offset
));
4965 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
4966 paddress (gdbarch
, longword_offset
));
4969 addr
= sp
+ stack_offset
+ longword_offset
;
4974 fprintf_unfiltered (gdb_stdlog
, " @%s ",
4975 paddress (gdbarch
, addr
));
4976 for (i
= 0; i
< partial_len
; i
++)
4978 fprintf_unfiltered (gdb_stdlog
, "%02x",
4982 write_memory (addr
, val
, partial_len
);
4985 /* Note!!! This is NOT an else clause. Odd sized
4986 structs may go thru BOTH paths. */
4987 /* Write this portion of the argument to a general
4988 purpose register. */
4989 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
4993 /* Sign extend pointers, 32-bit integers and signed
4994 16-bit and 8-bit integers; everything else is taken
4997 if ((partial_len
== 4
4998 && (typecode
== TYPE_CODE_PTR
4999 || typecode
== TYPE_CODE_INT
))
5001 && typecode
== TYPE_CODE_INT
5002 && !TYPE_UNSIGNED (arg_type
)))
5003 regval
= extract_signed_integer (val
, partial_len
,
5006 regval
= extract_unsigned_integer (val
, partial_len
,
5009 /* A non-floating-point argument being passed in a
5010 general register. If a struct or union, and if
5011 the remaining length is smaller than the register
5012 size, we have to adjust the register value on
5015 It does not seem to be necessary to do the
5016 same for integral types. */
5018 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
5019 && partial_len
< MIPS64_REGSIZE
5020 && (typecode
== TYPE_CODE_STRUCT
5021 || typecode
== TYPE_CODE_UNION
))
5022 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
5026 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
5028 phex (regval
, MIPS64_REGSIZE
));
5029 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5031 if (mips_n32n64_fp_arg_chunk_p (gdbarch
, arg_type
,
5032 TYPE_LENGTH (arg_type
) - len
))
5035 fprintf_filtered (gdb_stdlog
, " - fpreg=%d val=%s",
5037 phex (regval
, MIPS64_REGSIZE
));
5038 regcache_cooked_write_unsigned (regcache
, float_argreg
,
5049 /* Compute the offset into the stack at which we will
5050 copy the next parameter.
5052 In N32 (N64?), the stack_offset only needs to be
5053 adjusted when it has been used. */
5056 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
5060 fprintf_unfiltered (gdb_stdlog
, "\n");
5063 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
5065 /* Return adjusted stack pointer. */
5069 static enum return_value_convention
5070 mips_n32n64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
5071 struct type
*type
, struct regcache
*regcache
,
5072 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5074 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5076 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
5078 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
5079 if needed), as appropriate for the type. Composite results (struct,
5080 union, or array) are returned in $2/$f0 and $3/$f2 according to the
5083 * A struct with only one or two floating point fields is returned in $f0
5084 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
5087 * Any other composite results of at most 128 bits are returned in
5088 $2 (first 64 bits) and $3 (remainder, if necessary).
5090 * Larger composite results are handled by converting the function to a
5091 procedure with an implicit first parameter, which is a pointer to an area
5092 reserved by the caller to receive the result. [The o32-bit ABI requires
5093 that all composite results be handled by conversion to implicit first
5094 parameters. The MIPS/SGI Fortran implementation has always made a
5095 specific exception to return COMPLEX results in the floating point
5098 if (TYPE_LENGTH (type
) > 2 * MIPS64_REGSIZE
)
5099 return RETURN_VALUE_STRUCT_CONVENTION
;
5100 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
5101 && TYPE_LENGTH (type
) == 16
5102 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5104 /* A 128-bit floating-point value fills both $f0 and $f2. The
5105 two registers are used in the same as memory order, so the
5106 eight bytes with the lower memory address are in $f0. */
5108 fprintf_unfiltered (gdb_stderr
, "Return float in $f0 and $f2\n");
5109 mips_xfer_register (gdbarch
, regcache
,
5110 (gdbarch_num_regs (gdbarch
)
5111 + mips_regnum (gdbarch
)->fp0
),
5112 8, gdbarch_byte_order (gdbarch
),
5113 readbuf
, writebuf
, 0);
5114 mips_xfer_register (gdbarch
, regcache
,
5115 (gdbarch_num_regs (gdbarch
)
5116 + mips_regnum (gdbarch
)->fp0
+ 2),
5117 8, gdbarch_byte_order (gdbarch
),
5118 readbuf
? readbuf
+ 8 : readbuf
,
5119 writebuf
? writebuf
+ 8 : writebuf
, 0);
5120 return RETURN_VALUE_REGISTER_CONVENTION
;
5122 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
5123 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5125 /* A single or double floating-point value that fits in FP0. */
5127 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
5128 mips_xfer_register (gdbarch
, regcache
,
5129 (gdbarch_num_regs (gdbarch
)
5130 + mips_regnum (gdbarch
)->fp0
),
5132 gdbarch_byte_order (gdbarch
),
5133 readbuf
, writebuf
, 0);
5134 return RETURN_VALUE_REGISTER_CONVENTION
;
5136 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5137 && TYPE_NFIELDS (type
) <= 2
5138 && TYPE_NFIELDS (type
) >= 1
5139 && ((TYPE_NFIELDS (type
) == 1
5140 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
5142 || (TYPE_NFIELDS (type
) == 2
5143 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
5145 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 1)))
5146 == TYPE_CODE_FLT
))))
5148 /* A struct that contains one or two floats. Each value is part
5149 in the least significant part of their floating point
5150 register (or GPR, for soft float). */
5153 for (field
= 0, regnum
= (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
5154 ? mips_regnum (gdbarch
)->fp0
5156 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
5158 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
5161 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
5163 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)) == 16)
5165 /* A 16-byte long double field goes in two consecutive
5167 mips_xfer_register (gdbarch
, regcache
,
5168 gdbarch_num_regs (gdbarch
) + regnum
,
5170 gdbarch_byte_order (gdbarch
),
5171 readbuf
, writebuf
, offset
);
5172 mips_xfer_register (gdbarch
, regcache
,
5173 gdbarch_num_regs (gdbarch
) + regnum
+ 1,
5175 gdbarch_byte_order (gdbarch
),
5176 readbuf
, writebuf
, offset
+ 8);
5179 mips_xfer_register (gdbarch
, regcache
,
5180 gdbarch_num_regs (gdbarch
) + regnum
,
5181 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
5182 gdbarch_byte_order (gdbarch
),
5183 readbuf
, writebuf
, offset
);
5185 return RETURN_VALUE_REGISTER_CONVENTION
;
5187 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5188 || TYPE_CODE (type
) == TYPE_CODE_UNION
5189 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
5191 /* A composite type. Extract the left justified value,
5192 regardless of the byte order. I.e. DO NOT USE
5196 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5197 offset
< TYPE_LENGTH (type
);
5198 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5200 int xfer
= register_size (gdbarch
, regnum
);
5201 if (offset
+ xfer
> TYPE_LENGTH (type
))
5202 xfer
= TYPE_LENGTH (type
) - offset
;
5204 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5205 offset
, xfer
, regnum
);
5206 mips_xfer_register (gdbarch
, regcache
,
5207 gdbarch_num_regs (gdbarch
) + regnum
,
5208 xfer
, BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
,
5211 return RETURN_VALUE_REGISTER_CONVENTION
;
5215 /* A scalar extract each part but least-significant-byte
5219 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5220 offset
< TYPE_LENGTH (type
);
5221 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5223 int xfer
= register_size (gdbarch
, regnum
);
5224 if (offset
+ xfer
> TYPE_LENGTH (type
))
5225 xfer
= TYPE_LENGTH (type
) - offset
;
5227 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5228 offset
, xfer
, regnum
);
5229 mips_xfer_register (gdbarch
, regcache
,
5230 gdbarch_num_regs (gdbarch
) + regnum
,
5231 xfer
, gdbarch_byte_order (gdbarch
),
5232 readbuf
, writebuf
, offset
);
5234 return RETURN_VALUE_REGISTER_CONVENTION
;
5238 /* Which registers to use for passing floating-point values between
5239 function calls, one of floating-point, general and both kinds of
5240 registers. O32 and O64 use different register kinds for standard
5241 MIPS and MIPS16 code; to make the handling of cases where we may
5242 not know what kind of code is being used (e.g. no debug information)
5243 easier we sometimes use both kinds. */
5252 /* O32 ABI stuff. */
5255 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
5256 struct regcache
*regcache
, CORE_ADDR bp_addr
,
5257 int nargs
, struct value
**args
, CORE_ADDR sp
,
5258 int struct_return
, CORE_ADDR struct_addr
)
5264 int stack_offset
= 0;
5265 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5266 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
5268 /* For shared libraries, "t9" needs to point at the function
5270 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
5272 /* Set the return address register to point to the entry point of
5273 the program, where a breakpoint lies in wait. */
5274 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
5276 /* First ensure that the stack and structure return address (if any)
5277 are properly aligned. The stack has to be at least 64-bit
5278 aligned even on 32-bit machines, because doubles must be 64-bit
5279 aligned. For n32 and n64, stack frames need to be 128-bit
5280 aligned, so we round to this widest known alignment. */
5282 sp
= align_down (sp
, 16);
5283 struct_addr
= align_down (struct_addr
, 16);
5285 /* Now make space on the stack for the args. */
5286 for (argnum
= 0; argnum
< nargs
; argnum
++)
5288 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
5290 /* Align to double-word if necessary. */
5291 if (mips_type_needs_double_align (arg_type
))
5292 len
= align_up (len
, MIPS32_REGSIZE
* 2);
5293 /* Allocate space on the stack. */
5294 len
+= align_up (TYPE_LENGTH (arg_type
), MIPS32_REGSIZE
);
5296 sp
-= align_up (len
, 16);
5299 fprintf_unfiltered (gdb_stdlog
,
5300 "mips_o32_push_dummy_call: sp=%s allocated %ld\n",
5301 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
5303 /* Initialize the integer and float register pointers. */
5304 argreg
= MIPS_A0_REGNUM
;
5305 float_argreg
= mips_fpa0_regnum (gdbarch
);
5307 /* The struct_return pointer occupies the first parameter-passing reg. */
5311 fprintf_unfiltered (gdb_stdlog
,
5312 "mips_o32_push_dummy_call: "
5313 "struct_return reg=%d %s\n",
5314 argreg
, paddress (gdbarch
, struct_addr
));
5315 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
5316 stack_offset
+= MIPS32_REGSIZE
;
5319 /* Now load as many as possible of the first arguments into
5320 registers, and push the rest onto the stack. Loop thru args
5321 from first to last. */
5322 for (argnum
= 0; argnum
< nargs
; argnum
++)
5324 const gdb_byte
*val
;
5325 struct value
*arg
= args
[argnum
];
5326 struct type
*arg_type
= check_typedef (value_type (arg
));
5327 int len
= TYPE_LENGTH (arg_type
);
5328 enum type_code typecode
= TYPE_CODE (arg_type
);
5331 fprintf_unfiltered (gdb_stdlog
,
5332 "mips_o32_push_dummy_call: %d len=%d type=%d",
5333 argnum
+ 1, len
, (int) typecode
);
5335 val
= value_contents (arg
);
5337 /* 32-bit ABIs always start floating point arguments in an
5338 even-numbered floating point register. Round the FP register
5339 up before the check to see if there are any FP registers
5340 left. O32 targets also pass the FP in the integer registers
5341 so also round up normal registers. */
5342 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
5344 if ((float_argreg
& 1))
5348 /* Floating point arguments passed in registers have to be
5349 treated specially. On 32-bit architectures, doubles are
5350 passed in register pairs; the even FP register gets the
5351 low word, and the odd FP register gets the high word.
5352 On O32, the first two floating point arguments are also
5353 copied to general registers, following their memory order,
5354 because MIPS16 functions don't use float registers for
5355 arguments. This duplication of arguments in general
5356 registers can't hurt non-MIPS16 functions, because those
5357 registers are normally skipped. */
5359 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5360 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
5362 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
5364 int freg_offset
= gdbarch_byte_order (gdbarch
)
5365 == BFD_ENDIAN_BIG
? 1 : 0;
5366 unsigned long regval
;
5369 regval
= extract_unsigned_integer (val
, 4, byte_order
);
5371 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5372 float_argreg
+ freg_offset
,
5374 regcache_cooked_write_unsigned (regcache
,
5375 float_argreg
++ + freg_offset
,
5378 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5379 argreg
, phex (regval
, 4));
5380 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5383 regval
= extract_unsigned_integer (val
+ 4, 4, byte_order
);
5385 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5386 float_argreg
- freg_offset
,
5388 regcache_cooked_write_unsigned (regcache
,
5389 float_argreg
++ - freg_offset
,
5392 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5393 argreg
, phex (regval
, 4));
5394 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5398 /* This is a floating point value that fits entirely
5399 in a single register. */
5400 /* On 32 bit ABI's the float_argreg is further adjusted
5401 above to ensure that it is even register aligned. */
5402 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
5404 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5405 float_argreg
, phex (regval
, len
));
5406 regcache_cooked_write_unsigned (regcache
,
5407 float_argreg
++, regval
);
5408 /* Although two FP registers are reserved for each
5409 argument, only one corresponding integer register is
5412 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5413 argreg
, phex (regval
, len
));
5414 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5416 /* Reserve space for the FP register. */
5417 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
5421 /* Copy the argument to general registers or the stack in
5422 register-sized pieces. Large arguments are split between
5423 registers and stack. */
5424 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
5425 are treated specially: Irix cc passes
5426 them in registers where gcc sometimes puts them on the
5427 stack. For maximum compatibility, we will put them in
5429 int odd_sized_struct
= (len
> MIPS32_REGSIZE
5430 && len
% MIPS32_REGSIZE
!= 0);
5431 /* Structures should be aligned to eight bytes (even arg registers)
5432 on MIPS_ABI_O32, if their first member has double precision. */
5433 if (mips_type_needs_double_align (arg_type
))
5438 stack_offset
+= MIPS32_REGSIZE
;
5443 /* Remember if the argument was written to the stack. */
5444 int stack_used_p
= 0;
5445 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
5448 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
5451 /* Write this portion of the argument to the stack. */
5452 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
5453 || odd_sized_struct
)
5455 /* Should shorter than int integer values be
5456 promoted to int before being stored? */
5457 int longword_offset
= 0;
5463 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
5464 paddress (gdbarch
, stack_offset
));
5465 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
5466 paddress (gdbarch
, longword_offset
));
5469 addr
= sp
+ stack_offset
+ longword_offset
;
5474 fprintf_unfiltered (gdb_stdlog
, " @%s ",
5475 paddress (gdbarch
, addr
));
5476 for (i
= 0; i
< partial_len
; i
++)
5478 fprintf_unfiltered (gdb_stdlog
, "%02x",
5482 write_memory (addr
, val
, partial_len
);
5485 /* Note!!! This is NOT an else clause. Odd sized
5486 structs may go thru BOTH paths. */
5487 /* Write this portion of the argument to a general
5488 purpose register. */
5489 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
5491 LONGEST regval
= extract_signed_integer (val
, partial_len
,
5493 /* Value may need to be sign extended, because
5494 mips_isa_regsize() != mips_abi_regsize(). */
5496 /* A non-floating-point argument being passed in a
5497 general register. If a struct or union, and if
5498 the remaining length is smaller than the register
5499 size, we have to adjust the register value on
5502 It does not seem to be necessary to do the
5503 same for integral types.
5505 Also don't do this adjustment on O64 binaries.
5507 cagney/2001-07-23: gdb/179: Also, GCC, when
5508 outputting LE O32 with sizeof (struct) <
5509 mips_abi_regsize(), generates a left shift
5510 as part of storing the argument in a register
5511 (the left shift isn't generated when
5512 sizeof (struct) >= mips_abi_regsize()). Since
5513 it is quite possible that this is GCC
5514 contradicting the LE/O32 ABI, GDB has not been
5515 adjusted to accommodate this. Either someone
5516 needs to demonstrate that the LE/O32 ABI
5517 specifies such a left shift OR this new ABI gets
5518 identified as such and GDB gets tweaked
5521 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
5522 && partial_len
< MIPS32_REGSIZE
5523 && (typecode
== TYPE_CODE_STRUCT
5524 || typecode
== TYPE_CODE_UNION
))
5525 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
5529 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
5531 phex (regval
, MIPS32_REGSIZE
));
5532 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5535 /* Prevent subsequent floating point arguments from
5536 being passed in floating point registers. */
5537 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
5543 /* Compute the offset into the stack at which we will
5544 copy the next parameter.
5546 In older ABIs, the caller reserved space for
5547 registers that contained arguments. This was loosely
5548 refered to as their "home". Consequently, space is
5549 always allocated. */
5551 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
5555 fprintf_unfiltered (gdb_stdlog
, "\n");
5558 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
5560 /* Return adjusted stack pointer. */
5564 static enum return_value_convention
5565 mips_o32_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
5566 struct type
*type
, struct regcache
*regcache
,
5567 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5569 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
5570 int mips16
= mips_pc_is_mips16 (gdbarch
, func_addr
);
5571 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5572 enum mips_fval_reg fval_reg
;
5574 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
5575 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5576 || TYPE_CODE (type
) == TYPE_CODE_UNION
5577 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
5578 return RETURN_VALUE_STRUCT_CONVENTION
;
5579 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
5580 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5582 /* A single-precision floating-point value. If reading in or copying,
5583 then we get it from/put it to FP0 for standard MIPS code or GPR2
5584 for MIPS16 code. If writing out only, then we put it to both FP0
5585 and GPR2. We do not support reading in with no function known, if
5586 this safety check ever triggers, then we'll have to try harder. */
5587 gdb_assert (function
|| !readbuf
);
5592 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
5595 fprintf_unfiltered (gdb_stderr
, "Return float in $2\n");
5597 case mips_fval_both
:
5598 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0 and $2\n");
5601 if (fval_reg
!= mips_fval_gpr
)
5602 mips_xfer_register (gdbarch
, regcache
,
5603 (gdbarch_num_regs (gdbarch
)
5604 + mips_regnum (gdbarch
)->fp0
),
5606 gdbarch_byte_order (gdbarch
),
5607 readbuf
, writebuf
, 0);
5608 if (fval_reg
!= mips_fval_fpr
)
5609 mips_xfer_register (gdbarch
, regcache
,
5610 gdbarch_num_regs (gdbarch
) + 2,
5612 gdbarch_byte_order (gdbarch
),
5613 readbuf
, writebuf
, 0);
5614 return RETURN_VALUE_REGISTER_CONVENTION
;
5616 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
5617 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5619 /* A double-precision floating-point value. If reading in or copying,
5620 then we get it from/put it to FP1 and FP0 for standard MIPS code or
5621 GPR2 and GPR3 for MIPS16 code. If writing out only, then we put it
5622 to both FP1/FP0 and GPR2/GPR3. We do not support reading in with
5623 no function known, if this safety check ever triggers, then we'll
5624 have to try harder. */
5625 gdb_assert (function
|| !readbuf
);
5630 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
5633 fprintf_unfiltered (gdb_stderr
, "Return float in $2/$3\n");
5635 case mips_fval_both
:
5636 fprintf_unfiltered (gdb_stderr
,
5637 "Return float in $fp1/$fp0 and $2/$3\n");
5640 if (fval_reg
!= mips_fval_gpr
)
5642 /* The most significant part goes in FP1, and the least significant
5644 switch (gdbarch_byte_order (gdbarch
))
5646 case BFD_ENDIAN_LITTLE
:
5647 mips_xfer_register (gdbarch
, regcache
,
5648 (gdbarch_num_regs (gdbarch
)
5649 + mips_regnum (gdbarch
)->fp0
+ 0),
5650 4, gdbarch_byte_order (gdbarch
),
5651 readbuf
, writebuf
, 0);
5652 mips_xfer_register (gdbarch
, regcache
,
5653 (gdbarch_num_regs (gdbarch
)
5654 + mips_regnum (gdbarch
)->fp0
+ 1),
5655 4, gdbarch_byte_order (gdbarch
),
5656 readbuf
, writebuf
, 4);
5658 case BFD_ENDIAN_BIG
:
5659 mips_xfer_register (gdbarch
, regcache
,
5660 (gdbarch_num_regs (gdbarch
)
5661 + mips_regnum (gdbarch
)->fp0
+ 1),
5662 4, gdbarch_byte_order (gdbarch
),
5663 readbuf
, writebuf
, 0);
5664 mips_xfer_register (gdbarch
, regcache
,
5665 (gdbarch_num_regs (gdbarch
)
5666 + mips_regnum (gdbarch
)->fp0
+ 0),
5667 4, gdbarch_byte_order (gdbarch
),
5668 readbuf
, writebuf
, 4);
5671 internal_error (__FILE__
, __LINE__
, _("bad switch"));
5674 if (fval_reg
!= mips_fval_fpr
)
5676 /* The two 32-bit parts are always placed in GPR2 and GPR3
5677 following these registers' memory order. */
5678 mips_xfer_register (gdbarch
, regcache
,
5679 gdbarch_num_regs (gdbarch
) + 2,
5680 4, gdbarch_byte_order (gdbarch
),
5681 readbuf
, writebuf
, 0);
5682 mips_xfer_register (gdbarch
, regcache
,
5683 gdbarch_num_regs (gdbarch
) + 3,
5684 4, gdbarch_byte_order (gdbarch
),
5685 readbuf
, writebuf
, 4);
5687 return RETURN_VALUE_REGISTER_CONVENTION
;
5690 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5691 && TYPE_NFIELDS (type
) <= 2
5692 && TYPE_NFIELDS (type
) >= 1
5693 && ((TYPE_NFIELDS (type
) == 1
5694 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
5696 || (TYPE_NFIELDS (type
) == 2
5697 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
5699 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
5701 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5703 /* A struct that contains one or two floats. Each value is part
5704 in the least significant part of their floating point
5706 gdb_byte reg
[MAX_REGISTER_SIZE
];
5709 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
5710 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
5712 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
5715 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
5717 mips_xfer_register (gdbarch
, regcache
,
5718 gdbarch_num_regs (gdbarch
) + regnum
,
5719 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
5720 gdbarch_byte_order (gdbarch
),
5721 readbuf
, writebuf
, offset
);
5723 return RETURN_VALUE_REGISTER_CONVENTION
;
5727 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5728 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
5730 /* A structure or union. Extract the left justified value,
5731 regardless of the byte order. I.e. DO NOT USE
5735 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5736 offset
< TYPE_LENGTH (type
);
5737 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5739 int xfer
= register_size (gdbarch
, regnum
);
5740 if (offset
+ xfer
> TYPE_LENGTH (type
))
5741 xfer
= TYPE_LENGTH (type
) - offset
;
5743 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5744 offset
, xfer
, regnum
);
5745 mips_xfer_register (gdbarch
, regcache
,
5746 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
5747 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
5749 return RETURN_VALUE_REGISTER_CONVENTION
;
5754 /* A scalar extract each part but least-significant-byte
5755 justified. o32 thinks registers are 4 byte, regardless of
5759 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5760 offset
< TYPE_LENGTH (type
);
5761 offset
+= MIPS32_REGSIZE
, regnum
++)
5763 int xfer
= MIPS32_REGSIZE
;
5764 if (offset
+ xfer
> TYPE_LENGTH (type
))
5765 xfer
= TYPE_LENGTH (type
) - offset
;
5767 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5768 offset
, xfer
, regnum
);
5769 mips_xfer_register (gdbarch
, regcache
,
5770 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
5771 gdbarch_byte_order (gdbarch
),
5772 readbuf
, writebuf
, offset
);
5774 return RETURN_VALUE_REGISTER_CONVENTION
;
5778 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
5782 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
5783 struct regcache
*regcache
, CORE_ADDR bp_addr
,
5785 struct value
**args
, CORE_ADDR sp
,
5786 int struct_return
, CORE_ADDR struct_addr
)
5792 int stack_offset
= 0;
5793 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5794 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
5796 /* For shared libraries, "t9" needs to point at the function
5798 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
5800 /* Set the return address register to point to the entry point of
5801 the program, where a breakpoint lies in wait. */
5802 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
5804 /* First ensure that the stack and structure return address (if any)
5805 are properly aligned. The stack has to be at least 64-bit
5806 aligned even on 32-bit machines, because doubles must be 64-bit
5807 aligned. For n32 and n64, stack frames need to be 128-bit
5808 aligned, so we round to this widest known alignment. */
5810 sp
= align_down (sp
, 16);
5811 struct_addr
= align_down (struct_addr
, 16);
5813 /* Now make space on the stack for the args. */
5814 for (argnum
= 0; argnum
< nargs
; argnum
++)
5816 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
5818 /* Allocate space on the stack. */
5819 len
+= align_up (TYPE_LENGTH (arg_type
), MIPS64_REGSIZE
);
5821 sp
-= align_up (len
, 16);
5824 fprintf_unfiltered (gdb_stdlog
,
5825 "mips_o64_push_dummy_call: sp=%s allocated %ld\n",
5826 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
5828 /* Initialize the integer and float register pointers. */
5829 argreg
= MIPS_A0_REGNUM
;
5830 float_argreg
= mips_fpa0_regnum (gdbarch
);
5832 /* The struct_return pointer occupies the first parameter-passing reg. */
5836 fprintf_unfiltered (gdb_stdlog
,
5837 "mips_o64_push_dummy_call: "
5838 "struct_return reg=%d %s\n",
5839 argreg
, paddress (gdbarch
, struct_addr
));
5840 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
5841 stack_offset
+= MIPS64_REGSIZE
;
5844 /* Now load as many as possible of the first arguments into
5845 registers, and push the rest onto the stack. Loop thru args
5846 from first to last. */
5847 for (argnum
= 0; argnum
< nargs
; argnum
++)
5849 const gdb_byte
*val
;
5850 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
5851 struct value
*arg
= args
[argnum
];
5852 struct type
*arg_type
= check_typedef (value_type (arg
));
5853 int len
= TYPE_LENGTH (arg_type
);
5854 enum type_code typecode
= TYPE_CODE (arg_type
);
5857 fprintf_unfiltered (gdb_stdlog
,
5858 "mips_o64_push_dummy_call: %d len=%d type=%d",
5859 argnum
+ 1, len
, (int) typecode
);
5861 val
= value_contents (arg
);
5863 /* Function pointer arguments to mips16 code need to be made into
5865 if (typecode
== TYPE_CODE_PTR
5866 && TYPE_CODE (TYPE_TARGET_TYPE (arg_type
)) == TYPE_CODE_FUNC
)
5868 CORE_ADDR addr
= extract_signed_integer (value_contents (arg
),
5870 if (!mips_pc_is_mips (addr
))
5872 store_signed_integer (valbuf
, len
, byte_order
,
5873 make_compact_addr (addr
));
5878 /* Floating point arguments passed in registers have to be
5879 treated specially. On 32-bit architectures, doubles are
5880 passed in register pairs; the even FP register gets the
5881 low word, and the odd FP register gets the high word.
5882 On O64, the first two floating point arguments are also
5883 copied to general registers, because MIPS16 functions
5884 don't use float registers for arguments. This duplication
5885 of arguments in general registers can't hurt non-MIPS16
5886 functions because those registers are normally skipped. */
5888 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5889 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
5891 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
5893 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5894 float_argreg
, phex (regval
, len
));
5895 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
5897 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5898 argreg
, phex (regval
, len
));
5899 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5901 /* Reserve space for the FP register. */
5902 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
5906 /* Copy the argument to general registers or the stack in
5907 register-sized pieces. Large arguments are split between
5908 registers and stack. */
5909 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
5910 are treated specially: Irix cc passes them in registers
5911 where gcc sometimes puts them on the stack. For maximum
5912 compatibility, we will put them in both places. */
5913 int odd_sized_struct
= (len
> MIPS64_REGSIZE
5914 && len
% MIPS64_REGSIZE
!= 0);
5917 /* Remember if the argument was written to the stack. */
5918 int stack_used_p
= 0;
5919 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
5922 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
5925 /* Write this portion of the argument to the stack. */
5926 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
5927 || odd_sized_struct
)
5929 /* Should shorter than int integer values be
5930 promoted to int before being stored? */
5931 int longword_offset
= 0;
5934 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5936 if ((typecode
== TYPE_CODE_INT
5937 || typecode
== TYPE_CODE_PTR
5938 || typecode
== TYPE_CODE_FLT
)
5940 longword_offset
= MIPS64_REGSIZE
- len
;
5945 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
5946 paddress (gdbarch
, stack_offset
));
5947 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
5948 paddress (gdbarch
, longword_offset
));
5951 addr
= sp
+ stack_offset
+ longword_offset
;
5956 fprintf_unfiltered (gdb_stdlog
, " @%s ",
5957 paddress (gdbarch
, addr
));
5958 for (i
= 0; i
< partial_len
; i
++)
5960 fprintf_unfiltered (gdb_stdlog
, "%02x",
5964 write_memory (addr
, val
, partial_len
);
5967 /* Note!!! This is NOT an else clause. Odd sized
5968 structs may go thru BOTH paths. */
5969 /* Write this portion of the argument to a general
5970 purpose register. */
5971 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
5973 LONGEST regval
= extract_signed_integer (val
, partial_len
,
5975 /* Value may need to be sign extended, because
5976 mips_isa_regsize() != mips_abi_regsize(). */
5978 /* A non-floating-point argument being passed in a
5979 general register. If a struct or union, and if
5980 the remaining length is smaller than the register
5981 size, we have to adjust the register value on
5984 It does not seem to be necessary to do the
5985 same for integral types. */
5987 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
5988 && partial_len
< MIPS64_REGSIZE
5989 && (typecode
== TYPE_CODE_STRUCT
5990 || typecode
== TYPE_CODE_UNION
))
5991 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
5995 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
5997 phex (regval
, MIPS64_REGSIZE
));
5998 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
6001 /* Prevent subsequent floating point arguments from
6002 being passed in floating point registers. */
6003 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
6009 /* Compute the offset into the stack at which we will
6010 copy the next parameter.
6012 In older ABIs, the caller reserved space for
6013 registers that contained arguments. This was loosely
6014 refered to as their "home". Consequently, space is
6015 always allocated. */
6017 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
6021 fprintf_unfiltered (gdb_stdlog
, "\n");
6024 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
6026 /* Return adjusted stack pointer. */
6030 static enum return_value_convention
6031 mips_o64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
6032 struct type
*type
, struct regcache
*regcache
,
6033 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
6035 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
6036 int mips16
= mips_pc_is_mips16 (gdbarch
, func_addr
);
6037 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
6038 enum mips_fval_reg fval_reg
;
6040 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
6041 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
6042 || TYPE_CODE (type
) == TYPE_CODE_UNION
6043 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
6044 return RETURN_VALUE_STRUCT_CONVENTION
;
6045 else if (fp_register_arg_p (gdbarch
, TYPE_CODE (type
), type
))
6047 /* A floating-point value. If reading in or copying, then we get it
6048 from/put it to FP0 for standard MIPS code or GPR2 for MIPS16 code.
6049 If writing out only, then we put it to both FP0 and GPR2. We do
6050 not support reading in with no function known, if this safety
6051 check ever triggers, then we'll have to try harder. */
6052 gdb_assert (function
|| !readbuf
);
6057 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
6060 fprintf_unfiltered (gdb_stderr
, "Return float in $2\n");
6062 case mips_fval_both
:
6063 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0 and $2\n");
6066 if (fval_reg
!= mips_fval_gpr
)
6067 mips_xfer_register (gdbarch
, regcache
,
6068 (gdbarch_num_regs (gdbarch
)
6069 + mips_regnum (gdbarch
)->fp0
),
6071 gdbarch_byte_order (gdbarch
),
6072 readbuf
, writebuf
, 0);
6073 if (fval_reg
!= mips_fval_fpr
)
6074 mips_xfer_register (gdbarch
, regcache
,
6075 gdbarch_num_regs (gdbarch
) + 2,
6077 gdbarch_byte_order (gdbarch
),
6078 readbuf
, writebuf
, 0);
6079 return RETURN_VALUE_REGISTER_CONVENTION
;
6083 /* A scalar extract each part but least-significant-byte
6087 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
6088 offset
< TYPE_LENGTH (type
);
6089 offset
+= MIPS64_REGSIZE
, regnum
++)
6091 int xfer
= MIPS64_REGSIZE
;
6092 if (offset
+ xfer
> TYPE_LENGTH (type
))
6093 xfer
= TYPE_LENGTH (type
) - offset
;
6095 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
6096 offset
, xfer
, regnum
);
6097 mips_xfer_register (gdbarch
, regcache
,
6098 gdbarch_num_regs (gdbarch
) + regnum
,
6099 xfer
, gdbarch_byte_order (gdbarch
),
6100 readbuf
, writebuf
, offset
);
6102 return RETURN_VALUE_REGISTER_CONVENTION
;
6106 /* Floating point register management.
6108 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
6109 64bit operations, these early MIPS cpus treat fp register pairs
6110 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
6111 registers and offer a compatibility mode that emulates the MIPS2 fp
6112 model. When operating in MIPS2 fp compat mode, later cpu's split
6113 double precision floats into two 32-bit chunks and store them in
6114 consecutive fp regs. To display 64-bit floats stored in this
6115 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
6116 Throw in user-configurable endianness and you have a real mess.
6118 The way this works is:
6119 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
6120 double-precision value will be split across two logical registers.
6121 The lower-numbered logical register will hold the low-order bits,
6122 regardless of the processor's endianness.
6123 - If we are on a 64-bit processor, and we are looking for a
6124 single-precision value, it will be in the low ordered bits
6125 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
6126 save slot in memory.
6127 - If we are in 64-bit mode, everything is straightforward.
6129 Note that this code only deals with "live" registers at the top of the
6130 stack. We will attempt to deal with saved registers later, when
6131 the raw/cooked register interface is in place. (We need a general
6132 interface that can deal with dynamic saved register sizes -- fp
6133 regs could be 32 bits wide in one frame and 64 on the frame above
6136 /* Copy a 32-bit single-precision value from the current frame
6137 into rare_buffer. */
6140 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
6141 gdb_byte
*rare_buffer
)
6143 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6144 int raw_size
= register_size (gdbarch
, regno
);
6145 gdb_byte
*raw_buffer
= alloca (raw_size
);
6147 if (!deprecated_frame_register_read (frame
, regno
, raw_buffer
))
6148 error (_("can't read register %d (%s)"),
6149 regno
, gdbarch_register_name (gdbarch
, regno
));
6152 /* We have a 64-bit value for this register. Find the low-order
6156 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6161 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
6165 memcpy (rare_buffer
, raw_buffer
, 4);
6169 /* Copy a 64-bit double-precision value from the current frame into
6170 rare_buffer. This may include getting half of it from the next
6174 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
6175 gdb_byte
*rare_buffer
)
6177 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6178 int raw_size
= register_size (gdbarch
, regno
);
6180 if (raw_size
== 8 && !mips2_fp_compat (frame
))
6182 /* We have a 64-bit value for this register, and we should use
6184 if (!deprecated_frame_register_read (frame
, regno
, rare_buffer
))
6185 error (_("can't read register %d (%s)"),
6186 regno
, gdbarch_register_name (gdbarch
, regno
));
6190 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
6192 if ((rawnum
- mips_regnum (gdbarch
)->fp0
) & 1)
6193 internal_error (__FILE__
, __LINE__
,
6194 _("mips_read_fp_register_double: bad access to "
6195 "odd-numbered FP register"));
6197 /* mips_read_fp_register_single will find the correct 32 bits from
6199 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6201 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
6202 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
6206 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
6207 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
6213 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
6215 { /* Do values for FP (float) regs. */
6216 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6217 gdb_byte
*raw_buffer
;
6218 double doub
, flt1
; /* Doubles extracted from raw hex data. */
6221 raw_buffer
= alloca (2 * register_size (gdbarch
,
6222 mips_regnum (gdbarch
)->fp0
));
6224 fprintf_filtered (file
, "%s:", gdbarch_register_name (gdbarch
, regnum
));
6225 fprintf_filtered (file
, "%*s",
6226 4 - (int) strlen (gdbarch_register_name (gdbarch
, regnum
)),
6229 if (register_size (gdbarch
, regnum
) == 4 || mips2_fp_compat (frame
))
6231 struct value_print_options opts
;
6233 /* 4-byte registers: Print hex and floating. Also print even
6234 numbered registers as doubles. */
6235 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
6236 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
6239 get_formatted_print_options (&opts
, 'x');
6240 print_scalar_formatted (raw_buffer
,
6241 builtin_type (gdbarch
)->builtin_uint32
,
6244 fprintf_filtered (file
, " flt: ");
6246 fprintf_filtered (file
, " <invalid float> ");
6248 fprintf_filtered (file
, "%-17.9g", flt1
);
6250 if ((regnum
- gdbarch_num_regs (gdbarch
)) % 2 == 0)
6252 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
6253 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
6256 fprintf_filtered (file
, " dbl: ");
6258 fprintf_filtered (file
, "<invalid double>");
6260 fprintf_filtered (file
, "%-24.17g", doub
);
6265 struct value_print_options opts
;
6267 /* Eight byte registers: print each one as hex, float and double. */
6268 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
6269 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
6272 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
6273 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
6276 get_formatted_print_options (&opts
, 'x');
6277 print_scalar_formatted (raw_buffer
,
6278 builtin_type (gdbarch
)->builtin_uint64
,
6281 fprintf_filtered (file
, " flt: ");
6283 fprintf_filtered (file
, "<invalid float>");
6285 fprintf_filtered (file
, "%-17.9g", flt1
);
6287 fprintf_filtered (file
, " dbl: ");
6289 fprintf_filtered (file
, "<invalid double>");
6291 fprintf_filtered (file
, "%-24.17g", doub
);
6296 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
6299 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6300 struct value_print_options opts
;
6303 if (mips_float_register_p (gdbarch
, regnum
))
6305 mips_print_fp_register (file
, frame
, regnum
);
6309 val
= get_frame_register_value (frame
, regnum
);
6311 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
6313 /* The problem with printing numeric register names (r26, etc.) is that
6314 the user can't use them on input. Probably the best solution is to
6315 fix it so that either the numeric or the funky (a2, etc.) names
6316 are accepted on input. */
6317 if (regnum
< MIPS_NUMREGS
)
6318 fprintf_filtered (file
, "(r%d): ", regnum
);
6320 fprintf_filtered (file
, ": ");
6322 get_formatted_print_options (&opts
, 'x');
6323 val_print_scalar_formatted (value_type (val
),
6324 value_contents_for_printing (val
),
6325 value_embedded_offset (val
),
6330 /* Replacement for generic do_registers_info.
6331 Print regs in pretty columns. */
6334 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
6337 fprintf_filtered (file
, " ");
6338 mips_print_fp_register (file
, frame
, regnum
);
6339 fprintf_filtered (file
, "\n");
6344 /* Print a row's worth of GP (int) registers, with name labels above. */
6347 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
6350 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6351 /* Do values for GP (int) regs. */
6352 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
6353 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols
6358 /* For GP registers, we print a separate row of names above the vals. */
6359 for (col
= 0, regnum
= start_regnum
;
6360 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
6361 + gdbarch_num_pseudo_regs (gdbarch
);
6364 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
6365 continue; /* unused register */
6366 if (mips_float_register_p (gdbarch
, regnum
))
6367 break; /* End the row: reached FP register. */
6368 /* Large registers are handled separately. */
6369 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
6372 break; /* End the row before this register. */
6374 /* Print this register on a row by itself. */
6375 mips_print_register (file
, frame
, regnum
);
6376 fprintf_filtered (file
, "\n");
6380 fprintf_filtered (file
, " ");
6381 fprintf_filtered (file
,
6382 mips_abi_regsize (gdbarch
) == 8 ? "%17s" : "%9s",
6383 gdbarch_register_name (gdbarch
, regnum
));
6390 /* Print the R0 to R31 names. */
6391 if ((start_regnum
% gdbarch_num_regs (gdbarch
)) < MIPS_NUMREGS
)
6392 fprintf_filtered (file
, "\n R%-4d",
6393 start_regnum
% gdbarch_num_regs (gdbarch
));
6395 fprintf_filtered (file
, "\n ");
6397 /* Now print the values in hex, 4 or 8 to the row. */
6398 for (col
= 0, regnum
= start_regnum
;
6399 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
6400 + gdbarch_num_pseudo_regs (gdbarch
);
6403 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
6404 continue; /* unused register */
6405 if (mips_float_register_p (gdbarch
, regnum
))
6406 break; /* End row: reached FP register. */
6407 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
6408 break; /* End row: large register. */
6410 /* OK: get the data in raw format. */
6411 if (!deprecated_frame_register_read (frame
, regnum
, raw_buffer
))
6412 error (_("can't read register %d (%s)"),
6413 regnum
, gdbarch_register_name (gdbarch
, regnum
));
6414 /* pad small registers */
6416 byte
< (mips_abi_regsize (gdbarch
)
6417 - register_size (gdbarch
, regnum
)); byte
++)
6418 printf_filtered (" ");
6419 /* Now print the register value in hex, endian order. */
6420 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6422 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
6423 byte
< register_size (gdbarch
, regnum
); byte
++)
6424 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
6426 for (byte
= register_size (gdbarch
, regnum
) - 1;
6428 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
6429 fprintf_filtered (file
, " ");
6432 if (col
> 0) /* ie. if we actually printed anything... */
6433 fprintf_filtered (file
, "\n");
6438 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */
6441 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
6442 struct frame_info
*frame
, int regnum
, int all
)
6444 if (regnum
!= -1) /* Do one specified register. */
6446 gdb_assert (regnum
>= gdbarch_num_regs (gdbarch
));
6447 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
6448 error (_("Not a valid register for the current processor type"));
6450 mips_print_register (file
, frame
, regnum
);
6451 fprintf_filtered (file
, "\n");
6454 /* Do all (or most) registers. */
6456 regnum
= gdbarch_num_regs (gdbarch
);
6457 while (regnum
< gdbarch_num_regs (gdbarch
)
6458 + gdbarch_num_pseudo_regs (gdbarch
))
6460 if (mips_float_register_p (gdbarch
, regnum
))
6462 if (all
) /* True for "INFO ALL-REGISTERS" command. */
6463 regnum
= print_fp_register_row (file
, frame
, regnum
);
6465 regnum
+= MIPS_NUMREGS
; /* Skip floating point regs. */
6468 regnum
= print_gp_register_row (file
, frame
, regnum
);
6474 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
6475 struct frame_info
*frame
)
6477 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
6478 CORE_ADDR pc
= get_frame_pc (frame
);
6479 struct address_space
*aspace
;
6485 if ((mips_pc_is_mips (pc
)
6486 && !mips32_insn_at_pc_has_delay_slot (gdbarch
, pc
))
6487 || (mips_pc_is_micromips (gdbarch
, pc
)
6488 && !micromips_insn_at_pc_has_delay_slot (gdbarch
, pc
, 0))
6489 || (mips_pc_is_mips16 (gdbarch
, pc
)
6490 && !mips16_insn_at_pc_has_delay_slot (gdbarch
, pc
, 0)))
6493 isa
= mips_pc_isa (gdbarch
, pc
);
6494 /* _has_delay_slot above will have validated the read. */
6495 insn
= mips_fetch_instruction (gdbarch
, isa
, pc
, NULL
);
6496 size
= mips_insn_size (isa
, insn
);
6497 aspace
= get_frame_address_space (frame
);
6498 return breakpoint_here_p (aspace
, pc
+ size
) != no_breakpoint_here
;
6501 /* To skip prologues, I use this predicate. Returns either PC itself
6502 if the code at PC does not look like a function prologue; otherwise
6503 returns an address that (if we're lucky) follows the prologue. If
6504 LENIENT, then we must skip everything which is involved in setting
6505 up the frame (it's OK to skip more, just so long as we don't skip
6506 anything which might clobber the registers which are being saved.
6507 We must skip more in the case where part of the prologue is in the
6508 delay slot of a non-prologue instruction). */
6511 mips_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6514 CORE_ADDR func_addr
;
6516 /* See if we can determine the end of the prologue via the symbol table.
6517 If so, then return either PC, or the PC after the prologue, whichever
6519 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
6521 CORE_ADDR post_prologue_pc
6522 = skip_prologue_using_sal (gdbarch
, func_addr
);
6523 if (post_prologue_pc
!= 0)
6524 return max (pc
, post_prologue_pc
);
6527 /* Can't determine prologue from the symbol table, need to examine
6530 /* Find an upper limit on the function prologue using the debug
6531 information. If the debug information could not be used to provide
6532 that bound, then use an arbitrary large number as the upper bound. */
6533 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
6535 limit_pc
= pc
+ 100; /* Magic. */
6537 if (mips_pc_is_mips16 (gdbarch
, pc
))
6538 return mips16_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6539 else if (mips_pc_is_micromips (gdbarch
, pc
))
6540 return micromips_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6542 return mips32_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6545 /* Check whether the PC is in a function epilogue (32-bit version).
6546 This is a helper function for mips_in_function_epilogue_p. */
6548 mips32_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6550 CORE_ADDR func_addr
= 0, func_end
= 0;
6552 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6554 /* The MIPS epilogue is max. 12 bytes long. */
6555 CORE_ADDR addr
= func_end
- 12;
6557 if (addr
< func_addr
+ 4)
6558 addr
= func_addr
+ 4;
6562 for (; pc
< func_end
; pc
+= MIPS_INSN32_SIZE
)
6564 unsigned long high_word
;
6567 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
6568 high_word
= (inst
>> 16) & 0xffff;
6570 if (high_word
!= 0x27bd /* addiu $sp,$sp,offset */
6571 && high_word
!= 0x67bd /* daddiu $sp,$sp,offset */
6572 && inst
!= 0x03e00008 /* jr $ra */
6573 && inst
!= 0x00000000) /* nop */
6583 /* Check whether the PC is in a function epilogue (microMIPS version).
6584 This is a helper function for mips_in_function_epilogue_p. */
6587 micromips_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6589 CORE_ADDR func_addr
= 0;
6590 CORE_ADDR func_end
= 0;
6598 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6601 /* The microMIPS epilogue is max. 12 bytes long. */
6602 addr
= func_end
- 12;
6604 if (addr
< func_addr
+ 2)
6605 addr
= func_addr
+ 2;
6609 for (; pc
< func_end
; pc
+= loc
)
6612 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
6613 loc
+= MIPS_INSN16_SIZE
;
6614 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
6616 /* 48-bit instructions. */
6617 case 3 * MIPS_INSN16_SIZE
:
6618 /* No epilogue instructions in this category. */
6621 /* 32-bit instructions. */
6622 case 2 * MIPS_INSN16_SIZE
:
6624 insn
|= mips_fetch_instruction (gdbarch
,
6625 ISA_MICROMIPS
, pc
+ loc
, NULL
);
6626 loc
+= MIPS_INSN16_SIZE
;
6627 switch (micromips_op (insn
>> 16))
6629 case 0xc: /* ADDIU: bits 001100 */
6630 case 0x17: /* DADDIU: bits 010111 */
6631 sreg
= b0s5_reg (insn
>> 16);
6632 dreg
= b5s5_reg (insn
>> 16);
6633 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
6634 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
6635 /* (D)ADDIU $sp, imm */
6645 /* 16-bit instructions. */
6646 case MIPS_INSN16_SIZE
:
6647 switch (micromips_op (insn
))
6649 case 0x3: /* MOVE: bits 000011 */
6650 sreg
= b0s5_reg (insn
);
6651 dreg
= b5s5_reg (insn
);
6652 if (sreg
== 0 && dreg
== 0)
6653 /* MOVE $zero, $zero aka NOP */
6657 case 0x11: /* POOL16C: bits 010001 */
6658 if (b5s5_op (insn
) == 0x18
6659 /* JRADDIUSP: bits 010011 11000 */
6660 || (b5s5_op (insn
) == 0xd
6661 /* JRC: bits 010011 01101 */
6662 && b0s5_reg (insn
) == MIPS_RA_REGNUM
))
6667 case 0x13: /* POOL16D: bits 010011 */
6668 offset
= micromips_decode_imm9 (b1s9_imm (insn
));
6669 if ((insn
& 0x1) == 0x1
6670 /* ADDIUSP: bits 010011 1 */
6684 /* Check whether the PC is in a function epilogue (16-bit version).
6685 This is a helper function for mips_in_function_epilogue_p. */
6687 mips16_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6689 CORE_ADDR func_addr
= 0, func_end
= 0;
6691 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6693 /* The MIPS epilogue is max. 12 bytes long. */
6694 CORE_ADDR addr
= func_end
- 12;
6696 if (addr
< func_addr
+ 4)
6697 addr
= func_addr
+ 4;
6701 for (; pc
< func_end
; pc
+= MIPS_INSN16_SIZE
)
6703 unsigned short inst
;
6705 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, pc
, NULL
);
6707 if ((inst
& 0xf800) == 0xf000) /* extend */
6710 if (inst
!= 0x6300 /* addiu $sp,offset */
6711 && inst
!= 0xfb00 /* daddiu $sp,$sp,offset */
6712 && inst
!= 0xe820 /* jr $ra */
6713 && inst
!= 0xe8a0 /* jrc $ra */
6714 && inst
!= 0x6500) /* nop */
6724 /* The epilogue is defined here as the area at the end of a function,
6725 after an instruction which destroys the function's stack frame. */
6727 mips_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6729 if (mips_pc_is_mips16 (gdbarch
, pc
))
6730 return mips16_in_function_epilogue_p (gdbarch
, pc
);
6731 else if (mips_pc_is_micromips (gdbarch
, pc
))
6732 return micromips_in_function_epilogue_p (gdbarch
, pc
);
6734 return mips32_in_function_epilogue_p (gdbarch
, pc
);
6737 /* Root of all "set mips "/"show mips " commands. This will eventually be
6738 used for all MIPS-specific commands. */
6741 show_mips_command (char *args
, int from_tty
)
6743 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
6747 set_mips_command (char *args
, int from_tty
)
6750 ("\"set mips\" must be followed by an appropriate subcommand.\n");
6751 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
6754 /* Commands to show/set the MIPS FPU type. */
6757 show_mipsfpu_command (char *args
, int from_tty
)
6761 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_mips
)
6764 ("The MIPS floating-point coprocessor is unknown "
6765 "because the current architecture is not MIPS.\n");
6769 switch (MIPS_FPU_TYPE (target_gdbarch ()))
6771 case MIPS_FPU_SINGLE
:
6772 fpu
= "single-precision";
6774 case MIPS_FPU_DOUBLE
:
6775 fpu
= "double-precision";
6778 fpu
= "absent (none)";
6781 internal_error (__FILE__
, __LINE__
, _("bad switch"));
6783 if (mips_fpu_type_auto
)
6784 printf_unfiltered ("The MIPS floating-point coprocessor "
6785 "is set automatically (currently %s)\n",
6789 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
6794 set_mipsfpu_command (char *args
, int from_tty
)
6796 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", "
6797 "\"single\",\"none\" or \"auto\".\n");
6798 show_mipsfpu_command (args
, from_tty
);
6802 set_mipsfpu_single_command (char *args
, int from_tty
)
6804 struct gdbarch_info info
;
6805 gdbarch_info_init (&info
);
6806 mips_fpu_type
= MIPS_FPU_SINGLE
;
6807 mips_fpu_type_auto
= 0;
6808 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6809 instead of relying on globals. Doing that would let generic code
6810 handle the search for this specific architecture. */
6811 if (!gdbarch_update_p (info
))
6812 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6816 set_mipsfpu_double_command (char *args
, int from_tty
)
6818 struct gdbarch_info info
;
6819 gdbarch_info_init (&info
);
6820 mips_fpu_type
= MIPS_FPU_DOUBLE
;
6821 mips_fpu_type_auto
= 0;
6822 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6823 instead of relying on globals. Doing that would let generic code
6824 handle the search for this specific architecture. */
6825 if (!gdbarch_update_p (info
))
6826 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6830 set_mipsfpu_none_command (char *args
, int from_tty
)
6832 struct gdbarch_info info
;
6833 gdbarch_info_init (&info
);
6834 mips_fpu_type
= MIPS_FPU_NONE
;
6835 mips_fpu_type_auto
= 0;
6836 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6837 instead of relying on globals. Doing that would let generic code
6838 handle the search for this specific architecture. */
6839 if (!gdbarch_update_p (info
))
6840 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6844 set_mipsfpu_auto_command (char *args
, int from_tty
)
6846 mips_fpu_type_auto
= 1;
6849 /* Attempt to identify the particular processor model by reading the
6850 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
6851 the relevant processor still exists (it dates back to '94) and
6852 secondly this is not the way to do this. The processor type should
6853 be set by forcing an architecture change. */
6856 deprecated_mips_set_processor_regs_hack (void)
6858 struct regcache
*regcache
= get_current_regcache ();
6859 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
6860 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
6863 regcache_cooked_read_unsigned (regcache
, MIPS_PRID_REGNUM
, &prid
);
6864 if ((prid
& ~0xf) == 0x700)
6865 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
6868 /* Just like reinit_frame_cache, but with the right arguments to be
6869 callable as an sfunc. */
6872 reinit_frame_cache_sfunc (char *args
, int from_tty
,
6873 struct cmd_list_element
*c
)
6875 reinit_frame_cache ();
6879 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
6881 struct gdbarch
*gdbarch
= info
->application_data
;
6883 /* FIXME: cagney/2003-06-26: Is this even necessary? The
6884 disassembler needs to be able to locally determine the ISA, and
6885 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
6887 if (mips_pc_is_mips16 (gdbarch
, memaddr
))
6888 info
->mach
= bfd_mach_mips16
;
6889 else if (mips_pc_is_micromips (gdbarch
, memaddr
))
6890 info
->mach
= bfd_mach_mips_micromips
;
6892 /* Round down the instruction address to the appropriate boundary. */
6893 memaddr
&= (info
->mach
== bfd_mach_mips16
6894 || info
->mach
== bfd_mach_mips_micromips
) ? ~1 : ~3;
6896 /* Set the disassembler options. */
6897 if (!info
->disassembler_options
)
6898 /* This string is not recognized explicitly by the disassembler,
6899 but it tells the disassembler to not try to guess the ABI from
6900 the bfd elf headers, such that, if the user overrides the ABI
6901 of a program linked as NewABI, the disassembly will follow the
6902 register naming conventions specified by the user. */
6903 info
->disassembler_options
= "gpr-names=32";
6905 /* Call the appropriate disassembler based on the target endian-ness. */
6906 if (info
->endian
== BFD_ENDIAN_BIG
)
6907 return print_insn_big_mips (memaddr
, info
);
6909 return print_insn_little_mips (memaddr
, info
);
6913 gdb_print_insn_mips_n32 (bfd_vma memaddr
, struct disassemble_info
*info
)
6915 /* Set up the disassembler info, so that we get the right
6916 register names from libopcodes. */
6917 info
->disassembler_options
= "gpr-names=n32";
6918 info
->flavour
= bfd_target_elf_flavour
;
6920 return gdb_print_insn_mips (memaddr
, info
);
6924 gdb_print_insn_mips_n64 (bfd_vma memaddr
, struct disassemble_info
*info
)
6926 /* Set up the disassembler info, so that we get the right
6927 register names from libopcodes. */
6928 info
->disassembler_options
= "gpr-names=64";
6929 info
->flavour
= bfd_target_elf_flavour
;
6931 return gdb_print_insn_mips (memaddr
, info
);
6934 /* This function implements gdbarch_breakpoint_from_pc. It uses the
6935 program counter value to determine whether a 16- or 32-bit breakpoint
6936 should be used. It returns a pointer to a string of bytes that encode a
6937 breakpoint instruction, stores the length of the string to *lenptr, and
6938 adjusts pc (if necessary) to point to the actual memory location where
6939 the breakpoint should be inserted. */
6941 static const gdb_byte
*
6942 mips_breakpoint_from_pc (struct gdbarch
*gdbarch
,
6943 CORE_ADDR
*pcptr
, int *lenptr
)
6945 CORE_ADDR pc
= *pcptr
;
6947 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6949 if (mips_pc_is_mips16 (gdbarch
, pc
))
6951 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
6952 *pcptr
= unmake_compact_addr (pc
);
6953 *lenptr
= sizeof (mips16_big_breakpoint
);
6954 return mips16_big_breakpoint
;
6956 else if (mips_pc_is_micromips (gdbarch
, pc
))
6958 static gdb_byte micromips16_big_breakpoint
[] = { 0x46, 0x85 };
6959 static gdb_byte micromips32_big_breakpoint
[] = { 0, 0x5, 0, 0x7 };
6964 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, &status
);
6966 : mips_insn_size (ISA_MICROMIPS
, insn
) == 2 ? 2 : 4;
6967 *pcptr
= unmake_compact_addr (pc
);
6969 return (size
== 2) ? micromips16_big_breakpoint
6970 : micromips32_big_breakpoint
;
6974 /* The IDT board uses an unusual breakpoint value, and
6975 sometimes gets confused when it sees the usual MIPS
6976 breakpoint instruction. */
6977 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
6978 static gdb_byte pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
6979 static gdb_byte idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
6980 /* Likewise, IRIX appears to expect a different breakpoint,
6981 although this is not apparent until you try to use pthreads. */
6982 static gdb_byte irix_big_breakpoint
[] = { 0, 0, 0, 0xd };
6984 *lenptr
= sizeof (big_breakpoint
);
6986 if (strcmp (target_shortname
, "mips") == 0)
6987 return idt_big_breakpoint
;
6988 else if (strcmp (target_shortname
, "ddb") == 0
6989 || strcmp (target_shortname
, "pmon") == 0
6990 || strcmp (target_shortname
, "lsi") == 0)
6991 return pmon_big_breakpoint
;
6992 else if (gdbarch_osabi (gdbarch
) == GDB_OSABI_IRIX
)
6993 return irix_big_breakpoint
;
6995 return big_breakpoint
;
7000 if (mips_pc_is_mips16 (gdbarch
, pc
))
7002 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
7003 *pcptr
= unmake_compact_addr (pc
);
7004 *lenptr
= sizeof (mips16_little_breakpoint
);
7005 return mips16_little_breakpoint
;
7007 else if (mips_pc_is_micromips (gdbarch
, pc
))
7009 static gdb_byte micromips16_little_breakpoint
[] = { 0x85, 0x46 };
7010 static gdb_byte micromips32_little_breakpoint
[] = { 0x5, 0, 0x7, 0 };
7015 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, &status
);
7017 : mips_insn_size (ISA_MICROMIPS
, insn
) == 2 ? 2 : 4;
7018 *pcptr
= unmake_compact_addr (pc
);
7020 return (size
== 2) ? micromips16_little_breakpoint
7021 : micromips32_little_breakpoint
;
7025 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
7026 static gdb_byte pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
7027 static gdb_byte idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
7029 *lenptr
= sizeof (little_breakpoint
);
7031 if (strcmp (target_shortname
, "mips") == 0)
7032 return idt_little_breakpoint
;
7033 else if (strcmp (target_shortname
, "ddb") == 0
7034 || strcmp (target_shortname
, "pmon") == 0
7035 || strcmp (target_shortname
, "lsi") == 0)
7036 return pmon_little_breakpoint
;
7038 return little_breakpoint
;
7043 /* Determine the remote breakpoint kind suitable for the PC. The following
7046 * 2 -- 16-bit MIPS16 mode breakpoint,
7048 * 3 -- 16-bit microMIPS mode breakpoint,
7050 * 4 -- 32-bit standard MIPS mode breakpoint,
7052 * 5 -- 32-bit microMIPS mode breakpoint. */
7055 mips_remote_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
,
7058 CORE_ADDR pc
= *pcptr
;
7060 if (mips_pc_is_mips16 (gdbarch
, pc
))
7062 *pcptr
= unmake_compact_addr (pc
);
7065 else if (mips_pc_is_micromips (gdbarch
, pc
))
7071 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, &status
);
7072 size
= status
? 2 : mips_insn_size (ISA_MICROMIPS
, insn
) == 2 ? 2 : 4;
7073 *pcptr
= unmake_compact_addr (pc
);
7074 *kindptr
= size
| 1;
7080 /* Return non-zero if the standard MIPS instruction INST has a branch
7081 delay slot (i.e. it is a jump or branch instruction). This function
7082 is based on mips32_next_pc. */
7085 mips32_instruction_has_delay_slot (struct gdbarch
*gdbarch
, ULONGEST inst
)
7091 op
= itype_op (inst
);
7092 if ((inst
& 0xe0000000) != 0)
7094 rs
= itype_rs (inst
);
7095 rt
= itype_rt (inst
);
7096 return (is_octeon_bbit_op (op
, gdbarch
)
7097 || op
>> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
7098 || op
== 29 /* JALX: bits 011101 */
7101 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
7102 || (rs
== 9 && (rt
& 0x2) == 0)
7103 /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */
7104 || (rs
== 10 && (rt
& 0x2) == 0))));
7105 /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */
7108 switch (op
& 0x07) /* extract bits 28,27,26 */
7110 case 0: /* SPECIAL */
7111 op
= rtype_funct (inst
);
7112 return (op
== 8 /* JR */
7113 || op
== 9); /* JALR */
7114 break; /* end SPECIAL */
7115 case 1: /* REGIMM */
7116 rs
= itype_rs (inst
);
7117 rt
= itype_rt (inst
); /* branch condition */
7118 return ((rt
& 0xc) == 0
7119 /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */
7120 /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */
7121 || ((rt
& 0x1e) == 0x1c && rs
== 0));
7122 /* BPOSGE32, BPOSGE64: bits 1110x */
7123 break; /* end REGIMM */
7124 default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */
7130 /* Return non-zero if a standard MIPS instruction at ADDR has a branch
7131 delay slot (i.e. it is a jump or branch instruction). */
7134 mips32_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
7139 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, addr
, &status
);
7143 return mips32_instruction_has_delay_slot (gdbarch
, insn
);
7146 /* Return non-zero if the microMIPS instruction INSN, comprising the
7147 16-bit major opcode word in the high 16 bits and any second word
7148 in the low 16 bits, has a branch delay slot (i.e. it is a non-compact
7149 jump or branch instruction). The instruction must be 32-bit if
7150 MUSTBE32 is set or can be any instruction otherwise. */
7153 micromips_instruction_has_delay_slot (ULONGEST insn
, int mustbe32
)
7155 ULONGEST major
= insn
>> 16;
7157 switch (micromips_op (major
))
7159 /* 16-bit instructions. */
7160 case 0x33: /* B16: bits 110011 */
7161 case 0x2b: /* BNEZ16: bits 101011 */
7162 case 0x23: /* BEQZ16: bits 100011 */
7164 case 0x11: /* POOL16C: bits 010001 */
7166 && ((b5s5_op (major
) == 0xc
7167 /* JR16: bits 010001 01100 */
7168 || (b5s5_op (major
) & 0x1e) == 0xe)));
7169 /* JALR16, JALRS16: bits 010001 0111x */
7170 /* 32-bit instructions. */
7171 case 0x3d: /* JAL: bits 111101 */
7172 case 0x3c: /* JALX: bits 111100 */
7173 case 0x35: /* J: bits 110101 */
7174 case 0x2d: /* BNE: bits 101101 */
7175 case 0x25: /* BEQ: bits 100101 */
7176 case 0x1d: /* JALS: bits 011101 */
7178 case 0x10: /* POOL32I: bits 010000 */
7179 return ((b5s5_op (major
) & 0x1c) == 0x0
7180 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
7181 || (b5s5_op (major
) & 0x1d) == 0x4
7182 /* BLEZ, BGTZ: bits 010000 001x0 */
7183 || (b5s5_op (major
) & 0x1d) == 0x11
7184 /* BLTZALS, BGEZALS: bits 010000 100x1 */
7185 || ((b5s5_op (major
) & 0x1e) == 0x14
7186 && (major
& 0x3) == 0x0)
7187 /* BC2F, BC2T: bits 010000 1010x xxx00 */
7188 || (b5s5_op (major
) & 0x1e) == 0x1a
7189 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
7190 || ((b5s5_op (major
) & 0x1e) == 0x1c
7191 && (major
& 0x3) == 0x0)
7192 /* BC1F, BC1T: bits 010000 1110x xxx00 */
7193 || ((b5s5_op (major
) & 0x1c) == 0x1c
7194 && (major
& 0x3) == 0x1));
7195 /* BC1ANY*: bits 010000 111xx xxx01 */
7196 case 0x0: /* POOL32A: bits 000000 */
7197 return (b0s6_op (insn
) == 0x3c
7198 /* POOL32Axf: bits 000000 ... 111100 */
7199 && (b6s10_ext (insn
) & 0x2bf) == 0x3c);
7200 /* JALR, JALR.HB: 000000 000x111100 111100 */
7201 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
7207 /* Return non-zero if a microMIPS instruction at ADDR has a branch delay
7208 slot (i.e. it is a non-compact jump instruction). The instruction
7209 must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */
7212 micromips_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
7213 CORE_ADDR addr
, int mustbe32
)
7218 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, addr
, &status
);
7222 if (mips_insn_size (ISA_MICROMIPS
, insn
) == 2 * MIPS_INSN16_SIZE
)
7224 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, addr
, &status
);
7229 return micromips_instruction_has_delay_slot (insn
, mustbe32
);
7232 /* Return non-zero if the MIPS16 instruction INST, which must be
7233 a 32-bit instruction if MUSTBE32 is set or can be any instruction
7234 otherwise, has a branch delay slot (i.e. it is a non-compact jump
7235 instruction). This function is based on mips16_next_pc. */
7238 mips16_instruction_has_delay_slot (unsigned short inst
, int mustbe32
)
7240 if ((inst
& 0xf89f) == 0xe800) /* JR/JALR (16-bit instruction) */
7242 return (inst
& 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */
7245 /* Return non-zero if a MIPS16 instruction at ADDR has a branch delay
7246 slot (i.e. it is a non-compact jump instruction). The instruction
7247 must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */
7250 mips16_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
7251 CORE_ADDR addr
, int mustbe32
)
7253 unsigned short insn
;
7256 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, addr
, &status
);
7260 return mips16_instruction_has_delay_slot (insn
, mustbe32
);
7263 /* Calculate the starting address of the MIPS memory segment BPADDR is in.
7264 This assumes KSSEG exists. */
7267 mips_segment_boundary (CORE_ADDR bpaddr
)
7269 CORE_ADDR mask
= CORE_ADDR_MAX
;
7272 if (sizeof (CORE_ADDR
) == 8)
7273 /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid
7274 a compiler warning produced where CORE_ADDR is a 32-bit type even
7275 though in that case this is dead code). */
7276 switch (bpaddr
>> ((sizeof (CORE_ADDR
) << 3) - 2) & 3)
7279 if (bpaddr
== (bfd_signed_vma
) (int32_t) bpaddr
)
7280 segsize
= 29; /* 32-bit compatibility segment */
7282 segsize
= 62; /* xkseg */
7284 case 2: /* xkphys */
7287 default: /* xksseg (1), xkuseg/kuseg (0) */
7291 else if (bpaddr
& 0x80000000) /* kernel segment */
7294 segsize
= 31; /* user segment */
7296 return bpaddr
& mask
;
7299 /* Move the breakpoint at BPADDR out of any branch delay slot by shifting
7300 it backwards if necessary. Return the address of the new location. */
7303 mips_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
7305 CORE_ADDR prev_addr
;
7307 CORE_ADDR func_addr
;
7309 /* If a breakpoint is set on the instruction in a branch delay slot,
7310 GDB gets confused. When the breakpoint is hit, the PC isn't on
7311 the instruction in the branch delay slot, the PC will point to
7312 the branch instruction. Since the PC doesn't match any known
7313 breakpoints, GDB reports a trap exception.
7315 There are two possible fixes for this problem.
7317 1) When the breakpoint gets hit, see if the BD bit is set in the
7318 Cause register (which indicates the last exception occurred in a
7319 branch delay slot). If the BD bit is set, fix the PC to point to
7320 the instruction in the branch delay slot.
7322 2) When the user sets the breakpoint, don't allow him to set the
7323 breakpoint on the instruction in the branch delay slot. Instead
7324 move the breakpoint to the branch instruction (which will have
7327 The problem with the first solution is that if the user then
7328 single-steps the processor, the branch instruction will get
7329 skipped (since GDB thinks the PC is on the instruction in the
7332 So, we'll use the second solution. To do this we need to know if
7333 the instruction we're trying to set the breakpoint on is in the
7334 branch delay slot. */
7336 boundary
= mips_segment_boundary (bpaddr
);
7338 /* Make sure we don't scan back before the beginning of the current
7339 function, since we may fetch constant data or insns that look like
7340 a jump. Of course we might do that anyway if the compiler has
7341 moved constants inline. :-( */
7342 if (find_pc_partial_function (bpaddr
, NULL
, &func_addr
, NULL
)
7343 && func_addr
> boundary
&& func_addr
<= bpaddr
)
7344 boundary
= func_addr
;
7346 if (mips_pc_is_mips (bpaddr
))
7348 if (bpaddr
== boundary
)
7351 /* If the previous instruction has a branch delay slot, we have
7352 to move the breakpoint to the branch instruction. */
7353 prev_addr
= bpaddr
- 4;
7354 if (mips32_insn_at_pc_has_delay_slot (gdbarch
, prev_addr
))
7359 int (*insn_at_pc_has_delay_slot
) (struct gdbarch
*, CORE_ADDR
, int);
7360 CORE_ADDR addr
, jmpaddr
;
7363 boundary
= unmake_compact_addr (boundary
);
7365 /* The only MIPS16 instructions with delay slots are JAL, JALX,
7366 JALR and JR. An absolute JAL/JALX is always 4 bytes long,
7367 so try for that first, then try the 2 byte JALR/JR.
7368 The microMIPS ASE has a whole range of jumps and branches
7369 with delay slots, some of which take 4 bytes and some take
7370 2 bytes, so the idea is the same.
7371 FIXME: We have to assume that bpaddr is not the second half
7372 of an extended instruction. */
7373 insn_at_pc_has_delay_slot
= (mips_pc_is_micromips (gdbarch
, bpaddr
)
7374 ? micromips_insn_at_pc_has_delay_slot
7375 : mips16_insn_at_pc_has_delay_slot
);
7379 for (i
= 1; i
< 4; i
++)
7381 if (unmake_compact_addr (addr
) == boundary
)
7383 addr
-= MIPS_INSN16_SIZE
;
7384 if (i
== 1 && insn_at_pc_has_delay_slot (gdbarch
, addr
, 0))
7385 /* Looks like a JR/JALR at [target-1], but it could be
7386 the second word of a previous JAL/JALX, so record it
7387 and check back one more. */
7389 else if (i
> 1 && insn_at_pc_has_delay_slot (gdbarch
, addr
, 1))
7392 /* Looks like a JAL/JALX at [target-2], but it could also
7393 be the second word of a previous JAL/JALX, record it,
7394 and check back one more. */
7397 /* Looks like a JAL/JALX at [target-3], so any previously
7398 recorded JAL/JALX or JR/JALR must be wrong, because:
7401 -2: JAL-ext (can't be JAL/JALX)
7402 -1: bdslot (can't be JR/JALR)
7405 Of course it could be another JAL-ext which looks
7406 like a JAL, but in that case we'd have broken out
7407 of this loop at [target-2]:
7411 -2: bdslot (can't be jmp)
7418 /* Not a jump instruction: if we're at [target-1] this
7419 could be the second word of a JAL/JALX, so continue;
7420 otherwise we're done. */
7433 /* Return non-zero if SUFFIX is one of the numeric suffixes used for MIPS16
7434 call stubs, one of 1, 2, 5, 6, 9, 10, or, if ZERO is non-zero, also 0. */
7437 mips_is_stub_suffix (const char *suffix
, int zero
)
7442 return zero
&& suffix
[1] == '\0';
7444 return suffix
[1] == '\0' || (suffix
[1] == '0' && suffix
[2] == '\0');
7449 return suffix
[1] == '\0';
7455 /* Return non-zero if MODE is one of the mode infixes used for MIPS16
7456 call stubs, one of sf, df, sc, or dc. */
7459 mips_is_stub_mode (const char *mode
)
7461 return ((mode
[0] == 's' || mode
[0] == 'd')
7462 && (mode
[1] == 'f' || mode
[1] == 'c'));
7465 /* Code at PC is a compiler-generated stub. Such a stub for a function
7466 bar might have a name like __fn_stub_bar, and might look like this:
7473 followed by (or interspersed with):
7480 addiu $25, $25, %lo(bar)
7483 ($1 may be used in old code; for robustness we accept any register)
7486 lui $28, %hi(_gp_disp)
7487 addiu $28, $28, %lo(_gp_disp)
7490 addiu $25, $25, %lo(bar)
7493 In the case of a __call_stub_bar stub, the sequence to set up
7494 arguments might look like this:
7501 followed by (or interspersed with) one of the jump sequences above.
7503 In the case of a __call_stub_fp_bar stub, JAL or JALR is used instead
7504 of J or JR, respectively, followed by:
7510 We are at the beginning of the stub here, and scan down and extract
7511 the target address from the jump immediate instruction or, if a jump
7512 register instruction is used, from the register referred. Return
7513 the value of PC calculated or 0 if inconclusive.
7515 The limit on the search is arbitrarily set to 20 instructions. FIXME. */
7518 mips_get_mips16_fn_stub_pc (struct frame_info
*frame
, CORE_ADDR pc
)
7520 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7521 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7522 int addrreg
= MIPS_ZERO_REGNUM
;
7523 CORE_ADDR start_pc
= pc
;
7524 CORE_ADDR target_pc
= 0;
7531 status
== 0 && target_pc
== 0 && i
< 20;
7532 i
++, pc
+= MIPS_INSN32_SIZE
)
7534 ULONGEST inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
7540 switch (itype_op (inst
))
7542 case 0: /* SPECIAL */
7543 switch (rtype_funct (inst
))
7547 rs
= rtype_rs (inst
);
7548 if (rs
== MIPS_GP_REGNUM
)
7549 target_pc
= gp
; /* Hmm... */
7550 else if (rs
== addrreg
)
7554 case 0x21: /* ADDU */
7555 rt
= rtype_rt (inst
);
7556 rs
= rtype_rs (inst
);
7557 rd
= rtype_rd (inst
);
7558 if (rd
== MIPS_GP_REGNUM
7559 && ((rs
== MIPS_GP_REGNUM
&& rt
== MIPS_T9_REGNUM
)
7560 || (rs
== MIPS_T9_REGNUM
&& rt
== MIPS_GP_REGNUM
)))
7568 target_pc
= jtype_target (inst
) << 2;
7569 target_pc
+= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
7573 rt
= itype_rt (inst
);
7574 rs
= itype_rs (inst
);
7577 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
7578 if (rt
== MIPS_GP_REGNUM
)
7580 else if (rt
== addrreg
)
7586 rt
= itype_rt (inst
);
7587 imm
= ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 16;
7588 if (rt
== MIPS_GP_REGNUM
)
7590 else if (rt
!= MIPS_ZERO_REGNUM
)
7598 rt
= itype_rt (inst
);
7599 rs
= itype_rs (inst
);
7600 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
7601 if (gp
!= 0 && rs
== MIPS_GP_REGNUM
)
7605 memset (buf
, 0, sizeof (buf
));
7606 status
= target_read_memory (gp
+ imm
, buf
, sizeof (buf
));
7608 addr
= extract_signed_integer (buf
, sizeof (buf
), byte_order
);
7617 /* If PC is in a MIPS16 call or return stub, return the address of the
7618 target PC, which is either the callee or the caller. There are several
7619 cases which must be handled:
7621 * If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7622 and the target PC is in $31 ($ra).
7623 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7624 and the target PC is in $2.
7625 * If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7626 i.e. before the JALR instruction, this is effectively a call stub
7627 and the target PC is in $2. Otherwise this is effectively
7628 a return stub and the target PC is in $18.
7629 * If the PC is at the start of __call_stub_fp_*, i.e. before the
7630 JAL or JALR instruction, this is effectively a call stub and the
7631 target PC is buried in the instruction stream. Otherwise this
7632 is effectively a return stub and the target PC is in $18.
7633 * If the PC is in __call_stub_* or in __fn_stub_*, this is a call
7634 stub and the target PC is buried in the instruction stream.
7636 See the source code for the stubs in gcc/config/mips/mips16.S, or the
7637 stub builder in gcc/config/mips/mips.c (mips16_build_call_stub) for the
7641 mips_skip_mips16_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7643 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7644 CORE_ADDR start_addr
;
7648 /* Find the starting address and name of the function containing the PC. */
7649 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
7652 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7653 and the target PC is in $31 ($ra). */
7654 prefixlen
= strlen (mips_str_mips16_ret_stub
);
7655 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
7656 && mips_is_stub_mode (name
+ prefixlen
)
7657 && name
[prefixlen
+ 2] == '\0')
7658 return get_frame_register_signed
7659 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
7661 /* If the PC is in __mips16_call_stub_*, this is one of the call
7662 call/return stubs. */
7663 prefixlen
= strlen (mips_str_mips16_call_stub
);
7664 if (strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0)
7666 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7667 and the target PC is in $2. */
7668 if (mips_is_stub_suffix (name
+ prefixlen
, 0))
7669 return get_frame_register_signed
7670 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
7672 /* If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7673 i.e. before the JALR instruction, this is effectively a call stub
7674 and the target PC is in $2. Otherwise this is effectively
7675 a return stub and the target PC is in $18. */
7676 else if (mips_is_stub_mode (name
+ prefixlen
)
7677 && name
[prefixlen
+ 2] == '_'
7678 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 0))
7680 if (pc
== start_addr
)
7681 /* This is the 'call' part of a call stub. The return
7682 address is in $2. */
7683 return get_frame_register_signed
7684 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
7686 /* This is the 'return' part of a call stub. The return
7687 address is in $18. */
7688 return get_frame_register_signed
7689 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
7692 return 0; /* Not a stub. */
7695 /* If the PC is in __call_stub_* or __fn_stub*, this is one of the
7696 compiler-generated call or call/return stubs. */
7697 if (strncmp (name
, mips_str_fn_stub
, strlen (mips_str_fn_stub
)) == 0
7698 || strncmp (name
, mips_str_call_stub
, strlen (mips_str_call_stub
)) == 0)
7700 if (pc
== start_addr
)
7701 /* This is the 'call' part of a call stub. Call this helper
7702 to scan through this code for interesting instructions
7703 and determine the final PC. */
7704 return mips_get_mips16_fn_stub_pc (frame
, pc
);
7706 /* This is the 'return' part of a call stub. The return address
7708 return get_frame_register_signed
7709 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
7712 return 0; /* Not a stub. */
7715 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
7716 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
7719 mips_in_return_stub (struct gdbarch
*gdbarch
, CORE_ADDR pc
, const char *name
)
7721 CORE_ADDR start_addr
;
7724 /* Find the starting address of the function containing the PC. */
7725 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
7728 /* If the PC is in __mips16_call_stub_{s,d}{f,c}_{0..10} but not at
7729 the start, i.e. after the JALR instruction, this is effectively
7731 prefixlen
= strlen (mips_str_mips16_call_stub
);
7732 if (pc
!= start_addr
7733 && strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0
7734 && mips_is_stub_mode (name
+ prefixlen
)
7735 && name
[prefixlen
+ 2] == '_'
7736 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 1))
7739 /* If the PC is in __call_stub_fp_* but not at the start, i.e. after
7740 the JAL or JALR instruction, this is effectively a return stub. */
7741 prefixlen
= strlen (mips_str_call_fp_stub
);
7742 if (pc
!= start_addr
7743 && strncmp (name
, mips_str_call_fp_stub
, prefixlen
) == 0)
7746 /* Consume the .pic. prefix of any PIC stub, this function must return
7747 true when the PC is in a PIC stub of a __mips16_ret_{d,s}{f,c} stub
7748 or the call stub path will trigger in handle_inferior_event causing
7750 prefixlen
= strlen (mips_str_pic
);
7751 if (strncmp (name
, mips_str_pic
, prefixlen
) == 0)
7754 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub. */
7755 prefixlen
= strlen (mips_str_mips16_ret_stub
);
7756 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
7757 && mips_is_stub_mode (name
+ prefixlen
)
7758 && name
[prefixlen
+ 2] == '\0')
7761 return 0; /* Not a stub. */
7764 /* If the current PC is the start of a non-PIC-to-PIC stub, return the
7765 PC of the stub target. The stub just loads $t9 and jumps to it,
7766 so that $t9 has the correct value at function entry. */
7769 mips_skip_pic_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7771 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7772 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7773 struct bound_minimal_symbol msym
;
7775 gdb_byte stub_code
[16];
7776 int32_t stub_words
[4];
7778 /* The stub for foo is named ".pic.foo", and is either two
7779 instructions inserted before foo or a three instruction sequence
7780 which jumps to foo. */
7781 msym
= lookup_minimal_symbol_by_pc (pc
);
7782 if (msym
.minsym
== NULL
7783 || BMSYMBOL_VALUE_ADDRESS (msym
) != pc
7784 || MSYMBOL_LINKAGE_NAME (msym
.minsym
) == NULL
7785 || strncmp (MSYMBOL_LINKAGE_NAME (msym
.minsym
), ".pic.", 5) != 0)
7788 /* A two-instruction header. */
7789 if (MSYMBOL_SIZE (msym
.minsym
) == 8)
7792 /* A three-instruction (plus delay slot) trampoline. */
7793 if (MSYMBOL_SIZE (msym
.minsym
) == 16)
7795 if (target_read_memory (pc
, stub_code
, 16) != 0)
7797 for (i
= 0; i
< 4; i
++)
7798 stub_words
[i
] = extract_unsigned_integer (stub_code
+ i
* 4,
7801 /* A stub contains these instructions:
7804 addiu t9, t9, %lo(target)
7807 This works even for N64, since stubs are only generated with
7809 if ((stub_words
[0] & 0xffff0000U
) == 0x3c190000
7810 && (stub_words
[1] & 0xfc000000U
) == 0x08000000
7811 && (stub_words
[2] & 0xffff0000U
) == 0x27390000
7812 && stub_words
[3] == 0x00000000)
7813 return ((((stub_words
[0] & 0x0000ffff) << 16)
7814 + (stub_words
[2] & 0x0000ffff)) ^ 0x8000) - 0x8000;
7817 /* Not a recognized stub. */
7822 mips_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7824 CORE_ADDR requested_pc
= pc
;
7825 CORE_ADDR target_pc
;
7832 new_pc
= mips_skip_mips16_trampoline_code (frame
, pc
);
7836 if (is_compact_addr (pc
))
7837 pc
= unmake_compact_addr (pc
);
7840 new_pc
= find_solib_trampoline_target (frame
, pc
);
7844 if (is_compact_addr (pc
))
7845 pc
= unmake_compact_addr (pc
);
7848 new_pc
= mips_skip_pic_trampoline_code (frame
, pc
);
7852 if (is_compact_addr (pc
))
7853 pc
= unmake_compact_addr (pc
);
7856 while (pc
!= target_pc
);
7858 return pc
!= requested_pc
? pc
: 0;
7861 /* Convert a dbx stab register number (from `r' declaration) to a GDB
7862 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7865 mips_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
7868 if (num
>= 0 && num
< 32)
7870 else if (num
>= 38 && num
< 70)
7871 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 38;
7873 regnum
= mips_regnum (gdbarch
)->hi
;
7875 regnum
= mips_regnum (gdbarch
)->lo
;
7876 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 72 && num
< 78)
7877 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 72;
7879 /* This will hopefully (eventually) provoke a warning. Should
7880 we be calling complaint() here? */
7881 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
7882 return gdbarch_num_regs (gdbarch
) + regnum
;
7886 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
7887 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7890 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
7893 if (num
>= 0 && num
< 32)
7895 else if (num
>= 32 && num
< 64)
7896 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 32;
7898 regnum
= mips_regnum (gdbarch
)->hi
;
7900 regnum
= mips_regnum (gdbarch
)->lo
;
7901 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 66 && num
< 72)
7902 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 66;
7904 /* This will hopefully (eventually) provoke a warning. Should we
7905 be calling complaint() here? */
7906 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
7907 return gdbarch_num_regs (gdbarch
) + regnum
;
7911 mips_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
7913 /* Only makes sense to supply raw registers. */
7914 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
));
7915 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
7916 decide if it is valid. Should instead define a standard sim/gdb
7917 register numbering scheme. */
7918 if (gdbarch_register_name (gdbarch
,
7919 gdbarch_num_regs (gdbarch
) + regnum
) != NULL
7920 && gdbarch_register_name (gdbarch
,
7921 gdbarch_num_regs (gdbarch
)
7922 + regnum
)[0] != '\0')
7925 return LEGACY_SIM_REGNO_IGNORE
;
7929 /* Convert an integer into an address. Extracting the value signed
7930 guarantees a correctly sign extended address. */
7933 mips_integer_to_address (struct gdbarch
*gdbarch
,
7934 struct type
*type
, const gdb_byte
*buf
)
7936 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7937 return extract_signed_integer (buf
, TYPE_LENGTH (type
), byte_order
);
7940 /* Dummy virtual frame pointer method. This is no more or less accurate
7941 than most other architectures; we just need to be explicit about it,
7942 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
7943 an assertion failure. */
7946 mips_virtual_frame_pointer (struct gdbarch
*gdbarch
,
7947 CORE_ADDR pc
, int *reg
, LONGEST
*offset
)
7949 *reg
= MIPS_SP_REGNUM
;
7954 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
7956 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
7957 const char *name
= bfd_get_section_name (abfd
, sect
);
7959 if (*abip
!= MIPS_ABI_UNKNOWN
)
7962 if (strncmp (name
, ".mdebug.", 8) != 0)
7965 if (strcmp (name
, ".mdebug.abi32") == 0)
7966 *abip
= MIPS_ABI_O32
;
7967 else if (strcmp (name
, ".mdebug.abiN32") == 0)
7968 *abip
= MIPS_ABI_N32
;
7969 else if (strcmp (name
, ".mdebug.abi64") == 0)
7970 *abip
= MIPS_ABI_N64
;
7971 else if (strcmp (name
, ".mdebug.abiO64") == 0)
7972 *abip
= MIPS_ABI_O64
;
7973 else if (strcmp (name
, ".mdebug.eabi32") == 0)
7974 *abip
= MIPS_ABI_EABI32
;
7975 else if (strcmp (name
, ".mdebug.eabi64") == 0)
7976 *abip
= MIPS_ABI_EABI64
;
7978 warning (_("unsupported ABI %s."), name
+ 8);
7982 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
7984 int *lbp
= (int *) obj
;
7985 const char *name
= bfd_get_section_name (abfd
, sect
);
7987 if (strncmp (name
, ".gcc_compiled_long32", 20) == 0)
7989 else if (strncmp (name
, ".gcc_compiled_long64", 20) == 0)
7991 else if (strncmp (name
, ".gcc_compiled_long", 18) == 0)
7992 warning (_("unrecognized .gcc_compiled_longXX"));
7995 static enum mips_abi
7996 global_mips_abi (void)
8000 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
8001 if (mips_abi_strings
[i
] == mips_abi_string
)
8002 return (enum mips_abi
) i
;
8004 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
8007 /* Return the default compressed instruction set, either of MIPS16
8008 or microMIPS, selected when none could have been determined from
8009 the ELF header of the binary being executed (or no binary has been
8012 static enum mips_isa
8013 global_mips_compression (void)
8017 for (i
= 0; mips_compression_strings
[i
] != NULL
; i
++)
8018 if (mips_compression_strings
[i
] == mips_compression_string
)
8019 return (enum mips_isa
) i
;
8021 internal_error (__FILE__
, __LINE__
, _("unknown compressed ISA string"));
8025 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
8027 /* If the size matches the set of 32-bit or 64-bit integer registers,
8028 assume that's what we've got. */
8029 register_remote_g_packet_guess (gdbarch
, 38 * 4, mips_tdesc_gp32
);
8030 register_remote_g_packet_guess (gdbarch
, 38 * 8, mips_tdesc_gp64
);
8032 /* If the size matches the full set of registers GDB traditionally
8033 knows about, including floating point, for either 32-bit or
8034 64-bit, assume that's what we've got. */
8035 register_remote_g_packet_guess (gdbarch
, 90 * 4, mips_tdesc_gp32
);
8036 register_remote_g_packet_guess (gdbarch
, 90 * 8, mips_tdesc_gp64
);
8038 /* Otherwise we don't have a useful guess. */
8041 static struct value
*
8042 value_of_mips_user_reg (struct frame_info
*frame
, const void *baton
)
8044 const int *reg_p
= baton
;
8045 return value_of_register (*reg_p
, frame
);
8048 static struct gdbarch
*
8049 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
8051 struct gdbarch
*gdbarch
;
8052 struct gdbarch_tdep
*tdep
;
8054 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
8056 enum mips_fpu_type fpu_type
;
8057 struct tdesc_arch_data
*tdesc_data
= NULL
;
8058 int elf_fpu_type
= Val_GNU_MIPS_ABI_FP_ANY
;
8059 const char **reg_names
;
8060 struct mips_regnum mips_regnum
, *regnum
;
8061 enum mips_isa mips_isa
;
8065 /* Fill in the OS dependent register numbers and names. */
8066 if (info
.osabi
== GDB_OSABI_IRIX
)
8068 mips_regnum
.fp0
= 32;
8069 mips_regnum
.pc
= 64;
8070 mips_regnum
.cause
= 65;
8071 mips_regnum
.badvaddr
= 66;
8072 mips_regnum
.hi
= 67;
8073 mips_regnum
.lo
= 68;
8074 mips_regnum
.fp_control_status
= 69;
8075 mips_regnum
.fp_implementation_revision
= 70;
8076 mips_regnum
.dspacc
= dspacc
= -1;
8077 mips_regnum
.dspctl
= dspctl
= -1;
8079 reg_names
= mips_irix_reg_names
;
8081 else if (info
.osabi
== GDB_OSABI_LINUX
)
8083 mips_regnum
.fp0
= 38;
8084 mips_regnum
.pc
= 37;
8085 mips_regnum
.cause
= 36;
8086 mips_regnum
.badvaddr
= 35;
8087 mips_regnum
.hi
= 34;
8088 mips_regnum
.lo
= 33;
8089 mips_regnum
.fp_control_status
= 70;
8090 mips_regnum
.fp_implementation_revision
= 71;
8091 mips_regnum
.dspacc
= -1;
8092 mips_regnum
.dspctl
= -1;
8096 reg_names
= mips_linux_reg_names
;
8100 mips_regnum
.lo
= MIPS_EMBED_LO_REGNUM
;
8101 mips_regnum
.hi
= MIPS_EMBED_HI_REGNUM
;
8102 mips_regnum
.badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
8103 mips_regnum
.cause
= MIPS_EMBED_CAUSE_REGNUM
;
8104 mips_regnum
.pc
= MIPS_EMBED_PC_REGNUM
;
8105 mips_regnum
.fp0
= MIPS_EMBED_FP0_REGNUM
;
8106 mips_regnum
.fp_control_status
= 70;
8107 mips_regnum
.fp_implementation_revision
= 71;
8108 mips_regnum
.dspacc
= dspacc
= -1;
8109 mips_regnum
.dspctl
= dspctl
= -1;
8110 num_regs
= MIPS_LAST_EMBED_REGNUM
+ 1;
8111 if (info
.bfd_arch_info
!= NULL
8112 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
8113 reg_names
= mips_tx39_reg_names
;
8115 reg_names
= mips_generic_reg_names
;
8118 /* Check any target description for validity. */
8119 if (tdesc_has_registers (info
.target_desc
))
8121 static const char *const mips_gprs
[] = {
8122 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
8123 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
8124 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
8125 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
8127 static const char *const mips_fprs
[] = {
8128 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
8129 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
8130 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
8131 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
8134 const struct tdesc_feature
*feature
;
8137 feature
= tdesc_find_feature (info
.target_desc
,
8138 "org.gnu.gdb.mips.cpu");
8139 if (feature
== NULL
)
8142 tdesc_data
= tdesc_data_alloc ();
8145 for (i
= MIPS_ZERO_REGNUM
; i
<= MIPS_RA_REGNUM
; i
++)
8146 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
8150 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8151 mips_regnum
.lo
, "lo");
8152 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8153 mips_regnum
.hi
, "hi");
8154 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8155 mips_regnum
.pc
, "pc");
8159 tdesc_data_cleanup (tdesc_data
);
8163 feature
= tdesc_find_feature (info
.target_desc
,
8164 "org.gnu.gdb.mips.cp0");
8165 if (feature
== NULL
)
8167 tdesc_data_cleanup (tdesc_data
);
8172 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8173 mips_regnum
.badvaddr
, "badvaddr");
8174 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8175 MIPS_PS_REGNUM
, "status");
8176 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8177 mips_regnum
.cause
, "cause");
8181 tdesc_data_cleanup (tdesc_data
);
8185 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
8186 backend is not prepared for that, though. */
8187 feature
= tdesc_find_feature (info
.target_desc
,
8188 "org.gnu.gdb.mips.fpu");
8189 if (feature
== NULL
)
8191 tdesc_data_cleanup (tdesc_data
);
8196 for (i
= 0; i
< 32; i
++)
8197 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8198 i
+ mips_regnum
.fp0
, mips_fprs
[i
]);
8200 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8201 mips_regnum
.fp_control_status
,
8204 &= tdesc_numbered_register (feature
, tdesc_data
,
8205 mips_regnum
.fp_implementation_revision
,
8210 tdesc_data_cleanup (tdesc_data
);
8216 feature
= tdesc_find_feature (info
.target_desc
,
8217 "org.gnu.gdb.mips.dsp");
8218 /* The DSP registers are optional; it's OK if they are absent. */
8219 if (feature
!= NULL
)
8223 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8224 dspacc
+ i
++, "hi1");
8225 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8226 dspacc
+ i
++, "lo1");
8227 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8228 dspacc
+ i
++, "hi2");
8229 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8230 dspacc
+ i
++, "lo2");
8231 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8232 dspacc
+ i
++, "hi3");
8233 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8234 dspacc
+ i
++, "lo3");
8236 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8241 tdesc_data_cleanup (tdesc_data
);
8245 mips_regnum
.dspacc
= dspacc
;
8246 mips_regnum
.dspctl
= dspctl
;
8250 /* It would be nice to detect an attempt to use a 64-bit ABI
8251 when only 32-bit registers are provided. */
8255 /* First of all, extract the elf_flags, if available. */
8256 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
8257 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
8258 else if (arches
!= NULL
)
8259 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
8263 fprintf_unfiltered (gdb_stdlog
,
8264 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
8266 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
8267 switch ((elf_flags
& EF_MIPS_ABI
))
8269 case E_MIPS_ABI_O32
:
8270 found_abi
= MIPS_ABI_O32
;
8272 case E_MIPS_ABI_O64
:
8273 found_abi
= MIPS_ABI_O64
;
8275 case E_MIPS_ABI_EABI32
:
8276 found_abi
= MIPS_ABI_EABI32
;
8278 case E_MIPS_ABI_EABI64
:
8279 found_abi
= MIPS_ABI_EABI64
;
8282 if ((elf_flags
& EF_MIPS_ABI2
))
8283 found_abi
= MIPS_ABI_N32
;
8285 found_abi
= MIPS_ABI_UNKNOWN
;
8289 /* GCC creates a pseudo-section whose name describes the ABI. */
8290 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
8291 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
8293 /* If we have no useful BFD information, use the ABI from the last
8294 MIPS architecture (if there is one). */
8295 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
8296 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
8298 /* Try the architecture for any hint of the correct ABI. */
8299 if (found_abi
== MIPS_ABI_UNKNOWN
8300 && info
.bfd_arch_info
!= NULL
8301 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
8303 switch (info
.bfd_arch_info
->mach
)
8305 case bfd_mach_mips3900
:
8306 found_abi
= MIPS_ABI_EABI32
;
8308 case bfd_mach_mips4100
:
8309 case bfd_mach_mips5000
:
8310 found_abi
= MIPS_ABI_EABI64
;
8312 case bfd_mach_mips8000
:
8313 case bfd_mach_mips10000
:
8314 /* On Irix, ELF64 executables use the N64 ABI. The
8315 pseudo-sections which describe the ABI aren't present
8316 on IRIX. (Even for executables created by gcc.) */
8317 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
8318 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
8319 found_abi
= MIPS_ABI_N64
;
8321 found_abi
= MIPS_ABI_N32
;
8326 /* Default 64-bit objects to N64 instead of O32. */
8327 if (found_abi
== MIPS_ABI_UNKNOWN
8328 && info
.abfd
!= NULL
8329 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
8330 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
8331 found_abi
= MIPS_ABI_N64
;
8334 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
8337 /* What has the user specified from the command line? */
8338 wanted_abi
= global_mips_abi ();
8340 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
8343 /* Now that we have found what the ABI for this binary would be,
8344 check whether the user is overriding it. */
8345 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
8346 mips_abi
= wanted_abi
;
8347 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
8348 mips_abi
= found_abi
;
8350 mips_abi
= MIPS_ABI_O32
;
8352 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
8355 /* Determine the default compressed ISA. */
8356 if ((elf_flags
& EF_MIPS_ARCH_ASE_MICROMIPS
) != 0
8357 && (elf_flags
& EF_MIPS_ARCH_ASE_M16
) == 0)
8358 mips_isa
= ISA_MICROMIPS
;
8359 else if ((elf_flags
& EF_MIPS_ARCH_ASE_M16
) != 0
8360 && (elf_flags
& EF_MIPS_ARCH_ASE_MICROMIPS
) == 0)
8361 mips_isa
= ISA_MIPS16
;
8363 mips_isa
= global_mips_compression ();
8364 mips_compression_string
= mips_compression_strings
[mips_isa
];
8366 /* Also used when doing an architecture lookup. */
8368 fprintf_unfiltered (gdb_stdlog
,
8369 "mips_gdbarch_init: "
8370 "mips64_transfers_32bit_regs_p = %d\n",
8371 mips64_transfers_32bit_regs_p
);
8373 /* Determine the MIPS FPU type. */
8376 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
8377 elf_fpu_type
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
8378 Tag_GNU_MIPS_ABI_FP
);
8379 #endif /* HAVE_ELF */
8381 if (!mips_fpu_type_auto
)
8382 fpu_type
= mips_fpu_type
;
8383 else if (elf_fpu_type
!= Val_GNU_MIPS_ABI_FP_ANY
)
8385 switch (elf_fpu_type
)
8387 case Val_GNU_MIPS_ABI_FP_DOUBLE
:
8388 fpu_type
= MIPS_FPU_DOUBLE
;
8390 case Val_GNU_MIPS_ABI_FP_SINGLE
:
8391 fpu_type
= MIPS_FPU_SINGLE
;
8393 case Val_GNU_MIPS_ABI_FP_SOFT
:
8395 /* Soft float or unknown. */
8396 fpu_type
= MIPS_FPU_NONE
;
8400 else if (info
.bfd_arch_info
!= NULL
8401 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
8402 switch (info
.bfd_arch_info
->mach
)
8404 case bfd_mach_mips3900
:
8405 case bfd_mach_mips4100
:
8406 case bfd_mach_mips4111
:
8407 case bfd_mach_mips4120
:
8408 fpu_type
= MIPS_FPU_NONE
;
8410 case bfd_mach_mips4650
:
8411 fpu_type
= MIPS_FPU_SINGLE
;
8414 fpu_type
= MIPS_FPU_DOUBLE
;
8417 else if (arches
!= NULL
)
8418 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
8420 fpu_type
= MIPS_FPU_DOUBLE
;
8422 fprintf_unfiltered (gdb_stdlog
,
8423 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
8425 /* Check for blatant incompatibilities. */
8427 /* If we have only 32-bit registers, then we can't debug a 64-bit
8429 if (info
.target_desc
8430 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
8431 && mips_abi
!= MIPS_ABI_EABI32
8432 && mips_abi
!= MIPS_ABI_O32
)
8434 if (tdesc_data
!= NULL
)
8435 tdesc_data_cleanup (tdesc_data
);
8439 /* Try to find a pre-existing architecture. */
8440 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
8442 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
8444 /* MIPS needs to be pedantic about which ABI and the compressed
8445 ISA variation the object is using. */
8446 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
8448 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
8450 if (gdbarch_tdep (arches
->gdbarch
)->mips_isa
!= mips_isa
)
8452 /* Need to be pedantic about which register virtual size is
8454 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
8455 != mips64_transfers_32bit_regs_p
)
8457 /* Be pedantic about which FPU is selected. */
8458 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
8461 if (tdesc_data
!= NULL
)
8462 tdesc_data_cleanup (tdesc_data
);
8463 return arches
->gdbarch
;
8466 /* Need a new architecture. Fill in a target specific vector. */
8467 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
8468 gdbarch
= gdbarch_alloc (&info
, tdep
);
8469 tdep
->elf_flags
= elf_flags
;
8470 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
8471 tdep
->found_abi
= found_abi
;
8472 tdep
->mips_abi
= mips_abi
;
8473 tdep
->mips_isa
= mips_isa
;
8474 tdep
->mips_fpu_type
= fpu_type
;
8475 tdep
->register_size_valid_p
= 0;
8476 tdep
->register_size
= 0;
8478 if (info
.target_desc
)
8480 /* Some useful properties can be inferred from the target. */
8481 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
8483 tdep
->register_size_valid_p
= 1;
8484 tdep
->register_size
= 4;
8486 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
8488 tdep
->register_size_valid_p
= 1;
8489 tdep
->register_size
= 8;
8493 /* Initially set everything according to the default ABI/ISA. */
8494 set_gdbarch_short_bit (gdbarch
, 16);
8495 set_gdbarch_int_bit (gdbarch
, 32);
8496 set_gdbarch_float_bit (gdbarch
, 32);
8497 set_gdbarch_double_bit (gdbarch
, 64);
8498 set_gdbarch_long_double_bit (gdbarch
, 64);
8499 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
8500 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
8501 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
8503 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
8504 mips_ax_pseudo_register_collect
);
8505 set_gdbarch_ax_pseudo_register_push_stack
8506 (gdbarch
, mips_ax_pseudo_register_push_stack
);
8508 set_gdbarch_elf_make_msymbol_special (gdbarch
,
8509 mips_elf_make_msymbol_special
);
8511 regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
, struct mips_regnum
);
8512 *regnum
= mips_regnum
;
8513 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
8514 set_gdbarch_num_regs (gdbarch
, num_regs
);
8515 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
8516 set_gdbarch_register_name (gdbarch
, mips_register_name
);
8517 set_gdbarch_virtual_frame_pointer (gdbarch
, mips_virtual_frame_pointer
);
8518 tdep
->mips_processor_reg_names
= reg_names
;
8519 tdep
->regnum
= regnum
;
8524 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
8525 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
8526 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
8527 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
8528 tdep
->default_mask_address_p
= 0;
8529 set_gdbarch_long_bit (gdbarch
, 32);
8530 set_gdbarch_ptr_bit (gdbarch
, 32);
8531 set_gdbarch_long_long_bit (gdbarch
, 64);
8534 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
8535 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
8536 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
8537 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
8538 tdep
->default_mask_address_p
= 0;
8539 set_gdbarch_long_bit (gdbarch
, 32);
8540 set_gdbarch_ptr_bit (gdbarch
, 32);
8541 set_gdbarch_long_long_bit (gdbarch
, 64);
8543 case MIPS_ABI_EABI32
:
8544 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
8545 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
8546 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8547 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8548 tdep
->default_mask_address_p
= 0;
8549 set_gdbarch_long_bit (gdbarch
, 32);
8550 set_gdbarch_ptr_bit (gdbarch
, 32);
8551 set_gdbarch_long_long_bit (gdbarch
, 64);
8553 case MIPS_ABI_EABI64
:
8554 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
8555 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
8556 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8557 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8558 tdep
->default_mask_address_p
= 0;
8559 set_gdbarch_long_bit (gdbarch
, 64);
8560 set_gdbarch_ptr_bit (gdbarch
, 64);
8561 set_gdbarch_long_long_bit (gdbarch
, 64);
8564 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
8565 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
8566 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8567 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8568 tdep
->default_mask_address_p
= 0;
8569 set_gdbarch_long_bit (gdbarch
, 32);
8570 set_gdbarch_ptr_bit (gdbarch
, 32);
8571 set_gdbarch_long_long_bit (gdbarch
, 64);
8572 set_gdbarch_long_double_bit (gdbarch
, 128);
8573 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
8576 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
8577 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
8578 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8579 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8580 tdep
->default_mask_address_p
= 0;
8581 set_gdbarch_long_bit (gdbarch
, 64);
8582 set_gdbarch_ptr_bit (gdbarch
, 64);
8583 set_gdbarch_long_long_bit (gdbarch
, 64);
8584 set_gdbarch_long_double_bit (gdbarch
, 128);
8585 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
8588 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
8591 /* GCC creates a pseudo-section whose name specifies the size of
8592 longs, since -mlong32 or -mlong64 may be used independent of
8593 other options. How those options affect pointer sizes is ABI and
8594 architecture dependent, so use them to override the default sizes
8595 set by the ABI. This table shows the relationship between ABI,
8596 -mlongXX, and size of pointers:
8598 ABI -mlongXX ptr bits
8599 --- -------- --------
8613 Note that for o32 and eabi32, pointers are always 32 bits
8614 regardless of any -mlongXX option. For all others, pointers and
8615 longs are the same, as set by -mlongXX or set by defaults. */
8617 if (info
.abfd
!= NULL
)
8621 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
8624 set_gdbarch_long_bit (gdbarch
, long_bit
);
8628 case MIPS_ABI_EABI32
:
8633 case MIPS_ABI_EABI64
:
8634 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
8637 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
8642 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
8643 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
8646 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
8647 flag in object files because to do so would make it impossible to
8648 link with libraries compiled without "-gp32". This is
8649 unnecessarily restrictive.
8651 We could solve this problem by adding "-gp32" multilibs to gcc,
8652 but to set this flag before gcc is built with such multilibs will
8653 break too many systems.''
8655 But even more unhelpfully, the default linker output target for
8656 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
8657 for 64-bit programs - you need to change the ABI to change this,
8658 and not all gcc targets support that currently. Therefore using
8659 this flag to detect 32-bit mode would do the wrong thing given
8660 the current gcc - it would make GDB treat these 64-bit programs
8661 as 32-bit programs by default. */
8663 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
8664 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
8666 /* Add/remove bits from an address. The MIPS needs be careful to
8667 ensure that all 32 bit addresses are sign extended to 64 bits. */
8668 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
8670 /* Unwind the frame. */
8671 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
8672 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
8673 set_gdbarch_dummy_id (gdbarch
, mips_dummy_id
);
8675 /* Map debug register numbers onto internal register numbers. */
8676 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
8677 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
8678 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
8679 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
8680 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
8681 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
8683 /* MIPS version of CALL_DUMMY. */
8685 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
8686 set_gdbarch_push_dummy_code (gdbarch
, mips_push_dummy_code
);
8687 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
8689 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
8690 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
8691 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
8693 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
8694 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
8695 set_gdbarch_remote_breakpoint_from_pc (gdbarch
,
8696 mips_remote_breakpoint_from_pc
);
8697 set_gdbarch_adjust_breakpoint_address (gdbarch
,
8698 mips_adjust_breakpoint_address
);
8700 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
8702 set_gdbarch_in_function_epilogue_p (gdbarch
, mips_in_function_epilogue_p
);
8704 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
8705 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
8706 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
8708 set_gdbarch_register_type (gdbarch
, mips_register_type
);
8710 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
8712 if (mips_abi
== MIPS_ABI_N32
)
8713 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n32
);
8714 else if (mips_abi
== MIPS_ABI_N64
)
8715 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n64
);
8717 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
8719 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint,
8720 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint
8721 need to all be folded into the target vector. Since they are
8722 being used as guards for target_stopped_by_watchpoint, why not have
8723 target_stopped_by_watchpoint return the type of watchpoint that the code
8725 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
8727 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
8729 /* NOTE drow/2012-04-25: We overload the core solib trampoline code
8730 to support MIPS16. This is a bad thing. Make sure not to do it
8731 if we have an OS ABI that actually supports shared libraries, since
8732 shared library support is more important. If we have an OS someday
8733 that supports both shared libraries and MIPS16, we'll have to find
8734 a better place for these.
8735 macro/2012-04-25: But that applies to return trampolines only and
8736 currently no MIPS OS ABI uses shared libraries that have them. */
8737 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
8739 set_gdbarch_single_step_through_delay (gdbarch
,
8740 mips_single_step_through_delay
);
8742 /* Virtual tables. */
8743 set_gdbarch_vbit_in_delta (gdbarch
, 1);
8745 mips_register_g_packet_guesses (gdbarch
);
8747 /* Hook in OS ABI-specific overrides, if they have been registered. */
8748 info
.tdep_info
= (void *) tdesc_data
;
8749 gdbarch_init_osabi (info
, gdbarch
);
8751 /* The hook may have adjusted num_regs, fetch the final value and
8752 set pc_regnum and sp_regnum now that it has been fixed. */
8753 num_regs
= gdbarch_num_regs (gdbarch
);
8754 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
8755 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
8757 /* Unwind the frame. */
8758 dwarf2_append_unwinders (gdbarch
);
8759 frame_unwind_append_unwinder (gdbarch
, &mips_stub_frame_unwind
);
8760 frame_unwind_append_unwinder (gdbarch
, &mips_insn16_frame_unwind
);
8761 frame_unwind_append_unwinder (gdbarch
, &mips_micro_frame_unwind
);
8762 frame_unwind_append_unwinder (gdbarch
, &mips_insn32_frame_unwind
);
8763 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
8764 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
8765 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
8766 frame_base_append_sniffer (gdbarch
, mips_micro_frame_base_sniffer
);
8767 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
8771 set_tdesc_pseudo_register_type (gdbarch
, mips_pseudo_register_type
);
8772 tdesc_use_registers (gdbarch
, info
.target_desc
, tdesc_data
);
8774 /* Override the normal target description methods to handle our
8775 dual real and pseudo registers. */
8776 set_gdbarch_register_name (gdbarch
, mips_register_name
);
8777 set_gdbarch_register_reggroup_p (gdbarch
,
8778 mips_tdesc_register_reggroup_p
);
8780 num_regs
= gdbarch_num_regs (gdbarch
);
8781 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
8782 set_gdbarch_pc_regnum (gdbarch
, tdep
->regnum
->pc
+ num_regs
);
8783 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
8786 /* Add ABI-specific aliases for the registers. */
8787 if (mips_abi
== MIPS_ABI_N32
|| mips_abi
== MIPS_ABI_N64
)
8788 for (i
= 0; i
< ARRAY_SIZE (mips_n32_n64_aliases
); i
++)
8789 user_reg_add (gdbarch
, mips_n32_n64_aliases
[i
].name
,
8790 value_of_mips_user_reg
, &mips_n32_n64_aliases
[i
].regnum
);
8792 for (i
= 0; i
< ARRAY_SIZE (mips_o32_aliases
); i
++)
8793 user_reg_add (gdbarch
, mips_o32_aliases
[i
].name
,
8794 value_of_mips_user_reg
, &mips_o32_aliases
[i
].regnum
);
8796 /* Add some other standard aliases. */
8797 for (i
= 0; i
< ARRAY_SIZE (mips_register_aliases
); i
++)
8798 user_reg_add (gdbarch
, mips_register_aliases
[i
].name
,
8799 value_of_mips_user_reg
, &mips_register_aliases
[i
].regnum
);
8801 for (i
= 0; i
< ARRAY_SIZE (mips_numeric_register_aliases
); i
++)
8802 user_reg_add (gdbarch
, mips_numeric_register_aliases
[i
].name
,
8803 value_of_mips_user_reg
,
8804 &mips_numeric_register_aliases
[i
].regnum
);
8810 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
8812 struct gdbarch_info info
;
8814 /* Force the architecture to update, and (if it's a MIPS architecture)
8815 mips_gdbarch_init will take care of the rest. */
8816 gdbarch_info_init (&info
);
8817 gdbarch_update_p (info
);
8820 /* Print out which MIPS ABI is in use. */
8823 show_mips_abi (struct ui_file
*file
,
8825 struct cmd_list_element
*ignored_cmd
,
8826 const char *ignored_value
)
8828 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_mips
)
8831 "The MIPS ABI is unknown because the current architecture "
8835 enum mips_abi global_abi
= global_mips_abi ();
8836 enum mips_abi actual_abi
= mips_abi (target_gdbarch ());
8837 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
8839 if (global_abi
== MIPS_ABI_UNKNOWN
)
8842 "The MIPS ABI is set automatically (currently \"%s\").\n",
8844 else if (global_abi
== actual_abi
)
8847 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
8851 /* Probably shouldn't happen... */
8852 fprintf_filtered (file
,
8853 "The (auto detected) MIPS ABI \"%s\" is in use "
8854 "even though the user setting was \"%s\".\n",
8855 actual_abi_str
, mips_abi_strings
[global_abi
]);
8860 /* Print out which MIPS compressed ISA encoding is used. */
8863 show_mips_compression (struct ui_file
*file
, int from_tty
,
8864 struct cmd_list_element
*c
, const char *value
)
8866 fprintf_filtered (file
, _("The compressed ISA encoding used is %s.\n"),
8871 mips_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
8873 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
8877 int ef_mips_32bitmode
;
8878 /* Determine the ISA. */
8879 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
8897 /* Determine the size of a pointer. */
8898 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
8899 fprintf_unfiltered (file
,
8900 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
8902 fprintf_unfiltered (file
,
8903 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
8905 fprintf_unfiltered (file
,
8906 "mips_dump_tdep: ef_mips_arch = %d\n",
8908 fprintf_unfiltered (file
,
8909 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
8910 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
8911 fprintf_unfiltered (file
,
8913 "mips_mask_address_p() %d (default %d)\n",
8914 mips_mask_address_p (tdep
),
8915 tdep
->default_mask_address_p
);
8917 fprintf_unfiltered (file
,
8918 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
8919 MIPS_DEFAULT_FPU_TYPE
,
8920 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
8921 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
8922 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
8924 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n",
8925 MIPS_EABI (gdbarch
));
8926 fprintf_unfiltered (file
,
8927 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
8928 MIPS_FPU_TYPE (gdbarch
),
8929 (MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_NONE
? "none"
8930 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_SINGLE
? "single"
8931 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_DOUBLE
? "double"
8935 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
8938 _initialize_mips_tdep (void)
8940 static struct cmd_list_element
*mipsfpulist
= NULL
;
8941 struct cmd_list_element
*c
;
8943 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
8944 if (MIPS_ABI_LAST
+ 1
8945 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
8946 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
8948 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
8950 mips_pdr_data
= register_objfile_data ();
8952 /* Create feature sets with the appropriate properties. The values
8953 are not important. */
8954 mips_tdesc_gp32
= allocate_target_description ();
8955 set_tdesc_property (mips_tdesc_gp32
, PROPERTY_GP32
, "");
8957 mips_tdesc_gp64
= allocate_target_description ();
8958 set_tdesc_property (mips_tdesc_gp64
, PROPERTY_GP64
, "");
8960 /* Add root prefix command for all "set mips"/"show mips" commands. */
8961 add_prefix_cmd ("mips", no_class
, set_mips_command
,
8962 _("Various MIPS specific commands."),
8963 &setmipscmdlist
, "set mips ", 0, &setlist
);
8965 add_prefix_cmd ("mips", no_class
, show_mips_command
,
8966 _("Various MIPS specific commands."),
8967 &showmipscmdlist
, "show mips ", 0, &showlist
);
8969 /* Allow the user to override the ABI. */
8970 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
8971 &mips_abi_string
, _("\
8972 Set the MIPS ABI used by this program."), _("\
8973 Show the MIPS ABI used by this program."), _("\
8974 This option can be set to one of:\n\
8975 auto - the default ABI associated with the current binary\n\
8984 &setmipscmdlist
, &showmipscmdlist
);
8986 /* Allow the user to set the ISA to assume for compressed code if ELF
8987 file flags don't tell or there is no program file selected. This
8988 setting is updated whenever unambiguous ELF file flags are interpreted,
8989 and carried over to subsequent sessions. */
8990 add_setshow_enum_cmd ("compression", class_obscure
, mips_compression_strings
,
8991 &mips_compression_string
, _("\
8992 Set the compressed ISA encoding used by MIPS code."), _("\
8993 Show the compressed ISA encoding used by MIPS code."), _("\
8994 Select the compressed ISA encoding used in functions that have no symbol\n\
8995 information available. The encoding can be set to either of:\n\
8998 and is updated automatically from ELF file flags if available."),
9000 show_mips_compression
,
9001 &setmipscmdlist
, &showmipscmdlist
);
9003 /* Let the user turn off floating point and set the fence post for
9004 heuristic_proc_start. */
9006 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
9007 _("Set use of MIPS floating-point coprocessor."),
9008 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
9009 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
9010 _("Select single-precision MIPS floating-point coprocessor."),
9012 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
9013 _("Select double-precision MIPS floating-point coprocessor."),
9015 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
9016 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
9017 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
9018 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
9019 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
9020 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
9021 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
9022 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
9023 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
9024 _("Select MIPS floating-point coprocessor automatically."),
9026 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
9027 _("Show current use of MIPS floating-point coprocessor target."),
9030 /* We really would like to have both "0" and "unlimited" work, but
9031 command.c doesn't deal with that. So make it a var_zinteger
9032 because the user can always use "999999" or some such for unlimited. */
9033 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
9034 &heuristic_fence_post
, _("\
9035 Set the distance searched for the start of a function."), _("\
9036 Show the distance searched for the start of a function."), _("\
9037 If you are debugging a stripped executable, GDB needs to search through the\n\
9038 program for the start of a function. This command sets the distance of the\n\
9039 search. The only need to set it is when debugging a stripped executable."),
9040 reinit_frame_cache_sfunc
,
9041 NULL
, /* FIXME: i18n: The distance searched for
9042 the start of a function is %s. */
9043 &setlist
, &showlist
);
9045 /* Allow the user to control whether the upper bits of 64-bit
9046 addresses should be zeroed. */
9047 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
9048 &mask_address_var
, _("\
9049 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
9050 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
9051 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\
9052 allow GDB to determine the correct value."),
9053 NULL
, show_mask_address
,
9054 &setmipscmdlist
, &showmipscmdlist
);
9056 /* Allow the user to control the size of 32 bit registers within the
9057 raw remote packet. */
9058 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
9059 &mips64_transfers_32bit_regs_p
, _("\
9060 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
9062 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
9064 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
9065 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
9066 64 bits for others. Use \"off\" to disable compatibility mode"),
9067 set_mips64_transfers_32bit_regs
,
9068 NULL
, /* FIXME: i18n: Compatibility with 64-bit
9069 MIPS target that transfers 32-bit
9070 quantities is %s. */
9071 &setlist
, &showlist
);
9073 /* Debug this files internals. */
9074 add_setshow_zuinteger_cmd ("mips", class_maintenance
,
9076 Set mips debugging."), _("\
9077 Show mips debugging."), _("\
9078 When non-zero, mips specific debugging is enabled."),
9080 NULL
, /* FIXME: i18n: Mips debugging is
9082 &setdebuglist
, &showdebuglist
);