1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
2 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996
3 Free Software Foundation, Inc.
4 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
5 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
24 #include "gdb_string.h"
37 #include "opcode/mips.h"
39 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
41 /* FIXME: Put this declaration in frame.h. */
42 extern struct obstack frame_cache_obstack
;
45 static int mips_in_lenient_prologue
PARAMS ((CORE_ADDR
, CORE_ADDR
));
48 static int gdb_print_insn_mips
PARAMS ((bfd_vma
, disassemble_info
*));
50 static void mips_print_register
PARAMS ((int, int));
52 static mips_extra_func_info_t
53 heuristic_proc_desc
PARAMS ((CORE_ADDR
, CORE_ADDR
, struct frame_info
*));
55 static CORE_ADDR heuristic_proc_start
PARAMS ((CORE_ADDR
));
57 static CORE_ADDR read_next_frame_reg
PARAMS ((struct frame_info
*, int));
59 static void mips_set_fpu_command
PARAMS ((char *, int,
60 struct cmd_list_element
*));
62 static void mips_show_fpu_command
PARAMS ((char *, int,
63 struct cmd_list_element
*));
65 void mips_set_processor_type_command
PARAMS ((char *, int));
67 int mips_set_processor_type
PARAMS ((char *));
69 static void mips_show_processor_type_command
PARAMS ((char *, int));
71 static void reinit_frame_cache_sfunc
PARAMS ((char *, int,
72 struct cmd_list_element
*));
74 static mips_extra_func_info_t
75 find_proc_desc
PARAMS ((CORE_ADDR pc
, struct frame_info
*next_frame
));
77 static CORE_ADDR after_prologue
PARAMS ((CORE_ADDR pc
,
78 mips_extra_func_info_t proc_desc
));
80 /* This value is the model of MIPS in use. It is derived from the value
81 of the PrID register. */
83 char *mips_processor_type
;
85 char *tmp_mips_processor_type
;
87 /* Some MIPS boards don't support floating point, so we permit the
88 user to turn it off. */
90 enum mips_fpu_type mips_fpu
;
92 static char *mips_fpu_string
;
94 /* A set of original names, to be used when restoring back to generic
95 registers from a specific set. */
97 char *mips_generic_reg_names
[] = REGISTER_NAMES
;
99 /* Names of IDT R3041 registers. */
101 char *mips_r3041_reg_names
[] = {
102 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
103 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
104 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
105 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
106 "sr", "lo", "hi", "bad", "cause","pc",
107 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
108 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
109 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
110 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
111 "fsr", "fir", "fp", "",
112 "", "", "bus", "ccfg", "", "", "", "",
113 "", "", "port", "cmp", "", "", "epc", "prid",
116 /* Names of IDT R3051 registers. */
118 char *mips_r3051_reg_names
[] = {
119 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
120 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
121 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
122 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
123 "sr", "lo", "hi", "bad", "cause","pc",
124 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
125 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
126 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
127 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
128 "fsr", "fir", "fp", "",
129 "inx", "rand", "elo", "", "ctxt", "", "", "",
130 "", "", "ehi", "", "", "", "epc", "prid",
133 /* Names of IDT R3081 registers. */
135 char *mips_r3081_reg_names
[] = {
136 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
137 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
138 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
139 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
140 "sr", "lo", "hi", "bad", "cause","pc",
141 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
142 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
143 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
144 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
145 "fsr", "fir", "fp", "",
146 "inx", "rand", "elo", "cfg", "ctxt", "", "", "",
147 "", "", "ehi", "", "", "", "epc", "prid",
150 /* Names of LSI 33k registers. */
152 char *mips_lsi33k_reg_names
[] = {
153 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
154 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
155 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
156 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
157 "epc", "hi", "lo", "sr", "cause","badvaddr",
158 "dcic", "bpc", "bda", "", "", "", "", "",
159 "", "", "", "", "", "", "", "",
160 "", "", "", "", "", "", "", "",
161 "", "", "", "", "", "", "", "",
163 "", "", "", "", "", "", "", "",
164 "", "", "", "", "", "", "", "",
170 } mips_processor_type_table
[] = {
171 { "generic", mips_generic_reg_names
},
172 { "r3041", mips_r3041_reg_names
},
173 { "r3051", mips_r3051_reg_names
},
174 { "r3071", mips_r3081_reg_names
},
175 { "r3081", mips_r3081_reg_names
},
176 { "lsi33k", mips_lsi33k_reg_names
},
180 /* Table to translate MIPS16 register field to actual register number. */
181 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
183 /* Heuristic_proc_start may hunt through the text section for a long
184 time across a 2400 baud serial line. Allows the user to limit this
187 static unsigned int heuristic_fence_post
= 0;
189 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
190 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
191 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
192 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
193 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
194 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
195 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
196 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
197 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
198 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
199 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
200 #define _PROC_MAGIC_ 0x0F0F0F0F
201 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
202 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
204 struct linked_proc_info
206 struct mips_extra_func_info info
;
207 struct linked_proc_info
*next
;
208 } *linked_proc_desc_table
= NULL
;
211 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
214 pc_is_mips16 (bfd_vma memaddr
)
216 struct minimal_symbol
*sym
;
218 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
219 if (IS_MIPS16_ADDR (memaddr
))
222 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
223 the high bit of the info field. Use this to decide if the function is
224 MIPS16 or normal MIPS. */
225 sym
= lookup_minimal_symbol_by_pc (memaddr
);
227 return MSYMBOL_IS_SPECIAL (sym
);
233 /* This returns the PC of the first inst after the prologue. If we can't
234 find the prologue, then return 0. */
237 after_prologue (pc
, proc_desc
)
239 mips_extra_func_info_t proc_desc
;
241 struct symtab_and_line sal
;
242 CORE_ADDR func_addr
, func_end
;
245 proc_desc
= find_proc_desc (pc
, NULL
);
249 /* If function is frameless, then we need to do it the hard way. I
250 strongly suspect that frameless always means prologueless... */
251 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
252 && PROC_FRAME_OFFSET (proc_desc
) == 0)
256 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
257 return 0; /* Unknown */
259 sal
= find_pc_line (func_addr
, 0);
261 if (sal
.end
< func_end
)
264 /* The line after the prologue is after the end of the function. In this
265 case, tell the caller to find the prologue the hard way. */
270 /* Decode a MIPS32 instruction that saves a register in the stack, and
271 set the appropriate bit in the general register mask or float register mask
272 to indicate which register is saved. This is a helper function
273 for mips_find_saved_regs. */
276 mips32_decode_reg_save (inst
, gen_mask
, float_mask
)
278 unsigned long *gen_mask
;
279 unsigned long *float_mask
;
283 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
284 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
285 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
287 /* It might be possible to use the instruction to
288 find the offset, rather than the code below which
289 is based on things being in a certain order in the
290 frame, but figuring out what the instruction's offset
291 is relative to might be a little tricky. */
292 reg
= (inst
& 0x001f0000) >> 16;
293 *gen_mask
|= (1 << reg
);
295 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
296 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
297 || (inst
& 0xffe00000) == 0xf7a00000)/* sdc1 freg,n($sp) */
300 reg
= ((inst
& 0x001f0000) >> 16);
301 *float_mask
|= (1 << reg
);
305 /* Decode a MIPS16 instruction that saves a register in the stack, and
306 set the appropriate bit in the general register or float register mask
307 to indicate which register is saved. This is a helper function
308 for mips_find_saved_regs. */
311 mips16_decode_reg_save (inst
, gen_mask
)
313 unsigned long *gen_mask
;
315 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
317 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
318 *gen_mask
|= (1 << reg
);
320 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
322 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
323 *gen_mask
|= (1 << reg
);
325 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
326 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
327 *gen_mask
|= (1 << RA_REGNUM
);
331 /* Fetch and return instruction from the specified location. If the PC
332 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
335 mips_fetch_instruction (addr
)
338 char buf
[MIPS_INSTLEN
];
342 if (pc_is_mips16 (addr
))
344 instlen
= MIPS16_INSTLEN
;
345 addr
= UNMAKE_MIPS16_ADDR (addr
);
348 instlen
= MIPS_INSTLEN
;
349 status
= read_memory_nobpt (addr
, buf
, instlen
);
351 memory_error (status
, addr
);
352 return extract_unsigned_integer (buf
, instlen
);
356 /* Guaranteed to set fci->saved_regs to some values (it never leaves it
360 mips_find_saved_regs (fci
)
361 struct frame_info
*fci
;
364 CORE_ADDR reg_position
;
365 /* r0 bit means kernel trap */
367 /* What registers have been saved? Bitmasks. */
368 unsigned long gen_mask
, float_mask
;
369 mips_extra_func_info_t proc_desc
;
372 fci
->saved_regs
= (struct frame_saved_regs
*)
373 obstack_alloc (&frame_cache_obstack
, sizeof(struct frame_saved_regs
));
374 memset (fci
->saved_regs
, 0, sizeof (struct frame_saved_regs
));
376 /* If it is the frame for sigtramp, the saved registers are located
377 in a sigcontext structure somewhere on the stack.
378 If the stack layout for sigtramp changes we might have to change these
379 constants and the companion fixup_sigtramp in mdebugread.c */
380 #ifndef SIGFRAME_BASE
381 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
382 above the sigtramp frame. */
383 #define SIGFRAME_BASE MIPS_REGSIZE
384 /* FIXME! Are these correct?? */
385 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE)
386 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE)
387 #define SIGFRAME_FPREGSAVE_OFF \
388 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE)
390 #ifndef SIGFRAME_REG_SIZE
391 /* FIXME! Is this correct?? */
392 #define SIGFRAME_REG_SIZE MIPS_REGSIZE
394 if (fci
->signal_handler_caller
)
396 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
398 reg_position
= fci
->frame
+ SIGFRAME_REGSAVE_OFF
399 + ireg
* SIGFRAME_REG_SIZE
;
400 fci
->saved_regs
->regs
[ireg
] = reg_position
;
402 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
404 reg_position
= fci
->frame
+ SIGFRAME_FPREGSAVE_OFF
405 + ireg
* SIGFRAME_REG_SIZE
;
406 fci
->saved_regs
->regs
[FP0_REGNUM
+ ireg
] = reg_position
;
408 fci
->saved_regs
->regs
[PC_REGNUM
] = fci
->frame
+ SIGFRAME_PC_OFF
;
412 proc_desc
= fci
->proc_desc
;
413 if (proc_desc
== NULL
)
414 /* I'm not sure how/whether this can happen. Normally when we can't
415 find a proc_desc, we "synthesize" one using heuristic_proc_desc
416 and set the saved_regs right away. */
419 kernel_trap
= PROC_REG_MASK(proc_desc
) & 1;
420 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK(proc_desc
);
421 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK(proc_desc
);
423 if (/* In any frame other than the innermost or a frame interrupted by
424 a signal, we assume that all registers have been saved.
425 This assumes that all register saves in a function happen before
426 the first function call. */
427 (fci
->next
== NULL
|| fci
->next
->signal_handler_caller
)
429 /* In a dummy frame we know exactly where things are saved. */
430 && !PROC_DESC_IS_DUMMY (proc_desc
)
432 /* Don't bother unless we are inside a function prologue. Outside the
433 prologue, we know where everything is. */
435 && in_prologue (fci
->pc
, PROC_LOW_ADDR (proc_desc
))
437 /* Not sure exactly what kernel_trap means, but if it means
438 the kernel saves the registers without a prologue doing it,
439 we better not examine the prologue to see whether registers
440 have been saved yet. */
443 /* We need to figure out whether the registers that the proc_desc
444 claims are saved have been saved yet. */
448 /* Bitmasks; set if we have found a save for the register. */
449 unsigned long gen_save_found
= 0;
450 unsigned long float_save_found
= 0;
453 /* If the address is odd, assume this is MIPS16 code. */
454 addr
= PROC_LOW_ADDR (proc_desc
);
455 instlen
= pc_is_mips16 (addr
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
457 /* Scan through this function's instructions preceding the current
458 PC, and look for those that save registers. */
459 while (addr
< fci
->pc
)
461 inst
= mips_fetch_instruction (addr
);
462 if (pc_is_mips16 (addr
))
463 mips16_decode_reg_save (inst
, &gen_save_found
);
465 mips32_decode_reg_save (inst
, &gen_save_found
, &float_save_found
);
468 gen_mask
= gen_save_found
;
469 float_mask
= float_save_found
;
472 /* Fill in the offsets for the registers which gen_mask says
474 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
475 for (ireg
= MIPS_NUMREGS
-1; gen_mask
; --ireg
, gen_mask
<<= 1)
476 if (gen_mask
& 0x80000000)
478 fci
->saved_regs
->regs
[ireg
] = reg_position
;
479 reg_position
-= MIPS_REGSIZE
;
482 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order
483 of that normally used by gcc. Therefore, we have to fetch the first
484 instruction of the function, and if it's an entry instruction that
485 saves $s0 or $s1, correct their saved addresses. */
486 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
488 inst
= mips_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
489 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
492 int sreg_count
= (inst
>> 6) & 3;
494 /* Check if the ra register was pushed on the stack. */
495 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
497 reg_position
-= MIPS_REGSIZE
;
499 /* Check if the s0 and s1 registers were pushed on the stack. */
500 for (reg
= 16; reg
< sreg_count
+16; reg
++)
502 fci
->saved_regs
->regs
[reg
] = reg_position
;
503 reg_position
-= MIPS_REGSIZE
;
508 /* Fill in the offsets for the registers which float_mask says
510 reg_position
= fci
->frame
+ PROC_FREG_OFFSET (proc_desc
);
512 /* The freg_offset points to where the first *double* register
513 is saved. So skip to the high-order word. */
514 if (! GDB_TARGET_IS_MIPS64
)
515 reg_position
+= MIPS_REGSIZE
;
517 /* Fill in the offsets for the float registers which float_mask says
519 for (ireg
= MIPS_NUMREGS
-1; float_mask
; --ireg
, float_mask
<<= 1)
520 if (float_mask
& 0x80000000)
522 fci
->saved_regs
->regs
[FP0_REGNUM
+ireg
] = reg_position
;
523 reg_position
-= MIPS_REGSIZE
;
526 fci
->saved_regs
->regs
[PC_REGNUM
] = fci
->saved_regs
->regs
[RA_REGNUM
];
530 read_next_frame_reg(fi
, regno
)
531 struct frame_info
*fi
;
534 for (; fi
; fi
= fi
->next
)
536 /* We have to get the saved sp from the sigcontext
537 if it is a signal handler frame. */
538 if (regno
== SP_REGNUM
&& !fi
->signal_handler_caller
)
542 if (fi
->saved_regs
== NULL
)
543 mips_find_saved_regs (fi
);
544 if (fi
->saved_regs
->regs
[regno
])
545 return read_memory_integer(fi
->saved_regs
->regs
[regno
], MIPS_REGSIZE
);
548 return read_register (regno
);
551 /* mips_addr_bits_remove - remove useless address bits */
554 mips_addr_bits_remove (addr
)
557 #if GDB_TARGET_IS_MIPS64
558 if ((addr
>> 32 == (CORE_ADDR
)0xffffffff)
559 && (strcmp (target_shortname
,"pmon")==0
560 || strcmp (target_shortname
,"ddb")==0
561 || strcmp (target_shortname
,"sim")==0))
563 /* This hack is a work-around for existing boards using PMON,
564 the simulator, and any other 64-bit targets that doesn't have
565 true 64-bit addressing. On these targets, the upper 32 bits
566 of addresses are ignored by the hardware. Thus, the PC or SP
567 are likely to have been sign extended to all 1s by instruction
568 sequences that load 32-bit addresses. For example, a typical
569 piece of code that loads an address is this:
570 lui $r2, <upper 16 bits>
571 ori $r2, <lower 16 bits>
572 But the lui sign-extends the value such that the upper 32 bits
573 may be all 1s. The workaround is simply to mask off these bits.
574 In the future, gcc may be changed to support true 64-bit
575 addressing, and this masking will have to be disabled. */
576 addr
&= (CORE_ADDR
)0xffffffff;
579 /* Even when GDB is configured for some 32-bit targets (e.g. mips-elf),
580 BFD is configured to handle 64-bit targets, so CORE_ADDR is 64 bits.
581 So we still have to mask off useless bits from addresses. */
582 addr
&= (CORE_ADDR
)0xffffffff;
589 mips_init_frame_pc_first (fromleaf
, prev
)
591 struct frame_info
*prev
;
595 pc
= ((fromleaf
) ? SAVED_PC_AFTER_CALL (prev
->next
) :
596 prev
->next
? FRAME_SAVED_PC (prev
->next
) : read_pc ());
597 tmp
= mips_skip_stub (pc
);
598 prev
->pc
= tmp
? tmp
: pc
;
603 mips_frame_saved_pc(frame
)
604 struct frame_info
*frame
;
607 mips_extra_func_info_t proc_desc
= frame
->proc_desc
;
608 /* We have to get the saved pc from the sigcontext
609 if it is a signal handler frame. */
610 int pcreg
= frame
->signal_handler_caller
? PC_REGNUM
611 : (proc_desc
? PROC_PC_REG(proc_desc
) : RA_REGNUM
);
613 if (proc_desc
&& PROC_DESC_IS_DUMMY(proc_desc
))
614 saved_pc
= read_memory_integer(frame
->frame
- MIPS_REGSIZE
, MIPS_REGSIZE
);
616 saved_pc
= read_next_frame_reg(frame
, pcreg
);
618 return ADDR_BITS_REMOVE (saved_pc
);
621 static struct mips_extra_func_info temp_proc_desc
;
622 static struct frame_saved_regs temp_saved_regs
;
624 /* This fencepost looks highly suspicious to me. Removing it also
625 seems suspicious as it could affect remote debugging across serial
629 heuristic_proc_start(pc
)
637 pc
= ADDR_BITS_REMOVE (pc
);
639 fence
= start_pc
- heuristic_fence_post
;
640 if (start_pc
== 0) return 0;
642 if (heuristic_fence_post
== UINT_MAX
643 || fence
< VM_MIN_ADDRESS
)
644 fence
= VM_MIN_ADDRESS
;
646 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
648 /* search back for previous return */
649 for (start_pc
-= instlen
; ; start_pc
-= instlen
)
650 if (start_pc
< fence
)
652 /* It's not clear to me why we reach this point when
653 stop_soon_quietly, but with this test, at least we
654 don't print out warnings for every child forked (eg, on
655 decstation). 22apr93 rich@cygnus.com. */
656 if (!stop_soon_quietly
)
658 static int blurb_printed
= 0;
660 if (fence
== VM_MIN_ADDRESS
)
661 warning("Hit beginning of text section without finding");
663 warning("Hit heuristic-fence-post without finding");
665 warning("enclosing function for address 0x%s", paddr_nz (pc
));
669 This warning occurs if you are debugging a function without any symbols\n\
670 (for example, in a stripped executable). In that case, you may wish to\n\
671 increase the size of the search with the `set heuristic-fence-post' command.\n\
673 Otherwise, you told GDB there was a function where there isn't one, or\n\
674 (more likely) you have encountered a bug in GDB.\n");
681 else if (pc_is_mips16 (start_pc
))
685 /* On MIPS16, any one of the following is likely to be the
690 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
691 inst
= mips_fetch_instruction (start_pc
);
692 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
693 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
694 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
695 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
697 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
698 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
703 else if (ABOUT_TO_RETURN(start_pc
))
705 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
710 /* skip nops (usually 1) 0 - is this */
711 while (start_pc
< pc
&& read_memory_integer (start_pc
, MIPS_INSTLEN
) == 0)
712 start_pc
+= MIPS_INSTLEN
;
717 /* Fetch the immediate value from a MIPS16 instruction.
718 If the previous instruction was an EXTEND, use it to extend
719 the upper bits of the immediate value. This is a helper function
720 for mips16_heuristic_proc_desc. */
723 mips16_get_imm (prev_inst
, inst
, nbits
, scale
, is_signed
)
724 unsigned short prev_inst
; /* previous instruction */
725 unsigned short inst
; /* current instruction */
726 int nbits
; /* number of bits in imm field */
727 int scale
; /* scale factor to be applied to imm */
728 int is_signed
; /* is the imm field signed? */
732 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
734 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
735 if (offset
& 0x8000) /* check for negative extend */
736 offset
= 0 - (0x10000 - (offset
& 0xffff));
737 return offset
| (inst
& 0x1f);
741 int max_imm
= 1 << nbits
;
742 int mask
= max_imm
- 1;
743 int sign_bit
= max_imm
>> 1;
745 offset
= inst
& mask
;
746 if (is_signed
&& (offset
& sign_bit
))
747 offset
= 0 - (max_imm
- offset
);
748 return offset
* scale
;
753 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
754 stream from start_pc to limit_pc. */
757 mips16_heuristic_proc_desc(start_pc
, limit_pc
, next_frame
, sp
)
758 CORE_ADDR start_pc
, limit_pc
;
759 struct frame_info
*next_frame
;
763 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
764 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
765 unsigned inst
= 0; /* current instruction */
767 PROC_FRAME_OFFSET(&temp_proc_desc
) = 0; /* size of stack frame */
768 PROC_FRAME_ADJUST(&temp_proc_desc
) = 0; /* offset of FP from SP */
770 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
774 /* Save the previous instruction. If it's an EXTEND, we'll extract
775 the immediate offset extension from it in mips16_get_imm. */
778 /* Fetch and decode the instruction. */
779 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
780 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
781 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
783 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
784 if (offset
< 0) /* negative stack adjustment? */
785 PROC_FRAME_OFFSET(&temp_proc_desc
) -= offset
;
787 /* Exit loop if a positive stack adjustment is found, which
788 usually means that the stack cleanup code in the function
789 epilogue is reached. */
792 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
794 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
795 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
796 PROC_REG_MASK(&temp_proc_desc
) |= (1 << reg
);
797 temp_saved_regs
.regs
[reg
] = sp
+ offset
;
799 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
801 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
802 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
803 PROC_REG_MASK(&temp_proc_desc
) |= (1 << reg
);
804 temp_saved_regs
.regs
[reg
] = sp
+ offset
;
806 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
808 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
809 PROC_REG_MASK(&temp_proc_desc
) |= (1 << RA_REGNUM
);
810 temp_saved_regs
.regs
[RA_REGNUM
] = sp
+ offset
;
812 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
814 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
815 PROC_REG_MASK(&temp_proc_desc
) |= (1 << RA_REGNUM
);
816 temp_saved_regs
.regs
[RA_REGNUM
] = sp
+ offset
;
818 else if (inst
== 0x673d) /* move $s1, $sp */
820 frame_addr
= read_next_frame_reg(next_frame
, 30);
821 PROC_FRAME_REG (&temp_proc_desc
) = 17;
823 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
825 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
826 frame_addr
= sp
+ offset
;
827 PROC_FRAME_REG (&temp_proc_desc
) = 17;
828 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
830 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
832 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
833 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
834 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
835 temp_saved_regs
.regs
[reg
] = frame_addr
+ offset
;
837 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
839 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
840 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
841 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
842 temp_saved_regs
.regs
[reg
] = frame_addr
+ offset
;
844 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
846 int areg_count
= (inst
>> 8) & 7;
847 int sreg_count
= (inst
>> 6) & 3;
849 /* The entry instruction always subtracts 32 from the SP. */
850 PROC_FRAME_OFFSET(&temp_proc_desc
) += 32;
852 /* Check if a0-a3 were saved in the caller's argument save area. */
853 for (reg
= 4, offset
= 32; reg
< areg_count
+4; reg
++)
855 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
856 temp_saved_regs
.regs
[reg
] = sp
+ offset
;
857 offset
-= MIPS_REGSIZE
;
860 /* Check if the ra register was pushed on the stack. */
864 PROC_REG_MASK(&temp_proc_desc
) |= 1 << RA_REGNUM
;
865 temp_saved_regs
.regs
[RA_REGNUM
] = sp
+ offset
;
866 offset
-= MIPS_REGSIZE
;
869 /* Check if the s0 and s1 registers were pushed on the stack. */
870 for (reg
= 16; reg
< sreg_count
+16; reg
++)
872 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
873 temp_saved_regs
.regs
[reg
] = sp
+ offset
;
874 offset
-= MIPS_REGSIZE
;
877 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
878 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
883 mips32_heuristic_proc_desc(start_pc
, limit_pc
, next_frame
, sp
)
884 CORE_ADDR start_pc
, limit_pc
;
885 struct frame_info
*next_frame
;
889 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
891 PROC_FRAME_OFFSET(&temp_proc_desc
) = 0;
892 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
894 unsigned long inst
, high_word
, low_word
;
897 /* Fetch the instruction. */
898 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
900 /* Save some code by pre-extracting some useful fields. */
901 high_word
= (inst
>> 16) & 0xffff;
902 low_word
= inst
& 0xffff;
903 reg
= high_word
& 0x1f;
905 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
906 || high_word
== 0x23bd /* addi $sp,$sp,-i */
907 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
909 if (low_word
& 0x8000) /* negative stack adjustment? */
910 PROC_FRAME_OFFSET(&temp_proc_desc
) += 0x10000 - low_word
;
912 /* Exit loop if a positive stack adjustment is found, which
913 usually means that the stack cleanup code in the function
914 epilogue is reached. */
917 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
919 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
920 temp_saved_regs
.regs
[reg
] = sp
+ low_word
;
922 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
924 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
925 but the register size used is only 32 bits. Make the address
926 for the saved register point to the lower 32 bits. */
927 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
928 temp_saved_regs
.regs
[reg
] = sp
+ low_word
+ 8 - MIPS_REGSIZE
;
930 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
932 /* Old gcc frame, r30 is virtual frame pointer. */
933 if ((long)low_word
!= PROC_FRAME_OFFSET(&temp_proc_desc
))
934 frame_addr
= sp
+ low_word
;
935 else if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
937 unsigned alloca_adjust
;
938 PROC_FRAME_REG (&temp_proc_desc
) = 30;
939 frame_addr
= read_next_frame_reg(next_frame
, 30);
940 alloca_adjust
= (unsigned)(frame_addr
- (sp
+ low_word
));
941 if (alloca_adjust
> 0)
943 /* FP > SP + frame_size. This may be because
944 * of an alloca or somethings similar.
945 * Fix sp to "pre-alloca" value, and try again.
952 /* move $30,$sp. With different versions of gas this will be either
953 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
954 Accept any one of these. */
955 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
957 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
958 if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
960 unsigned alloca_adjust
;
961 PROC_FRAME_REG (&temp_proc_desc
) = 30;
962 frame_addr
= read_next_frame_reg(next_frame
, 30);
963 alloca_adjust
= (unsigned)(frame_addr
- sp
);
964 if (alloca_adjust
> 0)
966 /* FP > SP + frame_size. This may be because
967 * of an alloca or somethings similar.
968 * Fix sp to "pre-alloca" value, and try again.
975 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
977 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
978 temp_saved_regs
.regs
[reg
] = frame_addr
+ low_word
;
983 static mips_extra_func_info_t
984 heuristic_proc_desc(start_pc
, limit_pc
, next_frame
)
985 CORE_ADDR start_pc
, limit_pc
;
986 struct frame_info
*next_frame
;
988 CORE_ADDR sp
= read_next_frame_reg (next_frame
, SP_REGNUM
);
990 if (start_pc
== 0) return NULL
;
991 memset (&temp_proc_desc
, '\0', sizeof(temp_proc_desc
));
992 memset (&temp_saved_regs
, '\0', sizeof(struct frame_saved_regs
));
993 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
994 PROC_FRAME_REG (&temp_proc_desc
) = SP_REGNUM
;
995 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
997 if (start_pc
+ 200 < limit_pc
)
998 limit_pc
= start_pc
+ 200;
999 if (pc_is_mips16 (start_pc
))
1000 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1002 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1003 return &temp_proc_desc
;
1006 static mips_extra_func_info_t
1007 non_heuristic_proc_desc (pc
, addrptr
)
1011 CORE_ADDR startaddr
;
1012 mips_extra_func_info_t proc_desc
;
1013 struct block
*b
= block_for_pc(pc
);
1016 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
1018 *addrptr
= startaddr
;
1019 if (b
== NULL
|| PC_IN_CALL_DUMMY (pc
, 0, 0))
1023 if (startaddr
> BLOCK_START (b
))
1024 /* This is the "pathological" case referred to in a comment in
1025 print_frame_info. It might be better to move this check into
1029 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_NAMESPACE
, 0, NULL
);
1032 /* If we never found a PDR for this function in symbol reading, then
1033 examine prologues to find the information. */
1036 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
1037 if (PROC_FRAME_REG (proc_desc
) == -1)
1047 static mips_extra_func_info_t
1048 find_proc_desc (pc
, next_frame
)
1050 struct frame_info
*next_frame
;
1052 mips_extra_func_info_t proc_desc
;
1053 CORE_ADDR startaddr
;
1055 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
1059 /* IF this is the topmost frame AND
1060 * (this proc does not have debugging information OR
1061 * the PC is in the procedure prologue)
1062 * THEN create a "heuristic" proc_desc (by analyzing
1063 * the actual code) to replace the "official" proc_desc.
1065 if (next_frame
== NULL
)
1067 struct symtab_and_line val
;
1068 struct symbol
*proc_symbol
=
1069 PROC_DESC_IS_DUMMY(proc_desc
) ? 0 : PROC_SYMBOL(proc_desc
);
1073 val
= find_pc_line (BLOCK_START
1074 (SYMBOL_BLOCK_VALUE(proc_symbol
)),
1076 val
.pc
= val
.end
? val
.end
: pc
;
1078 if (!proc_symbol
|| pc
< val
.pc
)
1080 mips_extra_func_info_t found_heuristic
=
1081 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
),
1083 if (found_heuristic
)
1084 proc_desc
= found_heuristic
;
1090 /* Is linked_proc_desc_table really necessary? It only seems to be used
1091 by procedure call dummys. However, the procedures being called ought
1092 to have their own proc_descs, and even if they don't,
1093 heuristic_proc_desc knows how to create them! */
1095 register struct linked_proc_info
*link
;
1097 for (link
= linked_proc_desc_table
; link
; link
= link
->next
)
1098 if (PROC_LOW_ADDR(&link
->info
) <= pc
1099 && PROC_HIGH_ADDR(&link
->info
) > pc
)
1103 startaddr
= heuristic_proc_start (pc
);
1106 heuristic_proc_desc (startaddr
, pc
, next_frame
);
1112 get_frame_pointer(frame
, proc_desc
)
1113 struct frame_info
*frame
;
1114 mips_extra_func_info_t proc_desc
;
1116 return ADDR_BITS_REMOVE (
1117 read_next_frame_reg (frame
, PROC_FRAME_REG (proc_desc
)) +
1118 PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
1121 mips_extra_func_info_t cached_proc_desc
;
1124 mips_frame_chain(frame
)
1125 struct frame_info
*frame
;
1127 mips_extra_func_info_t proc_desc
;
1129 CORE_ADDR saved_pc
= FRAME_SAVED_PC(frame
);
1131 if (saved_pc
== 0 || inside_entry_file (saved_pc
))
1134 /* Check if the PC is inside a call stub. If it is, fetch the
1135 PC of the caller of that stub. */
1136 if ((tmp
= mips_skip_stub (saved_pc
)) != 0)
1139 /* Look up the procedure descriptor for this PC. */
1140 proc_desc
= find_proc_desc(saved_pc
, frame
);
1144 cached_proc_desc
= proc_desc
;
1146 /* If no frame pointer and frame size is zero, we must be at end
1147 of stack (or otherwise hosed). If we don't check frame size,
1148 we loop forever if we see a zero size frame. */
1149 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
1150 && PROC_FRAME_OFFSET (proc_desc
) == 0
1151 /* The previous frame from a sigtramp frame might be frameless
1152 and have frame size zero. */
1153 && !frame
->signal_handler_caller
)
1156 return get_frame_pointer (frame
, proc_desc
);
1160 init_extra_frame_info(fci
)
1161 struct frame_info
*fci
;
1165 /* Use proc_desc calculated in frame_chain */
1166 mips_extra_func_info_t proc_desc
=
1167 fci
->next
? cached_proc_desc
: find_proc_desc(fci
->pc
, fci
->next
);
1169 fci
->saved_regs
= NULL
;
1171 proc_desc
== &temp_proc_desc
? 0 : proc_desc
;
1174 /* Fixup frame-pointer - only needed for top frame */
1175 /* This may not be quite right, if proc has a real frame register.
1176 Get the value of the frame relative sp, procedure might have been
1177 interrupted by a signal at it's very start. */
1178 if (fci
->pc
== PROC_LOW_ADDR (proc_desc
)
1179 && !PROC_DESC_IS_DUMMY (proc_desc
))
1180 fci
->frame
= read_next_frame_reg (fci
->next
, SP_REGNUM
);
1182 fci
->frame
= get_frame_pointer (fci
->next
, proc_desc
);
1184 if (proc_desc
== &temp_proc_desc
)
1188 /* Do not set the saved registers for a sigtramp frame,
1189 mips_find_saved_registers will do that for us.
1190 We can't use fci->signal_handler_caller, it is not yet set. */
1191 find_pc_partial_function (fci
->pc
, &name
,
1192 (CORE_ADDR
*)NULL
,(CORE_ADDR
*)NULL
);
1193 if (!IN_SIGTRAMP (fci
->pc
, name
))
1195 fci
->saved_regs
= (struct frame_saved_regs
*)
1196 obstack_alloc (&frame_cache_obstack
,
1197 sizeof (struct frame_saved_regs
));
1198 *fci
->saved_regs
= temp_saved_regs
;
1199 fci
->saved_regs
->regs
[PC_REGNUM
]
1200 = fci
->saved_regs
->regs
[RA_REGNUM
];
1204 /* hack: if argument regs are saved, guess these contain args */
1205 fci
->num_args
= -1; /* assume we can't tell how many args for now */
1206 for (regnum
= MIPS_LAST_ARG_REGNUM
; regnum
>= A0_REGNUM
; regnum
--)
1208 if (PROC_REG_MASK(proc_desc
) & (1 << regnum
))
1210 fci
->num_args
= regnum
- A0_REGNUM
+ 1;
1217 /* MIPS stack frames are almost impenetrable. When execution stops,
1218 we basically have to look at symbol information for the function
1219 that we stopped in, which tells us *which* register (if any) is
1220 the base of the frame pointer, and what offset from that register
1221 the frame itself is at.
1223 This presents a problem when trying to examine a stack in memory
1224 (that isn't executing at the moment), using the "frame" command. We
1225 don't have a PC, nor do we have any registers except SP.
1227 This routine takes two arguments, SP and PC, and tries to make the
1228 cached frames look as if these two arguments defined a frame on the
1229 cache. This allows the rest of info frame to extract the important
1230 arguments without difficulty. */
1233 setup_arbitrary_frame (argc
, argv
)
1238 error ("MIPS frame specifications require two arguments: sp and pc");
1240 return create_new_frame (argv
[0], argv
[1]);
1244 mips_push_arguments(nargs
, args
, sp
, struct_return
, struct_addr
)
1249 CORE_ADDR struct_addr
;
1255 int stack_offset
= 0;
1257 /* Macros to round N up or down to the next A boundary; A must be
1259 #define ROUND_DOWN(n,a) ((n) & ~((a)-1))
1260 #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1))
1262 /* First ensure that the stack and structure return address (if any)
1263 are properly aligned. The stack has to be 64-bit aligned even
1264 on 32-bit machines, because doubles must be 64-bit aligned. */
1265 sp
= ROUND_DOWN (sp
, 8);
1266 struct_addr
= ROUND_DOWN (struct_addr
, MIPS_REGSIZE
);
1268 /* Now make space on the stack for the args. We allocate more
1269 than necessary for EABI, because the first few arguments are
1270 passed in registers, but that's OK. */
1271 for (argnum
= 0; argnum
< nargs
; argnum
++)
1272 len
+= ROUND_UP (TYPE_LENGTH(VALUE_TYPE(args
[argnum
])), MIPS_REGSIZE
);
1273 sp
-= ROUND_UP (len
, 8);
1275 /* Initialize the integer and float register pointers. */
1277 float_argreg
= FPA0_REGNUM
;
1279 /* the struct_return pointer occupies the first parameter-passing reg */
1281 write_register (argreg
++, struct_addr
);
1283 /* Now load as many as possible of the first arguments into
1284 registers, and push the rest onto the stack. Loop thru args
1285 from first to last. */
1286 for (argnum
= 0; argnum
< nargs
; argnum
++)
1289 char valbuf
[REGISTER_RAW_SIZE(A0_REGNUM
)];
1290 value_ptr arg
= args
[argnum
];
1291 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
1292 int len
= TYPE_LENGTH (arg_type
);
1293 enum type_code typecode
= TYPE_CODE (arg_type
);
1295 /* The EABI passes structures that do not fit in a register by
1296 reference. In all other cases, pass the structure by value. */
1297 if (MIPS_EABI
&& len
> MIPS_REGSIZE
&&
1298 (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
1300 store_address (valbuf
, MIPS_REGSIZE
, VALUE_ADDRESS (arg
));
1301 typecode
= TYPE_CODE_PTR
;
1306 val
= (char *)VALUE_CONTENTS (arg
);
1308 /* 32-bit ABIs always start floating point arguments in an
1309 even-numbered floating point register. */
1310 if (!GDB_TARGET_IS_MIPS64
&& typecode
== TYPE_CODE_FLT
1311 && (float_argreg
& 1))
1314 /* Floating point arguments passed in registers have to be
1315 treated specially. On 32-bit architectures, doubles
1316 are passed in register pairs; the even register gets
1317 the low word, and the odd register gets the high word.
1318 On non-EABI processors, the first two floating point arguments are
1319 also copied to general registers, because MIPS16 functions
1320 don't use float registers for arguments. This duplication of
1321 arguments in general registers can't hurt non-MIPS16 functions
1322 because those registers are normally skipped. */
1323 if (typecode
== TYPE_CODE_FLT
1324 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
1325 && mips_fpu
!= MIPS_FPU_NONE
)
1327 if (!GDB_TARGET_IS_MIPS64
&& len
== 8)
1329 int low_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 4 : 0;
1330 unsigned long regval
;
1332 /* Write the low word of the double to the even register(s). */
1333 regval
= extract_unsigned_integer (val
+low_offset
, 4);
1334 write_register (float_argreg
++, regval
);
1336 write_register (argreg
+1, regval
);
1338 /* Write the high word of the double to the odd register(s). */
1339 regval
= extract_unsigned_integer (val
+4-low_offset
, 4);
1340 write_register (float_argreg
++, regval
);
1343 write_register (argreg
, regval
);
1350 /* This is a floating point value that fits entirely
1351 in a single register. */
1352 CORE_ADDR regval
= extract_address (val
, len
);
1353 write_register (float_argreg
++, regval
);
1356 write_register (argreg
, regval
);
1357 argreg
+= GDB_TARGET_IS_MIPS64
? 1 : 2;
1363 /* Copy the argument to general registers or the stack in
1364 register-sized pieces. Large arguments are split between
1365 registers and stack. */
1366 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
1367 are treated specially: Irix cc passes them in registers
1368 where gcc sometimes puts them on the stack. For maximum
1369 compatibility, we will put them in both places. */
1371 int odd_sized_struct
= ((len
> MIPS_REGSIZE
) &&
1372 (len
% MIPS_REGSIZE
!= 0));
1375 int partial_len
= len
< MIPS_REGSIZE
? len
: MIPS_REGSIZE
;
1377 if (argreg
> MIPS_LAST_ARG_REGNUM
|| odd_sized_struct
)
1379 /* Write this portion of the argument to the stack. */
1380 int longword_offset
;
1382 longword_offset
= 0;
1383 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
1384 if (MIPS_REGSIZE
== 8 &&
1385 (typecode
== TYPE_CODE_INT
||
1386 typecode
== TYPE_CODE_PTR
||
1387 typecode
== TYPE_CODE_FLT
) && len
<= 4)
1388 longword_offset
= 4;
1389 else if ((typecode
== TYPE_CODE_STRUCT
||
1390 typecode
== TYPE_CODE_UNION
) &&
1391 TYPE_LENGTH (arg_type
) < MIPS_REGSIZE
)
1392 longword_offset
= MIPS_REGSIZE
- len
;
1394 write_memory (sp
+ stack_offset
+ longword_offset
,
1398 /* Note!!! This is NOT an else clause.
1399 Odd sized structs may go thru BOTH paths. */
1400 if (argreg
<= MIPS_LAST_ARG_REGNUM
)
1402 CORE_ADDR regval
= extract_address (val
, partial_len
);
1404 /* A non-floating-point argument being passed in a
1405 general register. If a struct or union, and if
1406 the remaining length is smaller than the register
1407 size, we have to adjust the register value on
1410 It does not seem to be necessary to do the
1411 same for integral types.
1413 Also don't do this adjustment on EABI targets. */
1416 TARGET_BYTE_ORDER
== BIG_ENDIAN
&&
1417 partial_len
< MIPS_REGSIZE
&&
1418 (typecode
== TYPE_CODE_STRUCT
||
1419 typecode
== TYPE_CODE_UNION
))
1420 regval
<<= ((MIPS_REGSIZE
- partial_len
) *
1423 write_register (argreg
, regval
);
1426 /* If this is the old ABI, prevent subsequent floating
1427 point arguments from being passed in floating point
1430 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
1436 /* The offset onto the stack at which we will start
1437 copying parameters (after the registers are used up)
1438 begins at (4 * MIPS_REGSIZE) in the old ABI. This
1439 leaves room for the "home" area for register parameters.
1441 In the new EABI, the 8 register parameters do not
1442 have "home" stack space reserved for them, so the
1443 stack offset does not get incremented until after
1444 we have used up the 8 parameter registers. */
1445 if (!(MIPS_EABI
&& argnum
< 8))
1446 stack_offset
+= ROUND_UP (partial_len
, MIPS_REGSIZE
);
1451 /* Set the return address register to point to the entry
1452 point of the program, where a breakpoint lies in wait. */
1453 write_register (RA_REGNUM
, CALL_DUMMY_ADDRESS());
1455 /* Return adjusted stack pointer. */
1460 mips_push_register(CORE_ADDR
*sp
, int regno
)
1462 char buffer
[MAX_REGISTER_RAW_SIZE
];
1463 int regsize
= REGISTER_RAW_SIZE (regno
);
1466 read_register_gen (regno
, buffer
);
1467 write_memory (*sp
, buffer
, regsize
);
1470 /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */
1471 #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1))
1474 mips_push_dummy_frame()
1477 struct linked_proc_info
*link
= (struct linked_proc_info
*)
1478 xmalloc(sizeof(struct linked_proc_info
));
1479 mips_extra_func_info_t proc_desc
= &link
->info
;
1480 CORE_ADDR sp
= ADDR_BITS_REMOVE (read_register (SP_REGNUM
));
1481 CORE_ADDR old_sp
= sp
;
1482 link
->next
= linked_proc_desc_table
;
1483 linked_proc_desc_table
= link
;
1485 /* FIXME! are these correct ? */
1486 #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */
1487 #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1))
1488 #define FLOAT_REG_SAVE_MASK MASK(0,19)
1489 #define FLOAT_SINGLE_REG_SAVE_MASK \
1490 ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0))
1492 * The registers we must save are all those not preserved across
1493 * procedure calls. Dest_Reg (see tm-mips.h) must also be saved.
1494 * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI
1495 * and FP Control/Status registers.
1498 * Dummy frame layout:
1501 * Saved MMHI, MMLO, FPC_CSR
1506 * Saved D18 (i.e. F19, F18)
1508 * Saved D0 (i.e. F1, F0)
1509 * Argument build area and stack arguments written via mips_push_arguments
1513 /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */
1514 PROC_FRAME_REG(proc_desc
) = PUSH_FP_REGNUM
;
1515 PROC_FRAME_OFFSET(proc_desc
) = 0;
1516 mips_push_register (&sp
, PC_REGNUM
);
1517 mips_push_register (&sp
, HI_REGNUM
);
1518 mips_push_register (&sp
, LO_REGNUM
);
1519 mips_push_register (&sp
, mips_fpu
== MIPS_FPU_NONE
? 0 : FCRCS_REGNUM
);
1521 /* Save general CPU registers */
1522 PROC_REG_MASK(proc_desc
) = GEN_REG_SAVE_MASK
;
1523 PROC_REG_OFFSET(proc_desc
) = sp
- old_sp
; /* offset of (Saved R31) from FP */
1524 for (ireg
= 32; --ireg
>= 0; )
1525 if (PROC_REG_MASK(proc_desc
) & (1 << ireg
))
1526 mips_push_register (&sp
, ireg
);
1528 /* Save floating point registers starting with high order word */
1529 PROC_FREG_MASK(proc_desc
) =
1530 mips_fpu
== MIPS_FPU_DOUBLE
? FLOAT_REG_SAVE_MASK
1531 : mips_fpu
== MIPS_FPU_SINGLE
? FLOAT_SINGLE_REG_SAVE_MASK
: 0;
1532 PROC_FREG_OFFSET(proc_desc
) = sp
- old_sp
; /* offset of (Saved D18) from FP */
1533 for (ireg
= 32; --ireg
>= 0; )
1534 if (PROC_FREG_MASK(proc_desc
) & (1 << ireg
))
1535 mips_push_register (&sp
, ireg
+ FP0_REGNUM
);
1537 /* Update the frame pointer for the call dummy and the stack pointer.
1538 Set the procedure's starting and ending addresses to point to the
1539 call dummy address at the entry point. */
1540 write_register (PUSH_FP_REGNUM
, old_sp
);
1541 write_register (SP_REGNUM
, sp
);
1542 PROC_LOW_ADDR(proc_desc
) = CALL_DUMMY_ADDRESS();
1543 PROC_HIGH_ADDR(proc_desc
) = CALL_DUMMY_ADDRESS() + 4;
1544 SET_PROC_DESC_IS_DUMMY(proc_desc
);
1545 PROC_PC_REG(proc_desc
) = RA_REGNUM
;
1551 register int regnum
;
1552 struct frame_info
*frame
= get_current_frame ();
1553 CORE_ADDR new_sp
= FRAME_FP (frame
);
1555 mips_extra_func_info_t proc_desc
= frame
->proc_desc
;
1557 write_register (PC_REGNUM
, FRAME_SAVED_PC(frame
));
1558 if (frame
->saved_regs
== NULL
)
1559 mips_find_saved_regs (frame
);
1560 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
1562 if (regnum
!= SP_REGNUM
&& regnum
!= PC_REGNUM
1563 && frame
->saved_regs
->regs
[regnum
])
1564 write_register (regnum
,
1565 read_memory_integer (frame
->saved_regs
->regs
[regnum
],
1568 write_register (SP_REGNUM
, new_sp
);
1569 flush_cached_frames ();
1571 if (proc_desc
&& PROC_DESC_IS_DUMMY(proc_desc
))
1573 struct linked_proc_info
*pi_ptr
, *prev_ptr
;
1575 for (pi_ptr
= linked_proc_desc_table
, prev_ptr
= NULL
;
1577 prev_ptr
= pi_ptr
, pi_ptr
= pi_ptr
->next
)
1579 if (&pi_ptr
->info
== proc_desc
)
1584 error ("Can't locate dummy extra frame info\n");
1586 if (prev_ptr
!= NULL
)
1587 prev_ptr
->next
= pi_ptr
->next
;
1589 linked_proc_desc_table
= pi_ptr
->next
;
1593 write_register (HI_REGNUM
,
1594 read_memory_integer (new_sp
- 2*MIPS_REGSIZE
, MIPS_REGSIZE
));
1595 write_register (LO_REGNUM
,
1596 read_memory_integer (new_sp
- 3*MIPS_REGSIZE
, MIPS_REGSIZE
));
1597 if (mips_fpu
!= MIPS_FPU_NONE
)
1598 write_register (FCRCS_REGNUM
,
1599 read_memory_integer (new_sp
- 4*MIPS_REGSIZE
, MIPS_REGSIZE
));
1604 mips_print_register (regnum
, all
)
1607 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
1609 /* Get the data in raw format. */
1610 if (read_relative_register_raw_bytes (regnum
, raw_buffer
))
1612 printf_filtered ("%s: [Invalid]", reg_names
[regnum
]);
1616 /* If an even floating point register, also print as double. */
1617 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
1618 && !((regnum
-FP0_REGNUM
) & 1))
1619 if (REGISTER_RAW_SIZE(regnum
) == 4) /* this would be silly on MIPS64 */
1621 char dbuffer
[2 * MAX_REGISTER_RAW_SIZE
];
1623 read_relative_register_raw_bytes (regnum
, dbuffer
);
1624 read_relative_register_raw_bytes (regnum
+1, dbuffer
+MIPS_REGSIZE
);
1625 REGISTER_CONVERT_TO_TYPE (regnum
, builtin_type_double
, dbuffer
);
1627 printf_filtered ("(d%d: ", regnum
-FP0_REGNUM
);
1628 val_print (builtin_type_double
, dbuffer
, 0,
1629 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
1630 printf_filtered ("); ");
1632 fputs_filtered (reg_names
[regnum
], gdb_stdout
);
1634 /* The problem with printing numeric register names (r26, etc.) is that
1635 the user can't use them on input. Probably the best solution is to
1636 fix it so that either the numeric or the funky (a2, etc.) names
1637 are accepted on input. */
1638 if (regnum
< MIPS_NUMREGS
)
1639 printf_filtered ("(r%d): ", regnum
);
1641 printf_filtered (": ");
1643 /* If virtual format is floating, print it that way. */
1644 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
1645 if (REGISTER_RAW_SIZE(regnum
) == 8)
1646 { /* show 8-byte floats as float AND double: */
1647 int offset
= 4 * (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
1649 printf_filtered (" (float) ");
1650 val_print (builtin_type_float
, raw_buffer
+ offset
, 0,
1651 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
1652 printf_filtered (", (double) ");
1653 val_print (builtin_type_double
, raw_buffer
, 0,
1654 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
1657 val_print (REGISTER_VIRTUAL_TYPE (regnum
), raw_buffer
, 0,
1658 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
1659 /* Else print as integer in hex. */
1661 print_scalar_formatted (raw_buffer
, REGISTER_VIRTUAL_TYPE (regnum
),
1662 'x', 0, gdb_stdout
);
1665 /* Replacement for generic do_registers_info.
1666 Print regs in pretty columns. */
1669 do_fp_register_row (regnum
)
1671 { /* do values for FP (float) regs */
1672 char raw_buffer
[2] [REGISTER_RAW_SIZE(FP0_REGNUM
)];
1673 char dbl_buffer
[2 * REGISTER_RAW_SIZE(FP0_REGNUM
)];
1674 /* use HI and LO to control the order of combining two flt regs */
1675 int HI
= (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
1676 int LO
= (TARGET_BYTE_ORDER
!= BIG_ENDIAN
);
1677 double doub
, flt1
, flt2
; /* doubles extracted from raw hex data */
1678 int inv1
, inv2
, inv3
;
1680 /* Get the data in raw format. */
1681 if (read_relative_register_raw_bytes (regnum
, raw_buffer
[HI
]))
1682 error ("can't read register %d (%s)", regnum
, reg_names
[regnum
]);
1683 if (REGISTER_RAW_SIZE(regnum
) == 4)
1685 /* 4-byte registers: we can fit two registers per row. */
1686 /* Also print every pair of 4-byte regs as an 8-byte double. */
1687 if (read_relative_register_raw_bytes (regnum
+ 1, raw_buffer
[LO
]))
1688 error ("can't read register %d (%s)",
1689 regnum
+ 1, reg_names
[regnum
+ 1]);
1691 /* copy the two floats into one double, and unpack both */
1692 memcpy (dbl_buffer
, raw_buffer
, sizeof(dbl_buffer
));
1693 flt1
= unpack_double (builtin_type_float
, raw_buffer
[HI
], &inv1
);
1694 flt2
= unpack_double (builtin_type_float
, raw_buffer
[LO
], &inv2
);
1695 doub
= unpack_double (builtin_type_double
, dbl_buffer
, &inv3
);
1697 printf_filtered (inv1
? " %-5s: <invalid float>" :
1698 " %-5s%-17.9g", reg_names
[regnum
], flt1
);
1699 printf_filtered (inv2
? " %-5s: <invalid float>" :
1700 " %-5s%-17.9g", reg_names
[regnum
+ 1], flt2
);
1701 printf_filtered (inv3
? " dbl: <invalid double>\n" :
1702 " dbl: %-24.17g\n", doub
);
1703 /* may want to do hex display here (future enhancement) */
1707 { /* eight byte registers: print each one as float AND as double. */
1708 int offset
= 4 * (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
1710 memcpy (dbl_buffer
, raw_buffer
[HI
], sizeof(dbl_buffer
));
1711 flt1
= unpack_double (builtin_type_float
,
1712 &raw_buffer
[HI
][offset
], &inv1
);
1713 doub
= unpack_double (builtin_type_double
, dbl_buffer
, &inv3
);
1715 printf_filtered (inv1
? " %-5s: <invalid float>" :
1716 " %-5s flt: %-17.9g", reg_names
[regnum
], flt1
);
1717 printf_filtered (inv3
? " dbl: <invalid double>\n" :
1718 " dbl: %-24.17g\n", doub
);
1719 /* may want to do hex display here (future enhancement) */
1725 /* Print a row's worth of GP (int) registers, with name labels above */
1728 do_gp_register_row (regnum
)
1730 { /* do values for GP (int) regs */
1731 char raw_buffer
[REGISTER_RAW_SIZE(0)];
1732 int ncols
= MIPS_REGSIZE
== 8 ? 4 : 8; /* display cols per row */
1733 int col
, byte
, start_regnum
= regnum
;
1735 /* For GP registers, we print a separate row of names above the vals */
1736 printf_filtered (" ");
1737 for (col
= 0; col
< ncols
&& regnum
< NUM_REGS
; regnum
++)
1739 if (*reg_names
[regnum
] == '\0')
1740 continue; /* unused register */
1741 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
1742 break; /* end the row: reached FP register */
1743 printf_filtered (MIPS_REGSIZE
== 8 ? "%17s" : "%9s",
1747 printf_filtered (start_regnum
< MIPS_NUMREGS
? "\n R%-4d" : "\n ",
1748 start_regnum
); /* print the R0 to R31 names */
1750 regnum
= start_regnum
; /* go back to start of row */
1751 /* now print the values in hex, 4 or 8 to the row */
1752 for (col
= 0; col
< ncols
&& regnum
< NUM_REGS
; regnum
++)
1754 if (*reg_names
[regnum
] == '\0')
1755 continue; /* unused register */
1756 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
1757 break; /* end row: reached FP register */
1758 /* OK: get the data in raw format. */
1759 if (read_relative_register_raw_bytes (regnum
, raw_buffer
))
1760 error ("can't read register %d (%s)", regnum
, reg_names
[regnum
]);
1761 /* Now print the register value in hex, endian order. */
1762 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
1763 for (byte
= 0; byte
< REGISTER_RAW_SIZE (regnum
); byte
++)
1764 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
1766 for (byte
= REGISTER_RAW_SIZE (regnum
) - 1; byte
>= 0; byte
--)
1767 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
1768 printf_filtered (" ");
1771 if (col
> 0) /* ie. if we actually printed anything... */
1772 printf_filtered ("\n");
1777 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
1780 mips_do_registers_info (regnum
, fpregs
)
1784 if (regnum
!= -1) /* do one specified register */
1786 if (*(reg_names
[regnum
]) == '\0')
1787 error ("Not a valid register for the current processor type");
1789 mips_print_register (regnum
, 0);
1790 printf_filtered ("\n");
1792 else /* do all (or most) registers */
1795 while (regnum
< NUM_REGS
)
1796 if (TYPE_CODE(REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
1797 if (fpregs
) /* true for "INFO ALL-REGISTERS" command */
1798 regnum
= do_fp_register_row (regnum
); /* FP regs */
1800 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
1802 regnum
= do_gp_register_row (regnum
); /* GP (int) regs */
1806 /* Return number of args passed to a frame. described by FIP.
1807 Can return -1, meaning no way to tell. */
1810 mips_frame_num_args (frame
)
1811 struct frame_info
*frame
;
1813 #if 0 /* FIXME Use or lose this! */
1814 struct chain_info_t
*p
;
1816 p
= mips_find_cached_frame (FRAME_FP (frame
));
1818 return p
->the_info
.numargs
;
1823 /* Is this a branch with a delay slot? */
1825 static int is_delayed
PARAMS ((unsigned long));
1832 for (i
= 0; i
< NUMOPCODES
; ++i
)
1833 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
1834 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
1836 return (i
< NUMOPCODES
1837 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
1838 | INSN_COND_BRANCH_DELAY
1839 | INSN_COND_BRANCH_LIKELY
)));
1843 mips_step_skips_delay (pc
)
1846 char buf
[MIPS_INSTLEN
];
1848 /* There is no branch delay slot on MIPS16. */
1849 if (pc_is_mips16 (pc
))
1852 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
1853 /* If error reading memory, guess that it is not a delayed branch. */
1855 return is_delayed ((unsigned long)extract_unsigned_integer (buf
, MIPS_INSTLEN
));
1859 /* Skip the PC past function prologue instructions (32-bit version).
1860 This is a helper function for mips_skip_prologue. */
1863 mips32_skip_prologue (pc
, lenient
)
1864 CORE_ADDR pc
; /* starting PC to search from */
1869 int seen_sp_adjust
= 0;
1870 int load_immediate_bytes
= 0;
1872 /* Skip the typical prologue instructions. These are the stack adjustment
1873 instruction and the instructions that save registers on the stack
1874 or in the gcc frame. */
1875 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
1877 unsigned long high_word
;
1879 inst
= mips_fetch_instruction (pc
);
1880 high_word
= (inst
>> 16) & 0xffff;
1883 if (lenient
&& is_delayed (inst
))
1887 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
1888 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
1890 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
1891 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
1893 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
1894 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
1895 && (inst
& 0x001F0000)) /* reg != $zero */
1898 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
1900 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
1902 continue; /* reg != $zero */
1904 /* move $s8,$sp. With different versions of gas this will be either
1905 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
1906 Accept any one of these. */
1907 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
1910 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
1912 else if (high_word
== 0x3c1c) /* lui $gp,n */
1914 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
1916 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
1917 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
1919 /* The following instructions load $at or $t0 with an immediate
1920 value in preparation for a stack adjustment via
1921 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
1922 a local variable, so we accept them only before a stack adjustment
1923 instruction was seen. */
1924 else if (!seen_sp_adjust
)
1926 if (high_word
== 0x3c01 || /* lui $at,n */
1927 high_word
== 0x3c08) /* lui $t0,n */
1929 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
1932 else if (high_word
== 0x3421 || /* ori $at,$at,n */
1933 high_word
== 0x3508 || /* ori $t0,$t0,n */
1934 high_word
== 0x3401 || /* ori $at,$zero,n */
1935 high_word
== 0x3408) /* ori $t0,$zero,n */
1937 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
1947 /* In a frameless function, we might have incorrectly
1948 skipped some load immediate instructions. Undo the skipping
1949 if the load immediate was not followed by a stack adjustment. */
1950 if (load_immediate_bytes
&& !seen_sp_adjust
)
1951 pc
-= load_immediate_bytes
;
1955 /* Skip the PC past function prologue instructions (16-bit version).
1956 This is a helper function for mips_skip_prologue. */
1959 mips16_skip_prologue (pc
, lenient
)
1960 CORE_ADDR pc
; /* starting PC to search from */
1964 int extend_bytes
= 0;
1965 int prev_extend_bytes
;
1967 /* Table of instructions likely to be found in a function prologue. */
1970 unsigned short inst
;
1971 unsigned short mask
;
1974 { 0x6300, 0xff00 }, /* addiu $sp,offset */
1975 { 0xfb00, 0xff00 }, /* daddiu $sp,offset */
1976 { 0xd000, 0xf800 }, /* sw reg,n($sp) */
1977 { 0xf900, 0xff00 }, /* sd reg,n($sp) */
1978 { 0x6200, 0xff00 }, /* sw $ra,n($sp) */
1979 { 0xfa00, 0xff00 }, /* sd $ra,n($sp) */
1980 { 0x673d, 0xffff }, /* move $s1,sp */
1981 { 0xd980, 0xff80 }, /* sw $a0-$a3,n($s1) */
1982 { 0x6704, 0xff1c }, /* move reg,$a0-$a3 */
1983 { 0xe809, 0xf81f }, /* entry pseudo-op */
1984 { 0x0100, 0xff00 }, /* addiu $s1,$sp,n */
1985 { 0, 0 } /* end of table marker */
1988 /* Skip the typical prologue instructions. These are the stack adjustment
1989 instruction and the instructions that save registers on the stack
1990 or in the gcc frame. */
1991 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
1993 unsigned short inst
;
1996 inst
= mips_fetch_instruction (pc
);
1998 /* Normally we ignore an extend instruction. However, if it is
1999 not followed by a valid prologue instruction, we must adjust
2000 the pc back over the extend so that it won't be considered
2001 part of the prologue. */
2002 if ((inst
& 0xf800) == 0xf000) /* extend */
2004 extend_bytes
= MIPS16_INSTLEN
;
2007 prev_extend_bytes
= extend_bytes
;
2010 /* Check for other valid prologue instructions besides extend. */
2011 for (i
= 0; table
[i
].mask
!= 0; i
++)
2012 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
2014 if (table
[i
].mask
!= 0) /* it was in table? */
2015 continue; /* ignore it */
2016 else /* non-prologue */
2018 /* Return the current pc, adjusted backwards by 2 if
2019 the previous instruction was an extend. */
2020 return pc
- prev_extend_bytes
;
2026 /* To skip prologues, I use this predicate. Returns either PC itself
2027 if the code at PC does not look like a function prologue; otherwise
2028 returns an address that (if we're lucky) follows the prologue. If
2029 LENIENT, then we must skip everything which is involved in setting
2030 up the frame (it's OK to skip more, just so long as we don't skip
2031 anything which might clobber the registers which are being saved.
2032 We must skip more in the case where part of the prologue is in the
2033 delay slot of a non-prologue instruction). */
2036 mips_skip_prologue (pc
, lenient
)
2040 /* See if we can determine the end of the prologue via the symbol table.
2041 If so, then return either PC, or the PC after the prologue, whichever
2044 CORE_ADDR post_prologue_pc
= after_prologue (pc
, NULL
);
2046 if (post_prologue_pc
!= 0)
2047 return max (pc
, post_prologue_pc
);
2049 /* Can't determine prologue from the symbol table, need to examine
2052 if (pc_is_mips16 (pc
))
2053 return mips16_skip_prologue (pc
, lenient
);
2055 return mips32_skip_prologue (pc
, lenient
);
2059 /* The lenient prologue stuff should be superseded by the code in
2060 init_extra_frame_info which looks to see whether the stores mentioned
2061 in the proc_desc have actually taken place. */
2063 /* Is address PC in the prologue (loosely defined) for function at
2067 mips_in_lenient_prologue (startaddr
, pc
)
2068 CORE_ADDR startaddr
;
2071 CORE_ADDR end_prologue
= mips_skip_prologue (startaddr
, 1);
2072 return pc
>= startaddr
&& pc
< end_prologue
;
2076 /* Given a return value in `regbuf' with a type `valtype',
2077 extract and copy its value into `valbuf'. */
2079 mips_extract_return_value (valtype
, regbuf
, valbuf
)
2080 struct type
*valtype
;
2081 char regbuf
[REGISTER_BYTES
];
2086 int len
= TYPE_LENGTH (valtype
);
2089 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
2090 && (mips_fpu
== MIPS_FPU_DOUBLE
2091 || (mips_fpu
== MIPS_FPU_SINGLE
&& len
<= MIPS_REGSIZE
)))
2092 regnum
= FP0_REGNUM
;
2094 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2095 { /* "un-left-justify" the value from the register */
2096 if (len
< REGISTER_RAW_SIZE (regnum
))
2097 offset
= REGISTER_RAW_SIZE (regnum
) - len
;
2098 if (len
> REGISTER_RAW_SIZE (regnum
) && /* odd-size structs */
2099 len
< REGISTER_RAW_SIZE (regnum
) * 2 &&
2100 (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
2101 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
2102 offset
= 2 * REGISTER_RAW_SIZE (regnum
) - len
;
2104 memcpy (valbuf
, regbuf
+ REGISTER_BYTE (regnum
) + offset
, len
);
2105 REGISTER_CONVERT_TO_TYPE (regnum
, valtype
, valbuf
);
2108 /* Given a return value in `regbuf' with a type `valtype',
2109 write it's value into the appropriate register. */
2111 mips_store_return_value (valtype
, valbuf
)
2112 struct type
*valtype
;
2117 int len
= TYPE_LENGTH (valtype
);
2118 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2121 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
2122 && (mips_fpu
== MIPS_FPU_DOUBLE
2123 || (mips_fpu
== MIPS_FPU_SINGLE
&& len
<= MIPS_REGSIZE
)))
2124 regnum
= FP0_REGNUM
;
2126 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2127 { /* "left-justify" the value in the register */
2128 if (len
< REGISTER_RAW_SIZE (regnum
))
2129 offset
= REGISTER_RAW_SIZE (regnum
) - len
;
2130 if (len
> REGISTER_RAW_SIZE (regnum
) && /* odd-size structs */
2131 len
< REGISTER_RAW_SIZE (regnum
) * 2 &&
2132 (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
2133 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
2134 offset
= 2 * REGISTER_RAW_SIZE (regnum
) - len
;
2136 memcpy(raw_buffer
+ offset
, valbuf
, len
);
2137 REGISTER_CONVERT_FROM_TYPE(regnum
, valtype
, raw_buffer
);
2138 write_register_bytes(REGISTER_BYTE (regnum
), raw_buffer
,
2139 len
> REGISTER_RAW_SIZE (regnum
) ?
2140 len
: REGISTER_RAW_SIZE (regnum
));
2143 /* Exported procedure: Is PC in the signal trampoline code */
2146 in_sigtramp (pc
, ignore
)
2148 char *ignore
; /* function name */
2150 if (sigtramp_address
== 0)
2152 return (pc
>= sigtramp_address
&& pc
< sigtramp_end
);
2155 /* Command to set FPU type. mips_fpu_string will have been set to the
2156 user's argument. Set mips_fpu based on mips_fpu_string, and then
2157 canonicalize mips_fpu_string. */
2161 mips_set_fpu_command (args
, from_tty
, c
)
2164 struct cmd_list_element
*c
;
2168 if (mips_fpu_string
== NULL
|| *mips_fpu_string
== '\0')
2169 mips_fpu
= MIPS_FPU_DOUBLE
;
2170 else if (strcasecmp (mips_fpu_string
, "double") == 0
2171 || strcasecmp (mips_fpu_string
, "on") == 0
2172 || strcasecmp (mips_fpu_string
, "1") == 0
2173 || strcasecmp (mips_fpu_string
, "yes") == 0)
2174 mips_fpu
= MIPS_FPU_DOUBLE
;
2175 else if (strcasecmp (mips_fpu_string
, "none") == 0
2176 || strcasecmp (mips_fpu_string
, "off") == 0
2177 || strcasecmp (mips_fpu_string
, "0") == 0
2178 || strcasecmp (mips_fpu_string
, "no") == 0)
2179 mips_fpu
= MIPS_FPU_NONE
;
2180 else if (strcasecmp (mips_fpu_string
, "single") == 0)
2181 mips_fpu
= MIPS_FPU_SINGLE
;
2183 err
= strsave (mips_fpu_string
);
2185 if (mips_fpu_string
!= NULL
)
2186 free (mips_fpu_string
);
2190 case MIPS_FPU_DOUBLE
:
2191 mips_fpu_string
= strsave ("double");
2193 case MIPS_FPU_SINGLE
:
2194 mips_fpu_string
= strsave ("single");
2197 mips_fpu_string
= strsave ("none");
2203 struct cleanup
*cleanups
= make_cleanup (free
, err
);
2204 error ("Unknown FPU type `%s'. Use `double', `none', or `single'.",
2206 do_cleanups (cleanups
);
2211 mips_show_fpu_command (args
, from_tty
, c
)
2214 struct cmd_list_element
*c
;
2218 /* Command to set the processor type. */
2221 mips_set_processor_type_command (args
, from_tty
)
2227 if (tmp_mips_processor_type
== NULL
|| *tmp_mips_processor_type
== '\0')
2229 printf_unfiltered ("The known MIPS processor types are as follows:\n\n");
2230 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
2231 printf_unfiltered ("%s\n", mips_processor_type_table
[i
].name
);
2233 /* Restore the value. */
2234 tmp_mips_processor_type
= strsave (mips_processor_type
);
2239 if (!mips_set_processor_type (tmp_mips_processor_type
))
2241 error ("Unknown processor type `%s'.", tmp_mips_processor_type
);
2242 /* Restore its value. */
2243 tmp_mips_processor_type
= strsave (mips_processor_type
);
2248 mips_show_processor_type_command (args
, from_tty
)
2254 /* Modify the actual processor type. */
2257 mips_set_processor_type (str
)
2265 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
2267 if (strcasecmp (str
, mips_processor_type_table
[i
].name
) == 0)
2269 mips_processor_type
= str
;
2271 for (j
= 0; j
< NUM_REGS
; ++j
)
2272 reg_names
[j
] = mips_processor_type_table
[i
].regnames
[j
];
2276 /* FIXME tweak fpu flag too */
2283 /* Attempt to identify the particular processor model by reading the
2287 mips_read_processor_type ()
2291 prid
= read_register (PRID_REGNUM
);
2293 if ((prid
& ~0xf) == 0x700)
2294 return savestring ("r3041", strlen("r3041"));
2299 /* Just like reinit_frame_cache, but with the right arguments to be
2300 callable as an sfunc. */
2303 reinit_frame_cache_sfunc (args
, from_tty
, c
)
2306 struct cmd_list_element
*c
;
2308 reinit_frame_cache ();
2312 gdb_print_insn_mips (memaddr
, info
)
2314 disassemble_info
*info
;
2316 mips_extra_func_info_t proc_desc
;
2318 /* Search for the function containing this address. Set the low bit
2319 of the address when searching, in case we were given an even address
2320 that is the start of a 16-bit function. If we didn't do this,
2321 the search would fail because the symbol table says the function
2322 starts at an odd address, i.e. 1 byte past the given address. */
2323 memaddr
= ADDR_BITS_REMOVE (memaddr
);
2324 proc_desc
= non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr
), NULL
);
2326 /* Make an attempt to determine if this is a 16-bit function. If
2327 the procedure descriptor exists and the address therein is odd,
2328 it's definitely a 16-bit function. Otherwise, we have to just
2329 guess that if the address passed in is odd, it's 16-bits. */
2331 info
->mach
= pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)) ? 16 : 0;
2333 info
->mach
= pc_is_mips16 (memaddr
) ? 16 : 0;
2335 /* Round down the instruction address to the appropriate boundary. */
2336 memaddr
&= (info
->mach
== 16 ? ~1 : ~3);
2338 /* Call the appropriate disassembler based on the target endian-ness. */
2339 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2340 return print_insn_big_mips (memaddr
, info
);
2342 return print_insn_little_mips (memaddr
, info
);
2345 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
2346 counter value to determine whether a 16- or 32-bit breakpoint should be
2347 used. It returns a pointer to a string of bytes that encode a breakpoint
2348 instruction, stores the length of the string to *lenptr, and adjusts pc
2349 (if necessary) to point to the actual memory location where the
2350 breakpoint should be inserted. */
2352 unsigned char *mips_breakpoint_from_pc (pcptr
, lenptr
)
2356 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2358 if (pc_is_mips16 (*pcptr
))
2360 static char mips16_big_breakpoint
[] = MIPS16_BIG_BREAKPOINT
;
2361 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
2362 *lenptr
= sizeof(mips16_big_breakpoint
);
2363 return mips16_big_breakpoint
;
2367 static char big_breakpoint
[] = BIG_BREAKPOINT
;
2368 static char pmon_big_breakpoint
[] = PMON_BIG_BREAKPOINT
;
2369 static char idt_big_breakpoint
[] = IDT_BIG_BREAKPOINT
;
2371 *lenptr
= sizeof(big_breakpoint
);
2373 if (strcmp (target_shortname
, "mips") == 0)
2374 return idt_big_breakpoint
;
2375 else if (strcmp (target_shortname
, "ddb") == 0
2376 || strcmp (target_shortname
, "pmon") == 0
2377 || strcmp (target_shortname
, "lsi") == 0)
2378 return pmon_big_breakpoint
;
2380 return big_breakpoint
;
2385 if (pc_is_mips16 (*pcptr
))
2387 static char mips16_little_breakpoint
[] = MIPS16_LITTLE_BREAKPOINT
;
2388 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
2389 *lenptr
= sizeof(mips16_little_breakpoint
);
2390 return mips16_little_breakpoint
;
2394 static char little_breakpoint
[] = LITTLE_BREAKPOINT
;
2395 static char pmon_little_breakpoint
[] = PMON_LITTLE_BREAKPOINT
;
2396 static char idt_little_breakpoint
[] = IDT_LITTLE_BREAKPOINT
;
2398 *lenptr
= sizeof(little_breakpoint
);
2400 if (strcmp (target_shortname
, "mips") == 0)
2401 return idt_little_breakpoint
;
2402 else if (strcmp (target_shortname
, "ddb") == 0
2403 || strcmp (target_shortname
, "pmon") == 0
2404 || strcmp (target_shortname
, "lsi") == 0)
2405 return pmon_little_breakpoint
;
2407 return little_breakpoint
;
2412 /* Test whether the PC points to the return instruction at the
2413 end of a function. This implements the ABOUT_TO_RETURN macro. */
2416 mips_about_to_return (pc
)
2419 if (pc_is_mips16 (pc
))
2420 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2421 generates a "jr $ra"; other times it generates code to load
2422 the return address from the stack to an accessible register (such
2423 as $a3), then a "jr" using that register. This second case
2424 is almost impossible to distinguish from an indirect jump
2425 used for switch statements, so we don't even try. */
2426 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
2428 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
2432 /* If PC is in a mips16 call or return stub, return the address of the target
2433 PC, which is either the callee or the caller. There are several
2434 cases which must be handled:
2436 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
2437 target PC is in $31 ($ra).
2438 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
2439 and the target PC is in $2.
2440 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
2441 before the jal instruction, this is effectively a call stub
2442 and the the target PC is in $2. Otherwise this is effectively
2443 a return stub and the target PC is in $18.
2445 See the source code for the stubs in gcc/config/mips/mips16.S for
2448 This function implements the SKIP_TRAMPOLINE_CODE macro.
2456 CORE_ADDR start_addr
;
2458 /* Find the starting address and name of the function containing the PC. */
2459 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
2462 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
2463 target PC is in $31 ($ra). */
2464 if (strcmp (name
, "__mips16_ret_sf") == 0
2465 || strcmp (name
, "__mips16_ret_df") == 0)
2466 return read_register (RA_REGNUM
);
2468 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
2470 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
2471 and the target PC is in $2. */
2472 if (name
[19] >= '0' && name
[19] <= '9')
2473 return read_register (2);
2475 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
2476 before the jal instruction, this is effectively a call stub
2477 and the the target PC is in $2. Otherwise this is effectively
2478 a return stub and the target PC is in $18. */
2479 else if (name
[19] == 's' || name
[19] == 'd')
2481 if (pc
== start_addr
)
2483 /* Check if the target of the stub is a compiler-generated
2484 stub. Such a stub for a function bar might have a name
2485 like __fn_stub_bar, and might look like this:
2490 la $1,bar (becomes a lui/addiu pair)
2492 So scan down to the lui/addi and extract the target
2493 address from those two instructions. */
2495 CORE_ADDR target_pc
= read_register (2);
2499 /* See if the name of the target function is __fn_stub_*. */
2500 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) == 0)
2502 if (strncmp (name
, "__fn_stub_", 10) != 0
2503 && strcmp (name
, "etext") != 0
2504 && strcmp (name
, "_etext") != 0)
2507 /* Scan through this _fn_stub_ code for the lui/addiu pair.
2508 The limit on the search is arbitrarily set to 20
2509 instructions. FIXME. */
2510 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
2512 inst
= mips_fetch_instruction (target_pc
);
2513 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
2514 pc
= (inst
<< 16) & 0xffff0000; /* high word */
2515 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
2516 return pc
| (inst
& 0xffff); /* low word */
2519 /* Couldn't find the lui/addui pair, so return stub address. */
2523 /* This is the 'return' part of a call stub. The return
2524 address is in $r18. */
2525 return read_register (18);
2528 return 0; /* not a stub */
2532 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
2533 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
2536 mips_in_call_stub (pc
, name
)
2540 CORE_ADDR start_addr
;
2542 /* Find the starting address of the function containing the PC. If the
2543 caller didn't give us a name, look it up at the same time. */
2544 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
2547 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
2549 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
2550 if (name
[19] >= '0' && name
[19] <= '9')
2552 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
2553 before the jal instruction, this is effectively a call stub. */
2554 else if (name
[19] == 's' || name
[19] == 'd')
2555 return pc
== start_addr
;
2558 return 0; /* not a stub */
2562 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
2563 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
2566 mips_in_return_stub (pc
, name
)
2570 CORE_ADDR start_addr
;
2572 /* Find the starting address of the function containing the PC. */
2573 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
2576 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
2577 if (strcmp (name
, "__mips16_ret_sf") == 0
2578 || strcmp (name
, "__mips16_ret_df") == 0)
2581 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
2582 i.e. after the jal instruction, this is effectively a return stub. */
2583 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
2584 && (name
[19] == 's' || name
[19] == 'd')
2585 && pc
!= start_addr
)
2588 return 0; /* not a stub */
2592 /* Return non-zero if the PC is in a library helper function that should
2593 be ignored. This implements the IGNORE_HELPER_CALL macro. */
2596 mips_ignore_helper (pc
)
2601 /* Find the starting address and name of the function containing the PC. */
2602 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
2605 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
2606 that we want to ignore. */
2607 return (strcmp (name
, "__mips16_ret_sf") == 0
2608 || strcmp (name
, "__mips16_ret_df") == 0);
2613 _initialize_mips_tdep ()
2615 struct cmd_list_element
*c
;
2617 tm_print_insn
= gdb_print_insn_mips
;
2619 /* Let the user turn off floating point and set the fence post for
2620 heuristic_proc_start. */
2622 c
= add_set_cmd ("mipsfpu", class_support
, var_string_noescape
,
2623 (char *) &mips_fpu_string
,
2624 "Set use of floating point coprocessor.\n\
2625 Set to `none' to avoid using floating point instructions when calling\n\
2626 functions or dealing with return values. Set to `single' to use only\n\
2627 single precision floating point as on the R4650. Set to `double' for\n\
2628 normal floating point support.",
2630 c
->function
.sfunc
= mips_set_fpu_command
;
2631 c
= add_show_from_set (c
, &showlist
);
2632 c
->function
.sfunc
= mips_show_fpu_command
;
2634 #ifndef MIPS_DEFAULT_FPU_TYPE
2635 mips_fpu
= MIPS_FPU_DOUBLE
;
2636 mips_fpu_string
= strsave ("double");
2638 mips_fpu
= MIPS_DEFAULT_FPU_TYPE
;
2641 case MIPS_FPU_DOUBLE
: mips_fpu_string
= strsave ("double"); break;
2642 case MIPS_FPU_SINGLE
: mips_fpu_string
= strsave ("single"); break;
2643 case MIPS_FPU_NONE
: mips_fpu_string
= strsave ("none"); break;
2647 c
= add_set_cmd ("processor", class_support
, var_string_noescape
,
2648 (char *) &tmp_mips_processor_type
,
2649 "Set the type of MIPS processor in use.\n\
2650 Set this to be able to access processor-type-specific registers.\n\
2653 c
->function
.cfunc
= mips_set_processor_type_command
;
2654 c
= add_show_from_set (c
, &showlist
);
2655 c
->function
.cfunc
= mips_show_processor_type_command
;
2657 tmp_mips_processor_type
= strsave (DEFAULT_MIPS_TYPE
);
2658 mips_set_processor_type_command (strsave (DEFAULT_MIPS_TYPE
), 0);
2660 /* We really would like to have both "0" and "unlimited" work, but
2661 command.c doesn't deal with that. So make it a var_zinteger
2662 because the user can always use "999999" or some such for unlimited. */
2663 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
2664 (char *) &heuristic_fence_post
,
2666 Set the distance searched for the start of a function.\n\
2667 If you are debugging a stripped executable, GDB needs to search through the\n\
2668 program for the start of a function. This command sets the distance of the\n\
2669 search. The only need to set it is when debugging a stripped executable.",
2671 /* We need to throw away the frame cache when we set this, since it
2672 might change our ability to get backtraces. */
2673 c
->function
.sfunc
= reinit_frame_cache_sfunc
;
2674 add_show_from_set (c
, &showlist
);