1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
5 Free Software Foundation, Inc.
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software
24 Foundation, Inc., 51 Franklin Street, Fifth Floor,
25 Boston, MA 02110-1301, USA. */
28 #include "gdb_string.h"
29 #include "gdb_assert.h"
41 #include "arch-utils.h"
44 #include "mips-tdep.h"
46 #include "reggroups.h"
47 #include "opcode/mips.h"
51 #include "sim-regno.h"
53 #include "frame-unwind.h"
54 #include "frame-base.h"
55 #include "trad-frame.h"
57 #include "floatformat.h"
59 #include "target-descriptions.h"
60 #include "dwarf2-frame.h"
62 static const struct objfile_data
*mips_pdr_data
;
64 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
66 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
67 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
68 #define ST0_FR (1 << 26)
70 /* The sizes of floating point registers. */
74 MIPS_FPU_SINGLE_REGSIZE
= 4,
75 MIPS_FPU_DOUBLE_REGSIZE
= 8
84 static const char *mips_abi_string
;
86 static const char *mips_abi_strings
[] = {
97 /* Some MIPS boards don't support floating point while others only
98 support single-precision floating-point operations. */
102 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
103 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
104 MIPS_FPU_NONE
/* No floating point. */
107 #ifndef MIPS_DEFAULT_FPU_TYPE
108 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
110 static int mips_fpu_type_auto
= 1;
111 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
113 static int mips_debug
= 0;
115 /* Properties (for struct target_desc) describing the g/G packet
117 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
118 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
120 /* MIPS specific per-architecture information */
123 /* from the elf header */
127 enum mips_abi mips_abi
;
128 enum mips_abi found_abi
;
129 enum mips_fpu_type mips_fpu_type
;
130 int mips_last_arg_regnum
;
131 int mips_last_fp_arg_regnum
;
132 int default_mask_address_p
;
133 /* Is the target using 64-bit raw integer registers but only
134 storing a left-aligned 32-bit value in each? */
135 int mips64_transfers_32bit_regs_p
;
136 /* Indexes for various registers. IRIX and embedded have
137 different values. This contains the "public" fields. Don't
138 add any that do not need to be public. */
139 const struct mips_regnum
*regnum
;
140 /* Register names table for the current register set. */
141 const char **mips_processor_reg_names
;
143 /* The size of register data available from the target, if known.
144 This doesn't quite obsolete the manual
145 mips64_transfers_32bit_regs_p, since that is documented to force
146 left alignment even for big endian (very strange). */
147 int register_size_valid_p
;
152 n32n64_floatformat_always_valid (const struct floatformat
*fmt
,
158 /* FIXME: brobecker/2004-08-08: Long Double values are 128 bit long.
159 They are implemented as a pair of 64bit doubles where the high
160 part holds the result of the operation rounded to double, and
161 the low double holds the difference between the exact result and
162 the rounded result. So "high" + "low" contains the result with
163 added precision. Unfortunately, the floatformat structure used
164 by GDB is not powerful enough to describe this format. As a temporary
165 measure, we define a 128bit floatformat that only uses the high part.
166 We lose a bit of precision but that's probably the best we can do
167 for now with the current infrastructure. */
169 static const struct floatformat floatformat_n32n64_long_double_big
=
171 floatformat_big
, 128, 0, 1, 11, 1023, 2047, 12, 52,
172 floatformat_intbit_no
,
173 "floatformat_n32n64_long_double_big",
174 n32n64_floatformat_always_valid
177 static const struct floatformat
*floatformats_n32n64_long
[BFD_ENDIAN_UNKNOWN
] =
179 &floatformat_n32n64_long_double_big
,
180 &floatformat_n32n64_long_double_big
183 const struct mips_regnum
*
184 mips_regnum (struct gdbarch
*gdbarch
)
186 return gdbarch_tdep (gdbarch
)->regnum
;
190 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
192 return mips_regnum (gdbarch
)->fp0
+ 12;
195 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
196 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
198 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
200 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
202 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
204 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
205 functions to test, set, or clear bit 0 of addresses. */
208 is_mips16_addr (CORE_ADDR addr
)
214 unmake_mips16_addr (CORE_ADDR addr
)
216 return ((addr
) & ~(CORE_ADDR
) 1);
219 /* Return the contents of register REGNUM as a signed integer. */
222 read_signed_register (int regnum
)
225 regcache_cooked_read_signed (current_regcache
, regnum
, &val
);
230 read_signed_register_pid (int regnum
, ptid_t ptid
)
235 if (ptid_equal (ptid
, inferior_ptid
))
236 return read_signed_register (regnum
);
238 save_ptid
= inferior_ptid
;
240 inferior_ptid
= ptid
;
242 retval
= read_signed_register (regnum
);
244 inferior_ptid
= save_ptid
;
249 /* Return the MIPS ABI associated with GDBARCH. */
251 mips_abi (struct gdbarch
*gdbarch
)
253 return gdbarch_tdep (gdbarch
)->mips_abi
;
257 mips_isa_regsize (struct gdbarch
*gdbarch
)
259 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
261 /* If we know how big the registers are, use that size. */
262 if (tdep
->register_size_valid_p
)
263 return tdep
->register_size
;
265 /* Fall back to the previous behavior. */
266 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
267 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
270 /* Return the currently configured (or set) saved register size. */
273 mips_abi_regsize (struct gdbarch
*gdbarch
)
275 switch (mips_abi (gdbarch
))
277 case MIPS_ABI_EABI32
:
283 case MIPS_ABI_EABI64
:
285 case MIPS_ABI_UNKNOWN
:
288 internal_error (__FILE__
, __LINE__
, _("bad switch"));
292 /* Functions for setting and testing a bit in a minimal symbol that
293 marks it as 16-bit function. The MSB of the minimal symbol's
294 "info" field is used for this purpose.
296 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special",
297 i.e. refers to a 16-bit function, and sets a "special" bit in a
298 minimal symbol to mark it as a 16-bit function
300 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
303 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
305 if (((elf_symbol_type
*) (sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
307 MSYMBOL_INFO (msym
) = (char *)
308 (((long) MSYMBOL_INFO (msym
)) | 0x80000000);
309 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
314 msymbol_is_special (struct minimal_symbol
*msym
)
316 return (((long) MSYMBOL_INFO (msym
) & 0x80000000) != 0);
319 /* XFER a value from the big/little/left end of the register.
320 Depending on the size of the value it might occupy the entire
321 register or just part of it. Make an allowance for this, aligning
322 things accordingly. */
325 mips_xfer_register (struct regcache
*regcache
, int reg_num
, int length
,
326 enum bfd_endian endian
, gdb_byte
*in
,
327 const gdb_byte
*out
, int buf_offset
)
330 gdb_assert (reg_num
>= gdbarch_num_regs (current_gdbarch
));
331 /* Need to transfer the left or right part of the register, based on
332 the targets byte order. */
336 reg_offset
= register_size (current_gdbarch
, reg_num
) - length
;
338 case BFD_ENDIAN_LITTLE
:
341 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
345 internal_error (__FILE__
, __LINE__
, _("bad switch"));
348 fprintf_unfiltered (gdb_stderr
,
349 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
350 reg_num
, reg_offset
, buf_offset
, length
);
351 if (mips_debug
&& out
!= NULL
)
354 fprintf_unfiltered (gdb_stdlog
, "out ");
355 for (i
= 0; i
< length
; i
++)
356 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
359 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
362 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
364 if (mips_debug
&& in
!= NULL
)
367 fprintf_unfiltered (gdb_stdlog
, "in ");
368 for (i
= 0; i
< length
; i
++)
369 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
372 fprintf_unfiltered (gdb_stdlog
, "\n");
375 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
376 compatiblity mode. A return value of 1 means that we have
377 physical 64-bit registers, but should treat them as 32-bit registers. */
380 mips2_fp_compat (void)
382 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
384 if (register_size (current_gdbarch
, mips_regnum (current_gdbarch
)->fp0
) ==
389 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
390 in all the places we deal with FP registers. PR gdb/413. */
391 /* Otherwise check the FR bit in the status register - it controls
392 the FP compatiblity mode. If it is clear we are in compatibility
394 if ((read_register (MIPS_PS_REGNUM
) & ST0_FR
) == 0)
401 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
403 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
405 static CORE_ADDR
read_next_frame_reg (struct frame_info
*, int);
407 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
409 static struct type
*mips_float_register_type (void);
410 static struct type
*mips_double_register_type (void);
412 /* The list of available "set mips " and "show mips " commands */
414 static struct cmd_list_element
*setmipscmdlist
= NULL
;
415 static struct cmd_list_element
*showmipscmdlist
= NULL
;
417 /* Integer registers 0 thru 31 are handled explicitly by
418 mips_register_name(). Processor specific registers 32 and above
419 are listed in the following tables. */
422 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
426 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
427 "sr", "lo", "hi", "bad", "cause", "pc",
428 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
429 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
430 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
431 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
432 "fsr", "fir", "" /*"fp" */ , "",
433 "", "", "", "", "", "", "", "",
434 "", "", "", "", "", "", "", "",
437 /* Names of IDT R3041 registers. */
439 static const char *mips_r3041_reg_names
[] = {
440 "sr", "lo", "hi", "bad", "cause", "pc",
441 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
442 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
443 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
444 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
445 "fsr", "fir", "", /*"fp" */ "",
446 "", "", "bus", "ccfg", "", "", "", "",
447 "", "", "port", "cmp", "", "", "epc", "prid",
450 /* Names of tx39 registers. */
452 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
453 "sr", "lo", "hi", "bad", "cause", "pc",
454 "", "", "", "", "", "", "", "",
455 "", "", "", "", "", "", "", "",
456 "", "", "", "", "", "", "", "",
457 "", "", "", "", "", "", "", "",
459 "", "", "", "", "", "", "", "",
460 "", "", "config", "cache", "debug", "depc", "epc", ""
463 /* Names of IRIX registers. */
464 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
465 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
466 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
467 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
468 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
469 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
473 /* Return the name of the register corresponding to REGNO. */
475 mips_register_name (int regno
)
477 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
478 /* GPR names for all ABIs other than n32/n64. */
479 static char *mips_gpr_names
[] = {
480 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
481 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
482 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
483 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
486 /* GPR names for n32 and n64 ABIs. */
487 static char *mips_n32_n64_gpr_names
[] = {
488 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
489 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
490 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
491 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
494 enum mips_abi abi
= mips_abi (current_gdbarch
);
496 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
497 but then don't make the raw register names visible. */
498 int rawnum
= regno
% gdbarch_num_regs (current_gdbarch
);
499 if (regno
< gdbarch_num_regs (current_gdbarch
))
502 /* The MIPS integer registers are always mapped from 0 to 31. The
503 names of the registers (which reflects the conventions regarding
504 register use) vary depending on the ABI. */
505 if (0 <= rawnum
&& rawnum
< 32)
507 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
508 return mips_n32_n64_gpr_names
[rawnum
];
510 return mips_gpr_names
[rawnum
];
512 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (current_gdbarch
))
514 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
515 return tdep
->mips_processor_reg_names
[rawnum
- 32];
518 internal_error (__FILE__
, __LINE__
,
519 _("mips_register_name: bad register number %d"), rawnum
);
522 /* Return the groups that a MIPS register can be categorised into. */
525 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
526 struct reggroup
*reggroup
)
531 int rawnum
= regnum
% gdbarch_num_regs (current_gdbarch
);
532 int pseudo
= regnum
/ gdbarch_num_regs (current_gdbarch
);
533 if (reggroup
== all_reggroup
)
535 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
536 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
537 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
538 (gdbarch), as not all architectures are multi-arch. */
539 raw_p
= rawnum
< gdbarch_num_regs (current_gdbarch
);
540 if (gdbarch_register_name (current_gdbarch
, regnum
) == NULL
541 || gdbarch_register_name (current_gdbarch
, regnum
)[0] == '\0')
543 if (reggroup
== float_reggroup
)
544 return float_p
&& pseudo
;
545 if (reggroup
== vector_reggroup
)
546 return vector_p
&& pseudo
;
547 if (reggroup
== general_reggroup
)
548 return (!vector_p
&& !float_p
) && pseudo
;
549 /* Save the pseudo registers. Need to make certain that any code
550 extracting register values from a saved register cache also uses
552 if (reggroup
== save_reggroup
)
553 return raw_p
&& pseudo
;
554 /* Restore the same pseudo register. */
555 if (reggroup
== restore_reggroup
)
556 return raw_p
&& pseudo
;
560 /* Map the symbol table registers which live in the range [1 *
561 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
562 registers. Take care of alignment and size problems. */
565 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
566 int cookednum
, gdb_byte
*buf
)
568 int rawnum
= cookednum
% gdbarch_num_regs (current_gdbarch
);
569 gdb_assert (cookednum
>= gdbarch_num_regs (current_gdbarch
)
570 && cookednum
< 2 * gdbarch_num_regs (current_gdbarch
));
571 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
572 regcache_raw_read (regcache
, rawnum
, buf
);
573 else if (register_size (gdbarch
, rawnum
) >
574 register_size (gdbarch
, cookednum
))
576 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
577 || gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_LITTLE
)
578 regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
580 regcache_raw_read_part (regcache
, rawnum
, 4, 4, buf
);
583 internal_error (__FILE__
, __LINE__
, _("bad register size"));
587 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
588 struct regcache
*regcache
, int cookednum
,
591 int rawnum
= cookednum
% gdbarch_num_regs (current_gdbarch
);
592 gdb_assert (cookednum
>= gdbarch_num_regs (current_gdbarch
)
593 && cookednum
< 2 * gdbarch_num_regs (current_gdbarch
));
594 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
595 regcache_raw_write (regcache
, rawnum
, buf
);
596 else if (register_size (gdbarch
, rawnum
) >
597 register_size (gdbarch
, cookednum
))
599 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
600 || gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_LITTLE
)
601 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
603 regcache_raw_write_part (regcache
, rawnum
, 4, 4, buf
);
606 internal_error (__FILE__
, __LINE__
, _("bad register size"));
609 /* Table to translate MIPS16 register field to actual register number. */
610 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
612 /* Heuristic_proc_start may hunt through the text section for a long
613 time across a 2400 baud serial line. Allows the user to limit this
616 static unsigned int heuristic_fence_post
= 0;
618 /* Number of bytes of storage in the actual machine representation for
619 register N. NOTE: This defines the pseudo register type so need to
620 rebuild the architecture vector. */
622 static int mips64_transfers_32bit_regs_p
= 0;
625 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
626 struct cmd_list_element
*c
)
628 struct gdbarch_info info
;
629 gdbarch_info_init (&info
);
630 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
631 instead of relying on globals. Doing that would let generic code
632 handle the search for this specific architecture. */
633 if (!gdbarch_update_p (info
))
635 mips64_transfers_32bit_regs_p
= 0;
636 error (_("32-bit compatibility mode not supported"));
640 /* Convert to/from a register and the corresponding memory value. */
643 mips_convert_register_p (int regnum
, struct type
*type
)
645 return (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
646 && register_size (current_gdbarch
, regnum
) == 4
647 && (regnum
% gdbarch_num_regs (current_gdbarch
))
648 >= mips_regnum (current_gdbarch
)->fp0
649 && (regnum
% gdbarch_num_regs (current_gdbarch
))
650 < mips_regnum (current_gdbarch
)->fp0
+ 32
651 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
655 mips_register_to_value (struct frame_info
*frame
, int regnum
,
656 struct type
*type
, gdb_byte
*to
)
658 get_frame_register (frame
, regnum
+ 0, to
+ 4);
659 get_frame_register (frame
, regnum
+ 1, to
+ 0);
663 mips_value_to_register (struct frame_info
*frame
, int regnum
,
664 struct type
*type
, const gdb_byte
*from
)
666 put_frame_register (frame
, regnum
+ 0, from
+ 4);
667 put_frame_register (frame
, regnum
+ 1, from
+ 0);
670 /* Return the GDB type object for the "standard" data type of data in
674 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
676 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (current_gdbarch
));
677 if ((regnum
% gdbarch_num_regs (current_gdbarch
))
678 >= mips_regnum (current_gdbarch
)->fp0
679 && (regnum
% gdbarch_num_regs (current_gdbarch
))
680 < mips_regnum (current_gdbarch
)->fp0
+ 32)
682 /* The floating-point registers raw, or cooked, always match
683 mips_isa_regsize(), and also map 1:1, byte for byte. */
684 if (mips_isa_regsize (gdbarch
) == 4)
685 return builtin_type_ieee_single
;
687 return builtin_type_ieee_double
;
689 else if (regnum
< gdbarch_num_regs (current_gdbarch
))
691 /* The raw or ISA registers. These are all sized according to
693 if (mips_isa_regsize (gdbarch
) == 4)
694 return builtin_type_int32
;
696 return builtin_type_int64
;
700 /* The cooked or ABI registers. These are sized according to
701 the ABI (with a few complications). */
702 if (regnum
>= (gdbarch_num_regs (current_gdbarch
)
703 + mips_regnum (current_gdbarch
)->fp_control_status
)
704 && regnum
<= gdbarch_num_regs (current_gdbarch
)
705 + MIPS_LAST_EMBED_REGNUM
)
706 /* The pseudo/cooked view of the embedded registers is always
707 32-bit. The raw view is handled below. */
708 return builtin_type_int32
;
709 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
710 /* The target, while possibly using a 64-bit register buffer,
711 is only transfering 32-bits of each integer register.
712 Reflect this in the cooked/pseudo (ABI) register value. */
713 return builtin_type_int32
;
714 else if (mips_abi_regsize (gdbarch
) == 4)
715 /* The ABI is restricted to 32-bit registers (the ISA could be
717 return builtin_type_int32
;
720 return builtin_type_int64
;
725 /* Should the upper word of 64-bit addresses be zeroed? */
726 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
729 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
731 switch (mask_address_var
)
733 case AUTO_BOOLEAN_TRUE
:
735 case AUTO_BOOLEAN_FALSE
:
738 case AUTO_BOOLEAN_AUTO
:
739 return tdep
->default_mask_address_p
;
741 internal_error (__FILE__
, __LINE__
, _("mips_mask_address_p: bad switch"));
747 show_mask_address (struct ui_file
*file
, int from_tty
,
748 struct cmd_list_element
*c
, const char *value
)
750 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
752 deprecated_show_value_hack (file
, from_tty
, c
, value
);
753 switch (mask_address_var
)
755 case AUTO_BOOLEAN_TRUE
:
756 printf_filtered ("The 32 bit mips address mask is enabled\n");
758 case AUTO_BOOLEAN_FALSE
:
759 printf_filtered ("The 32 bit mips address mask is disabled\n");
761 case AUTO_BOOLEAN_AUTO
:
763 ("The 32 bit address mask is set automatically. Currently %s\n",
764 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
767 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
772 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
775 mips_pc_is_mips16 (CORE_ADDR memaddr
)
777 struct minimal_symbol
*sym
;
779 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
780 if (is_mips16_addr (memaddr
))
783 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
784 the high bit of the info field. Use this to decide if the function is
785 MIPS16 or normal MIPS. */
786 sym
= lookup_minimal_symbol_by_pc (memaddr
);
788 return msymbol_is_special (sym
);
793 /* MIPS believes that the PC has a sign extended value. Perhaps the
794 all registers should be sign extended for simplicity? */
797 mips_read_pc (ptid_t ptid
)
799 return read_signed_register_pid (mips_regnum (current_gdbarch
)->pc
, ptid
);
803 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
805 return frame_unwind_register_signed (next_frame
,
806 gdbarch_num_regs (current_gdbarch
)
807 + mips_regnum (gdbarch
)->pc
);
811 mips_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
813 return frame_unwind_register_signed (next_frame
,
814 gdbarch_num_regs (current_gdbarch
)
818 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
819 dummy frame. The frame ID's base needs to match the TOS value
820 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
823 static struct frame_id
824 mips_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
826 return frame_id_build
827 (frame_unwind_register_signed (next_frame
,
828 gdbarch_num_regs (current_gdbarch
)
830 frame_pc_unwind (next_frame
));
834 mips_write_pc (CORE_ADDR pc
, ptid_t ptid
)
836 write_register_pid (mips_regnum (current_gdbarch
)->pc
, pc
, ptid
);
839 /* Fetch and return instruction from the specified location. If the PC
840 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
843 mips_fetch_instruction (CORE_ADDR addr
)
845 gdb_byte buf
[MIPS_INSN32_SIZE
];
849 if (mips_pc_is_mips16 (addr
))
851 instlen
= MIPS_INSN16_SIZE
;
852 addr
= unmake_mips16_addr (addr
);
855 instlen
= MIPS_INSN32_SIZE
;
856 status
= read_memory_nobpt (addr
, buf
, instlen
);
858 memory_error (status
, addr
);
859 return extract_unsigned_integer (buf
, instlen
);
862 /* These the fields of 32 bit mips instructions */
863 #define mips32_op(x) (x >> 26)
864 #define itype_op(x) (x >> 26)
865 #define itype_rs(x) ((x >> 21) & 0x1f)
866 #define itype_rt(x) ((x >> 16) & 0x1f)
867 #define itype_immediate(x) (x & 0xffff)
869 #define jtype_op(x) (x >> 26)
870 #define jtype_target(x) (x & 0x03ffffff)
872 #define rtype_op(x) (x >> 26)
873 #define rtype_rs(x) ((x >> 21) & 0x1f)
874 #define rtype_rt(x) ((x >> 16) & 0x1f)
875 #define rtype_rd(x) ((x >> 11) & 0x1f)
876 #define rtype_shamt(x) ((x >> 6) & 0x1f)
877 #define rtype_funct(x) (x & 0x3f)
880 mips32_relative_offset (ULONGEST inst
)
882 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
885 /* Determine where to set a single step breakpoint while considering
886 branch prediction. */
888 mips32_next_pc (CORE_ADDR pc
)
892 inst
= mips_fetch_instruction (pc
);
893 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
895 if (itype_op (inst
) >> 2 == 5)
896 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
898 op
= (itype_op (inst
) & 0x03);
913 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
914 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
916 int tf
= itype_rt (inst
) & 0x01;
917 int cnum
= itype_rt (inst
) >> 2;
919 read_signed_register (mips_regnum (current_gdbarch
)->
921 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
923 if (((cond
>> cnum
) & 0x01) == tf
)
924 pc
+= mips32_relative_offset (inst
) + 4;
929 pc
+= 4; /* Not a branch, next instruction is easy */
932 { /* This gets way messy */
934 /* Further subdivide into SPECIAL, REGIMM and other */
935 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
937 case 0: /* SPECIAL */
938 op
= rtype_funct (inst
);
943 /* Set PC to that address */
944 pc
= read_signed_register (rtype_rs (inst
));
950 break; /* end SPECIAL */
953 op
= itype_rt (inst
); /* branch condition */
958 case 16: /* BLTZAL */
959 case 18: /* BLTZALL */
961 if (read_signed_register (itype_rs (inst
)) < 0)
962 pc
+= mips32_relative_offset (inst
) + 4;
964 pc
+= 8; /* after the delay slot */
968 case 17: /* BGEZAL */
969 case 19: /* BGEZALL */
970 if (read_signed_register (itype_rs (inst
)) >= 0)
971 pc
+= mips32_relative_offset (inst
) + 4;
973 pc
+= 8; /* after the delay slot */
975 /* All of the other instructions in the REGIMM category */
980 break; /* end REGIMM */
985 reg
= jtype_target (inst
) << 2;
986 /* Upper four bits get never changed... */
987 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
990 /* FIXME case JALX : */
993 reg
= jtype_target (inst
) << 2;
994 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + 1; /* yes, +1 */
995 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
997 break; /* The new PC will be alternate mode */
998 case 4: /* BEQ, BEQL */
1000 if (read_signed_register (itype_rs (inst
)) ==
1001 read_signed_register (itype_rt (inst
)))
1002 pc
+= mips32_relative_offset (inst
) + 4;
1006 case 5: /* BNE, BNEL */
1008 if (read_signed_register (itype_rs (inst
)) !=
1009 read_signed_register (itype_rt (inst
)))
1010 pc
+= mips32_relative_offset (inst
) + 4;
1014 case 6: /* BLEZ, BLEZL */
1015 if (read_signed_register (itype_rs (inst
)) <= 0)
1016 pc
+= mips32_relative_offset (inst
) + 4;
1022 greater_branch
: /* BGTZ, BGTZL */
1023 if (read_signed_register (itype_rs (inst
)) > 0)
1024 pc
+= mips32_relative_offset (inst
) + 4;
1031 } /* mips32_next_pc */
1033 /* Decoding the next place to set a breakpoint is irregular for the
1034 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1035 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1036 We dont want to set a single step instruction on the extend instruction
1040 /* Lots of mips16 instruction formats */
1041 /* Predicting jumps requires itype,ritype,i8type
1042 and their extensions extItype,extritype,extI8type
1044 enum mips16_inst_fmts
1046 itype
, /* 0 immediate 5,10 */
1047 ritype
, /* 1 5,3,8 */
1048 rrtype
, /* 2 5,3,3,5 */
1049 rritype
, /* 3 5,3,3,5 */
1050 rrrtype
, /* 4 5,3,3,3,2 */
1051 rriatype
, /* 5 5,3,3,1,4 */
1052 shifttype
, /* 6 5,3,3,3,2 */
1053 i8type
, /* 7 5,3,8 */
1054 i8movtype
, /* 8 5,3,3,5 */
1055 i8mov32rtype
, /* 9 5,3,5,3 */
1056 i64type
, /* 10 5,3,8 */
1057 ri64type
, /* 11 5,3,3,5 */
1058 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1059 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1060 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1061 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1062 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1063 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1064 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1065 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1066 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1067 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1069 /* I am heaping all the fields of the formats into one structure and
1070 then, only the fields which are involved in instruction extension */
1074 unsigned int regx
; /* Function in i8 type */
1079 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1080 for the bits which make up the immediatate extension. */
1083 extended_offset (unsigned int extension
)
1086 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1088 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1090 value
|= extension
& 0x01f; /* extract 4:0 */
1094 /* Only call this function if you know that this is an extendable
1095 instruction, It wont malfunction, but why make excess remote memory references?
1096 If the immediate operands get sign extended or somthing, do it after
1097 the extension is performed.
1099 /* FIXME: Every one of these cases needs to worry about sign extension
1100 when the offset is to be used in relative addressing */
1104 fetch_mips_16 (CORE_ADDR pc
)
1107 pc
&= 0xfffffffe; /* clear the low order bit */
1108 target_read_memory (pc
, buf
, 2);
1109 return extract_unsigned_integer (buf
, 2);
1113 unpack_mips16 (CORE_ADDR pc
,
1114 unsigned int extension
,
1116 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1121 switch (insn_format
)
1128 value
= extended_offset (extension
);
1129 value
= value
<< 11; /* rom for the original value */
1130 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1134 value
= inst
& 0x7ff;
1135 /* FIXME : Consider sign extension */
1144 { /* A register identifier and an offset */
1145 /* Most of the fields are the same as I type but the
1146 immediate value is of a different length */
1150 value
= extended_offset (extension
);
1151 value
= value
<< 8; /* from the original instruction */
1152 value
|= inst
& 0xff; /* eleven bits from instruction */
1153 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1154 if (value
& 0x4000) /* test the sign bit , bit 26 */
1156 value
&= ~0x3fff; /* remove the sign bit */
1162 value
= inst
& 0xff; /* 8 bits */
1163 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1164 /* FIXME: Do sign extension , this format needs it */
1165 if (value
& 0x80) /* THIS CONFUSES ME */
1167 value
&= 0xef; /* remove the sign bit */
1177 unsigned long value
;
1178 unsigned int nexthalf
;
1179 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1180 value
= value
<< 16;
1181 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1189 internal_error (__FILE__
, __LINE__
, _("bad switch"));
1191 upk
->offset
= offset
;
1198 add_offset_16 (CORE_ADDR pc
, int offset
)
1200 return ((offset
<< 2) | ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)));
1204 extended_mips16_next_pc (CORE_ADDR pc
,
1205 unsigned int extension
, unsigned int insn
)
1207 int op
= (insn
>> 11);
1210 case 2: /* Branch */
1213 struct upk_mips16 upk
;
1214 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1215 offset
= upk
.offset
;
1221 pc
+= (offset
<< 1) + 2;
1224 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1226 struct upk_mips16 upk
;
1227 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1228 pc
= add_offset_16 (pc
, upk
.offset
);
1229 if ((insn
>> 10) & 0x01) /* Exchange mode */
1230 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1237 struct upk_mips16 upk
;
1239 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1240 reg
= read_signed_register (upk
.regx
);
1242 pc
+= (upk
.offset
<< 1) + 2;
1249 struct upk_mips16 upk
;
1251 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1252 reg
= read_signed_register (upk
.regx
);
1254 pc
+= (upk
.offset
<< 1) + 2;
1259 case 12: /* I8 Formats btez btnez */
1261 struct upk_mips16 upk
;
1263 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1264 /* upk.regx contains the opcode */
1265 reg
= read_signed_register (24); /* Test register is 24 */
1266 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1267 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1268 /* pc = add_offset_16(pc,upk.offset) ; */
1269 pc
+= (upk
.offset
<< 1) + 2;
1274 case 29: /* RR Formats JR, JALR, JALR-RA */
1276 struct upk_mips16 upk
;
1277 /* upk.fmt = rrtype; */
1282 upk
.regx
= (insn
>> 8) & 0x07;
1283 upk
.regy
= (insn
>> 5) & 0x07;
1291 break; /* Function return instruction */
1297 break; /* BOGUS Guess */
1299 pc
= read_signed_register (reg
);
1306 /* This is an instruction extension. Fetch the real instruction
1307 (which follows the extension) and decode things based on
1311 pc
= extended_mips16_next_pc (pc
, insn
, fetch_mips_16 (pc
));
1324 mips16_next_pc (CORE_ADDR pc
)
1326 unsigned int insn
= fetch_mips_16 (pc
);
1327 return extended_mips16_next_pc (pc
, 0, insn
);
1330 /* The mips_next_pc function supports single_step when the remote
1331 target monitor or stub is not developed enough to do a single_step.
1332 It works by decoding the current instruction and predicting where a
1333 branch will go. This isnt hard because all the data is available.
1334 The MIPS32 and MIPS16 variants are quite different */
1336 mips_next_pc (CORE_ADDR pc
)
1339 return mips16_next_pc (pc
);
1341 return mips32_next_pc (pc
);
1344 struct mips_frame_cache
1347 struct trad_frame_saved_reg
*saved_regs
;
1350 /* Set a register's saved stack address in temp_saved_regs. If an
1351 address has already been set for this register, do nothing; this
1352 way we will only recognize the first save of a given register in a
1355 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
1356 [gdbarch_num_regs .. 2*gdbarch_num_regs).
1357 Strictly speaking, only the second range is used as it is only second
1358 range (the ABI instead of ISA registers) that comes into play when finding
1359 saved registers in a frame. */
1362 set_reg_offset (struct mips_frame_cache
*this_cache
, int regnum
,
1365 if (this_cache
!= NULL
1366 && this_cache
->saved_regs
[regnum
].addr
== -1)
1368 this_cache
->saved_regs
[regnum
1369 + 0 * gdbarch_num_regs (current_gdbarch
)].addr
1371 this_cache
->saved_regs
[regnum
1372 + 1 * gdbarch_num_regs (current_gdbarch
)].addr
1378 /* Fetch the immediate value from a MIPS16 instruction.
1379 If the previous instruction was an EXTEND, use it to extend
1380 the upper bits of the immediate value. This is a helper function
1381 for mips16_scan_prologue. */
1384 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1385 unsigned short inst
, /* current instruction */
1386 int nbits
, /* number of bits in imm field */
1387 int scale
, /* scale factor to be applied to imm */
1388 int is_signed
) /* is the imm field signed? */
1392 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1394 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1395 if (offset
& 0x8000) /* check for negative extend */
1396 offset
= 0 - (0x10000 - (offset
& 0xffff));
1397 return offset
| (inst
& 0x1f);
1401 int max_imm
= 1 << nbits
;
1402 int mask
= max_imm
- 1;
1403 int sign_bit
= max_imm
>> 1;
1405 offset
= inst
& mask
;
1406 if (is_signed
&& (offset
& sign_bit
))
1407 offset
= 0 - (max_imm
- offset
);
1408 return offset
* scale
;
1413 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1414 the associated FRAME_CACHE if not null.
1415 Return the address of the first instruction past the prologue. */
1418 mips16_scan_prologue (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1419 struct frame_info
*next_frame
,
1420 struct mips_frame_cache
*this_cache
)
1423 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1425 long frame_offset
= 0; /* Size of stack frame. */
1426 long frame_adjust
= 0; /* Offset of FP from SP. */
1427 int frame_reg
= MIPS_SP_REGNUM
;
1428 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1429 unsigned inst
= 0; /* current instruction */
1430 unsigned entry_inst
= 0; /* the entry instruction */
1433 int extend_bytes
= 0;
1434 int prev_extend_bytes
;
1435 CORE_ADDR end_prologue_addr
= 0;
1437 /* Can be called when there's no process, and hence when there's no
1439 if (next_frame
!= NULL
)
1440 sp
= read_next_frame_reg (next_frame
, gdbarch_num_regs (current_gdbarch
)
1445 if (limit_pc
> start_pc
+ 200)
1446 limit_pc
= start_pc
+ 200;
1448 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
1450 /* Save the previous instruction. If it's an EXTEND, we'll extract
1451 the immediate offset extension from it in mips16_get_imm. */
1454 /* Fetch and decode the instruction. */
1455 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1457 /* Normally we ignore extend instructions. However, if it is
1458 not followed by a valid prologue instruction, then this
1459 instruction is not part of the prologue either. We must
1460 remember in this case to adjust the end_prologue_addr back
1462 if ((inst
& 0xf800) == 0xf000) /* extend */
1464 extend_bytes
= MIPS_INSN16_SIZE
;
1468 prev_extend_bytes
= extend_bytes
;
1471 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1472 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1474 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1475 if (offset
< 0) /* negative stack adjustment? */
1476 frame_offset
-= offset
;
1478 /* Exit loop if a positive stack adjustment is found, which
1479 usually means that the stack cleanup code in the function
1480 epilogue is reached. */
1483 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1485 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1486 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1487 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1489 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1491 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1492 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1493 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1495 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1497 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1498 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1500 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1502 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1503 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1505 else if (inst
== 0x673d) /* move $s1, $sp */
1510 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1512 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1513 frame_addr
= sp
+ offset
;
1515 frame_adjust
= offset
;
1517 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1519 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1520 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1521 set_reg_offset (this_cache
, reg
, frame_addr
+ offset
);
1523 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1525 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1526 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1527 set_reg_offset (this_cache
, reg
, frame_addr
+ offset
);
1529 else if ((inst
& 0xf81f) == 0xe809
1530 && (inst
& 0x700) != 0x700) /* entry */
1531 entry_inst
= inst
; /* save for later processing */
1532 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1533 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
1534 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
1536 /* This instruction is part of the prologue, but we don't
1537 need to do anything special to handle it. */
1541 /* This instruction is not an instruction typically found
1542 in a prologue, so we must have reached the end of the
1544 if (end_prologue_addr
== 0)
1545 end_prologue_addr
= cur_pc
- prev_extend_bytes
;
1549 /* The entry instruction is typically the first instruction in a function,
1550 and it stores registers at offsets relative to the value of the old SP
1551 (before the prologue). But the value of the sp parameter to this
1552 function is the new SP (after the prologue has been executed). So we
1553 can't calculate those offsets until we've seen the entire prologue,
1554 and can calculate what the old SP must have been. */
1555 if (entry_inst
!= 0)
1557 int areg_count
= (entry_inst
>> 8) & 7;
1558 int sreg_count
= (entry_inst
>> 6) & 3;
1560 /* The entry instruction always subtracts 32 from the SP. */
1563 /* Now we can calculate what the SP must have been at the
1564 start of the function prologue. */
1567 /* Check if a0-a3 were saved in the caller's argument save area. */
1568 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1570 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1571 offset
+= mips_abi_regsize (current_gdbarch
);
1574 /* Check if the ra register was pushed on the stack. */
1576 if (entry_inst
& 0x20)
1578 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1579 offset
-= mips_abi_regsize (current_gdbarch
);
1582 /* Check if the s0 and s1 registers were pushed on the stack. */
1583 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1585 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1586 offset
-= mips_abi_regsize (current_gdbarch
);
1590 if (this_cache
!= NULL
)
1593 (frame_unwind_register_signed (next_frame
,
1594 gdbarch_num_regs (current_gdbarch
)
1596 + frame_offset
- frame_adjust
);
1597 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
1598 be able to get rid of the assignment below, evetually. But it's
1599 still needed for now. */
1600 this_cache
->saved_regs
[gdbarch_num_regs (current_gdbarch
)
1601 + mips_regnum (current_gdbarch
)->pc
]
1602 = this_cache
->saved_regs
[gdbarch_num_regs (current_gdbarch
)
1606 /* If we didn't reach the end of the prologue when scanning the function
1607 instructions, then set end_prologue_addr to the address of the
1608 instruction immediately after the last one we scanned. */
1609 if (end_prologue_addr
== 0)
1610 end_prologue_addr
= cur_pc
;
1612 return end_prologue_addr
;
1615 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
1616 Procedures that use the 32-bit instruction set are handled by the
1617 mips_insn32 unwinder. */
1619 static struct mips_frame_cache
*
1620 mips_insn16_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1622 struct mips_frame_cache
*cache
;
1624 if ((*this_cache
) != NULL
)
1625 return (*this_cache
);
1626 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1627 (*this_cache
) = cache
;
1628 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1630 /* Analyze the function prologue. */
1632 const CORE_ADDR pc
=
1633 frame_unwind_address_in_block (next_frame
, NORMAL_FRAME
);
1634 CORE_ADDR start_addr
;
1636 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
1637 if (start_addr
== 0)
1638 start_addr
= heuristic_proc_start (pc
);
1639 /* We can't analyze the prologue if we couldn't find the begining
1641 if (start_addr
== 0)
1644 mips16_scan_prologue (start_addr
, pc
, next_frame
, *this_cache
);
1647 /* SP_REGNUM, contains the value and not the address. */
1648 trad_frame_set_value (cache
->saved_regs
, gdbarch_num_regs (current_gdbarch
)
1649 + MIPS_SP_REGNUM
, cache
->base
);
1651 return (*this_cache
);
1655 mips_insn16_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1656 struct frame_id
*this_id
)
1658 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1660 (*this_id
) = frame_id_build (info
->base
,
1661 frame_func_unwind (next_frame
, NORMAL_FRAME
));
1665 mips_insn16_frame_prev_register (struct frame_info
*next_frame
,
1667 int regnum
, int *optimizedp
,
1668 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1669 int *realnump
, gdb_byte
*valuep
)
1671 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1673 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
1674 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
1677 static const struct frame_unwind mips_insn16_frame_unwind
=
1680 mips_insn16_frame_this_id
,
1681 mips_insn16_frame_prev_register
1684 static const struct frame_unwind
*
1685 mips_insn16_frame_sniffer (struct frame_info
*next_frame
)
1687 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1688 if (mips_pc_is_mips16 (pc
))
1689 return &mips_insn16_frame_unwind
;
1694 mips_insn16_frame_base_address (struct frame_info
*next_frame
,
1697 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1702 static const struct frame_base mips_insn16_frame_base
=
1704 &mips_insn16_frame_unwind
,
1705 mips_insn16_frame_base_address
,
1706 mips_insn16_frame_base_address
,
1707 mips_insn16_frame_base_address
1710 static const struct frame_base
*
1711 mips_insn16_frame_base_sniffer (struct frame_info
*next_frame
)
1713 if (mips_insn16_frame_sniffer (next_frame
) != NULL
)
1714 return &mips_insn16_frame_base
;
1719 /* Mark all the registers as unset in the saved_regs array
1720 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
1723 reset_saved_regs (struct mips_frame_cache
*this_cache
)
1725 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
1729 const int num_regs
= gdbarch_num_regs (current_gdbarch
);
1732 for (i
= 0; i
< num_regs
; i
++)
1734 this_cache
->saved_regs
[i
].addr
= -1;
1739 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1740 the associated FRAME_CACHE if not null.
1741 Return the address of the first instruction past the prologue. */
1744 mips32_scan_prologue (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1745 struct frame_info
*next_frame
,
1746 struct mips_frame_cache
*this_cache
)
1749 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
1752 int frame_reg
= MIPS_SP_REGNUM
;
1754 CORE_ADDR end_prologue_addr
= 0;
1755 int seen_sp_adjust
= 0;
1756 int load_immediate_bytes
= 0;
1758 /* Can be called when there's no process, and hence when there's no
1760 if (next_frame
!= NULL
)
1761 sp
= read_next_frame_reg (next_frame
, gdbarch_num_regs (current_gdbarch
)
1766 if (limit_pc
> start_pc
+ 200)
1767 limit_pc
= start_pc
+ 200;
1772 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
1774 unsigned long inst
, high_word
, low_word
;
1777 /* Fetch the instruction. */
1778 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
1780 /* Save some code by pre-extracting some useful fields. */
1781 high_word
= (inst
>> 16) & 0xffff;
1782 low_word
= inst
& 0xffff;
1783 reg
= high_word
& 0x1f;
1785 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
1786 || high_word
== 0x23bd /* addi $sp,$sp,-i */
1787 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
1789 if (low_word
& 0x8000) /* negative stack adjustment? */
1790 frame_offset
+= 0x10000 - low_word
;
1792 /* Exit loop if a positive stack adjustment is found, which
1793 usually means that the stack cleanup code in the function
1794 epilogue is reached. */
1798 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1800 set_reg_offset (this_cache
, reg
, sp
+ low_word
);
1802 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1804 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
1805 set_reg_offset (this_cache
, reg
, sp
+ low_word
);
1807 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
1809 /* Old gcc frame, r30 is virtual frame pointer. */
1810 if ((long) low_word
!= frame_offset
)
1811 frame_addr
= sp
+ low_word
;
1812 else if (frame_reg
== MIPS_SP_REGNUM
)
1814 unsigned alloca_adjust
;
1817 frame_addr
= read_next_frame_reg (next_frame
,
1819 (current_gdbarch
) + 30);
1820 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
1821 if (alloca_adjust
> 0)
1823 /* FP > SP + frame_size. This may be because of
1824 an alloca or somethings similar. Fix sp to
1825 "pre-alloca" value, and try again. */
1826 sp
+= alloca_adjust
;
1827 /* Need to reset the status of all registers. Otherwise,
1828 we will hit a guard that prevents the new address
1829 for each register to be recomputed during the second
1831 reset_saved_regs (this_cache
);
1836 /* move $30,$sp. With different versions of gas this will be either
1837 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
1838 Accept any one of these. */
1839 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
1841 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
1842 if (frame_reg
== MIPS_SP_REGNUM
)
1844 unsigned alloca_adjust
;
1847 frame_addr
= read_next_frame_reg (next_frame
,
1849 (current_gdbarch
) + 30);
1850 alloca_adjust
= (unsigned) (frame_addr
- sp
);
1851 if (alloca_adjust
> 0)
1853 /* FP > SP + frame_size. This may be because of
1854 an alloca or somethings similar. Fix sp to
1855 "pre-alloca" value, and try again. */
1857 /* Need to reset the status of all registers. Otherwise,
1858 we will hit a guard that prevents the new address
1859 for each register to be recomputed during the second
1861 reset_saved_regs (this_cache
);
1866 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
1868 set_reg_offset (this_cache
, reg
, frame_addr
+ low_word
);
1870 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
1871 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
1872 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
1873 || high_word
== 0x3c1c /* lui $gp,n */
1874 || high_word
== 0x279c /* addiu $gp,$gp,n */
1875 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
1876 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
1879 /* These instructions are part of the prologue, but we don't
1880 need to do anything special to handle them. */
1882 /* The instructions below load $at or $t0 with an immediate
1883 value in preparation for a stack adjustment via
1884 subu $sp,$sp,[$at,$t0]. These instructions could also
1885 initialize a local variable, so we accept them only before
1886 a stack adjustment instruction was seen. */
1887 else if (!seen_sp_adjust
1888 && (high_word
== 0x3c01 /* lui $at,n */
1889 || high_word
== 0x3c08 /* lui $t0,n */
1890 || high_word
== 0x3421 /* ori $at,$at,n */
1891 || high_word
== 0x3508 /* ori $t0,$t0,n */
1892 || high_word
== 0x3401 /* ori $at,$zero,n */
1893 || high_word
== 0x3408 /* ori $t0,$zero,n */
1896 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
1900 /* This instruction is not an instruction typically found
1901 in a prologue, so we must have reached the end of the
1903 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
1904 loop now? Why would we need to continue scanning the function
1906 if (end_prologue_addr
== 0)
1907 end_prologue_addr
= cur_pc
;
1911 if (this_cache
!= NULL
)
1914 (frame_unwind_register_signed (next_frame
,
1915 gdbarch_num_regs (current_gdbarch
)
1918 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
1919 this assignment below, eventually. But it's still needed
1921 this_cache
->saved_regs
[gdbarch_num_regs (current_gdbarch
)
1922 + mips_regnum (current_gdbarch
)->pc
]
1923 = this_cache
->saved_regs
[gdbarch_num_regs (current_gdbarch
)
1927 /* If we didn't reach the end of the prologue when scanning the function
1928 instructions, then set end_prologue_addr to the address of the
1929 instruction immediately after the last one we scanned. */
1930 /* brobecker/2004-10-10: I don't think this would ever happen, but
1931 we may as well be careful and do our best if we have a null
1932 end_prologue_addr. */
1933 if (end_prologue_addr
== 0)
1934 end_prologue_addr
= cur_pc
;
1936 /* In a frameless function, we might have incorrectly
1937 skipped some load immediate instructions. Undo the skipping
1938 if the load immediate was not followed by a stack adjustment. */
1939 if (load_immediate_bytes
&& !seen_sp_adjust
)
1940 end_prologue_addr
-= load_immediate_bytes
;
1942 return end_prologue_addr
;
1945 /* Heuristic unwinder for procedures using 32-bit instructions (covers
1946 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
1947 instructions (a.k.a. MIPS16) are handled by the mips_insn16
1950 static struct mips_frame_cache
*
1951 mips_insn32_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1953 struct mips_frame_cache
*cache
;
1955 if ((*this_cache
) != NULL
)
1956 return (*this_cache
);
1958 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1959 (*this_cache
) = cache
;
1960 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1962 /* Analyze the function prologue. */
1964 const CORE_ADDR pc
=
1965 frame_unwind_address_in_block (next_frame
, NORMAL_FRAME
);
1966 CORE_ADDR start_addr
;
1968 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
1969 if (start_addr
== 0)
1970 start_addr
= heuristic_proc_start (pc
);
1971 /* We can't analyze the prologue if we couldn't find the begining
1973 if (start_addr
== 0)
1976 mips32_scan_prologue (start_addr
, pc
, next_frame
, *this_cache
);
1979 /* SP_REGNUM, contains the value and not the address. */
1980 trad_frame_set_value (cache
->saved_regs
,
1981 gdbarch_num_regs (current_gdbarch
) + MIPS_SP_REGNUM
,
1984 return (*this_cache
);
1988 mips_insn32_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1989 struct frame_id
*this_id
)
1991 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
1993 (*this_id
) = frame_id_build (info
->base
,
1994 frame_func_unwind (next_frame
, NORMAL_FRAME
));
1998 mips_insn32_frame_prev_register (struct frame_info
*next_frame
,
2000 int regnum
, int *optimizedp
,
2001 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2002 int *realnump
, gdb_byte
*valuep
)
2004 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2006 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
2007 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
2010 static const struct frame_unwind mips_insn32_frame_unwind
=
2013 mips_insn32_frame_this_id
,
2014 mips_insn32_frame_prev_register
2017 static const struct frame_unwind
*
2018 mips_insn32_frame_sniffer (struct frame_info
*next_frame
)
2020 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2021 if (! mips_pc_is_mips16 (pc
))
2022 return &mips_insn32_frame_unwind
;
2027 mips_insn32_frame_base_address (struct frame_info
*next_frame
,
2030 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2035 static const struct frame_base mips_insn32_frame_base
=
2037 &mips_insn32_frame_unwind
,
2038 mips_insn32_frame_base_address
,
2039 mips_insn32_frame_base_address
,
2040 mips_insn32_frame_base_address
2043 static const struct frame_base
*
2044 mips_insn32_frame_base_sniffer (struct frame_info
*next_frame
)
2046 if (mips_insn32_frame_sniffer (next_frame
) != NULL
)
2047 return &mips_insn32_frame_base
;
2052 static struct trad_frame_cache
*
2053 mips_stub_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
2056 CORE_ADDR start_addr
;
2057 CORE_ADDR stack_addr
;
2058 struct trad_frame_cache
*this_trad_cache
;
2060 if ((*this_cache
) != NULL
)
2061 return (*this_cache
);
2062 this_trad_cache
= trad_frame_cache_zalloc (next_frame
);
2063 (*this_cache
) = this_trad_cache
;
2065 /* The return address is in the link register. */
2066 trad_frame_set_reg_realreg (this_trad_cache
, PC_REGNUM
, MIPS_RA_REGNUM
);
2068 /* Frame ID, since it's a frameless / stackless function, no stack
2069 space is allocated and SP on entry is the current SP. */
2070 pc
= frame_pc_unwind (next_frame
);
2071 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2072 stack_addr
= frame_unwind_register_signed (next_frame
, MIPS_SP_REGNUM
);
2073 trad_frame_set_id (this_trad_cache
, frame_id_build (start_addr
, stack_addr
));
2075 /* Assume that the frame's base is the same as the
2077 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
2079 return this_trad_cache
;
2083 mips_stub_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2084 struct frame_id
*this_id
)
2086 struct trad_frame_cache
*this_trad_cache
2087 = mips_stub_frame_cache (next_frame
, this_cache
);
2088 trad_frame_get_id (this_trad_cache
, this_id
);
2092 mips_stub_frame_prev_register (struct frame_info
*next_frame
,
2094 int regnum
, int *optimizedp
,
2095 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2096 int *realnump
, gdb_byte
*valuep
)
2098 struct trad_frame_cache
*this_trad_cache
2099 = mips_stub_frame_cache (next_frame
, this_cache
);
2100 trad_frame_get_register (this_trad_cache
, next_frame
, regnum
, optimizedp
,
2101 lvalp
, addrp
, realnump
, valuep
);
2104 static const struct frame_unwind mips_stub_frame_unwind
=
2107 mips_stub_frame_this_id
,
2108 mips_stub_frame_prev_register
2111 static const struct frame_unwind
*
2112 mips_stub_frame_sniffer (struct frame_info
*next_frame
)
2114 struct obj_section
*s
;
2115 CORE_ADDR pc
= frame_unwind_address_in_block (next_frame
, NORMAL_FRAME
);
2117 if (in_plt_section (pc
, NULL
))
2118 return &mips_stub_frame_unwind
;
2120 /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */
2121 s
= find_pc_section (pc
);
2124 && strcmp (bfd_get_section_name (s
->objfile
->obfd
, s
->the_bfd_section
),
2125 ".MIPS.stubs") == 0)
2126 return &mips_stub_frame_unwind
;
2132 mips_stub_frame_base_address (struct frame_info
*next_frame
,
2135 struct trad_frame_cache
*this_trad_cache
2136 = mips_stub_frame_cache (next_frame
, this_cache
);
2137 return trad_frame_get_this_base (this_trad_cache
);
2140 static const struct frame_base mips_stub_frame_base
=
2142 &mips_stub_frame_unwind
,
2143 mips_stub_frame_base_address
,
2144 mips_stub_frame_base_address
,
2145 mips_stub_frame_base_address
2148 static const struct frame_base
*
2149 mips_stub_frame_base_sniffer (struct frame_info
*next_frame
)
2151 if (mips_stub_frame_sniffer (next_frame
) != NULL
)
2152 return &mips_stub_frame_base
;
2158 read_next_frame_reg (struct frame_info
*fi
, int regno
)
2160 /* Always a pseudo. */
2161 gdb_assert (regno
>= gdbarch_num_regs (current_gdbarch
));
2165 regcache_cooked_read_signed (current_regcache
, regno
, &val
);
2169 return frame_unwind_register_signed (fi
, regno
);
2173 /* mips_addr_bits_remove - remove useless address bits */
2176 mips_addr_bits_remove (CORE_ADDR addr
)
2178 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2179 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
2180 /* This hack is a work-around for existing boards using PMON, the
2181 simulator, and any other 64-bit targets that doesn't have true
2182 64-bit addressing. On these targets, the upper 32 bits of
2183 addresses are ignored by the hardware. Thus, the PC or SP are
2184 likely to have been sign extended to all 1s by instruction
2185 sequences that load 32-bit addresses. For example, a typical
2186 piece of code that loads an address is this:
2188 lui $r2, <upper 16 bits>
2189 ori $r2, <lower 16 bits>
2191 But the lui sign-extends the value such that the upper 32 bits
2192 may be all 1s. The workaround is simply to mask off these
2193 bits. In the future, gcc may be changed to support true 64-bit
2194 addressing, and this masking will have to be disabled. */
2195 return addr
&= 0xffffffffUL
;
2200 /* mips_software_single_step() is called just before we want to resume
2201 the inferior, if we want to single-step it but there is no hardware
2202 or kernel single-step support (MIPS on GNU/Linux for example). We find
2203 the target of the coming instruction and breakpoint it. */
2206 mips_software_single_step (struct regcache
*regcache
)
2208 CORE_ADDR pc
, next_pc
;
2210 pc
= read_register (mips_regnum (current_gdbarch
)->pc
);
2211 next_pc
= mips_next_pc (pc
);
2213 insert_single_step_breakpoint (next_pc
);
2217 /* Test whether the PC points to the return instruction at the
2218 end of a function. */
2221 mips_about_to_return (CORE_ADDR pc
)
2223 if (mips_pc_is_mips16 (pc
))
2224 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2225 generates a "jr $ra"; other times it generates code to load
2226 the return address from the stack to an accessible register (such
2227 as $a3), then a "jr" using that register. This second case
2228 is almost impossible to distinguish from an indirect jump
2229 used for switch statements, so we don't even try. */
2230 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
2232 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
2236 /* This fencepost looks highly suspicious to me. Removing it also
2237 seems suspicious as it could affect remote debugging across serial
2241 heuristic_proc_start (CORE_ADDR pc
)
2248 pc
= ADDR_BITS_REMOVE (pc
);
2250 fence
= start_pc
- heuristic_fence_post
;
2254 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
2255 fence
= VM_MIN_ADDRESS
;
2257 instlen
= mips_pc_is_mips16 (pc
) ? MIPS_INSN16_SIZE
: MIPS_INSN32_SIZE
;
2259 /* search back for previous return */
2260 for (start_pc
-= instlen
;; start_pc
-= instlen
)
2261 if (start_pc
< fence
)
2263 /* It's not clear to me why we reach this point when
2264 stop_soon, but with this test, at least we
2265 don't print out warnings for every child forked (eg, on
2266 decstation). 22apr93 rich@cygnus.com. */
2267 if (stop_soon
== NO_STOP_QUIETLY
)
2269 static int blurb_printed
= 0;
2271 warning (_("GDB can't find the start of the function at 0x%s."),
2276 /* This actually happens frequently in embedded
2277 development, when you first connect to a board
2278 and your stack pointer and pc are nowhere in
2279 particular. This message needs to give people
2280 in that situation enough information to
2281 determine that it's no big deal. */
2282 printf_filtered ("\n\
2283 GDB is unable to find the start of the function at 0x%s\n\
2284 and thus can't determine the size of that function's stack frame.\n\
2285 This means that GDB may be unable to access that stack frame, or\n\
2286 the frames below it.\n\
2287 This problem is most likely caused by an invalid program counter or\n\
2289 However, if you think GDB should simply search farther back\n\
2290 from 0x%s for code which looks like the beginning of a\n\
2291 function, you can increase the range of the search using the `set\n\
2292 heuristic-fence-post' command.\n", paddr_nz (pc
), paddr_nz (pc
));
2299 else if (mips_pc_is_mips16 (start_pc
))
2301 unsigned short inst
;
2303 /* On MIPS16, any one of the following is likely to be the
2304 start of a function:
2308 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
2309 inst
= mips_fetch_instruction (start_pc
);
2310 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
2311 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
2312 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
2313 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
2315 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2316 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2321 else if (mips_about_to_return (start_pc
))
2323 /* Skip return and its delay slot. */
2324 start_pc
+= 2 * MIPS_INSN32_SIZE
;
2331 struct mips_objfile_private
2337 /* According to the current ABI, should the type be passed in a
2338 floating-point register (assuming that there is space)? When there
2339 is no FPU, FP are not even considered as possible candidates for
2340 FP registers and, consequently this returns false - forces FP
2341 arguments into integer registers. */
2344 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
2346 return ((typecode
== TYPE_CODE_FLT
2348 && (typecode
== TYPE_CODE_STRUCT
2349 || typecode
== TYPE_CODE_UNION
)
2350 && TYPE_NFIELDS (arg_type
) == 1
2351 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type
, 0)))
2353 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
2356 /* On o32, argument passing in GPRs depends on the alignment of the type being
2357 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2360 mips_type_needs_double_align (struct type
*type
)
2362 enum type_code typecode
= TYPE_CODE (type
);
2364 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2366 else if (typecode
== TYPE_CODE_STRUCT
)
2368 if (TYPE_NFIELDS (type
) < 1)
2370 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2372 else if (typecode
== TYPE_CODE_UNION
)
2376 n
= TYPE_NFIELDS (type
);
2377 for (i
= 0; i
< n
; i
++)
2378 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2385 /* Adjust the address downward (direction of stack growth) so that it
2386 is correctly aligned for a new stack frame. */
2388 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2390 return align_down (addr
, 16);
2394 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2395 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2396 int nargs
, struct value
**args
, CORE_ADDR sp
,
2397 int struct_return
, CORE_ADDR struct_addr
)
2403 int stack_offset
= 0;
2404 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2405 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
2406 int regsize
= mips_abi_regsize (gdbarch
);
2408 /* For shared libraries, "t9" needs to point at the function
2410 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
2412 /* Set the return address register to point to the entry point of
2413 the program, where a breakpoint lies in wait. */
2414 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
2416 /* First ensure that the stack and structure return address (if any)
2417 are properly aligned. The stack has to be at least 64-bit
2418 aligned even on 32-bit machines, because doubles must be 64-bit
2419 aligned. For n32 and n64, stack frames need to be 128-bit
2420 aligned, so we round to this widest known alignment. */
2422 sp
= align_down (sp
, 16);
2423 struct_addr
= align_down (struct_addr
, 16);
2425 /* Now make space on the stack for the args. We allocate more
2426 than necessary for EABI, because the first few arguments are
2427 passed in registers, but that's OK. */
2428 for (argnum
= 0; argnum
< nargs
; argnum
++)
2429 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), regsize
);
2430 sp
-= align_up (len
, 16);
2433 fprintf_unfiltered (gdb_stdlog
,
2434 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
2435 paddr_nz (sp
), (long) align_up (len
, 16));
2437 /* Initialize the integer and float register pointers. */
2438 argreg
= MIPS_A0_REGNUM
;
2439 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
2441 /* The struct_return pointer occupies the first parameter-passing reg. */
2445 fprintf_unfiltered (gdb_stdlog
,
2446 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
2447 argreg
, paddr_nz (struct_addr
));
2448 write_register (argreg
++, struct_addr
);
2451 /* Now load as many as possible of the first arguments into
2452 registers, and push the rest onto the stack. Loop thru args
2453 from first to last. */
2454 for (argnum
= 0; argnum
< nargs
; argnum
++)
2456 const gdb_byte
*val
;
2457 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
2458 struct value
*arg
= args
[argnum
];
2459 struct type
*arg_type
= check_typedef (value_type (arg
));
2460 int len
= TYPE_LENGTH (arg_type
);
2461 enum type_code typecode
= TYPE_CODE (arg_type
);
2464 fprintf_unfiltered (gdb_stdlog
,
2465 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2466 argnum
+ 1, len
, (int) typecode
);
2468 /* The EABI passes structures that do not fit in a register by
2471 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2473 store_unsigned_integer (valbuf
, regsize
, VALUE_ADDRESS (arg
));
2474 typecode
= TYPE_CODE_PTR
;
2478 fprintf_unfiltered (gdb_stdlog
, " push");
2481 val
= value_contents (arg
);
2483 /* 32-bit ABIs always start floating point arguments in an
2484 even-numbered floating point register. Round the FP register
2485 up before the check to see if there are any FP registers
2486 left. Non MIPS_EABI targets also pass the FP in the integer
2487 registers so also round up normal registers. */
2488 if (regsize
< 8 && fp_register_arg_p (typecode
, arg_type
))
2490 if ((float_argreg
& 1))
2494 /* Floating point arguments passed in registers have to be
2495 treated specially. On 32-bit architectures, doubles
2496 are passed in register pairs; the even register gets
2497 the low word, and the odd register gets the high word.
2498 On non-EABI processors, the first two floating point arguments are
2499 also copied to general registers, because MIPS16 functions
2500 don't use float registers for arguments. This duplication of
2501 arguments in general registers can't hurt non-MIPS16 functions
2502 because those registers are normally skipped. */
2503 /* MIPS_EABI squeezes a struct that contains a single floating
2504 point value into an FP register instead of pushing it onto the
2506 if (fp_register_arg_p (typecode
, arg_type
)
2507 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2509 /* EABI32 will pass doubles in consecutive registers, even on
2510 64-bit cores. At one time, we used to check the size of
2511 `float_argreg' to determine whether or not to pass doubles
2512 in consecutive registers, but this is not sufficient for
2513 making the ABI determination. */
2514 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
2516 int low_offset
= gdbarch_byte_order (current_gdbarch
)
2517 == BFD_ENDIAN_BIG
? 4 : 0;
2518 unsigned long regval
;
2520 /* Write the low word of the double to the even register(s). */
2521 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2523 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2524 float_argreg
, phex (regval
, 4));
2525 write_register (float_argreg
++, regval
);
2527 /* Write the high word of the double to the odd register(s). */
2528 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2530 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2531 float_argreg
, phex (regval
, 4));
2532 write_register (float_argreg
++, regval
);
2536 /* This is a floating point value that fits entirely
2537 in a single register. */
2538 /* On 32 bit ABI's the float_argreg is further adjusted
2539 above to ensure that it is even register aligned. */
2540 LONGEST regval
= extract_unsigned_integer (val
, len
);
2542 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2543 float_argreg
, phex (regval
, len
));
2544 write_register (float_argreg
++, regval
);
2549 /* Copy the argument to general registers or the stack in
2550 register-sized pieces. Large arguments are split between
2551 registers and stack. */
2552 /* Note: structs whose size is not a multiple of regsize
2553 are treated specially: Irix cc passes
2554 them in registers where gcc sometimes puts them on the
2555 stack. For maximum compatibility, we will put them in
2557 int odd_sized_struct
= (len
> regsize
&& len
% regsize
!= 0);
2559 /* Note: Floating-point values that didn't fit into an FP
2560 register are only written to memory. */
2563 /* Remember if the argument was written to the stack. */
2564 int stack_used_p
= 0;
2565 int partial_len
= (len
< regsize
? len
: regsize
);
2568 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2571 /* Write this portion of the argument to the stack. */
2572 if (argreg
> MIPS_LAST_ARG_REGNUM
2574 || fp_register_arg_p (typecode
, arg_type
))
2576 /* Should shorter than int integer values be
2577 promoted to int before being stored? */
2578 int longword_offset
= 0;
2581 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
2584 && (typecode
== TYPE_CODE_INT
2585 || typecode
== TYPE_CODE_PTR
2586 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
2587 longword_offset
= regsize
- len
;
2588 else if ((typecode
== TYPE_CODE_STRUCT
2589 || typecode
== TYPE_CODE_UNION
)
2590 && TYPE_LENGTH (arg_type
) < regsize
)
2591 longword_offset
= regsize
- len
;
2596 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
2597 paddr_nz (stack_offset
));
2598 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
2599 paddr_nz (longword_offset
));
2602 addr
= sp
+ stack_offset
+ longword_offset
;
2607 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
2609 for (i
= 0; i
< partial_len
; i
++)
2611 fprintf_unfiltered (gdb_stdlog
, "%02x",
2615 write_memory (addr
, val
, partial_len
);
2618 /* Note!!! This is NOT an else clause. Odd sized
2619 structs may go thru BOTH paths. Floating point
2620 arguments will not. */
2621 /* Write this portion of the argument to a general
2622 purpose register. */
2623 if (argreg
<= MIPS_LAST_ARG_REGNUM
2624 && !fp_register_arg_p (typecode
, arg_type
))
2627 extract_unsigned_integer (val
, partial_len
);
2630 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2632 phex (regval
, regsize
));
2633 write_register (argreg
, regval
);
2640 /* Compute the the offset into the stack at which we
2641 will copy the next parameter.
2643 In the new EABI (and the NABI32), the stack_offset
2644 only needs to be adjusted when it has been used. */
2647 stack_offset
+= align_up (partial_len
, regsize
);
2651 fprintf_unfiltered (gdb_stdlog
, "\n");
2654 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
2656 /* Return adjusted stack pointer. */
2660 /* Determine the return value convention being used. */
2662 static enum return_value_convention
2663 mips_eabi_return_value (struct gdbarch
*gdbarch
,
2664 struct type
*type
, struct regcache
*regcache
,
2665 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2667 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
2668 return RETURN_VALUE_STRUCT_CONVENTION
;
2670 memset (readbuf
, 0, TYPE_LENGTH (type
));
2671 return RETURN_VALUE_REGISTER_CONVENTION
;
2675 /* N32/N64 ABI stuff. */
2678 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2679 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2680 int nargs
, struct value
**args
, CORE_ADDR sp
,
2681 int struct_return
, CORE_ADDR struct_addr
)
2687 int stack_offset
= 0;
2688 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2689 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
2691 /* For shared libraries, "t9" needs to point at the function
2693 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
2695 /* Set the return address register to point to the entry point of
2696 the program, where a breakpoint lies in wait. */
2697 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
2699 /* First ensure that the stack and structure return address (if any)
2700 are properly aligned. The stack has to be at least 64-bit
2701 aligned even on 32-bit machines, because doubles must be 64-bit
2702 aligned. For n32 and n64, stack frames need to be 128-bit
2703 aligned, so we round to this widest known alignment. */
2705 sp
= align_down (sp
, 16);
2706 struct_addr
= align_down (struct_addr
, 16);
2708 /* Now make space on the stack for the args. */
2709 for (argnum
= 0; argnum
< nargs
; argnum
++)
2710 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), MIPS64_REGSIZE
);
2711 sp
-= align_up (len
, 16);
2714 fprintf_unfiltered (gdb_stdlog
,
2715 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
2716 paddr_nz (sp
), (long) align_up (len
, 16));
2718 /* Initialize the integer and float register pointers. */
2719 argreg
= MIPS_A0_REGNUM
;
2720 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
2722 /* The struct_return pointer occupies the first parameter-passing reg. */
2726 fprintf_unfiltered (gdb_stdlog
,
2727 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
2728 argreg
, paddr_nz (struct_addr
));
2729 write_register (argreg
++, struct_addr
);
2732 /* Now load as many as possible of the first arguments into
2733 registers, and push the rest onto the stack. Loop thru args
2734 from first to last. */
2735 for (argnum
= 0; argnum
< nargs
; argnum
++)
2737 const gdb_byte
*val
;
2738 struct value
*arg
= args
[argnum
];
2739 struct type
*arg_type
= check_typedef (value_type (arg
));
2740 int len
= TYPE_LENGTH (arg_type
);
2741 enum type_code typecode
= TYPE_CODE (arg_type
);
2744 fprintf_unfiltered (gdb_stdlog
,
2745 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
2746 argnum
+ 1, len
, (int) typecode
);
2748 val
= value_contents (arg
);
2750 if (fp_register_arg_p (typecode
, arg_type
)
2751 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2753 /* This is a floating point value that fits entirely
2754 in a single register. */
2755 /* On 32 bit ABI's the float_argreg is further adjusted
2756 above to ensure that it is even register aligned. */
2757 LONGEST regval
= extract_unsigned_integer (val
, len
);
2759 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2760 float_argreg
, phex (regval
, len
));
2761 write_register (float_argreg
++, regval
);
2764 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
2765 argreg
, phex (regval
, len
));
2766 write_register (argreg
, regval
);
2771 /* Copy the argument to general registers or the stack in
2772 register-sized pieces. Large arguments are split between
2773 registers and stack. */
2774 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
2775 are treated specially: Irix cc passes them in registers
2776 where gcc sometimes puts them on the stack. For maximum
2777 compatibility, we will put them in both places. */
2778 int odd_sized_struct
= (len
> MIPS64_REGSIZE
2779 && len
% MIPS64_REGSIZE
!= 0);
2780 /* Note: Floating-point values that didn't fit into an FP
2781 register are only written to memory. */
2784 /* Remember if the argument was written to the stack. */
2785 int stack_used_p
= 0;
2786 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
2789 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2792 /* Write this portion of the argument to the stack. */
2793 if (argreg
> MIPS_LAST_ARG_REGNUM
2795 || fp_register_arg_p (typecode
, arg_type
))
2797 /* Should shorter than int integer values be
2798 promoted to int before being stored? */
2799 int longword_offset
= 0;
2802 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
2804 if ((typecode
== TYPE_CODE_INT
2805 || typecode
== TYPE_CODE_PTR
2806 || typecode
== TYPE_CODE_FLT
)
2808 longword_offset
= MIPS64_REGSIZE
- len
;
2813 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
2814 paddr_nz (stack_offset
));
2815 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
2816 paddr_nz (longword_offset
));
2819 addr
= sp
+ stack_offset
+ longword_offset
;
2824 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
2826 for (i
= 0; i
< partial_len
; i
++)
2828 fprintf_unfiltered (gdb_stdlog
, "%02x",
2832 write_memory (addr
, val
, partial_len
);
2835 /* Note!!! This is NOT an else clause. Odd sized
2836 structs may go thru BOTH paths. Floating point
2837 arguments will not. */
2838 /* Write this portion of the argument to a general
2839 purpose register. */
2840 if (argreg
<= MIPS_LAST_ARG_REGNUM
2841 && !fp_register_arg_p (typecode
, arg_type
))
2844 extract_unsigned_integer (val
, partial_len
);
2846 /* A non-floating-point argument being passed in a
2847 general register. If a struct or union, and if
2848 the remaining length is smaller than the register
2849 size, we have to adjust the register value on
2852 It does not seem to be necessary to do the
2853 same for integral types. */
2855 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
2856 && partial_len
< MIPS64_REGSIZE
2857 && (typecode
== TYPE_CODE_STRUCT
2858 || typecode
== TYPE_CODE_UNION
))
2859 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
2863 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2865 phex (regval
, MIPS64_REGSIZE
));
2866 write_register (argreg
, regval
);
2873 /* Compute the the offset into the stack at which we
2874 will copy the next parameter.
2876 In N32 (N64?), the stack_offset only needs to be
2877 adjusted when it has been used. */
2880 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
2884 fprintf_unfiltered (gdb_stdlog
, "\n");
2887 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
2889 /* Return adjusted stack pointer. */
2893 static enum return_value_convention
2894 mips_n32n64_return_value (struct gdbarch
*gdbarch
,
2895 struct type
*type
, struct regcache
*regcache
,
2896 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2898 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2899 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
2900 || TYPE_CODE (type
) == TYPE_CODE_UNION
2901 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
2902 || TYPE_LENGTH (type
) > 2 * MIPS64_REGSIZE
)
2903 return RETURN_VALUE_STRUCT_CONVENTION
;
2904 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
2905 && TYPE_LENGTH (type
) == 16
2906 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
2908 /* A 128-bit floating-point value fills both $f0 and $f2. The
2909 two registers are used in the same as memory order, so the
2910 eight bytes with the lower memory address are in $f0. */
2912 fprintf_unfiltered (gdb_stderr
, "Return float in $f0 and $f2\n");
2913 mips_xfer_register (regcache
,
2914 gdbarch_num_regs (current_gdbarch
)
2915 + mips_regnum (current_gdbarch
)->fp0
,
2916 8, gdbarch_byte_order (current_gdbarch
),
2917 readbuf
, writebuf
, 0);
2918 mips_xfer_register (regcache
,
2919 gdbarch_num_regs (current_gdbarch
)
2920 + mips_regnum (current_gdbarch
)->fp0
+ 2,
2921 8, gdbarch_byte_order (current_gdbarch
),
2922 readbuf
? readbuf
+ 8 : readbuf
,
2923 writebuf
? writebuf
+ 8 : writebuf
, 0);
2924 return RETURN_VALUE_REGISTER_CONVENTION
;
2926 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
2927 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
2929 /* A floating-point value belongs in the least significant part
2932 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
2933 mips_xfer_register (regcache
,
2934 gdbarch_num_regs (current_gdbarch
)
2935 + mips_regnum (current_gdbarch
)->fp0
,
2937 gdbarch_byte_order (current_gdbarch
),
2938 readbuf
, writebuf
, 0);
2939 return RETURN_VALUE_REGISTER_CONVENTION
;
2941 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
2942 && TYPE_NFIELDS (type
) <= 2
2943 && TYPE_NFIELDS (type
) >= 1
2944 && ((TYPE_NFIELDS (type
) == 1
2945 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
2947 || (TYPE_NFIELDS (type
) == 2
2948 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
2950 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
2952 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
2954 /* A struct that contains one or two floats. Each value is part
2955 in the least significant part of their floating point
2959 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
2960 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
2962 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
2965 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
2967 mips_xfer_register (regcache
, gdbarch_num_regs (current_gdbarch
)
2969 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
2970 gdbarch_byte_order (current_gdbarch
),
2971 readbuf
, writebuf
, offset
);
2973 return RETURN_VALUE_REGISTER_CONVENTION
;
2975 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
2976 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
2978 /* A structure or union. Extract the left justified value,
2979 regardless of the byte order. I.e. DO NOT USE
2983 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
2984 offset
< TYPE_LENGTH (type
);
2985 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
2987 int xfer
= register_size (current_gdbarch
, regnum
);
2988 if (offset
+ xfer
> TYPE_LENGTH (type
))
2989 xfer
= TYPE_LENGTH (type
) - offset
;
2991 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
2992 offset
, xfer
, regnum
);
2993 mips_xfer_register (regcache
, gdbarch_num_regs (current_gdbarch
)
2995 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
2997 return RETURN_VALUE_REGISTER_CONVENTION
;
3001 /* A scalar extract each part but least-significant-byte
3005 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3006 offset
< TYPE_LENGTH (type
);
3007 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3009 int xfer
= register_size (current_gdbarch
, regnum
);
3010 if (offset
+ xfer
> TYPE_LENGTH (type
))
3011 xfer
= TYPE_LENGTH (type
) - offset
;
3013 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3014 offset
, xfer
, regnum
);
3015 mips_xfer_register (regcache
, gdbarch_num_regs (current_gdbarch
)
3017 gdbarch_byte_order (current_gdbarch
),
3018 readbuf
, writebuf
, offset
);
3020 return RETURN_VALUE_REGISTER_CONVENTION
;
3024 /* O32 ABI stuff. */
3027 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3028 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3029 int nargs
, struct value
**args
, CORE_ADDR sp
,
3030 int struct_return
, CORE_ADDR struct_addr
)
3036 int stack_offset
= 0;
3037 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3038 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3040 /* For shared libraries, "t9" needs to point at the function
3042 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3044 /* Set the return address register to point to the entry point of
3045 the program, where a breakpoint lies in wait. */
3046 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3048 /* First ensure that the stack and structure return address (if any)
3049 are properly aligned. The stack has to be at least 64-bit
3050 aligned even on 32-bit machines, because doubles must be 64-bit
3051 aligned. For n32 and n64, stack frames need to be 128-bit
3052 aligned, so we round to this widest known alignment. */
3054 sp
= align_down (sp
, 16);
3055 struct_addr
= align_down (struct_addr
, 16);
3057 /* Now make space on the stack for the args. */
3058 for (argnum
= 0; argnum
< nargs
; argnum
++)
3060 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
3061 int arglen
= TYPE_LENGTH (arg_type
);
3063 /* Align to double-word if necessary. */
3064 if (mips_type_needs_double_align (arg_type
))
3065 len
= align_up (len
, MIPS32_REGSIZE
* 2);
3066 /* Allocate space on the stack. */
3067 len
+= align_up (arglen
, MIPS32_REGSIZE
);
3069 sp
-= align_up (len
, 16);
3072 fprintf_unfiltered (gdb_stdlog
,
3073 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
3074 paddr_nz (sp
), (long) align_up (len
, 16));
3076 /* Initialize the integer and float register pointers. */
3077 argreg
= MIPS_A0_REGNUM
;
3078 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3080 /* The struct_return pointer occupies the first parameter-passing reg. */
3084 fprintf_unfiltered (gdb_stdlog
,
3085 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
3086 argreg
, paddr_nz (struct_addr
));
3087 write_register (argreg
++, struct_addr
);
3088 stack_offset
+= MIPS32_REGSIZE
;
3091 /* Now load as many as possible of the first arguments into
3092 registers, and push the rest onto the stack. Loop thru args
3093 from first to last. */
3094 for (argnum
= 0; argnum
< nargs
; argnum
++)
3096 const gdb_byte
*val
;
3097 struct value
*arg
= args
[argnum
];
3098 struct type
*arg_type
= check_typedef (value_type (arg
));
3099 int len
= TYPE_LENGTH (arg_type
);
3100 enum type_code typecode
= TYPE_CODE (arg_type
);
3103 fprintf_unfiltered (gdb_stdlog
,
3104 "mips_o32_push_dummy_call: %d len=%d type=%d",
3105 argnum
+ 1, len
, (int) typecode
);
3107 val
= value_contents (arg
);
3109 /* 32-bit ABIs always start floating point arguments in an
3110 even-numbered floating point register. Round the FP register
3111 up before the check to see if there are any FP registers
3112 left. O32/O64 targets also pass the FP in the integer
3113 registers so also round up normal registers. */
3114 if (fp_register_arg_p (typecode
, arg_type
))
3116 if ((float_argreg
& 1))
3120 /* Floating point arguments passed in registers have to be
3121 treated specially. On 32-bit architectures, doubles
3122 are passed in register pairs; the even register gets
3123 the low word, and the odd register gets the high word.
3124 On O32/O64, the first two floating point arguments are
3125 also copied to general registers, because MIPS16 functions
3126 don't use float registers for arguments. This duplication of
3127 arguments in general registers can't hurt non-MIPS16 functions
3128 because those registers are normally skipped. */
3130 if (fp_register_arg_p (typecode
, arg_type
)
3131 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3133 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
3135 int low_offset
= gdbarch_byte_order (current_gdbarch
)
3136 == BFD_ENDIAN_BIG
? 4 : 0;
3137 unsigned long regval
;
3139 /* Write the low word of the double to the even register(s). */
3140 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3142 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3143 float_argreg
, phex (regval
, 4));
3144 write_register (float_argreg
++, regval
);
3146 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3147 argreg
, phex (regval
, 4));
3148 write_register (argreg
++, regval
);
3150 /* Write the high word of the double to the odd register(s). */
3151 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3153 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3154 float_argreg
, phex (regval
, 4));
3155 write_register (float_argreg
++, regval
);
3158 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3159 argreg
, phex (regval
, 4));
3160 write_register (argreg
++, regval
);
3164 /* This is a floating point value that fits entirely
3165 in a single register. */
3166 /* On 32 bit ABI's the float_argreg is further adjusted
3167 above to ensure that it is even register aligned. */
3168 LONGEST regval
= extract_unsigned_integer (val
, len
);
3170 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3171 float_argreg
, phex (regval
, len
));
3172 write_register (float_argreg
++, regval
);
3173 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3174 registers for each argument. The below is (my
3175 guess) to ensure that the corresponding integer
3176 register has reserved the same space. */
3178 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3179 argreg
, phex (regval
, len
));
3180 write_register (argreg
, regval
);
3183 /* Reserve space for the FP register. */
3184 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
3188 /* Copy the argument to general registers or the stack in
3189 register-sized pieces. Large arguments are split between
3190 registers and stack. */
3191 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
3192 are treated specially: Irix cc passes
3193 them in registers where gcc sometimes puts them on the
3194 stack. For maximum compatibility, we will put them in
3196 int odd_sized_struct
= (len
> MIPS32_REGSIZE
3197 && len
% MIPS32_REGSIZE
!= 0);
3198 /* Structures should be aligned to eight bytes (even arg registers)
3199 on MIPS_ABI_O32, if their first member has double precision. */
3200 if (mips_type_needs_double_align (arg_type
))
3205 stack_offset
+= MIPS32_REGSIZE
;
3210 /* Remember if the argument was written to the stack. */
3211 int stack_used_p
= 0;
3212 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
3215 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3218 /* Write this portion of the argument to the stack. */
3219 if (argreg
> MIPS_LAST_ARG_REGNUM
3220 || odd_sized_struct
)
3222 /* Should shorter than int integer values be
3223 promoted to int before being stored? */
3224 int longword_offset
= 0;
3230 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3231 paddr_nz (stack_offset
));
3232 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3233 paddr_nz (longword_offset
));
3236 addr
= sp
+ stack_offset
+ longword_offset
;
3241 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3243 for (i
= 0; i
< partial_len
; i
++)
3245 fprintf_unfiltered (gdb_stdlog
, "%02x",
3249 write_memory (addr
, val
, partial_len
);
3252 /* Note!!! This is NOT an else clause. Odd sized
3253 structs may go thru BOTH paths. */
3254 /* Write this portion of the argument to a general
3255 purpose register. */
3256 if (argreg
<= MIPS_LAST_ARG_REGNUM
)
3258 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3259 /* Value may need to be sign extended, because
3260 mips_isa_regsize() != mips_abi_regsize(). */
3262 /* A non-floating-point argument being passed in a
3263 general register. If a struct or union, and if
3264 the remaining length is smaller than the register
3265 size, we have to adjust the register value on
3268 It does not seem to be necessary to do the
3269 same for integral types.
3271 Also don't do this adjustment on O64 binaries.
3273 cagney/2001-07-23: gdb/179: Also, GCC, when
3274 outputting LE O32 with sizeof (struct) <
3275 mips_abi_regsize(), generates a left shift
3276 as part of storing the argument in a register
3277 (the left shift isn't generated when
3278 sizeof (struct) >= mips_abi_regsize()). Since
3279 it is quite possible that this is GCC
3280 contradicting the LE/O32 ABI, GDB has not been
3281 adjusted to accommodate this. Either someone
3282 needs to demonstrate that the LE/O32 ABI
3283 specifies such a left shift OR this new ABI gets
3284 identified as such and GDB gets tweaked
3287 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
3288 && partial_len
< MIPS32_REGSIZE
3289 && (typecode
== TYPE_CODE_STRUCT
3290 || typecode
== TYPE_CODE_UNION
))
3291 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
3295 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3297 phex (regval
, MIPS32_REGSIZE
));
3298 write_register (argreg
, regval
);
3301 /* Prevent subsequent floating point arguments from
3302 being passed in floating point registers. */
3303 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3309 /* Compute the the offset into the stack at which we
3310 will copy the next parameter.
3312 In older ABIs, the caller reserved space for
3313 registers that contained arguments. This was loosely
3314 refered to as their "home". Consequently, space is
3315 always allocated. */
3317 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
3321 fprintf_unfiltered (gdb_stdlog
, "\n");
3324 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3326 /* Return adjusted stack pointer. */
3330 static enum return_value_convention
3331 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
3332 struct regcache
*regcache
,
3333 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3335 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3337 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3338 || TYPE_CODE (type
) == TYPE_CODE_UNION
3339 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3340 return RETURN_VALUE_STRUCT_CONVENTION
;
3341 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3342 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3344 /* A single-precision floating-point value. It fits in the
3345 least significant part of FP0. */
3347 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3348 mips_xfer_register (regcache
,
3349 gdbarch_num_regs (current_gdbarch
)
3350 + mips_regnum (current_gdbarch
)->fp0
,
3352 gdbarch_byte_order (current_gdbarch
),
3353 readbuf
, writebuf
, 0);
3354 return RETURN_VALUE_REGISTER_CONVENTION
;
3356 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3357 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3359 /* A double-precision floating-point value. The most
3360 significant part goes in FP1, and the least significant in
3363 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
3364 switch (gdbarch_byte_order (current_gdbarch
))
3366 case BFD_ENDIAN_LITTLE
:
3367 mips_xfer_register (regcache
,
3368 gdbarch_num_regs (current_gdbarch
)
3369 + mips_regnum (current_gdbarch
)->fp0
+
3370 0, 4, gdbarch_byte_order (current_gdbarch
),
3371 readbuf
, writebuf
, 0);
3372 mips_xfer_register (regcache
,
3373 gdbarch_num_regs (current_gdbarch
)
3374 + mips_regnum (current_gdbarch
)->fp0
+ 1,
3375 4, gdbarch_byte_order (current_gdbarch
),
3376 readbuf
, writebuf
, 4);
3378 case BFD_ENDIAN_BIG
:
3379 mips_xfer_register (regcache
,
3380 gdbarch_num_regs (current_gdbarch
)
3381 + mips_regnum (current_gdbarch
)->fp0
+ 1,
3382 4, gdbarch_byte_order (current_gdbarch
),
3383 readbuf
, writebuf
, 0);
3384 mips_xfer_register (regcache
,
3385 gdbarch_num_regs (current_gdbarch
)
3386 + mips_regnum (current_gdbarch
)->fp0
+ 0,
3387 4, gdbarch_byte_order (current_gdbarch
),
3388 readbuf
, writebuf
, 4);
3391 internal_error (__FILE__
, __LINE__
, _("bad switch"));
3393 return RETURN_VALUE_REGISTER_CONVENTION
;
3396 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3397 && TYPE_NFIELDS (type
) <= 2
3398 && TYPE_NFIELDS (type
) >= 1
3399 && ((TYPE_NFIELDS (type
) == 1
3400 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3402 || (TYPE_NFIELDS (type
) == 2
3403 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3405 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
3407 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3409 /* A struct that contains one or two floats. Each value is part
3410 in the least significant part of their floating point
3412 gdb_byte reg
[MAX_REGISTER_SIZE
];
3415 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
3416 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3418 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3421 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3423 mips_xfer_register (regcache
, gdbarch_num_regs (current_gdbarch
)
3425 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3426 gdbarch_byte_order (current_gdbarch
),
3427 readbuf
, writebuf
, offset
);
3429 return RETURN_VALUE_REGISTER_CONVENTION
;
3433 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3434 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3436 /* A structure or union. Extract the left justified value,
3437 regardless of the byte order. I.e. DO NOT USE
3441 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3442 offset
< TYPE_LENGTH (type
);
3443 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3445 int xfer
= register_size (current_gdbarch
, regnum
);
3446 if (offset
+ xfer
> TYPE_LENGTH (type
))
3447 xfer
= TYPE_LENGTH (type
) - offset
;
3449 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3450 offset
, xfer
, regnum
);
3451 mips_xfer_register (regcache
, gdbarch_num_regs (current_gdbarch
)
3453 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
3455 return RETURN_VALUE_REGISTER_CONVENTION
;
3460 /* A scalar extract each part but least-significant-byte
3461 justified. o32 thinks registers are 4 byte, regardless of
3465 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3466 offset
< TYPE_LENGTH (type
);
3467 offset
+= MIPS32_REGSIZE
, regnum
++)
3469 int xfer
= MIPS32_REGSIZE
;
3470 if (offset
+ xfer
> TYPE_LENGTH (type
))
3471 xfer
= TYPE_LENGTH (type
) - offset
;
3473 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3474 offset
, xfer
, regnum
);
3475 mips_xfer_register (regcache
, gdbarch_num_regs (current_gdbarch
)
3477 gdbarch_byte_order (current_gdbarch
),
3478 readbuf
, writebuf
, offset
);
3480 return RETURN_VALUE_REGISTER_CONVENTION
;
3484 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
3488 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3489 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3491 struct value
**args
, CORE_ADDR sp
,
3492 int struct_return
, CORE_ADDR struct_addr
)
3498 int stack_offset
= 0;
3499 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3500 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3502 /* For shared libraries, "t9" needs to point at the function
3504 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3506 /* Set the return address register to point to the entry point of
3507 the program, where a breakpoint lies in wait. */
3508 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3510 /* First ensure that the stack and structure return address (if any)
3511 are properly aligned. The stack has to be at least 64-bit
3512 aligned even on 32-bit machines, because doubles must be 64-bit
3513 aligned. For n32 and n64, stack frames need to be 128-bit
3514 aligned, so we round to this widest known alignment. */
3516 sp
= align_down (sp
, 16);
3517 struct_addr
= align_down (struct_addr
, 16);
3519 /* Now make space on the stack for the args. */
3520 for (argnum
= 0; argnum
< nargs
; argnum
++)
3522 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
3523 int arglen
= TYPE_LENGTH (arg_type
);
3525 /* Allocate space on the stack. */
3526 len
+= align_up (arglen
, MIPS64_REGSIZE
);
3528 sp
-= align_up (len
, 16);
3531 fprintf_unfiltered (gdb_stdlog
,
3532 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
3533 paddr_nz (sp
), (long) align_up (len
, 16));
3535 /* Initialize the integer and float register pointers. */
3536 argreg
= MIPS_A0_REGNUM
;
3537 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3539 /* The struct_return pointer occupies the first parameter-passing reg. */
3543 fprintf_unfiltered (gdb_stdlog
,
3544 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
3545 argreg
, paddr_nz (struct_addr
));
3546 write_register (argreg
++, struct_addr
);
3547 stack_offset
+= MIPS64_REGSIZE
;
3550 /* Now load as many as possible of the first arguments into
3551 registers, and push the rest onto the stack. Loop thru args
3552 from first to last. */
3553 for (argnum
= 0; argnum
< nargs
; argnum
++)
3555 const gdb_byte
*val
;
3556 struct value
*arg
= args
[argnum
];
3557 struct type
*arg_type
= check_typedef (value_type (arg
));
3558 int len
= TYPE_LENGTH (arg_type
);
3559 enum type_code typecode
= TYPE_CODE (arg_type
);
3562 fprintf_unfiltered (gdb_stdlog
,
3563 "mips_o64_push_dummy_call: %d len=%d type=%d",
3564 argnum
+ 1, len
, (int) typecode
);
3566 val
= value_contents (arg
);
3568 /* Floating point arguments passed in registers have to be
3569 treated specially. On 32-bit architectures, doubles
3570 are passed in register pairs; the even register gets
3571 the low word, and the odd register gets the high word.
3572 On O32/O64, the first two floating point arguments are
3573 also copied to general registers, because MIPS16 functions
3574 don't use float registers for arguments. This duplication of
3575 arguments in general registers can't hurt non-MIPS16 functions
3576 because those registers are normally skipped. */
3578 if (fp_register_arg_p (typecode
, arg_type
)
3579 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3581 LONGEST regval
= extract_unsigned_integer (val
, len
);
3583 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3584 float_argreg
, phex (regval
, len
));
3585 write_register (float_argreg
++, regval
);
3587 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3588 argreg
, phex (regval
, len
));
3589 write_register (argreg
, regval
);
3591 /* Reserve space for the FP register. */
3592 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
3596 /* Copy the argument to general registers or the stack in
3597 register-sized pieces. Large arguments are split between
3598 registers and stack. */
3599 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
3600 are treated specially: Irix cc passes them in registers
3601 where gcc sometimes puts them on the stack. For maximum
3602 compatibility, we will put them in both places. */
3603 int odd_sized_struct
= (len
> MIPS64_REGSIZE
3604 && len
% MIPS64_REGSIZE
!= 0);
3607 /* Remember if the argument was written to the stack. */
3608 int stack_used_p
= 0;
3609 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
3612 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3615 /* Write this portion of the argument to the stack. */
3616 if (argreg
> MIPS_LAST_ARG_REGNUM
3617 || odd_sized_struct
)
3619 /* Should shorter than int integer values be
3620 promoted to int before being stored? */
3621 int longword_offset
= 0;
3624 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
3626 if ((typecode
== TYPE_CODE_INT
3627 || typecode
== TYPE_CODE_PTR
3628 || typecode
== TYPE_CODE_FLT
)
3630 longword_offset
= MIPS64_REGSIZE
- len
;
3635 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3636 paddr_nz (stack_offset
));
3637 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3638 paddr_nz (longword_offset
));
3641 addr
= sp
+ stack_offset
+ longword_offset
;
3646 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3648 for (i
= 0; i
< partial_len
; i
++)
3650 fprintf_unfiltered (gdb_stdlog
, "%02x",
3654 write_memory (addr
, val
, partial_len
);
3657 /* Note!!! This is NOT an else clause. Odd sized
3658 structs may go thru BOTH paths. */
3659 /* Write this portion of the argument to a general
3660 purpose register. */
3661 if (argreg
<= MIPS_LAST_ARG_REGNUM
)
3663 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3664 /* Value may need to be sign extended, because
3665 mips_isa_regsize() != mips_abi_regsize(). */
3667 /* A non-floating-point argument being passed in a
3668 general register. If a struct or union, and if
3669 the remaining length is smaller than the register
3670 size, we have to adjust the register value on
3673 It does not seem to be necessary to do the
3674 same for integral types. */
3676 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
3677 && partial_len
< MIPS64_REGSIZE
3678 && (typecode
== TYPE_CODE_STRUCT
3679 || typecode
== TYPE_CODE_UNION
))
3680 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
3684 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3686 phex (regval
, MIPS64_REGSIZE
));
3687 write_register (argreg
, regval
);
3690 /* Prevent subsequent floating point arguments from
3691 being passed in floating point registers. */
3692 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3698 /* Compute the the offset into the stack at which we
3699 will copy the next parameter.
3701 In older ABIs, the caller reserved space for
3702 registers that contained arguments. This was loosely
3703 refered to as their "home". Consequently, space is
3704 always allocated. */
3706 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
3710 fprintf_unfiltered (gdb_stdlog
, "\n");
3713 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3715 /* Return adjusted stack pointer. */
3719 static enum return_value_convention
3720 mips_o64_return_value (struct gdbarch
*gdbarch
,
3721 struct type
*type
, struct regcache
*regcache
,
3722 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3724 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3726 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3727 || TYPE_CODE (type
) == TYPE_CODE_UNION
3728 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3729 return RETURN_VALUE_STRUCT_CONVENTION
;
3730 else if (fp_register_arg_p (TYPE_CODE (type
), type
))
3732 /* A floating-point value. It fits in the least significant
3735 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3736 mips_xfer_register (regcache
,
3737 gdbarch_num_regs (current_gdbarch
)
3738 + mips_regnum (current_gdbarch
)->fp0
,
3740 gdbarch_byte_order (current_gdbarch
),
3741 readbuf
, writebuf
, 0);
3742 return RETURN_VALUE_REGISTER_CONVENTION
;
3746 /* A scalar extract each part but least-significant-byte
3750 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3751 offset
< TYPE_LENGTH (type
);
3752 offset
+= MIPS64_REGSIZE
, regnum
++)
3754 int xfer
= MIPS64_REGSIZE
;
3755 if (offset
+ xfer
> TYPE_LENGTH (type
))
3756 xfer
= TYPE_LENGTH (type
) - offset
;
3758 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3759 offset
, xfer
, regnum
);
3760 mips_xfer_register (regcache
, gdbarch_num_regs (current_gdbarch
)
3762 gdbarch_byte_order (current_gdbarch
),
3763 readbuf
, writebuf
, offset
);
3765 return RETURN_VALUE_REGISTER_CONVENTION
;
3769 /* Floating point register management.
3771 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
3772 64bit operations, these early MIPS cpus treat fp register pairs
3773 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
3774 registers and offer a compatibility mode that emulates the MIPS2 fp
3775 model. When operating in MIPS2 fp compat mode, later cpu's split
3776 double precision floats into two 32-bit chunks and store them in
3777 consecutive fp regs. To display 64-bit floats stored in this
3778 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
3779 Throw in user-configurable endianness and you have a real mess.
3781 The way this works is:
3782 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
3783 double-precision value will be split across two logical registers.
3784 The lower-numbered logical register will hold the low-order bits,
3785 regardless of the processor's endianness.
3786 - If we are on a 64-bit processor, and we are looking for a
3787 single-precision value, it will be in the low ordered bits
3788 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
3789 save slot in memory.
3790 - If we are in 64-bit mode, everything is straightforward.
3792 Note that this code only deals with "live" registers at the top of the
3793 stack. We will attempt to deal with saved registers later, when
3794 the raw/cooked register interface is in place. (We need a general
3795 interface that can deal with dynamic saved register sizes -- fp
3796 regs could be 32 bits wide in one frame and 64 on the frame above
3799 static struct type
*
3800 mips_float_register_type (void)
3802 return builtin_type_ieee_single
;
3805 static struct type
*
3806 mips_double_register_type (void)
3808 return builtin_type_ieee_double
;
3811 /* Copy a 32-bit single-precision value from the current frame
3812 into rare_buffer. */
3815 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
3816 gdb_byte
*rare_buffer
)
3818 int raw_size
= register_size (current_gdbarch
, regno
);
3819 gdb_byte
*raw_buffer
= alloca (raw_size
);
3821 if (!frame_register_read (frame
, regno
, raw_buffer
))
3822 error (_("can't read register %d (%s)"),
3823 regno
, gdbarch_register_name (current_gdbarch
, regno
));
3826 /* We have a 64-bit value for this register. Find the low-order
3830 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
3835 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
3839 memcpy (rare_buffer
, raw_buffer
, 4);
3843 /* Copy a 64-bit double-precision value from the current frame into
3844 rare_buffer. This may include getting half of it from the next
3848 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
3849 gdb_byte
*rare_buffer
)
3851 int raw_size
= register_size (current_gdbarch
, regno
);
3853 if (raw_size
== 8 && !mips2_fp_compat ())
3855 /* We have a 64-bit value for this register, and we should use
3857 if (!frame_register_read (frame
, regno
, rare_buffer
))
3858 error (_("can't read register %d (%s)"),
3859 regno
, gdbarch_register_name (current_gdbarch
, regno
));
3863 if ((regno
- mips_regnum (current_gdbarch
)->fp0
) & 1)
3864 internal_error (__FILE__
, __LINE__
,
3865 _("mips_read_fp_register_double: bad access to "
3866 "odd-numbered FP register"));
3868 /* mips_read_fp_register_single will find the correct 32 bits from
3870 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
3872 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
3873 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
3877 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
3878 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
3884 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
3886 { /* do values for FP (float) regs */
3887 gdb_byte
*raw_buffer
;
3888 double doub
, flt1
; /* doubles extracted from raw hex data */
3891 raw_buffer
= alloca (2 * register_size (current_gdbarch
,
3892 mips_regnum (current_gdbarch
)->fp0
));
3894 fprintf_filtered (file
, "%s:",
3895 gdbarch_register_name (current_gdbarch
, regnum
));
3896 fprintf_filtered (file
, "%*s",
3897 4 - (int) strlen (gdbarch_register_name
3898 (current_gdbarch
, regnum
)),
3901 if (register_size (current_gdbarch
, regnum
) == 4 || mips2_fp_compat ())
3903 /* 4-byte registers: Print hex and floating. Also print even
3904 numbered registers as doubles. */
3905 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
3906 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
3908 print_scalar_formatted (raw_buffer
, builtin_type_uint32
, 'x', 'w',
3911 fprintf_filtered (file
, " flt: ");
3913 fprintf_filtered (file
, " <invalid float> ");
3915 fprintf_filtered (file
, "%-17.9g", flt1
);
3917 if (regnum
% 2 == 0)
3919 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
3920 doub
= unpack_double (mips_double_register_type (), raw_buffer
,
3923 fprintf_filtered (file
, " dbl: ");
3925 fprintf_filtered (file
, "<invalid double>");
3927 fprintf_filtered (file
, "%-24.17g", doub
);
3932 /* Eight byte registers: print each one as hex, float and double. */
3933 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
3934 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
3936 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
3937 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv2
);
3940 print_scalar_formatted (raw_buffer
, builtin_type_uint64
, 'x', 'g',
3943 fprintf_filtered (file
, " flt: ");
3945 fprintf_filtered (file
, "<invalid float>");
3947 fprintf_filtered (file
, "%-17.9g", flt1
);
3949 fprintf_filtered (file
, " dbl: ");
3951 fprintf_filtered (file
, "<invalid double>");
3953 fprintf_filtered (file
, "%-24.17g", doub
);
3958 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
3959 int regnum
, int all
)
3961 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3962 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
3965 if (TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
3967 mips_print_fp_register (file
, frame
, regnum
);
3971 /* Get the data in raw format. */
3972 if (!frame_register_read (frame
, regnum
, raw_buffer
))
3974 fprintf_filtered (file
, "%s: [Invalid]",
3975 gdbarch_register_name (current_gdbarch
, regnum
));
3979 fputs_filtered (gdbarch_register_name (current_gdbarch
, regnum
), file
);
3981 /* The problem with printing numeric register names (r26, etc.) is that
3982 the user can't use them on input. Probably the best solution is to
3983 fix it so that either the numeric or the funky (a2, etc.) names
3984 are accepted on input. */
3985 if (regnum
< MIPS_NUMREGS
)
3986 fprintf_filtered (file
, "(r%d): ", regnum
);
3988 fprintf_filtered (file
, ": ");
3990 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
3992 register_size (current_gdbarch
,
3993 regnum
) - register_size (current_gdbarch
, regnum
);
3997 print_scalar_formatted (raw_buffer
+ offset
,
3998 register_type (gdbarch
, regnum
), 'x', 0,
4002 /* Replacement for generic do_registers_info.
4003 Print regs in pretty columns. */
4006 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4009 fprintf_filtered (file
, " ");
4010 mips_print_fp_register (file
, frame
, regnum
);
4011 fprintf_filtered (file
, "\n");
4016 /* Print a row's worth of GP (int) registers, with name labels above */
4019 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4022 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4023 /* do values for GP (int) regs */
4024 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
4025 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols per row */
4029 /* For GP registers, we print a separate row of names above the vals */
4030 for (col
= 0, regnum
= start_regnum
;
4031 col
< ncols
&& regnum
< gdbarch_num_regs (current_gdbarch
)
4032 + gdbarch_num_pseudo_regs (current_gdbarch
);
4035 if (*gdbarch_register_name (current_gdbarch
, regnum
) == '\0')
4036 continue; /* unused register */
4037 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4039 break; /* end the row: reached FP register */
4041 fprintf_filtered (file
, " ");
4042 fprintf_filtered (file
,
4043 mips_abi_regsize (current_gdbarch
) == 8 ? "%17s" : "%9s",
4044 gdbarch_register_name (current_gdbarch
, regnum
));
4051 /* print the R0 to R31 names */
4052 if ((start_regnum
% gdbarch_num_regs (current_gdbarch
)) < MIPS_NUMREGS
)
4053 fprintf_filtered (file
, "\n R%-4d",
4054 start_regnum
% gdbarch_num_regs (current_gdbarch
));
4056 fprintf_filtered (file
, "\n ");
4058 /* now print the values in hex, 4 or 8 to the row */
4059 for (col
= 0, regnum
= start_regnum
;
4060 col
< ncols
&& regnum
< gdbarch_num_regs (current_gdbarch
)
4061 + gdbarch_num_pseudo_regs (current_gdbarch
);
4064 if (*gdbarch_register_name (current_gdbarch
, regnum
) == '\0')
4065 continue; /* unused register */
4066 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4068 break; /* end row: reached FP register */
4069 /* OK: get the data in raw format. */
4070 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4071 error (_("can't read register %d (%s)"),
4072 regnum
, gdbarch_register_name (current_gdbarch
, regnum
));
4073 /* pad small registers */
4075 byte
< (mips_abi_regsize (current_gdbarch
)
4076 - register_size (current_gdbarch
, regnum
)); byte
++)
4077 printf_filtered (" ");
4078 /* Now print the register value in hex, endian order. */
4079 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
4081 register_size (current_gdbarch
,
4082 regnum
) - register_size (current_gdbarch
, regnum
);
4083 byte
< register_size (current_gdbarch
, regnum
); byte
++)
4084 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4086 for (byte
= register_size (current_gdbarch
, regnum
) - 1;
4088 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4089 fprintf_filtered (file
, " ");
4092 if (col
> 0) /* ie. if we actually printed anything... */
4093 fprintf_filtered (file
, "\n");
4098 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4101 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4102 struct frame_info
*frame
, int regnum
, int all
)
4104 if (regnum
!= -1) /* do one specified register */
4106 gdb_assert (regnum
>= gdbarch_num_regs (current_gdbarch
));
4107 if (*(gdbarch_register_name (current_gdbarch
, regnum
)) == '\0')
4108 error (_("Not a valid register for the current processor type"));
4110 mips_print_register (file
, frame
, regnum
, 0);
4111 fprintf_filtered (file
, "\n");
4114 /* do all (or most) registers */
4116 regnum
= gdbarch_num_regs (current_gdbarch
);
4117 while (regnum
< gdbarch_num_regs (current_gdbarch
)
4118 + gdbarch_num_pseudo_regs (current_gdbarch
))
4120 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4123 if (all
) /* true for "INFO ALL-REGISTERS" command */
4124 regnum
= print_fp_register_row (file
, frame
, regnum
);
4126 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
4129 regnum
= print_gp_register_row (file
, frame
, regnum
);
4134 /* Is this a branch with a delay slot? */
4137 is_delayed (unsigned long insn
)
4140 for (i
= 0; i
< NUMOPCODES
; ++i
)
4141 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4142 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4144 return (i
< NUMOPCODES
4145 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4146 | INSN_COND_BRANCH_DELAY
4147 | INSN_COND_BRANCH_LIKELY
)));
4151 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
4152 struct frame_info
*frame
)
4154 CORE_ADDR pc
= get_frame_pc (frame
);
4155 gdb_byte buf
[MIPS_INSN32_SIZE
];
4157 /* There is no branch delay slot on MIPS16. */
4158 if (mips_pc_is_mips16 (pc
))
4161 if (!breakpoint_here_p (pc
+ 4))
4164 if (!safe_frame_unwind_memory (frame
, pc
, buf
, sizeof buf
))
4165 /* If error reading memory, guess that it is not a delayed
4168 return is_delayed (extract_unsigned_integer (buf
, sizeof buf
));
4171 /* To skip prologues, I use this predicate. Returns either PC itself
4172 if the code at PC does not look like a function prologue; otherwise
4173 returns an address that (if we're lucky) follows the prologue. If
4174 LENIENT, then we must skip everything which is involved in setting
4175 up the frame (it's OK to skip more, just so long as we don't skip
4176 anything which might clobber the registers which are being saved.
4177 We must skip more in the case where part of the prologue is in the
4178 delay slot of a non-prologue instruction). */
4181 mips_skip_prologue (CORE_ADDR pc
)
4184 CORE_ADDR func_addr
;
4186 /* See if we can determine the end of the prologue via the symbol table.
4187 If so, then return either PC, or the PC after the prologue, whichever
4189 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
4191 CORE_ADDR post_prologue_pc
= skip_prologue_using_sal (func_addr
);
4192 if (post_prologue_pc
!= 0)
4193 return max (pc
, post_prologue_pc
);
4196 /* Can't determine prologue from the symbol table, need to examine
4199 /* Find an upper limit on the function prologue using the debug
4200 information. If the debug information could not be used to provide
4201 that bound, then use an arbitrary large number as the upper bound. */
4202 limit_pc
= skip_prologue_using_sal (pc
);
4204 limit_pc
= pc
+ 100; /* Magic. */
4206 if (mips_pc_is_mips16 (pc
))
4207 return mips16_scan_prologue (pc
, limit_pc
, NULL
, NULL
);
4209 return mips32_scan_prologue (pc
, limit_pc
, NULL
, NULL
);
4212 /* Root of all "set mips "/"show mips " commands. This will eventually be
4213 used for all MIPS-specific commands. */
4216 show_mips_command (char *args
, int from_tty
)
4218 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
4222 set_mips_command (char *args
, int from_tty
)
4225 ("\"set mips\" must be followed by an appropriate subcommand.\n");
4226 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
4229 /* Commands to show/set the MIPS FPU type. */
4232 show_mipsfpu_command (char *args
, int from_tty
)
4235 switch (MIPS_FPU_TYPE
)
4237 case MIPS_FPU_SINGLE
:
4238 fpu
= "single-precision";
4240 case MIPS_FPU_DOUBLE
:
4241 fpu
= "double-precision";
4244 fpu
= "absent (none)";
4247 internal_error (__FILE__
, __LINE__
, _("bad switch"));
4249 if (mips_fpu_type_auto
)
4251 ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
4255 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
4260 set_mipsfpu_command (char *args
, int from_tty
)
4263 ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
4264 show_mipsfpu_command (args
, from_tty
);
4268 set_mipsfpu_single_command (char *args
, int from_tty
)
4270 struct gdbarch_info info
;
4271 gdbarch_info_init (&info
);
4272 mips_fpu_type
= MIPS_FPU_SINGLE
;
4273 mips_fpu_type_auto
= 0;
4274 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4275 instead of relying on globals. Doing that would let generic code
4276 handle the search for this specific architecture. */
4277 if (!gdbarch_update_p (info
))
4278 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4282 set_mipsfpu_double_command (char *args
, int from_tty
)
4284 struct gdbarch_info info
;
4285 gdbarch_info_init (&info
);
4286 mips_fpu_type
= MIPS_FPU_DOUBLE
;
4287 mips_fpu_type_auto
= 0;
4288 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4289 instead of relying on globals. Doing that would let generic code
4290 handle the search for this specific architecture. */
4291 if (!gdbarch_update_p (info
))
4292 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4296 set_mipsfpu_none_command (char *args
, int from_tty
)
4298 struct gdbarch_info info
;
4299 gdbarch_info_init (&info
);
4300 mips_fpu_type
= MIPS_FPU_NONE
;
4301 mips_fpu_type_auto
= 0;
4302 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4303 instead of relying on globals. Doing that would let generic code
4304 handle the search for this specific architecture. */
4305 if (!gdbarch_update_p (info
))
4306 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4310 set_mipsfpu_auto_command (char *args
, int from_tty
)
4312 mips_fpu_type_auto
= 1;
4315 /* Attempt to identify the particular processor model by reading the
4316 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
4317 the relevant processor still exists (it dates back to '94) and
4318 secondly this is not the way to do this. The processor type should
4319 be set by forcing an architecture change. */
4322 deprecated_mips_set_processor_regs_hack (void)
4324 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4327 prid
= read_register (MIPS_PRID_REGNUM
);
4329 if ((prid
& ~0xf) == 0x700)
4330 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
4333 /* Just like reinit_frame_cache, but with the right arguments to be
4334 callable as an sfunc. */
4337 reinit_frame_cache_sfunc (char *args
, int from_tty
,
4338 struct cmd_list_element
*c
)
4340 reinit_frame_cache ();
4344 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
4346 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4348 /* FIXME: cagney/2003-06-26: Is this even necessary? The
4349 disassembler needs to be able to locally determine the ISA, and
4350 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
4352 if (mips_pc_is_mips16 (memaddr
))
4353 info
->mach
= bfd_mach_mips16
;
4355 /* Round down the instruction address to the appropriate boundary. */
4356 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
4358 /* Set the disassembler options. */
4359 if (tdep
->mips_abi
== MIPS_ABI_N32
|| tdep
->mips_abi
== MIPS_ABI_N64
)
4361 /* Set up the disassembler info, so that we get the right
4362 register names from libopcodes. */
4363 if (tdep
->mips_abi
== MIPS_ABI_N32
)
4364 info
->disassembler_options
= "gpr-names=n32";
4366 info
->disassembler_options
= "gpr-names=64";
4367 info
->flavour
= bfd_target_elf_flavour
;
4370 /* This string is not recognized explicitly by the disassembler,
4371 but it tells the disassembler to not try to guess the ABI from
4372 the bfd elf headers, such that, if the user overrides the ABI
4373 of a program linked as NewABI, the disassembly will follow the
4374 register naming conventions specified by the user. */
4375 info
->disassembler_options
= "gpr-names=32";
4377 /* Call the appropriate disassembler based on the target endian-ness. */
4378 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
4379 return print_insn_big_mips (memaddr
, info
);
4381 return print_insn_little_mips (memaddr
, info
);
4384 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
4385 counter value to determine whether a 16- or 32-bit breakpoint should be
4386 used. It returns a pointer to a string of bytes that encode a breakpoint
4387 instruction, stores the length of the string to *lenptr, and adjusts pc
4388 (if necessary) to point to the actual memory location where the
4389 breakpoint should be inserted. */
4391 static const gdb_byte
*
4392 mips_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
4394 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
4396 if (mips_pc_is_mips16 (*pcptr
))
4398 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
4399 *pcptr
= unmake_mips16_addr (*pcptr
);
4400 *lenptr
= sizeof (mips16_big_breakpoint
);
4401 return mips16_big_breakpoint
;
4405 /* The IDT board uses an unusual breakpoint value, and
4406 sometimes gets confused when it sees the usual MIPS
4407 breakpoint instruction. */
4408 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
4409 static gdb_byte pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
4410 static gdb_byte idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
4412 *lenptr
= sizeof (big_breakpoint
);
4414 if (strcmp (target_shortname
, "mips") == 0)
4415 return idt_big_breakpoint
;
4416 else if (strcmp (target_shortname
, "ddb") == 0
4417 || strcmp (target_shortname
, "pmon") == 0
4418 || strcmp (target_shortname
, "lsi") == 0)
4419 return pmon_big_breakpoint
;
4421 return big_breakpoint
;
4426 if (mips_pc_is_mips16 (*pcptr
))
4428 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
4429 *pcptr
= unmake_mips16_addr (*pcptr
);
4430 *lenptr
= sizeof (mips16_little_breakpoint
);
4431 return mips16_little_breakpoint
;
4435 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
4436 static gdb_byte pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
4437 static gdb_byte idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
4439 *lenptr
= sizeof (little_breakpoint
);
4441 if (strcmp (target_shortname
, "mips") == 0)
4442 return idt_little_breakpoint
;
4443 else if (strcmp (target_shortname
, "ddb") == 0
4444 || strcmp (target_shortname
, "pmon") == 0
4445 || strcmp (target_shortname
, "lsi") == 0)
4446 return pmon_little_breakpoint
;
4448 return little_breakpoint
;
4453 /* If PC is in a mips16 call or return stub, return the address of the target
4454 PC, which is either the callee or the caller. There are several
4455 cases which must be handled:
4457 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
4458 target PC is in $31 ($ra).
4459 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
4460 and the target PC is in $2.
4461 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4462 before the jal instruction, this is effectively a call stub
4463 and the the target PC is in $2. Otherwise this is effectively
4464 a return stub and the target PC is in $18.
4466 See the source code for the stubs in gcc/config/mips/mips16.S for
4470 mips_skip_trampoline_code (CORE_ADDR pc
)
4473 CORE_ADDR start_addr
;
4475 /* Find the starting address and name of the function containing the PC. */
4476 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
4479 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
4480 target PC is in $31 ($ra). */
4481 if (strcmp (name
, "__mips16_ret_sf") == 0
4482 || strcmp (name
, "__mips16_ret_df") == 0)
4483 return read_signed_register (MIPS_RA_REGNUM
);
4485 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
4487 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
4488 and the target PC is in $2. */
4489 if (name
[19] >= '0' && name
[19] <= '9')
4490 return read_signed_register (2);
4492 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4493 before the jal instruction, this is effectively a call stub
4494 and the the target PC is in $2. Otherwise this is effectively
4495 a return stub and the target PC is in $18. */
4496 else if (name
[19] == 's' || name
[19] == 'd')
4498 if (pc
== start_addr
)
4500 /* Check if the target of the stub is a compiler-generated
4501 stub. Such a stub for a function bar might have a name
4502 like __fn_stub_bar, and might look like this:
4507 la $1,bar (becomes a lui/addiu pair)
4509 So scan down to the lui/addi and extract the target
4510 address from those two instructions. */
4512 CORE_ADDR target_pc
= read_signed_register (2);
4516 /* See if the name of the target function is __fn_stub_*. */
4517 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) ==
4520 if (strncmp (name
, "__fn_stub_", 10) != 0
4521 && strcmp (name
, "etext") != 0
4522 && strcmp (name
, "_etext") != 0)
4525 /* Scan through this _fn_stub_ code for the lui/addiu pair.
4526 The limit on the search is arbitrarily set to 20
4527 instructions. FIXME. */
4528 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSN32_SIZE
)
4530 inst
= mips_fetch_instruction (target_pc
);
4531 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
4532 pc
= (inst
<< 16) & 0xffff0000; /* high word */
4533 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
4534 return pc
| (inst
& 0xffff); /* low word */
4537 /* Couldn't find the lui/addui pair, so return stub address. */
4541 /* This is the 'return' part of a call stub. The return
4542 address is in $r18. */
4543 return read_signed_register (18);
4546 return 0; /* not a stub */
4549 /* Convert a dbx stab register number (from `r' declaration) to a GDB
4550 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
4553 mips_stab_reg_to_regnum (int num
)
4556 if (num
>= 0 && num
< 32)
4558 else if (num
>= 38 && num
< 70)
4559 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 38;
4561 regnum
= mips_regnum (current_gdbarch
)->hi
;
4563 regnum
= mips_regnum (current_gdbarch
)->lo
;
4565 /* This will hopefully (eventually) provoke a warning. Should
4566 we be calling complaint() here? */
4567 return gdbarch_num_regs (current_gdbarch
)
4568 + gdbarch_num_pseudo_regs (current_gdbarch
);
4569 return gdbarch_num_regs (current_gdbarch
) + regnum
;
4573 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
4574 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
4577 mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num
)
4580 if (num
>= 0 && num
< 32)
4582 else if (num
>= 32 && num
< 64)
4583 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 32;
4585 regnum
= mips_regnum (current_gdbarch
)->hi
;
4587 regnum
= mips_regnum (current_gdbarch
)->lo
;
4589 /* This will hopefully (eventually) provoke a warning. Should we
4590 be calling complaint() here? */
4591 return gdbarch_num_regs (current_gdbarch
)
4592 + gdbarch_num_pseudo_regs (current_gdbarch
);
4593 return gdbarch_num_regs (current_gdbarch
) + regnum
;
4597 mips_register_sim_regno (int regnum
)
4599 /* Only makes sense to supply raw registers. */
4600 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (current_gdbarch
));
4601 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
4602 decide if it is valid. Should instead define a standard sim/gdb
4603 register numbering scheme. */
4604 if (gdbarch_register_name (current_gdbarch
,
4606 (current_gdbarch
) + regnum
) != NULL
4607 && gdbarch_register_name (current_gdbarch
,
4609 (current_gdbarch
) + regnum
)[0] != '\0')
4612 return LEGACY_SIM_REGNO_IGNORE
;
4616 /* Convert an integer into an address. Extracting the value signed
4617 guarantees a correctly sign extended address. */
4620 mips_integer_to_address (struct gdbarch
*gdbarch
,
4621 struct type
*type
, const gdb_byte
*buf
)
4623 return (CORE_ADDR
) extract_signed_integer (buf
, TYPE_LENGTH (type
));
4627 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
4629 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
4630 const char *name
= bfd_get_section_name (abfd
, sect
);
4632 if (*abip
!= MIPS_ABI_UNKNOWN
)
4635 if (strncmp (name
, ".mdebug.", 8) != 0)
4638 if (strcmp (name
, ".mdebug.abi32") == 0)
4639 *abip
= MIPS_ABI_O32
;
4640 else if (strcmp (name
, ".mdebug.abiN32") == 0)
4641 *abip
= MIPS_ABI_N32
;
4642 else if (strcmp (name
, ".mdebug.abi64") == 0)
4643 *abip
= MIPS_ABI_N64
;
4644 else if (strcmp (name
, ".mdebug.abiO64") == 0)
4645 *abip
= MIPS_ABI_O64
;
4646 else if (strcmp (name
, ".mdebug.eabi32") == 0)
4647 *abip
= MIPS_ABI_EABI32
;
4648 else if (strcmp (name
, ".mdebug.eabi64") == 0)
4649 *abip
= MIPS_ABI_EABI64
;
4651 warning (_("unsupported ABI %s."), name
+ 8);
4655 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
4657 int *lbp
= (int *) obj
;
4658 const char *name
= bfd_get_section_name (abfd
, sect
);
4660 if (strncmp (name
, ".gcc_compiled_long32", 20) == 0)
4662 else if (strncmp (name
, ".gcc_compiled_long64", 20) == 0)
4664 else if (strncmp (name
, ".gcc_compiled_long", 18) == 0)
4665 warning (_("unrecognized .gcc_compiled_longXX"));
4668 static enum mips_abi
4669 global_mips_abi (void)
4673 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
4674 if (mips_abi_strings
[i
] == mips_abi_string
)
4675 return (enum mips_abi
) i
;
4677 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
4681 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
4683 static struct target_desc
*tdesc_gp32
, *tdesc_gp64
;
4685 if (tdesc_gp32
== NULL
)
4687 /* Create feature sets with the appropriate properties. The values
4688 are not important. */
4690 tdesc_gp32
= allocate_target_description ();
4691 set_tdesc_property (tdesc_gp32
, PROPERTY_GP32
, "");
4693 tdesc_gp64
= allocate_target_description ();
4694 set_tdesc_property (tdesc_gp64
, PROPERTY_GP64
, "");
4697 /* If the size matches the set of 32-bit or 64-bit integer registers,
4698 assume that's what we've got. */
4699 register_remote_g_packet_guess (gdbarch
, 38 * 4, tdesc_gp32
);
4700 register_remote_g_packet_guess (gdbarch
, 38 * 8, tdesc_gp64
);
4702 /* If the size matches the full set of registers GDB traditionally
4703 knows about, including floating point, for either 32-bit or
4704 64-bit, assume that's what we've got. */
4705 register_remote_g_packet_guess (gdbarch
, 90 * 4, tdesc_gp32
);
4706 register_remote_g_packet_guess (gdbarch
, 90 * 8, tdesc_gp64
);
4708 /* Otherwise we don't have a useful guess. */
4711 static struct gdbarch
*
4712 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
4714 struct gdbarch
*gdbarch
;
4715 struct gdbarch_tdep
*tdep
;
4717 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
4719 enum mips_fpu_type fpu_type
;
4721 /* First of all, extract the elf_flags, if available. */
4722 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
4723 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
4724 else if (arches
!= NULL
)
4725 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
4729 fprintf_unfiltered (gdb_stdlog
,
4730 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
4732 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
4733 switch ((elf_flags
& EF_MIPS_ABI
))
4735 case E_MIPS_ABI_O32
:
4736 found_abi
= MIPS_ABI_O32
;
4738 case E_MIPS_ABI_O64
:
4739 found_abi
= MIPS_ABI_O64
;
4741 case E_MIPS_ABI_EABI32
:
4742 found_abi
= MIPS_ABI_EABI32
;
4744 case E_MIPS_ABI_EABI64
:
4745 found_abi
= MIPS_ABI_EABI64
;
4748 if ((elf_flags
& EF_MIPS_ABI2
))
4749 found_abi
= MIPS_ABI_N32
;
4751 found_abi
= MIPS_ABI_UNKNOWN
;
4755 /* GCC creates a pseudo-section whose name describes the ABI. */
4756 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
4757 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
4759 /* If we have no useful BFD information, use the ABI from the last
4760 MIPS architecture (if there is one). */
4761 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
4762 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
4764 /* Try the architecture for any hint of the correct ABI. */
4765 if (found_abi
== MIPS_ABI_UNKNOWN
4766 && info
.bfd_arch_info
!= NULL
4767 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
4769 switch (info
.bfd_arch_info
->mach
)
4771 case bfd_mach_mips3900
:
4772 found_abi
= MIPS_ABI_EABI32
;
4774 case bfd_mach_mips4100
:
4775 case bfd_mach_mips5000
:
4776 found_abi
= MIPS_ABI_EABI64
;
4778 case bfd_mach_mips8000
:
4779 case bfd_mach_mips10000
:
4780 /* On Irix, ELF64 executables use the N64 ABI. The
4781 pseudo-sections which describe the ABI aren't present
4782 on IRIX. (Even for executables created by gcc.) */
4783 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
4784 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
4785 found_abi
= MIPS_ABI_N64
;
4787 found_abi
= MIPS_ABI_N32
;
4792 /* Default 64-bit objects to N64 instead of O32. */
4793 if (found_abi
== MIPS_ABI_UNKNOWN
4794 && info
.abfd
!= NULL
4795 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
4796 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
4797 found_abi
= MIPS_ABI_N64
;
4800 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
4803 /* What has the user specified from the command line? */
4804 wanted_abi
= global_mips_abi ();
4806 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
4809 /* Now that we have found what the ABI for this binary would be,
4810 check whether the user is overriding it. */
4811 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
4812 mips_abi
= wanted_abi
;
4813 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
4814 mips_abi
= found_abi
;
4816 mips_abi
= MIPS_ABI_O32
;
4818 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
4821 /* Also used when doing an architecture lookup. */
4823 fprintf_unfiltered (gdb_stdlog
,
4824 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
4825 mips64_transfers_32bit_regs_p
);
4827 /* Determine the MIPS FPU type. */
4828 if (!mips_fpu_type_auto
)
4829 fpu_type
= mips_fpu_type
;
4830 else if (info
.bfd_arch_info
!= NULL
4831 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
4832 switch (info
.bfd_arch_info
->mach
)
4834 case bfd_mach_mips3900
:
4835 case bfd_mach_mips4100
:
4836 case bfd_mach_mips4111
:
4837 case bfd_mach_mips4120
:
4838 fpu_type
= MIPS_FPU_NONE
;
4840 case bfd_mach_mips4650
:
4841 fpu_type
= MIPS_FPU_SINGLE
;
4844 fpu_type
= MIPS_FPU_DOUBLE
;
4847 else if (arches
!= NULL
)
4848 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
4850 fpu_type
= MIPS_FPU_DOUBLE
;
4852 fprintf_unfiltered (gdb_stdlog
,
4853 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
4855 /* Check for blatant incompatibilities. */
4857 /* If we have only 32-bit registers, then we can't debug a 64-bit
4859 if (info
.target_desc
4860 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
4861 && mips_abi
!= MIPS_ABI_EABI32
4862 && mips_abi
!= MIPS_ABI_O32
)
4865 /* try to find a pre-existing architecture */
4866 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
4868 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
4870 /* MIPS needs to be pedantic about which ABI the object is
4872 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
4874 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
4876 /* Need to be pedantic about which register virtual size is
4878 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
4879 != mips64_transfers_32bit_regs_p
)
4881 /* Be pedantic about which FPU is selected. */
4882 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
4884 return arches
->gdbarch
;
4887 /* Need a new architecture. Fill in a target specific vector. */
4888 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
4889 gdbarch
= gdbarch_alloc (&info
, tdep
);
4890 tdep
->elf_flags
= elf_flags
;
4891 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
4892 tdep
->found_abi
= found_abi
;
4893 tdep
->mips_abi
= mips_abi
;
4894 tdep
->mips_fpu_type
= fpu_type
;
4895 tdep
->register_size_valid_p
= 0;
4896 tdep
->register_size
= 0;
4898 if (info
.target_desc
)
4900 /* Some useful properties can be inferred from the target. */
4901 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
4903 tdep
->register_size_valid_p
= 1;
4904 tdep
->register_size
= 4;
4906 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
4908 tdep
->register_size_valid_p
= 1;
4909 tdep
->register_size
= 8;
4913 /* Initially set everything according to the default ABI/ISA. */
4914 set_gdbarch_short_bit (gdbarch
, 16);
4915 set_gdbarch_int_bit (gdbarch
, 32);
4916 set_gdbarch_float_bit (gdbarch
, 32);
4917 set_gdbarch_double_bit (gdbarch
, 64);
4918 set_gdbarch_long_double_bit (gdbarch
, 64);
4919 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
4920 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
4921 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
4923 set_gdbarch_elf_make_msymbol_special (gdbarch
,
4924 mips_elf_make_msymbol_special
);
4926 /* Fill in the OS dependant register numbers and names. */
4928 const char **reg_names
;
4929 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
4930 struct mips_regnum
);
4931 if (info
.osabi
== GDB_OSABI_IRIX
)
4936 regnum
->badvaddr
= 66;
4939 regnum
->fp_control_status
= 69;
4940 regnum
->fp_implementation_revision
= 70;
4942 reg_names
= mips_irix_reg_names
;
4946 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
4947 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
4948 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
4949 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
4950 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
4951 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
4952 regnum
->fp_control_status
= 70;
4953 regnum
->fp_implementation_revision
= 71;
4955 if (info
.bfd_arch_info
!= NULL
4956 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
4957 reg_names
= mips_tx39_reg_names
;
4959 reg_names
= mips_generic_reg_names
;
4961 /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been
4962 replaced by read_pc? */
4963 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
4964 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
4965 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
4966 set_gdbarch_num_regs (gdbarch
, num_regs
);
4967 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
4968 set_gdbarch_register_name (gdbarch
, mips_register_name
);
4969 tdep
->mips_processor_reg_names
= reg_names
;
4970 tdep
->regnum
= regnum
;
4976 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
4977 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
4978 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
4979 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
4980 tdep
->default_mask_address_p
= 0;
4981 set_gdbarch_long_bit (gdbarch
, 32);
4982 set_gdbarch_ptr_bit (gdbarch
, 32);
4983 set_gdbarch_long_long_bit (gdbarch
, 64);
4986 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
4987 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
4988 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
4989 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
4990 tdep
->default_mask_address_p
= 0;
4991 set_gdbarch_long_bit (gdbarch
, 32);
4992 set_gdbarch_ptr_bit (gdbarch
, 32);
4993 set_gdbarch_long_long_bit (gdbarch
, 64);
4995 case MIPS_ABI_EABI32
:
4996 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
4997 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
4998 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
4999 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5000 tdep
->default_mask_address_p
= 0;
5001 set_gdbarch_long_bit (gdbarch
, 32);
5002 set_gdbarch_ptr_bit (gdbarch
, 32);
5003 set_gdbarch_long_long_bit (gdbarch
, 64);
5005 case MIPS_ABI_EABI64
:
5006 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5007 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
5008 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5009 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5010 tdep
->default_mask_address_p
= 0;
5011 set_gdbarch_long_bit (gdbarch
, 64);
5012 set_gdbarch_ptr_bit (gdbarch
, 64);
5013 set_gdbarch_long_long_bit (gdbarch
, 64);
5016 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5017 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5018 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5019 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5020 tdep
->default_mask_address_p
= 0;
5021 set_gdbarch_long_bit (gdbarch
, 32);
5022 set_gdbarch_ptr_bit (gdbarch
, 32);
5023 set_gdbarch_long_long_bit (gdbarch
, 64);
5024 set_gdbarch_long_double_bit (gdbarch
, 128);
5025 set_gdbarch_long_double_format (gdbarch
, floatformats_n32n64_long
);
5028 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5029 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5030 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5031 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5032 tdep
->default_mask_address_p
= 0;
5033 set_gdbarch_long_bit (gdbarch
, 64);
5034 set_gdbarch_ptr_bit (gdbarch
, 64);
5035 set_gdbarch_long_long_bit (gdbarch
, 64);
5036 set_gdbarch_long_double_bit (gdbarch
, 128);
5037 set_gdbarch_long_double_format (gdbarch
, floatformats_n32n64_long
);
5040 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
5043 /* GCC creates a pseudo-section whose name specifies the size of
5044 longs, since -mlong32 or -mlong64 may be used independent of
5045 other options. How those options affect pointer sizes is ABI and
5046 architecture dependent, so use them to override the default sizes
5047 set by the ABI. This table shows the relationship between ABI,
5048 -mlongXX, and size of pointers:
5050 ABI -mlongXX ptr bits
5051 --- -------- --------
5065 Note that for o32 and eabi32, pointers are always 32 bits
5066 regardless of any -mlongXX option. For all others, pointers and
5067 longs are the same, as set by -mlongXX or set by defaults.
5070 if (info
.abfd
!= NULL
)
5074 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
5077 set_gdbarch_long_bit (gdbarch
, long_bit
);
5081 case MIPS_ABI_EABI32
:
5086 case MIPS_ABI_EABI64
:
5087 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
5090 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
5095 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5096 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5099 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
5100 flag in object files because to do so would make it impossible to
5101 link with libraries compiled without "-gp32". This is
5102 unnecessarily restrictive.
5104 We could solve this problem by adding "-gp32" multilibs to gcc,
5105 but to set this flag before gcc is built with such multilibs will
5106 break too many systems.''
5108 But even more unhelpfully, the default linker output target for
5109 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
5110 for 64-bit programs - you need to change the ABI to change this,
5111 and not all gcc targets support that currently. Therefore using
5112 this flag to detect 32-bit mode would do the wrong thing given
5113 the current gcc - it would make GDB treat these 64-bit programs
5114 as 32-bit programs by default. */
5116 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
5117 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
5119 /* Add/remove bits from an address. The MIPS needs be careful to
5120 ensure that all 32 bit addresses are sign extended to 64 bits. */
5121 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
5123 /* Unwind the frame. */
5124 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
5125 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
5126 set_gdbarch_unwind_dummy_id (gdbarch
, mips_unwind_dummy_id
);
5128 /* Map debug register numbers onto internal register numbers. */
5129 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
5130 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
5131 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5132 set_gdbarch_dwarf_reg_to_regnum (gdbarch
,
5133 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5134 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
5135 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5136 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
5138 /* MIPS version of CALL_DUMMY */
5140 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
5141 replaced by a command, and all targets will default to on stack
5142 (regardless of the stack's execute status). */
5143 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
5144 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
5146 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
5147 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
5148 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
5150 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
5151 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
5153 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
5155 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
5156 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
5157 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
5159 set_gdbarch_register_type (gdbarch
, mips_register_type
);
5161 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
5163 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
5165 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
5166 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
5167 need to all be folded into the target vector. Since they are
5168 being used as guards for STOPPED_BY_WATCHPOINT, why not have
5169 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
5171 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
5173 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
5175 set_gdbarch_single_step_through_delay (gdbarch
, mips_single_step_through_delay
);
5177 /* Virtual tables. */
5178 set_gdbarch_vbit_in_delta (gdbarch
, 1);
5180 mips_register_g_packet_guesses (gdbarch
);
5182 /* Hook in OS ABI-specific overrides, if they have been registered. */
5183 gdbarch_init_osabi (info
, gdbarch
);
5185 /* Unwind the frame. */
5186 frame_unwind_append_sniffer (gdbarch
, dwarf2_frame_sniffer
);
5187 frame_unwind_append_sniffer (gdbarch
, mips_stub_frame_sniffer
);
5188 frame_unwind_append_sniffer (gdbarch
, mips_insn16_frame_sniffer
);
5189 frame_unwind_append_sniffer (gdbarch
, mips_insn32_frame_sniffer
);
5190 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
5191 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
5192 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
5193 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
5199 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
5201 struct gdbarch_info info
;
5203 /* Force the architecture to update, and (if it's a MIPS architecture)
5204 mips_gdbarch_init will take care of the rest. */
5205 gdbarch_info_init (&info
);
5206 gdbarch_update_p (info
);
5209 /* Print out which MIPS ABI is in use. */
5212 show_mips_abi (struct ui_file
*file
,
5214 struct cmd_list_element
*ignored_cmd
,
5215 const char *ignored_value
)
5217 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_mips
)
5220 "The MIPS ABI is unknown because the current architecture "
5224 enum mips_abi global_abi
= global_mips_abi ();
5225 enum mips_abi actual_abi
= mips_abi (current_gdbarch
);
5226 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
5228 if (global_abi
== MIPS_ABI_UNKNOWN
)
5231 "The MIPS ABI is set automatically (currently \"%s\").\n",
5233 else if (global_abi
== actual_abi
)
5236 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
5240 /* Probably shouldn't happen... */
5243 "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
5244 actual_abi_str
, mips_abi_strings
[global_abi
]);
5250 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
5252 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5256 int ef_mips_32bitmode
;
5257 /* Determine the ISA. */
5258 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
5276 /* Determine the size of a pointer. */
5277 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
5278 fprintf_unfiltered (file
,
5279 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
5281 fprintf_unfiltered (file
,
5282 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
5284 fprintf_unfiltered (file
,
5285 "mips_dump_tdep: ef_mips_arch = %d\n",
5287 fprintf_unfiltered (file
,
5288 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
5289 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
5290 fprintf_unfiltered (file
,
5291 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
5292 mips_mask_address_p (tdep
),
5293 tdep
->default_mask_address_p
);
5295 fprintf_unfiltered (file
,
5296 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
5297 MIPS_DEFAULT_FPU_TYPE
,
5298 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
5299 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
5300 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
5302 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI
);
5303 fprintf_unfiltered (file
,
5304 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
5306 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
5307 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
5308 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
5312 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
5315 _initialize_mips_tdep (void)
5317 static struct cmd_list_element
*mipsfpulist
= NULL
;
5318 struct cmd_list_element
*c
;
5320 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
5321 if (MIPS_ABI_LAST
+ 1
5322 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
5323 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
5325 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
5327 mips_pdr_data
= register_objfile_data ();
5329 /* Add root prefix command for all "set mips"/"show mips" commands */
5330 add_prefix_cmd ("mips", no_class
, set_mips_command
,
5331 _("Various MIPS specific commands."),
5332 &setmipscmdlist
, "set mips ", 0, &setlist
);
5334 add_prefix_cmd ("mips", no_class
, show_mips_command
,
5335 _("Various MIPS specific commands."),
5336 &showmipscmdlist
, "show mips ", 0, &showlist
);
5338 /* Allow the user to override the ABI. */
5339 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
5340 &mips_abi_string
, _("\
5341 Set the MIPS ABI used by this program."), _("\
5342 Show the MIPS ABI used by this program."), _("\
5343 This option can be set to one of:\n\
5344 auto - the default ABI associated with the current binary\n\
5353 &setmipscmdlist
, &showmipscmdlist
);
5355 /* Let the user turn off floating point and set the fence post for
5356 heuristic_proc_start. */
5358 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
5359 _("Set use of MIPS floating-point coprocessor."),
5360 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
5361 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
5362 _("Select single-precision MIPS floating-point coprocessor."),
5364 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
5365 _("Select double-precision MIPS floating-point coprocessor."),
5367 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
5368 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
5369 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
5370 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
5371 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
5372 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
5373 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
5374 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
5375 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
5376 _("Select MIPS floating-point coprocessor automatically."),
5378 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
5379 _("Show current use of MIPS floating-point coprocessor target."),
5382 /* We really would like to have both "0" and "unlimited" work, but
5383 command.c doesn't deal with that. So make it a var_zinteger
5384 because the user can always use "999999" or some such for unlimited. */
5385 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
5386 &heuristic_fence_post
, _("\
5387 Set the distance searched for the start of a function."), _("\
5388 Show the distance searched for the start of a function."), _("\
5389 If you are debugging a stripped executable, GDB needs to search through the\n\
5390 program for the start of a function. This command sets the distance of the\n\
5391 search. The only need to set it is when debugging a stripped executable."),
5392 reinit_frame_cache_sfunc
,
5393 NULL
, /* FIXME: i18n: The distance searched for the start of a function is %s. */
5394 &setlist
, &showlist
);
5396 /* Allow the user to control whether the upper bits of 64-bit
5397 addresses should be zeroed. */
5398 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
5399 &mask_address_var
, _("\
5400 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
5401 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
5402 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
5403 allow GDB to determine the correct value."),
5404 NULL
, show_mask_address
,
5405 &setmipscmdlist
, &showmipscmdlist
);
5407 /* Allow the user to control the size of 32 bit registers within the
5408 raw remote packet. */
5409 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
5410 &mips64_transfers_32bit_regs_p
, _("\
5411 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
5413 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
5415 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
5416 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
5417 64 bits for others. Use \"off\" to disable compatibility mode"),
5418 set_mips64_transfers_32bit_regs
,
5419 NULL
, /* FIXME: i18n: Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s. */
5420 &setlist
, &showlist
);
5422 /* Debug this files internals. */
5423 add_setshow_zinteger_cmd ("mips", class_maintenance
,
5425 Set mips debugging."), _("\
5426 Show mips debugging."), _("\
5427 When non-zero, mips specific debugging is enabled."),
5429 NULL
, /* FIXME: i18n: Mips debugging is currently %s. */
5430 &setdebuglist
, &showdebuglist
);