1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988-2016 Free Software Foundation, Inc.
5 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
6 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
35 #include "arch-utils.h"
38 #include "mips-tdep.h"
40 #include "reggroups.h"
41 #include "opcode/mips.h"
45 #include "sim-regno.h"
47 #include "frame-unwind.h"
48 #include "frame-base.h"
49 #include "trad-frame.h"
51 #include "floatformat.h"
53 #include "target-descriptions.h"
54 #include "dwarf2-frame.h"
55 #include "user-regs.h"
60 static const struct objfile_data
*mips_pdr_data
;
62 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
64 static int mips32_instruction_has_delay_slot (struct gdbarch
*gdbarch
,
66 static int micromips_instruction_has_delay_slot (ULONGEST insn
, int mustbe32
);
67 static int mips16_instruction_has_delay_slot (unsigned short inst
,
70 static int mips32_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
72 static int micromips_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
73 CORE_ADDR addr
, int mustbe32
);
74 static int mips16_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
75 CORE_ADDR addr
, int mustbe32
);
77 static void mips_print_float_info (struct gdbarch
*, struct ui_file
*,
78 struct frame_info
*, const char *);
80 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
81 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
82 #define ST0_FR (1 << 26)
84 /* The sizes of floating point registers. */
88 MIPS_FPU_SINGLE_REGSIZE
= 4,
89 MIPS_FPU_DOUBLE_REGSIZE
= 8
98 static const char *mips_abi_string
;
100 static const char *const mips_abi_strings
[] = {
111 /* For backwards compatibility we default to MIPS16. This flag is
112 overridden as soon as unambiguous ELF file flags tell us the
113 compressed ISA encoding used. */
114 static const char mips_compression_mips16
[] = "mips16";
115 static const char mips_compression_micromips
[] = "micromips";
116 static const char *const mips_compression_strings
[] =
118 mips_compression_mips16
,
119 mips_compression_micromips
,
123 static const char *mips_compression_string
= mips_compression_mips16
;
125 /* The standard register names, and all the valid aliases for them. */
126 struct register_alias
132 /* Aliases for o32 and most other ABIs. */
133 const struct register_alias mips_o32_aliases
[] = {
140 /* Aliases for n32 and n64. */
141 const struct register_alias mips_n32_n64_aliases
[] = {
148 /* Aliases for ABI-independent registers. */
149 const struct register_alias mips_register_aliases
[] = {
150 /* The architecture manuals specify these ABI-independent names for
152 #define R(n) { "r" #n, n }
153 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
154 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
155 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
156 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
159 /* k0 and k1 are sometimes called these instead (for "kernel
164 /* This is the traditional GDB name for the CP0 status register. */
165 { "sr", MIPS_PS_REGNUM
},
167 /* This is the traditional GDB name for the CP0 BadVAddr register. */
168 { "bad", MIPS_EMBED_BADVADDR_REGNUM
},
170 /* This is the traditional GDB name for the FCSR. */
171 { "fsr", MIPS_EMBED_FP0_REGNUM
+ 32 }
174 const struct register_alias mips_numeric_register_aliases
[] = {
175 #define R(n) { #n, n }
176 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
177 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
178 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
179 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
183 #ifndef MIPS_DEFAULT_FPU_TYPE
184 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
186 static int mips_fpu_type_auto
= 1;
187 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
189 static unsigned int mips_debug
= 0;
191 /* Properties (for struct target_desc) describing the g/G packet
193 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
194 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
196 struct target_desc
*mips_tdesc_gp32
;
197 struct target_desc
*mips_tdesc_gp64
;
199 const struct mips_regnum
*
200 mips_regnum (struct gdbarch
*gdbarch
)
202 return gdbarch_tdep (gdbarch
)->regnum
;
206 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
208 return mips_regnum (gdbarch
)->fp0
+ 12;
211 /* Return 1 if REGNUM refers to a floating-point general register, raw
212 or cooked. Otherwise return 0. */
215 mips_float_register_p (struct gdbarch
*gdbarch
, int regnum
)
217 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
219 return (rawnum
>= mips_regnum (gdbarch
)->fp0
220 && rawnum
< mips_regnum (gdbarch
)->fp0
+ 32);
223 #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \
225 || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64)
227 #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \
228 (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum)
230 #define MIPS_LAST_ARG_REGNUM(gdbarch) \
231 (gdbarch_tdep (gdbarch)->mips_last_arg_regnum)
233 #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type)
235 /* Return the MIPS ABI associated with GDBARCH. */
237 mips_abi (struct gdbarch
*gdbarch
)
239 return gdbarch_tdep (gdbarch
)->mips_abi
;
243 mips_isa_regsize (struct gdbarch
*gdbarch
)
245 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
247 /* If we know how big the registers are, use that size. */
248 if (tdep
->register_size_valid_p
)
249 return tdep
->register_size
;
251 /* Fall back to the previous behavior. */
252 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
253 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
256 /* Return the currently configured (or set) saved register size. */
259 mips_abi_regsize (struct gdbarch
*gdbarch
)
261 switch (mips_abi (gdbarch
))
263 case MIPS_ABI_EABI32
:
269 case MIPS_ABI_EABI64
:
271 case MIPS_ABI_UNKNOWN
:
274 internal_error (__FILE__
, __LINE__
, _("bad switch"));
278 /* MIPS16/microMIPS function addresses are odd (bit 0 is set). Here
279 are some functions to handle addresses associated with compressed
280 code including but not limited to testing, setting, or clearing
281 bit 0 of such addresses. */
283 /* Return one iff compressed code is the MIPS16 instruction set. */
286 is_mips16_isa (struct gdbarch
*gdbarch
)
288 return gdbarch_tdep (gdbarch
)->mips_isa
== ISA_MIPS16
;
291 /* Return one iff compressed code is the microMIPS instruction set. */
294 is_micromips_isa (struct gdbarch
*gdbarch
)
296 return gdbarch_tdep (gdbarch
)->mips_isa
== ISA_MICROMIPS
;
299 /* Return one iff ADDR denotes compressed code. */
302 is_compact_addr (CORE_ADDR addr
)
307 /* Return one iff ADDR denotes standard ISA code. */
310 is_mips_addr (CORE_ADDR addr
)
312 return !is_compact_addr (addr
);
315 /* Return one iff ADDR denotes MIPS16 code. */
318 is_mips16_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
320 return is_compact_addr (addr
) && is_mips16_isa (gdbarch
);
323 /* Return one iff ADDR denotes microMIPS code. */
326 is_micromips_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
328 return is_compact_addr (addr
) && is_micromips_isa (gdbarch
);
331 /* Strip the ISA (compression) bit off from ADDR. */
334 unmake_compact_addr (CORE_ADDR addr
)
336 return ((addr
) & ~(CORE_ADDR
) 1);
339 /* Add the ISA (compression) bit to ADDR. */
342 make_compact_addr (CORE_ADDR addr
)
344 return ((addr
) | (CORE_ADDR
) 1);
347 /* Extern version of unmake_compact_addr; we use a separate function
348 so that unmake_compact_addr can be inlined throughout this file. */
351 mips_unmake_compact_addr (CORE_ADDR addr
)
353 return unmake_compact_addr (addr
);
356 /* Functions for setting and testing a bit in a minimal symbol that
357 marks it as MIPS16 or microMIPS function. The MSB of the minimal
358 symbol's "info" field is used for this purpose.
360 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is
361 "special", i.e. refers to a MIPS16 or microMIPS function, and sets
362 one of the "special" bits in a minimal symbol to mark it accordingly.
363 The test checks an ELF-private flag that is valid for true function
364 symbols only; for synthetic symbols such as for PLT stubs that have
365 no ELF-private part at all the MIPS BFD backend arranges for this
366 information to be carried in the asymbol's udata field instead.
368 msymbol_is_mips16 and msymbol_is_micromips test the "special" bit
369 in a minimal symbol. */
372 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
374 elf_symbol_type
*elfsym
= (elf_symbol_type
*) sym
;
375 unsigned char st_other
;
377 if ((sym
->flags
& BSF_SYNTHETIC
) == 0)
378 st_other
= elfsym
->internal_elf_sym
.st_other
;
379 else if ((sym
->flags
& BSF_FUNCTION
) != 0)
380 st_other
= sym
->udata
.i
;
384 if (ELF_ST_IS_MICROMIPS (st_other
))
386 MSYMBOL_TARGET_FLAG_MICROMIPS (msym
) = 1;
387 SET_MSYMBOL_VALUE_ADDRESS (msym
, MSYMBOL_VALUE_RAW_ADDRESS (msym
) | 1);
389 else if (ELF_ST_IS_MIPS16 (st_other
))
391 MSYMBOL_TARGET_FLAG_MIPS16 (msym
) = 1;
392 SET_MSYMBOL_VALUE_ADDRESS (msym
, MSYMBOL_VALUE_RAW_ADDRESS (msym
) | 1);
396 /* Return one iff MSYM refers to standard ISA code. */
399 msymbol_is_mips (struct minimal_symbol
*msym
)
401 return !(MSYMBOL_TARGET_FLAG_MIPS16 (msym
)
402 | MSYMBOL_TARGET_FLAG_MICROMIPS (msym
));
405 /* Return one iff MSYM refers to MIPS16 code. */
408 msymbol_is_mips16 (struct minimal_symbol
*msym
)
410 return MSYMBOL_TARGET_FLAG_MIPS16 (msym
);
413 /* Return one iff MSYM refers to microMIPS code. */
416 msymbol_is_micromips (struct minimal_symbol
*msym
)
418 return MSYMBOL_TARGET_FLAG_MICROMIPS (msym
);
421 /* Set the ISA bit in the main symbol too, complementing the corresponding
422 minimal symbol setting and reflecting the run-time value of the symbol.
423 The need for comes from the ISA bit having been cleared as code in
424 `_bfd_mips_elf_symbol_processing' separated it into the ELF symbol's
425 `st_other' STO_MIPS16 or STO_MICROMIPS annotation, making the values
426 of symbols referring to compressed code different in GDB to the values
427 used by actual code. That in turn makes them evaluate incorrectly in
428 expressions, producing results different to what the same expressions
429 yield when compiled into the program being debugged. */
432 mips_make_symbol_special (struct symbol
*sym
, struct objfile
*objfile
)
434 if (SYMBOL_CLASS (sym
) == LOC_BLOCK
)
436 /* We are in symbol reading so it is OK to cast away constness. */
437 struct block
*block
= (struct block
*) SYMBOL_BLOCK_VALUE (sym
);
438 CORE_ADDR compact_block_start
;
439 struct bound_minimal_symbol msym
;
441 compact_block_start
= BLOCK_START (block
) | 1;
442 msym
= lookup_minimal_symbol_by_pc (compact_block_start
);
443 if (msym
.minsym
&& !msymbol_is_mips (msym
.minsym
))
445 BLOCK_START (block
) = compact_block_start
;
450 /* XFER a value from the big/little/left end of the register.
451 Depending on the size of the value it might occupy the entire
452 register or just part of it. Make an allowance for this, aligning
453 things accordingly. */
456 mips_xfer_register (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
457 int reg_num
, int length
,
458 enum bfd_endian endian
, gdb_byte
*in
,
459 const gdb_byte
*out
, int buf_offset
)
463 gdb_assert (reg_num
>= gdbarch_num_regs (gdbarch
));
464 /* Need to transfer the left or right part of the register, based on
465 the targets byte order. */
469 reg_offset
= register_size (gdbarch
, reg_num
) - length
;
471 case BFD_ENDIAN_LITTLE
:
474 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
478 internal_error (__FILE__
, __LINE__
, _("bad switch"));
481 fprintf_unfiltered (gdb_stderr
,
482 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
483 reg_num
, reg_offset
, buf_offset
, length
);
484 if (mips_debug
&& out
!= NULL
)
487 fprintf_unfiltered (gdb_stdlog
, "out ");
488 for (i
= 0; i
< length
; i
++)
489 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
492 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
495 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
497 if (mips_debug
&& in
!= NULL
)
500 fprintf_unfiltered (gdb_stdlog
, "in ");
501 for (i
= 0; i
< length
; i
++)
502 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
505 fprintf_unfiltered (gdb_stdlog
, "\n");
508 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
509 compatiblity mode. A return value of 1 means that we have
510 physical 64-bit registers, but should treat them as 32-bit registers. */
513 mips2_fp_compat (struct frame_info
*frame
)
515 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
516 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
518 if (register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) == 4)
522 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
523 in all the places we deal with FP registers. PR gdb/413. */
524 /* Otherwise check the FR bit in the status register - it controls
525 the FP compatiblity mode. If it is clear we are in compatibility
527 if ((get_frame_register_unsigned (frame
, MIPS_PS_REGNUM
) & ST0_FR
) == 0)
534 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
536 static CORE_ADDR
heuristic_proc_start (struct gdbarch
*, CORE_ADDR
);
538 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
540 /* The list of available "set mips " and "show mips " commands. */
542 static struct cmd_list_element
*setmipscmdlist
= NULL
;
543 static struct cmd_list_element
*showmipscmdlist
= NULL
;
545 /* Integer registers 0 thru 31 are handled explicitly by
546 mips_register_name(). Processor specific registers 32 and above
547 are listed in the following tables. */
550 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
554 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
555 "sr", "lo", "hi", "bad", "cause", "pc",
556 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
557 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
558 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
559 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
563 /* Names of IDT R3041 registers. */
565 static const char *mips_r3041_reg_names
[] = {
566 "sr", "lo", "hi", "bad", "cause", "pc",
567 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
568 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
569 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
570 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
571 "fsr", "fir", "", /*"fp" */ "",
572 "", "", "bus", "ccfg", "", "", "", "",
573 "", "", "port", "cmp", "", "", "epc", "prid",
576 /* Names of tx39 registers. */
578 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
579 "sr", "lo", "hi", "bad", "cause", "pc",
580 "", "", "", "", "", "", "", "",
581 "", "", "", "", "", "", "", "",
582 "", "", "", "", "", "", "", "",
583 "", "", "", "", "", "", "", "",
585 "", "", "", "", "", "", "", "",
586 "", "", "config", "cache", "debug", "depc", "epc",
589 /* Names of registers with Linux kernels. */
590 static const char *mips_linux_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
591 "sr", "lo", "hi", "bad", "cause", "pc",
592 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
593 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
594 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
595 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
600 /* Return the name of the register corresponding to REGNO. */
602 mips_register_name (struct gdbarch
*gdbarch
, int regno
)
604 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
605 /* GPR names for all ABIs other than n32/n64. */
606 static char *mips_gpr_names
[] = {
607 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
608 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
609 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
610 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
613 /* GPR names for n32 and n64 ABIs. */
614 static char *mips_n32_n64_gpr_names
[] = {
615 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
616 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
617 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
618 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
621 enum mips_abi abi
= mips_abi (gdbarch
);
623 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
624 but then don't make the raw register names visible. This (upper)
625 range of user visible register numbers are the pseudo-registers.
627 This approach was adopted accommodate the following scenario:
628 It is possible to debug a 64-bit device using a 32-bit
629 programming model. In such instances, the raw registers are
630 configured to be 64-bits wide, while the pseudo registers are
631 configured to be 32-bits wide. The registers that the user
632 sees - the pseudo registers - match the users expectations
633 given the programming model being used. */
634 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
635 if (regno
< gdbarch_num_regs (gdbarch
))
638 /* The MIPS integer registers are always mapped from 0 to 31. The
639 names of the registers (which reflects the conventions regarding
640 register use) vary depending on the ABI. */
641 if (0 <= rawnum
&& rawnum
< 32)
643 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
644 return mips_n32_n64_gpr_names
[rawnum
];
646 return mips_gpr_names
[rawnum
];
648 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
649 return tdesc_register_name (gdbarch
, rawnum
);
650 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (gdbarch
))
652 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
653 if (tdep
->mips_processor_reg_names
[rawnum
- 32])
654 return tdep
->mips_processor_reg_names
[rawnum
- 32];
658 internal_error (__FILE__
, __LINE__
,
659 _("mips_register_name: bad register number %d"), rawnum
);
662 /* Return the groups that a MIPS register can be categorised into. */
665 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
666 struct reggroup
*reggroup
)
671 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
672 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
673 if (reggroup
== all_reggroup
)
675 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
676 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
677 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
678 (gdbarch), as not all architectures are multi-arch. */
679 raw_p
= rawnum
< gdbarch_num_regs (gdbarch
);
680 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
681 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
683 if (reggroup
== float_reggroup
)
684 return float_p
&& pseudo
;
685 if (reggroup
== vector_reggroup
)
686 return vector_p
&& pseudo
;
687 if (reggroup
== general_reggroup
)
688 return (!vector_p
&& !float_p
) && pseudo
;
689 /* Save the pseudo registers. Need to make certain that any code
690 extracting register values from a saved register cache also uses
692 if (reggroup
== save_reggroup
)
693 return raw_p
&& pseudo
;
694 /* Restore the same pseudo register. */
695 if (reggroup
== restore_reggroup
)
696 return raw_p
&& pseudo
;
700 /* Return the groups that a MIPS register can be categorised into.
701 This version is only used if we have a target description which
702 describes real registers (and their groups). */
705 mips_tdesc_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
706 struct reggroup
*reggroup
)
708 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
709 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
712 /* Only save, restore, and display the pseudo registers. Need to
713 make certain that any code extracting register values from a
714 saved register cache also uses pseudo registers.
716 Note: saving and restoring the pseudo registers is slightly
717 strange; if we have 64 bits, we should save and restore all
718 64 bits. But this is hard and has little benefit. */
722 ret
= tdesc_register_in_reggroup_p (gdbarch
, rawnum
, reggroup
);
726 return mips_register_reggroup_p (gdbarch
, regnum
, reggroup
);
729 /* Map the symbol table registers which live in the range [1 *
730 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
731 registers. Take care of alignment and size problems. */
733 static enum register_status
734 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
735 int cookednum
, gdb_byte
*buf
)
737 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
738 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
739 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
740 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
741 return regcache_raw_read (regcache
, rawnum
, buf
);
742 else if (register_size (gdbarch
, rawnum
) >
743 register_size (gdbarch
, cookednum
))
745 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
746 return regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
749 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
751 enum register_status status
;
753 status
= regcache_raw_read_signed (regcache
, rawnum
, ®val
);
754 if (status
== REG_VALID
)
755 store_signed_integer (buf
, 4, byte_order
, regval
);
760 internal_error (__FILE__
, __LINE__
, _("bad register size"));
764 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
765 struct regcache
*regcache
, int cookednum
,
768 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
769 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
770 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
771 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
772 regcache_raw_write (regcache
, rawnum
, buf
);
773 else if (register_size (gdbarch
, rawnum
) >
774 register_size (gdbarch
, cookednum
))
776 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
777 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
780 /* Sign extend the shortened version of the register prior
781 to placing it in the raw register. This is required for
782 some mips64 parts in order to avoid unpredictable behavior. */
783 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
784 LONGEST regval
= extract_signed_integer (buf
, 4, byte_order
);
785 regcache_raw_write_signed (regcache
, rawnum
, regval
);
789 internal_error (__FILE__
, __LINE__
, _("bad register size"));
793 mips_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
794 struct agent_expr
*ax
, int reg
)
796 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
797 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
798 && reg
< 2 * gdbarch_num_regs (gdbarch
));
800 ax_reg_mask (ax
, rawnum
);
806 mips_ax_pseudo_register_push_stack (struct gdbarch
*gdbarch
,
807 struct agent_expr
*ax
, int reg
)
809 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
810 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
811 && reg
< 2 * gdbarch_num_regs (gdbarch
));
812 if (register_size (gdbarch
, rawnum
) >= register_size (gdbarch
, reg
))
816 if (register_size (gdbarch
, rawnum
) > register_size (gdbarch
, reg
))
818 if (!gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
819 || gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_BIG
)
822 ax_simple (ax
, aop_lsh
);
825 ax_simple (ax
, aop_rsh_signed
);
829 internal_error (__FILE__
, __LINE__
, _("bad register size"));
834 /* Table to translate 3-bit register field to actual register number. */
835 static const signed char mips_reg3_to_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
837 /* Heuristic_proc_start may hunt through the text section for a long
838 time across a 2400 baud serial line. Allows the user to limit this
841 static int heuristic_fence_post
= 0;
843 /* Number of bytes of storage in the actual machine representation for
844 register N. NOTE: This defines the pseudo register type so need to
845 rebuild the architecture vector. */
847 static int mips64_transfers_32bit_regs_p
= 0;
850 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
851 struct cmd_list_element
*c
)
853 struct gdbarch_info info
;
854 gdbarch_info_init (&info
);
855 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
856 instead of relying on globals. Doing that would let generic code
857 handle the search for this specific architecture. */
858 if (!gdbarch_update_p (info
))
860 mips64_transfers_32bit_regs_p
= 0;
861 error (_("32-bit compatibility mode not supported"));
865 /* Convert to/from a register and the corresponding memory value. */
867 /* This predicate tests for the case of an 8 byte floating point
868 value that is being transferred to or from a pair of floating point
869 registers each of which are (or are considered to be) only 4 bytes
872 mips_convert_register_float_case_p (struct gdbarch
*gdbarch
, int regnum
,
875 return (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
876 && register_size (gdbarch
, regnum
) == 4
877 && mips_float_register_p (gdbarch
, regnum
)
878 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
881 /* This predicate tests for the case of a value of less than 8
882 bytes in width that is being transfered to or from an 8 byte
883 general purpose register. */
885 mips_convert_register_gpreg_case_p (struct gdbarch
*gdbarch
, int regnum
,
888 int num_regs
= gdbarch_num_regs (gdbarch
);
890 return (register_size (gdbarch
, regnum
) == 8
891 && regnum
% num_regs
> 0 && regnum
% num_regs
< 32
892 && TYPE_LENGTH (type
) < 8);
896 mips_convert_register_p (struct gdbarch
*gdbarch
,
897 int regnum
, struct type
*type
)
899 return (mips_convert_register_float_case_p (gdbarch
, regnum
, type
)
900 || mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
));
904 mips_register_to_value (struct frame_info
*frame
, int regnum
,
905 struct type
*type
, gdb_byte
*to
,
906 int *optimizedp
, int *unavailablep
)
908 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
910 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
912 get_frame_register (frame
, regnum
+ 0, to
+ 4);
913 get_frame_register (frame
, regnum
+ 1, to
+ 0);
915 if (!get_frame_register_bytes (frame
, regnum
+ 0, 0, 4, to
+ 4,
916 optimizedp
, unavailablep
))
919 if (!get_frame_register_bytes (frame
, regnum
+ 1, 0, 4, to
+ 0,
920 optimizedp
, unavailablep
))
922 *optimizedp
= *unavailablep
= 0;
925 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
927 int len
= TYPE_LENGTH (type
);
930 offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 8 - len
: 0;
931 if (!get_frame_register_bytes (frame
, regnum
, offset
, len
, to
,
932 optimizedp
, unavailablep
))
935 *optimizedp
= *unavailablep
= 0;
940 internal_error (__FILE__
, __LINE__
,
941 _("mips_register_to_value: unrecognized case"));
946 mips_value_to_register (struct frame_info
*frame
, int regnum
,
947 struct type
*type
, const gdb_byte
*from
)
949 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
951 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
953 put_frame_register (frame
, regnum
+ 0, from
+ 4);
954 put_frame_register (frame
, regnum
+ 1, from
+ 0);
956 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
959 int len
= TYPE_LENGTH (type
);
961 /* Sign extend values, irrespective of type, that are stored to
962 a 64-bit general purpose register. (32-bit unsigned values
963 are stored as signed quantities within a 64-bit register.
964 When performing an operation, in compiled code, that combines
965 a 32-bit unsigned value with a signed 64-bit value, a type
966 conversion is first performed that zeroes out the high 32 bits.) */
967 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
970 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, -1);
972 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, 0);
973 put_frame_register_bytes (frame
, regnum
, 0, 8 - len
, fill
);
974 put_frame_register_bytes (frame
, regnum
, 8 - len
, len
, from
);
978 if (from
[len
-1] & 0x80)
979 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, -1);
981 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, 0);
982 put_frame_register_bytes (frame
, regnum
, 0, len
, from
);
983 put_frame_register_bytes (frame
, regnum
, len
, 8 - len
, fill
);
988 internal_error (__FILE__
, __LINE__
,
989 _("mips_value_to_register: unrecognized case"));
993 /* Return the GDB type object for the "standard" data type of data in
997 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
999 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (gdbarch
));
1000 if (mips_float_register_p (gdbarch
, regnum
))
1002 /* The floating-point registers raw, or cooked, always match
1003 mips_isa_regsize(), and also map 1:1, byte for byte. */
1004 if (mips_isa_regsize (gdbarch
) == 4)
1005 return builtin_type (gdbarch
)->builtin_float
;
1007 return builtin_type (gdbarch
)->builtin_double
;
1009 else if (regnum
< gdbarch_num_regs (gdbarch
))
1011 /* The raw or ISA registers. These are all sized according to
1013 if (mips_isa_regsize (gdbarch
) == 4)
1014 return builtin_type (gdbarch
)->builtin_int32
;
1016 return builtin_type (gdbarch
)->builtin_int64
;
1020 int rawnum
= regnum
- gdbarch_num_regs (gdbarch
);
1022 /* The cooked or ABI registers. These are sized according to
1023 the ABI (with a few complications). */
1024 if (rawnum
== mips_regnum (gdbarch
)->fp_control_status
1025 || rawnum
== mips_regnum (gdbarch
)->fp_implementation_revision
)
1026 return builtin_type (gdbarch
)->builtin_int32
;
1027 else if (gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
1028 && rawnum
>= MIPS_FIRST_EMBED_REGNUM
1029 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
1030 /* The pseudo/cooked view of the embedded registers is always
1031 32-bit. The raw view is handled below. */
1032 return builtin_type (gdbarch
)->builtin_int32
;
1033 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
1034 /* The target, while possibly using a 64-bit register buffer,
1035 is only transfering 32-bits of each integer register.
1036 Reflect this in the cooked/pseudo (ABI) register value. */
1037 return builtin_type (gdbarch
)->builtin_int32
;
1038 else if (mips_abi_regsize (gdbarch
) == 4)
1039 /* The ABI is restricted to 32-bit registers (the ISA could be
1041 return builtin_type (gdbarch
)->builtin_int32
;
1044 return builtin_type (gdbarch
)->builtin_int64
;
1048 /* Return the GDB type for the pseudo register REGNUM, which is the
1049 ABI-level view. This function is only called if there is a target
1050 description which includes registers, so we know precisely the
1051 types of hardware registers. */
1053 static struct type
*
1054 mips_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
1056 const int num_regs
= gdbarch_num_regs (gdbarch
);
1057 int rawnum
= regnum
% num_regs
;
1058 struct type
*rawtype
;
1060 gdb_assert (regnum
>= num_regs
&& regnum
< 2 * num_regs
);
1062 /* Absent registers are still absent. */
1063 rawtype
= gdbarch_register_type (gdbarch
, rawnum
);
1064 if (TYPE_LENGTH (rawtype
) == 0)
1067 /* Present the floating point registers however the hardware did;
1068 do not try to convert between FPU layouts. */
1069 if (mips_float_register_p (gdbarch
, rawnum
))
1072 /* Floating-point control registers are always 32-bit even though for
1073 backwards compatibility reasons 64-bit targets will transfer them
1074 as 64-bit quantities even if using XML descriptions. */
1075 if (rawnum
== mips_regnum (gdbarch
)->fp_control_status
1076 || rawnum
== mips_regnum (gdbarch
)->fp_implementation_revision
)
1077 return builtin_type (gdbarch
)->builtin_int32
;
1079 /* Use pointer types for registers if we can. For n32 we can not,
1080 since we do not have a 64-bit pointer type. */
1081 if (mips_abi_regsize (gdbarch
)
1082 == TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
))
1084 if (rawnum
== MIPS_SP_REGNUM
1085 || rawnum
== mips_regnum (gdbarch
)->badvaddr
)
1086 return builtin_type (gdbarch
)->builtin_data_ptr
;
1087 else if (rawnum
== mips_regnum (gdbarch
)->pc
)
1088 return builtin_type (gdbarch
)->builtin_func_ptr
;
1091 if (mips_abi_regsize (gdbarch
) == 4 && TYPE_LENGTH (rawtype
) == 8
1092 && ((rawnum
>= MIPS_ZERO_REGNUM
&& rawnum
<= MIPS_PS_REGNUM
)
1093 || rawnum
== mips_regnum (gdbarch
)->lo
1094 || rawnum
== mips_regnum (gdbarch
)->hi
1095 || rawnum
== mips_regnum (gdbarch
)->badvaddr
1096 || rawnum
== mips_regnum (gdbarch
)->cause
1097 || rawnum
== mips_regnum (gdbarch
)->pc
1098 || (mips_regnum (gdbarch
)->dspacc
!= -1
1099 && rawnum
>= mips_regnum (gdbarch
)->dspacc
1100 && rawnum
< mips_regnum (gdbarch
)->dspacc
+ 6)))
1101 return builtin_type (gdbarch
)->builtin_int32
;
1103 /* The pseudo/cooked view of embedded registers is always
1104 32-bit, even if the target transfers 64-bit values for them.
1105 New targets relying on XML descriptions should only transfer
1106 the necessary 32 bits, but older versions of GDB expected 64,
1107 so allow the target to provide 64 bits without interfering
1108 with the displayed type. */
1109 if (gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
1110 && rawnum
>= MIPS_FIRST_EMBED_REGNUM
1111 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
1112 return builtin_type (gdbarch
)->builtin_int32
;
1114 /* For all other registers, pass through the hardware type. */
1118 /* Should the upper word of 64-bit addresses be zeroed? */
1119 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
1122 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
1124 switch (mask_address_var
)
1126 case AUTO_BOOLEAN_TRUE
:
1128 case AUTO_BOOLEAN_FALSE
:
1131 case AUTO_BOOLEAN_AUTO
:
1132 return tdep
->default_mask_address_p
;
1134 internal_error (__FILE__
, __LINE__
,
1135 _("mips_mask_address_p: bad switch"));
1141 show_mask_address (struct ui_file
*file
, int from_tty
,
1142 struct cmd_list_element
*c
, const char *value
)
1144 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch ());
1146 deprecated_show_value_hack (file
, from_tty
, c
, value
);
1147 switch (mask_address_var
)
1149 case AUTO_BOOLEAN_TRUE
:
1150 printf_filtered ("The 32 bit mips address mask is enabled\n");
1152 case AUTO_BOOLEAN_FALSE
:
1153 printf_filtered ("The 32 bit mips address mask is disabled\n");
1155 case AUTO_BOOLEAN_AUTO
:
1157 ("The 32 bit address mask is set automatically. Currently %s\n",
1158 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
1161 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
1166 /* Tell if the program counter value in MEMADDR is in a standard ISA
1170 mips_pc_is_mips (CORE_ADDR memaddr
)
1172 struct bound_minimal_symbol sym
;
1174 /* Flags indicating that this is a MIPS16 or microMIPS function is
1175 stored by elfread.c in the high bit of the info field. Use this
1176 to decide if the function is standard MIPS. Otherwise if bit 0
1177 of the address is clear, then this is a standard MIPS function. */
1178 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1180 return msymbol_is_mips (sym
.minsym
);
1182 return is_mips_addr (memaddr
);
1185 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
1188 mips_pc_is_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1190 struct bound_minimal_symbol sym
;
1192 /* A flag indicating that this is a MIPS16 function is stored by
1193 elfread.c in the high bit of the info field. Use this to decide
1194 if the function is MIPS16. Otherwise if bit 0 of the address is
1195 set, then ELF file flags will tell if this is a MIPS16 function. */
1196 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1198 return msymbol_is_mips16 (sym
.minsym
);
1200 return is_mips16_addr (gdbarch
, memaddr
);
1203 /* Tell if the program counter value in MEMADDR is in a microMIPS function. */
1206 mips_pc_is_micromips (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1208 struct bound_minimal_symbol sym
;
1210 /* A flag indicating that this is a microMIPS function is stored by
1211 elfread.c in the high bit of the info field. Use this to decide
1212 if the function is microMIPS. Otherwise if bit 0 of the address
1213 is set, then ELF file flags will tell if this is a microMIPS
1215 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1217 return msymbol_is_micromips (sym
.minsym
);
1219 return is_micromips_addr (gdbarch
, memaddr
);
1222 /* Tell the ISA type of the function the program counter value in MEMADDR
1225 static enum mips_isa
1226 mips_pc_isa (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1228 struct bound_minimal_symbol sym
;
1230 /* A flag indicating that this is a MIPS16 or a microMIPS function
1231 is stored by elfread.c in the high bit of the info field. Use
1232 this to decide if the function is MIPS16 or microMIPS or normal
1233 MIPS. Otherwise if bit 0 of the address is set, then ELF file
1234 flags will tell if this is a MIPS16 or a microMIPS function. */
1235 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1238 if (msymbol_is_micromips (sym
.minsym
))
1239 return ISA_MICROMIPS
;
1240 else if (msymbol_is_mips16 (sym
.minsym
))
1247 if (is_mips_addr (memaddr
))
1249 else if (is_micromips_addr (gdbarch
, memaddr
))
1250 return ISA_MICROMIPS
;
1256 /* Set the ISA bit correctly in the PC, used by DWARF-2 machinery.
1257 The need for comes from the ISA bit having been cleared, making
1258 addresses in FDE, range records, etc. referring to compressed code
1259 different to those in line information, the symbol table and finally
1260 the PC register. That in turn confuses many operations. */
1263 mips_adjust_dwarf2_addr (CORE_ADDR pc
)
1265 pc
= unmake_compact_addr (pc
);
1266 return mips_pc_is_mips (pc
) ? pc
: make_compact_addr (pc
);
1269 /* Recalculate the line record requested so that the resulting PC has
1270 the ISA bit set correctly, used by DWARF-2 machinery. The need for
1271 this adjustment comes from some records associated with compressed
1272 code having the ISA bit cleared, most notably at function prologue
1273 ends. The ISA bit is in this context retrieved from the minimal
1274 symbol covering the address requested, which in turn has been
1275 constructed from the binary's symbol table rather than DWARF-2
1276 information. The correct setting of the ISA bit is required for
1277 breakpoint addresses to correctly match against the stop PC.
1279 As line entries can specify relative address adjustments we need to
1280 keep track of the absolute value of the last line address recorded
1281 in line information, so that we can calculate the actual address to
1282 apply the ISA bit adjustment to. We use PC for this tracking and
1283 keep the original address there.
1285 As such relative address adjustments can be odd within compressed
1286 code we need to keep track of the last line address with the ISA
1287 bit adjustment applied too, as the original address may or may not
1288 have had the ISA bit set. We use ADJ_PC for this tracking and keep
1289 the adjusted address there.
1291 For relative address adjustments we then use these variables to
1292 calculate the address intended by line information, which will be
1293 PC-relative, and return an updated adjustment carrying ISA bit
1294 information, which will be ADJ_PC-relative. For absolute address
1295 adjustments we just return the same address that we store in ADJ_PC
1298 As the first line entry can be relative to an implied address value
1299 of 0 we need to have the initial address set up that we store in PC
1300 and ADJ_PC. This is arranged with a call from `dwarf_decode_lines_1'
1301 that sets PC to 0 and ADJ_PC accordingly, usually 0 as well. */
1304 mips_adjust_dwarf2_line (CORE_ADDR addr
, int rel
)
1306 static CORE_ADDR adj_pc
;
1307 static CORE_ADDR pc
;
1310 pc
= rel
? pc
+ addr
: addr
;
1311 isa_pc
= mips_adjust_dwarf2_addr (pc
);
1312 addr
= rel
? isa_pc
- adj_pc
: isa_pc
;
1317 /* Various MIPS16 thunk (aka stub or trampoline) names. */
1319 static const char mips_str_mips16_call_stub
[] = "__mips16_call_stub_";
1320 static const char mips_str_mips16_ret_stub
[] = "__mips16_ret_";
1321 static const char mips_str_call_fp_stub
[] = "__call_stub_fp_";
1322 static const char mips_str_call_stub
[] = "__call_stub_";
1323 static const char mips_str_fn_stub
[] = "__fn_stub_";
1325 /* This is used as a PIC thunk prefix. */
1327 static const char mips_str_pic
[] = ".pic.";
1329 /* Return non-zero if the PC is inside a call thunk (aka stub or
1330 trampoline) that should be treated as a temporary frame. */
1333 mips_in_frame_stub (CORE_ADDR pc
)
1335 CORE_ADDR start_addr
;
1338 /* Find the starting address of the function containing the PC. */
1339 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
1342 /* If the PC is in __mips16_call_stub_*, this is a call/return stub. */
1343 if (startswith (name
, mips_str_mips16_call_stub
))
1345 /* If the PC is in __call_stub_*, this is a call/return or a call stub. */
1346 if (startswith (name
, mips_str_call_stub
))
1348 /* If the PC is in __fn_stub_*, this is a call stub. */
1349 if (startswith (name
, mips_str_fn_stub
))
1352 return 0; /* Not a stub. */
1355 /* MIPS believes that the PC has a sign extended value. Perhaps the
1356 all registers should be sign extended for simplicity? */
1359 mips_read_pc (struct regcache
*regcache
)
1361 int regnum
= gdbarch_pc_regnum (get_regcache_arch (regcache
));
1364 regcache_cooked_read_signed (regcache
, regnum
, &pc
);
1369 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1373 pc
= frame_unwind_register_signed (next_frame
, gdbarch_pc_regnum (gdbarch
));
1374 /* macro/2012-04-20: This hack skips over MIPS16 call thunks as
1375 intermediate frames. In this case we can get the caller's address
1376 from $ra, or if $ra contains an address within a thunk as well, then
1377 it must be in the return path of __mips16_call_stub_{s,d}{f,c}_{0..10}
1378 and thus the caller's address is in $s2. */
1379 if (frame_relative_level (next_frame
) >= 0 && mips_in_frame_stub (pc
))
1381 pc
= frame_unwind_register_signed
1382 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
1383 if (mips_in_frame_stub (pc
))
1384 pc
= frame_unwind_register_signed
1385 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
1391 mips_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1393 return frame_unwind_register_signed
1394 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
);
1397 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1398 dummy frame. The frame ID's base needs to match the TOS value
1399 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1402 static struct frame_id
1403 mips_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1405 return frame_id_build
1406 (get_frame_register_signed (this_frame
,
1407 gdbarch_num_regs (gdbarch
)
1409 get_frame_pc (this_frame
));
1412 /* Implement the "write_pc" gdbarch method. */
1415 mips_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1417 int regnum
= gdbarch_pc_regnum (get_regcache_arch (regcache
));
1419 regcache_cooked_write_unsigned (regcache
, regnum
, pc
);
1422 /* Fetch and return instruction from the specified location. Handle
1423 MIPS16/microMIPS as appropriate. */
1426 mips_fetch_instruction (struct gdbarch
*gdbarch
,
1427 enum mips_isa isa
, CORE_ADDR addr
, int *errp
)
1429 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1430 gdb_byte buf
[MIPS_INSN32_SIZE
];
1438 instlen
= MIPS_INSN16_SIZE
;
1439 addr
= unmake_compact_addr (addr
);
1442 instlen
= MIPS_INSN32_SIZE
;
1445 internal_error (__FILE__
, __LINE__
, _("invalid ISA"));
1448 err
= target_read_memory (addr
, buf
, instlen
);
1454 memory_error (TARGET_XFER_E_IO
, addr
);
1457 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1460 /* These are the fields of 32 bit mips instructions. */
1461 #define mips32_op(x) (x >> 26)
1462 #define itype_op(x) (x >> 26)
1463 #define itype_rs(x) ((x >> 21) & 0x1f)
1464 #define itype_rt(x) ((x >> 16) & 0x1f)
1465 #define itype_immediate(x) (x & 0xffff)
1467 #define jtype_op(x) (x >> 26)
1468 #define jtype_target(x) (x & 0x03ffffff)
1470 #define rtype_op(x) (x >> 26)
1471 #define rtype_rs(x) ((x >> 21) & 0x1f)
1472 #define rtype_rt(x) ((x >> 16) & 0x1f)
1473 #define rtype_rd(x) ((x >> 11) & 0x1f)
1474 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1475 #define rtype_funct(x) (x & 0x3f)
1477 /* MicroMIPS instruction fields. */
1478 #define micromips_op(x) ((x) >> 10)
1480 /* 16-bit/32-bit-high-part instruction formats, B and S refer to the lowest
1481 bit and the size respectively of the field extracted. */
1482 #define b0s4_imm(x) ((x) & 0xf)
1483 #define b0s5_imm(x) ((x) & 0x1f)
1484 #define b0s5_reg(x) ((x) & 0x1f)
1485 #define b0s7_imm(x) ((x) & 0x7f)
1486 #define b0s10_imm(x) ((x) & 0x3ff)
1487 #define b1s4_imm(x) (((x) >> 1) & 0xf)
1488 #define b1s9_imm(x) (((x) >> 1) & 0x1ff)
1489 #define b2s3_cc(x) (((x) >> 2) & 0x7)
1490 #define b4s2_regl(x) (((x) >> 4) & 0x3)
1491 #define b5s5_op(x) (((x) >> 5) & 0x1f)
1492 #define b5s5_reg(x) (((x) >> 5) & 0x1f)
1493 #define b6s4_op(x) (((x) >> 6) & 0xf)
1494 #define b7s3_reg(x) (((x) >> 7) & 0x7)
1496 /* 32-bit instruction formats, B and S refer to the lowest bit and the size
1497 respectively of the field extracted. */
1498 #define b0s6_op(x) ((x) & 0x3f)
1499 #define b0s11_op(x) ((x) & 0x7ff)
1500 #define b0s12_imm(x) ((x) & 0xfff)
1501 #define b0s16_imm(x) ((x) & 0xffff)
1502 #define b0s26_imm(x) ((x) & 0x3ffffff)
1503 #define b6s10_ext(x) (((x) >> 6) & 0x3ff)
1504 #define b11s5_reg(x) (((x) >> 11) & 0x1f)
1505 #define b12s4_op(x) (((x) >> 12) & 0xf)
1507 /* Return the size in bytes of the instruction INSN encoded in the ISA
1511 mips_insn_size (enum mips_isa isa
, ULONGEST insn
)
1516 if ((micromips_op (insn
) & 0x4) == 0x4
1517 || (micromips_op (insn
) & 0x7) == 0x0)
1518 return 2 * MIPS_INSN16_SIZE
;
1520 return MIPS_INSN16_SIZE
;
1522 if ((insn
& 0xf800) == 0xf000)
1523 return 2 * MIPS_INSN16_SIZE
;
1525 return MIPS_INSN16_SIZE
;
1527 return MIPS_INSN32_SIZE
;
1529 internal_error (__FILE__
, __LINE__
, _("invalid ISA"));
1533 mips32_relative_offset (ULONGEST inst
)
1535 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
1538 /* Determine the address of the next instruction executed after the INST
1539 floating condition branch instruction at PC. COUNT specifies the
1540 number of the floating condition bits tested by the branch. */
1543 mips32_bc1_pc (struct gdbarch
*gdbarch
, struct frame_info
*frame
,
1544 ULONGEST inst
, CORE_ADDR pc
, int count
)
1546 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1547 int cnum
= (itype_rt (inst
) >> 2) & (count
- 1);
1548 int tf
= itype_rt (inst
) & 1;
1549 int mask
= (1 << count
) - 1;
1554 /* No way to handle; it'll most likely trap anyway. */
1557 fcs
= get_frame_register_unsigned (frame
, fcsr
);
1558 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1560 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1561 pc
+= mips32_relative_offset (inst
);
1568 /* Return nonzero if the gdbarch is an Octeon series. */
1571 is_octeon (struct gdbarch
*gdbarch
)
1573 const struct bfd_arch_info
*info
= gdbarch_bfd_arch_info (gdbarch
);
1575 return (info
->mach
== bfd_mach_mips_octeon
1576 || info
->mach
== bfd_mach_mips_octeonp
1577 || info
->mach
== bfd_mach_mips_octeon2
);
1580 /* Return true if the OP represents the Octeon's BBIT instruction. */
1583 is_octeon_bbit_op (int op
, struct gdbarch
*gdbarch
)
1585 if (!is_octeon (gdbarch
))
1587 /* BBIT0 is encoded as LWC2: 110 010. */
1588 /* BBIT032 is encoded as LDC2: 110 110. */
1589 /* BBIT1 is encoded as SWC2: 111 010. */
1590 /* BBIT132 is encoded as SDC2: 111 110. */
1591 if (op
== 50 || op
== 54 || op
== 58 || op
== 62)
1597 /* Determine where to set a single step breakpoint while considering
1598 branch prediction. */
1601 mips32_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1603 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1606 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
1607 op
= itype_op (inst
);
1608 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch
1612 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1623 goto greater_branch
;
1628 else if (op
== 17 && itype_rs (inst
) == 8)
1629 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1630 pc
= mips32_bc1_pc (gdbarch
, frame
, inst
, pc
+ 4, 1);
1631 else if (op
== 17 && itype_rs (inst
) == 9
1632 && (itype_rt (inst
) & 2) == 0)
1633 /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */
1634 pc
= mips32_bc1_pc (gdbarch
, frame
, inst
, pc
+ 4, 2);
1635 else if (op
== 17 && itype_rs (inst
) == 10
1636 && (itype_rt (inst
) & 2) == 0)
1637 /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */
1638 pc
= mips32_bc1_pc (gdbarch
, frame
, inst
, pc
+ 4, 4);
1641 /* The new PC will be alternate mode. */
1645 reg
= jtype_target (inst
) << 2;
1646 /* Add 1 to indicate 16-bit mode -- invert ISA mode. */
1647 pc
= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + reg
+ 1;
1649 else if (is_octeon_bbit_op (op
, gdbarch
))
1653 branch_if
= op
== 58 || op
== 62;
1654 bit
= itype_rt (inst
);
1656 /* Take into account the *32 instructions. */
1657 if (op
== 54 || op
== 62)
1660 if (((get_frame_register_signed (frame
,
1661 itype_rs (inst
)) >> bit
) & 1)
1663 pc
+= mips32_relative_offset (inst
) + 4;
1665 pc
+= 8; /* After the delay slot. */
1669 pc
+= 4; /* Not a branch, next instruction is easy. */
1672 { /* This gets way messy. */
1674 /* Further subdivide into SPECIAL, REGIMM and other. */
1675 switch (op
& 0x07) /* Extract bits 28,27,26. */
1677 case 0: /* SPECIAL */
1678 op
= rtype_funct (inst
);
1683 /* Set PC to that address. */
1684 pc
= get_frame_register_signed (frame
, rtype_rs (inst
));
1686 case 12: /* SYSCALL */
1688 struct gdbarch_tdep
*tdep
;
1690 tdep
= gdbarch_tdep (get_frame_arch (frame
));
1691 if (tdep
->syscall_next_pc
!= NULL
)
1692 pc
= tdep
->syscall_next_pc (frame
);
1701 break; /* end SPECIAL */
1702 case 1: /* REGIMM */
1704 op
= itype_rt (inst
); /* branch condition */
1709 case 16: /* BLTZAL */
1710 case 18: /* BLTZALL */
1712 if (get_frame_register_signed (frame
, itype_rs (inst
)) < 0)
1713 pc
+= mips32_relative_offset (inst
) + 4;
1715 pc
+= 8; /* after the delay slot */
1719 case 17: /* BGEZAL */
1720 case 19: /* BGEZALL */
1721 if (get_frame_register_signed (frame
, itype_rs (inst
)) >= 0)
1722 pc
+= mips32_relative_offset (inst
) + 4;
1724 pc
+= 8; /* after the delay slot */
1726 case 0x1c: /* BPOSGE32 */
1727 case 0x1e: /* BPOSGE64 */
1729 if (itype_rs (inst
) == 0)
1731 unsigned int pos
= (op
& 2) ? 64 : 32;
1732 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
1735 /* No way to handle; it'll most likely trap anyway. */
1738 if ((get_frame_register_unsigned (frame
,
1739 dspctl
) & 0x7f) >= pos
)
1740 pc
+= mips32_relative_offset (inst
);
1745 /* All of the other instructions in the REGIMM category */
1750 break; /* end REGIMM */
1755 reg
= jtype_target (inst
) << 2;
1756 /* Upper four bits get never changed... */
1757 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1760 case 4: /* BEQ, BEQL */
1762 if (get_frame_register_signed (frame
, itype_rs (inst
)) ==
1763 get_frame_register_signed (frame
, itype_rt (inst
)))
1764 pc
+= mips32_relative_offset (inst
) + 4;
1768 case 5: /* BNE, BNEL */
1770 if (get_frame_register_signed (frame
, itype_rs (inst
)) !=
1771 get_frame_register_signed (frame
, itype_rt (inst
)))
1772 pc
+= mips32_relative_offset (inst
) + 4;
1776 case 6: /* BLEZ, BLEZL */
1777 if (get_frame_register_signed (frame
, itype_rs (inst
)) <= 0)
1778 pc
+= mips32_relative_offset (inst
) + 4;
1784 greater_branch
: /* BGTZ, BGTZL */
1785 if (get_frame_register_signed (frame
, itype_rs (inst
)) > 0)
1786 pc
+= mips32_relative_offset (inst
) + 4;
1793 } /* mips32_next_pc */
1795 /* Extract the 7-bit signed immediate offset from the microMIPS instruction
1799 micromips_relative_offset7 (ULONGEST insn
)
1801 return ((b0s7_imm (insn
) ^ 0x40) - 0x40) << 1;
1804 /* Extract the 10-bit signed immediate offset from the microMIPS instruction
1808 micromips_relative_offset10 (ULONGEST insn
)
1810 return ((b0s10_imm (insn
) ^ 0x200) - 0x200) << 1;
1813 /* Extract the 16-bit signed immediate offset from the microMIPS instruction
1817 micromips_relative_offset16 (ULONGEST insn
)
1819 return ((b0s16_imm (insn
) ^ 0x8000) - 0x8000) << 1;
1822 /* Return the size in bytes of the microMIPS instruction at the address PC. */
1825 micromips_pc_insn_size (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1829 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1830 return mips_insn_size (ISA_MICROMIPS
, insn
);
1833 /* Calculate the address of the next microMIPS instruction to execute
1834 after the INSN coprocessor 1 conditional branch instruction at the
1835 address PC. COUNT denotes the number of coprocessor condition bits
1836 examined by the branch. */
1839 micromips_bc1_pc (struct gdbarch
*gdbarch
, struct frame_info
*frame
,
1840 ULONGEST insn
, CORE_ADDR pc
, int count
)
1842 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1843 int cnum
= b2s3_cc (insn
>> 16) & (count
- 1);
1844 int tf
= b5s5_op (insn
>> 16) & 1;
1845 int mask
= (1 << count
) - 1;
1850 /* No way to handle; it'll most likely trap anyway. */
1853 fcs
= get_frame_register_unsigned (frame
, fcsr
);
1854 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1856 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1857 pc
+= micromips_relative_offset16 (insn
);
1859 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1864 /* Calculate the address of the next microMIPS instruction to execute
1865 after the instruction at the address PC. */
1868 micromips_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1870 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1873 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1874 pc
+= MIPS_INSN16_SIZE
;
1875 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
1877 /* 32-bit instructions. */
1878 case 2 * MIPS_INSN16_SIZE
:
1880 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1881 pc
+= MIPS_INSN16_SIZE
;
1882 switch (micromips_op (insn
>> 16))
1884 case 0x00: /* POOL32A: bits 000000 */
1885 if (b0s6_op (insn
) == 0x3c
1886 /* POOL32Axf: bits 000000 ... 111100 */
1887 && (b6s10_ext (insn
) & 0x2bf) == 0x3c)
1888 /* JALR, JALR.HB: 000000 000x111100 111100 */
1889 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
1890 pc
= get_frame_register_signed (frame
, b0s5_reg (insn
>> 16));
1893 case 0x10: /* POOL32I: bits 010000 */
1894 switch (b5s5_op (insn
>> 16))
1896 case 0x00: /* BLTZ: bits 010000 00000 */
1897 case 0x01: /* BLTZAL: bits 010000 00001 */
1898 case 0x11: /* BLTZALS: bits 010000 10001 */
1899 if (get_frame_register_signed (frame
,
1900 b0s5_reg (insn
>> 16)) < 0)
1901 pc
+= micromips_relative_offset16 (insn
);
1903 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1906 case 0x02: /* BGEZ: bits 010000 00010 */
1907 case 0x03: /* BGEZAL: bits 010000 00011 */
1908 case 0x13: /* BGEZALS: bits 010000 10011 */
1909 if (get_frame_register_signed (frame
,
1910 b0s5_reg (insn
>> 16)) >= 0)
1911 pc
+= micromips_relative_offset16 (insn
);
1913 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1916 case 0x04: /* BLEZ: bits 010000 00100 */
1917 if (get_frame_register_signed (frame
,
1918 b0s5_reg (insn
>> 16)) <= 0)
1919 pc
+= micromips_relative_offset16 (insn
);
1921 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1924 case 0x05: /* BNEZC: bits 010000 00101 */
1925 if (get_frame_register_signed (frame
,
1926 b0s5_reg (insn
>> 16)) != 0)
1927 pc
+= micromips_relative_offset16 (insn
);
1930 case 0x06: /* BGTZ: bits 010000 00110 */
1931 if (get_frame_register_signed (frame
,
1932 b0s5_reg (insn
>> 16)) > 0)
1933 pc
+= micromips_relative_offset16 (insn
);
1935 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1938 case 0x07: /* BEQZC: bits 010000 00111 */
1939 if (get_frame_register_signed (frame
,
1940 b0s5_reg (insn
>> 16)) == 0)
1941 pc
+= micromips_relative_offset16 (insn
);
1944 case 0x14: /* BC2F: bits 010000 10100 xxx00 */
1945 case 0x15: /* BC2T: bits 010000 10101 xxx00 */
1946 if (((insn
>> 16) & 0x3) == 0x0)
1947 /* BC2F, BC2T: don't know how to handle these. */
1951 case 0x1a: /* BPOSGE64: bits 010000 11010 */
1952 case 0x1b: /* BPOSGE32: bits 010000 11011 */
1954 unsigned int pos
= (b5s5_op (insn
>> 16) & 1) ? 32 : 64;
1955 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
1958 /* No way to handle; it'll most likely trap anyway. */
1961 if ((get_frame_register_unsigned (frame
,
1962 dspctl
) & 0x7f) >= pos
)
1963 pc
+= micromips_relative_offset16 (insn
);
1965 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1969 case 0x1c: /* BC1F: bits 010000 11100 xxx00 */
1970 /* BC1ANY2F: bits 010000 11100 xxx01 */
1971 case 0x1d: /* BC1T: bits 010000 11101 xxx00 */
1972 /* BC1ANY2T: bits 010000 11101 xxx01 */
1973 if (((insn
>> 16) & 0x2) == 0x0)
1974 pc
= micromips_bc1_pc (gdbarch
, frame
, insn
, pc
,
1975 ((insn
>> 16) & 0x1) + 1);
1978 case 0x1e: /* BC1ANY4F: bits 010000 11110 xxx01 */
1979 case 0x1f: /* BC1ANY4T: bits 010000 11111 xxx01 */
1980 if (((insn
>> 16) & 0x3) == 0x1)
1981 pc
= micromips_bc1_pc (gdbarch
, frame
, insn
, pc
, 4);
1986 case 0x1d: /* JALS: bits 011101 */
1987 case 0x35: /* J: bits 110101 */
1988 case 0x3d: /* JAL: bits 111101 */
1989 pc
= ((pc
| 0x7fffffe) ^ 0x7fffffe) | (b0s26_imm (insn
) << 1);
1992 case 0x25: /* BEQ: bits 100101 */
1993 if (get_frame_register_signed (frame
, b0s5_reg (insn
>> 16))
1994 == get_frame_register_signed (frame
, b5s5_reg (insn
>> 16)))
1995 pc
+= micromips_relative_offset16 (insn
);
1997 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2000 case 0x2d: /* BNE: bits 101101 */
2001 if (get_frame_register_signed (frame
, b0s5_reg (insn
>> 16))
2002 != get_frame_register_signed (frame
, b5s5_reg (insn
>> 16)))
2003 pc
+= micromips_relative_offset16 (insn
);
2005 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2008 case 0x3c: /* JALX: bits 111100 */
2009 pc
= ((pc
| 0xfffffff) ^ 0xfffffff) | (b0s26_imm (insn
) << 2);
2014 /* 16-bit instructions. */
2015 case MIPS_INSN16_SIZE
:
2016 switch (micromips_op (insn
))
2018 case 0x11: /* POOL16C: bits 010001 */
2019 if ((b5s5_op (insn
) & 0x1c) == 0xc)
2020 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
2021 pc
= get_frame_register_signed (frame
, b0s5_reg (insn
));
2022 else if (b5s5_op (insn
) == 0x18)
2023 /* JRADDIUSP: bits 010001 11000 */
2024 pc
= get_frame_register_signed (frame
, MIPS_RA_REGNUM
);
2027 case 0x23: /* BEQZ16: bits 100011 */
2029 int rs
= mips_reg3_to_reg
[b7s3_reg (insn
)];
2031 if (get_frame_register_signed (frame
, rs
) == 0)
2032 pc
+= micromips_relative_offset7 (insn
);
2034 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2038 case 0x2b: /* BNEZ16: bits 101011 */
2040 int rs
= mips_reg3_to_reg
[b7s3_reg (insn
)];
2042 if (get_frame_register_signed (frame
, rs
) != 0)
2043 pc
+= micromips_relative_offset7 (insn
);
2045 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2049 case 0x33: /* B16: bits 110011 */
2050 pc
+= micromips_relative_offset10 (insn
);
2059 /* Decoding the next place to set a breakpoint is irregular for the
2060 mips 16 variant, but fortunately, there fewer instructions. We have
2061 to cope ith extensions for 16 bit instructions and a pair of actual
2062 32 bit instructions. We dont want to set a single step instruction
2063 on the extend instruction either. */
2065 /* Lots of mips16 instruction formats */
2066 /* Predicting jumps requires itype,ritype,i8type
2067 and their extensions extItype,extritype,extI8type. */
2068 enum mips16_inst_fmts
2070 itype
, /* 0 immediate 5,10 */
2071 ritype
, /* 1 5,3,8 */
2072 rrtype
, /* 2 5,3,3,5 */
2073 rritype
, /* 3 5,3,3,5 */
2074 rrrtype
, /* 4 5,3,3,3,2 */
2075 rriatype
, /* 5 5,3,3,1,4 */
2076 shifttype
, /* 6 5,3,3,3,2 */
2077 i8type
, /* 7 5,3,8 */
2078 i8movtype
, /* 8 5,3,3,5 */
2079 i8mov32rtype
, /* 9 5,3,5,3 */
2080 i64type
, /* 10 5,3,8 */
2081 ri64type
, /* 11 5,3,3,5 */
2082 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
2083 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
2084 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
2085 extRRItype
, /* 15 5,5,5,5,3,3,5 */
2086 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
2087 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
2088 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
2089 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
2090 extRi64type
, /* 20 5,6,5,5,3,3,5 */
2091 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
2093 /* I am heaping all the fields of the formats into one structure and
2094 then, only the fields which are involved in instruction extension. */
2098 unsigned int regx
; /* Function in i8 type. */
2103 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
2104 for the bits which make up the immediate extension. */
2107 extended_offset (unsigned int extension
)
2111 value
= (extension
>> 16) & 0x1f; /* Extract 15:11. */
2113 value
|= (extension
>> 21) & 0x3f; /* Extract 10:5. */
2115 value
|= extension
& 0x1f; /* Extract 4:0. */
2120 /* Only call this function if you know that this is an extendable
2121 instruction. It won't malfunction, but why make excess remote memory
2122 references? If the immediate operands get sign extended or something,
2123 do it after the extension is performed. */
2124 /* FIXME: Every one of these cases needs to worry about sign extension
2125 when the offset is to be used in relative addressing. */
2128 fetch_mips_16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2130 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2133 pc
= unmake_compact_addr (pc
); /* Clear the low order bit. */
2134 target_read_memory (pc
, buf
, 2);
2135 return extract_unsigned_integer (buf
, 2, byte_order
);
2139 unpack_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
2140 unsigned int extension
,
2142 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
2147 switch (insn_format
)
2154 value
= extended_offset ((extension
<< 16) | inst
);
2155 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
2159 value
= inst
& 0x7ff;
2160 value
= (value
^ 0x400) - 0x400; /* Sign-extend. */
2169 { /* A register identifier and an offset. */
2170 /* Most of the fields are the same as I type but the
2171 immediate value is of a different length. */
2175 value
= extended_offset ((extension
<< 16) | inst
);
2176 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
2180 value
= inst
& 0xff; /* 8 bits */
2181 value
= (value
^ 0x80) - 0x80; /* Sign-extend. */
2184 regx
= (inst
>> 8) & 0x07; /* i8 funct */
2190 unsigned long value
;
2191 unsigned int nexthalf
;
2192 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
2193 value
= value
<< 16;
2194 nexthalf
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, pc
+ 2, NULL
);
2195 /* Low bit still set. */
2203 internal_error (__FILE__
, __LINE__
, _("bad switch"));
2205 upk
->offset
= offset
;
2211 /* Calculate the destination of a branch whose 16-bit opcode word is at PC,
2212 and having a signed 16-bit OFFSET. */
2215 add_offset_16 (CORE_ADDR pc
, int offset
)
2217 return pc
+ (offset
<< 1) + 2;
2221 extended_mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
,
2222 unsigned int extension
, unsigned int insn
)
2224 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2225 int op
= (insn
>> 11);
2228 case 2: /* Branch */
2230 struct upk_mips16 upk
;
2231 unpack_mips16 (gdbarch
, pc
, extension
, insn
, itype
, &upk
);
2232 pc
= add_offset_16 (pc
, upk
.offset
);
2235 case 3: /* JAL , JALX - Watch out, these are 32 bit
2238 struct upk_mips16 upk
;
2239 unpack_mips16 (gdbarch
, pc
, extension
, insn
, jalxtype
, &upk
);
2240 pc
= ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)) | (upk
.offset
<< 2);
2241 if ((insn
>> 10) & 0x01) /* Exchange mode */
2242 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode. */
2249 struct upk_mips16 upk
;
2251 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
2252 reg
= get_frame_register_signed (frame
, mips_reg3_to_reg
[upk
.regx
]);
2254 pc
= add_offset_16 (pc
, upk
.offset
);
2261 struct upk_mips16 upk
;
2263 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
2264 reg
= get_frame_register_signed (frame
, mips_reg3_to_reg
[upk
.regx
]);
2266 pc
= add_offset_16 (pc
, upk
.offset
);
2271 case 12: /* I8 Formats btez btnez */
2273 struct upk_mips16 upk
;
2275 unpack_mips16 (gdbarch
, pc
, extension
, insn
, i8type
, &upk
);
2276 /* upk.regx contains the opcode */
2277 reg
= get_frame_register_signed (frame
, 24); /* Test register is 24 */
2278 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
2279 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
2280 pc
= add_offset_16 (pc
, upk
.offset
);
2285 case 29: /* RR Formats JR, JALR, JALR-RA */
2287 struct upk_mips16 upk
;
2288 /* upk.fmt = rrtype; */
2293 upk
.regx
= (insn
>> 8) & 0x07;
2294 upk
.regy
= (insn
>> 5) & 0x07;
2295 if ((upk
.regy
& 1) == 0)
2296 reg
= mips_reg3_to_reg
[upk
.regx
];
2298 reg
= 31; /* Function return instruction. */
2299 pc
= get_frame_register_signed (frame
, reg
);
2306 /* This is an instruction extension. Fetch the real instruction
2307 (which follows the extension) and decode things based on
2311 pc
= extended_mips16_next_pc (frame
, pc
, insn
,
2312 fetch_mips_16 (gdbarch
, pc
));
2325 mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
2327 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2328 unsigned int insn
= fetch_mips_16 (gdbarch
, pc
);
2329 return extended_mips16_next_pc (frame
, pc
, 0, insn
);
2332 /* The mips_next_pc function supports single_step when the remote
2333 target monitor or stub is not developed enough to do a single_step.
2334 It works by decoding the current instruction and predicting where a
2335 branch will go. This isn't hard because all the data is available.
2336 The MIPS32, MIPS16 and microMIPS variants are quite different. */
2338 mips_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
2340 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2342 if (mips_pc_is_mips16 (gdbarch
, pc
))
2343 return mips16_next_pc (frame
, pc
);
2344 else if (mips_pc_is_micromips (gdbarch
, pc
))
2345 return micromips_next_pc (frame
, pc
);
2347 return mips32_next_pc (frame
, pc
);
2350 /* Return non-zero if the MIPS16 instruction INSN is a compact branch
2354 mips16_instruction_is_compact_branch (unsigned short insn
)
2356 switch (insn
& 0xf800)
2359 return (insn
& 0x009f) == 0x80; /* JALRC/JRC */
2361 return (insn
& 0x0600) == 0; /* BTNEZ/BTEQZ */
2362 case 0x2800: /* BNEZ */
2363 case 0x2000: /* BEQZ */
2364 case 0x1000: /* B */
2371 /* Return non-zero if the microMIPS instruction INSN is a compact branch
2375 micromips_instruction_is_compact_branch (unsigned short insn
)
2377 switch (micromips_op (insn
))
2379 case 0x11: /* POOL16C: bits 010001 */
2380 return (b5s5_op (insn
) == 0x18
2381 /* JRADDIUSP: bits 010001 11000 */
2382 || b5s5_op (insn
) == 0xd);
2383 /* JRC: bits 010011 01101 */
2384 case 0x10: /* POOL32I: bits 010000 */
2385 return (b5s5_op (insn
) & 0x1d) == 0x5;
2386 /* BEQZC/BNEZC: bits 010000 001x1 */
2392 struct mips_frame_cache
2395 struct trad_frame_saved_reg
*saved_regs
;
2398 /* Set a register's saved stack address in temp_saved_regs. If an
2399 address has already been set for this register, do nothing; this
2400 way we will only recognize the first save of a given register in a
2403 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
2404 [gdbarch_num_regs .. 2*gdbarch_num_regs).
2405 Strictly speaking, only the second range is used as it is only second
2406 range (the ABI instead of ISA registers) that comes into play when finding
2407 saved registers in a frame. */
2410 set_reg_offset (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
,
2411 int regnum
, CORE_ADDR offset
)
2413 if (this_cache
!= NULL
2414 && this_cache
->saved_regs
[regnum
].addr
== -1)
2416 this_cache
->saved_regs
[regnum
+ 0 * gdbarch_num_regs (gdbarch
)].addr
2418 this_cache
->saved_regs
[regnum
+ 1 * gdbarch_num_regs (gdbarch
)].addr
2424 /* Fetch the immediate value from a MIPS16 instruction.
2425 If the previous instruction was an EXTEND, use it to extend
2426 the upper bits of the immediate value. This is a helper function
2427 for mips16_scan_prologue. */
2430 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
2431 unsigned short inst
, /* current instruction */
2432 int nbits
, /* number of bits in imm field */
2433 int scale
, /* scale factor to be applied to imm */
2434 int is_signed
) /* is the imm field signed? */
2438 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
2440 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
2441 if (offset
& 0x8000) /* check for negative extend */
2442 offset
= 0 - (0x10000 - (offset
& 0xffff));
2443 return offset
| (inst
& 0x1f);
2447 int max_imm
= 1 << nbits
;
2448 int mask
= max_imm
- 1;
2449 int sign_bit
= max_imm
>> 1;
2451 offset
= inst
& mask
;
2452 if (is_signed
&& (offset
& sign_bit
))
2453 offset
= 0 - (max_imm
- offset
);
2454 return offset
* scale
;
2459 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
2460 the associated FRAME_CACHE if not null.
2461 Return the address of the first instruction past the prologue. */
2464 mips16_scan_prologue (struct gdbarch
*gdbarch
,
2465 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2466 struct frame_info
*this_frame
,
2467 struct mips_frame_cache
*this_cache
)
2469 int prev_non_prologue_insn
= 0;
2470 int this_non_prologue_insn
;
2471 int non_prologue_insns
= 0;
2474 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer. */
2476 long frame_offset
= 0; /* Size of stack frame. */
2477 long frame_adjust
= 0; /* Offset of FP from SP. */
2478 int frame_reg
= MIPS_SP_REGNUM
;
2479 unsigned short prev_inst
= 0; /* saved copy of previous instruction. */
2480 unsigned inst
= 0; /* current instruction */
2481 unsigned entry_inst
= 0; /* the entry instruction */
2482 unsigned save_inst
= 0; /* the save instruction */
2483 int prev_delay_slot
= 0;
2487 int extend_bytes
= 0;
2488 int prev_extend_bytes
= 0;
2489 CORE_ADDR end_prologue_addr
;
2491 /* Can be called when there's no process, and hence when there's no
2493 if (this_frame
!= NULL
)
2494 sp
= get_frame_register_signed (this_frame
,
2495 gdbarch_num_regs (gdbarch
)
2500 if (limit_pc
> start_pc
+ 200)
2501 limit_pc
= start_pc
+ 200;
2504 /* Permit at most one non-prologue non-control-transfer instruction
2505 in the middle which may have been reordered by the compiler for
2507 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
2509 this_non_prologue_insn
= 0;
2512 /* Save the previous instruction. If it's an EXTEND, we'll extract
2513 the immediate offset extension from it in mips16_get_imm. */
2516 /* Fetch and decode the instruction. */
2517 inst
= (unsigned short) mips_fetch_instruction (gdbarch
, ISA_MIPS16
,
2520 /* Normally we ignore extend instructions. However, if it is
2521 not followed by a valid prologue instruction, then this
2522 instruction is not part of the prologue either. We must
2523 remember in this case to adjust the end_prologue_addr back
2525 if ((inst
& 0xf800) == 0xf000) /* extend */
2527 extend_bytes
= MIPS_INSN16_SIZE
;
2531 prev_extend_bytes
= extend_bytes
;
2534 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2535 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2537 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
2538 if (offset
< 0) /* Negative stack adjustment? */
2539 frame_offset
-= offset
;
2541 /* Exit loop if a positive stack adjustment is found, which
2542 usually means that the stack cleanup code in the function
2543 epilogue is reached. */
2546 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
2548 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2549 reg
= mips_reg3_to_reg
[(inst
& 0x700) >> 8];
2550 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2552 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
2554 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2555 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2556 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2558 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
2560 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2561 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2563 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2565 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
2566 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2568 else if (inst
== 0x673d) /* move $s1, $sp */
2573 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
2575 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2576 frame_addr
= sp
+ offset
;
2578 frame_adjust
= offset
;
2580 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2582 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
2583 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2584 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
2586 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2588 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2589 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2590 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
2592 else if ((inst
& 0xf81f) == 0xe809
2593 && (inst
& 0x700) != 0x700) /* entry */
2594 entry_inst
= inst
; /* Save for later processing. */
2595 else if ((inst
& 0xff80) == 0x6480) /* save */
2597 save_inst
= inst
; /* Save for later processing. */
2598 if (prev_extend_bytes
) /* extend */
2599 save_inst
|= prev_inst
<< 16;
2601 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
2603 /* This instruction is part of the prologue, but we don't
2604 need to do anything special to handle it. */
2606 else if (mips16_instruction_has_delay_slot (inst
, 0))
2607 /* JAL/JALR/JALX/JR */
2609 /* The instruction in the delay slot can be a part
2610 of the prologue, so move forward once more. */
2612 if (mips16_instruction_has_delay_slot (inst
, 1))
2615 prev_extend_bytes
= MIPS_INSN16_SIZE
;
2616 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
2621 this_non_prologue_insn
= 1;
2624 non_prologue_insns
+= this_non_prologue_insn
;
2626 /* A jump or branch, or enough non-prologue insns seen? If so,
2627 then we must have reached the end of the prologue by now. */
2628 if (prev_delay_slot
|| non_prologue_insns
> 1
2629 || mips16_instruction_is_compact_branch (inst
))
2632 prev_non_prologue_insn
= this_non_prologue_insn
;
2633 prev_delay_slot
= in_delay_slot
;
2634 prev_pc
= cur_pc
- prev_extend_bytes
;
2637 /* The entry instruction is typically the first instruction in a function,
2638 and it stores registers at offsets relative to the value of the old SP
2639 (before the prologue). But the value of the sp parameter to this
2640 function is the new SP (after the prologue has been executed). So we
2641 can't calculate those offsets until we've seen the entire prologue,
2642 and can calculate what the old SP must have been. */
2643 if (entry_inst
!= 0)
2645 int areg_count
= (entry_inst
>> 8) & 7;
2646 int sreg_count
= (entry_inst
>> 6) & 3;
2648 /* The entry instruction always subtracts 32 from the SP. */
2651 /* Now we can calculate what the SP must have been at the
2652 start of the function prologue. */
2655 /* Check if a0-a3 were saved in the caller's argument save area. */
2656 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
2658 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2659 offset
+= mips_abi_regsize (gdbarch
);
2662 /* Check if the ra register was pushed on the stack. */
2664 if (entry_inst
& 0x20)
2666 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2667 offset
-= mips_abi_regsize (gdbarch
);
2670 /* Check if the s0 and s1 registers were pushed on the stack. */
2671 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2673 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2674 offset
-= mips_abi_regsize (gdbarch
);
2678 /* The SAVE instruction is similar to ENTRY, except that defined by the
2679 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
2680 size of the frame is specified as an immediate field of instruction
2681 and an extended variation exists which lets additional registers and
2682 frame space to be specified. The instruction always treats registers
2683 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
2684 if (save_inst
!= 0 && mips_abi_regsize (gdbarch
) == 4)
2686 static int args_table
[16] = {
2687 0, 0, 0, 0, 1, 1, 1, 1,
2688 2, 2, 2, 0, 3, 3, 4, -1,
2690 static int astatic_table
[16] = {
2691 0, 1, 2, 3, 0, 1, 2, 3,
2692 0, 1, 2, 4, 0, 1, 0, -1,
2694 int aregs
= (save_inst
>> 16) & 0xf;
2695 int xsregs
= (save_inst
>> 24) & 0x7;
2696 int args
= args_table
[aregs
];
2697 int astatic
= astatic_table
[aregs
];
2702 warning (_("Invalid number of argument registers encoded in SAVE."));
2707 warning (_("Invalid number of static registers encoded in SAVE."));
2711 /* For standard SAVE the frame size of 0 means 128. */
2712 frame_size
= ((save_inst
>> 16) & 0xf0) | (save_inst
& 0xf);
2713 if (frame_size
== 0 && (save_inst
>> 16) == 0)
2716 frame_offset
+= frame_size
;
2718 /* Now we can calculate what the SP must have been at the
2719 start of the function prologue. */
2722 /* Check if A0-A3 were saved in the caller's argument save area. */
2723 for (reg
= MIPS_A0_REGNUM
, offset
= 0; reg
< args
+ 4; reg
++)
2725 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2726 offset
+= mips_abi_regsize (gdbarch
);
2731 /* Check if the RA register was pushed on the stack. */
2732 if (save_inst
& 0x40)
2734 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2735 offset
-= mips_abi_regsize (gdbarch
);
2738 /* Check if the S8 register was pushed on the stack. */
2741 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ offset
);
2742 offset
-= mips_abi_regsize (gdbarch
);
2745 /* Check if S2-S7 were pushed on the stack. */
2746 for (reg
= 18 + xsregs
- 1; reg
> 18 - 1; reg
--)
2748 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2749 offset
-= mips_abi_regsize (gdbarch
);
2752 /* Check if the S1 register was pushed on the stack. */
2753 if (save_inst
& 0x10)
2755 set_reg_offset (gdbarch
, this_cache
, 17, sp
+ offset
);
2756 offset
-= mips_abi_regsize (gdbarch
);
2758 /* Check if the S0 register was pushed on the stack. */
2759 if (save_inst
& 0x20)
2761 set_reg_offset (gdbarch
, this_cache
, 16, sp
+ offset
);
2762 offset
-= mips_abi_regsize (gdbarch
);
2765 /* Check if A0-A3 were pushed on the stack. */
2766 for (reg
= MIPS_A0_REGNUM
+ 3; reg
> MIPS_A0_REGNUM
+ 3 - astatic
; reg
--)
2768 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2769 offset
-= mips_abi_regsize (gdbarch
);
2773 if (this_cache
!= NULL
)
2776 (get_frame_register_signed (this_frame
,
2777 gdbarch_num_regs (gdbarch
) + frame_reg
)
2778 + frame_offset
- frame_adjust
);
2779 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
2780 be able to get rid of the assignment below, evetually. But it's
2781 still needed for now. */
2782 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2783 + mips_regnum (gdbarch
)->pc
]
2784 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
2787 /* Set end_prologue_addr to the address of the instruction immediately
2788 after the last one we scanned. Unless the last one looked like a
2789 non-prologue instruction (and we looked ahead), in which case use
2790 its address instead. */
2791 end_prologue_addr
= (prev_non_prologue_insn
|| prev_delay_slot
2792 ? prev_pc
: cur_pc
- prev_extend_bytes
);
2794 return end_prologue_addr
;
2797 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
2798 Procedures that use the 32-bit instruction set are handled by the
2799 mips_insn32 unwinder. */
2801 static struct mips_frame_cache
*
2802 mips_insn16_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2804 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2805 struct mips_frame_cache
*cache
;
2807 if ((*this_cache
) != NULL
)
2808 return (struct mips_frame_cache
*) (*this_cache
);
2809 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2810 (*this_cache
) = cache
;
2811 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2813 /* Analyze the function prologue. */
2815 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2816 CORE_ADDR start_addr
;
2818 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2819 if (start_addr
== 0)
2820 start_addr
= heuristic_proc_start (gdbarch
, pc
);
2821 /* We can't analyze the prologue if we couldn't find the begining
2823 if (start_addr
== 0)
2826 mips16_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
2827 (struct mips_frame_cache
*) *this_cache
);
2830 /* gdbarch_sp_regnum contains the value and not the address. */
2831 trad_frame_set_value (cache
->saved_regs
,
2832 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
2835 return (struct mips_frame_cache
*) (*this_cache
);
2839 mips_insn16_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2840 struct frame_id
*this_id
)
2842 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2844 /* This marks the outermost frame. */
2845 if (info
->base
== 0)
2847 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2850 static struct value
*
2851 mips_insn16_frame_prev_register (struct frame_info
*this_frame
,
2852 void **this_cache
, int regnum
)
2854 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2856 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2860 mips_insn16_frame_sniffer (const struct frame_unwind
*self
,
2861 struct frame_info
*this_frame
, void **this_cache
)
2863 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2864 CORE_ADDR pc
= get_frame_pc (this_frame
);
2865 if (mips_pc_is_mips16 (gdbarch
, pc
))
2870 static const struct frame_unwind mips_insn16_frame_unwind
=
2873 default_frame_unwind_stop_reason
,
2874 mips_insn16_frame_this_id
,
2875 mips_insn16_frame_prev_register
,
2877 mips_insn16_frame_sniffer
2881 mips_insn16_frame_base_address (struct frame_info
*this_frame
,
2884 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2889 static const struct frame_base mips_insn16_frame_base
=
2891 &mips_insn16_frame_unwind
,
2892 mips_insn16_frame_base_address
,
2893 mips_insn16_frame_base_address
,
2894 mips_insn16_frame_base_address
2897 static const struct frame_base
*
2898 mips_insn16_frame_base_sniffer (struct frame_info
*this_frame
)
2900 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2901 CORE_ADDR pc
= get_frame_pc (this_frame
);
2902 if (mips_pc_is_mips16 (gdbarch
, pc
))
2903 return &mips_insn16_frame_base
;
2908 /* Decode a 9-bit signed immediate argument of ADDIUSP -- -2 is mapped
2909 to -258, -1 -- to -257, 0 -- to 256, 1 -- to 257 and other values are
2910 interpreted directly, and then multiplied by 4. */
2913 micromips_decode_imm9 (int imm
)
2915 imm
= (imm
^ 0x100) - 0x100;
2916 if (imm
> -3 && imm
< 2)
2921 /* Analyze the function prologue from START_PC to LIMIT_PC. Return
2922 the address of the first instruction past the prologue. */
2925 micromips_scan_prologue (struct gdbarch
*gdbarch
,
2926 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2927 struct frame_info
*this_frame
,
2928 struct mips_frame_cache
*this_cache
)
2930 CORE_ADDR end_prologue_addr
;
2931 int prev_non_prologue_insn
= 0;
2932 int frame_reg
= MIPS_SP_REGNUM
;
2933 int this_non_prologue_insn
;
2934 int non_prologue_insns
= 0;
2935 long frame_offset
= 0; /* Size of stack frame. */
2936 long frame_adjust
= 0; /* Offset of FP from SP. */
2937 int prev_delay_slot
= 0;
2941 ULONGEST insn
; /* current instruction */
2945 long v1_off
= 0; /* The assumption is LUI will replace it. */
2956 /* Can be called when there's no process, and hence when there's no
2958 if (this_frame
!= NULL
)
2959 sp
= get_frame_register_signed (this_frame
,
2960 gdbarch_num_regs (gdbarch
)
2965 if (limit_pc
> start_pc
+ 200)
2966 limit_pc
= start_pc
+ 200;
2969 /* Permit at most one non-prologue non-control-transfer instruction
2970 in the middle which may have been reordered by the compiler for
2972 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= loc
)
2974 this_non_prologue_insn
= 0;
2978 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, cur_pc
, NULL
);
2979 loc
+= MIPS_INSN16_SIZE
;
2980 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
2982 /* 32-bit instructions. */
2983 case 2 * MIPS_INSN16_SIZE
:
2985 insn
|= mips_fetch_instruction (gdbarch
,
2986 ISA_MICROMIPS
, cur_pc
+ loc
, NULL
);
2987 loc
+= MIPS_INSN16_SIZE
;
2988 switch (micromips_op (insn
>> 16))
2990 /* Record $sp/$fp adjustment. */
2991 /* Discard (D)ADDU $gp,$jp used for PIC code. */
2992 case 0x0: /* POOL32A: bits 000000 */
2993 case 0x16: /* POOL32S: bits 010110 */
2994 op
= b0s11_op (insn
);
2995 sreg
= b0s5_reg (insn
>> 16);
2996 treg
= b5s5_reg (insn
>> 16);
2997 dreg
= b11s5_reg (insn
);
2999 /* SUBU: bits 000000 00111010000 */
3000 /* DSUBU: bits 010110 00111010000 */
3001 && dreg
== MIPS_SP_REGNUM
&& sreg
== MIPS_SP_REGNUM
3003 /* (D)SUBU $sp, $v1 */
3005 else if (op
!= 0x150
3006 /* ADDU: bits 000000 00101010000 */
3007 /* DADDU: bits 010110 00101010000 */
3008 || dreg
!= 28 || sreg
!= 28 || treg
!= MIPS_T9_REGNUM
)
3009 this_non_prologue_insn
= 1;
3012 case 0x8: /* POOL32B: bits 001000 */
3013 op
= b12s4_op (insn
);
3014 breg
= b0s5_reg (insn
>> 16);
3015 reglist
= sreg
= b5s5_reg (insn
>> 16);
3016 offset
= (b0s12_imm (insn
) ^ 0x800) - 0x800;
3017 if ((op
== 0x9 || op
== 0xc)
3018 /* SWP: bits 001000 1001 */
3019 /* SDP: bits 001000 1100 */
3020 && breg
== MIPS_SP_REGNUM
&& sreg
< MIPS_RA_REGNUM
)
3021 /* S[DW]P reg,offset($sp) */
3023 s
= 4 << ((b12s4_op (insn
) & 0x4) == 0x4);
3024 set_reg_offset (gdbarch
, this_cache
,
3026 set_reg_offset (gdbarch
, this_cache
,
3027 sreg
+ 1, sp
+ offset
+ s
);
3029 else if ((op
== 0xd || op
== 0xf)
3030 /* SWM: bits 001000 1101 */
3031 /* SDM: bits 001000 1111 */
3032 && breg
== MIPS_SP_REGNUM
3033 /* SWM reglist,offset($sp) */
3034 && ((reglist
>= 1 && reglist
<= 9)
3035 || (reglist
>= 16 && reglist
<= 25)))
3037 int sreglist
= std::min(reglist
& 0xf, 8);
3039 s
= 4 << ((b12s4_op (insn
) & 0x2) == 0x2);
3040 for (i
= 0; i
< sreglist
; i
++)
3041 set_reg_offset (gdbarch
, this_cache
, 16 + i
, sp
+ s
* i
);
3042 if ((reglist
& 0xf) > 8)
3043 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ s
* i
++);
3044 if ((reglist
& 0x10) == 0x10)
3045 set_reg_offset (gdbarch
, this_cache
,
3046 MIPS_RA_REGNUM
, sp
+ s
* i
++);
3049 this_non_prologue_insn
= 1;
3052 /* Record $sp/$fp adjustment. */
3053 /* Discard (D)ADDIU $gp used for PIC code. */
3054 case 0xc: /* ADDIU: bits 001100 */
3055 case 0x17: /* DADDIU: bits 010111 */
3056 sreg
= b0s5_reg (insn
>> 16);
3057 dreg
= b5s5_reg (insn
>> 16);
3058 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
3059 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
)
3060 /* (D)ADDIU $sp, imm */
3062 else if (sreg
== MIPS_SP_REGNUM
&& dreg
== 30)
3063 /* (D)ADDIU $fp, $sp, imm */
3065 frame_adjust
= offset
;
3068 else if (sreg
!= 28 || dreg
!= 28)
3069 /* (D)ADDIU $gp, imm */
3070 this_non_prologue_insn
= 1;
3073 /* LUI $v1 is used for larger $sp adjustments. */
3074 /* Discard LUI $gp used for PIC code. */
3075 case 0x10: /* POOL32I: bits 010000 */
3076 if (b5s5_op (insn
>> 16) == 0xd
3077 /* LUI: bits 010000 001101 */
3078 && b0s5_reg (insn
>> 16) == 3)
3080 v1_off
= ((b0s16_imm (insn
) << 16) ^ 0x80000000) - 0x80000000;
3081 else if (b5s5_op (insn
>> 16) != 0xd
3082 /* LUI: bits 010000 001101 */
3083 || b0s5_reg (insn
>> 16) != 28)
3085 this_non_prologue_insn
= 1;
3088 /* ORI $v1 is used for larger $sp adjustments. */
3089 case 0x14: /* ORI: bits 010100 */
3090 sreg
= b0s5_reg (insn
>> 16);
3091 dreg
= b5s5_reg (insn
>> 16);
3092 if (sreg
== 3 && dreg
== 3)
3094 v1_off
|= b0s16_imm (insn
);
3096 this_non_prologue_insn
= 1;
3099 case 0x26: /* SWC1: bits 100110 */
3100 case 0x2e: /* SDC1: bits 101110 */
3101 breg
= b0s5_reg (insn
>> 16);
3102 if (breg
!= MIPS_SP_REGNUM
)
3103 /* S[DW]C1 reg,offset($sp) */
3104 this_non_prologue_insn
= 1;
3107 case 0x36: /* SD: bits 110110 */
3108 case 0x3e: /* SW: bits 111110 */
3109 breg
= b0s5_reg (insn
>> 16);
3110 sreg
= b5s5_reg (insn
>> 16);
3111 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
3112 if (breg
== MIPS_SP_REGNUM
)
3113 /* S[DW] reg,offset($sp) */
3114 set_reg_offset (gdbarch
, this_cache
, sreg
, sp
+ offset
);
3116 this_non_prologue_insn
= 1;
3120 /* The instruction in the delay slot can be a part
3121 of the prologue, so move forward once more. */
3122 if (micromips_instruction_has_delay_slot (insn
, 0))
3125 this_non_prologue_insn
= 1;
3131 /* 16-bit instructions. */
3132 case MIPS_INSN16_SIZE
:
3133 switch (micromips_op (insn
))
3135 case 0x3: /* MOVE: bits 000011 */
3136 sreg
= b0s5_reg (insn
);
3137 dreg
= b5s5_reg (insn
);
3138 if (sreg
== MIPS_SP_REGNUM
&& dreg
== 30)
3141 else if ((sreg
& 0x1c) != 0x4)
3142 /* MOVE reg, $a0-$a3 */
3143 this_non_prologue_insn
= 1;
3146 case 0x11: /* POOL16C: bits 010001 */
3147 if (b6s4_op (insn
) == 0x5)
3148 /* SWM: bits 010001 0101 */
3150 offset
= ((b0s4_imm (insn
) << 2) ^ 0x20) - 0x20;
3151 reglist
= b4s2_regl (insn
);
3152 for (i
= 0; i
<= reglist
; i
++)
3153 set_reg_offset (gdbarch
, this_cache
, 16 + i
, sp
+ 4 * i
);
3154 set_reg_offset (gdbarch
, this_cache
,
3155 MIPS_RA_REGNUM
, sp
+ 4 * i
++);
3158 this_non_prologue_insn
= 1;
3161 case 0x13: /* POOL16D: bits 010011 */
3162 if ((insn
& 0x1) == 0x1)
3163 /* ADDIUSP: bits 010011 1 */
3164 sp_adj
= micromips_decode_imm9 (b1s9_imm (insn
));
3165 else if (b5s5_reg (insn
) == MIPS_SP_REGNUM
)
3166 /* ADDIUS5: bits 010011 0 */
3167 /* ADDIUS5 $sp, imm */
3168 sp_adj
= (b1s4_imm (insn
) ^ 8) - 8;
3170 this_non_prologue_insn
= 1;
3173 case 0x32: /* SWSP: bits 110010 */
3174 offset
= b0s5_imm (insn
) << 2;
3175 sreg
= b5s5_reg (insn
);
3176 set_reg_offset (gdbarch
, this_cache
, sreg
, sp
+ offset
);
3180 /* The instruction in the delay slot can be a part
3181 of the prologue, so move forward once more. */
3182 if (micromips_instruction_has_delay_slot (insn
<< 16, 0))
3185 this_non_prologue_insn
= 1;
3191 frame_offset
-= sp_adj
;
3193 non_prologue_insns
+= this_non_prologue_insn
;
3195 /* A jump or branch, enough non-prologue insns seen or positive
3196 stack adjustment? If so, then we must have reached the end
3197 of the prologue by now. */
3198 if (prev_delay_slot
|| non_prologue_insns
> 1 || sp_adj
> 0
3199 || micromips_instruction_is_compact_branch (insn
))
3202 prev_non_prologue_insn
= this_non_prologue_insn
;
3203 prev_delay_slot
= in_delay_slot
;
3207 if (this_cache
!= NULL
)
3210 (get_frame_register_signed (this_frame
,
3211 gdbarch_num_regs (gdbarch
) + frame_reg
)
3212 + frame_offset
- frame_adjust
);
3213 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
3214 be able to get rid of the assignment below, evetually. But it's
3215 still needed for now. */
3216 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3217 + mips_regnum (gdbarch
)->pc
]
3218 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
3221 /* Set end_prologue_addr to the address of the instruction immediately
3222 after the last one we scanned. Unless the last one looked like a
3223 non-prologue instruction (and we looked ahead), in which case use
3224 its address instead. */
3226 = prev_non_prologue_insn
|| prev_delay_slot
? prev_pc
: cur_pc
;
3228 return end_prologue_addr
;
3231 /* Heuristic unwinder for procedures using microMIPS instructions.
3232 Procedures that use the 32-bit instruction set are handled by the
3233 mips_insn32 unwinder. Likewise MIPS16 and the mips_insn16 unwinder. */
3235 static struct mips_frame_cache
*
3236 mips_micro_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3238 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3239 struct mips_frame_cache
*cache
;
3241 if ((*this_cache
) != NULL
)
3242 return (struct mips_frame_cache
*) (*this_cache
);
3244 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
3245 (*this_cache
) = cache
;
3246 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3248 /* Analyze the function prologue. */
3250 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3251 CORE_ADDR start_addr
;
3253 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3254 if (start_addr
== 0)
3255 start_addr
= heuristic_proc_start (get_frame_arch (this_frame
), pc
);
3256 /* We can't analyze the prologue if we couldn't find the begining
3258 if (start_addr
== 0)
3261 micromips_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
3262 (struct mips_frame_cache
*) *this_cache
);
3265 /* gdbarch_sp_regnum contains the value and not the address. */
3266 trad_frame_set_value (cache
->saved_regs
,
3267 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
3270 return (struct mips_frame_cache
*) (*this_cache
);
3274 mips_micro_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3275 struct frame_id
*this_id
)
3277 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3279 /* This marks the outermost frame. */
3280 if (info
->base
== 0)
3282 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3285 static struct value
*
3286 mips_micro_frame_prev_register (struct frame_info
*this_frame
,
3287 void **this_cache
, int regnum
)
3289 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3291 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3295 mips_micro_frame_sniffer (const struct frame_unwind
*self
,
3296 struct frame_info
*this_frame
, void **this_cache
)
3298 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3299 CORE_ADDR pc
= get_frame_pc (this_frame
);
3301 if (mips_pc_is_micromips (gdbarch
, pc
))
3306 static const struct frame_unwind mips_micro_frame_unwind
=
3309 default_frame_unwind_stop_reason
,
3310 mips_micro_frame_this_id
,
3311 mips_micro_frame_prev_register
,
3313 mips_micro_frame_sniffer
3317 mips_micro_frame_base_address (struct frame_info
*this_frame
,
3320 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3325 static const struct frame_base mips_micro_frame_base
=
3327 &mips_micro_frame_unwind
,
3328 mips_micro_frame_base_address
,
3329 mips_micro_frame_base_address
,
3330 mips_micro_frame_base_address
3333 static const struct frame_base
*
3334 mips_micro_frame_base_sniffer (struct frame_info
*this_frame
)
3336 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3337 CORE_ADDR pc
= get_frame_pc (this_frame
);
3339 if (mips_pc_is_micromips (gdbarch
, pc
))
3340 return &mips_micro_frame_base
;
3345 /* Mark all the registers as unset in the saved_regs array
3346 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
3349 reset_saved_regs (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
)
3351 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
3355 const int num_regs
= gdbarch_num_regs (gdbarch
);
3358 for (i
= 0; i
< num_regs
; i
++)
3360 this_cache
->saved_regs
[i
].addr
= -1;
3365 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
3366 the associated FRAME_CACHE if not null.
3367 Return the address of the first instruction past the prologue. */
3370 mips32_scan_prologue (struct gdbarch
*gdbarch
,
3371 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
3372 struct frame_info
*this_frame
,
3373 struct mips_frame_cache
*this_cache
)
3375 int prev_non_prologue_insn
;
3376 int this_non_prologue_insn
;
3377 int non_prologue_insns
;
3378 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for
3380 int prev_delay_slot
;
3385 int frame_reg
= MIPS_SP_REGNUM
;
3387 CORE_ADDR end_prologue_addr
;
3388 int seen_sp_adjust
= 0;
3389 int load_immediate_bytes
= 0;
3391 int regsize_is_64_bits
= (mips_abi_regsize (gdbarch
) == 8);
3393 /* Can be called when there's no process, and hence when there's no
3395 if (this_frame
!= NULL
)
3396 sp
= get_frame_register_signed (this_frame
,
3397 gdbarch_num_regs (gdbarch
)
3402 if (limit_pc
> start_pc
+ 200)
3403 limit_pc
= start_pc
+ 200;
3406 prev_non_prologue_insn
= 0;
3407 non_prologue_insns
= 0;
3408 prev_delay_slot
= 0;
3411 /* Permit at most one non-prologue non-control-transfer instruction
3412 in the middle which may have been reordered by the compiler for
3415 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
3417 unsigned long inst
, high_word
;
3421 this_non_prologue_insn
= 0;
3424 /* Fetch the instruction. */
3425 inst
= (unsigned long) mips_fetch_instruction (gdbarch
, ISA_MIPS
,
3428 /* Save some code by pre-extracting some useful fields. */
3429 high_word
= (inst
>> 16) & 0xffff;
3430 offset
= ((inst
& 0xffff) ^ 0x8000) - 0x8000;
3431 reg
= high_word
& 0x1f;
3433 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
3434 || high_word
== 0x23bd /* addi $sp,$sp,-i */
3435 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
3437 if (offset
< 0) /* Negative stack adjustment? */
3438 frame_offset
-= offset
;
3440 /* Exit loop if a positive stack adjustment is found, which
3441 usually means that the stack cleanup code in the function
3442 epilogue is reached. */
3446 else if (((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
3447 && !regsize_is_64_bits
)
3449 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
3451 else if (((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
3452 && regsize_is_64_bits
)
3454 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
3455 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
3457 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
3459 /* Old gcc frame, r30 is virtual frame pointer. */
3460 if (offset
!= frame_offset
)
3461 frame_addr
= sp
+ offset
;
3462 else if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
3464 unsigned alloca_adjust
;
3467 frame_addr
= get_frame_register_signed
3468 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
3471 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ offset
));
3472 if (alloca_adjust
> 0)
3474 /* FP > SP + frame_size. This may be because of
3475 an alloca or somethings similar. Fix sp to
3476 "pre-alloca" value, and try again. */
3477 sp
+= alloca_adjust
;
3478 /* Need to reset the status of all registers. Otherwise,
3479 we will hit a guard that prevents the new address
3480 for each register to be recomputed during the second
3482 reset_saved_regs (gdbarch
, this_cache
);
3487 /* move $30,$sp. With different versions of gas this will be either
3488 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
3489 Accept any one of these. */
3490 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
3492 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
3493 if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
3495 unsigned alloca_adjust
;
3498 frame_addr
= get_frame_register_signed
3499 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
3501 alloca_adjust
= (unsigned) (frame_addr
- sp
);
3502 if (alloca_adjust
> 0)
3504 /* FP > SP + frame_size. This may be because of
3505 an alloca or somethings similar. Fix sp to
3506 "pre-alloca" value, and try again. */
3508 /* Need to reset the status of all registers. Otherwise,
3509 we will hit a guard that prevents the new address
3510 for each register to be recomputed during the second
3512 reset_saved_regs (gdbarch
, this_cache
);
3517 else if ((high_word
& 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
3518 && !regsize_is_64_bits
)
3520 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
3522 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
3523 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
3524 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
3525 || high_word
== 0x3c1c /* lui $gp,n */
3526 || high_word
== 0x279c /* addiu $gp,$gp,n */
3527 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
3528 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
3531 /* These instructions are part of the prologue, but we don't
3532 need to do anything special to handle them. */
3534 /* The instructions below load $at or $t0 with an immediate
3535 value in preparation for a stack adjustment via
3536 subu $sp,$sp,[$at,$t0]. These instructions could also
3537 initialize a local variable, so we accept them only before
3538 a stack adjustment instruction was seen. */
3539 else if (!seen_sp_adjust
3541 && (high_word
== 0x3c01 /* lui $at,n */
3542 || high_word
== 0x3c08 /* lui $t0,n */
3543 || high_word
== 0x3421 /* ori $at,$at,n */
3544 || high_word
== 0x3508 /* ori $t0,$t0,n */
3545 || high_word
== 0x3401 /* ori $at,$zero,n */
3546 || high_word
== 0x3408 /* ori $t0,$zero,n */
3549 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
3551 /* Check for branches and jumps. The instruction in the delay
3552 slot can be a part of the prologue, so move forward once more. */
3553 else if (mips32_instruction_has_delay_slot (gdbarch
, inst
))
3557 /* This instruction is not an instruction typically found
3558 in a prologue, so we must have reached the end of the
3562 this_non_prologue_insn
= 1;
3565 non_prologue_insns
+= this_non_prologue_insn
;
3567 /* A jump or branch, or enough non-prologue insns seen? If so,
3568 then we must have reached the end of the prologue by now. */
3569 if (prev_delay_slot
|| non_prologue_insns
> 1)
3572 prev_non_prologue_insn
= this_non_prologue_insn
;
3573 prev_delay_slot
= in_delay_slot
;
3577 if (this_cache
!= NULL
)
3580 (get_frame_register_signed (this_frame
,
3581 gdbarch_num_regs (gdbarch
) + frame_reg
)
3583 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
3584 this assignment below, eventually. But it's still needed
3586 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3587 + mips_regnum (gdbarch
)->pc
]
3588 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3592 /* Set end_prologue_addr to the address of the instruction immediately
3593 after the last one we scanned. Unless the last one looked like a
3594 non-prologue instruction (and we looked ahead), in which case use
3595 its address instead. */
3597 = prev_non_prologue_insn
|| prev_delay_slot
? prev_pc
: cur_pc
;
3599 /* In a frameless function, we might have incorrectly
3600 skipped some load immediate instructions. Undo the skipping
3601 if the load immediate was not followed by a stack adjustment. */
3602 if (load_immediate_bytes
&& !seen_sp_adjust
)
3603 end_prologue_addr
-= load_immediate_bytes
;
3605 return end_prologue_addr
;
3608 /* Heuristic unwinder for procedures using 32-bit instructions (covers
3609 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
3610 instructions (a.k.a. MIPS16) are handled by the mips_insn16
3611 unwinder. Likewise microMIPS and the mips_micro unwinder. */
3613 static struct mips_frame_cache
*
3614 mips_insn32_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3616 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3617 struct mips_frame_cache
*cache
;
3619 if ((*this_cache
) != NULL
)
3620 return (struct mips_frame_cache
*) (*this_cache
);
3622 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
3623 (*this_cache
) = cache
;
3624 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3626 /* Analyze the function prologue. */
3628 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3629 CORE_ADDR start_addr
;
3631 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3632 if (start_addr
== 0)
3633 start_addr
= heuristic_proc_start (gdbarch
, pc
);
3634 /* We can't analyze the prologue if we couldn't find the begining
3636 if (start_addr
== 0)
3639 mips32_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
3640 (struct mips_frame_cache
*) *this_cache
);
3643 /* gdbarch_sp_regnum contains the value and not the address. */
3644 trad_frame_set_value (cache
->saved_regs
,
3645 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
3648 return (struct mips_frame_cache
*) (*this_cache
);
3652 mips_insn32_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3653 struct frame_id
*this_id
)
3655 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3657 /* This marks the outermost frame. */
3658 if (info
->base
== 0)
3660 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3663 static struct value
*
3664 mips_insn32_frame_prev_register (struct frame_info
*this_frame
,
3665 void **this_cache
, int regnum
)
3667 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3669 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3673 mips_insn32_frame_sniffer (const struct frame_unwind
*self
,
3674 struct frame_info
*this_frame
, void **this_cache
)
3676 CORE_ADDR pc
= get_frame_pc (this_frame
);
3677 if (mips_pc_is_mips (pc
))
3682 static const struct frame_unwind mips_insn32_frame_unwind
=
3685 default_frame_unwind_stop_reason
,
3686 mips_insn32_frame_this_id
,
3687 mips_insn32_frame_prev_register
,
3689 mips_insn32_frame_sniffer
3693 mips_insn32_frame_base_address (struct frame_info
*this_frame
,
3696 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3701 static const struct frame_base mips_insn32_frame_base
=
3703 &mips_insn32_frame_unwind
,
3704 mips_insn32_frame_base_address
,
3705 mips_insn32_frame_base_address
,
3706 mips_insn32_frame_base_address
3709 static const struct frame_base
*
3710 mips_insn32_frame_base_sniffer (struct frame_info
*this_frame
)
3712 CORE_ADDR pc
= get_frame_pc (this_frame
);
3713 if (mips_pc_is_mips (pc
))
3714 return &mips_insn32_frame_base
;
3719 static struct trad_frame_cache
*
3720 mips_stub_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3723 CORE_ADDR start_addr
;
3724 CORE_ADDR stack_addr
;
3725 struct trad_frame_cache
*this_trad_cache
;
3726 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3727 int num_regs
= gdbarch_num_regs (gdbarch
);
3729 if ((*this_cache
) != NULL
)
3730 return (struct trad_frame_cache
*) (*this_cache
);
3731 this_trad_cache
= trad_frame_cache_zalloc (this_frame
);
3732 (*this_cache
) = this_trad_cache
;
3734 /* The return address is in the link register. */
3735 trad_frame_set_reg_realreg (this_trad_cache
,
3736 gdbarch_pc_regnum (gdbarch
),
3737 num_regs
+ MIPS_RA_REGNUM
);
3739 /* Frame ID, since it's a frameless / stackless function, no stack
3740 space is allocated and SP on entry is the current SP. */
3741 pc
= get_frame_pc (this_frame
);
3742 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3743 stack_addr
= get_frame_register_signed (this_frame
,
3744 num_regs
+ MIPS_SP_REGNUM
);
3745 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
3747 /* Assume that the frame's base is the same as the
3749 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
3751 return this_trad_cache
;
3755 mips_stub_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3756 struct frame_id
*this_id
)
3758 struct trad_frame_cache
*this_trad_cache
3759 = mips_stub_frame_cache (this_frame
, this_cache
);
3760 trad_frame_get_id (this_trad_cache
, this_id
);
3763 static struct value
*
3764 mips_stub_frame_prev_register (struct frame_info
*this_frame
,
3765 void **this_cache
, int regnum
)
3767 struct trad_frame_cache
*this_trad_cache
3768 = mips_stub_frame_cache (this_frame
, this_cache
);
3769 return trad_frame_get_register (this_trad_cache
, this_frame
, regnum
);
3773 mips_stub_frame_sniffer (const struct frame_unwind
*self
,
3774 struct frame_info
*this_frame
, void **this_cache
)
3777 struct obj_section
*s
;
3778 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3779 struct bound_minimal_symbol msym
;
3781 /* Use the stub unwinder for unreadable code. */
3782 if (target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
3785 if (in_plt_section (pc
) || in_mips_stubs_section (pc
))
3788 /* Calling a PIC function from a non-PIC function passes through a
3789 stub. The stub for foo is named ".pic.foo". */
3790 msym
= lookup_minimal_symbol_by_pc (pc
);
3791 if (msym
.minsym
!= NULL
3792 && MSYMBOL_LINKAGE_NAME (msym
.minsym
) != NULL
3793 && startswith (MSYMBOL_LINKAGE_NAME (msym
.minsym
), ".pic."))
3799 static const struct frame_unwind mips_stub_frame_unwind
=
3802 default_frame_unwind_stop_reason
,
3803 mips_stub_frame_this_id
,
3804 mips_stub_frame_prev_register
,
3806 mips_stub_frame_sniffer
3810 mips_stub_frame_base_address (struct frame_info
*this_frame
,
3813 struct trad_frame_cache
*this_trad_cache
3814 = mips_stub_frame_cache (this_frame
, this_cache
);
3815 return trad_frame_get_this_base (this_trad_cache
);
3818 static const struct frame_base mips_stub_frame_base
=
3820 &mips_stub_frame_unwind
,
3821 mips_stub_frame_base_address
,
3822 mips_stub_frame_base_address
,
3823 mips_stub_frame_base_address
3826 static const struct frame_base
*
3827 mips_stub_frame_base_sniffer (struct frame_info
*this_frame
)
3829 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind
, this_frame
, NULL
))
3830 return &mips_stub_frame_base
;
3835 /* mips_addr_bits_remove - remove useless address bits */
3838 mips_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
3840 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3842 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
3843 /* This hack is a work-around for existing boards using PMON, the
3844 simulator, and any other 64-bit targets that doesn't have true
3845 64-bit addressing. On these targets, the upper 32 bits of
3846 addresses are ignored by the hardware. Thus, the PC or SP are
3847 likely to have been sign extended to all 1s by instruction
3848 sequences that load 32-bit addresses. For example, a typical
3849 piece of code that loads an address is this:
3851 lui $r2, <upper 16 bits>
3852 ori $r2, <lower 16 bits>
3854 But the lui sign-extends the value such that the upper 32 bits
3855 may be all 1s. The workaround is simply to mask off these
3856 bits. In the future, gcc may be changed to support true 64-bit
3857 addressing, and this masking will have to be disabled. */
3858 return addr
&= 0xffffffffUL
;
3864 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
3865 instruction and ending with a SC/SCD instruction. If such a sequence
3866 is found, attempt to step through it. A breakpoint is placed at the end of
3869 /* Instructions used during single-stepping of atomic sequences, standard
3871 #define LL_OPCODE 0x30
3872 #define LLD_OPCODE 0x34
3873 #define SC_OPCODE 0x38
3874 #define SCD_OPCODE 0x3c
3877 mips_deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
3878 struct address_space
*aspace
, CORE_ADDR pc
)
3880 CORE_ADDR breaks
[2] = {-1, -1};
3882 CORE_ADDR branch_bp
; /* Breakpoint at branch instruction's destination. */
3886 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
3887 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
3889 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, loc
, NULL
);
3890 /* Assume all atomic sequences start with a ll/lld instruction. */
3891 if (itype_op (insn
) != LL_OPCODE
&& itype_op (insn
) != LLD_OPCODE
)
3894 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
3896 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
3899 loc
+= MIPS_INSN32_SIZE
;
3900 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, loc
, NULL
);
3902 /* Assume that there is at most one branch in the atomic
3903 sequence. If a branch is found, put a breakpoint in its
3904 destination address. */
3905 switch (itype_op (insn
))
3907 case 0: /* SPECIAL */
3908 if (rtype_funct (insn
) >> 1 == 4) /* JR, JALR */
3909 return 0; /* fallback to the standard single-step code. */
3911 case 1: /* REGIMM */
3912 is_branch
= ((itype_rt (insn
) & 0xc) == 0 /* B{LT,GE}Z* */
3913 || ((itype_rt (insn
) & 0x1e) == 0
3914 && itype_rs (insn
) == 0)); /* BPOSGE* */
3918 return 0; /* fallback to the standard single-step code. */
3925 case 22: /* BLEZL */
3926 case 23: /* BGTTL */
3930 is_branch
= ((itype_rs (insn
) == 9 || itype_rs (insn
) == 10)
3931 && (itype_rt (insn
) & 0x2) == 0);
3932 if (is_branch
) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */
3937 is_branch
= (itype_rs (insn
) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
3942 branch_bp
= loc
+ mips32_relative_offset (insn
) + 4;
3943 if (last_breakpoint
>= 1)
3944 return 0; /* More than one branch found, fallback to the
3945 standard single-step code. */
3946 breaks
[1] = branch_bp
;
3950 if (itype_op (insn
) == SC_OPCODE
|| itype_op (insn
) == SCD_OPCODE
)
3954 /* Assume that the atomic sequence ends with a sc/scd instruction. */
3955 if (itype_op (insn
) != SC_OPCODE
&& itype_op (insn
) != SCD_OPCODE
)
3958 loc
+= MIPS_INSN32_SIZE
;
3960 /* Insert a breakpoint right after the end of the atomic sequence. */
3963 /* Check for duplicated breakpoints. Check also for a breakpoint
3964 placed (branch instruction's destination) in the atomic sequence. */
3965 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
3966 last_breakpoint
= 0;
3968 /* Effectively inserts the breakpoints. */
3969 for (index
= 0; index
<= last_breakpoint
; index
++)
3970 insert_single_step_breakpoint (gdbarch
, aspace
, breaks
[index
]);
3976 micromips_deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
3977 struct address_space
*aspace
,
3980 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
3981 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
3982 CORE_ADDR breaks
[2] = {-1, -1};
3983 CORE_ADDR branch_bp
= 0; /* Breakpoint at branch instruction's
3991 /* Assume all atomic sequences start with a ll/lld instruction. */
3992 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
3993 if (micromips_op (insn
) != 0x18) /* POOL32C: bits 011000 */
3995 loc
+= MIPS_INSN16_SIZE
;
3997 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
3998 if ((b12s4_op (insn
) & 0xb) != 0x3) /* LL, LLD: bits 011000 0x11 */
4000 loc
+= MIPS_INSN16_SIZE
;
4002 /* Assume all atomic sequences end with an sc/scd instruction. Assume
4003 that no atomic sequence is longer than "atomic_sequence_length"
4005 for (insn_count
= 0;
4006 !sc_found
&& insn_count
< atomic_sequence_length
;
4011 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
4012 loc
+= MIPS_INSN16_SIZE
;
4014 /* Assume that there is at most one conditional branch in the
4015 atomic sequence. If a branch is found, put a breakpoint in
4016 its destination address. */
4017 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
4019 /* 32-bit instructions. */
4020 case 2 * MIPS_INSN16_SIZE
:
4021 switch (micromips_op (insn
))
4023 case 0x10: /* POOL32I: bits 010000 */
4024 if ((b5s5_op (insn
) & 0x18) != 0x0
4025 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
4026 /* BLEZ, BNEZC, BGTZ, BEQZC: 010000 001xx */
4027 && (b5s5_op (insn
) & 0x1d) != 0x11
4028 /* BLTZALS, BGEZALS: bits 010000 100x1 */
4029 && ((b5s5_op (insn
) & 0x1e) != 0x14
4030 || (insn
& 0x3) != 0x0)
4031 /* BC2F, BC2T: bits 010000 1010x xxx00 */
4032 && (b5s5_op (insn
) & 0x1e) != 0x1a
4033 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
4034 && ((b5s5_op (insn
) & 0x1e) != 0x1c
4035 || (insn
& 0x3) != 0x0)
4036 /* BC1F, BC1T: bits 010000 1110x xxx00 */
4037 && ((b5s5_op (insn
) & 0x1c) != 0x1c
4038 || (insn
& 0x3) != 0x1))
4039 /* BC1ANY*: bits 010000 111xx xxx01 */
4043 case 0x25: /* BEQ: bits 100101 */
4044 case 0x2d: /* BNE: bits 101101 */
4046 insn
|= mips_fetch_instruction (gdbarch
,
4047 ISA_MICROMIPS
, loc
, NULL
);
4048 branch_bp
= (loc
+ MIPS_INSN16_SIZE
4049 + micromips_relative_offset16 (insn
));
4053 case 0x00: /* POOL32A: bits 000000 */
4055 insn
|= mips_fetch_instruction (gdbarch
,
4056 ISA_MICROMIPS
, loc
, NULL
);
4057 if (b0s6_op (insn
) != 0x3c
4058 /* POOL32Axf: bits 000000 ... 111100 */
4059 || (b6s10_ext (insn
) & 0x2bf) != 0x3c)
4060 /* JALR, JALR.HB: 000000 000x111100 111100 */
4061 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
4065 case 0x1d: /* JALS: bits 011101 */
4066 case 0x35: /* J: bits 110101 */
4067 case 0x3d: /* JAL: bits 111101 */
4068 case 0x3c: /* JALX: bits 111100 */
4069 return 0; /* Fall back to the standard single-step code. */
4071 case 0x18: /* POOL32C: bits 011000 */
4072 if ((b12s4_op (insn
) & 0xb) == 0xb)
4073 /* SC, SCD: bits 011000 1x11 */
4077 loc
+= MIPS_INSN16_SIZE
;
4080 /* 16-bit instructions. */
4081 case MIPS_INSN16_SIZE
:
4082 switch (micromips_op (insn
))
4084 case 0x23: /* BEQZ16: bits 100011 */
4085 case 0x2b: /* BNEZ16: bits 101011 */
4086 branch_bp
= loc
+ micromips_relative_offset7 (insn
);
4090 case 0x11: /* POOL16C: bits 010001 */
4091 if ((b5s5_op (insn
) & 0x1c) != 0xc
4092 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
4093 && b5s5_op (insn
) != 0x18)
4094 /* JRADDIUSP: bits 010001 11000 */
4096 return 0; /* Fall back to the standard single-step code. */
4098 case 0x33: /* B16: bits 110011 */
4099 return 0; /* Fall back to the standard single-step code. */
4105 if (last_breakpoint
>= 1)
4106 return 0; /* More than one branch found, fallback to the
4107 standard single-step code. */
4108 breaks
[1] = branch_bp
;
4115 /* Insert a breakpoint right after the end of the atomic sequence. */
4118 /* Check for duplicated breakpoints. Check also for a breakpoint
4119 placed (branch instruction's destination) in the atomic sequence */
4120 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
4121 last_breakpoint
= 0;
4123 /* Effectively inserts the breakpoints. */
4124 for (index
= 0; index
<= last_breakpoint
; index
++)
4125 insert_single_step_breakpoint (gdbarch
, aspace
, breaks
[index
]);
4131 deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
4132 struct address_space
*aspace
, CORE_ADDR pc
)
4134 if (mips_pc_is_mips (pc
))
4135 return mips_deal_with_atomic_sequence (gdbarch
, aspace
, pc
);
4136 else if (mips_pc_is_micromips (gdbarch
, pc
))
4137 return micromips_deal_with_atomic_sequence (gdbarch
, aspace
, pc
);
4142 /* mips_software_single_step() is called just before we want to resume
4143 the inferior, if we want to single-step it but there is no hardware
4144 or kernel single-step support (MIPS on GNU/Linux for example). We find
4145 the target of the coming instruction and breakpoint it. */
4148 mips_software_single_step (struct frame_info
*frame
)
4150 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4151 struct address_space
*aspace
= get_frame_address_space (frame
);
4152 CORE_ADDR pc
, next_pc
;
4154 pc
= get_frame_pc (frame
);
4155 if (deal_with_atomic_sequence (gdbarch
, aspace
, pc
))
4158 next_pc
= mips_next_pc (frame
, pc
);
4160 insert_single_step_breakpoint (gdbarch
, aspace
, next_pc
);
4164 /* Test whether the PC points to the return instruction at the
4165 end of a function. */
4168 mips_about_to_return (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4173 /* This used to check for MIPS16, but this piece of code is never
4174 called for MIPS16 functions. And likewise microMIPS ones. */
4175 gdb_assert (mips_pc_is_mips (pc
));
4177 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
4179 return (insn
& ~hint
) == 0x3e00008; /* jr(.hb) $ra */
4183 /* This fencepost looks highly suspicious to me. Removing it also
4184 seems suspicious as it could affect remote debugging across serial
4188 heuristic_proc_start (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4194 struct inferior
*inf
;
4196 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
4198 fence
= start_pc
- heuristic_fence_post
;
4202 if (heuristic_fence_post
== -1 || fence
< VM_MIN_ADDRESS
)
4203 fence
= VM_MIN_ADDRESS
;
4205 instlen
= mips_pc_is_mips (pc
) ? MIPS_INSN32_SIZE
: MIPS_INSN16_SIZE
;
4207 inf
= current_inferior ();
4209 /* Search back for previous return. */
4210 for (start_pc
-= instlen
;; start_pc
-= instlen
)
4211 if (start_pc
< fence
)
4213 /* It's not clear to me why we reach this point when
4214 stop_soon, but with this test, at least we
4215 don't print out warnings for every child forked (eg, on
4216 decstation). 22apr93 rich@cygnus.com. */
4217 if (inf
->control
.stop_soon
== NO_STOP_QUIETLY
)
4219 static int blurb_printed
= 0;
4221 warning (_("GDB can't find the start of the function at %s."),
4222 paddress (gdbarch
, pc
));
4226 /* This actually happens frequently in embedded
4227 development, when you first connect to a board
4228 and your stack pointer and pc are nowhere in
4229 particular. This message needs to give people
4230 in that situation enough information to
4231 determine that it's no big deal. */
4232 printf_filtered ("\n\
4233 GDB is unable to find the start of the function at %s\n\
4234 and thus can't determine the size of that function's stack frame.\n\
4235 This means that GDB may be unable to access that stack frame, or\n\
4236 the frames below it.\n\
4237 This problem is most likely caused by an invalid program counter or\n\
4239 However, if you think GDB should simply search farther back\n\
4240 from %s for code which looks like the beginning of a\n\
4241 function, you can increase the range of the search using the `set\n\
4242 heuristic-fence-post' command.\n",
4243 paddress (gdbarch
, pc
), paddress (gdbarch
, pc
));
4250 else if (mips_pc_is_mips16 (gdbarch
, start_pc
))
4252 unsigned short inst
;
4254 /* On MIPS16, any one of the following is likely to be the
4255 start of a function:
4261 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */
4262 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, start_pc
, NULL
);
4263 if ((inst
& 0xff80) == 0x6480) /* save */
4265 if (start_pc
- instlen
>= fence
)
4267 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
,
4268 start_pc
- instlen
, NULL
);
4269 if ((inst
& 0xf800) == 0xf000) /* extend */
4270 start_pc
-= instlen
;
4274 else if (((inst
& 0xf81f) == 0xe809
4275 && (inst
& 0x700) != 0x700) /* entry */
4276 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
4277 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
4278 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
4280 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
4281 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
4286 else if (mips_pc_is_micromips (gdbarch
, start_pc
))
4294 /* On microMIPS, any one of the following is likely to be the
4295 start of a function:
4299 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
4300 switch (micromips_op (insn
))
4302 case 0xc: /* ADDIU: bits 001100 */
4303 case 0x17: /* DADDIU: bits 010111 */
4304 sreg
= b0s5_reg (insn
);
4305 dreg
= b5s5_reg (insn
);
4307 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
,
4308 pc
+ MIPS_INSN16_SIZE
, NULL
);
4309 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
4310 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
4311 /* (D)ADDIU $sp, imm */
4316 case 0x10: /* POOL32I: bits 010000 */
4317 if (b5s5_op (insn
) == 0xd
4318 /* LUI: bits 010000 001101 */
4319 && b0s5_reg (insn
>> 16) == 28)
4324 case 0x13: /* POOL16D: bits 010011 */
4325 if ((insn
& 0x1) == 0x1)
4326 /* ADDIUSP: bits 010011 1 */
4328 offset
= micromips_decode_imm9 (b1s9_imm (insn
));
4334 /* ADDIUS5: bits 010011 0 */
4336 dreg
= b5s5_reg (insn
);
4337 offset
= (b1s4_imm (insn
) ^ 8) - 8;
4338 if (dreg
== MIPS_SP_REGNUM
&& offset
< 0)
4339 /* ADDIUS5 $sp, -imm */
4347 else if (mips_about_to_return (gdbarch
, start_pc
))
4349 /* Skip return and its delay slot. */
4350 start_pc
+= 2 * MIPS_INSN32_SIZE
;
4357 struct mips_objfile_private
4363 /* According to the current ABI, should the type be passed in a
4364 floating-point register (assuming that there is space)? When there
4365 is no FPU, FP are not even considered as possible candidates for
4366 FP registers and, consequently this returns false - forces FP
4367 arguments into integer registers. */
4370 fp_register_arg_p (struct gdbarch
*gdbarch
, enum type_code typecode
,
4371 struct type
*arg_type
)
4373 return ((typecode
== TYPE_CODE_FLT
4374 || (MIPS_EABI (gdbarch
)
4375 && (typecode
== TYPE_CODE_STRUCT
4376 || typecode
== TYPE_CODE_UNION
)
4377 && TYPE_NFIELDS (arg_type
) == 1
4378 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type
, 0)))
4380 && MIPS_FPU_TYPE(gdbarch
) != MIPS_FPU_NONE
);
4383 /* On o32, argument passing in GPRs depends on the alignment of the type being
4384 passed. Return 1 if this type must be aligned to a doubleword boundary. */
4387 mips_type_needs_double_align (struct type
*type
)
4389 enum type_code typecode
= TYPE_CODE (type
);
4391 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
4393 else if (typecode
== TYPE_CODE_STRUCT
)
4395 if (TYPE_NFIELDS (type
) < 1)
4397 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
4399 else if (typecode
== TYPE_CODE_UNION
)
4403 n
= TYPE_NFIELDS (type
);
4404 for (i
= 0; i
< n
; i
++)
4405 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
4412 /* Adjust the address downward (direction of stack growth) so that it
4413 is correctly aligned for a new stack frame. */
4415 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
4417 return align_down (addr
, 16);
4420 /* Implement the "push_dummy_code" gdbarch method. */
4423 mips_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
4424 CORE_ADDR funaddr
, struct value
**args
,
4425 int nargs
, struct type
*value_type
,
4426 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
4427 struct regcache
*regcache
)
4429 static gdb_byte nop_insn
[] = { 0, 0, 0, 0 };
4433 /* Reserve enough room on the stack for our breakpoint instruction. */
4434 bp_slot
= sp
- sizeof (nop_insn
);
4436 /* Return to microMIPS mode if calling microMIPS code to avoid
4437 triggering an address error exception on processors that only
4438 support microMIPS execution. */
4439 *bp_addr
= (mips_pc_is_micromips (gdbarch
, funaddr
)
4440 ? make_compact_addr (bp_slot
) : bp_slot
);
4442 /* The breakpoint layer automatically adjusts the address of
4443 breakpoints inserted in a branch delay slot. With enough
4444 bad luck, the 4 bytes located just before our breakpoint
4445 instruction could look like a branch instruction, and thus
4446 trigger the adjustement, and break the function call entirely.
4447 So, we reserve those 4 bytes and write a nop instruction
4448 to prevent that from happening. */
4449 nop_addr
= bp_slot
- sizeof (nop_insn
);
4450 write_memory (nop_addr
, nop_insn
, sizeof (nop_insn
));
4451 sp
= mips_frame_align (gdbarch
, nop_addr
);
4453 /* Inferior resumes at the function entry point. */
4460 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4461 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4462 int nargs
, struct value
**args
, CORE_ADDR sp
,
4463 int struct_return
, CORE_ADDR struct_addr
)
4469 int stack_offset
= 0;
4470 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4471 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4472 int regsize
= mips_abi_regsize (gdbarch
);
4474 /* For shared libraries, "t9" needs to point at the function
4476 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4478 /* Set the return address register to point to the entry point of
4479 the program, where a breakpoint lies in wait. */
4480 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4482 /* First ensure that the stack and structure return address (if any)
4483 are properly aligned. The stack has to be at least 64-bit
4484 aligned even on 32-bit machines, because doubles must be 64-bit
4485 aligned. For n32 and n64, stack frames need to be 128-bit
4486 aligned, so we round to this widest known alignment. */
4488 sp
= align_down (sp
, 16);
4489 struct_addr
= align_down (struct_addr
, 16);
4491 /* Now make space on the stack for the args. We allocate more
4492 than necessary for EABI, because the first few arguments are
4493 passed in registers, but that's OK. */
4494 for (argnum
= 0; argnum
< nargs
; argnum
++)
4495 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), regsize
);
4496 sp
-= align_up (len
, 16);
4499 fprintf_unfiltered (gdb_stdlog
,
4500 "mips_eabi_push_dummy_call: sp=%s allocated %ld\n",
4501 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
4503 /* Initialize the integer and float register pointers. */
4504 argreg
= MIPS_A0_REGNUM
;
4505 float_argreg
= mips_fpa0_regnum (gdbarch
);
4507 /* The struct_return pointer occupies the first parameter-passing reg. */
4511 fprintf_unfiltered (gdb_stdlog
,
4512 "mips_eabi_push_dummy_call: "
4513 "struct_return reg=%d %s\n",
4514 argreg
, paddress (gdbarch
, struct_addr
));
4515 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4518 /* Now load as many as possible of the first arguments into
4519 registers, and push the rest onto the stack. Loop thru args
4520 from first to last. */
4521 for (argnum
= 0; argnum
< nargs
; argnum
++)
4523 const gdb_byte
*val
;
4524 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
4525 struct value
*arg
= args
[argnum
];
4526 struct type
*arg_type
= check_typedef (value_type (arg
));
4527 int len
= TYPE_LENGTH (arg_type
);
4528 enum type_code typecode
= TYPE_CODE (arg_type
);
4531 fprintf_unfiltered (gdb_stdlog
,
4532 "mips_eabi_push_dummy_call: %d len=%d type=%d",
4533 argnum
+ 1, len
, (int) typecode
);
4535 /* The EABI passes structures that do not fit in a register by
4538 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
4540 store_unsigned_integer (valbuf
, regsize
, byte_order
,
4541 value_address (arg
));
4542 typecode
= TYPE_CODE_PTR
;
4546 fprintf_unfiltered (gdb_stdlog
, " push");
4549 val
= value_contents (arg
);
4551 /* 32-bit ABIs always start floating point arguments in an
4552 even-numbered floating point register. Round the FP register
4553 up before the check to see if there are any FP registers
4554 left. Non MIPS_EABI targets also pass the FP in the integer
4555 registers so also round up normal registers. */
4556 if (regsize
< 8 && fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4558 if ((float_argreg
& 1))
4562 /* Floating point arguments passed in registers have to be
4563 treated specially. On 32-bit architectures, doubles
4564 are passed in register pairs; the even register gets
4565 the low word, and the odd register gets the high word.
4566 On non-EABI processors, the first two floating point arguments are
4567 also copied to general registers, because MIPS16 functions
4568 don't use float registers for arguments. This duplication of
4569 arguments in general registers can't hurt non-MIPS16 functions
4570 because those registers are normally skipped. */
4571 /* MIPS_EABI squeezes a struct that contains a single floating
4572 point value into an FP register instead of pushing it onto the
4574 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4575 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
4577 /* EABI32 will pass doubles in consecutive registers, even on
4578 64-bit cores. At one time, we used to check the size of
4579 `float_argreg' to determine whether or not to pass doubles
4580 in consecutive registers, but this is not sufficient for
4581 making the ABI determination. */
4582 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
4584 int low_offset
= gdbarch_byte_order (gdbarch
)
4585 == BFD_ENDIAN_BIG
? 4 : 0;
4588 /* Write the low word of the double to the even register(s). */
4589 regval
= extract_signed_integer (val
+ low_offset
,
4592 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4593 float_argreg
, phex (regval
, 4));
4594 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4596 /* Write the high word of the double to the odd register(s). */
4597 regval
= extract_signed_integer (val
+ 4 - low_offset
,
4600 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4601 float_argreg
, phex (regval
, 4));
4602 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4606 /* This is a floating point value that fits entirely
4607 in a single register. */
4608 /* On 32 bit ABI's the float_argreg is further adjusted
4609 above to ensure that it is even register aligned. */
4610 LONGEST regval
= extract_signed_integer (val
, len
, byte_order
);
4612 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4613 float_argreg
, phex (regval
, len
));
4614 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4619 /* Copy the argument to general registers or the stack in
4620 register-sized pieces. Large arguments are split between
4621 registers and stack. */
4622 /* Note: structs whose size is not a multiple of regsize
4623 are treated specially: Irix cc passes
4624 them in registers where gcc sometimes puts them on the
4625 stack. For maximum compatibility, we will put them in
4627 int odd_sized_struct
= (len
> regsize
&& len
% regsize
!= 0);
4629 /* Note: Floating-point values that didn't fit into an FP
4630 register are only written to memory. */
4633 /* Remember if the argument was written to the stack. */
4634 int stack_used_p
= 0;
4635 int partial_len
= (len
< regsize
? len
: regsize
);
4638 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4641 /* Write this portion of the argument to the stack. */
4642 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
4644 || fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4646 /* Should shorter than int integer values be
4647 promoted to int before being stored? */
4648 int longword_offset
= 0;
4651 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4654 && (typecode
== TYPE_CODE_INT
4655 || typecode
== TYPE_CODE_PTR
4656 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
4657 longword_offset
= regsize
- len
;
4658 else if ((typecode
== TYPE_CODE_STRUCT
4659 || typecode
== TYPE_CODE_UNION
)
4660 && TYPE_LENGTH (arg_type
) < regsize
)
4661 longword_offset
= regsize
- len
;
4666 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
4667 paddress (gdbarch
, stack_offset
));
4668 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
4669 paddress (gdbarch
, longword_offset
));
4672 addr
= sp
+ stack_offset
+ longword_offset
;
4677 fprintf_unfiltered (gdb_stdlog
, " @%s ",
4678 paddress (gdbarch
, addr
));
4679 for (i
= 0; i
< partial_len
; i
++)
4681 fprintf_unfiltered (gdb_stdlog
, "%02x",
4685 write_memory (addr
, val
, partial_len
);
4688 /* Note!!! This is NOT an else clause. Odd sized
4689 structs may go thru BOTH paths. Floating point
4690 arguments will not. */
4691 /* Write this portion of the argument to a general
4692 purpose register. */
4693 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
)
4694 && !fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4697 extract_signed_integer (val
, partial_len
, byte_order
);
4700 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4702 phex (regval
, regsize
));
4703 regcache_cooked_write_signed (regcache
, argreg
, regval
);
4710 /* Compute the offset into the stack at which we will
4711 copy the next parameter.
4713 In the new EABI (and the NABI32), the stack_offset
4714 only needs to be adjusted when it has been used. */
4717 stack_offset
+= align_up (partial_len
, regsize
);
4721 fprintf_unfiltered (gdb_stdlog
, "\n");
4724 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4726 /* Return adjusted stack pointer. */
4730 /* Determine the return value convention being used. */
4732 static enum return_value_convention
4733 mips_eabi_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
4734 struct type
*type
, struct regcache
*regcache
,
4735 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4737 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4738 int fp_return_type
= 0;
4739 int offset
, regnum
, xfer
;
4741 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
4742 return RETURN_VALUE_STRUCT_CONVENTION
;
4744 /* Floating point type? */
4745 if (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4747 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
4749 /* Structs with a single field of float type
4750 are returned in a floating point register. */
4751 if ((TYPE_CODE (type
) == TYPE_CODE_STRUCT
4752 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4753 && TYPE_NFIELDS (type
) == 1)
4755 struct type
*fieldtype
= TYPE_FIELD_TYPE (type
, 0);
4757 if (TYPE_CODE (check_typedef (fieldtype
)) == TYPE_CODE_FLT
)
4764 /* A floating-point value belongs in the least significant part
4767 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4768 regnum
= mips_regnum (gdbarch
)->fp0
;
4772 /* An integer value goes in V0/V1. */
4774 fprintf_unfiltered (gdb_stderr
, "Return scalar in $v0\n");
4775 regnum
= MIPS_V0_REGNUM
;
4778 offset
< TYPE_LENGTH (type
);
4779 offset
+= mips_abi_regsize (gdbarch
), regnum
++)
4781 xfer
= mips_abi_regsize (gdbarch
);
4782 if (offset
+ xfer
> TYPE_LENGTH (type
))
4783 xfer
= TYPE_LENGTH (type
) - offset
;
4784 mips_xfer_register (gdbarch
, regcache
,
4785 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
4786 gdbarch_byte_order (gdbarch
), readbuf
, writebuf
,
4790 return RETURN_VALUE_REGISTER_CONVENTION
;
4794 /* N32/N64 ABI stuff. */
4796 /* Search for a naturally aligned double at OFFSET inside a struct
4797 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
4801 mips_n32n64_fp_arg_chunk_p (struct gdbarch
*gdbarch
, struct type
*arg_type
,
4806 if (TYPE_CODE (arg_type
) != TYPE_CODE_STRUCT
)
4809 if (MIPS_FPU_TYPE (gdbarch
) != MIPS_FPU_DOUBLE
)
4812 if (TYPE_LENGTH (arg_type
) < offset
+ MIPS64_REGSIZE
)
4815 for (i
= 0; i
< TYPE_NFIELDS (arg_type
); i
++)
4818 struct type
*field_type
;
4820 /* We're only looking at normal fields. */
4821 if (field_is_static (&TYPE_FIELD (arg_type
, i
))
4822 || (TYPE_FIELD_BITPOS (arg_type
, i
) % 8) != 0)
4825 /* If we have gone past the offset, there is no double to pass. */
4826 pos
= TYPE_FIELD_BITPOS (arg_type
, i
) / 8;
4830 field_type
= check_typedef (TYPE_FIELD_TYPE (arg_type
, i
));
4832 /* If this field is entirely before the requested offset, go
4833 on to the next one. */
4834 if (pos
+ TYPE_LENGTH (field_type
) <= offset
)
4837 /* If this is our special aligned double, we can stop. */
4838 if (TYPE_CODE (field_type
) == TYPE_CODE_FLT
4839 && TYPE_LENGTH (field_type
) == MIPS64_REGSIZE
)
4842 /* This field starts at or before the requested offset, and
4843 overlaps it. If it is a structure, recurse inwards. */
4844 return mips_n32n64_fp_arg_chunk_p (gdbarch
, field_type
, offset
- pos
);
4851 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4852 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4853 int nargs
, struct value
**args
, CORE_ADDR sp
,
4854 int struct_return
, CORE_ADDR struct_addr
)
4860 int stack_offset
= 0;
4861 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4862 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4864 /* For shared libraries, "t9" needs to point at the function
4866 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4868 /* Set the return address register to point to the entry point of
4869 the program, where a breakpoint lies in wait. */
4870 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4872 /* First ensure that the stack and structure return address (if any)
4873 are properly aligned. The stack has to be at least 64-bit
4874 aligned even on 32-bit machines, because doubles must be 64-bit
4875 aligned. For n32 and n64, stack frames need to be 128-bit
4876 aligned, so we round to this widest known alignment. */
4878 sp
= align_down (sp
, 16);
4879 struct_addr
= align_down (struct_addr
, 16);
4881 /* Now make space on the stack for the args. */
4882 for (argnum
= 0; argnum
< nargs
; argnum
++)
4883 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), MIPS64_REGSIZE
);
4884 sp
-= align_up (len
, 16);
4887 fprintf_unfiltered (gdb_stdlog
,
4888 "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n",
4889 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
4891 /* Initialize the integer and float register pointers. */
4892 argreg
= MIPS_A0_REGNUM
;
4893 float_argreg
= mips_fpa0_regnum (gdbarch
);
4895 /* The struct_return pointer occupies the first parameter-passing reg. */
4899 fprintf_unfiltered (gdb_stdlog
,
4900 "mips_n32n64_push_dummy_call: "
4901 "struct_return reg=%d %s\n",
4902 argreg
, paddress (gdbarch
, struct_addr
));
4903 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4906 /* Now load as many as possible of the first arguments into
4907 registers, and push the rest onto the stack. Loop thru args
4908 from first to last. */
4909 for (argnum
= 0; argnum
< nargs
; argnum
++)
4911 const gdb_byte
*val
;
4912 struct value
*arg
= args
[argnum
];
4913 struct type
*arg_type
= check_typedef (value_type (arg
));
4914 int len
= TYPE_LENGTH (arg_type
);
4915 enum type_code typecode
= TYPE_CODE (arg_type
);
4918 fprintf_unfiltered (gdb_stdlog
,
4919 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
4920 argnum
+ 1, len
, (int) typecode
);
4922 val
= value_contents (arg
);
4924 /* A 128-bit long double value requires an even-odd pair of
4925 floating-point registers. */
4927 && fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4928 && (float_argreg
& 1))
4934 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4935 && argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
4937 /* This is a floating point value that fits entirely
4938 in a single register or a pair of registers. */
4939 int reglen
= (len
<= MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
4940 LONGEST regval
= extract_unsigned_integer (val
, reglen
, byte_order
);
4942 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4943 float_argreg
, phex (regval
, reglen
));
4944 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
4947 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4948 argreg
, phex (regval
, reglen
));
4949 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4954 regval
= extract_unsigned_integer (val
+ reglen
,
4955 reglen
, byte_order
);
4957 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4958 float_argreg
, phex (regval
, reglen
));
4959 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
4962 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4963 argreg
, phex (regval
, reglen
));
4964 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4971 /* Copy the argument to general registers or the stack in
4972 register-sized pieces. Large arguments are split between
4973 registers and stack. */
4974 /* For N32/N64, structs, unions, or other composite types are
4975 treated as a sequence of doublewords, and are passed in integer
4976 or floating point registers as though they were simple scalar
4977 parameters to the extent that they fit, with any excess on the
4978 stack packed according to the normal memory layout of the
4980 The caller does not reserve space for the register arguments;
4981 the callee is responsible for reserving it if required. */
4982 /* Note: Floating-point values that didn't fit into an FP
4983 register are only written to memory. */
4986 /* Remember if the argument was written to the stack. */
4987 int stack_used_p
= 0;
4988 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
4991 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4994 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4995 gdb_assert (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
));
4997 /* Write this portion of the argument to the stack. */
4998 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
))
5000 /* Should shorter than int integer values be
5001 promoted to int before being stored? */
5002 int longword_offset
= 0;
5005 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5007 if ((typecode
== TYPE_CODE_INT
5008 || typecode
== TYPE_CODE_PTR
)
5010 longword_offset
= MIPS64_REGSIZE
- len
;
5015 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
5016 paddress (gdbarch
, stack_offset
));
5017 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
5018 paddress (gdbarch
, longword_offset
));
5021 addr
= sp
+ stack_offset
+ longword_offset
;
5026 fprintf_unfiltered (gdb_stdlog
, " @%s ",
5027 paddress (gdbarch
, addr
));
5028 for (i
= 0; i
< partial_len
; i
++)
5030 fprintf_unfiltered (gdb_stdlog
, "%02x",
5034 write_memory (addr
, val
, partial_len
);
5037 /* Note!!! This is NOT an else clause. Odd sized
5038 structs may go thru BOTH paths. */
5039 /* Write this portion of the argument to a general
5040 purpose register. */
5041 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
5045 /* Sign extend pointers, 32-bit integers and signed
5046 16-bit and 8-bit integers; everything else is taken
5049 if ((partial_len
== 4
5050 && (typecode
== TYPE_CODE_PTR
5051 || typecode
== TYPE_CODE_INT
))
5053 && typecode
== TYPE_CODE_INT
5054 && !TYPE_UNSIGNED (arg_type
)))
5055 regval
= extract_signed_integer (val
, partial_len
,
5058 regval
= extract_unsigned_integer (val
, partial_len
,
5061 /* A non-floating-point argument being passed in a
5062 general register. If a struct or union, and if
5063 the remaining length is smaller than the register
5064 size, we have to adjust the register value on
5067 It does not seem to be necessary to do the
5068 same for integral types. */
5070 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
5071 && partial_len
< MIPS64_REGSIZE
5072 && (typecode
== TYPE_CODE_STRUCT
5073 || typecode
== TYPE_CODE_UNION
))
5074 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
5078 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
5080 phex (regval
, MIPS64_REGSIZE
));
5081 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5083 if (mips_n32n64_fp_arg_chunk_p (gdbarch
, arg_type
,
5084 TYPE_LENGTH (arg_type
) - len
))
5087 fprintf_filtered (gdb_stdlog
, " - fpreg=%d val=%s",
5089 phex (regval
, MIPS64_REGSIZE
));
5090 regcache_cooked_write_unsigned (regcache
, float_argreg
,
5101 /* Compute the offset into the stack at which we will
5102 copy the next parameter.
5104 In N32 (N64?), the stack_offset only needs to be
5105 adjusted when it has been used. */
5108 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
5112 fprintf_unfiltered (gdb_stdlog
, "\n");
5115 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
5117 /* Return adjusted stack pointer. */
5121 static enum return_value_convention
5122 mips_n32n64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
5123 struct type
*type
, struct regcache
*regcache
,
5124 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5126 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5128 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
5130 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
5131 if needed), as appropriate for the type. Composite results (struct,
5132 union, or array) are returned in $2/$f0 and $3/$f2 according to the
5135 * A struct with only one or two floating point fields is returned in $f0
5136 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
5139 * Any other composite results of at most 128 bits are returned in
5140 $2 (first 64 bits) and $3 (remainder, if necessary).
5142 * Larger composite results are handled by converting the function to a
5143 procedure with an implicit first parameter, which is a pointer to an area
5144 reserved by the caller to receive the result. [The o32-bit ABI requires
5145 that all composite results be handled by conversion to implicit first
5146 parameters. The MIPS/SGI Fortran implementation has always made a
5147 specific exception to return COMPLEX results in the floating point
5150 if (TYPE_LENGTH (type
) > 2 * MIPS64_REGSIZE
)
5151 return RETURN_VALUE_STRUCT_CONVENTION
;
5152 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
5153 && TYPE_LENGTH (type
) == 16
5154 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5156 /* A 128-bit floating-point value fills both $f0 and $f2. The
5157 two registers are used in the same as memory order, so the
5158 eight bytes with the lower memory address are in $f0. */
5160 fprintf_unfiltered (gdb_stderr
, "Return float in $f0 and $f2\n");
5161 mips_xfer_register (gdbarch
, regcache
,
5162 (gdbarch_num_regs (gdbarch
)
5163 + mips_regnum (gdbarch
)->fp0
),
5164 8, gdbarch_byte_order (gdbarch
),
5165 readbuf
, writebuf
, 0);
5166 mips_xfer_register (gdbarch
, regcache
,
5167 (gdbarch_num_regs (gdbarch
)
5168 + mips_regnum (gdbarch
)->fp0
+ 2),
5169 8, gdbarch_byte_order (gdbarch
),
5170 readbuf
? readbuf
+ 8 : readbuf
,
5171 writebuf
? writebuf
+ 8 : writebuf
, 0);
5172 return RETURN_VALUE_REGISTER_CONVENTION
;
5174 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
5175 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5177 /* A single or double floating-point value that fits in FP0. */
5179 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
5180 mips_xfer_register (gdbarch
, regcache
,
5181 (gdbarch_num_regs (gdbarch
)
5182 + mips_regnum (gdbarch
)->fp0
),
5184 gdbarch_byte_order (gdbarch
),
5185 readbuf
, writebuf
, 0);
5186 return RETURN_VALUE_REGISTER_CONVENTION
;
5188 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5189 && TYPE_NFIELDS (type
) <= 2
5190 && TYPE_NFIELDS (type
) >= 1
5191 && ((TYPE_NFIELDS (type
) == 1
5192 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
5194 || (TYPE_NFIELDS (type
) == 2
5195 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
5197 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 1)))
5198 == TYPE_CODE_FLT
))))
5200 /* A struct that contains one or two floats. Each value is part
5201 in the least significant part of their floating point
5202 register (or GPR, for soft float). */
5205 for (field
= 0, regnum
= (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
5206 ? mips_regnum (gdbarch
)->fp0
5208 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
5210 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
5213 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
5215 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)) == 16)
5217 /* A 16-byte long double field goes in two consecutive
5219 mips_xfer_register (gdbarch
, regcache
,
5220 gdbarch_num_regs (gdbarch
) + regnum
,
5222 gdbarch_byte_order (gdbarch
),
5223 readbuf
, writebuf
, offset
);
5224 mips_xfer_register (gdbarch
, regcache
,
5225 gdbarch_num_regs (gdbarch
) + regnum
+ 1,
5227 gdbarch_byte_order (gdbarch
),
5228 readbuf
, writebuf
, offset
+ 8);
5231 mips_xfer_register (gdbarch
, regcache
,
5232 gdbarch_num_regs (gdbarch
) + regnum
,
5233 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
5234 gdbarch_byte_order (gdbarch
),
5235 readbuf
, writebuf
, offset
);
5237 return RETURN_VALUE_REGISTER_CONVENTION
;
5239 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5240 || TYPE_CODE (type
) == TYPE_CODE_UNION
5241 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
5243 /* A composite type. Extract the left justified value,
5244 regardless of the byte order. I.e. DO NOT USE
5248 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5249 offset
< TYPE_LENGTH (type
);
5250 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5252 int xfer
= register_size (gdbarch
, regnum
);
5253 if (offset
+ xfer
> TYPE_LENGTH (type
))
5254 xfer
= TYPE_LENGTH (type
) - offset
;
5256 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5257 offset
, xfer
, regnum
);
5258 mips_xfer_register (gdbarch
, regcache
,
5259 gdbarch_num_regs (gdbarch
) + regnum
,
5260 xfer
, BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
,
5263 return RETURN_VALUE_REGISTER_CONVENTION
;
5267 /* A scalar extract each part but least-significant-byte
5271 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5272 offset
< TYPE_LENGTH (type
);
5273 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5275 int xfer
= register_size (gdbarch
, regnum
);
5276 if (offset
+ xfer
> TYPE_LENGTH (type
))
5277 xfer
= TYPE_LENGTH (type
) - offset
;
5279 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5280 offset
, xfer
, regnum
);
5281 mips_xfer_register (gdbarch
, regcache
,
5282 gdbarch_num_regs (gdbarch
) + regnum
,
5283 xfer
, gdbarch_byte_order (gdbarch
),
5284 readbuf
, writebuf
, offset
);
5286 return RETURN_VALUE_REGISTER_CONVENTION
;
5290 /* Which registers to use for passing floating-point values between
5291 function calls, one of floating-point, general and both kinds of
5292 registers. O32 and O64 use different register kinds for standard
5293 MIPS and MIPS16 code; to make the handling of cases where we may
5294 not know what kind of code is being used (e.g. no debug information)
5295 easier we sometimes use both kinds. */
5304 /* O32 ABI stuff. */
5307 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
5308 struct regcache
*regcache
, CORE_ADDR bp_addr
,
5309 int nargs
, struct value
**args
, CORE_ADDR sp
,
5310 int struct_return
, CORE_ADDR struct_addr
)
5316 int stack_offset
= 0;
5317 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5318 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
5320 /* For shared libraries, "t9" needs to point at the function
5322 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
5324 /* Set the return address register to point to the entry point of
5325 the program, where a breakpoint lies in wait. */
5326 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
5328 /* First ensure that the stack and structure return address (if any)
5329 are properly aligned. The stack has to be at least 64-bit
5330 aligned even on 32-bit machines, because doubles must be 64-bit
5331 aligned. For n32 and n64, stack frames need to be 128-bit
5332 aligned, so we round to this widest known alignment. */
5334 sp
= align_down (sp
, 16);
5335 struct_addr
= align_down (struct_addr
, 16);
5337 /* Now make space on the stack for the args. */
5338 for (argnum
= 0; argnum
< nargs
; argnum
++)
5340 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
5342 /* Align to double-word if necessary. */
5343 if (mips_type_needs_double_align (arg_type
))
5344 len
= align_up (len
, MIPS32_REGSIZE
* 2);
5345 /* Allocate space on the stack. */
5346 len
+= align_up (TYPE_LENGTH (arg_type
), MIPS32_REGSIZE
);
5348 sp
-= align_up (len
, 16);
5351 fprintf_unfiltered (gdb_stdlog
,
5352 "mips_o32_push_dummy_call: sp=%s allocated %ld\n",
5353 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
5355 /* Initialize the integer and float register pointers. */
5356 argreg
= MIPS_A0_REGNUM
;
5357 float_argreg
= mips_fpa0_regnum (gdbarch
);
5359 /* The struct_return pointer occupies the first parameter-passing reg. */
5363 fprintf_unfiltered (gdb_stdlog
,
5364 "mips_o32_push_dummy_call: "
5365 "struct_return reg=%d %s\n",
5366 argreg
, paddress (gdbarch
, struct_addr
));
5367 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
5368 stack_offset
+= MIPS32_REGSIZE
;
5371 /* Now load as many as possible of the first arguments into
5372 registers, and push the rest onto the stack. Loop thru args
5373 from first to last. */
5374 for (argnum
= 0; argnum
< nargs
; argnum
++)
5376 const gdb_byte
*val
;
5377 struct value
*arg
= args
[argnum
];
5378 struct type
*arg_type
= check_typedef (value_type (arg
));
5379 int len
= TYPE_LENGTH (arg_type
);
5380 enum type_code typecode
= TYPE_CODE (arg_type
);
5383 fprintf_unfiltered (gdb_stdlog
,
5384 "mips_o32_push_dummy_call: %d len=%d type=%d",
5385 argnum
+ 1, len
, (int) typecode
);
5387 val
= value_contents (arg
);
5389 /* 32-bit ABIs always start floating point arguments in an
5390 even-numbered floating point register. Round the FP register
5391 up before the check to see if there are any FP registers
5392 left. O32 targets also pass the FP in the integer registers
5393 so also round up normal registers. */
5394 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
5396 if ((float_argreg
& 1))
5400 /* Floating point arguments passed in registers have to be
5401 treated specially. On 32-bit architectures, doubles are
5402 passed in register pairs; the even FP register gets the
5403 low word, and the odd FP register gets the high word.
5404 On O32, the first two floating point arguments are also
5405 copied to general registers, following their memory order,
5406 because MIPS16 functions don't use float registers for
5407 arguments. This duplication of arguments in general
5408 registers can't hurt non-MIPS16 functions, because those
5409 registers are normally skipped. */
5411 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5412 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
5414 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
5416 int freg_offset
= gdbarch_byte_order (gdbarch
)
5417 == BFD_ENDIAN_BIG
? 1 : 0;
5418 unsigned long regval
;
5421 regval
= extract_unsigned_integer (val
, 4, byte_order
);
5423 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5424 float_argreg
+ freg_offset
,
5426 regcache_cooked_write_unsigned (regcache
,
5427 float_argreg
++ + freg_offset
,
5430 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5431 argreg
, phex (regval
, 4));
5432 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5435 regval
= extract_unsigned_integer (val
+ 4, 4, byte_order
);
5437 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5438 float_argreg
- freg_offset
,
5440 regcache_cooked_write_unsigned (regcache
,
5441 float_argreg
++ - freg_offset
,
5444 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5445 argreg
, phex (regval
, 4));
5446 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5450 /* This is a floating point value that fits entirely
5451 in a single register. */
5452 /* On 32 bit ABI's the float_argreg is further adjusted
5453 above to ensure that it is even register aligned. */
5454 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
5456 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5457 float_argreg
, phex (regval
, len
));
5458 regcache_cooked_write_unsigned (regcache
,
5459 float_argreg
++, regval
);
5460 /* Although two FP registers are reserved for each
5461 argument, only one corresponding integer register is
5464 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5465 argreg
, phex (regval
, len
));
5466 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5468 /* Reserve space for the FP register. */
5469 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
5473 /* Copy the argument to general registers or the stack in
5474 register-sized pieces. Large arguments are split between
5475 registers and stack. */
5476 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
5477 are treated specially: Irix cc passes
5478 them in registers where gcc sometimes puts them on the
5479 stack. For maximum compatibility, we will put them in
5481 int odd_sized_struct
= (len
> MIPS32_REGSIZE
5482 && len
% MIPS32_REGSIZE
!= 0);
5483 /* Structures should be aligned to eight bytes (even arg registers)
5484 on MIPS_ABI_O32, if their first member has double precision. */
5485 if (mips_type_needs_double_align (arg_type
))
5490 stack_offset
+= MIPS32_REGSIZE
;
5495 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
5498 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
5501 /* Write this portion of the argument to the stack. */
5502 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
5503 || odd_sized_struct
)
5505 /* Should shorter than int integer values be
5506 promoted to int before being stored? */
5507 int longword_offset
= 0;
5512 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
5513 paddress (gdbarch
, stack_offset
));
5514 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
5515 paddress (gdbarch
, longword_offset
));
5518 addr
= sp
+ stack_offset
+ longword_offset
;
5523 fprintf_unfiltered (gdb_stdlog
, " @%s ",
5524 paddress (gdbarch
, addr
));
5525 for (i
= 0; i
< partial_len
; i
++)
5527 fprintf_unfiltered (gdb_stdlog
, "%02x",
5531 write_memory (addr
, val
, partial_len
);
5534 /* Note!!! This is NOT an else clause. Odd sized
5535 structs may go thru BOTH paths. */
5536 /* Write this portion of the argument to a general
5537 purpose register. */
5538 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
5540 LONGEST regval
= extract_signed_integer (val
, partial_len
,
5542 /* Value may need to be sign extended, because
5543 mips_isa_regsize() != mips_abi_regsize(). */
5545 /* A non-floating-point argument being passed in a
5546 general register. If a struct or union, and if
5547 the remaining length is smaller than the register
5548 size, we have to adjust the register value on
5551 It does not seem to be necessary to do the
5552 same for integral types.
5554 Also don't do this adjustment on O64 binaries.
5556 cagney/2001-07-23: gdb/179: Also, GCC, when
5557 outputting LE O32 with sizeof (struct) <
5558 mips_abi_regsize(), generates a left shift
5559 as part of storing the argument in a register
5560 (the left shift isn't generated when
5561 sizeof (struct) >= mips_abi_regsize()). Since
5562 it is quite possible that this is GCC
5563 contradicting the LE/O32 ABI, GDB has not been
5564 adjusted to accommodate this. Either someone
5565 needs to demonstrate that the LE/O32 ABI
5566 specifies such a left shift OR this new ABI gets
5567 identified as such and GDB gets tweaked
5570 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
5571 && partial_len
< MIPS32_REGSIZE
5572 && (typecode
== TYPE_CODE_STRUCT
5573 || typecode
== TYPE_CODE_UNION
))
5574 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
5578 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
5580 phex (regval
, MIPS32_REGSIZE
));
5581 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5584 /* Prevent subsequent floating point arguments from
5585 being passed in floating point registers. */
5586 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
5592 /* Compute the offset into the stack at which we will
5593 copy the next parameter.
5595 In older ABIs, the caller reserved space for
5596 registers that contained arguments. This was loosely
5597 refered to as their "home". Consequently, space is
5598 always allocated. */
5600 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
5604 fprintf_unfiltered (gdb_stdlog
, "\n");
5607 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
5609 /* Return adjusted stack pointer. */
5613 static enum return_value_convention
5614 mips_o32_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
5615 struct type
*type
, struct regcache
*regcache
,
5616 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5618 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
5619 int mips16
= mips_pc_is_mips16 (gdbarch
, func_addr
);
5620 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5621 enum mips_fval_reg fval_reg
;
5623 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
5624 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5625 || TYPE_CODE (type
) == TYPE_CODE_UNION
5626 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
5627 return RETURN_VALUE_STRUCT_CONVENTION
;
5628 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
5629 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5631 /* A single-precision floating-point value. If reading in or copying,
5632 then we get it from/put it to FP0 for standard MIPS code or GPR2
5633 for MIPS16 code. If writing out only, then we put it to both FP0
5634 and GPR2. We do not support reading in with no function known, if
5635 this safety check ever triggers, then we'll have to try harder. */
5636 gdb_assert (function
|| !readbuf
);
5641 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
5644 fprintf_unfiltered (gdb_stderr
, "Return float in $2\n");
5646 case mips_fval_both
:
5647 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0 and $2\n");
5650 if (fval_reg
!= mips_fval_gpr
)
5651 mips_xfer_register (gdbarch
, regcache
,
5652 (gdbarch_num_regs (gdbarch
)
5653 + mips_regnum (gdbarch
)->fp0
),
5655 gdbarch_byte_order (gdbarch
),
5656 readbuf
, writebuf
, 0);
5657 if (fval_reg
!= mips_fval_fpr
)
5658 mips_xfer_register (gdbarch
, regcache
,
5659 gdbarch_num_regs (gdbarch
) + 2,
5661 gdbarch_byte_order (gdbarch
),
5662 readbuf
, writebuf
, 0);
5663 return RETURN_VALUE_REGISTER_CONVENTION
;
5665 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
5666 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5668 /* A double-precision floating-point value. If reading in or copying,
5669 then we get it from/put it to FP1 and FP0 for standard MIPS code or
5670 GPR2 and GPR3 for MIPS16 code. If writing out only, then we put it
5671 to both FP1/FP0 and GPR2/GPR3. We do not support reading in with
5672 no function known, if this safety check ever triggers, then we'll
5673 have to try harder. */
5674 gdb_assert (function
|| !readbuf
);
5679 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
5682 fprintf_unfiltered (gdb_stderr
, "Return float in $2/$3\n");
5684 case mips_fval_both
:
5685 fprintf_unfiltered (gdb_stderr
,
5686 "Return float in $fp1/$fp0 and $2/$3\n");
5689 if (fval_reg
!= mips_fval_gpr
)
5691 /* The most significant part goes in FP1, and the least significant
5693 switch (gdbarch_byte_order (gdbarch
))
5695 case BFD_ENDIAN_LITTLE
:
5696 mips_xfer_register (gdbarch
, regcache
,
5697 (gdbarch_num_regs (gdbarch
)
5698 + mips_regnum (gdbarch
)->fp0
+ 0),
5699 4, gdbarch_byte_order (gdbarch
),
5700 readbuf
, writebuf
, 0);
5701 mips_xfer_register (gdbarch
, regcache
,
5702 (gdbarch_num_regs (gdbarch
)
5703 + mips_regnum (gdbarch
)->fp0
+ 1),
5704 4, gdbarch_byte_order (gdbarch
),
5705 readbuf
, writebuf
, 4);
5707 case BFD_ENDIAN_BIG
:
5708 mips_xfer_register (gdbarch
, regcache
,
5709 (gdbarch_num_regs (gdbarch
)
5710 + mips_regnum (gdbarch
)->fp0
+ 1),
5711 4, gdbarch_byte_order (gdbarch
),
5712 readbuf
, writebuf
, 0);
5713 mips_xfer_register (gdbarch
, regcache
,
5714 (gdbarch_num_regs (gdbarch
)
5715 + mips_regnum (gdbarch
)->fp0
+ 0),
5716 4, gdbarch_byte_order (gdbarch
),
5717 readbuf
, writebuf
, 4);
5720 internal_error (__FILE__
, __LINE__
, _("bad switch"));
5723 if (fval_reg
!= mips_fval_fpr
)
5725 /* The two 32-bit parts are always placed in GPR2 and GPR3
5726 following these registers' memory order. */
5727 mips_xfer_register (gdbarch
, regcache
,
5728 gdbarch_num_regs (gdbarch
) + 2,
5729 4, gdbarch_byte_order (gdbarch
),
5730 readbuf
, writebuf
, 0);
5731 mips_xfer_register (gdbarch
, regcache
,
5732 gdbarch_num_regs (gdbarch
) + 3,
5733 4, gdbarch_byte_order (gdbarch
),
5734 readbuf
, writebuf
, 4);
5736 return RETURN_VALUE_REGISTER_CONVENTION
;
5739 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5740 && TYPE_NFIELDS (type
) <= 2
5741 && TYPE_NFIELDS (type
) >= 1
5742 && ((TYPE_NFIELDS (type
) == 1
5743 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
5745 || (TYPE_NFIELDS (type
) == 2
5746 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
5748 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
5750 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5752 /* A struct that contains one or two floats. Each value is part
5753 in the least significant part of their floating point
5755 gdb_byte reg
[MAX_REGISTER_SIZE
];
5758 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
5759 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
5761 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
5764 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
5766 mips_xfer_register (gdbarch
, regcache
,
5767 gdbarch_num_regs (gdbarch
) + regnum
,
5768 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
5769 gdbarch_byte_order (gdbarch
),
5770 readbuf
, writebuf
, offset
);
5772 return RETURN_VALUE_REGISTER_CONVENTION
;
5776 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5777 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
5779 /* A structure or union. Extract the left justified value,
5780 regardless of the byte order. I.e. DO NOT USE
5784 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5785 offset
< TYPE_LENGTH (type
);
5786 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5788 int xfer
= register_size (gdbarch
, regnum
);
5789 if (offset
+ xfer
> TYPE_LENGTH (type
))
5790 xfer
= TYPE_LENGTH (type
) - offset
;
5792 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5793 offset
, xfer
, regnum
);
5794 mips_xfer_register (gdbarch
, regcache
,
5795 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
5796 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
5798 return RETURN_VALUE_REGISTER_CONVENTION
;
5803 /* A scalar extract each part but least-significant-byte
5804 justified. o32 thinks registers are 4 byte, regardless of
5808 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5809 offset
< TYPE_LENGTH (type
);
5810 offset
+= MIPS32_REGSIZE
, regnum
++)
5812 int xfer
= MIPS32_REGSIZE
;
5813 if (offset
+ xfer
> TYPE_LENGTH (type
))
5814 xfer
= TYPE_LENGTH (type
) - offset
;
5816 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5817 offset
, xfer
, regnum
);
5818 mips_xfer_register (gdbarch
, regcache
,
5819 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
5820 gdbarch_byte_order (gdbarch
),
5821 readbuf
, writebuf
, offset
);
5823 return RETURN_VALUE_REGISTER_CONVENTION
;
5827 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
5831 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
5832 struct regcache
*regcache
, CORE_ADDR bp_addr
,
5834 struct value
**args
, CORE_ADDR sp
,
5835 int struct_return
, CORE_ADDR struct_addr
)
5841 int stack_offset
= 0;
5842 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5843 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
5845 /* For shared libraries, "t9" needs to point at the function
5847 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
5849 /* Set the return address register to point to the entry point of
5850 the program, where a breakpoint lies in wait. */
5851 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
5853 /* First ensure that the stack and structure return address (if any)
5854 are properly aligned. The stack has to be at least 64-bit
5855 aligned even on 32-bit machines, because doubles must be 64-bit
5856 aligned. For n32 and n64, stack frames need to be 128-bit
5857 aligned, so we round to this widest known alignment. */
5859 sp
= align_down (sp
, 16);
5860 struct_addr
= align_down (struct_addr
, 16);
5862 /* Now make space on the stack for the args. */
5863 for (argnum
= 0; argnum
< nargs
; argnum
++)
5865 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
5867 /* Allocate space on the stack. */
5868 len
+= align_up (TYPE_LENGTH (arg_type
), MIPS64_REGSIZE
);
5870 sp
-= align_up (len
, 16);
5873 fprintf_unfiltered (gdb_stdlog
,
5874 "mips_o64_push_dummy_call: sp=%s allocated %ld\n",
5875 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
5877 /* Initialize the integer and float register pointers. */
5878 argreg
= MIPS_A0_REGNUM
;
5879 float_argreg
= mips_fpa0_regnum (gdbarch
);
5881 /* The struct_return pointer occupies the first parameter-passing reg. */
5885 fprintf_unfiltered (gdb_stdlog
,
5886 "mips_o64_push_dummy_call: "
5887 "struct_return reg=%d %s\n",
5888 argreg
, paddress (gdbarch
, struct_addr
));
5889 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
5890 stack_offset
+= MIPS64_REGSIZE
;
5893 /* Now load as many as possible of the first arguments into
5894 registers, and push the rest onto the stack. Loop thru args
5895 from first to last. */
5896 for (argnum
= 0; argnum
< nargs
; argnum
++)
5898 const gdb_byte
*val
;
5899 struct value
*arg
= args
[argnum
];
5900 struct type
*arg_type
= check_typedef (value_type (arg
));
5901 int len
= TYPE_LENGTH (arg_type
);
5902 enum type_code typecode
= TYPE_CODE (arg_type
);
5905 fprintf_unfiltered (gdb_stdlog
,
5906 "mips_o64_push_dummy_call: %d len=%d type=%d",
5907 argnum
+ 1, len
, (int) typecode
);
5909 val
= value_contents (arg
);
5911 /* Floating point arguments passed in registers have to be
5912 treated specially. On 32-bit architectures, doubles are
5913 passed in register pairs; the even FP register gets the
5914 low word, and the odd FP register gets the high word.
5915 On O64, the first two floating point arguments are also
5916 copied to general registers, because MIPS16 functions
5917 don't use float registers for arguments. This duplication
5918 of arguments in general registers can't hurt non-MIPS16
5919 functions because those registers are normally skipped. */
5921 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5922 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
5924 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
5926 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5927 float_argreg
, phex (regval
, len
));
5928 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
5930 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5931 argreg
, phex (regval
, len
));
5932 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5934 /* Reserve space for the FP register. */
5935 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
5939 /* Copy the argument to general registers or the stack in
5940 register-sized pieces. Large arguments are split between
5941 registers and stack. */
5942 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
5943 are treated specially: Irix cc passes them in registers
5944 where gcc sometimes puts them on the stack. For maximum
5945 compatibility, we will put them in both places. */
5946 int odd_sized_struct
= (len
> MIPS64_REGSIZE
5947 && len
% MIPS64_REGSIZE
!= 0);
5950 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
5953 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
5956 /* Write this portion of the argument to the stack. */
5957 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
5958 || odd_sized_struct
)
5960 /* Should shorter than int integer values be
5961 promoted to int before being stored? */
5962 int longword_offset
= 0;
5964 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5966 if ((typecode
== TYPE_CODE_INT
5967 || typecode
== TYPE_CODE_PTR
5968 || typecode
== TYPE_CODE_FLT
)
5970 longword_offset
= MIPS64_REGSIZE
- len
;
5975 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
5976 paddress (gdbarch
, stack_offset
));
5977 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
5978 paddress (gdbarch
, longword_offset
));
5981 addr
= sp
+ stack_offset
+ longword_offset
;
5986 fprintf_unfiltered (gdb_stdlog
, " @%s ",
5987 paddress (gdbarch
, addr
));
5988 for (i
= 0; i
< partial_len
; i
++)
5990 fprintf_unfiltered (gdb_stdlog
, "%02x",
5994 write_memory (addr
, val
, partial_len
);
5997 /* Note!!! This is NOT an else clause. Odd sized
5998 structs may go thru BOTH paths. */
5999 /* Write this portion of the argument to a general
6000 purpose register. */
6001 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
6003 LONGEST regval
= extract_signed_integer (val
, partial_len
,
6005 /* Value may need to be sign extended, because
6006 mips_isa_regsize() != mips_abi_regsize(). */
6008 /* A non-floating-point argument being passed in a
6009 general register. If a struct or union, and if
6010 the remaining length is smaller than the register
6011 size, we have to adjust the register value on
6014 It does not seem to be necessary to do the
6015 same for integral types. */
6017 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
6018 && partial_len
< MIPS64_REGSIZE
6019 && (typecode
== TYPE_CODE_STRUCT
6020 || typecode
== TYPE_CODE_UNION
))
6021 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
6025 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
6027 phex (regval
, MIPS64_REGSIZE
));
6028 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
6031 /* Prevent subsequent floating point arguments from
6032 being passed in floating point registers. */
6033 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
6039 /* Compute the offset into the stack at which we will
6040 copy the next parameter.
6042 In older ABIs, the caller reserved space for
6043 registers that contained arguments. This was loosely
6044 refered to as their "home". Consequently, space is
6045 always allocated. */
6047 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
6051 fprintf_unfiltered (gdb_stdlog
, "\n");
6054 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
6056 /* Return adjusted stack pointer. */
6060 static enum return_value_convention
6061 mips_o64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
6062 struct type
*type
, struct regcache
*regcache
,
6063 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
6065 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
6066 int mips16
= mips_pc_is_mips16 (gdbarch
, func_addr
);
6067 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
6068 enum mips_fval_reg fval_reg
;
6070 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
6071 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
6072 || TYPE_CODE (type
) == TYPE_CODE_UNION
6073 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
6074 return RETURN_VALUE_STRUCT_CONVENTION
;
6075 else if (fp_register_arg_p (gdbarch
, TYPE_CODE (type
), type
))
6077 /* A floating-point value. If reading in or copying, then we get it
6078 from/put it to FP0 for standard MIPS code or GPR2 for MIPS16 code.
6079 If writing out only, then we put it to both FP0 and GPR2. We do
6080 not support reading in with no function known, if this safety
6081 check ever triggers, then we'll have to try harder. */
6082 gdb_assert (function
|| !readbuf
);
6087 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
6090 fprintf_unfiltered (gdb_stderr
, "Return float in $2\n");
6092 case mips_fval_both
:
6093 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0 and $2\n");
6096 if (fval_reg
!= mips_fval_gpr
)
6097 mips_xfer_register (gdbarch
, regcache
,
6098 (gdbarch_num_regs (gdbarch
)
6099 + mips_regnum (gdbarch
)->fp0
),
6101 gdbarch_byte_order (gdbarch
),
6102 readbuf
, writebuf
, 0);
6103 if (fval_reg
!= mips_fval_fpr
)
6104 mips_xfer_register (gdbarch
, regcache
,
6105 gdbarch_num_regs (gdbarch
) + 2,
6107 gdbarch_byte_order (gdbarch
),
6108 readbuf
, writebuf
, 0);
6109 return RETURN_VALUE_REGISTER_CONVENTION
;
6113 /* A scalar extract each part but least-significant-byte
6117 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
6118 offset
< TYPE_LENGTH (type
);
6119 offset
+= MIPS64_REGSIZE
, regnum
++)
6121 int xfer
= MIPS64_REGSIZE
;
6122 if (offset
+ xfer
> TYPE_LENGTH (type
))
6123 xfer
= TYPE_LENGTH (type
) - offset
;
6125 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
6126 offset
, xfer
, regnum
);
6127 mips_xfer_register (gdbarch
, regcache
,
6128 gdbarch_num_regs (gdbarch
) + regnum
,
6129 xfer
, gdbarch_byte_order (gdbarch
),
6130 readbuf
, writebuf
, offset
);
6132 return RETURN_VALUE_REGISTER_CONVENTION
;
6136 /* Floating point register management.
6138 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
6139 64bit operations, these early MIPS cpus treat fp register pairs
6140 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
6141 registers and offer a compatibility mode that emulates the MIPS2 fp
6142 model. When operating in MIPS2 fp compat mode, later cpu's split
6143 double precision floats into two 32-bit chunks and store them in
6144 consecutive fp regs. To display 64-bit floats stored in this
6145 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
6146 Throw in user-configurable endianness and you have a real mess.
6148 The way this works is:
6149 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
6150 double-precision value will be split across two logical registers.
6151 The lower-numbered logical register will hold the low-order bits,
6152 regardless of the processor's endianness.
6153 - If we are on a 64-bit processor, and we are looking for a
6154 single-precision value, it will be in the low ordered bits
6155 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
6156 save slot in memory.
6157 - If we are in 64-bit mode, everything is straightforward.
6159 Note that this code only deals with "live" registers at the top of the
6160 stack. We will attempt to deal with saved registers later, when
6161 the raw/cooked register interface is in place. (We need a general
6162 interface that can deal with dynamic saved register sizes -- fp
6163 regs could be 32 bits wide in one frame and 64 on the frame above
6166 /* Copy a 32-bit single-precision value from the current frame
6167 into rare_buffer. */
6170 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
6171 gdb_byte
*rare_buffer
)
6173 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6174 int raw_size
= register_size (gdbarch
, regno
);
6175 gdb_byte
*raw_buffer
= (gdb_byte
*) alloca (raw_size
);
6177 if (!deprecated_frame_register_read (frame
, regno
, raw_buffer
))
6178 error (_("can't read register %d (%s)"),
6179 regno
, gdbarch_register_name (gdbarch
, regno
));
6182 /* We have a 64-bit value for this register. Find the low-order
6186 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6191 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
6195 memcpy (rare_buffer
, raw_buffer
, 4);
6199 /* Copy a 64-bit double-precision value from the current frame into
6200 rare_buffer. This may include getting half of it from the next
6204 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
6205 gdb_byte
*rare_buffer
)
6207 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6208 int raw_size
= register_size (gdbarch
, regno
);
6210 if (raw_size
== 8 && !mips2_fp_compat (frame
))
6212 /* We have a 64-bit value for this register, and we should use
6214 if (!deprecated_frame_register_read (frame
, regno
, rare_buffer
))
6215 error (_("can't read register %d (%s)"),
6216 regno
, gdbarch_register_name (gdbarch
, regno
));
6220 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
6222 if ((rawnum
- mips_regnum (gdbarch
)->fp0
) & 1)
6223 internal_error (__FILE__
, __LINE__
,
6224 _("mips_read_fp_register_double: bad access to "
6225 "odd-numbered FP register"));
6227 /* mips_read_fp_register_single will find the correct 32 bits from
6229 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6231 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
6232 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
6236 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
6237 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
6243 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
6245 { /* Do values for FP (float) regs. */
6246 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6247 gdb_byte
*raw_buffer
;
6248 double doub
, flt1
; /* Doubles extracted from raw hex data. */
6253 alloca (2 * register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
)));
6255 fprintf_filtered (file
, "%s:", gdbarch_register_name (gdbarch
, regnum
));
6256 fprintf_filtered (file
, "%*s",
6257 4 - (int) strlen (gdbarch_register_name (gdbarch
, regnum
)),
6260 if (register_size (gdbarch
, regnum
) == 4 || mips2_fp_compat (frame
))
6262 struct value_print_options opts
;
6264 /* 4-byte registers: Print hex and floating. Also print even
6265 numbered registers as doubles. */
6266 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
6267 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
6270 get_formatted_print_options (&opts
, 'x');
6271 print_scalar_formatted (raw_buffer
,
6272 builtin_type (gdbarch
)->builtin_uint32
,
6275 fprintf_filtered (file
, " flt: ");
6277 fprintf_filtered (file
, " <invalid float> ");
6279 fprintf_filtered (file
, "%-17.9g", flt1
);
6281 if ((regnum
- gdbarch_num_regs (gdbarch
)) % 2 == 0)
6283 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
6284 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
6287 fprintf_filtered (file
, " dbl: ");
6289 fprintf_filtered (file
, "<invalid double>");
6291 fprintf_filtered (file
, "%-24.17g", doub
);
6296 struct value_print_options opts
;
6298 /* Eight byte registers: print each one as hex, float and double. */
6299 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
6300 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
6303 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
6304 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
6307 get_formatted_print_options (&opts
, 'x');
6308 print_scalar_formatted (raw_buffer
,
6309 builtin_type (gdbarch
)->builtin_uint64
,
6312 fprintf_filtered (file
, " flt: ");
6314 fprintf_filtered (file
, "<invalid float>");
6316 fprintf_filtered (file
, "%-17.9g", flt1
);
6318 fprintf_filtered (file
, " dbl: ");
6320 fprintf_filtered (file
, "<invalid double>");
6322 fprintf_filtered (file
, "%-24.17g", doub
);
6327 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
6330 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6331 struct value_print_options opts
;
6334 if (mips_float_register_p (gdbarch
, regnum
))
6336 mips_print_fp_register (file
, frame
, regnum
);
6340 val
= get_frame_register_value (frame
, regnum
);
6342 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
6344 /* The problem with printing numeric register names (r26, etc.) is that
6345 the user can't use them on input. Probably the best solution is to
6346 fix it so that either the numeric or the funky (a2, etc.) names
6347 are accepted on input. */
6348 if (regnum
< MIPS_NUMREGS
)
6349 fprintf_filtered (file
, "(r%d): ", regnum
);
6351 fprintf_filtered (file
, ": ");
6353 get_formatted_print_options (&opts
, 'x');
6354 val_print_scalar_formatted (value_type (val
),
6355 value_contents_for_printing (val
),
6356 value_embedded_offset (val
),
6361 /* Print IEEE exception condition bits in FLAGS. */
6364 print_fpu_flags (struct ui_file
*file
, int flags
)
6366 if (flags
& (1 << 0))
6367 fputs_filtered (" inexact", file
);
6368 if (flags
& (1 << 1))
6369 fputs_filtered (" uflow", file
);
6370 if (flags
& (1 << 2))
6371 fputs_filtered (" oflow", file
);
6372 if (flags
& (1 << 3))
6373 fputs_filtered (" div0", file
);
6374 if (flags
& (1 << 4))
6375 fputs_filtered (" inval", file
);
6376 if (flags
& (1 << 5))
6377 fputs_filtered (" unimp", file
);
6378 fputc_filtered ('\n', file
);
6381 /* Print interesting information about the floating point processor
6382 (if present) or emulator. */
6385 mips_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
6386 struct frame_info
*frame
, const char *args
)
6388 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
6389 enum mips_fpu_type type
= MIPS_FPU_TYPE (gdbarch
);
6393 if (fcsr
== -1 || !read_frame_register_unsigned (frame
, fcsr
, &fcs
))
6394 type
= MIPS_FPU_NONE
;
6396 fprintf_filtered (file
, "fpu type: %s\n",
6397 type
== MIPS_FPU_DOUBLE
? "double-precision"
6398 : type
== MIPS_FPU_SINGLE
? "single-precision"
6401 if (type
== MIPS_FPU_NONE
)
6404 fprintf_filtered (file
, "reg size: %d bits\n",
6405 register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) * 8);
6407 fputs_filtered ("cond :", file
);
6408 if (fcs
& (1 << 23))
6409 fputs_filtered (" 0", file
);
6410 for (i
= 1; i
<= 7; i
++)
6411 if (fcs
& (1 << (24 + i
)))
6412 fprintf_filtered (file
, " %d", i
);
6413 fputc_filtered ('\n', file
);
6415 fputs_filtered ("cause :", file
);
6416 print_fpu_flags (file
, (fcs
>> 12) & 0x3f);
6417 fputs ("mask :", stdout
);
6418 print_fpu_flags (file
, (fcs
>> 7) & 0x1f);
6419 fputs ("flags :", stdout
);
6420 print_fpu_flags (file
, (fcs
>> 2) & 0x1f);
6422 fputs_filtered ("rounding: ", file
);
6425 case 0: fputs_filtered ("nearest\n", file
); break;
6426 case 1: fputs_filtered ("zero\n", file
); break;
6427 case 2: fputs_filtered ("+inf\n", file
); break;
6428 case 3: fputs_filtered ("-inf\n", file
); break;
6431 fputs_filtered ("flush :", file
);
6432 if (fcs
& (1 << 21))
6433 fputs_filtered (" nearest", file
);
6434 if (fcs
& (1 << 22))
6435 fputs_filtered (" override", file
);
6436 if (fcs
& (1 << 24))
6437 fputs_filtered (" zero", file
);
6438 if ((fcs
& (0xb << 21)) == 0)
6439 fputs_filtered (" no", file
);
6440 fputc_filtered ('\n', file
);
6442 fprintf_filtered (file
, "nan2008 : %s\n", fcs
& (1 << 18) ? "yes" : "no");
6443 fprintf_filtered (file
, "abs2008 : %s\n", fcs
& (1 << 19) ? "yes" : "no");
6444 fputc_filtered ('\n', file
);
6446 default_print_float_info (gdbarch
, file
, frame
, args
);
6449 /* Replacement for generic do_registers_info.
6450 Print regs in pretty columns. */
6453 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
6456 fprintf_filtered (file
, " ");
6457 mips_print_fp_register (file
, frame
, regnum
);
6458 fprintf_filtered (file
, "\n");
6463 /* Print a row's worth of GP (int) registers, with name labels above. */
6466 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
6469 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6470 /* Do values for GP (int) regs. */
6471 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
6472 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols
6477 /* For GP registers, we print a separate row of names above the vals. */
6478 for (col
= 0, regnum
= start_regnum
;
6479 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
6480 + gdbarch_num_pseudo_regs (gdbarch
);
6483 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
6484 continue; /* unused register */
6485 if (mips_float_register_p (gdbarch
, regnum
))
6486 break; /* End the row: reached FP register. */
6487 /* Large registers are handled separately. */
6488 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
6491 break; /* End the row before this register. */
6493 /* Print this register on a row by itself. */
6494 mips_print_register (file
, frame
, regnum
);
6495 fprintf_filtered (file
, "\n");
6499 fprintf_filtered (file
, " ");
6500 fprintf_filtered (file
,
6501 mips_abi_regsize (gdbarch
) == 8 ? "%17s" : "%9s",
6502 gdbarch_register_name (gdbarch
, regnum
));
6509 /* Print the R0 to R31 names. */
6510 if ((start_regnum
% gdbarch_num_regs (gdbarch
)) < MIPS_NUMREGS
)
6511 fprintf_filtered (file
, "\n R%-4d",
6512 start_regnum
% gdbarch_num_regs (gdbarch
));
6514 fprintf_filtered (file
, "\n ");
6516 /* Now print the values in hex, 4 or 8 to the row. */
6517 for (col
= 0, regnum
= start_regnum
;
6518 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
6519 + gdbarch_num_pseudo_regs (gdbarch
);
6522 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
6523 continue; /* unused register */
6524 if (mips_float_register_p (gdbarch
, regnum
))
6525 break; /* End row: reached FP register. */
6526 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
6527 break; /* End row: large register. */
6529 /* OK: get the data in raw format. */
6530 if (!deprecated_frame_register_read (frame
, regnum
, raw_buffer
))
6531 error (_("can't read register %d (%s)"),
6532 regnum
, gdbarch_register_name (gdbarch
, regnum
));
6533 /* pad small registers */
6535 byte
< (mips_abi_regsize (gdbarch
)
6536 - register_size (gdbarch
, regnum
)); byte
++)
6537 printf_filtered (" ");
6538 /* Now print the register value in hex, endian order. */
6539 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6541 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
6542 byte
< register_size (gdbarch
, regnum
); byte
++)
6543 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
6545 for (byte
= register_size (gdbarch
, regnum
) - 1;
6547 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
6548 fprintf_filtered (file
, " ");
6551 if (col
> 0) /* ie. if we actually printed anything... */
6552 fprintf_filtered (file
, "\n");
6557 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */
6560 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
6561 struct frame_info
*frame
, int regnum
, int all
)
6563 if (regnum
!= -1) /* Do one specified register. */
6565 gdb_assert (regnum
>= gdbarch_num_regs (gdbarch
));
6566 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
6567 error (_("Not a valid register for the current processor type"));
6569 mips_print_register (file
, frame
, regnum
);
6570 fprintf_filtered (file
, "\n");
6573 /* Do all (or most) registers. */
6575 regnum
= gdbarch_num_regs (gdbarch
);
6576 while (regnum
< gdbarch_num_regs (gdbarch
)
6577 + gdbarch_num_pseudo_regs (gdbarch
))
6579 if (mips_float_register_p (gdbarch
, regnum
))
6581 if (all
) /* True for "INFO ALL-REGISTERS" command. */
6582 regnum
= print_fp_register_row (file
, frame
, regnum
);
6584 regnum
+= MIPS_NUMREGS
; /* Skip floating point regs. */
6587 regnum
= print_gp_register_row (file
, frame
, regnum
);
6593 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
6594 struct frame_info
*frame
)
6596 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
6597 CORE_ADDR pc
= get_frame_pc (frame
);
6598 struct address_space
*aspace
;
6604 if ((mips_pc_is_mips (pc
)
6605 && !mips32_insn_at_pc_has_delay_slot (gdbarch
, pc
))
6606 || (mips_pc_is_micromips (gdbarch
, pc
)
6607 && !micromips_insn_at_pc_has_delay_slot (gdbarch
, pc
, 0))
6608 || (mips_pc_is_mips16 (gdbarch
, pc
)
6609 && !mips16_insn_at_pc_has_delay_slot (gdbarch
, pc
, 0)))
6612 isa
= mips_pc_isa (gdbarch
, pc
);
6613 /* _has_delay_slot above will have validated the read. */
6614 insn
= mips_fetch_instruction (gdbarch
, isa
, pc
, NULL
);
6615 size
= mips_insn_size (isa
, insn
);
6616 aspace
= get_frame_address_space (frame
);
6617 return breakpoint_here_p (aspace
, pc
+ size
) != no_breakpoint_here
;
6620 /* To skip prologues, I use this predicate. Returns either PC itself
6621 if the code at PC does not look like a function prologue; otherwise
6622 returns an address that (if we're lucky) follows the prologue. If
6623 LENIENT, then we must skip everything which is involved in setting
6624 up the frame (it's OK to skip more, just so long as we don't skip
6625 anything which might clobber the registers which are being saved.
6626 We must skip more in the case where part of the prologue is in the
6627 delay slot of a non-prologue instruction). */
6630 mips_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6633 CORE_ADDR func_addr
;
6635 /* See if we can determine the end of the prologue via the symbol table.
6636 If so, then return either PC, or the PC after the prologue, whichever
6638 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
6640 CORE_ADDR post_prologue_pc
6641 = skip_prologue_using_sal (gdbarch
, func_addr
);
6642 if (post_prologue_pc
!= 0)
6643 return std::max (pc
, post_prologue_pc
);
6646 /* Can't determine prologue from the symbol table, need to examine
6649 /* Find an upper limit on the function prologue using the debug
6650 information. If the debug information could not be used to provide
6651 that bound, then use an arbitrary large number as the upper bound. */
6652 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
6654 limit_pc
= pc
+ 100; /* Magic. */
6656 if (mips_pc_is_mips16 (gdbarch
, pc
))
6657 return mips16_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6658 else if (mips_pc_is_micromips (gdbarch
, pc
))
6659 return micromips_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6661 return mips32_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6664 /* Implement the stack_frame_destroyed_p gdbarch method (32-bit version).
6665 This is a helper function for mips_stack_frame_destroyed_p. */
6668 mips32_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6670 CORE_ADDR func_addr
= 0, func_end
= 0;
6672 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6674 /* The MIPS epilogue is max. 12 bytes long. */
6675 CORE_ADDR addr
= func_end
- 12;
6677 if (addr
< func_addr
+ 4)
6678 addr
= func_addr
+ 4;
6682 for (; pc
< func_end
; pc
+= MIPS_INSN32_SIZE
)
6684 unsigned long high_word
;
6687 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
6688 high_word
= (inst
>> 16) & 0xffff;
6690 if (high_word
!= 0x27bd /* addiu $sp,$sp,offset */
6691 && high_word
!= 0x67bd /* daddiu $sp,$sp,offset */
6692 && inst
!= 0x03e00008 /* jr $ra */
6693 && inst
!= 0x00000000) /* nop */
6703 /* Implement the stack_frame_destroyed_p gdbarch method (microMIPS version).
6704 This is a helper function for mips_stack_frame_destroyed_p. */
6707 micromips_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6709 CORE_ADDR func_addr
= 0;
6710 CORE_ADDR func_end
= 0;
6718 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6721 /* The microMIPS epilogue is max. 12 bytes long. */
6722 addr
= func_end
- 12;
6724 if (addr
< func_addr
+ 2)
6725 addr
= func_addr
+ 2;
6729 for (; pc
< func_end
; pc
+= loc
)
6732 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
6733 loc
+= MIPS_INSN16_SIZE
;
6734 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
6736 /* 32-bit instructions. */
6737 case 2 * MIPS_INSN16_SIZE
:
6739 insn
|= mips_fetch_instruction (gdbarch
,
6740 ISA_MICROMIPS
, pc
+ loc
, NULL
);
6741 loc
+= MIPS_INSN16_SIZE
;
6742 switch (micromips_op (insn
>> 16))
6744 case 0xc: /* ADDIU: bits 001100 */
6745 case 0x17: /* DADDIU: bits 010111 */
6746 sreg
= b0s5_reg (insn
>> 16);
6747 dreg
= b5s5_reg (insn
>> 16);
6748 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
6749 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
6750 /* (D)ADDIU $sp, imm */
6760 /* 16-bit instructions. */
6761 case MIPS_INSN16_SIZE
:
6762 switch (micromips_op (insn
))
6764 case 0x3: /* MOVE: bits 000011 */
6765 sreg
= b0s5_reg (insn
);
6766 dreg
= b5s5_reg (insn
);
6767 if (sreg
== 0 && dreg
== 0)
6768 /* MOVE $zero, $zero aka NOP */
6772 case 0x11: /* POOL16C: bits 010001 */
6773 if (b5s5_op (insn
) == 0x18
6774 /* JRADDIUSP: bits 010011 11000 */
6775 || (b5s5_op (insn
) == 0xd
6776 /* JRC: bits 010011 01101 */
6777 && b0s5_reg (insn
) == MIPS_RA_REGNUM
))
6782 case 0x13: /* POOL16D: bits 010011 */
6783 offset
= micromips_decode_imm9 (b1s9_imm (insn
));
6784 if ((insn
& 0x1) == 0x1
6785 /* ADDIUSP: bits 010011 1 */
6799 /* Implement the stack_frame_destroyed_p gdbarch method (16-bit version).
6800 This is a helper function for mips_stack_frame_destroyed_p. */
6803 mips16_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6805 CORE_ADDR func_addr
= 0, func_end
= 0;
6807 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6809 /* The MIPS epilogue is max. 12 bytes long. */
6810 CORE_ADDR addr
= func_end
- 12;
6812 if (addr
< func_addr
+ 4)
6813 addr
= func_addr
+ 4;
6817 for (; pc
< func_end
; pc
+= MIPS_INSN16_SIZE
)
6819 unsigned short inst
;
6821 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, pc
, NULL
);
6823 if ((inst
& 0xf800) == 0xf000) /* extend */
6826 if (inst
!= 0x6300 /* addiu $sp,offset */
6827 && inst
!= 0xfb00 /* daddiu $sp,$sp,offset */
6828 && inst
!= 0xe820 /* jr $ra */
6829 && inst
!= 0xe8a0 /* jrc $ra */
6830 && inst
!= 0x6500) /* nop */
6840 /* Implement the stack_frame_destroyed_p gdbarch method.
6842 The epilogue is defined here as the area at the end of a function,
6843 after an instruction which destroys the function's stack frame. */
6846 mips_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6848 if (mips_pc_is_mips16 (gdbarch
, pc
))
6849 return mips16_stack_frame_destroyed_p (gdbarch
, pc
);
6850 else if (mips_pc_is_micromips (gdbarch
, pc
))
6851 return micromips_stack_frame_destroyed_p (gdbarch
, pc
);
6853 return mips32_stack_frame_destroyed_p (gdbarch
, pc
);
6856 /* Root of all "set mips "/"show mips " commands. This will eventually be
6857 used for all MIPS-specific commands. */
6860 show_mips_command (char *args
, int from_tty
)
6862 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
6866 set_mips_command (char *args
, int from_tty
)
6869 ("\"set mips\" must be followed by an appropriate subcommand.\n");
6870 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
6873 /* Commands to show/set the MIPS FPU type. */
6876 show_mipsfpu_command (char *args
, int from_tty
)
6880 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_mips
)
6883 ("The MIPS floating-point coprocessor is unknown "
6884 "because the current architecture is not MIPS.\n");
6888 switch (MIPS_FPU_TYPE (target_gdbarch ()))
6890 case MIPS_FPU_SINGLE
:
6891 fpu
= "single-precision";
6893 case MIPS_FPU_DOUBLE
:
6894 fpu
= "double-precision";
6897 fpu
= "absent (none)";
6900 internal_error (__FILE__
, __LINE__
, _("bad switch"));
6902 if (mips_fpu_type_auto
)
6903 printf_unfiltered ("The MIPS floating-point coprocessor "
6904 "is set automatically (currently %s)\n",
6908 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
6913 set_mipsfpu_command (char *args
, int from_tty
)
6915 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", "
6916 "\"single\",\"none\" or \"auto\".\n");
6917 show_mipsfpu_command (args
, from_tty
);
6921 set_mipsfpu_single_command (char *args
, int from_tty
)
6923 struct gdbarch_info info
;
6924 gdbarch_info_init (&info
);
6925 mips_fpu_type
= MIPS_FPU_SINGLE
;
6926 mips_fpu_type_auto
= 0;
6927 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6928 instead of relying on globals. Doing that would let generic code
6929 handle the search for this specific architecture. */
6930 if (!gdbarch_update_p (info
))
6931 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6935 set_mipsfpu_double_command (char *args
, int from_tty
)
6937 struct gdbarch_info info
;
6938 gdbarch_info_init (&info
);
6939 mips_fpu_type
= MIPS_FPU_DOUBLE
;
6940 mips_fpu_type_auto
= 0;
6941 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6942 instead of relying on globals. Doing that would let generic code
6943 handle the search for this specific architecture. */
6944 if (!gdbarch_update_p (info
))
6945 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6949 set_mipsfpu_none_command (char *args
, int from_tty
)
6951 struct gdbarch_info info
;
6952 gdbarch_info_init (&info
);
6953 mips_fpu_type
= MIPS_FPU_NONE
;
6954 mips_fpu_type_auto
= 0;
6955 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6956 instead of relying on globals. Doing that would let generic code
6957 handle the search for this specific architecture. */
6958 if (!gdbarch_update_p (info
))
6959 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6963 set_mipsfpu_auto_command (char *args
, int from_tty
)
6965 mips_fpu_type_auto
= 1;
6968 /* Just like reinit_frame_cache, but with the right arguments to be
6969 callable as an sfunc. */
6972 reinit_frame_cache_sfunc (char *args
, int from_tty
,
6973 struct cmd_list_element
*c
)
6975 reinit_frame_cache ();
6979 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
6981 struct gdbarch
*gdbarch
= (struct gdbarch
*) info
->application_data
;
6983 /* FIXME: cagney/2003-06-26: Is this even necessary? The
6984 disassembler needs to be able to locally determine the ISA, and
6985 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
6987 if (mips_pc_is_mips16 (gdbarch
, memaddr
))
6988 info
->mach
= bfd_mach_mips16
;
6989 else if (mips_pc_is_micromips (gdbarch
, memaddr
))
6990 info
->mach
= bfd_mach_mips_micromips
;
6992 /* Round down the instruction address to the appropriate boundary. */
6993 memaddr
&= (info
->mach
== bfd_mach_mips16
6994 || info
->mach
== bfd_mach_mips_micromips
) ? ~1 : ~3;
6996 /* Set the disassembler options. */
6997 if (!info
->disassembler_options
)
6998 /* This string is not recognized explicitly by the disassembler,
6999 but it tells the disassembler to not try to guess the ABI from
7000 the bfd elf headers, such that, if the user overrides the ABI
7001 of a program linked as NewABI, the disassembly will follow the
7002 register naming conventions specified by the user. */
7003 info
->disassembler_options
= "gpr-names=32";
7005 /* Call the appropriate disassembler based on the target endian-ness. */
7006 if (info
->endian
== BFD_ENDIAN_BIG
)
7007 return print_insn_big_mips (memaddr
, info
);
7009 return print_insn_little_mips (memaddr
, info
);
7013 gdb_print_insn_mips_n32 (bfd_vma memaddr
, struct disassemble_info
*info
)
7015 /* Set up the disassembler info, so that we get the right
7016 register names from libopcodes. */
7017 info
->disassembler_options
= "gpr-names=n32";
7018 info
->flavour
= bfd_target_elf_flavour
;
7020 return gdb_print_insn_mips (memaddr
, info
);
7024 gdb_print_insn_mips_n64 (bfd_vma memaddr
, struct disassemble_info
*info
)
7026 /* Set up the disassembler info, so that we get the right
7027 register names from libopcodes. */
7028 info
->disassembler_options
= "gpr-names=64";
7029 info
->flavour
= bfd_target_elf_flavour
;
7031 return gdb_print_insn_mips (memaddr
, info
);
7034 /* This function implements gdbarch_breakpoint_from_pc. It uses the
7035 program counter value to determine whether a 16- or 32-bit breakpoint
7036 should be used. It returns a pointer to a string of bytes that encode a
7037 breakpoint instruction, stores the length of the string to *lenptr, and
7038 adjusts pc (if necessary) to point to the actual memory location where
7039 the breakpoint should be inserted. */
7041 static const gdb_byte
*
7042 mips_breakpoint_from_pc (struct gdbarch
*gdbarch
,
7043 CORE_ADDR
*pcptr
, int *lenptr
)
7045 CORE_ADDR pc
= *pcptr
;
7047 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
7049 if (mips_pc_is_mips16 (gdbarch
, pc
))
7051 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
7052 *pcptr
= unmake_compact_addr (pc
);
7053 *lenptr
= sizeof (mips16_big_breakpoint
);
7054 return mips16_big_breakpoint
;
7056 else if (mips_pc_is_micromips (gdbarch
, pc
))
7058 static gdb_byte micromips16_big_breakpoint
[] = { 0x46, 0x85 };
7059 static gdb_byte micromips32_big_breakpoint
[] = { 0, 0x5, 0, 0x7 };
7064 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, &err
);
7065 size
= err
? 2 : mips_insn_size (ISA_MICROMIPS
, insn
);
7066 *pcptr
= unmake_compact_addr (pc
);
7068 return (size
== 2) ? micromips16_big_breakpoint
7069 : micromips32_big_breakpoint
;
7073 /* The IDT board uses an unusual breakpoint value, and
7074 sometimes gets confused when it sees the usual MIPS
7075 breakpoint instruction. */
7076 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
7077 static gdb_byte pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
7078 static gdb_byte idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
7080 *lenptr
= sizeof (big_breakpoint
);
7082 if (strcmp (target_shortname
, "mips") == 0)
7083 return idt_big_breakpoint
;
7084 else if (strcmp (target_shortname
, "ddb") == 0
7085 || strcmp (target_shortname
, "pmon") == 0
7086 || strcmp (target_shortname
, "lsi") == 0)
7087 return pmon_big_breakpoint
;
7089 return big_breakpoint
;
7094 if (mips_pc_is_mips16 (gdbarch
, pc
))
7096 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
7097 *pcptr
= unmake_compact_addr (pc
);
7098 *lenptr
= sizeof (mips16_little_breakpoint
);
7099 return mips16_little_breakpoint
;
7101 else if (mips_pc_is_micromips (gdbarch
, pc
))
7103 static gdb_byte micromips16_little_breakpoint
[] = { 0x85, 0x46 };
7104 static gdb_byte micromips32_little_breakpoint
[] = { 0x5, 0, 0x7, 0 };
7109 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, &err
);
7110 size
= err
? 2 : mips_insn_size (ISA_MICROMIPS
, insn
);
7111 *pcptr
= unmake_compact_addr (pc
);
7113 return (size
== 2) ? micromips16_little_breakpoint
7114 : micromips32_little_breakpoint
;
7118 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
7119 static gdb_byte pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
7120 static gdb_byte idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
7122 *lenptr
= sizeof (little_breakpoint
);
7124 if (strcmp (target_shortname
, "mips") == 0)
7125 return idt_little_breakpoint
;
7126 else if (strcmp (target_shortname
, "ddb") == 0
7127 || strcmp (target_shortname
, "pmon") == 0
7128 || strcmp (target_shortname
, "lsi") == 0)
7129 return pmon_little_breakpoint
;
7131 return little_breakpoint
;
7136 /* Determine the remote breakpoint kind suitable for the PC. The following
7139 * 2 -- 16-bit MIPS16 mode breakpoint,
7141 * 3 -- 16-bit microMIPS mode breakpoint,
7143 * 4 -- 32-bit standard MIPS mode breakpoint,
7145 * 5 -- 32-bit microMIPS mode breakpoint. */
7148 mips_remote_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
,
7151 CORE_ADDR pc
= *pcptr
;
7153 if (mips_pc_is_mips16 (gdbarch
, pc
))
7155 *pcptr
= unmake_compact_addr (pc
);
7158 else if (mips_pc_is_micromips (gdbarch
, pc
))
7164 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, &status
);
7165 size
= status
? 2 : mips_insn_size (ISA_MICROMIPS
, insn
) == 2 ? 2 : 4;
7166 *pcptr
= unmake_compact_addr (pc
);
7167 *kindptr
= size
| 1;
7173 /* Return non-zero if the standard MIPS instruction INST has a branch
7174 delay slot (i.e. it is a jump or branch instruction). This function
7175 is based on mips32_next_pc. */
7178 mips32_instruction_has_delay_slot (struct gdbarch
*gdbarch
, ULONGEST inst
)
7184 op
= itype_op (inst
);
7185 if ((inst
& 0xe0000000) != 0)
7187 rs
= itype_rs (inst
);
7188 rt
= itype_rt (inst
);
7189 return (is_octeon_bbit_op (op
, gdbarch
)
7190 || op
>> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
7191 || op
== 29 /* JALX: bits 011101 */
7194 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
7195 || (rs
== 9 && (rt
& 0x2) == 0)
7196 /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */
7197 || (rs
== 10 && (rt
& 0x2) == 0))));
7198 /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */
7201 switch (op
& 0x07) /* extract bits 28,27,26 */
7203 case 0: /* SPECIAL */
7204 op
= rtype_funct (inst
);
7205 return (op
== 8 /* JR */
7206 || op
== 9); /* JALR */
7207 break; /* end SPECIAL */
7208 case 1: /* REGIMM */
7209 rs
= itype_rs (inst
);
7210 rt
= itype_rt (inst
); /* branch condition */
7211 return ((rt
& 0xc) == 0
7212 /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */
7213 /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */
7214 || ((rt
& 0x1e) == 0x1c && rs
== 0));
7215 /* BPOSGE32, BPOSGE64: bits 1110x */
7216 break; /* end REGIMM */
7217 default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */
7223 /* Return non-zero if a standard MIPS instruction at ADDR has a branch
7224 delay slot (i.e. it is a jump or branch instruction). */
7227 mips32_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
7232 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, addr
, &status
);
7236 return mips32_instruction_has_delay_slot (gdbarch
, insn
);
7239 /* Return non-zero if the microMIPS instruction INSN, comprising the
7240 16-bit major opcode word in the high 16 bits and any second word
7241 in the low 16 bits, has a branch delay slot (i.e. it is a non-compact
7242 jump or branch instruction). The instruction must be 32-bit if
7243 MUSTBE32 is set or can be any instruction otherwise. */
7246 micromips_instruction_has_delay_slot (ULONGEST insn
, int mustbe32
)
7248 ULONGEST major
= insn
>> 16;
7250 switch (micromips_op (major
))
7252 /* 16-bit instructions. */
7253 case 0x33: /* B16: bits 110011 */
7254 case 0x2b: /* BNEZ16: bits 101011 */
7255 case 0x23: /* BEQZ16: bits 100011 */
7257 case 0x11: /* POOL16C: bits 010001 */
7259 && ((b5s5_op (major
) == 0xc
7260 /* JR16: bits 010001 01100 */
7261 || (b5s5_op (major
) & 0x1e) == 0xe)));
7262 /* JALR16, JALRS16: bits 010001 0111x */
7263 /* 32-bit instructions. */
7264 case 0x3d: /* JAL: bits 111101 */
7265 case 0x3c: /* JALX: bits 111100 */
7266 case 0x35: /* J: bits 110101 */
7267 case 0x2d: /* BNE: bits 101101 */
7268 case 0x25: /* BEQ: bits 100101 */
7269 case 0x1d: /* JALS: bits 011101 */
7271 case 0x10: /* POOL32I: bits 010000 */
7272 return ((b5s5_op (major
) & 0x1c) == 0x0
7273 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
7274 || (b5s5_op (major
) & 0x1d) == 0x4
7275 /* BLEZ, BGTZ: bits 010000 001x0 */
7276 || (b5s5_op (major
) & 0x1d) == 0x11
7277 /* BLTZALS, BGEZALS: bits 010000 100x1 */
7278 || ((b5s5_op (major
) & 0x1e) == 0x14
7279 && (major
& 0x3) == 0x0)
7280 /* BC2F, BC2T: bits 010000 1010x xxx00 */
7281 || (b5s5_op (major
) & 0x1e) == 0x1a
7282 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
7283 || ((b5s5_op (major
) & 0x1e) == 0x1c
7284 && (major
& 0x3) == 0x0)
7285 /* BC1F, BC1T: bits 010000 1110x xxx00 */
7286 || ((b5s5_op (major
) & 0x1c) == 0x1c
7287 && (major
& 0x3) == 0x1));
7288 /* BC1ANY*: bits 010000 111xx xxx01 */
7289 case 0x0: /* POOL32A: bits 000000 */
7290 return (b0s6_op (insn
) == 0x3c
7291 /* POOL32Axf: bits 000000 ... 111100 */
7292 && (b6s10_ext (insn
) & 0x2bf) == 0x3c);
7293 /* JALR, JALR.HB: 000000 000x111100 111100 */
7294 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
7300 /* Return non-zero if a microMIPS instruction at ADDR has a branch delay
7301 slot (i.e. it is a non-compact jump instruction). The instruction
7302 must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */
7305 micromips_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
7306 CORE_ADDR addr
, int mustbe32
)
7312 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, addr
, &status
);
7315 size
= mips_insn_size (ISA_MICROMIPS
, insn
);
7317 if (size
== 2 * MIPS_INSN16_SIZE
)
7319 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, addr
, &status
);
7324 return micromips_instruction_has_delay_slot (insn
, mustbe32
);
7327 /* Return non-zero if the MIPS16 instruction INST, which must be
7328 a 32-bit instruction if MUSTBE32 is set or can be any instruction
7329 otherwise, has a branch delay slot (i.e. it is a non-compact jump
7330 instruction). This function is based on mips16_next_pc. */
7333 mips16_instruction_has_delay_slot (unsigned short inst
, int mustbe32
)
7335 if ((inst
& 0xf89f) == 0xe800) /* JR/JALR (16-bit instruction) */
7337 return (inst
& 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */
7340 /* Return non-zero if a MIPS16 instruction at ADDR has a branch delay
7341 slot (i.e. it is a non-compact jump instruction). The instruction
7342 must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */
7345 mips16_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
7346 CORE_ADDR addr
, int mustbe32
)
7348 unsigned short insn
;
7351 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, addr
, &status
);
7355 return mips16_instruction_has_delay_slot (insn
, mustbe32
);
7358 /* Calculate the starting address of the MIPS memory segment BPADDR is in.
7359 This assumes KSSEG exists. */
7362 mips_segment_boundary (CORE_ADDR bpaddr
)
7364 CORE_ADDR mask
= CORE_ADDR_MAX
;
7367 if (sizeof (CORE_ADDR
) == 8)
7368 /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid
7369 a compiler warning produced where CORE_ADDR is a 32-bit type even
7370 though in that case this is dead code). */
7371 switch (bpaddr
>> ((sizeof (CORE_ADDR
) << 3) - 2) & 3)
7374 if (bpaddr
== (bfd_signed_vma
) (int32_t) bpaddr
)
7375 segsize
= 29; /* 32-bit compatibility segment */
7377 segsize
= 62; /* xkseg */
7379 case 2: /* xkphys */
7382 default: /* xksseg (1), xkuseg/kuseg (0) */
7386 else if (bpaddr
& 0x80000000) /* kernel segment */
7389 segsize
= 31; /* user segment */
7391 return bpaddr
& mask
;
7394 /* Move the breakpoint at BPADDR out of any branch delay slot by shifting
7395 it backwards if necessary. Return the address of the new location. */
7398 mips_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
7400 CORE_ADDR prev_addr
;
7402 CORE_ADDR func_addr
;
7404 /* If a breakpoint is set on the instruction in a branch delay slot,
7405 GDB gets confused. When the breakpoint is hit, the PC isn't on
7406 the instruction in the branch delay slot, the PC will point to
7407 the branch instruction. Since the PC doesn't match any known
7408 breakpoints, GDB reports a trap exception.
7410 There are two possible fixes for this problem.
7412 1) When the breakpoint gets hit, see if the BD bit is set in the
7413 Cause register (which indicates the last exception occurred in a
7414 branch delay slot). If the BD bit is set, fix the PC to point to
7415 the instruction in the branch delay slot.
7417 2) When the user sets the breakpoint, don't allow him to set the
7418 breakpoint on the instruction in the branch delay slot. Instead
7419 move the breakpoint to the branch instruction (which will have
7422 The problem with the first solution is that if the user then
7423 single-steps the processor, the branch instruction will get
7424 skipped (since GDB thinks the PC is on the instruction in the
7427 So, we'll use the second solution. To do this we need to know if
7428 the instruction we're trying to set the breakpoint on is in the
7429 branch delay slot. */
7431 boundary
= mips_segment_boundary (bpaddr
);
7433 /* Make sure we don't scan back before the beginning of the current
7434 function, since we may fetch constant data or insns that look like
7435 a jump. Of course we might do that anyway if the compiler has
7436 moved constants inline. :-( */
7437 if (find_pc_partial_function (bpaddr
, NULL
, &func_addr
, NULL
)
7438 && func_addr
> boundary
&& func_addr
<= bpaddr
)
7439 boundary
= func_addr
;
7441 if (mips_pc_is_mips (bpaddr
))
7443 if (bpaddr
== boundary
)
7446 /* If the previous instruction has a branch delay slot, we have
7447 to move the breakpoint to the branch instruction. */
7448 prev_addr
= bpaddr
- 4;
7449 if (mips32_insn_at_pc_has_delay_slot (gdbarch
, prev_addr
))
7454 int (*insn_at_pc_has_delay_slot
) (struct gdbarch
*, CORE_ADDR
, int);
7455 CORE_ADDR addr
, jmpaddr
;
7458 boundary
= unmake_compact_addr (boundary
);
7460 /* The only MIPS16 instructions with delay slots are JAL, JALX,
7461 JALR and JR. An absolute JAL/JALX is always 4 bytes long,
7462 so try for that first, then try the 2 byte JALR/JR.
7463 The microMIPS ASE has a whole range of jumps and branches
7464 with delay slots, some of which take 4 bytes and some take
7465 2 bytes, so the idea is the same.
7466 FIXME: We have to assume that bpaddr is not the second half
7467 of an extended instruction. */
7468 insn_at_pc_has_delay_slot
= (mips_pc_is_micromips (gdbarch
, bpaddr
)
7469 ? micromips_insn_at_pc_has_delay_slot
7470 : mips16_insn_at_pc_has_delay_slot
);
7474 for (i
= 1; i
< 4; i
++)
7476 if (unmake_compact_addr (addr
) == boundary
)
7478 addr
-= MIPS_INSN16_SIZE
;
7479 if (i
== 1 && insn_at_pc_has_delay_slot (gdbarch
, addr
, 0))
7480 /* Looks like a JR/JALR at [target-1], but it could be
7481 the second word of a previous JAL/JALX, so record it
7482 and check back one more. */
7484 else if (i
> 1 && insn_at_pc_has_delay_slot (gdbarch
, addr
, 1))
7487 /* Looks like a JAL/JALX at [target-2], but it could also
7488 be the second word of a previous JAL/JALX, record it,
7489 and check back one more. */
7492 /* Looks like a JAL/JALX at [target-3], so any previously
7493 recorded JAL/JALX or JR/JALR must be wrong, because:
7496 -2: JAL-ext (can't be JAL/JALX)
7497 -1: bdslot (can't be JR/JALR)
7500 Of course it could be another JAL-ext which looks
7501 like a JAL, but in that case we'd have broken out
7502 of this loop at [target-2]:
7506 -2: bdslot (can't be jmp)
7513 /* Not a jump instruction: if we're at [target-1] this
7514 could be the second word of a JAL/JALX, so continue;
7515 otherwise we're done. */
7528 /* Return non-zero if SUFFIX is one of the numeric suffixes used for MIPS16
7529 call stubs, one of 1, 2, 5, 6, 9, 10, or, if ZERO is non-zero, also 0. */
7532 mips_is_stub_suffix (const char *suffix
, int zero
)
7537 return zero
&& suffix
[1] == '\0';
7539 return suffix
[1] == '\0' || (suffix
[1] == '0' && suffix
[2] == '\0');
7544 return suffix
[1] == '\0';
7550 /* Return non-zero if MODE is one of the mode infixes used for MIPS16
7551 call stubs, one of sf, df, sc, or dc. */
7554 mips_is_stub_mode (const char *mode
)
7556 return ((mode
[0] == 's' || mode
[0] == 'd')
7557 && (mode
[1] == 'f' || mode
[1] == 'c'));
7560 /* Code at PC is a compiler-generated stub. Such a stub for a function
7561 bar might have a name like __fn_stub_bar, and might look like this:
7568 followed by (or interspersed with):
7575 addiu $25, $25, %lo(bar)
7578 ($1 may be used in old code; for robustness we accept any register)
7581 lui $28, %hi(_gp_disp)
7582 addiu $28, $28, %lo(_gp_disp)
7585 addiu $25, $25, %lo(bar)
7588 In the case of a __call_stub_bar stub, the sequence to set up
7589 arguments might look like this:
7596 followed by (or interspersed with) one of the jump sequences above.
7598 In the case of a __call_stub_fp_bar stub, JAL or JALR is used instead
7599 of J or JR, respectively, followed by:
7605 We are at the beginning of the stub here, and scan down and extract
7606 the target address from the jump immediate instruction or, if a jump
7607 register instruction is used, from the register referred. Return
7608 the value of PC calculated or 0 if inconclusive.
7610 The limit on the search is arbitrarily set to 20 instructions. FIXME. */
7613 mips_get_mips16_fn_stub_pc (struct frame_info
*frame
, CORE_ADDR pc
)
7615 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7616 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7617 int addrreg
= MIPS_ZERO_REGNUM
;
7618 CORE_ADDR start_pc
= pc
;
7619 CORE_ADDR target_pc
= 0;
7626 status
== 0 && target_pc
== 0 && i
< 20;
7627 i
++, pc
+= MIPS_INSN32_SIZE
)
7629 ULONGEST inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
7635 switch (itype_op (inst
))
7637 case 0: /* SPECIAL */
7638 switch (rtype_funct (inst
))
7642 rs
= rtype_rs (inst
);
7643 if (rs
== MIPS_GP_REGNUM
)
7644 target_pc
= gp
; /* Hmm... */
7645 else if (rs
== addrreg
)
7649 case 0x21: /* ADDU */
7650 rt
= rtype_rt (inst
);
7651 rs
= rtype_rs (inst
);
7652 rd
= rtype_rd (inst
);
7653 if (rd
== MIPS_GP_REGNUM
7654 && ((rs
== MIPS_GP_REGNUM
&& rt
== MIPS_T9_REGNUM
)
7655 || (rs
== MIPS_T9_REGNUM
&& rt
== MIPS_GP_REGNUM
)))
7663 target_pc
= jtype_target (inst
) << 2;
7664 target_pc
+= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
7668 rt
= itype_rt (inst
);
7669 rs
= itype_rs (inst
);
7672 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
7673 if (rt
== MIPS_GP_REGNUM
)
7675 else if (rt
== addrreg
)
7681 rt
= itype_rt (inst
);
7682 imm
= ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 16;
7683 if (rt
== MIPS_GP_REGNUM
)
7685 else if (rt
!= MIPS_ZERO_REGNUM
)
7693 rt
= itype_rt (inst
);
7694 rs
= itype_rs (inst
);
7695 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
7696 if (gp
!= 0 && rs
== MIPS_GP_REGNUM
)
7700 memset (buf
, 0, sizeof (buf
));
7701 status
= target_read_memory (gp
+ imm
, buf
, sizeof (buf
));
7703 addr
= extract_signed_integer (buf
, sizeof (buf
), byte_order
);
7712 /* If PC is in a MIPS16 call or return stub, return the address of the
7713 target PC, which is either the callee or the caller. There are several
7714 cases which must be handled:
7716 * If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7717 and the target PC is in $31 ($ra).
7718 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7719 and the target PC is in $2.
7720 * If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7721 i.e. before the JALR instruction, this is effectively a call stub
7722 and the target PC is in $2. Otherwise this is effectively
7723 a return stub and the target PC is in $18.
7724 * If the PC is at the start of __call_stub_fp_*, i.e. before the
7725 JAL or JALR instruction, this is effectively a call stub and the
7726 target PC is buried in the instruction stream. Otherwise this
7727 is effectively a return stub and the target PC is in $18.
7728 * If the PC is in __call_stub_* or in __fn_stub_*, this is a call
7729 stub and the target PC is buried in the instruction stream.
7731 See the source code for the stubs in gcc/config/mips/mips16.S, or the
7732 stub builder in gcc/config/mips/mips.c (mips16_build_call_stub) for the
7736 mips_skip_mips16_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7738 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7739 CORE_ADDR start_addr
;
7743 /* Find the starting address and name of the function containing the PC. */
7744 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
7747 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7748 and the target PC is in $31 ($ra). */
7749 prefixlen
= strlen (mips_str_mips16_ret_stub
);
7750 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
7751 && mips_is_stub_mode (name
+ prefixlen
)
7752 && name
[prefixlen
+ 2] == '\0')
7753 return get_frame_register_signed
7754 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
7756 /* If the PC is in __mips16_call_stub_*, this is one of the call
7757 call/return stubs. */
7758 prefixlen
= strlen (mips_str_mips16_call_stub
);
7759 if (strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0)
7761 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7762 and the target PC is in $2. */
7763 if (mips_is_stub_suffix (name
+ prefixlen
, 0))
7764 return get_frame_register_signed
7765 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
7767 /* If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7768 i.e. before the JALR instruction, this is effectively a call stub
7769 and the target PC is in $2. Otherwise this is effectively
7770 a return stub and the target PC is in $18. */
7771 else if (mips_is_stub_mode (name
+ prefixlen
)
7772 && name
[prefixlen
+ 2] == '_'
7773 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 0))
7775 if (pc
== start_addr
)
7776 /* This is the 'call' part of a call stub. The return
7777 address is in $2. */
7778 return get_frame_register_signed
7779 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
7781 /* This is the 'return' part of a call stub. The return
7782 address is in $18. */
7783 return get_frame_register_signed
7784 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
7787 return 0; /* Not a stub. */
7790 /* If the PC is in __call_stub_* or __fn_stub*, this is one of the
7791 compiler-generated call or call/return stubs. */
7792 if (startswith (name
, mips_str_fn_stub
)
7793 || startswith (name
, mips_str_call_stub
))
7795 if (pc
== start_addr
)
7796 /* This is the 'call' part of a call stub. Call this helper
7797 to scan through this code for interesting instructions
7798 and determine the final PC. */
7799 return mips_get_mips16_fn_stub_pc (frame
, pc
);
7801 /* This is the 'return' part of a call stub. The return address
7803 return get_frame_register_signed
7804 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
7807 return 0; /* Not a stub. */
7810 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
7811 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
7814 mips_in_return_stub (struct gdbarch
*gdbarch
, CORE_ADDR pc
, const char *name
)
7816 CORE_ADDR start_addr
;
7819 /* Find the starting address of the function containing the PC. */
7820 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
7823 /* If the PC is in __mips16_call_stub_{s,d}{f,c}_{0..10} but not at
7824 the start, i.e. after the JALR instruction, this is effectively
7826 prefixlen
= strlen (mips_str_mips16_call_stub
);
7827 if (pc
!= start_addr
7828 && strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0
7829 && mips_is_stub_mode (name
+ prefixlen
)
7830 && name
[prefixlen
+ 2] == '_'
7831 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 1))
7834 /* If the PC is in __call_stub_fp_* but not at the start, i.e. after
7835 the JAL or JALR instruction, this is effectively a return stub. */
7836 prefixlen
= strlen (mips_str_call_fp_stub
);
7837 if (pc
!= start_addr
7838 && strncmp (name
, mips_str_call_fp_stub
, prefixlen
) == 0)
7841 /* Consume the .pic. prefix of any PIC stub, this function must return
7842 true when the PC is in a PIC stub of a __mips16_ret_{d,s}{f,c} stub
7843 or the call stub path will trigger in handle_inferior_event causing
7845 prefixlen
= strlen (mips_str_pic
);
7846 if (strncmp (name
, mips_str_pic
, prefixlen
) == 0)
7849 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub. */
7850 prefixlen
= strlen (mips_str_mips16_ret_stub
);
7851 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
7852 && mips_is_stub_mode (name
+ prefixlen
)
7853 && name
[prefixlen
+ 2] == '\0')
7856 return 0; /* Not a stub. */
7859 /* If the current PC is the start of a non-PIC-to-PIC stub, return the
7860 PC of the stub target. The stub just loads $t9 and jumps to it,
7861 so that $t9 has the correct value at function entry. */
7864 mips_skip_pic_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7866 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7867 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7868 struct bound_minimal_symbol msym
;
7870 gdb_byte stub_code
[16];
7871 int32_t stub_words
[4];
7873 /* The stub for foo is named ".pic.foo", and is either two
7874 instructions inserted before foo or a three instruction sequence
7875 which jumps to foo. */
7876 msym
= lookup_minimal_symbol_by_pc (pc
);
7877 if (msym
.minsym
== NULL
7878 || BMSYMBOL_VALUE_ADDRESS (msym
) != pc
7879 || MSYMBOL_LINKAGE_NAME (msym
.minsym
) == NULL
7880 || !startswith (MSYMBOL_LINKAGE_NAME (msym
.minsym
), ".pic."))
7883 /* A two-instruction header. */
7884 if (MSYMBOL_SIZE (msym
.minsym
) == 8)
7887 /* A three-instruction (plus delay slot) trampoline. */
7888 if (MSYMBOL_SIZE (msym
.minsym
) == 16)
7890 if (target_read_memory (pc
, stub_code
, 16) != 0)
7892 for (i
= 0; i
< 4; i
++)
7893 stub_words
[i
] = extract_unsigned_integer (stub_code
+ i
* 4,
7896 /* A stub contains these instructions:
7899 addiu t9, t9, %lo(target)
7902 This works even for N64, since stubs are only generated with
7904 if ((stub_words
[0] & 0xffff0000U
) == 0x3c190000
7905 && (stub_words
[1] & 0xfc000000U
) == 0x08000000
7906 && (stub_words
[2] & 0xffff0000U
) == 0x27390000
7907 && stub_words
[3] == 0x00000000)
7908 return ((((stub_words
[0] & 0x0000ffff) << 16)
7909 + (stub_words
[2] & 0x0000ffff)) ^ 0x8000) - 0x8000;
7912 /* Not a recognized stub. */
7917 mips_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7919 CORE_ADDR requested_pc
= pc
;
7920 CORE_ADDR target_pc
;
7927 new_pc
= mips_skip_mips16_trampoline_code (frame
, pc
);
7931 new_pc
= find_solib_trampoline_target (frame
, pc
);
7935 new_pc
= mips_skip_pic_trampoline_code (frame
, pc
);
7939 while (pc
!= target_pc
);
7941 return pc
!= requested_pc
? pc
: 0;
7944 /* Convert a dbx stab register number (from `r' declaration) to a GDB
7945 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7948 mips_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
7951 if (num
>= 0 && num
< 32)
7953 else if (num
>= 38 && num
< 70)
7954 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 38;
7956 regnum
= mips_regnum (gdbarch
)->hi
;
7958 regnum
= mips_regnum (gdbarch
)->lo
;
7959 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 72 && num
< 78)
7960 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 72;
7963 return gdbarch_num_regs (gdbarch
) + regnum
;
7967 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
7968 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7971 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
7974 if (num
>= 0 && num
< 32)
7976 else if (num
>= 32 && num
< 64)
7977 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 32;
7979 regnum
= mips_regnum (gdbarch
)->hi
;
7981 regnum
= mips_regnum (gdbarch
)->lo
;
7982 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 66 && num
< 72)
7983 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 66;
7986 return gdbarch_num_regs (gdbarch
) + regnum
;
7990 mips_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
7992 /* Only makes sense to supply raw registers. */
7993 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
));
7994 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
7995 decide if it is valid. Should instead define a standard sim/gdb
7996 register numbering scheme. */
7997 if (gdbarch_register_name (gdbarch
,
7998 gdbarch_num_regs (gdbarch
) + regnum
) != NULL
7999 && gdbarch_register_name (gdbarch
,
8000 gdbarch_num_regs (gdbarch
)
8001 + regnum
)[0] != '\0')
8004 return LEGACY_SIM_REGNO_IGNORE
;
8008 /* Convert an integer into an address. Extracting the value signed
8009 guarantees a correctly sign extended address. */
8012 mips_integer_to_address (struct gdbarch
*gdbarch
,
8013 struct type
*type
, const gdb_byte
*buf
)
8015 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
8016 return extract_signed_integer (buf
, TYPE_LENGTH (type
), byte_order
);
8019 /* Dummy virtual frame pointer method. This is no more or less accurate
8020 than most other architectures; we just need to be explicit about it,
8021 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
8022 an assertion failure. */
8025 mips_virtual_frame_pointer (struct gdbarch
*gdbarch
,
8026 CORE_ADDR pc
, int *reg
, LONGEST
*offset
)
8028 *reg
= MIPS_SP_REGNUM
;
8033 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
8035 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
8036 const char *name
= bfd_get_section_name (abfd
, sect
);
8038 if (*abip
!= MIPS_ABI_UNKNOWN
)
8041 if (!startswith (name
, ".mdebug."))
8044 if (strcmp (name
, ".mdebug.abi32") == 0)
8045 *abip
= MIPS_ABI_O32
;
8046 else if (strcmp (name
, ".mdebug.abiN32") == 0)
8047 *abip
= MIPS_ABI_N32
;
8048 else if (strcmp (name
, ".mdebug.abi64") == 0)
8049 *abip
= MIPS_ABI_N64
;
8050 else if (strcmp (name
, ".mdebug.abiO64") == 0)
8051 *abip
= MIPS_ABI_O64
;
8052 else if (strcmp (name
, ".mdebug.eabi32") == 0)
8053 *abip
= MIPS_ABI_EABI32
;
8054 else if (strcmp (name
, ".mdebug.eabi64") == 0)
8055 *abip
= MIPS_ABI_EABI64
;
8057 warning (_("unsupported ABI %s."), name
+ 8);
8061 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
8063 int *lbp
= (int *) obj
;
8064 const char *name
= bfd_get_section_name (abfd
, sect
);
8066 if (startswith (name
, ".gcc_compiled_long32"))
8068 else if (startswith (name
, ".gcc_compiled_long64"))
8070 else if (startswith (name
, ".gcc_compiled_long"))
8071 warning (_("unrecognized .gcc_compiled_longXX"));
8074 static enum mips_abi
8075 global_mips_abi (void)
8079 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
8080 if (mips_abi_strings
[i
] == mips_abi_string
)
8081 return (enum mips_abi
) i
;
8083 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
8086 /* Return the default compressed instruction set, either of MIPS16
8087 or microMIPS, selected when none could have been determined from
8088 the ELF header of the binary being executed (or no binary has been
8091 static enum mips_isa
8092 global_mips_compression (void)
8096 for (i
= 0; mips_compression_strings
[i
] != NULL
; i
++)
8097 if (mips_compression_strings
[i
] == mips_compression_string
)
8098 return (enum mips_isa
) i
;
8100 internal_error (__FILE__
, __LINE__
, _("unknown compressed ISA string"));
8104 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
8106 /* If the size matches the set of 32-bit or 64-bit integer registers,
8107 assume that's what we've got. */
8108 register_remote_g_packet_guess (gdbarch
, 38 * 4, mips_tdesc_gp32
);
8109 register_remote_g_packet_guess (gdbarch
, 38 * 8, mips_tdesc_gp64
);
8111 /* If the size matches the full set of registers GDB traditionally
8112 knows about, including floating point, for either 32-bit or
8113 64-bit, assume that's what we've got. */
8114 register_remote_g_packet_guess (gdbarch
, 90 * 4, mips_tdesc_gp32
);
8115 register_remote_g_packet_guess (gdbarch
, 90 * 8, mips_tdesc_gp64
);
8117 /* Otherwise we don't have a useful guess. */
8120 static struct value
*
8121 value_of_mips_user_reg (struct frame_info
*frame
, const void *baton
)
8123 const int *reg_p
= (const int *) baton
;
8124 return value_of_register (*reg_p
, frame
);
8127 static struct gdbarch
*
8128 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
8130 struct gdbarch
*gdbarch
;
8131 struct gdbarch_tdep
*tdep
;
8133 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
8135 enum mips_fpu_type fpu_type
;
8136 struct tdesc_arch_data
*tdesc_data
= NULL
;
8137 int elf_fpu_type
= Val_GNU_MIPS_ABI_FP_ANY
;
8138 const char **reg_names
;
8139 struct mips_regnum mips_regnum
, *regnum
;
8140 enum mips_isa mips_isa
;
8144 /* Fill in the OS dependent register numbers and names. */
8145 if (info
.osabi
== GDB_OSABI_LINUX
)
8147 mips_regnum
.fp0
= 38;
8148 mips_regnum
.pc
= 37;
8149 mips_regnum
.cause
= 36;
8150 mips_regnum
.badvaddr
= 35;
8151 mips_regnum
.hi
= 34;
8152 mips_regnum
.lo
= 33;
8153 mips_regnum
.fp_control_status
= 70;
8154 mips_regnum
.fp_implementation_revision
= 71;
8155 mips_regnum
.dspacc
= -1;
8156 mips_regnum
.dspctl
= -1;
8160 reg_names
= mips_linux_reg_names
;
8164 mips_regnum
.lo
= MIPS_EMBED_LO_REGNUM
;
8165 mips_regnum
.hi
= MIPS_EMBED_HI_REGNUM
;
8166 mips_regnum
.badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
8167 mips_regnum
.cause
= MIPS_EMBED_CAUSE_REGNUM
;
8168 mips_regnum
.pc
= MIPS_EMBED_PC_REGNUM
;
8169 mips_regnum
.fp0
= MIPS_EMBED_FP0_REGNUM
;
8170 mips_regnum
.fp_control_status
= 70;
8171 mips_regnum
.fp_implementation_revision
= 71;
8172 mips_regnum
.dspacc
= dspacc
= -1;
8173 mips_regnum
.dspctl
= dspctl
= -1;
8174 num_regs
= MIPS_LAST_EMBED_REGNUM
+ 1;
8175 if (info
.bfd_arch_info
!= NULL
8176 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
8177 reg_names
= mips_tx39_reg_names
;
8179 reg_names
= mips_generic_reg_names
;
8182 /* Check any target description for validity. */
8183 if (tdesc_has_registers (info
.target_desc
))
8185 static const char *const mips_gprs
[] = {
8186 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
8187 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
8188 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
8189 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
8191 static const char *const mips_fprs
[] = {
8192 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
8193 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
8194 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
8195 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
8198 const struct tdesc_feature
*feature
;
8201 feature
= tdesc_find_feature (info
.target_desc
,
8202 "org.gnu.gdb.mips.cpu");
8203 if (feature
== NULL
)
8206 tdesc_data
= tdesc_data_alloc ();
8209 for (i
= MIPS_ZERO_REGNUM
; i
<= MIPS_RA_REGNUM
; i
++)
8210 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
8214 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8215 mips_regnum
.lo
, "lo");
8216 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8217 mips_regnum
.hi
, "hi");
8218 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8219 mips_regnum
.pc
, "pc");
8223 tdesc_data_cleanup (tdesc_data
);
8227 feature
= tdesc_find_feature (info
.target_desc
,
8228 "org.gnu.gdb.mips.cp0");
8229 if (feature
== NULL
)
8231 tdesc_data_cleanup (tdesc_data
);
8236 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8237 mips_regnum
.badvaddr
, "badvaddr");
8238 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8239 MIPS_PS_REGNUM
, "status");
8240 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8241 mips_regnum
.cause
, "cause");
8245 tdesc_data_cleanup (tdesc_data
);
8249 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
8250 backend is not prepared for that, though. */
8251 feature
= tdesc_find_feature (info
.target_desc
,
8252 "org.gnu.gdb.mips.fpu");
8253 if (feature
== NULL
)
8255 tdesc_data_cleanup (tdesc_data
);
8260 for (i
= 0; i
< 32; i
++)
8261 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8262 i
+ mips_regnum
.fp0
, mips_fprs
[i
]);
8264 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8265 mips_regnum
.fp_control_status
,
8268 &= tdesc_numbered_register (feature
, tdesc_data
,
8269 mips_regnum
.fp_implementation_revision
,
8274 tdesc_data_cleanup (tdesc_data
);
8278 num_regs
= mips_regnum
.fp_implementation_revision
+ 1;
8282 feature
= tdesc_find_feature (info
.target_desc
,
8283 "org.gnu.gdb.mips.dsp");
8284 /* The DSP registers are optional; it's OK if they are absent. */
8285 if (feature
!= NULL
)
8289 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8290 dspacc
+ i
++, "hi1");
8291 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8292 dspacc
+ i
++, "lo1");
8293 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8294 dspacc
+ i
++, "hi2");
8295 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8296 dspacc
+ i
++, "lo2");
8297 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8298 dspacc
+ i
++, "hi3");
8299 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8300 dspacc
+ i
++, "lo3");
8302 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8307 tdesc_data_cleanup (tdesc_data
);
8311 mips_regnum
.dspacc
= dspacc
;
8312 mips_regnum
.dspctl
= dspctl
;
8314 num_regs
= mips_regnum
.dspctl
+ 1;
8318 /* It would be nice to detect an attempt to use a 64-bit ABI
8319 when only 32-bit registers are provided. */
8323 /* First of all, extract the elf_flags, if available. */
8324 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
8325 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
8326 else if (arches
!= NULL
)
8327 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
8331 fprintf_unfiltered (gdb_stdlog
,
8332 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
8334 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
8335 switch ((elf_flags
& EF_MIPS_ABI
))
8337 case E_MIPS_ABI_O32
:
8338 found_abi
= MIPS_ABI_O32
;
8340 case E_MIPS_ABI_O64
:
8341 found_abi
= MIPS_ABI_O64
;
8343 case E_MIPS_ABI_EABI32
:
8344 found_abi
= MIPS_ABI_EABI32
;
8346 case E_MIPS_ABI_EABI64
:
8347 found_abi
= MIPS_ABI_EABI64
;
8350 if ((elf_flags
& EF_MIPS_ABI2
))
8351 found_abi
= MIPS_ABI_N32
;
8353 found_abi
= MIPS_ABI_UNKNOWN
;
8357 /* GCC creates a pseudo-section whose name describes the ABI. */
8358 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
8359 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
8361 /* If we have no useful BFD information, use the ABI from the last
8362 MIPS architecture (if there is one). */
8363 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
8364 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
8366 /* Try the architecture for any hint of the correct ABI. */
8367 if (found_abi
== MIPS_ABI_UNKNOWN
8368 && info
.bfd_arch_info
!= NULL
8369 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
8371 switch (info
.bfd_arch_info
->mach
)
8373 case bfd_mach_mips3900
:
8374 found_abi
= MIPS_ABI_EABI32
;
8376 case bfd_mach_mips4100
:
8377 case bfd_mach_mips5000
:
8378 found_abi
= MIPS_ABI_EABI64
;
8380 case bfd_mach_mips8000
:
8381 case bfd_mach_mips10000
:
8382 /* On Irix, ELF64 executables use the N64 ABI. The
8383 pseudo-sections which describe the ABI aren't present
8384 on IRIX. (Even for executables created by gcc.) */
8385 if (info
.abfd
!= NULL
8386 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
8387 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
8388 found_abi
= MIPS_ABI_N64
;
8390 found_abi
= MIPS_ABI_N32
;
8395 /* Default 64-bit objects to N64 instead of O32. */
8396 if (found_abi
== MIPS_ABI_UNKNOWN
8397 && info
.abfd
!= NULL
8398 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
8399 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
8400 found_abi
= MIPS_ABI_N64
;
8403 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
8406 /* What has the user specified from the command line? */
8407 wanted_abi
= global_mips_abi ();
8409 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
8412 /* Now that we have found what the ABI for this binary would be,
8413 check whether the user is overriding it. */
8414 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
8415 mips_abi
= wanted_abi
;
8416 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
8417 mips_abi
= found_abi
;
8419 mips_abi
= MIPS_ABI_O32
;
8421 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
8424 /* Determine the default compressed ISA. */
8425 if ((elf_flags
& EF_MIPS_ARCH_ASE_MICROMIPS
) != 0
8426 && (elf_flags
& EF_MIPS_ARCH_ASE_M16
) == 0)
8427 mips_isa
= ISA_MICROMIPS
;
8428 else if ((elf_flags
& EF_MIPS_ARCH_ASE_M16
) != 0
8429 && (elf_flags
& EF_MIPS_ARCH_ASE_MICROMIPS
) == 0)
8430 mips_isa
= ISA_MIPS16
;
8432 mips_isa
= global_mips_compression ();
8433 mips_compression_string
= mips_compression_strings
[mips_isa
];
8435 /* Also used when doing an architecture lookup. */
8437 fprintf_unfiltered (gdb_stdlog
,
8438 "mips_gdbarch_init: "
8439 "mips64_transfers_32bit_regs_p = %d\n",
8440 mips64_transfers_32bit_regs_p
);
8442 /* Determine the MIPS FPU type. */
8445 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
8446 elf_fpu_type
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
8447 Tag_GNU_MIPS_ABI_FP
);
8448 #endif /* HAVE_ELF */
8450 if (!mips_fpu_type_auto
)
8451 fpu_type
= mips_fpu_type
;
8452 else if (elf_fpu_type
!= Val_GNU_MIPS_ABI_FP_ANY
)
8454 switch (elf_fpu_type
)
8456 case Val_GNU_MIPS_ABI_FP_DOUBLE
:
8457 fpu_type
= MIPS_FPU_DOUBLE
;
8459 case Val_GNU_MIPS_ABI_FP_SINGLE
:
8460 fpu_type
= MIPS_FPU_SINGLE
;
8462 case Val_GNU_MIPS_ABI_FP_SOFT
:
8464 /* Soft float or unknown. */
8465 fpu_type
= MIPS_FPU_NONE
;
8469 else if (info
.bfd_arch_info
!= NULL
8470 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
8471 switch (info
.bfd_arch_info
->mach
)
8473 case bfd_mach_mips3900
:
8474 case bfd_mach_mips4100
:
8475 case bfd_mach_mips4111
:
8476 case bfd_mach_mips4120
:
8477 fpu_type
= MIPS_FPU_NONE
;
8479 case bfd_mach_mips4650
:
8480 fpu_type
= MIPS_FPU_SINGLE
;
8483 fpu_type
= MIPS_FPU_DOUBLE
;
8486 else if (arches
!= NULL
)
8487 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
8489 fpu_type
= MIPS_FPU_DOUBLE
;
8491 fprintf_unfiltered (gdb_stdlog
,
8492 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
8494 /* Check for blatant incompatibilities. */
8496 /* If we have only 32-bit registers, then we can't debug a 64-bit
8498 if (info
.target_desc
8499 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
8500 && mips_abi
!= MIPS_ABI_EABI32
8501 && mips_abi
!= MIPS_ABI_O32
)
8503 if (tdesc_data
!= NULL
)
8504 tdesc_data_cleanup (tdesc_data
);
8508 /* Try to find a pre-existing architecture. */
8509 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
8511 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
8513 /* MIPS needs to be pedantic about which ABI and the compressed
8514 ISA variation the object is using. */
8515 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
8517 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
8519 if (gdbarch_tdep (arches
->gdbarch
)->mips_isa
!= mips_isa
)
8521 /* Need to be pedantic about which register virtual size is
8523 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
8524 != mips64_transfers_32bit_regs_p
)
8526 /* Be pedantic about which FPU is selected. */
8527 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
8530 if (tdesc_data
!= NULL
)
8531 tdesc_data_cleanup (tdesc_data
);
8532 return arches
->gdbarch
;
8535 /* Need a new architecture. Fill in a target specific vector. */
8536 tdep
= XNEW (struct gdbarch_tdep
);
8537 gdbarch
= gdbarch_alloc (&info
, tdep
);
8538 tdep
->elf_flags
= elf_flags
;
8539 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
8540 tdep
->found_abi
= found_abi
;
8541 tdep
->mips_abi
= mips_abi
;
8542 tdep
->mips_isa
= mips_isa
;
8543 tdep
->mips_fpu_type
= fpu_type
;
8544 tdep
->register_size_valid_p
= 0;
8545 tdep
->register_size
= 0;
8547 if (info
.target_desc
)
8549 /* Some useful properties can be inferred from the target. */
8550 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
8552 tdep
->register_size_valid_p
= 1;
8553 tdep
->register_size
= 4;
8555 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
8557 tdep
->register_size_valid_p
= 1;
8558 tdep
->register_size
= 8;
8562 /* Initially set everything according to the default ABI/ISA. */
8563 set_gdbarch_short_bit (gdbarch
, 16);
8564 set_gdbarch_int_bit (gdbarch
, 32);
8565 set_gdbarch_float_bit (gdbarch
, 32);
8566 set_gdbarch_double_bit (gdbarch
, 64);
8567 set_gdbarch_long_double_bit (gdbarch
, 64);
8568 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
8569 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
8570 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
8572 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
8573 mips_ax_pseudo_register_collect
);
8574 set_gdbarch_ax_pseudo_register_push_stack
8575 (gdbarch
, mips_ax_pseudo_register_push_stack
);
8577 set_gdbarch_elf_make_msymbol_special (gdbarch
,
8578 mips_elf_make_msymbol_special
);
8579 set_gdbarch_make_symbol_special (gdbarch
, mips_make_symbol_special
);
8580 set_gdbarch_adjust_dwarf2_addr (gdbarch
, mips_adjust_dwarf2_addr
);
8581 set_gdbarch_adjust_dwarf2_line (gdbarch
, mips_adjust_dwarf2_line
);
8583 regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
, struct mips_regnum
);
8584 *regnum
= mips_regnum
;
8585 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
8586 set_gdbarch_num_regs (gdbarch
, num_regs
);
8587 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
8588 set_gdbarch_register_name (gdbarch
, mips_register_name
);
8589 set_gdbarch_virtual_frame_pointer (gdbarch
, mips_virtual_frame_pointer
);
8590 tdep
->mips_processor_reg_names
= reg_names
;
8591 tdep
->regnum
= regnum
;
8596 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
8597 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
8598 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
8599 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
8600 tdep
->default_mask_address_p
= 0;
8601 set_gdbarch_long_bit (gdbarch
, 32);
8602 set_gdbarch_ptr_bit (gdbarch
, 32);
8603 set_gdbarch_long_long_bit (gdbarch
, 64);
8606 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
8607 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
8608 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
8609 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
8610 tdep
->default_mask_address_p
= 0;
8611 set_gdbarch_long_bit (gdbarch
, 32);
8612 set_gdbarch_ptr_bit (gdbarch
, 32);
8613 set_gdbarch_long_long_bit (gdbarch
, 64);
8615 case MIPS_ABI_EABI32
:
8616 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
8617 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
8618 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8619 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8620 tdep
->default_mask_address_p
= 0;
8621 set_gdbarch_long_bit (gdbarch
, 32);
8622 set_gdbarch_ptr_bit (gdbarch
, 32);
8623 set_gdbarch_long_long_bit (gdbarch
, 64);
8625 case MIPS_ABI_EABI64
:
8626 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
8627 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
8628 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8629 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8630 tdep
->default_mask_address_p
= 0;
8631 set_gdbarch_long_bit (gdbarch
, 64);
8632 set_gdbarch_ptr_bit (gdbarch
, 64);
8633 set_gdbarch_long_long_bit (gdbarch
, 64);
8636 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
8637 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
8638 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8639 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8640 tdep
->default_mask_address_p
= 0;
8641 set_gdbarch_long_bit (gdbarch
, 32);
8642 set_gdbarch_ptr_bit (gdbarch
, 32);
8643 set_gdbarch_long_long_bit (gdbarch
, 64);
8644 set_gdbarch_long_double_bit (gdbarch
, 128);
8645 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
8648 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
8649 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
8650 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8651 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8652 tdep
->default_mask_address_p
= 0;
8653 set_gdbarch_long_bit (gdbarch
, 64);
8654 set_gdbarch_ptr_bit (gdbarch
, 64);
8655 set_gdbarch_long_long_bit (gdbarch
, 64);
8656 set_gdbarch_long_double_bit (gdbarch
, 128);
8657 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
8660 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
8663 /* GCC creates a pseudo-section whose name specifies the size of
8664 longs, since -mlong32 or -mlong64 may be used independent of
8665 other options. How those options affect pointer sizes is ABI and
8666 architecture dependent, so use them to override the default sizes
8667 set by the ABI. This table shows the relationship between ABI,
8668 -mlongXX, and size of pointers:
8670 ABI -mlongXX ptr bits
8671 --- -------- --------
8685 Note that for o32 and eabi32, pointers are always 32 bits
8686 regardless of any -mlongXX option. For all others, pointers and
8687 longs are the same, as set by -mlongXX or set by defaults. */
8689 if (info
.abfd
!= NULL
)
8693 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
8696 set_gdbarch_long_bit (gdbarch
, long_bit
);
8700 case MIPS_ABI_EABI32
:
8705 case MIPS_ABI_EABI64
:
8706 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
8709 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
8714 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
8715 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
8718 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
8719 flag in object files because to do so would make it impossible to
8720 link with libraries compiled without "-gp32". This is
8721 unnecessarily restrictive.
8723 We could solve this problem by adding "-gp32" multilibs to gcc,
8724 but to set this flag before gcc is built with such multilibs will
8725 break too many systems.''
8727 But even more unhelpfully, the default linker output target for
8728 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
8729 for 64-bit programs - you need to change the ABI to change this,
8730 and not all gcc targets support that currently. Therefore using
8731 this flag to detect 32-bit mode would do the wrong thing given
8732 the current gcc - it would make GDB treat these 64-bit programs
8733 as 32-bit programs by default. */
8735 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
8736 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
8738 /* Add/remove bits from an address. The MIPS needs be careful to
8739 ensure that all 32 bit addresses are sign extended to 64 bits. */
8740 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
8742 /* Unwind the frame. */
8743 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
8744 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
8745 set_gdbarch_dummy_id (gdbarch
, mips_dummy_id
);
8747 /* Map debug register numbers onto internal register numbers. */
8748 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
8749 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
8750 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
8751 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
8752 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
8753 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
8755 /* MIPS version of CALL_DUMMY. */
8757 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
8758 set_gdbarch_push_dummy_code (gdbarch
, mips_push_dummy_code
);
8759 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
8761 set_gdbarch_print_float_info (gdbarch
, mips_print_float_info
);
8763 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
8764 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
8765 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
8767 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
8768 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
8769 set_gdbarch_remote_breakpoint_from_pc (gdbarch
,
8770 mips_remote_breakpoint_from_pc
);
8771 set_gdbarch_adjust_breakpoint_address (gdbarch
,
8772 mips_adjust_breakpoint_address
);
8774 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
8776 set_gdbarch_stack_frame_destroyed_p (gdbarch
, mips_stack_frame_destroyed_p
);
8778 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
8779 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
8780 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
8782 set_gdbarch_register_type (gdbarch
, mips_register_type
);
8784 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
8786 if (mips_abi
== MIPS_ABI_N32
)
8787 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n32
);
8788 else if (mips_abi
== MIPS_ABI_N64
)
8789 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n64
);
8791 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
8793 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint,
8794 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint
8795 need to all be folded into the target vector. Since they are
8796 being used as guards for target_stopped_by_watchpoint, why not have
8797 target_stopped_by_watchpoint return the type of watchpoint that the code
8799 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
8801 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
8803 /* NOTE drow/2012-04-25: We overload the core solib trampoline code
8804 to support MIPS16. This is a bad thing. Make sure not to do it
8805 if we have an OS ABI that actually supports shared libraries, since
8806 shared library support is more important. If we have an OS someday
8807 that supports both shared libraries and MIPS16, we'll have to find
8808 a better place for these.
8809 macro/2012-04-25: But that applies to return trampolines only and
8810 currently no MIPS OS ABI uses shared libraries that have them. */
8811 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
8813 set_gdbarch_single_step_through_delay (gdbarch
,
8814 mips_single_step_through_delay
);
8816 /* Virtual tables. */
8817 set_gdbarch_vbit_in_delta (gdbarch
, 1);
8819 mips_register_g_packet_guesses (gdbarch
);
8821 /* Hook in OS ABI-specific overrides, if they have been registered. */
8822 info
.tdep_info
= tdesc_data
;
8823 gdbarch_init_osabi (info
, gdbarch
);
8825 /* The hook may have adjusted num_regs, fetch the final value and
8826 set pc_regnum and sp_regnum now that it has been fixed. */
8827 num_regs
= gdbarch_num_regs (gdbarch
);
8828 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
8829 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
8831 /* Unwind the frame. */
8832 dwarf2_append_unwinders (gdbarch
);
8833 frame_unwind_append_unwinder (gdbarch
, &mips_stub_frame_unwind
);
8834 frame_unwind_append_unwinder (gdbarch
, &mips_insn16_frame_unwind
);
8835 frame_unwind_append_unwinder (gdbarch
, &mips_micro_frame_unwind
);
8836 frame_unwind_append_unwinder (gdbarch
, &mips_insn32_frame_unwind
);
8837 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
8838 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
8839 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
8840 frame_base_append_sniffer (gdbarch
, mips_micro_frame_base_sniffer
);
8841 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
8845 set_tdesc_pseudo_register_type (gdbarch
, mips_pseudo_register_type
);
8846 tdesc_use_registers (gdbarch
, info
.target_desc
, tdesc_data
);
8848 /* Override the normal target description methods to handle our
8849 dual real and pseudo registers. */
8850 set_gdbarch_register_name (gdbarch
, mips_register_name
);
8851 set_gdbarch_register_reggroup_p (gdbarch
,
8852 mips_tdesc_register_reggroup_p
);
8854 num_regs
= gdbarch_num_regs (gdbarch
);
8855 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
8856 set_gdbarch_pc_regnum (gdbarch
, tdep
->regnum
->pc
+ num_regs
);
8857 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
8860 /* Add ABI-specific aliases for the registers. */
8861 if (mips_abi
== MIPS_ABI_N32
|| mips_abi
== MIPS_ABI_N64
)
8862 for (i
= 0; i
< ARRAY_SIZE (mips_n32_n64_aliases
); i
++)
8863 user_reg_add (gdbarch
, mips_n32_n64_aliases
[i
].name
,
8864 value_of_mips_user_reg
, &mips_n32_n64_aliases
[i
].regnum
);
8866 for (i
= 0; i
< ARRAY_SIZE (mips_o32_aliases
); i
++)
8867 user_reg_add (gdbarch
, mips_o32_aliases
[i
].name
,
8868 value_of_mips_user_reg
, &mips_o32_aliases
[i
].regnum
);
8870 /* Add some other standard aliases. */
8871 for (i
= 0; i
< ARRAY_SIZE (mips_register_aliases
); i
++)
8872 user_reg_add (gdbarch
, mips_register_aliases
[i
].name
,
8873 value_of_mips_user_reg
, &mips_register_aliases
[i
].regnum
);
8875 for (i
= 0; i
< ARRAY_SIZE (mips_numeric_register_aliases
); i
++)
8876 user_reg_add (gdbarch
, mips_numeric_register_aliases
[i
].name
,
8877 value_of_mips_user_reg
,
8878 &mips_numeric_register_aliases
[i
].regnum
);
8884 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
8886 struct gdbarch_info info
;
8888 /* Force the architecture to update, and (if it's a MIPS architecture)
8889 mips_gdbarch_init will take care of the rest. */
8890 gdbarch_info_init (&info
);
8891 gdbarch_update_p (info
);
8894 /* Print out which MIPS ABI is in use. */
8897 show_mips_abi (struct ui_file
*file
,
8899 struct cmd_list_element
*ignored_cmd
,
8900 const char *ignored_value
)
8902 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_mips
)
8905 "The MIPS ABI is unknown because the current architecture "
8909 enum mips_abi global_abi
= global_mips_abi ();
8910 enum mips_abi actual_abi
= mips_abi (target_gdbarch ());
8911 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
8913 if (global_abi
== MIPS_ABI_UNKNOWN
)
8916 "The MIPS ABI is set automatically (currently \"%s\").\n",
8918 else if (global_abi
== actual_abi
)
8921 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
8925 /* Probably shouldn't happen... */
8926 fprintf_filtered (file
,
8927 "The (auto detected) MIPS ABI \"%s\" is in use "
8928 "even though the user setting was \"%s\".\n",
8929 actual_abi_str
, mips_abi_strings
[global_abi
]);
8934 /* Print out which MIPS compressed ISA encoding is used. */
8937 show_mips_compression (struct ui_file
*file
, int from_tty
,
8938 struct cmd_list_element
*c
, const char *value
)
8940 fprintf_filtered (file
, _("The compressed ISA encoding used is %s.\n"),
8945 mips_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
8947 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
8951 int ef_mips_32bitmode
;
8952 /* Determine the ISA. */
8953 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
8971 /* Determine the size of a pointer. */
8972 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
8973 fprintf_unfiltered (file
,
8974 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
8976 fprintf_unfiltered (file
,
8977 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
8979 fprintf_unfiltered (file
,
8980 "mips_dump_tdep: ef_mips_arch = %d\n",
8982 fprintf_unfiltered (file
,
8983 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
8984 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
8985 fprintf_unfiltered (file
,
8987 "mips_mask_address_p() %d (default %d)\n",
8988 mips_mask_address_p (tdep
),
8989 tdep
->default_mask_address_p
);
8991 fprintf_unfiltered (file
,
8992 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
8993 MIPS_DEFAULT_FPU_TYPE
,
8994 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
8995 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
8996 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
8998 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n",
8999 MIPS_EABI (gdbarch
));
9000 fprintf_unfiltered (file
,
9001 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
9002 MIPS_FPU_TYPE (gdbarch
),
9003 (MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_NONE
? "none"
9004 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_SINGLE
? "single"
9005 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_DOUBLE
? "double"
9009 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
9012 _initialize_mips_tdep (void)
9014 static struct cmd_list_element
*mipsfpulist
= NULL
;
9015 struct cmd_list_element
*c
;
9017 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
9018 if (MIPS_ABI_LAST
+ 1
9019 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
9020 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
9022 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
9024 mips_pdr_data
= register_objfile_data ();
9026 /* Create feature sets with the appropriate properties. The values
9027 are not important. */
9028 mips_tdesc_gp32
= allocate_target_description ();
9029 set_tdesc_property (mips_tdesc_gp32
, PROPERTY_GP32
, "");
9031 mips_tdesc_gp64
= allocate_target_description ();
9032 set_tdesc_property (mips_tdesc_gp64
, PROPERTY_GP64
, "");
9034 /* Add root prefix command for all "set mips"/"show mips" commands. */
9035 add_prefix_cmd ("mips", no_class
, set_mips_command
,
9036 _("Various MIPS specific commands."),
9037 &setmipscmdlist
, "set mips ", 0, &setlist
);
9039 add_prefix_cmd ("mips", no_class
, show_mips_command
,
9040 _("Various MIPS specific commands."),
9041 &showmipscmdlist
, "show mips ", 0, &showlist
);
9043 /* Allow the user to override the ABI. */
9044 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
9045 &mips_abi_string
, _("\
9046 Set the MIPS ABI used by this program."), _("\
9047 Show the MIPS ABI used by this program."), _("\
9048 This option can be set to one of:\n\
9049 auto - the default ABI associated with the current binary\n\
9058 &setmipscmdlist
, &showmipscmdlist
);
9060 /* Allow the user to set the ISA to assume for compressed code if ELF
9061 file flags don't tell or there is no program file selected. This
9062 setting is updated whenever unambiguous ELF file flags are interpreted,
9063 and carried over to subsequent sessions. */
9064 add_setshow_enum_cmd ("compression", class_obscure
, mips_compression_strings
,
9065 &mips_compression_string
, _("\
9066 Set the compressed ISA encoding used by MIPS code."), _("\
9067 Show the compressed ISA encoding used by MIPS code."), _("\
9068 Select the compressed ISA encoding used in functions that have no symbol\n\
9069 information available. The encoding can be set to either of:\n\
9072 and is updated automatically from ELF file flags if available."),
9074 show_mips_compression
,
9075 &setmipscmdlist
, &showmipscmdlist
);
9077 /* Let the user turn off floating point and set the fence post for
9078 heuristic_proc_start. */
9080 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
9081 _("Set use of MIPS floating-point coprocessor."),
9082 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
9083 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
9084 _("Select single-precision MIPS floating-point coprocessor."),
9086 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
9087 _("Select double-precision MIPS floating-point coprocessor."),
9089 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
9090 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
9091 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
9092 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
9093 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
9094 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
9095 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
9096 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
9097 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
9098 _("Select MIPS floating-point coprocessor automatically."),
9100 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
9101 _("Show current use of MIPS floating-point coprocessor target."),
9104 /* We really would like to have both "0" and "unlimited" work, but
9105 command.c doesn't deal with that. So make it a var_zinteger
9106 because the user can always use "999999" or some such for unlimited. */
9107 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
9108 &heuristic_fence_post
, _("\
9109 Set the distance searched for the start of a function."), _("\
9110 Show the distance searched for the start of a function."), _("\
9111 If you are debugging a stripped executable, GDB needs to search through the\n\
9112 program for the start of a function. This command sets the distance of the\n\
9113 search. The only need to set it is when debugging a stripped executable."),
9114 reinit_frame_cache_sfunc
,
9115 NULL
, /* FIXME: i18n: The distance searched for
9116 the start of a function is %s. */
9117 &setlist
, &showlist
);
9119 /* Allow the user to control whether the upper bits of 64-bit
9120 addresses should be zeroed. */
9121 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
9122 &mask_address_var
, _("\
9123 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
9124 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
9125 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\
9126 allow GDB to determine the correct value."),
9127 NULL
, show_mask_address
,
9128 &setmipscmdlist
, &showmipscmdlist
);
9130 /* Allow the user to control the size of 32 bit registers within the
9131 raw remote packet. */
9132 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
9133 &mips64_transfers_32bit_regs_p
, _("\
9134 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
9136 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
9138 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
9139 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
9140 64 bits for others. Use \"off\" to disable compatibility mode"),
9141 set_mips64_transfers_32bit_regs
,
9142 NULL
, /* FIXME: i18n: Compatibility with 64-bit
9143 MIPS target that transfers 32-bit
9144 quantities is %s. */
9145 &setlist
, &showlist
);
9147 /* Debug this files internals. */
9148 add_setshow_zuinteger_cmd ("mips", class_maintenance
,
9150 Set mips debugging."), _("\
9151 Show mips debugging."), _("\
9152 When non-zero, mips specific debugging is enabled."),
9154 NULL
, /* FIXME: i18n: Mips debugging is
9156 &setdebuglist
, &showdebuglist
);