1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988-2022 Free Software Foundation, Inc.
5 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
6 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
35 #include "arch-utils.h"
38 #include "mips-tdep.h"
40 #include "reggroups.h"
41 #include "opcode/mips.h"
45 #include "sim-regno.h"
48 #include "frame-unwind.h"
49 #include "frame-base.h"
50 #include "trad-frame.h"
53 #include "target-descriptions.h"
54 #include "dwarf2/frame.h"
55 #include "user-regs.h"
58 #include "target-float.h"
61 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
63 static int mips32_instruction_has_delay_slot (struct gdbarch
*gdbarch
,
65 static int micromips_instruction_has_delay_slot (ULONGEST insn
, int mustbe32
);
66 static int mips16_instruction_has_delay_slot (unsigned short inst
,
69 static int mips32_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
71 static int micromips_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
72 CORE_ADDR addr
, int mustbe32
);
73 static int mips16_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
74 CORE_ADDR addr
, int mustbe32
);
76 static void mips_print_float_info (struct gdbarch
*, struct ui_file
*,
77 struct frame_info
*, const char *);
79 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
80 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
81 #define ST0_FR (1 << 26)
83 /* The sizes of floating point registers. */
87 MIPS_FPU_SINGLE_REGSIZE
= 4,
88 MIPS_FPU_DOUBLE_REGSIZE
= 8
97 static const char *mips_abi_string
;
99 static const char *const mips_abi_strings
[] = {
110 /* Enum describing the different kinds of breakpoints. */
112 enum mips_breakpoint_kind
114 /* 16-bit MIPS16 mode breakpoint. */
115 MIPS_BP_KIND_MIPS16
= 2,
117 /* 16-bit microMIPS mode breakpoint. */
118 MIPS_BP_KIND_MICROMIPS16
= 3,
120 /* 32-bit standard MIPS mode breakpoint. */
121 MIPS_BP_KIND_MIPS32
= 4,
123 /* 32-bit microMIPS mode breakpoint. */
124 MIPS_BP_KIND_MICROMIPS32
= 5,
127 /* For backwards compatibility we default to MIPS16. This flag is
128 overridden as soon as unambiguous ELF file flags tell us the
129 compressed ISA encoding used. */
130 static const char mips_compression_mips16
[] = "mips16";
131 static const char mips_compression_micromips
[] = "micromips";
132 static const char *const mips_compression_strings
[] =
134 mips_compression_mips16
,
135 mips_compression_micromips
,
139 static const char *mips_compression_string
= mips_compression_mips16
;
141 /* The standard register names, and all the valid aliases for them. */
142 struct register_alias
148 /* Aliases for o32 and most other ABIs. */
149 const struct register_alias mips_o32_aliases
[] = {
156 /* Aliases for n32 and n64. */
157 const struct register_alias mips_n32_n64_aliases
[] = {
164 /* Aliases for ABI-independent registers. */
165 const struct register_alias mips_register_aliases
[] = {
166 /* The architecture manuals specify these ABI-independent names for
168 #define R(n) { "r" #n, n }
169 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
170 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
171 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
172 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
175 /* k0 and k1 are sometimes called these instead (for "kernel
180 /* This is the traditional GDB name for the CP0 status register. */
181 { "sr", MIPS_PS_REGNUM
},
183 /* This is the traditional GDB name for the CP0 BadVAddr register. */
184 { "bad", MIPS_EMBED_BADVADDR_REGNUM
},
186 /* This is the traditional GDB name for the FCSR. */
187 { "fsr", MIPS_EMBED_FP0_REGNUM
+ 32 }
190 const struct register_alias mips_numeric_register_aliases
[] = {
191 #define R(n) { #n, n }
192 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
193 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
194 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
195 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
199 #ifndef MIPS_DEFAULT_FPU_TYPE
200 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
202 static int mips_fpu_type_auto
= 1;
203 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
205 static unsigned int mips_debug
= 0;
207 /* Properties (for struct target_desc) describing the g/G packet
209 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
210 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
212 struct target_desc
*mips_tdesc_gp32
;
213 struct target_desc
*mips_tdesc_gp64
;
215 /* The current set of options to be passed to the disassembler. */
216 static char *mips_disassembler_options
;
218 /* Implicit disassembler options for individual ABIs. These tell
219 libopcodes to use general-purpose register names corresponding
220 to the ABI we have selected, perhaps via a `set mips abi ...'
221 override, rather than ones inferred from the ABI set in the ELF
222 headers of the binary file selected for debugging. */
223 static const char mips_disassembler_options_o32
[] = "gpr-names=32";
224 static const char mips_disassembler_options_n32
[] = "gpr-names=n32";
225 static const char mips_disassembler_options_n64
[] = "gpr-names=64";
227 const struct mips_regnum
*
228 mips_regnum (struct gdbarch
*gdbarch
)
230 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
235 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
237 return mips_regnum (gdbarch
)->fp0
+ 12;
240 /* Return 1 if REGNUM refers to a floating-point general register, raw
241 or cooked. Otherwise return 0. */
244 mips_float_register_p (struct gdbarch
*gdbarch
, int regnum
)
246 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
248 return (rawnum
>= mips_regnum (gdbarch
)->fp0
249 && rawnum
< mips_regnum (gdbarch
)->fp0
+ 32);
253 mips_eabi (gdbarch
*arch
)
255 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (arch
);
256 return (tdep
->mips_abi
== MIPS_ABI_EABI32 \
257 || tdep
->mips_abi
== MIPS_ABI_EABI64
);
261 mips_last_fp_arg_regnum (gdbarch
*arch
)
263 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (arch
);
264 return tdep
->mips_last_fp_arg_regnum
;
268 mips_last_arg_regnum (gdbarch
*arch
)
270 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (arch
);
271 return tdep
->mips_last_arg_regnum
;
274 static enum mips_fpu_type
275 mips_get_fpu_type (gdbarch
*arch
)
277 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (arch
);
278 return tdep
->mips_fpu_type
;
281 /* Return the MIPS ABI associated with GDBARCH. */
283 mips_abi (struct gdbarch
*gdbarch
)
285 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
286 return tdep
->mips_abi
;
290 mips_isa_regsize (struct gdbarch
*gdbarch
)
292 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
294 /* If we know how big the registers are, use that size. */
295 if (tdep
->register_size_valid_p
)
296 return tdep
->register_size
;
298 /* Fall back to the previous behavior. */
299 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
300 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
303 /* Max saved register size. */
304 #define MAX_MIPS_ABI_REGSIZE 8
306 /* Return the currently configured (or set) saved register size. */
309 mips_abi_regsize (struct gdbarch
*gdbarch
)
311 switch (mips_abi (gdbarch
))
313 case MIPS_ABI_EABI32
:
319 case MIPS_ABI_EABI64
:
321 case MIPS_ABI_UNKNOWN
:
324 internal_error (__FILE__
, __LINE__
, _("bad switch"));
328 /* MIPS16/microMIPS function addresses are odd (bit 0 is set). Here
329 are some functions to handle addresses associated with compressed
330 code including but not limited to testing, setting, or clearing
331 bit 0 of such addresses. */
333 /* Return one iff compressed code is the MIPS16 instruction set. */
336 is_mips16_isa (struct gdbarch
*gdbarch
)
338 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
339 return tdep
->mips_isa
== ISA_MIPS16
;
342 /* Return one iff compressed code is the microMIPS instruction set. */
345 is_micromips_isa (struct gdbarch
*gdbarch
)
347 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
348 return tdep
->mips_isa
== ISA_MICROMIPS
;
351 /* Return one iff ADDR denotes compressed code. */
354 is_compact_addr (CORE_ADDR addr
)
359 /* Return one iff ADDR denotes standard ISA code. */
362 is_mips_addr (CORE_ADDR addr
)
364 return !is_compact_addr (addr
);
367 /* Return one iff ADDR denotes MIPS16 code. */
370 is_mips16_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
372 return is_compact_addr (addr
) && is_mips16_isa (gdbarch
);
375 /* Return one iff ADDR denotes microMIPS code. */
378 is_micromips_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
380 return is_compact_addr (addr
) && is_micromips_isa (gdbarch
);
383 /* Strip the ISA (compression) bit off from ADDR. */
386 unmake_compact_addr (CORE_ADDR addr
)
388 return ((addr
) & ~(CORE_ADDR
) 1);
391 /* Add the ISA (compression) bit to ADDR. */
394 make_compact_addr (CORE_ADDR addr
)
396 return ((addr
) | (CORE_ADDR
) 1);
399 /* Extern version of unmake_compact_addr; we use a separate function
400 so that unmake_compact_addr can be inlined throughout this file. */
403 mips_unmake_compact_addr (CORE_ADDR addr
)
405 return unmake_compact_addr (addr
);
408 /* Functions for setting and testing a bit in a minimal symbol that
409 marks it as MIPS16 or microMIPS function. The MSB of the minimal
410 symbol's "info" field is used for this purpose.
412 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is
413 "special", i.e. refers to a MIPS16 or microMIPS function, and sets
414 one of the "special" bits in a minimal symbol to mark it accordingly.
415 The test checks an ELF-private flag that is valid for true function
416 symbols only; for synthetic symbols such as for PLT stubs that have
417 no ELF-private part at all the MIPS BFD backend arranges for this
418 information to be carried in the asymbol's udata field instead.
420 msymbol_is_mips16 and msymbol_is_micromips test the "special" bit
421 in a minimal symbol. */
424 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
426 elf_symbol_type
*elfsym
= (elf_symbol_type
*) sym
;
427 unsigned char st_other
;
429 if ((sym
->flags
& BSF_SYNTHETIC
) == 0)
430 st_other
= elfsym
->internal_elf_sym
.st_other
;
431 else if ((sym
->flags
& BSF_FUNCTION
) != 0)
432 st_other
= sym
->udata
.i
;
436 if (ELF_ST_IS_MICROMIPS (st_other
))
438 SET_MSYMBOL_TARGET_FLAG_MICROMIPS (msym
);
439 msym
->set_value_address (msym
->value_raw_address () | 1);
441 else if (ELF_ST_IS_MIPS16 (st_other
))
443 SET_MSYMBOL_TARGET_FLAG_MIPS16 (msym
);
444 msym
->set_value_address (msym
->value_raw_address () | 1);
448 /* Return one iff MSYM refers to standard ISA code. */
451 msymbol_is_mips (struct minimal_symbol
*msym
)
453 return !(MSYMBOL_TARGET_FLAG_MIPS16 (msym
)
454 || MSYMBOL_TARGET_FLAG_MICROMIPS (msym
));
457 /* Return one iff MSYM refers to MIPS16 code. */
460 msymbol_is_mips16 (struct minimal_symbol
*msym
)
462 return MSYMBOL_TARGET_FLAG_MIPS16 (msym
);
465 /* Return one iff MSYM refers to microMIPS code. */
468 msymbol_is_micromips (struct minimal_symbol
*msym
)
470 return MSYMBOL_TARGET_FLAG_MICROMIPS (msym
);
473 /* Set the ISA bit in the main symbol too, complementing the corresponding
474 minimal symbol setting and reflecting the run-time value of the symbol.
475 The need for comes from the ISA bit having been cleared as code in
476 `_bfd_mips_elf_symbol_processing' separated it into the ELF symbol's
477 `st_other' STO_MIPS16 or STO_MICROMIPS annotation, making the values
478 of symbols referring to compressed code different in GDB to the values
479 used by actual code. That in turn makes them evaluate incorrectly in
480 expressions, producing results different to what the same expressions
481 yield when compiled into the program being debugged. */
484 mips_make_symbol_special (struct symbol
*sym
, struct objfile
*objfile
)
486 if (sym
->aclass () == LOC_BLOCK
)
488 /* We are in symbol reading so it is OK to cast away constness. */
489 struct block
*block
= (struct block
*) sym
->value_block ();
490 CORE_ADDR compact_block_start
;
491 struct bound_minimal_symbol msym
;
493 compact_block_start
= block
->start () | 1;
494 msym
= lookup_minimal_symbol_by_pc (compact_block_start
);
495 if (msym
.minsym
&& !msymbol_is_mips (msym
.minsym
))
497 block
->set_start (compact_block_start
);
502 /* XFER a value from the big/little/left end of the register.
503 Depending on the size of the value it might occupy the entire
504 register or just part of it. Make an allowance for this, aligning
505 things accordingly. */
508 mips_xfer_register (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
509 int reg_num
, int length
,
510 enum bfd_endian endian
, gdb_byte
*in
,
511 const gdb_byte
*out
, int buf_offset
)
515 gdb_assert (reg_num
>= gdbarch_num_regs (gdbarch
));
516 /* Need to transfer the left or right part of the register, based on
517 the targets byte order. */
521 reg_offset
= register_size (gdbarch
, reg_num
) - length
;
523 case BFD_ENDIAN_LITTLE
:
526 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
530 internal_error (__FILE__
, __LINE__
, _("bad switch"));
533 gdb_printf (gdb_stderr
,
534 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
535 reg_num
, reg_offset
, buf_offset
, length
);
536 if (mips_debug
&& out
!= NULL
)
539 gdb_printf (gdb_stdlog
, "out ");
540 for (i
= 0; i
< length
; i
++)
541 gdb_printf (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
544 regcache
->cooked_read_part (reg_num
, reg_offset
, length
, in
+ buf_offset
);
546 regcache
->cooked_write_part (reg_num
, reg_offset
, length
, out
+ buf_offset
);
547 if (mips_debug
&& in
!= NULL
)
550 gdb_printf (gdb_stdlog
, "in ");
551 for (i
= 0; i
< length
; i
++)
552 gdb_printf (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
555 gdb_printf (gdb_stdlog
, "\n");
558 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
559 compatiblity mode. A return value of 1 means that we have
560 physical 64-bit registers, but should treat them as 32-bit registers. */
563 mips2_fp_compat (struct frame_info
*frame
)
565 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
566 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
568 if (register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) == 4)
572 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
573 in all the places we deal with FP registers. PR gdb/413. */
574 /* Otherwise check the FR bit in the status register - it controls
575 the FP compatiblity mode. If it is clear we are in compatibility
577 if ((get_frame_register_unsigned (frame
, MIPS_PS_REGNUM
) & ST0_FR
) == 0)
584 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
586 static CORE_ADDR
heuristic_proc_start (struct gdbarch
*, CORE_ADDR
);
588 /* The list of available "set mips " and "show mips " commands. */
590 static struct cmd_list_element
*setmipscmdlist
= NULL
;
591 static struct cmd_list_element
*showmipscmdlist
= NULL
;
593 /* Integer registers 0 thru 31 are handled explicitly by
594 mips_register_name(). Processor specific registers 32 and above
595 are listed in the following tables. */
598 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
602 static const char * const mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
603 "sr", "lo", "hi", "bad", "cause", "pc",
604 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
605 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
606 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
607 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
611 /* Names of tx39 registers. */
613 static const char * const mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
614 "sr", "lo", "hi", "bad", "cause", "pc",
615 "", "", "", "", "", "", "", "",
616 "", "", "", "", "", "", "", "",
617 "", "", "", "", "", "", "", "",
618 "", "", "", "", "", "", "", "",
620 "", "", "", "", "", "", "", "",
621 "", "", "config", "cache", "debug", "depc", "epc",
624 /* Names of registers with Linux kernels. */
625 static const char * const mips_linux_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
626 "sr", "lo", "hi", "bad", "cause", "pc",
627 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
628 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
629 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
630 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
635 /* Return the name of the register corresponding to REGNO. */
637 mips_register_name (struct gdbarch
*gdbarch
, int regno
)
639 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
640 /* GPR names for all ABIs other than n32/n64. */
641 static const char *mips_gpr_names
[] = {
642 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
643 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
644 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
645 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
648 /* GPR names for n32 and n64 ABIs. */
649 static const char *mips_n32_n64_gpr_names
[] = {
650 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
651 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
652 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
653 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
656 enum mips_abi abi
= mips_abi (gdbarch
);
658 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
659 but then don't make the raw register names visible. This (upper)
660 range of user visible register numbers are the pseudo-registers.
662 This approach was adopted accommodate the following scenario:
663 It is possible to debug a 64-bit device using a 32-bit
664 programming model. In such instances, the raw registers are
665 configured to be 64-bits wide, while the pseudo registers are
666 configured to be 32-bits wide. The registers that the user
667 sees - the pseudo registers - match the users expectations
668 given the programming model being used. */
669 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
670 if (regno
< gdbarch_num_regs (gdbarch
))
673 /* The MIPS integer registers are always mapped from 0 to 31. The
674 names of the registers (which reflects the conventions regarding
675 register use) vary depending on the ABI. */
676 if (0 <= rawnum
&& rawnum
< 32)
678 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
679 return mips_n32_n64_gpr_names
[rawnum
];
681 return mips_gpr_names
[rawnum
];
683 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
684 return tdesc_register_name (gdbarch
, rawnum
);
685 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (gdbarch
))
687 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
688 if (tdep
->mips_processor_reg_names
[rawnum
- 32])
689 return tdep
->mips_processor_reg_names
[rawnum
- 32];
693 internal_error (__FILE__
, __LINE__
,
694 _("mips_register_name: bad register number %d"), rawnum
);
697 /* Return the groups that a MIPS register can be categorised into. */
700 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
701 const struct reggroup
*reggroup
)
706 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
707 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
708 if (reggroup
== all_reggroup
)
710 vector_p
= register_type (gdbarch
, regnum
)->is_vector ();
711 float_p
= register_type (gdbarch
, regnum
)->code () == TYPE_CODE_FLT
;
712 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
713 (gdbarch), as not all architectures are multi-arch. */
714 raw_p
= rawnum
< gdbarch_num_regs (gdbarch
);
715 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
716 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
718 if (reggroup
== float_reggroup
)
719 return float_p
&& pseudo
;
720 if (reggroup
== vector_reggroup
)
721 return vector_p
&& pseudo
;
722 if (reggroup
== general_reggroup
)
723 return (!vector_p
&& !float_p
) && pseudo
;
724 /* Save the pseudo registers. Need to make certain that any code
725 extracting register values from a saved register cache also uses
727 if (reggroup
== save_reggroup
)
728 return raw_p
&& pseudo
;
729 /* Restore the same pseudo register. */
730 if (reggroup
== restore_reggroup
)
731 return raw_p
&& pseudo
;
735 /* Return the groups that a MIPS register can be categorised into.
736 This version is only used if we have a target description which
737 describes real registers (and their groups). */
740 mips_tdesc_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
741 const struct reggroup
*reggroup
)
743 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
744 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
747 /* Only save, restore, and display the pseudo registers. Need to
748 make certain that any code extracting register values from a
749 saved register cache also uses pseudo registers.
751 Note: saving and restoring the pseudo registers is slightly
752 strange; if we have 64 bits, we should save and restore all
753 64 bits. But this is hard and has little benefit. */
757 ret
= tdesc_register_in_reggroup_p (gdbarch
, rawnum
, reggroup
);
761 return mips_register_reggroup_p (gdbarch
, regnum
, reggroup
);
764 /* Map the symbol table registers which live in the range [1 *
765 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
766 registers. Take care of alignment and size problems. */
768 static enum register_status
769 mips_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
770 int cookednum
, gdb_byte
*buf
)
772 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
773 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
774 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
775 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
776 return regcache
->raw_read (rawnum
, buf
);
777 else if (register_size (gdbarch
, rawnum
) >
778 register_size (gdbarch
, cookednum
))
780 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
782 if (tdep
->mips64_transfers_32bit_regs_p
)
783 return regcache
->raw_read_part (rawnum
, 0, 4, buf
);
786 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
788 enum register_status status
;
790 status
= regcache
->raw_read (rawnum
, ®val
);
791 if (status
== REG_VALID
)
792 store_signed_integer (buf
, 4, byte_order
, regval
);
797 internal_error (__FILE__
, __LINE__
, _("bad register size"));
801 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
802 struct regcache
*regcache
, int cookednum
,
805 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
806 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
807 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
808 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
809 regcache
->raw_write (rawnum
, buf
);
810 else if (register_size (gdbarch
, rawnum
) >
811 register_size (gdbarch
, cookednum
))
813 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
815 if (tdep
->mips64_transfers_32bit_regs_p
)
816 regcache
->raw_write_part (rawnum
, 0, 4, buf
);
819 /* Sign extend the shortened version of the register prior
820 to placing it in the raw register. This is required for
821 some mips64 parts in order to avoid unpredictable behavior. */
822 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
823 LONGEST regval
= extract_signed_integer (buf
, 4, byte_order
);
824 regcache_raw_write_signed (regcache
, rawnum
, regval
);
828 internal_error (__FILE__
, __LINE__
, _("bad register size"));
832 mips_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
833 struct agent_expr
*ax
, int reg
)
835 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
836 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
837 && reg
< 2 * gdbarch_num_regs (gdbarch
));
839 ax_reg_mask (ax
, rawnum
);
845 mips_ax_pseudo_register_push_stack (struct gdbarch
*gdbarch
,
846 struct agent_expr
*ax
, int reg
)
848 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
849 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
850 && reg
< 2 * gdbarch_num_regs (gdbarch
));
851 if (register_size (gdbarch
, rawnum
) >= register_size (gdbarch
, reg
))
855 if (register_size (gdbarch
, rawnum
) > register_size (gdbarch
, reg
))
857 mips_gdbarch_tdep
*tdep
858 = gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
860 if (!tdep
->mips64_transfers_32bit_regs_p
861 || gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_BIG
)
864 ax_simple (ax
, aop_lsh
);
867 ax_simple (ax
, aop_rsh_signed
);
871 internal_error (__FILE__
, __LINE__
, _("bad register size"));
876 /* Table to translate 3-bit register field to actual register number. */
877 static const signed char mips_reg3_to_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
879 /* Heuristic_proc_start may hunt through the text section for a long
880 time across a 2400 baud serial line. Allows the user to limit this
883 static int heuristic_fence_post
= 0;
885 /* Number of bytes of storage in the actual machine representation for
886 register N. NOTE: This defines the pseudo register type so need to
887 rebuild the architecture vector. */
889 static bool mips64_transfers_32bit_regs_p
= false;
892 set_mips64_transfers_32bit_regs (const char *args
, int from_tty
,
893 struct cmd_list_element
*c
)
895 struct gdbarch_info info
;
896 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
897 instead of relying on globals. Doing that would let generic code
898 handle the search for this specific architecture. */
899 if (!gdbarch_update_p (info
))
901 mips64_transfers_32bit_regs_p
= 0;
902 error (_("32-bit compatibility mode not supported"));
906 /* Convert to/from a register and the corresponding memory value. */
908 /* This predicate tests for the case of an 8 byte floating point
909 value that is being transferred to or from a pair of floating point
910 registers each of which are (or are considered to be) only 4 bytes
913 mips_convert_register_float_case_p (struct gdbarch
*gdbarch
, int regnum
,
916 return (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
917 && register_size (gdbarch
, regnum
) == 4
918 && mips_float_register_p (gdbarch
, regnum
)
919 && type
->code () == TYPE_CODE_FLT
&& type
->length () == 8);
922 /* This predicate tests for the case of a value of less than 8
923 bytes in width that is being transfered to or from an 8 byte
924 general purpose register. */
926 mips_convert_register_gpreg_case_p (struct gdbarch
*gdbarch
, int regnum
,
929 int num_regs
= gdbarch_num_regs (gdbarch
);
931 return (register_size (gdbarch
, regnum
) == 8
932 && regnum
% num_regs
> 0 && regnum
% num_regs
< 32
933 && type
->length () < 8);
937 mips_convert_register_p (struct gdbarch
*gdbarch
,
938 int regnum
, struct type
*type
)
940 return (mips_convert_register_float_case_p (gdbarch
, regnum
, type
)
941 || mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
));
945 mips_register_to_value (struct frame_info
*frame
, int regnum
,
946 struct type
*type
, gdb_byte
*to
,
947 int *optimizedp
, int *unavailablep
)
949 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
951 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
953 get_frame_register (frame
, regnum
+ 0, to
+ 4);
954 get_frame_register (frame
, regnum
+ 1, to
+ 0);
956 if (!get_frame_register_bytes (frame
, regnum
+ 0, 0, {to
+ 4, 4},
957 optimizedp
, unavailablep
))
960 if (!get_frame_register_bytes (frame
, regnum
+ 1, 0, {to
+ 0, 4},
961 optimizedp
, unavailablep
))
963 *optimizedp
= *unavailablep
= 0;
966 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
968 size_t len
= type
->length ();
971 offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 8 - len
: 0;
972 if (!get_frame_register_bytes (frame
, regnum
, offset
, {to
, len
},
973 optimizedp
, unavailablep
))
976 *optimizedp
= *unavailablep
= 0;
981 internal_error (__FILE__
, __LINE__
,
982 _("mips_register_to_value: unrecognized case"));
987 mips_value_to_register (struct frame_info
*frame
, int regnum
,
988 struct type
*type
, const gdb_byte
*from
)
990 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
992 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
994 put_frame_register (frame
, regnum
+ 0, from
+ 4);
995 put_frame_register (frame
, regnum
+ 1, from
+ 0);
997 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
1000 size_t len
= type
->length ();
1002 /* Sign extend values, irrespective of type, that are stored to
1003 a 64-bit general purpose register. (32-bit unsigned values
1004 are stored as signed quantities within a 64-bit register.
1005 When performing an operation, in compiled code, that combines
1006 a 32-bit unsigned value with a signed 64-bit value, a type
1007 conversion is first performed that zeroes out the high 32 bits.) */
1008 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1011 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, -1);
1013 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, 0);
1014 put_frame_register_bytes (frame
, regnum
, 0, {fill
, 8 - len
});
1015 put_frame_register_bytes (frame
, regnum
, 8 - len
, {from
, len
});
1019 if (from
[len
-1] & 0x80)
1020 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, -1);
1022 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, 0);
1023 put_frame_register_bytes (frame
, regnum
, 0, {from
, len
});
1024 put_frame_register_bytes (frame
, regnum
, len
, {fill
, 8 - len
});
1029 internal_error (__FILE__
, __LINE__
,
1030 _("mips_value_to_register: unrecognized case"));
1034 /* Return the GDB type object for the "standard" data type of data in
1037 static struct type
*
1038 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
1040 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (gdbarch
));
1041 if (mips_float_register_p (gdbarch
, regnum
))
1043 /* The floating-point registers raw, or cooked, always match
1044 mips_isa_regsize(), and also map 1:1, byte for byte. */
1045 if (mips_isa_regsize (gdbarch
) == 4)
1046 return builtin_type (gdbarch
)->builtin_float
;
1048 return builtin_type (gdbarch
)->builtin_double
;
1050 else if (regnum
< gdbarch_num_regs (gdbarch
))
1052 /* The raw or ISA registers. These are all sized according to
1054 if (mips_isa_regsize (gdbarch
) == 4)
1055 return builtin_type (gdbarch
)->builtin_int32
;
1057 return builtin_type (gdbarch
)->builtin_int64
;
1061 int rawnum
= regnum
- gdbarch_num_regs (gdbarch
);
1062 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
1064 /* The cooked or ABI registers. These are sized according to
1065 the ABI (with a few complications). */
1066 if (rawnum
== mips_regnum (gdbarch
)->fp_control_status
1067 || rawnum
== mips_regnum (gdbarch
)->fp_implementation_revision
)
1068 return builtin_type (gdbarch
)->builtin_int32
;
1069 else if (gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
1070 && rawnum
>= MIPS_FIRST_EMBED_REGNUM
1071 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
1072 /* The pseudo/cooked view of the embedded registers is always
1073 32-bit. The raw view is handled below. */
1074 return builtin_type (gdbarch
)->builtin_int32
;
1075 else if (tdep
->mips64_transfers_32bit_regs_p
)
1076 /* The target, while possibly using a 64-bit register buffer,
1077 is only transfering 32-bits of each integer register.
1078 Reflect this in the cooked/pseudo (ABI) register value. */
1079 return builtin_type (gdbarch
)->builtin_int32
;
1080 else if (mips_abi_regsize (gdbarch
) == 4)
1081 /* The ABI is restricted to 32-bit registers (the ISA could be
1083 return builtin_type (gdbarch
)->builtin_int32
;
1086 return builtin_type (gdbarch
)->builtin_int64
;
1090 /* Return the GDB type for the pseudo register REGNUM, which is the
1091 ABI-level view. This function is only called if there is a target
1092 description which includes registers, so we know precisely the
1093 types of hardware registers. */
1095 static struct type
*
1096 mips_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
1098 const int num_regs
= gdbarch_num_regs (gdbarch
);
1099 int rawnum
= regnum
% num_regs
;
1100 struct type
*rawtype
;
1102 gdb_assert (regnum
>= num_regs
&& regnum
< 2 * num_regs
);
1104 /* Absent registers are still absent. */
1105 rawtype
= gdbarch_register_type (gdbarch
, rawnum
);
1106 if (rawtype
->length () == 0)
1109 /* Present the floating point registers however the hardware did;
1110 do not try to convert between FPU layouts. */
1111 if (mips_float_register_p (gdbarch
, rawnum
))
1114 /* Floating-point control registers are always 32-bit even though for
1115 backwards compatibility reasons 64-bit targets will transfer them
1116 as 64-bit quantities even if using XML descriptions. */
1117 if (rawnum
== mips_regnum (gdbarch
)->fp_control_status
1118 || rawnum
== mips_regnum (gdbarch
)->fp_implementation_revision
)
1119 return builtin_type (gdbarch
)->builtin_int32
;
1121 /* Use pointer types for registers if we can. For n32 we can not,
1122 since we do not have a 64-bit pointer type. */
1123 if (mips_abi_regsize (gdbarch
)
1124 == builtin_type (gdbarch
)->builtin_data_ptr
->length())
1126 if (rawnum
== MIPS_SP_REGNUM
1127 || rawnum
== mips_regnum (gdbarch
)->badvaddr
)
1128 return builtin_type (gdbarch
)->builtin_data_ptr
;
1129 else if (rawnum
== mips_regnum (gdbarch
)->pc
)
1130 return builtin_type (gdbarch
)->builtin_func_ptr
;
1133 if (mips_abi_regsize (gdbarch
) == 4 && rawtype
->length () == 8
1134 && ((rawnum
>= MIPS_ZERO_REGNUM
&& rawnum
<= MIPS_PS_REGNUM
)
1135 || rawnum
== mips_regnum (gdbarch
)->lo
1136 || rawnum
== mips_regnum (gdbarch
)->hi
1137 || rawnum
== mips_regnum (gdbarch
)->badvaddr
1138 || rawnum
== mips_regnum (gdbarch
)->cause
1139 || rawnum
== mips_regnum (gdbarch
)->pc
1140 || (mips_regnum (gdbarch
)->dspacc
!= -1
1141 && rawnum
>= mips_regnum (gdbarch
)->dspacc
1142 && rawnum
< mips_regnum (gdbarch
)->dspacc
+ 6)))
1143 return builtin_type (gdbarch
)->builtin_int32
;
1145 /* The pseudo/cooked view of embedded registers is always
1146 32-bit, even if the target transfers 64-bit values for them.
1147 New targets relying on XML descriptions should only transfer
1148 the necessary 32 bits, but older versions of GDB expected 64,
1149 so allow the target to provide 64 bits without interfering
1150 with the displayed type. */
1151 if (gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
1152 && rawnum
>= MIPS_FIRST_EMBED_REGNUM
1153 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
1154 return builtin_type (gdbarch
)->builtin_int32
;
1156 /* For all other registers, pass through the hardware type. */
1160 /* Should the upper word of 64-bit addresses be zeroed? */
1161 static enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
1164 mips_mask_address_p (mips_gdbarch_tdep
*tdep
)
1166 switch (mask_address_var
)
1168 case AUTO_BOOLEAN_TRUE
:
1170 case AUTO_BOOLEAN_FALSE
:
1173 case AUTO_BOOLEAN_AUTO
:
1174 return tdep
->default_mask_address_p
;
1176 internal_error (__FILE__
, __LINE__
,
1177 _("mips_mask_address_p: bad switch"));
1183 show_mask_address (struct ui_file
*file
, int from_tty
,
1184 struct cmd_list_element
*c
, const char *value
)
1186 const char *additional_text
= "";
1187 if (mask_address_var
== AUTO_BOOLEAN_AUTO
)
1189 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_mips
)
1190 additional_text
= _(" (current architecture is not MIPS)");
1193 mips_gdbarch_tdep
*tdep
1194 = gdbarch_tdep
<mips_gdbarch_tdep
> (target_gdbarch ());
1196 if (mips_mask_address_p (tdep
))
1197 additional_text
= _(" (currently \"on\")");
1199 additional_text
= _(" (currently \"off\")");
1203 gdb_printf (file
, _("Zeroing of upper 32 bits of 64-bit addresses is \"%s\"%s.\n"),
1204 value
, additional_text
);
1207 /* Tell if the program counter value in MEMADDR is in a standard ISA
1211 mips_pc_is_mips (CORE_ADDR memaddr
)
1213 struct bound_minimal_symbol sym
;
1215 /* Flags indicating that this is a MIPS16 or microMIPS function is
1216 stored by elfread.c in the high bit of the info field. Use this
1217 to decide if the function is standard MIPS. Otherwise if bit 0
1218 of the address is clear, then this is a standard MIPS function. */
1219 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1221 return msymbol_is_mips (sym
.minsym
);
1223 return is_mips_addr (memaddr
);
1226 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
1229 mips_pc_is_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1231 struct bound_minimal_symbol sym
;
1233 /* A flag indicating that this is a MIPS16 function is stored by
1234 elfread.c in the high bit of the info field. Use this to decide
1235 if the function is MIPS16. Otherwise if bit 0 of the address is
1236 set, then ELF file flags will tell if this is a MIPS16 function. */
1237 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1239 return msymbol_is_mips16 (sym
.minsym
);
1241 return is_mips16_addr (gdbarch
, memaddr
);
1244 /* Tell if the program counter value in MEMADDR is in a microMIPS function. */
1247 mips_pc_is_micromips (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1249 struct bound_minimal_symbol sym
;
1251 /* A flag indicating that this is a microMIPS function is stored by
1252 elfread.c in the high bit of the info field. Use this to decide
1253 if the function is microMIPS. Otherwise if bit 0 of the address
1254 is set, then ELF file flags will tell if this is a microMIPS
1256 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1258 return msymbol_is_micromips (sym
.minsym
);
1260 return is_micromips_addr (gdbarch
, memaddr
);
1263 /* Tell the ISA type of the function the program counter value in MEMADDR
1266 static enum mips_isa
1267 mips_pc_isa (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1269 struct bound_minimal_symbol sym
;
1271 /* A flag indicating that this is a MIPS16 or a microMIPS function
1272 is stored by elfread.c in the high bit of the info field. Use
1273 this to decide if the function is MIPS16 or microMIPS or normal
1274 MIPS. Otherwise if bit 0 of the address is set, then ELF file
1275 flags will tell if this is a MIPS16 or a microMIPS function. */
1276 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1279 if (msymbol_is_micromips (sym
.minsym
))
1280 return ISA_MICROMIPS
;
1281 else if (msymbol_is_mips16 (sym
.minsym
))
1288 if (is_mips_addr (memaddr
))
1290 else if (is_micromips_addr (gdbarch
, memaddr
))
1291 return ISA_MICROMIPS
;
1297 /* Set the ISA bit correctly in the PC, used by DWARF-2 machinery.
1298 The need for comes from the ISA bit having been cleared, making
1299 addresses in FDE, range records, etc. referring to compressed code
1300 different to those in line information, the symbol table and finally
1301 the PC register. That in turn confuses many operations. */
1304 mips_adjust_dwarf2_addr (CORE_ADDR pc
)
1306 pc
= unmake_compact_addr (pc
);
1307 return mips_pc_is_mips (pc
) ? pc
: make_compact_addr (pc
);
1310 /* Recalculate the line record requested so that the resulting PC has
1311 the ISA bit set correctly, used by DWARF-2 machinery. The need for
1312 this adjustment comes from some records associated with compressed
1313 code having the ISA bit cleared, most notably at function prologue
1314 ends. The ISA bit is in this context retrieved from the minimal
1315 symbol covering the address requested, which in turn has been
1316 constructed from the binary's symbol table rather than DWARF-2
1317 information. The correct setting of the ISA bit is required for
1318 breakpoint addresses to correctly match against the stop PC.
1320 As line entries can specify relative address adjustments we need to
1321 keep track of the absolute value of the last line address recorded
1322 in line information, so that we can calculate the actual address to
1323 apply the ISA bit adjustment to. We use PC for this tracking and
1324 keep the original address there.
1326 As such relative address adjustments can be odd within compressed
1327 code we need to keep track of the last line address with the ISA
1328 bit adjustment applied too, as the original address may or may not
1329 have had the ISA bit set. We use ADJ_PC for this tracking and keep
1330 the adjusted address there.
1332 For relative address adjustments we then use these variables to
1333 calculate the address intended by line information, which will be
1334 PC-relative, and return an updated adjustment carrying ISA bit
1335 information, which will be ADJ_PC-relative. For absolute address
1336 adjustments we just return the same address that we store in ADJ_PC
1339 As the first line entry can be relative to an implied address value
1340 of 0 we need to have the initial address set up that we store in PC
1341 and ADJ_PC. This is arranged with a call from `dwarf_decode_lines_1'
1342 that sets PC to 0 and ADJ_PC accordingly, usually 0 as well. */
1345 mips_adjust_dwarf2_line (CORE_ADDR addr
, int rel
)
1347 static CORE_ADDR adj_pc
;
1348 static CORE_ADDR pc
;
1351 pc
= rel
? pc
+ addr
: addr
;
1352 isa_pc
= mips_adjust_dwarf2_addr (pc
);
1353 addr
= rel
? isa_pc
- adj_pc
: isa_pc
;
1358 /* Various MIPS16 thunk (aka stub or trampoline) names. */
1360 static const char mips_str_mips16_call_stub
[] = "__mips16_call_stub_";
1361 static const char mips_str_mips16_ret_stub
[] = "__mips16_ret_";
1362 static const char mips_str_call_fp_stub
[] = "__call_stub_fp_";
1363 static const char mips_str_call_stub
[] = "__call_stub_";
1364 static const char mips_str_fn_stub
[] = "__fn_stub_";
1366 /* This is used as a PIC thunk prefix. */
1368 static const char mips_str_pic
[] = ".pic.";
1370 /* Return non-zero if the PC is inside a call thunk (aka stub or
1371 trampoline) that should be treated as a temporary frame. */
1374 mips_in_frame_stub (CORE_ADDR pc
)
1376 CORE_ADDR start_addr
;
1379 /* Find the starting address of the function containing the PC. */
1380 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
1383 /* If the PC is in __mips16_call_stub_*, this is a call/return stub. */
1384 if (startswith (name
, mips_str_mips16_call_stub
))
1386 /* If the PC is in __call_stub_*, this is a call/return or a call stub. */
1387 if (startswith (name
, mips_str_call_stub
))
1389 /* If the PC is in __fn_stub_*, this is a call stub. */
1390 if (startswith (name
, mips_str_fn_stub
))
1393 return 0; /* Not a stub. */
1396 /* MIPS believes that the PC has a sign extended value. Perhaps the
1397 all registers should be sign extended for simplicity? */
1400 mips_read_pc (readable_regcache
*regcache
)
1402 int regnum
= gdbarch_pc_regnum (regcache
->arch ());
1405 regcache
->cooked_read (regnum
, &pc
);
1410 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1414 pc
= frame_unwind_register_signed (next_frame
, gdbarch_pc_regnum (gdbarch
));
1415 /* macro/2012-04-20: This hack skips over MIPS16 call thunks as
1416 intermediate frames. In this case we can get the caller's address
1417 from $ra, or if $ra contains an address within a thunk as well, then
1418 it must be in the return path of __mips16_call_stub_{s,d}{f,c}_{0..10}
1419 and thus the caller's address is in $s2. */
1420 if (frame_relative_level (next_frame
) >= 0 && mips_in_frame_stub (pc
))
1422 pc
= frame_unwind_register_signed
1423 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
1424 if (mips_in_frame_stub (pc
))
1425 pc
= frame_unwind_register_signed
1426 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
1432 mips_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1434 return frame_unwind_register_signed
1435 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
);
1438 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1439 dummy frame. The frame ID's base needs to match the TOS value
1440 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1443 static struct frame_id
1444 mips_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1446 return frame_id_build
1447 (get_frame_register_signed (this_frame
,
1448 gdbarch_num_regs (gdbarch
)
1450 get_frame_pc (this_frame
));
1453 /* Implement the "write_pc" gdbarch method. */
1456 mips_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1458 int regnum
= gdbarch_pc_regnum (regcache
->arch ());
1460 regcache_cooked_write_unsigned (regcache
, regnum
, pc
);
1463 /* Fetch and return instruction from the specified location. Handle
1464 MIPS16/microMIPS as appropriate. */
1467 mips_fetch_instruction (struct gdbarch
*gdbarch
,
1468 enum mips_isa isa
, CORE_ADDR addr
, int *errp
)
1470 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1471 gdb_byte buf
[MIPS_INSN32_SIZE
];
1479 instlen
= MIPS_INSN16_SIZE
;
1480 addr
= unmake_compact_addr (addr
);
1483 instlen
= MIPS_INSN32_SIZE
;
1486 internal_error (__FILE__
, __LINE__
, _("invalid ISA"));
1489 err
= target_read_memory (addr
, buf
, instlen
);
1495 memory_error (TARGET_XFER_E_IO
, addr
);
1498 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1501 /* These are the fields of 32 bit mips instructions. */
1502 #define mips32_op(x) (x >> 26)
1503 #define itype_op(x) (x >> 26)
1504 #define itype_rs(x) ((x >> 21) & 0x1f)
1505 #define itype_rt(x) ((x >> 16) & 0x1f)
1506 #define itype_immediate(x) (x & 0xffff)
1508 #define jtype_op(x) (x >> 26)
1509 #define jtype_target(x) (x & 0x03ffffff)
1511 #define rtype_op(x) (x >> 26)
1512 #define rtype_rs(x) ((x >> 21) & 0x1f)
1513 #define rtype_rt(x) ((x >> 16) & 0x1f)
1514 #define rtype_rd(x) ((x >> 11) & 0x1f)
1515 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1516 #define rtype_funct(x) (x & 0x3f)
1518 /* MicroMIPS instruction fields. */
1519 #define micromips_op(x) ((x) >> 10)
1521 /* 16-bit/32-bit-high-part instruction formats, B and S refer to the lowest
1522 bit and the size respectively of the field extracted. */
1523 #define b0s4_imm(x) ((x) & 0xf)
1524 #define b0s5_imm(x) ((x) & 0x1f)
1525 #define b0s5_reg(x) ((x) & 0x1f)
1526 #define b0s7_imm(x) ((x) & 0x7f)
1527 #define b0s10_imm(x) ((x) & 0x3ff)
1528 #define b1s4_imm(x) (((x) >> 1) & 0xf)
1529 #define b1s9_imm(x) (((x) >> 1) & 0x1ff)
1530 #define b2s3_cc(x) (((x) >> 2) & 0x7)
1531 #define b4s2_regl(x) (((x) >> 4) & 0x3)
1532 #define b5s5_op(x) (((x) >> 5) & 0x1f)
1533 #define b5s5_reg(x) (((x) >> 5) & 0x1f)
1534 #define b6s4_op(x) (((x) >> 6) & 0xf)
1535 #define b7s3_reg(x) (((x) >> 7) & 0x7)
1537 /* 32-bit instruction formats, B and S refer to the lowest bit and the size
1538 respectively of the field extracted. */
1539 #define b0s6_op(x) ((x) & 0x3f)
1540 #define b0s11_op(x) ((x) & 0x7ff)
1541 #define b0s12_imm(x) ((x) & 0xfff)
1542 #define b0s16_imm(x) ((x) & 0xffff)
1543 #define b0s26_imm(x) ((x) & 0x3ffffff)
1544 #define b6s10_ext(x) (((x) >> 6) & 0x3ff)
1545 #define b11s5_reg(x) (((x) >> 11) & 0x1f)
1546 #define b12s4_op(x) (((x) >> 12) & 0xf)
1548 /* Return the size in bytes of the instruction INSN encoded in the ISA
1552 mips_insn_size (enum mips_isa isa
, ULONGEST insn
)
1557 if ((micromips_op (insn
) & 0x4) == 0x4
1558 || (micromips_op (insn
) & 0x7) == 0x0)
1559 return 2 * MIPS_INSN16_SIZE
;
1561 return MIPS_INSN16_SIZE
;
1563 if ((insn
& 0xf800) == 0xf000)
1564 return 2 * MIPS_INSN16_SIZE
;
1566 return MIPS_INSN16_SIZE
;
1568 return MIPS_INSN32_SIZE
;
1570 internal_error (__FILE__
, __LINE__
, _("invalid ISA"));
1574 mips32_relative_offset (ULONGEST inst
)
1576 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
1579 /* Determine the address of the next instruction executed after the INST
1580 floating condition branch instruction at PC. COUNT specifies the
1581 number of the floating condition bits tested by the branch. */
1584 mips32_bc1_pc (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1585 ULONGEST inst
, CORE_ADDR pc
, int count
)
1587 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1588 int cnum
= (itype_rt (inst
) >> 2) & (count
- 1);
1589 int tf
= itype_rt (inst
) & 1;
1590 int mask
= (1 << count
) - 1;
1595 /* No way to handle; it'll most likely trap anyway. */
1598 fcs
= regcache_raw_get_unsigned (regcache
, fcsr
);
1599 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1601 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1602 pc
+= mips32_relative_offset (inst
);
1609 /* Return nonzero if the gdbarch is an Octeon series. */
1612 is_octeon (struct gdbarch
*gdbarch
)
1614 const struct bfd_arch_info
*info
= gdbarch_bfd_arch_info (gdbarch
);
1616 return (info
->mach
== bfd_mach_mips_octeon
1617 || info
->mach
== bfd_mach_mips_octeonp
1618 || info
->mach
== bfd_mach_mips_octeon2
);
1621 /* Return true if the OP represents the Octeon's BBIT instruction. */
1624 is_octeon_bbit_op (int op
, struct gdbarch
*gdbarch
)
1626 if (!is_octeon (gdbarch
))
1628 /* BBIT0 is encoded as LWC2: 110 010. */
1629 /* BBIT032 is encoded as LDC2: 110 110. */
1630 /* BBIT1 is encoded as SWC2: 111 010. */
1631 /* BBIT132 is encoded as SDC2: 111 110. */
1632 if (op
== 50 || op
== 54 || op
== 58 || op
== 62)
1638 /* Determine where to set a single step breakpoint while considering
1639 branch prediction. */
1642 mips32_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1644 struct gdbarch
*gdbarch
= regcache
->arch ();
1647 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
1648 op
= itype_op (inst
);
1649 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch
1653 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1664 goto greater_branch
;
1669 else if (op
== 17 && itype_rs (inst
) == 8)
1670 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1671 pc
= mips32_bc1_pc (gdbarch
, regcache
, inst
, pc
+ 4, 1);
1672 else if (op
== 17 && itype_rs (inst
) == 9
1673 && (itype_rt (inst
) & 2) == 0)
1674 /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */
1675 pc
= mips32_bc1_pc (gdbarch
, regcache
, inst
, pc
+ 4, 2);
1676 else if (op
== 17 && itype_rs (inst
) == 10
1677 && (itype_rt (inst
) & 2) == 0)
1678 /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */
1679 pc
= mips32_bc1_pc (gdbarch
, regcache
, inst
, pc
+ 4, 4);
1682 /* The new PC will be alternate mode. */
1686 reg
= jtype_target (inst
) << 2;
1687 /* Add 1 to indicate 16-bit mode -- invert ISA mode. */
1688 pc
= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + reg
+ 1;
1690 else if (is_octeon_bbit_op (op
, gdbarch
))
1694 branch_if
= op
== 58 || op
== 62;
1695 bit
= itype_rt (inst
);
1697 /* Take into account the *32 instructions. */
1698 if (op
== 54 || op
== 62)
1701 if (((regcache_raw_get_signed (regcache
,
1702 itype_rs (inst
)) >> bit
) & 1)
1704 pc
+= mips32_relative_offset (inst
) + 4;
1706 pc
+= 8; /* After the delay slot. */
1710 pc
+= 4; /* Not a branch, next instruction is easy. */
1713 { /* This gets way messy. */
1715 /* Further subdivide into SPECIAL, REGIMM and other. */
1716 switch (op
& 0x07) /* Extract bits 28,27,26. */
1718 case 0: /* SPECIAL */
1719 op
= rtype_funct (inst
);
1724 /* Set PC to that address. */
1725 pc
= regcache_raw_get_signed (regcache
, rtype_rs (inst
));
1727 case 12: /* SYSCALL */
1729 mips_gdbarch_tdep
*tdep
1730 = gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
1732 if (tdep
->syscall_next_pc
!= NULL
)
1733 pc
= tdep
->syscall_next_pc (get_current_frame ());
1742 break; /* end SPECIAL */
1743 case 1: /* REGIMM */
1745 op
= itype_rt (inst
); /* branch condition */
1750 case 16: /* BLTZAL */
1751 case 18: /* BLTZALL */
1753 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) < 0)
1754 pc
+= mips32_relative_offset (inst
) + 4;
1756 pc
+= 8; /* after the delay slot */
1760 case 17: /* BGEZAL */
1761 case 19: /* BGEZALL */
1762 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) >= 0)
1763 pc
+= mips32_relative_offset (inst
) + 4;
1765 pc
+= 8; /* after the delay slot */
1767 case 0x1c: /* BPOSGE32 */
1768 case 0x1e: /* BPOSGE64 */
1770 if (itype_rs (inst
) == 0)
1772 unsigned int pos
= (op
& 2) ? 64 : 32;
1773 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
1776 /* No way to handle; it'll most likely trap anyway. */
1779 if ((regcache_raw_get_unsigned (regcache
,
1780 dspctl
) & 0x7f) >= pos
)
1781 pc
+= mips32_relative_offset (inst
);
1786 /* All of the other instructions in the REGIMM category */
1791 break; /* end REGIMM */
1796 reg
= jtype_target (inst
) << 2;
1797 /* Upper four bits get never changed... */
1798 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1801 case 4: /* BEQ, BEQL */
1803 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) ==
1804 regcache_raw_get_signed (regcache
, itype_rt (inst
)))
1805 pc
+= mips32_relative_offset (inst
) + 4;
1809 case 5: /* BNE, BNEL */
1811 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) !=
1812 regcache_raw_get_signed (regcache
, itype_rt (inst
)))
1813 pc
+= mips32_relative_offset (inst
) + 4;
1817 case 6: /* BLEZ, BLEZL */
1818 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) <= 0)
1819 pc
+= mips32_relative_offset (inst
) + 4;
1825 greater_branch
: /* BGTZ, BGTZL */
1826 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) > 0)
1827 pc
+= mips32_relative_offset (inst
) + 4;
1834 } /* mips32_next_pc */
1836 /* Extract the 7-bit signed immediate offset from the microMIPS instruction
1840 micromips_relative_offset7 (ULONGEST insn
)
1842 return ((b0s7_imm (insn
) ^ 0x40) - 0x40) << 1;
1845 /* Extract the 10-bit signed immediate offset from the microMIPS instruction
1849 micromips_relative_offset10 (ULONGEST insn
)
1851 return ((b0s10_imm (insn
) ^ 0x200) - 0x200) << 1;
1854 /* Extract the 16-bit signed immediate offset from the microMIPS instruction
1858 micromips_relative_offset16 (ULONGEST insn
)
1860 return ((b0s16_imm (insn
) ^ 0x8000) - 0x8000) << 1;
1863 /* Return the size in bytes of the microMIPS instruction at the address PC. */
1866 micromips_pc_insn_size (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1870 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1871 return mips_insn_size (ISA_MICROMIPS
, insn
);
1874 /* Calculate the address of the next microMIPS instruction to execute
1875 after the INSN coprocessor 1 conditional branch instruction at the
1876 address PC. COUNT denotes the number of coprocessor condition bits
1877 examined by the branch. */
1880 micromips_bc1_pc (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1881 ULONGEST insn
, CORE_ADDR pc
, int count
)
1883 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1884 int cnum
= b2s3_cc (insn
>> 16) & (count
- 1);
1885 int tf
= b5s5_op (insn
>> 16) & 1;
1886 int mask
= (1 << count
) - 1;
1891 /* No way to handle; it'll most likely trap anyway. */
1894 fcs
= regcache_raw_get_unsigned (regcache
, fcsr
);
1895 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1897 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1898 pc
+= micromips_relative_offset16 (insn
);
1900 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1905 /* Calculate the address of the next microMIPS instruction to execute
1906 after the instruction at the address PC. */
1909 micromips_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1911 struct gdbarch
*gdbarch
= regcache
->arch ();
1914 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1915 pc
+= MIPS_INSN16_SIZE
;
1916 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
1918 /* 32-bit instructions. */
1919 case 2 * MIPS_INSN16_SIZE
:
1921 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1922 pc
+= MIPS_INSN16_SIZE
;
1923 switch (micromips_op (insn
>> 16))
1925 case 0x00: /* POOL32A: bits 000000 */
1926 switch (b0s6_op (insn
))
1928 case 0x3c: /* POOL32Axf: bits 000000 ... 111100 */
1929 switch (b6s10_ext (insn
))
1931 case 0x3c: /* JALR: 000000 0000111100 111100 */
1932 case 0x7c: /* JALR.HB: 000000 0001111100 111100 */
1933 case 0x13c: /* JALRS: 000000 0100111100 111100 */
1934 case 0x17c: /* JALRS.HB: 000000 0101111100 111100 */
1935 pc
= regcache_raw_get_signed (regcache
,
1936 b0s5_reg (insn
>> 16));
1938 case 0x22d: /* SYSCALL: 000000 1000101101 111100 */
1940 mips_gdbarch_tdep
*tdep
1941 = gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
1943 if (tdep
->syscall_next_pc
!= NULL
)
1944 pc
= tdep
->syscall_next_pc (get_current_frame ());
1952 case 0x10: /* POOL32I: bits 010000 */
1953 switch (b5s5_op (insn
>> 16))
1955 case 0x00: /* BLTZ: bits 010000 00000 */
1956 case 0x01: /* BLTZAL: bits 010000 00001 */
1957 case 0x11: /* BLTZALS: bits 010000 10001 */
1958 if (regcache_raw_get_signed (regcache
,
1959 b0s5_reg (insn
>> 16)) < 0)
1960 pc
+= micromips_relative_offset16 (insn
);
1962 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1965 case 0x02: /* BGEZ: bits 010000 00010 */
1966 case 0x03: /* BGEZAL: bits 010000 00011 */
1967 case 0x13: /* BGEZALS: bits 010000 10011 */
1968 if (regcache_raw_get_signed (regcache
,
1969 b0s5_reg (insn
>> 16)) >= 0)
1970 pc
+= micromips_relative_offset16 (insn
);
1972 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1975 case 0x04: /* BLEZ: bits 010000 00100 */
1976 if (regcache_raw_get_signed (regcache
,
1977 b0s5_reg (insn
>> 16)) <= 0)
1978 pc
+= micromips_relative_offset16 (insn
);
1980 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1983 case 0x05: /* BNEZC: bits 010000 00101 */
1984 if (regcache_raw_get_signed (regcache
,
1985 b0s5_reg (insn
>> 16)) != 0)
1986 pc
+= micromips_relative_offset16 (insn
);
1989 case 0x06: /* BGTZ: bits 010000 00110 */
1990 if (regcache_raw_get_signed (regcache
,
1991 b0s5_reg (insn
>> 16)) > 0)
1992 pc
+= micromips_relative_offset16 (insn
);
1994 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1997 case 0x07: /* BEQZC: bits 010000 00111 */
1998 if (regcache_raw_get_signed (regcache
,
1999 b0s5_reg (insn
>> 16)) == 0)
2000 pc
+= micromips_relative_offset16 (insn
);
2003 case 0x14: /* BC2F: bits 010000 10100 xxx00 */
2004 case 0x15: /* BC2T: bits 010000 10101 xxx00 */
2005 if (((insn
>> 16) & 0x3) == 0x0)
2006 /* BC2F, BC2T: don't know how to handle these. */
2010 case 0x1a: /* BPOSGE64: bits 010000 11010 */
2011 case 0x1b: /* BPOSGE32: bits 010000 11011 */
2013 unsigned int pos
= (b5s5_op (insn
>> 16) & 1) ? 32 : 64;
2014 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
2017 /* No way to handle; it'll most likely trap anyway. */
2020 if ((regcache_raw_get_unsigned (regcache
,
2021 dspctl
) & 0x7f) >= pos
)
2022 pc
+= micromips_relative_offset16 (insn
);
2024 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2028 case 0x1c: /* BC1F: bits 010000 11100 xxx00 */
2029 /* BC1ANY2F: bits 010000 11100 xxx01 */
2030 case 0x1d: /* BC1T: bits 010000 11101 xxx00 */
2031 /* BC1ANY2T: bits 010000 11101 xxx01 */
2032 if (((insn
>> 16) & 0x2) == 0x0)
2033 pc
= micromips_bc1_pc (gdbarch
, regcache
, insn
, pc
,
2034 ((insn
>> 16) & 0x1) + 1);
2037 case 0x1e: /* BC1ANY4F: bits 010000 11110 xxx01 */
2038 case 0x1f: /* BC1ANY4T: bits 010000 11111 xxx01 */
2039 if (((insn
>> 16) & 0x3) == 0x1)
2040 pc
= micromips_bc1_pc (gdbarch
, regcache
, insn
, pc
, 4);
2045 case 0x1d: /* JALS: bits 011101 */
2046 case 0x35: /* J: bits 110101 */
2047 case 0x3d: /* JAL: bits 111101 */
2048 pc
= ((pc
| 0x7fffffe) ^ 0x7fffffe) | (b0s26_imm (insn
) << 1);
2051 case 0x25: /* BEQ: bits 100101 */
2052 if (regcache_raw_get_signed (regcache
, b0s5_reg (insn
>> 16))
2053 == regcache_raw_get_signed (regcache
, b5s5_reg (insn
>> 16)))
2054 pc
+= micromips_relative_offset16 (insn
);
2056 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2059 case 0x2d: /* BNE: bits 101101 */
2060 if (regcache_raw_get_signed (regcache
, b0s5_reg (insn
>> 16))
2061 != regcache_raw_get_signed (regcache
, b5s5_reg (insn
>> 16)))
2062 pc
+= micromips_relative_offset16 (insn
);
2064 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2067 case 0x3c: /* JALX: bits 111100 */
2068 pc
= ((pc
| 0xfffffff) ^ 0xfffffff) | (b0s26_imm (insn
) << 2);
2073 /* 16-bit instructions. */
2074 case MIPS_INSN16_SIZE
:
2075 switch (micromips_op (insn
))
2077 case 0x11: /* POOL16C: bits 010001 */
2078 if ((b5s5_op (insn
) & 0x1c) == 0xc)
2079 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
2080 pc
= regcache_raw_get_signed (regcache
, b0s5_reg (insn
));
2081 else if (b5s5_op (insn
) == 0x18)
2082 /* JRADDIUSP: bits 010001 11000 */
2083 pc
= regcache_raw_get_signed (regcache
, MIPS_RA_REGNUM
);
2086 case 0x23: /* BEQZ16: bits 100011 */
2088 int rs
= mips_reg3_to_reg
[b7s3_reg (insn
)];
2090 if (regcache_raw_get_signed (regcache
, rs
) == 0)
2091 pc
+= micromips_relative_offset7 (insn
);
2093 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2097 case 0x2b: /* BNEZ16: bits 101011 */
2099 int rs
= mips_reg3_to_reg
[b7s3_reg (insn
)];
2101 if (regcache_raw_get_signed (regcache
, rs
) != 0)
2102 pc
+= micromips_relative_offset7 (insn
);
2104 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2108 case 0x33: /* B16: bits 110011 */
2109 pc
+= micromips_relative_offset10 (insn
);
2118 /* Decoding the next place to set a breakpoint is irregular for the
2119 mips 16 variant, but fortunately, there fewer instructions. We have
2120 to cope ith extensions for 16 bit instructions and a pair of actual
2121 32 bit instructions. We dont want to set a single step instruction
2122 on the extend instruction either. */
2124 /* Lots of mips16 instruction formats */
2125 /* Predicting jumps requires itype,ritype,i8type
2126 and their extensions extItype,extritype,extI8type. */
2127 enum mips16_inst_fmts
2129 itype
, /* 0 immediate 5,10 */
2130 ritype
, /* 1 5,3,8 */
2131 rrtype
, /* 2 5,3,3,5 */
2132 rritype
, /* 3 5,3,3,5 */
2133 rrrtype
, /* 4 5,3,3,3,2 */
2134 rriatype
, /* 5 5,3,3,1,4 */
2135 shifttype
, /* 6 5,3,3,3,2 */
2136 i8type
, /* 7 5,3,8 */
2137 i8movtype
, /* 8 5,3,3,5 */
2138 i8mov32rtype
, /* 9 5,3,5,3 */
2139 i64type
, /* 10 5,3,8 */
2140 ri64type
, /* 11 5,3,3,5 */
2141 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
2142 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
2143 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
2144 extRRItype
, /* 15 5,5,5,5,3,3,5 */
2145 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
2146 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
2147 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
2148 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
2149 extRi64type
, /* 20 5,6,5,5,3,3,5 */
2150 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
2152 /* I am heaping all the fields of the formats into one structure and
2153 then, only the fields which are involved in instruction extension. */
2157 unsigned int regx
; /* Function in i8 type. */
2162 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
2163 for the bits which make up the immediate extension. */
2166 extended_offset (unsigned int extension
)
2170 value
= (extension
>> 16) & 0x1f; /* Extract 15:11. */
2172 value
|= (extension
>> 21) & 0x3f; /* Extract 10:5. */
2174 value
|= extension
& 0x1f; /* Extract 4:0. */
2179 /* Only call this function if you know that this is an extendable
2180 instruction. It won't malfunction, but why make excess remote memory
2181 references? If the immediate operands get sign extended or something,
2182 do it after the extension is performed. */
2183 /* FIXME: Every one of these cases needs to worry about sign extension
2184 when the offset is to be used in relative addressing. */
2187 fetch_mips_16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2189 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2192 pc
= unmake_compact_addr (pc
); /* Clear the low order bit. */
2193 target_read_memory (pc
, buf
, 2);
2194 return extract_unsigned_integer (buf
, 2, byte_order
);
2198 unpack_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
2199 unsigned int extension
,
2201 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
2206 switch (insn_format
)
2213 value
= extended_offset ((extension
<< 16) | inst
);
2214 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
2218 value
= inst
& 0x7ff;
2219 value
= (value
^ 0x400) - 0x400; /* Sign-extend. */
2228 { /* A register identifier and an offset. */
2229 /* Most of the fields are the same as I type but the
2230 immediate value is of a different length. */
2234 value
= extended_offset ((extension
<< 16) | inst
);
2235 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
2239 value
= inst
& 0xff; /* 8 bits */
2240 value
= (value
^ 0x80) - 0x80; /* Sign-extend. */
2243 regx
= (inst
>> 8) & 0x07; /* i8 funct */
2249 unsigned long value
;
2250 unsigned int nexthalf
;
2251 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
2252 value
= value
<< 16;
2253 nexthalf
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, pc
+ 2, NULL
);
2254 /* Low bit still set. */
2262 internal_error (__FILE__
, __LINE__
, _("bad switch"));
2264 upk
->offset
= offset
;
2270 /* Calculate the destination of a branch whose 16-bit opcode word is at PC,
2271 and having a signed 16-bit OFFSET. */
2274 add_offset_16 (CORE_ADDR pc
, int offset
)
2276 return pc
+ (offset
<< 1) + 2;
2280 extended_mips16_next_pc (regcache
*regcache
, CORE_ADDR pc
,
2281 unsigned int extension
, unsigned int insn
)
2283 struct gdbarch
*gdbarch
= regcache
->arch ();
2284 int op
= (insn
>> 11);
2287 case 2: /* Branch */
2289 struct upk_mips16 upk
;
2290 unpack_mips16 (gdbarch
, pc
, extension
, insn
, itype
, &upk
);
2291 pc
= add_offset_16 (pc
, upk
.offset
);
2294 case 3: /* JAL , JALX - Watch out, these are 32 bit
2297 struct upk_mips16 upk
;
2298 unpack_mips16 (gdbarch
, pc
, extension
, insn
, jalxtype
, &upk
);
2299 pc
= ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)) | (upk
.offset
<< 2);
2300 if ((insn
>> 10) & 0x01) /* Exchange mode */
2301 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode. */
2308 struct upk_mips16 upk
;
2310 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
2311 reg
= regcache_raw_get_signed (regcache
, mips_reg3_to_reg
[upk
.regx
]);
2313 pc
= add_offset_16 (pc
, upk
.offset
);
2320 struct upk_mips16 upk
;
2322 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
2323 reg
= regcache_raw_get_signed (regcache
, mips_reg3_to_reg
[upk
.regx
]);
2325 pc
= add_offset_16 (pc
, upk
.offset
);
2330 case 12: /* I8 Formats btez btnez */
2332 struct upk_mips16 upk
;
2334 unpack_mips16 (gdbarch
, pc
, extension
, insn
, i8type
, &upk
);
2335 /* upk.regx contains the opcode */
2336 /* Test register is 24 */
2337 reg
= regcache_raw_get_signed (regcache
, 24);
2338 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
2339 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
2340 pc
= add_offset_16 (pc
, upk
.offset
);
2345 case 29: /* RR Formats JR, JALR, JALR-RA */
2347 struct upk_mips16 upk
;
2348 /* upk.fmt = rrtype; */
2353 upk
.regx
= (insn
>> 8) & 0x07;
2354 upk
.regy
= (insn
>> 5) & 0x07;
2355 if ((upk
.regy
& 1) == 0)
2356 reg
= mips_reg3_to_reg
[upk
.regx
];
2358 reg
= 31; /* Function return instruction. */
2359 pc
= regcache_raw_get_signed (regcache
, reg
);
2366 /* This is an instruction extension. Fetch the real instruction
2367 (which follows the extension) and decode things based on
2371 pc
= extended_mips16_next_pc (regcache
, pc
, insn
,
2372 fetch_mips_16 (gdbarch
, pc
));
2385 mips16_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
2387 struct gdbarch
*gdbarch
= regcache
->arch ();
2388 unsigned int insn
= fetch_mips_16 (gdbarch
, pc
);
2389 return extended_mips16_next_pc (regcache
, pc
, 0, insn
);
2392 /* The mips_next_pc function supports single_step when the remote
2393 target monitor or stub is not developed enough to do a single_step.
2394 It works by decoding the current instruction and predicting where a
2395 branch will go. This isn't hard because all the data is available.
2396 The MIPS32, MIPS16 and microMIPS variants are quite different. */
2398 mips_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
2400 struct gdbarch
*gdbarch
= regcache
->arch ();
2402 if (mips_pc_is_mips16 (gdbarch
, pc
))
2403 return mips16_next_pc (regcache
, pc
);
2404 else if (mips_pc_is_micromips (gdbarch
, pc
))
2405 return micromips_next_pc (regcache
, pc
);
2407 return mips32_next_pc (regcache
, pc
);
2410 /* Return non-zero if the MIPS16 instruction INSN is a compact branch
2414 mips16_instruction_is_compact_branch (unsigned short insn
)
2416 switch (insn
& 0xf800)
2419 return (insn
& 0x009f) == 0x80; /* JALRC/JRC */
2421 return (insn
& 0x0600) == 0; /* BTNEZ/BTEQZ */
2422 case 0x2800: /* BNEZ */
2423 case 0x2000: /* BEQZ */
2424 case 0x1000: /* B */
2431 /* Return non-zero if the microMIPS instruction INSN is a compact branch
2435 micromips_instruction_is_compact_branch (unsigned short insn
)
2437 switch (micromips_op (insn
))
2439 case 0x11: /* POOL16C: bits 010001 */
2440 return (b5s5_op (insn
) == 0x18
2441 /* JRADDIUSP: bits 010001 11000 */
2442 || b5s5_op (insn
) == 0xd);
2443 /* JRC: bits 010011 01101 */
2444 case 0x10: /* POOL32I: bits 010000 */
2445 return (b5s5_op (insn
) & 0x1d) == 0x5;
2446 /* BEQZC/BNEZC: bits 010000 001x1 */
2452 struct mips_frame_cache
2455 trad_frame_saved_reg
*saved_regs
;
2458 /* Set a register's saved stack address in temp_saved_regs. If an
2459 address has already been set for this register, do nothing; this
2460 way we will only recognize the first save of a given register in a
2463 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
2464 [gdbarch_num_regs .. 2*gdbarch_num_regs).
2465 Strictly speaking, only the second range is used as it is only second
2466 range (the ABI instead of ISA registers) that comes into play when finding
2467 saved registers in a frame. */
2470 set_reg_offset (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
,
2471 int regnum
, CORE_ADDR offset
)
2473 if (this_cache
!= NULL
2474 && this_cache
->saved_regs
[regnum
].is_realreg ()
2475 && this_cache
->saved_regs
[regnum
].realreg () == regnum
)
2477 this_cache
->saved_regs
[regnum
+ 0
2478 * gdbarch_num_regs (gdbarch
)].set_addr (offset
);
2479 this_cache
->saved_regs
[regnum
+ 1
2480 * gdbarch_num_regs (gdbarch
)].set_addr (offset
);
2485 /* Fetch the immediate value from a MIPS16 instruction.
2486 If the previous instruction was an EXTEND, use it to extend
2487 the upper bits of the immediate value. This is a helper function
2488 for mips16_scan_prologue. */
2491 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
2492 unsigned short inst
, /* current instruction */
2493 int nbits
, /* number of bits in imm field */
2494 int scale
, /* scale factor to be applied to imm */
2495 int is_signed
) /* is the imm field signed? */
2499 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
2501 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
2502 if (offset
& 0x8000) /* check for negative extend */
2503 offset
= 0 - (0x10000 - (offset
& 0xffff));
2504 return offset
| (inst
& 0x1f);
2508 int max_imm
= 1 << nbits
;
2509 int mask
= max_imm
- 1;
2510 int sign_bit
= max_imm
>> 1;
2512 offset
= inst
& mask
;
2513 if (is_signed
&& (offset
& sign_bit
))
2514 offset
= 0 - (max_imm
- offset
);
2515 return offset
* scale
;
2520 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
2521 the associated FRAME_CACHE if not null.
2522 Return the address of the first instruction past the prologue. */
2525 mips16_scan_prologue (struct gdbarch
*gdbarch
,
2526 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2527 struct frame_info
*this_frame
,
2528 struct mips_frame_cache
*this_cache
)
2530 int prev_non_prologue_insn
= 0;
2531 int this_non_prologue_insn
;
2532 int non_prologue_insns
= 0;
2535 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer. */
2537 long frame_offset
= 0; /* Size of stack frame. */
2538 long frame_adjust
= 0; /* Offset of FP from SP. */
2539 int frame_reg
= MIPS_SP_REGNUM
;
2540 unsigned short prev_inst
= 0; /* saved copy of previous instruction. */
2541 unsigned inst
= 0; /* current instruction */
2542 unsigned entry_inst
= 0; /* the entry instruction */
2543 unsigned save_inst
= 0; /* the save instruction */
2544 int prev_delay_slot
= 0;
2548 int extend_bytes
= 0;
2549 int prev_extend_bytes
= 0;
2550 CORE_ADDR end_prologue_addr
;
2552 /* Can be called when there's no process, and hence when there's no
2554 if (this_frame
!= NULL
)
2555 sp
= get_frame_register_signed (this_frame
,
2556 gdbarch_num_regs (gdbarch
)
2561 if (limit_pc
> start_pc
+ 200)
2562 limit_pc
= start_pc
+ 200;
2565 /* Permit at most one non-prologue non-control-transfer instruction
2566 in the middle which may have been reordered by the compiler for
2568 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
2570 this_non_prologue_insn
= 0;
2573 /* Save the previous instruction. If it's an EXTEND, we'll extract
2574 the immediate offset extension from it in mips16_get_imm. */
2577 /* Fetch and decode the instruction. */
2578 inst
= (unsigned short) mips_fetch_instruction (gdbarch
, ISA_MIPS16
,
2581 /* Normally we ignore extend instructions. However, if it is
2582 not followed by a valid prologue instruction, then this
2583 instruction is not part of the prologue either. We must
2584 remember in this case to adjust the end_prologue_addr back
2586 if ((inst
& 0xf800) == 0xf000) /* extend */
2588 extend_bytes
= MIPS_INSN16_SIZE
;
2592 prev_extend_bytes
= extend_bytes
;
2595 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2596 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2598 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
2599 if (offset
< 0) /* Negative stack adjustment? */
2600 frame_offset
-= offset
;
2602 /* Exit loop if a positive stack adjustment is found, which
2603 usually means that the stack cleanup code in the function
2604 epilogue is reached. */
2607 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
2609 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2610 reg
= mips_reg3_to_reg
[(inst
& 0x700) >> 8];
2611 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2613 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
2615 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2616 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2617 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2619 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
2621 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2622 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2624 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2626 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
2627 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2629 else if (inst
== 0x673d) /* move $s1, $sp */
2634 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
2636 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2637 frame_addr
= sp
+ offset
;
2639 frame_adjust
= offset
;
2641 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2643 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
2644 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2645 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
2647 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2649 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2650 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2651 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
2653 else if ((inst
& 0xf81f) == 0xe809
2654 && (inst
& 0x700) != 0x700) /* entry */
2655 entry_inst
= inst
; /* Save for later processing. */
2656 else if ((inst
& 0xff80) == 0x6480) /* save */
2658 save_inst
= inst
; /* Save for later processing. */
2659 if (prev_extend_bytes
) /* extend */
2660 save_inst
|= prev_inst
<< 16;
2662 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
2664 /* This instruction is part of the prologue, but we don't
2665 need to do anything special to handle it. */
2667 else if (mips16_instruction_has_delay_slot (inst
, 0))
2668 /* JAL/JALR/JALX/JR */
2670 /* The instruction in the delay slot can be a part
2671 of the prologue, so move forward once more. */
2673 if (mips16_instruction_has_delay_slot (inst
, 1))
2676 prev_extend_bytes
= MIPS_INSN16_SIZE
;
2677 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
2682 this_non_prologue_insn
= 1;
2685 non_prologue_insns
+= this_non_prologue_insn
;
2687 /* A jump or branch, or enough non-prologue insns seen? If so,
2688 then we must have reached the end of the prologue by now. */
2689 if (prev_delay_slot
|| non_prologue_insns
> 1
2690 || mips16_instruction_is_compact_branch (inst
))
2693 prev_non_prologue_insn
= this_non_prologue_insn
;
2694 prev_delay_slot
= in_delay_slot
;
2695 prev_pc
= cur_pc
- prev_extend_bytes
;
2698 /* The entry instruction is typically the first instruction in a function,
2699 and it stores registers at offsets relative to the value of the old SP
2700 (before the prologue). But the value of the sp parameter to this
2701 function is the new SP (after the prologue has been executed). So we
2702 can't calculate those offsets until we've seen the entire prologue,
2703 and can calculate what the old SP must have been. */
2704 if (entry_inst
!= 0)
2706 int areg_count
= (entry_inst
>> 8) & 7;
2707 int sreg_count
= (entry_inst
>> 6) & 3;
2709 /* The entry instruction always subtracts 32 from the SP. */
2712 /* Now we can calculate what the SP must have been at the
2713 start of the function prologue. */
2716 /* Check if a0-a3 were saved in the caller's argument save area. */
2717 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
2719 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2720 offset
+= mips_abi_regsize (gdbarch
);
2723 /* Check if the ra register was pushed on the stack. */
2725 if (entry_inst
& 0x20)
2727 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2728 offset
-= mips_abi_regsize (gdbarch
);
2731 /* Check if the s0 and s1 registers were pushed on the stack. */
2732 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2734 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2735 offset
-= mips_abi_regsize (gdbarch
);
2739 /* The SAVE instruction is similar to ENTRY, except that defined by the
2740 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
2741 size of the frame is specified as an immediate field of instruction
2742 and an extended variation exists which lets additional registers and
2743 frame space to be specified. The instruction always treats registers
2744 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
2745 if (save_inst
!= 0 && mips_abi_regsize (gdbarch
) == 4)
2747 static int args_table
[16] = {
2748 0, 0, 0, 0, 1, 1, 1, 1,
2749 2, 2, 2, 0, 3, 3, 4, -1,
2751 static int astatic_table
[16] = {
2752 0, 1, 2, 3, 0, 1, 2, 3,
2753 0, 1, 2, 4, 0, 1, 0, -1,
2755 int aregs
= (save_inst
>> 16) & 0xf;
2756 int xsregs
= (save_inst
>> 24) & 0x7;
2757 int args
= args_table
[aregs
];
2758 int astatic
= astatic_table
[aregs
];
2763 warning (_("Invalid number of argument registers encoded in SAVE."));
2768 warning (_("Invalid number of static registers encoded in SAVE."));
2772 /* For standard SAVE the frame size of 0 means 128. */
2773 frame_size
= ((save_inst
>> 16) & 0xf0) | (save_inst
& 0xf);
2774 if (frame_size
== 0 && (save_inst
>> 16) == 0)
2777 frame_offset
+= frame_size
;
2779 /* Now we can calculate what the SP must have been at the
2780 start of the function prologue. */
2783 /* Check if A0-A3 were saved in the caller's argument save area. */
2784 for (reg
= MIPS_A0_REGNUM
, offset
= 0; reg
< args
+ 4; reg
++)
2786 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2787 offset
+= mips_abi_regsize (gdbarch
);
2792 /* Check if the RA register was pushed on the stack. */
2793 if (save_inst
& 0x40)
2795 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2796 offset
-= mips_abi_regsize (gdbarch
);
2799 /* Check if the S8 register was pushed on the stack. */
2802 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ offset
);
2803 offset
-= mips_abi_regsize (gdbarch
);
2806 /* Check if S2-S7 were pushed on the stack. */
2807 for (reg
= 18 + xsregs
- 1; reg
> 18 - 1; reg
--)
2809 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2810 offset
-= mips_abi_regsize (gdbarch
);
2813 /* Check if the S1 register was pushed on the stack. */
2814 if (save_inst
& 0x10)
2816 set_reg_offset (gdbarch
, this_cache
, 17, sp
+ offset
);
2817 offset
-= mips_abi_regsize (gdbarch
);
2819 /* Check if the S0 register was pushed on the stack. */
2820 if (save_inst
& 0x20)
2822 set_reg_offset (gdbarch
, this_cache
, 16, sp
+ offset
);
2823 offset
-= mips_abi_regsize (gdbarch
);
2826 /* Check if A0-A3 were pushed on the stack. */
2827 for (reg
= MIPS_A0_REGNUM
+ 3; reg
> MIPS_A0_REGNUM
+ 3 - astatic
; reg
--)
2829 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2830 offset
-= mips_abi_regsize (gdbarch
);
2834 if (this_cache
!= NULL
)
2837 (get_frame_register_signed (this_frame
,
2838 gdbarch_num_regs (gdbarch
) + frame_reg
)
2839 + frame_offset
- frame_adjust
);
2840 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
2841 be able to get rid of the assignment below, evetually. But it's
2842 still needed for now. */
2843 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2844 + mips_regnum (gdbarch
)->pc
]
2845 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
2848 /* Set end_prologue_addr to the address of the instruction immediately
2849 after the last one we scanned. Unless the last one looked like a
2850 non-prologue instruction (and we looked ahead), in which case use
2851 its address instead. */
2852 end_prologue_addr
= (prev_non_prologue_insn
|| prev_delay_slot
2853 ? prev_pc
: cur_pc
- prev_extend_bytes
);
2855 return end_prologue_addr
;
2858 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
2859 Procedures that use the 32-bit instruction set are handled by the
2860 mips_insn32 unwinder. */
2862 static struct mips_frame_cache
*
2863 mips_insn16_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2865 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2866 struct mips_frame_cache
*cache
;
2868 if ((*this_cache
) != NULL
)
2869 return (struct mips_frame_cache
*) (*this_cache
);
2870 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2871 (*this_cache
) = cache
;
2872 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2874 /* Analyze the function prologue. */
2876 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2877 CORE_ADDR start_addr
;
2879 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2880 if (start_addr
== 0)
2881 start_addr
= heuristic_proc_start (gdbarch
, pc
);
2882 /* We can't analyze the prologue if we couldn't find the begining
2884 if (start_addr
== 0)
2887 mips16_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
2888 (struct mips_frame_cache
*) *this_cache
);
2891 /* gdbarch_sp_regnum contains the value and not the address. */
2892 cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2893 + MIPS_SP_REGNUM
].set_value (cache
->base
);
2895 return (struct mips_frame_cache
*) (*this_cache
);
2899 mips_insn16_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2900 struct frame_id
*this_id
)
2902 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2904 /* This marks the outermost frame. */
2905 if (info
->base
== 0)
2907 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2910 static struct value
*
2911 mips_insn16_frame_prev_register (struct frame_info
*this_frame
,
2912 void **this_cache
, int regnum
)
2914 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2916 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2920 mips_insn16_frame_sniffer (const struct frame_unwind
*self
,
2921 struct frame_info
*this_frame
, void **this_cache
)
2923 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2924 CORE_ADDR pc
= get_frame_pc (this_frame
);
2925 if (mips_pc_is_mips16 (gdbarch
, pc
))
2930 static const struct frame_unwind mips_insn16_frame_unwind
=
2932 "mips insn16 prologue",
2934 default_frame_unwind_stop_reason
,
2935 mips_insn16_frame_this_id
,
2936 mips_insn16_frame_prev_register
,
2938 mips_insn16_frame_sniffer
2942 mips_insn16_frame_base_address (struct frame_info
*this_frame
,
2945 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2950 static const struct frame_base mips_insn16_frame_base
=
2952 &mips_insn16_frame_unwind
,
2953 mips_insn16_frame_base_address
,
2954 mips_insn16_frame_base_address
,
2955 mips_insn16_frame_base_address
2958 static const struct frame_base
*
2959 mips_insn16_frame_base_sniffer (struct frame_info
*this_frame
)
2961 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2962 CORE_ADDR pc
= get_frame_pc (this_frame
);
2963 if (mips_pc_is_mips16 (gdbarch
, pc
))
2964 return &mips_insn16_frame_base
;
2969 /* Decode a 9-bit signed immediate argument of ADDIUSP -- -2 is mapped
2970 to -258, -1 -- to -257, 0 -- to 256, 1 -- to 257 and other values are
2971 interpreted directly, and then multiplied by 4. */
2974 micromips_decode_imm9 (int imm
)
2976 imm
= (imm
^ 0x100) - 0x100;
2977 if (imm
> -3 && imm
< 2)
2982 /* Analyze the function prologue from START_PC to LIMIT_PC. Return
2983 the address of the first instruction past the prologue. */
2986 micromips_scan_prologue (struct gdbarch
*gdbarch
,
2987 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2988 struct frame_info
*this_frame
,
2989 struct mips_frame_cache
*this_cache
)
2991 CORE_ADDR end_prologue_addr
;
2992 int prev_non_prologue_insn
= 0;
2993 int frame_reg
= MIPS_SP_REGNUM
;
2994 int this_non_prologue_insn
;
2995 int non_prologue_insns
= 0;
2996 long frame_offset
= 0; /* Size of stack frame. */
2997 long frame_adjust
= 0; /* Offset of FP from SP. */
2998 int prev_delay_slot
= 0;
3002 ULONGEST insn
; /* current instruction */
3006 long v1_off
= 0; /* The assumption is LUI will replace it. */
3017 /* Can be called when there's no process, and hence when there's no
3019 if (this_frame
!= NULL
)
3020 sp
= get_frame_register_signed (this_frame
,
3021 gdbarch_num_regs (gdbarch
)
3026 if (limit_pc
> start_pc
+ 200)
3027 limit_pc
= start_pc
+ 200;
3030 /* Permit at most one non-prologue non-control-transfer instruction
3031 in the middle which may have been reordered by the compiler for
3033 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= loc
)
3035 this_non_prologue_insn
= 0;
3039 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, cur_pc
, NULL
);
3040 loc
+= MIPS_INSN16_SIZE
;
3041 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
3043 /* 32-bit instructions. */
3044 case 2 * MIPS_INSN16_SIZE
:
3046 insn
|= mips_fetch_instruction (gdbarch
,
3047 ISA_MICROMIPS
, cur_pc
+ loc
, NULL
);
3048 loc
+= MIPS_INSN16_SIZE
;
3049 switch (micromips_op (insn
>> 16))
3051 /* Record $sp/$fp adjustment. */
3052 /* Discard (D)ADDU $gp,$jp used for PIC code. */
3053 case 0x0: /* POOL32A: bits 000000 */
3054 case 0x16: /* POOL32S: bits 010110 */
3055 op
= b0s11_op (insn
);
3056 sreg
= b0s5_reg (insn
>> 16);
3057 treg
= b5s5_reg (insn
>> 16);
3058 dreg
= b11s5_reg (insn
);
3060 /* SUBU: bits 000000 00111010000 */
3061 /* DSUBU: bits 010110 00111010000 */
3062 && dreg
== MIPS_SP_REGNUM
&& sreg
== MIPS_SP_REGNUM
3064 /* (D)SUBU $sp, $v1 */
3066 else if (op
!= 0x150
3067 /* ADDU: bits 000000 00101010000 */
3068 /* DADDU: bits 010110 00101010000 */
3069 || dreg
!= 28 || sreg
!= 28 || treg
!= MIPS_T9_REGNUM
)
3070 this_non_prologue_insn
= 1;
3073 case 0x8: /* POOL32B: bits 001000 */
3074 op
= b12s4_op (insn
);
3075 breg
= b0s5_reg (insn
>> 16);
3076 reglist
= sreg
= b5s5_reg (insn
>> 16);
3077 offset
= (b0s12_imm (insn
) ^ 0x800) - 0x800;
3078 if ((op
== 0x9 || op
== 0xc)
3079 /* SWP: bits 001000 1001 */
3080 /* SDP: bits 001000 1100 */
3081 && breg
== MIPS_SP_REGNUM
&& sreg
< MIPS_RA_REGNUM
)
3082 /* S[DW]P reg,offset($sp) */
3084 s
= 4 << ((b12s4_op (insn
) & 0x4) == 0x4);
3085 set_reg_offset (gdbarch
, this_cache
,
3087 set_reg_offset (gdbarch
, this_cache
,
3088 sreg
+ 1, sp
+ offset
+ s
);
3090 else if ((op
== 0xd || op
== 0xf)
3091 /* SWM: bits 001000 1101 */
3092 /* SDM: bits 001000 1111 */
3093 && breg
== MIPS_SP_REGNUM
3094 /* SWM reglist,offset($sp) */
3095 && ((reglist
>= 1 && reglist
<= 9)
3096 || (reglist
>= 16 && reglist
<= 25)))
3098 int sreglist
= std::min(reglist
& 0xf, 8);
3100 s
= 4 << ((b12s4_op (insn
) & 0x2) == 0x2);
3101 for (i
= 0; i
< sreglist
; i
++)
3102 set_reg_offset (gdbarch
, this_cache
, 16 + i
, sp
+ s
* i
);
3103 if ((reglist
& 0xf) > 8)
3104 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ s
* i
++);
3105 if ((reglist
& 0x10) == 0x10)
3106 set_reg_offset (gdbarch
, this_cache
,
3107 MIPS_RA_REGNUM
, sp
+ s
* i
++);
3110 this_non_prologue_insn
= 1;
3113 /* Record $sp/$fp adjustment. */
3114 /* Discard (D)ADDIU $gp used for PIC code. */
3115 case 0xc: /* ADDIU: bits 001100 */
3116 case 0x17: /* DADDIU: bits 010111 */
3117 sreg
= b0s5_reg (insn
>> 16);
3118 dreg
= b5s5_reg (insn
>> 16);
3119 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
3120 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
)
3121 /* (D)ADDIU $sp, imm */
3123 else if (sreg
== MIPS_SP_REGNUM
&& dreg
== 30)
3124 /* (D)ADDIU $fp, $sp, imm */
3126 frame_adjust
= offset
;
3129 else if (sreg
!= 28 || dreg
!= 28)
3130 /* (D)ADDIU $gp, imm */
3131 this_non_prologue_insn
= 1;
3134 /* LUI $v1 is used for larger $sp adjustments. */
3135 /* Discard LUI $gp used for PIC code. */
3136 case 0x10: /* POOL32I: bits 010000 */
3137 if (b5s5_op (insn
>> 16) == 0xd
3138 /* LUI: bits 010000 001101 */
3139 && b0s5_reg (insn
>> 16) == 3)
3141 v1_off
= ((b0s16_imm (insn
) << 16) ^ 0x80000000) - 0x80000000;
3142 else if (b5s5_op (insn
>> 16) != 0xd
3143 /* LUI: bits 010000 001101 */
3144 || b0s5_reg (insn
>> 16) != 28)
3146 this_non_prologue_insn
= 1;
3149 /* ORI $v1 is used for larger $sp adjustments. */
3150 case 0x14: /* ORI: bits 010100 */
3151 sreg
= b0s5_reg (insn
>> 16);
3152 dreg
= b5s5_reg (insn
>> 16);
3153 if (sreg
== 3 && dreg
== 3)
3155 v1_off
|= b0s16_imm (insn
);
3157 this_non_prologue_insn
= 1;
3160 case 0x26: /* SWC1: bits 100110 */
3161 case 0x2e: /* SDC1: bits 101110 */
3162 breg
= b0s5_reg (insn
>> 16);
3163 if (breg
!= MIPS_SP_REGNUM
)
3164 /* S[DW]C1 reg,offset($sp) */
3165 this_non_prologue_insn
= 1;
3168 case 0x36: /* SD: bits 110110 */
3169 case 0x3e: /* SW: bits 111110 */
3170 breg
= b0s5_reg (insn
>> 16);
3171 sreg
= b5s5_reg (insn
>> 16);
3172 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
3173 if (breg
== MIPS_SP_REGNUM
)
3174 /* S[DW] reg,offset($sp) */
3175 set_reg_offset (gdbarch
, this_cache
, sreg
, sp
+ offset
);
3177 this_non_prologue_insn
= 1;
3181 /* The instruction in the delay slot can be a part
3182 of the prologue, so move forward once more. */
3183 if (micromips_instruction_has_delay_slot (insn
, 0))
3186 this_non_prologue_insn
= 1;
3192 /* 16-bit instructions. */
3193 case MIPS_INSN16_SIZE
:
3194 switch (micromips_op (insn
))
3196 case 0x3: /* MOVE: bits 000011 */
3197 sreg
= b0s5_reg (insn
);
3198 dreg
= b5s5_reg (insn
);
3199 if (sreg
== MIPS_SP_REGNUM
&& dreg
== 30)
3202 else if ((sreg
& 0x1c) != 0x4)
3203 /* MOVE reg, $a0-$a3 */
3204 this_non_prologue_insn
= 1;
3207 case 0x11: /* POOL16C: bits 010001 */
3208 if (b6s4_op (insn
) == 0x5)
3209 /* SWM: bits 010001 0101 */
3211 offset
= ((b0s4_imm (insn
) << 2) ^ 0x20) - 0x20;
3212 reglist
= b4s2_regl (insn
);
3213 for (i
= 0; i
<= reglist
; i
++)
3214 set_reg_offset (gdbarch
, this_cache
, 16 + i
, sp
+ 4 * i
);
3215 set_reg_offset (gdbarch
, this_cache
,
3216 MIPS_RA_REGNUM
, sp
+ 4 * i
++);
3219 this_non_prologue_insn
= 1;
3222 case 0x13: /* POOL16D: bits 010011 */
3223 if ((insn
& 0x1) == 0x1)
3224 /* ADDIUSP: bits 010011 1 */
3225 sp_adj
= micromips_decode_imm9 (b1s9_imm (insn
));
3226 else if (b5s5_reg (insn
) == MIPS_SP_REGNUM
)
3227 /* ADDIUS5: bits 010011 0 */
3228 /* ADDIUS5 $sp, imm */
3229 sp_adj
= (b1s4_imm (insn
) ^ 8) - 8;
3231 this_non_prologue_insn
= 1;
3234 case 0x32: /* SWSP: bits 110010 */
3235 offset
= b0s5_imm (insn
) << 2;
3236 sreg
= b5s5_reg (insn
);
3237 set_reg_offset (gdbarch
, this_cache
, sreg
, sp
+ offset
);
3241 /* The instruction in the delay slot can be a part
3242 of the prologue, so move forward once more. */
3243 if (micromips_instruction_has_delay_slot (insn
<< 16, 0))
3246 this_non_prologue_insn
= 1;
3252 frame_offset
-= sp_adj
;
3254 non_prologue_insns
+= this_non_prologue_insn
;
3256 /* A jump or branch, enough non-prologue insns seen or positive
3257 stack adjustment? If so, then we must have reached the end
3258 of the prologue by now. */
3259 if (prev_delay_slot
|| non_prologue_insns
> 1 || sp_adj
> 0
3260 || micromips_instruction_is_compact_branch (insn
))
3263 prev_non_prologue_insn
= this_non_prologue_insn
;
3264 prev_delay_slot
= in_delay_slot
;
3268 if (this_cache
!= NULL
)
3271 (get_frame_register_signed (this_frame
,
3272 gdbarch_num_regs (gdbarch
) + frame_reg
)
3273 + frame_offset
- frame_adjust
);
3274 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
3275 be able to get rid of the assignment below, evetually. But it's
3276 still needed for now. */
3277 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3278 + mips_regnum (gdbarch
)->pc
]
3279 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
3282 /* Set end_prologue_addr to the address of the instruction immediately
3283 after the last one we scanned. Unless the last one looked like a
3284 non-prologue instruction (and we looked ahead), in which case use
3285 its address instead. */
3287 = prev_non_prologue_insn
|| prev_delay_slot
? prev_pc
: cur_pc
;
3289 return end_prologue_addr
;
3292 /* Heuristic unwinder for procedures using microMIPS instructions.
3293 Procedures that use the 32-bit instruction set are handled by the
3294 mips_insn32 unwinder. Likewise MIPS16 and the mips_insn16 unwinder. */
3296 static struct mips_frame_cache
*
3297 mips_micro_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3299 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3300 struct mips_frame_cache
*cache
;
3302 if ((*this_cache
) != NULL
)
3303 return (struct mips_frame_cache
*) (*this_cache
);
3305 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
3306 (*this_cache
) = cache
;
3307 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3309 /* Analyze the function prologue. */
3311 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3312 CORE_ADDR start_addr
;
3314 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3315 if (start_addr
== 0)
3316 start_addr
= heuristic_proc_start (get_frame_arch (this_frame
), pc
);
3317 /* We can't analyze the prologue if we couldn't find the begining
3319 if (start_addr
== 0)
3322 micromips_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
3323 (struct mips_frame_cache
*) *this_cache
);
3326 /* gdbarch_sp_regnum contains the value and not the address. */
3327 cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3328 + MIPS_SP_REGNUM
].set_value (cache
->base
);
3330 return (struct mips_frame_cache
*) (*this_cache
);
3334 mips_micro_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3335 struct frame_id
*this_id
)
3337 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3339 /* This marks the outermost frame. */
3340 if (info
->base
== 0)
3342 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3345 static struct value
*
3346 mips_micro_frame_prev_register (struct frame_info
*this_frame
,
3347 void **this_cache
, int regnum
)
3349 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3351 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3355 mips_micro_frame_sniffer (const struct frame_unwind
*self
,
3356 struct frame_info
*this_frame
, void **this_cache
)
3358 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3359 CORE_ADDR pc
= get_frame_pc (this_frame
);
3361 if (mips_pc_is_micromips (gdbarch
, pc
))
3366 static const struct frame_unwind mips_micro_frame_unwind
=
3368 "mips micro prologue",
3370 default_frame_unwind_stop_reason
,
3371 mips_micro_frame_this_id
,
3372 mips_micro_frame_prev_register
,
3374 mips_micro_frame_sniffer
3378 mips_micro_frame_base_address (struct frame_info
*this_frame
,
3381 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3386 static const struct frame_base mips_micro_frame_base
=
3388 &mips_micro_frame_unwind
,
3389 mips_micro_frame_base_address
,
3390 mips_micro_frame_base_address
,
3391 mips_micro_frame_base_address
3394 static const struct frame_base
*
3395 mips_micro_frame_base_sniffer (struct frame_info
*this_frame
)
3397 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3398 CORE_ADDR pc
= get_frame_pc (this_frame
);
3400 if (mips_pc_is_micromips (gdbarch
, pc
))
3401 return &mips_micro_frame_base
;
3406 /* Mark all the registers as unset in the saved_regs array
3407 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
3410 reset_saved_regs (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
)
3412 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
3416 const int num_regs
= gdbarch_num_regs (gdbarch
);
3419 /* Reset the register values to their default state. Register i's value
3420 is in register i. */
3421 for (i
= 0; i
< num_regs
; i
++)
3422 this_cache
->saved_regs
[i
].set_realreg (i
);
3426 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
3427 the associated FRAME_CACHE if not null.
3428 Return the address of the first instruction past the prologue. */
3431 mips32_scan_prologue (struct gdbarch
*gdbarch
,
3432 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
3433 struct frame_info
*this_frame
,
3434 struct mips_frame_cache
*this_cache
)
3436 int prev_non_prologue_insn
;
3437 int this_non_prologue_insn
;
3438 int non_prologue_insns
;
3439 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for
3441 int prev_delay_slot
;
3446 int frame_reg
= MIPS_SP_REGNUM
;
3448 CORE_ADDR end_prologue_addr
;
3449 int seen_sp_adjust
= 0;
3450 int load_immediate_bytes
= 0;
3452 int regsize_is_64_bits
= (mips_abi_regsize (gdbarch
) == 8);
3454 /* Can be called when there's no process, and hence when there's no
3456 if (this_frame
!= NULL
)
3457 sp
= get_frame_register_signed (this_frame
,
3458 gdbarch_num_regs (gdbarch
)
3463 if (limit_pc
> start_pc
+ 200)
3464 limit_pc
= start_pc
+ 200;
3467 prev_non_prologue_insn
= 0;
3468 non_prologue_insns
= 0;
3469 prev_delay_slot
= 0;
3472 /* Permit at most one non-prologue non-control-transfer instruction
3473 in the middle which may have been reordered by the compiler for
3476 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
3478 unsigned long inst
, high_word
;
3482 this_non_prologue_insn
= 0;
3485 /* Fetch the instruction. */
3486 inst
= (unsigned long) mips_fetch_instruction (gdbarch
, ISA_MIPS
,
3489 /* Save some code by pre-extracting some useful fields. */
3490 high_word
= (inst
>> 16) & 0xffff;
3491 offset
= ((inst
& 0xffff) ^ 0x8000) - 0x8000;
3492 reg
= high_word
& 0x1f;
3494 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
3495 || high_word
== 0x23bd /* addi $sp,$sp,-i */
3496 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
3498 if (offset
< 0) /* Negative stack adjustment? */
3499 frame_offset
-= offset
;
3501 /* Exit loop if a positive stack adjustment is found, which
3502 usually means that the stack cleanup code in the function
3503 epilogue is reached. */
3507 else if (((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
3508 && !regsize_is_64_bits
)
3510 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
3512 else if (((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
3513 && regsize_is_64_bits
)
3515 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
3516 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
3518 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
3520 /* Old gcc frame, r30 is virtual frame pointer. */
3521 if (offset
!= frame_offset
)
3522 frame_addr
= sp
+ offset
;
3523 else if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
3525 unsigned alloca_adjust
;
3528 frame_addr
= get_frame_register_signed
3529 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
3532 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ offset
));
3533 if (alloca_adjust
> 0)
3535 /* FP > SP + frame_size. This may be because of
3536 an alloca or somethings similar. Fix sp to
3537 "pre-alloca" value, and try again. */
3538 sp
+= alloca_adjust
;
3539 /* Need to reset the status of all registers. Otherwise,
3540 we will hit a guard that prevents the new address
3541 for each register to be recomputed during the second
3543 reset_saved_regs (gdbarch
, this_cache
);
3548 /* move $30,$sp. With different versions of gas this will be either
3549 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
3550 Accept any one of these. */
3551 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
3553 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
3554 if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
3556 unsigned alloca_adjust
;
3559 frame_addr
= get_frame_register_signed
3560 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
3562 alloca_adjust
= (unsigned) (frame_addr
- sp
);
3563 if (alloca_adjust
> 0)
3565 /* FP > SP + frame_size. This may be because of
3566 an alloca or somethings similar. Fix sp to
3567 "pre-alloca" value, and try again. */
3569 /* Need to reset the status of all registers. Otherwise,
3570 we will hit a guard that prevents the new address
3571 for each register to be recomputed during the second
3573 reset_saved_regs (gdbarch
, this_cache
);
3578 else if ((high_word
& 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
3579 && !regsize_is_64_bits
)
3581 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
3583 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
3584 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
3585 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
3586 || high_word
== 0x3c1c /* lui $gp,n */
3587 || high_word
== 0x279c /* addiu $gp,$gp,n */
3588 || high_word
== 0x679c /* daddiu $gp,$gp,n */
3589 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
3590 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
3591 || inst
== 0x0399e02d /* daddu $gp,$gp,$t9 */
3592 || inst
== 0x033ce02d /* daddu $gp,$t9,$gp */
3595 /* These instructions are part of the prologue, but we don't
3596 need to do anything special to handle them. */
3598 /* The instructions below load $at or $t0 with an immediate
3599 value in preparation for a stack adjustment via
3600 subu $sp,$sp,[$at,$t0]. These instructions could also
3601 initialize a local variable, so we accept them only before
3602 a stack adjustment instruction was seen. */
3603 else if (!seen_sp_adjust
3605 && (high_word
== 0x3c01 /* lui $at,n */
3606 || high_word
== 0x3c08 /* lui $t0,n */
3607 || high_word
== 0x3421 /* ori $at,$at,n */
3608 || high_word
== 0x3508 /* ori $t0,$t0,n */
3609 || high_word
== 0x3401 /* ori $at,$zero,n */
3610 || high_word
== 0x3408 /* ori $t0,$zero,n */
3613 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
3615 /* Check for branches and jumps. The instruction in the delay
3616 slot can be a part of the prologue, so move forward once more. */
3617 else if (mips32_instruction_has_delay_slot (gdbarch
, inst
))
3621 /* This instruction is not an instruction typically found
3622 in a prologue, so we must have reached the end of the
3626 this_non_prologue_insn
= 1;
3629 non_prologue_insns
+= this_non_prologue_insn
;
3631 /* A jump or branch, or enough non-prologue insns seen? If so,
3632 then we must have reached the end of the prologue by now. */
3633 if (prev_delay_slot
|| non_prologue_insns
> 1)
3636 prev_non_prologue_insn
= this_non_prologue_insn
;
3637 prev_delay_slot
= in_delay_slot
;
3641 if (this_cache
!= NULL
)
3644 (get_frame_register_signed (this_frame
,
3645 gdbarch_num_regs (gdbarch
) + frame_reg
)
3647 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
3648 this assignment below, eventually. But it's still needed
3650 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3651 + mips_regnum (gdbarch
)->pc
]
3652 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3656 /* Set end_prologue_addr to the address of the instruction immediately
3657 after the last one we scanned. Unless the last one looked like a
3658 non-prologue instruction (and we looked ahead), in which case use
3659 its address instead. */
3661 = prev_non_prologue_insn
|| prev_delay_slot
? prev_pc
: cur_pc
;
3663 /* In a frameless function, we might have incorrectly
3664 skipped some load immediate instructions. Undo the skipping
3665 if the load immediate was not followed by a stack adjustment. */
3666 if (load_immediate_bytes
&& !seen_sp_adjust
)
3667 end_prologue_addr
-= load_immediate_bytes
;
3669 return end_prologue_addr
;
3672 /* Heuristic unwinder for procedures using 32-bit instructions (covers
3673 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
3674 instructions (a.k.a. MIPS16) are handled by the mips_insn16
3675 unwinder. Likewise microMIPS and the mips_micro unwinder. */
3677 static struct mips_frame_cache
*
3678 mips_insn32_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3680 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3681 struct mips_frame_cache
*cache
;
3683 if ((*this_cache
) != NULL
)
3684 return (struct mips_frame_cache
*) (*this_cache
);
3686 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
3687 (*this_cache
) = cache
;
3688 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3690 /* Analyze the function prologue. */
3692 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3693 CORE_ADDR start_addr
;
3695 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3696 if (start_addr
== 0)
3697 start_addr
= heuristic_proc_start (gdbarch
, pc
);
3698 /* We can't analyze the prologue if we couldn't find the begining
3700 if (start_addr
== 0)
3703 mips32_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
3704 (struct mips_frame_cache
*) *this_cache
);
3707 /* gdbarch_sp_regnum contains the value and not the address. */
3708 cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3709 + MIPS_SP_REGNUM
].set_value (cache
->base
);
3711 return (struct mips_frame_cache
*) (*this_cache
);
3715 mips_insn32_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3716 struct frame_id
*this_id
)
3718 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3720 /* This marks the outermost frame. */
3721 if (info
->base
== 0)
3723 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3726 static struct value
*
3727 mips_insn32_frame_prev_register (struct frame_info
*this_frame
,
3728 void **this_cache
, int regnum
)
3730 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3732 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3736 mips_insn32_frame_sniffer (const struct frame_unwind
*self
,
3737 struct frame_info
*this_frame
, void **this_cache
)
3739 CORE_ADDR pc
= get_frame_pc (this_frame
);
3740 if (mips_pc_is_mips (pc
))
3745 static const struct frame_unwind mips_insn32_frame_unwind
=
3747 "mips insn32 prologue",
3749 default_frame_unwind_stop_reason
,
3750 mips_insn32_frame_this_id
,
3751 mips_insn32_frame_prev_register
,
3753 mips_insn32_frame_sniffer
3757 mips_insn32_frame_base_address (struct frame_info
*this_frame
,
3760 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3765 static const struct frame_base mips_insn32_frame_base
=
3767 &mips_insn32_frame_unwind
,
3768 mips_insn32_frame_base_address
,
3769 mips_insn32_frame_base_address
,
3770 mips_insn32_frame_base_address
3773 static const struct frame_base
*
3774 mips_insn32_frame_base_sniffer (struct frame_info
*this_frame
)
3776 CORE_ADDR pc
= get_frame_pc (this_frame
);
3777 if (mips_pc_is_mips (pc
))
3778 return &mips_insn32_frame_base
;
3783 static struct trad_frame_cache
*
3784 mips_stub_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3787 CORE_ADDR start_addr
;
3788 CORE_ADDR stack_addr
;
3789 struct trad_frame_cache
*this_trad_cache
;
3790 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3791 int num_regs
= gdbarch_num_regs (gdbarch
);
3793 if ((*this_cache
) != NULL
)
3794 return (struct trad_frame_cache
*) (*this_cache
);
3795 this_trad_cache
= trad_frame_cache_zalloc (this_frame
);
3796 (*this_cache
) = this_trad_cache
;
3798 /* The return address is in the link register. */
3799 trad_frame_set_reg_realreg (this_trad_cache
,
3800 gdbarch_pc_regnum (gdbarch
),
3801 num_regs
+ MIPS_RA_REGNUM
);
3803 /* Frame ID, since it's a frameless / stackless function, no stack
3804 space is allocated and SP on entry is the current SP. */
3805 pc
= get_frame_pc (this_frame
);
3806 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3807 stack_addr
= get_frame_register_signed (this_frame
,
3808 num_regs
+ MIPS_SP_REGNUM
);
3809 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
3811 /* Assume that the frame's base is the same as the
3813 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
3815 return this_trad_cache
;
3819 mips_stub_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3820 struct frame_id
*this_id
)
3822 struct trad_frame_cache
*this_trad_cache
3823 = mips_stub_frame_cache (this_frame
, this_cache
);
3824 trad_frame_get_id (this_trad_cache
, this_id
);
3827 static struct value
*
3828 mips_stub_frame_prev_register (struct frame_info
*this_frame
,
3829 void **this_cache
, int regnum
)
3831 struct trad_frame_cache
*this_trad_cache
3832 = mips_stub_frame_cache (this_frame
, this_cache
);
3833 return trad_frame_get_register (this_trad_cache
, this_frame
, regnum
);
3837 mips_stub_frame_sniffer (const struct frame_unwind
*self
,
3838 struct frame_info
*this_frame
, void **this_cache
)
3841 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3842 struct bound_minimal_symbol msym
;
3844 /* Use the stub unwinder for unreadable code. */
3845 if (target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
3848 if (in_plt_section (pc
) || in_mips_stubs_section (pc
))
3851 /* Calling a PIC function from a non-PIC function passes through a
3852 stub. The stub for foo is named ".pic.foo". */
3853 msym
= lookup_minimal_symbol_by_pc (pc
);
3854 if (msym
.minsym
!= NULL
3855 && msym
.minsym
->linkage_name () != NULL
3856 && startswith (msym
.minsym
->linkage_name (), ".pic."))
3862 static const struct frame_unwind mips_stub_frame_unwind
=
3866 default_frame_unwind_stop_reason
,
3867 mips_stub_frame_this_id
,
3868 mips_stub_frame_prev_register
,
3870 mips_stub_frame_sniffer
3874 mips_stub_frame_base_address (struct frame_info
*this_frame
,
3877 struct trad_frame_cache
*this_trad_cache
3878 = mips_stub_frame_cache (this_frame
, this_cache
);
3879 return trad_frame_get_this_base (this_trad_cache
);
3882 static const struct frame_base mips_stub_frame_base
=
3884 &mips_stub_frame_unwind
,
3885 mips_stub_frame_base_address
,
3886 mips_stub_frame_base_address
,
3887 mips_stub_frame_base_address
3890 static const struct frame_base
*
3891 mips_stub_frame_base_sniffer (struct frame_info
*this_frame
)
3893 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind
, this_frame
, NULL
))
3894 return &mips_stub_frame_base
;
3899 /* mips_addr_bits_remove - remove useless address bits */
3902 mips_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
3904 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
3906 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
3907 /* This hack is a work-around for existing boards using PMON, the
3908 simulator, and any other 64-bit targets that doesn't have true
3909 64-bit addressing. On these targets, the upper 32 bits of
3910 addresses are ignored by the hardware. Thus, the PC or SP are
3911 likely to have been sign extended to all 1s by instruction
3912 sequences that load 32-bit addresses. For example, a typical
3913 piece of code that loads an address is this:
3915 lui $r2, <upper 16 bits>
3916 ori $r2, <lower 16 bits>
3918 But the lui sign-extends the value such that the upper 32 bits
3919 may be all 1s. The workaround is simply to mask off these
3920 bits. In the future, gcc may be changed to support true 64-bit
3921 addressing, and this masking will have to be disabled. */
3922 return addr
&= 0xffffffffUL
;
3928 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
3929 instruction and ending with a SC/SCD instruction. If such a sequence
3930 is found, attempt to step through it. A breakpoint is placed at the end of
3933 /* Instructions used during single-stepping of atomic sequences, standard
3935 #define LL_OPCODE 0x30
3936 #define LLD_OPCODE 0x34
3937 #define SC_OPCODE 0x38
3938 #define SCD_OPCODE 0x3c
3940 static std::vector
<CORE_ADDR
>
3941 mips_deal_with_atomic_sequence (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3943 CORE_ADDR breaks
[2] = {CORE_ADDR_MAX
, CORE_ADDR_MAX
};
3945 CORE_ADDR branch_bp
; /* Breakpoint at branch instruction's destination. */
3949 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
3950 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
3952 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, loc
, NULL
);
3953 /* Assume all atomic sequences start with a ll/lld instruction. */
3954 if (itype_op (insn
) != LL_OPCODE
&& itype_op (insn
) != LLD_OPCODE
)
3957 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
3959 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
3962 loc
+= MIPS_INSN32_SIZE
;
3963 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, loc
, NULL
);
3965 /* Assume that there is at most one branch in the atomic
3966 sequence. If a branch is found, put a breakpoint in its
3967 destination address. */
3968 switch (itype_op (insn
))
3970 case 0: /* SPECIAL */
3971 if (rtype_funct (insn
) >> 1 == 4) /* JR, JALR */
3972 return {}; /* fallback to the standard single-step code. */
3974 case 1: /* REGIMM */
3975 is_branch
= ((itype_rt (insn
) & 0xc) == 0 /* B{LT,GE}Z* */
3976 || ((itype_rt (insn
) & 0x1e) == 0
3977 && itype_rs (insn
) == 0)); /* BPOSGE* */
3981 return {}; /* fallback to the standard single-step code. */
3988 case 22: /* BLEZL */
3989 case 23: /* BGTTL */
3993 is_branch
= ((itype_rs (insn
) == 9 || itype_rs (insn
) == 10)
3994 && (itype_rt (insn
) & 0x2) == 0);
3995 if (is_branch
) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */
4000 is_branch
= (itype_rs (insn
) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
4005 branch_bp
= loc
+ mips32_relative_offset (insn
) + 4;
4006 if (last_breakpoint
>= 1)
4007 return {}; /* More than one branch found, fallback to the
4008 standard single-step code. */
4009 breaks
[1] = branch_bp
;
4013 if (itype_op (insn
) == SC_OPCODE
|| itype_op (insn
) == SCD_OPCODE
)
4017 /* Assume that the atomic sequence ends with a sc/scd instruction. */
4018 if (itype_op (insn
) != SC_OPCODE
&& itype_op (insn
) != SCD_OPCODE
)
4021 loc
+= MIPS_INSN32_SIZE
;
4023 /* Insert a breakpoint right after the end of the atomic sequence. */
4026 /* Check for duplicated breakpoints. Check also for a breakpoint
4027 placed (branch instruction's destination) in the atomic sequence. */
4028 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
4029 last_breakpoint
= 0;
4031 std::vector
<CORE_ADDR
> next_pcs
;
4033 /* Effectively inserts the breakpoints. */
4034 for (index
= 0; index
<= last_breakpoint
; index
++)
4035 next_pcs
.push_back (breaks
[index
]);
4040 static std::vector
<CORE_ADDR
>
4041 micromips_deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
4044 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
4045 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
4046 CORE_ADDR breaks
[2] = {CORE_ADDR_MAX
, CORE_ADDR_MAX
};
4047 CORE_ADDR branch_bp
= 0; /* Breakpoint at branch instruction's
4055 /* Assume all atomic sequences start with a ll/lld instruction. */
4056 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
4057 if (micromips_op (insn
) != 0x18) /* POOL32C: bits 011000 */
4059 loc
+= MIPS_INSN16_SIZE
;
4061 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
4062 if ((b12s4_op (insn
) & 0xb) != 0x3) /* LL, LLD: bits 011000 0x11 */
4064 loc
+= MIPS_INSN16_SIZE
;
4066 /* Assume all atomic sequences end with an sc/scd instruction. Assume
4067 that no atomic sequence is longer than "atomic_sequence_length"
4069 for (insn_count
= 0;
4070 !sc_found
&& insn_count
< atomic_sequence_length
;
4075 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
4076 loc
+= MIPS_INSN16_SIZE
;
4078 /* Assume that there is at most one conditional branch in the
4079 atomic sequence. If a branch is found, put a breakpoint in
4080 its destination address. */
4081 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
4083 /* 32-bit instructions. */
4084 case 2 * MIPS_INSN16_SIZE
:
4085 switch (micromips_op (insn
))
4087 case 0x10: /* POOL32I: bits 010000 */
4088 if ((b5s5_op (insn
) & 0x18) != 0x0
4089 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
4090 /* BLEZ, BNEZC, BGTZ, BEQZC: 010000 001xx */
4091 && (b5s5_op (insn
) & 0x1d) != 0x11
4092 /* BLTZALS, BGEZALS: bits 010000 100x1 */
4093 && ((b5s5_op (insn
) & 0x1e) != 0x14
4094 || (insn
& 0x3) != 0x0)
4095 /* BC2F, BC2T: bits 010000 1010x xxx00 */
4096 && (b5s5_op (insn
) & 0x1e) != 0x1a
4097 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
4098 && ((b5s5_op (insn
) & 0x1e) != 0x1c
4099 || (insn
& 0x3) != 0x0)
4100 /* BC1F, BC1T: bits 010000 1110x xxx00 */
4101 && ((b5s5_op (insn
) & 0x1c) != 0x1c
4102 || (insn
& 0x3) != 0x1))
4103 /* BC1ANY*: bits 010000 111xx xxx01 */
4107 case 0x25: /* BEQ: bits 100101 */
4108 case 0x2d: /* BNE: bits 101101 */
4110 insn
|= mips_fetch_instruction (gdbarch
,
4111 ISA_MICROMIPS
, loc
, NULL
);
4112 branch_bp
= (loc
+ MIPS_INSN16_SIZE
4113 + micromips_relative_offset16 (insn
));
4117 case 0x00: /* POOL32A: bits 000000 */
4119 insn
|= mips_fetch_instruction (gdbarch
,
4120 ISA_MICROMIPS
, loc
, NULL
);
4121 if (b0s6_op (insn
) != 0x3c
4122 /* POOL32Axf: bits 000000 ... 111100 */
4123 || (b6s10_ext (insn
) & 0x2bf) != 0x3c)
4124 /* JALR, JALR.HB: 000000 000x111100 111100 */
4125 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
4129 case 0x1d: /* JALS: bits 011101 */
4130 case 0x35: /* J: bits 110101 */
4131 case 0x3d: /* JAL: bits 111101 */
4132 case 0x3c: /* JALX: bits 111100 */
4133 return {}; /* Fall back to the standard single-step code. */
4135 case 0x18: /* POOL32C: bits 011000 */
4136 if ((b12s4_op (insn
) & 0xb) == 0xb)
4137 /* SC, SCD: bits 011000 1x11 */
4141 loc
+= MIPS_INSN16_SIZE
;
4144 /* 16-bit instructions. */
4145 case MIPS_INSN16_SIZE
:
4146 switch (micromips_op (insn
))
4148 case 0x23: /* BEQZ16: bits 100011 */
4149 case 0x2b: /* BNEZ16: bits 101011 */
4150 branch_bp
= loc
+ micromips_relative_offset7 (insn
);
4154 case 0x11: /* POOL16C: bits 010001 */
4155 if ((b5s5_op (insn
) & 0x1c) != 0xc
4156 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
4157 && b5s5_op (insn
) != 0x18)
4158 /* JRADDIUSP: bits 010001 11000 */
4160 return {}; /* Fall back to the standard single-step code. */
4162 case 0x33: /* B16: bits 110011 */
4163 return {}; /* Fall back to the standard single-step code. */
4169 if (last_breakpoint
>= 1)
4170 return {}; /* More than one branch found, fallback to the
4171 standard single-step code. */
4172 breaks
[1] = branch_bp
;
4179 /* Insert a breakpoint right after the end of the atomic sequence. */
4182 /* Check for duplicated breakpoints. Check also for a breakpoint
4183 placed (branch instruction's destination) in the atomic sequence */
4184 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
4185 last_breakpoint
= 0;
4187 std::vector
<CORE_ADDR
> next_pcs
;
4189 /* Effectively inserts the breakpoints. */
4190 for (index
= 0; index
<= last_breakpoint
; index
++)
4191 next_pcs
.push_back (breaks
[index
]);
4196 static std::vector
<CORE_ADDR
>
4197 deal_with_atomic_sequence (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4199 if (mips_pc_is_mips (pc
))
4200 return mips_deal_with_atomic_sequence (gdbarch
, pc
);
4201 else if (mips_pc_is_micromips (gdbarch
, pc
))
4202 return micromips_deal_with_atomic_sequence (gdbarch
, pc
);
4207 /* mips_software_single_step() is called just before we want to resume
4208 the inferior, if we want to single-step it but there is no hardware
4209 or kernel single-step support (MIPS on GNU/Linux for example). We find
4210 the target of the coming instruction and breakpoint it. */
4212 std::vector
<CORE_ADDR
>
4213 mips_software_single_step (struct regcache
*regcache
)
4215 struct gdbarch
*gdbarch
= regcache
->arch ();
4216 CORE_ADDR pc
, next_pc
;
4218 pc
= regcache_read_pc (regcache
);
4219 std::vector
<CORE_ADDR
> next_pcs
= deal_with_atomic_sequence (gdbarch
, pc
);
4221 if (!next_pcs
.empty ())
4224 next_pc
= mips_next_pc (regcache
, pc
);
4229 /* Test whether the PC points to the return instruction at the
4230 end of a function. */
4233 mips_about_to_return (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4238 /* This used to check for MIPS16, but this piece of code is never
4239 called for MIPS16 functions. And likewise microMIPS ones. */
4240 gdb_assert (mips_pc_is_mips (pc
));
4242 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
4244 return (insn
& ~hint
) == 0x3e00008; /* jr(.hb) $ra */
4248 /* This fencepost looks highly suspicious to me. Removing it also
4249 seems suspicious as it could affect remote debugging across serial
4253 heuristic_proc_start (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4259 struct inferior
*inf
;
4261 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
4263 fence
= start_pc
- heuristic_fence_post
;
4267 if (heuristic_fence_post
== -1 || fence
< VM_MIN_ADDRESS
)
4268 fence
= VM_MIN_ADDRESS
;
4270 instlen
= mips_pc_is_mips (pc
) ? MIPS_INSN32_SIZE
: MIPS_INSN16_SIZE
;
4272 inf
= current_inferior ();
4274 /* Search back for previous return. */
4275 for (start_pc
-= instlen
;; start_pc
-= instlen
)
4276 if (start_pc
< fence
)
4278 /* It's not clear to me why we reach this point when
4279 stop_soon, but with this test, at least we
4280 don't print out warnings for every child forked (eg, on
4281 decstation). 22apr93 rich@cygnus.com. */
4282 if (inf
->control
.stop_soon
== NO_STOP_QUIETLY
)
4284 static int blurb_printed
= 0;
4286 warning (_("GDB can't find the start of the function at %s."),
4287 paddress (gdbarch
, pc
));
4291 /* This actually happens frequently in embedded
4292 development, when you first connect to a board
4293 and your stack pointer and pc are nowhere in
4294 particular. This message needs to give people
4295 in that situation enough information to
4296 determine that it's no big deal. */
4298 GDB is unable to find the start of the function at %s\n\
4299 and thus can't determine the size of that function's stack frame.\n\
4300 This means that GDB may be unable to access that stack frame, or\n\
4301 the frames below it.\n\
4302 This problem is most likely caused by an invalid program counter or\n\
4304 However, if you think GDB should simply search farther back\n\
4305 from %s for code which looks like the beginning of a\n\
4306 function, you can increase the range of the search using the `set\n\
4307 heuristic-fence-post' command.\n",
4308 paddress (gdbarch
, pc
), paddress (gdbarch
, pc
));
4315 else if (mips_pc_is_mips16 (gdbarch
, start_pc
))
4317 unsigned short inst
;
4319 /* On MIPS16, any one of the following is likely to be the
4320 start of a function:
4326 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */
4327 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, start_pc
, NULL
);
4328 if ((inst
& 0xff80) == 0x6480) /* save */
4330 if (start_pc
- instlen
>= fence
)
4332 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
,
4333 start_pc
- instlen
, NULL
);
4334 if ((inst
& 0xf800) == 0xf000) /* extend */
4335 start_pc
-= instlen
;
4339 else if (((inst
& 0xf81f) == 0xe809
4340 && (inst
& 0x700) != 0x700) /* entry */
4341 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
4342 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
4343 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
4345 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
4346 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
4351 else if (mips_pc_is_micromips (gdbarch
, start_pc
))
4359 /* On microMIPS, any one of the following is likely to be the
4360 start of a function:
4364 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
4365 switch (micromips_op (insn
))
4367 case 0xc: /* ADDIU: bits 001100 */
4368 case 0x17: /* DADDIU: bits 010111 */
4369 sreg
= b0s5_reg (insn
);
4370 dreg
= b5s5_reg (insn
);
4372 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
,
4373 pc
+ MIPS_INSN16_SIZE
, NULL
);
4374 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
4375 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
4376 /* (D)ADDIU $sp, imm */
4381 case 0x10: /* POOL32I: bits 010000 */
4382 if (b5s5_op (insn
) == 0xd
4383 /* LUI: bits 010000 001101 */
4384 && b0s5_reg (insn
>> 16) == 28)
4389 case 0x13: /* POOL16D: bits 010011 */
4390 if ((insn
& 0x1) == 0x1)
4391 /* ADDIUSP: bits 010011 1 */
4393 offset
= micromips_decode_imm9 (b1s9_imm (insn
));
4399 /* ADDIUS5: bits 010011 0 */
4401 dreg
= b5s5_reg (insn
);
4402 offset
= (b1s4_imm (insn
) ^ 8) - 8;
4403 if (dreg
== MIPS_SP_REGNUM
&& offset
< 0)
4404 /* ADDIUS5 $sp, -imm */
4412 else if (mips_about_to_return (gdbarch
, start_pc
))
4414 /* Skip return and its delay slot. */
4415 start_pc
+= 2 * MIPS_INSN32_SIZE
;
4422 struct mips_objfile_private
4428 /* According to the current ABI, should the type be passed in a
4429 floating-point register (assuming that there is space)? When there
4430 is no FPU, FP are not even considered as possible candidates for
4431 FP registers and, consequently this returns false - forces FP
4432 arguments into integer registers. */
4435 fp_register_arg_p (struct gdbarch
*gdbarch
, enum type_code typecode
,
4436 struct type
*arg_type
)
4438 return ((typecode
== TYPE_CODE_FLT
4439 || (mips_eabi (gdbarch
)
4440 && (typecode
== TYPE_CODE_STRUCT
4441 || typecode
== TYPE_CODE_UNION
)
4442 && arg_type
->num_fields () == 1
4443 && check_typedef (arg_type
->field (0).type ())->code ()
4445 && mips_get_fpu_type (gdbarch
) != MIPS_FPU_NONE
);
4448 /* On o32, argument passing in GPRs depends on the alignment of the type being
4449 passed. Return 1 if this type must be aligned to a doubleword boundary. */
4452 mips_type_needs_double_align (struct type
*type
)
4454 enum type_code typecode
= type
->code ();
4456 if (typecode
== TYPE_CODE_FLT
&& type
->length () == 8)
4458 else if (typecode
== TYPE_CODE_STRUCT
)
4460 if (type
->num_fields () < 1)
4462 return mips_type_needs_double_align (type
->field (0).type ());
4464 else if (typecode
== TYPE_CODE_UNION
)
4468 n
= type
->num_fields ();
4469 for (i
= 0; i
< n
; i
++)
4470 if (mips_type_needs_double_align (type
->field (i
).type ()))
4477 /* Adjust the address downward (direction of stack growth) so that it
4478 is correctly aligned for a new stack frame. */
4480 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
4482 return align_down (addr
, 16);
4485 /* Implement the "push_dummy_code" gdbarch method. */
4488 mips_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
4489 CORE_ADDR funaddr
, struct value
**args
,
4490 int nargs
, struct type
*value_type
,
4491 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
4492 struct regcache
*regcache
)
4494 static gdb_byte nop_insn
[] = { 0, 0, 0, 0 };
4498 /* Reserve enough room on the stack for our breakpoint instruction. */
4499 bp_slot
= sp
- sizeof (nop_insn
);
4501 /* Return to microMIPS mode if calling microMIPS code to avoid
4502 triggering an address error exception on processors that only
4503 support microMIPS execution. */
4504 *bp_addr
= (mips_pc_is_micromips (gdbarch
, funaddr
)
4505 ? make_compact_addr (bp_slot
) : bp_slot
);
4507 /* The breakpoint layer automatically adjusts the address of
4508 breakpoints inserted in a branch delay slot. With enough
4509 bad luck, the 4 bytes located just before our breakpoint
4510 instruction could look like a branch instruction, and thus
4511 trigger the adjustement, and break the function call entirely.
4512 So, we reserve those 4 bytes and write a nop instruction
4513 to prevent that from happening. */
4514 nop_addr
= bp_slot
- sizeof (nop_insn
);
4515 write_memory (nop_addr
, nop_insn
, sizeof (nop_insn
));
4516 sp
= mips_frame_align (gdbarch
, nop_addr
);
4518 /* Inferior resumes at the function entry point. */
4525 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4526 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4527 int nargs
, struct value
**args
, CORE_ADDR sp
,
4528 function_call_return_method return_method
,
4529 CORE_ADDR struct_addr
)
4535 int stack_offset
= 0;
4536 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4537 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4538 int abi_regsize
= mips_abi_regsize (gdbarch
);
4540 /* For shared libraries, "t9" needs to point at the function
4542 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4544 /* Set the return address register to point to the entry point of
4545 the program, where a breakpoint lies in wait. */
4546 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4548 /* First ensure that the stack and structure return address (if any)
4549 are properly aligned. The stack has to be at least 64-bit
4550 aligned even on 32-bit machines, because doubles must be 64-bit
4551 aligned. For n32 and n64, stack frames need to be 128-bit
4552 aligned, so we round to this widest known alignment. */
4554 sp
= align_down (sp
, 16);
4555 struct_addr
= align_down (struct_addr
, 16);
4557 /* Now make space on the stack for the args. We allocate more
4558 than necessary for EABI, because the first few arguments are
4559 passed in registers, but that's OK. */
4560 for (argnum
= 0; argnum
< nargs
; argnum
++)
4561 arg_space
+= align_up (value_type (args
[argnum
])->length (),
4563 sp
-= align_up (arg_space
, 16);
4566 gdb_printf (gdb_stdlog
,
4567 "mips_eabi_push_dummy_call: sp=%s allocated %ld\n",
4568 paddress (gdbarch
, sp
),
4569 (long) align_up (arg_space
, 16));
4571 /* Initialize the integer and float register pointers. */
4572 argreg
= MIPS_A0_REGNUM
;
4573 float_argreg
= mips_fpa0_regnum (gdbarch
);
4575 /* The struct_return pointer occupies the first parameter-passing reg. */
4576 if (return_method
== return_method_struct
)
4579 gdb_printf (gdb_stdlog
,
4580 "mips_eabi_push_dummy_call: "
4581 "struct_return reg=%d %s\n",
4582 argreg
, paddress (gdbarch
, struct_addr
));
4583 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4586 /* Now load as many as possible of the first arguments into
4587 registers, and push the rest onto the stack. Loop thru args
4588 from first to last. */
4589 for (argnum
= 0; argnum
< nargs
; argnum
++)
4591 const gdb_byte
*val
;
4592 /* This holds the address of structures that are passed by
4594 gdb_byte ref_valbuf
[MAX_MIPS_ABI_REGSIZE
];
4595 struct value
*arg
= args
[argnum
];
4596 struct type
*arg_type
= check_typedef (value_type (arg
));
4597 int len
= arg_type
->length ();
4598 enum type_code typecode
= arg_type
->code ();
4601 gdb_printf (gdb_stdlog
,
4602 "mips_eabi_push_dummy_call: %d len=%d type=%d",
4603 argnum
+ 1, len
, (int) typecode
);
4605 /* The EABI passes structures that do not fit in a register by
4607 if (len
> abi_regsize
4608 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
4610 gdb_assert (abi_regsize
<= ARRAY_SIZE (ref_valbuf
));
4611 store_unsigned_integer (ref_valbuf
, abi_regsize
, byte_order
,
4612 value_address (arg
));
4613 typecode
= TYPE_CODE_PTR
;
4617 gdb_printf (gdb_stdlog
, " push");
4620 val
= value_contents (arg
).data ();
4622 /* 32-bit ABIs always start floating point arguments in an
4623 even-numbered floating point register. Round the FP register
4624 up before the check to see if there are any FP registers
4625 left. Non MIPS_EABI targets also pass the FP in the integer
4626 registers so also round up normal registers. */
4627 if (abi_regsize
< 8 && fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4629 if ((float_argreg
& 1))
4633 /* Floating point arguments passed in registers have to be
4634 treated specially. On 32-bit architectures, doubles
4635 are passed in register pairs; the even register gets
4636 the low word, and the odd register gets the high word.
4637 On non-EABI processors, the first two floating point arguments are
4638 also copied to general registers, because MIPS16 functions
4639 don't use float registers for arguments. This duplication of
4640 arguments in general registers can't hurt non-MIPS16 functions
4641 because those registers are normally skipped. */
4642 /* MIPS_EABI squeezes a struct that contains a single floating
4643 point value into an FP register instead of pushing it onto the
4645 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4646 && float_argreg
<= mips_last_fp_arg_regnum (gdbarch
))
4648 /* EABI32 will pass doubles in consecutive registers, even on
4649 64-bit cores. At one time, we used to check the size of
4650 `float_argreg' to determine whether or not to pass doubles
4651 in consecutive registers, but this is not sufficient for
4652 making the ABI determination. */
4653 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
4655 int low_offset
= gdbarch_byte_order (gdbarch
)
4656 == BFD_ENDIAN_BIG
? 4 : 0;
4659 /* Write the low word of the double to the even register(s). */
4660 regval
= extract_signed_integer (val
+ low_offset
,
4663 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
4664 float_argreg
, phex (regval
, 4));
4665 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4667 /* Write the high word of the double to the odd register(s). */
4668 regval
= extract_signed_integer (val
+ 4 - low_offset
,
4671 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
4672 float_argreg
, phex (regval
, 4));
4673 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4677 /* This is a floating point value that fits entirely
4678 in a single register. */
4679 /* On 32 bit ABI's the float_argreg is further adjusted
4680 above to ensure that it is even register aligned. */
4681 LONGEST regval
= extract_signed_integer (val
, len
, byte_order
);
4683 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
4684 float_argreg
, phex (regval
, len
));
4685 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4690 /* Copy the argument to general registers or the stack in
4691 register-sized pieces. Large arguments are split between
4692 registers and stack. */
4693 /* Note: structs whose size is not a multiple of abi_regsize
4694 are treated specially: Irix cc passes
4695 them in registers where gcc sometimes puts them on the
4696 stack. For maximum compatibility, we will put them in
4698 int odd_sized_struct
= (len
> abi_regsize
&& len
% abi_regsize
!= 0);
4700 /* Note: Floating-point values that didn't fit into an FP
4701 register are only written to memory. */
4704 /* Remember if the argument was written to the stack. */
4705 int stack_used_p
= 0;
4706 int partial_len
= (len
< abi_regsize
? len
: abi_regsize
);
4709 gdb_printf (gdb_stdlog
, " -- partial=%d",
4712 /* Write this portion of the argument to the stack. */
4713 if (argreg
> mips_last_arg_regnum (gdbarch
)
4715 || fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4717 /* Should shorter than int integer values be
4718 promoted to int before being stored? */
4719 int longword_offset
= 0;
4722 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4724 if (abi_regsize
== 8
4725 && (typecode
== TYPE_CODE_INT
4726 || typecode
== TYPE_CODE_PTR
4727 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
4728 longword_offset
= abi_regsize
- len
;
4729 else if ((typecode
== TYPE_CODE_STRUCT
4730 || typecode
== TYPE_CODE_UNION
)
4731 && arg_type
->length () < abi_regsize
)
4732 longword_offset
= abi_regsize
- len
;
4737 gdb_printf (gdb_stdlog
, " - stack_offset=%s",
4738 paddress (gdbarch
, stack_offset
));
4739 gdb_printf (gdb_stdlog
, " longword_offset=%s",
4740 paddress (gdbarch
, longword_offset
));
4743 addr
= sp
+ stack_offset
+ longword_offset
;
4748 gdb_printf (gdb_stdlog
, " @%s ",
4749 paddress (gdbarch
, addr
));
4750 for (i
= 0; i
< partial_len
; i
++)
4752 gdb_printf (gdb_stdlog
, "%02x",
4756 write_memory (addr
, val
, partial_len
);
4759 /* Note!!! This is NOT an else clause. Odd sized
4760 structs may go thru BOTH paths. Floating point
4761 arguments will not. */
4762 /* Write this portion of the argument to a general
4763 purpose register. */
4764 if (argreg
<= mips_last_arg_regnum (gdbarch
)
4765 && !fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4768 extract_signed_integer (val
, partial_len
, byte_order
);
4771 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
4773 phex (regval
, abi_regsize
));
4774 regcache_cooked_write_signed (regcache
, argreg
, regval
);
4781 /* Compute the offset into the stack at which we will
4782 copy the next parameter.
4784 In the new EABI (and the NABI32), the stack_offset
4785 only needs to be adjusted when it has been used. */
4788 stack_offset
+= align_up (partial_len
, abi_regsize
);
4792 gdb_printf (gdb_stdlog
, "\n");
4795 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4797 /* Return adjusted stack pointer. */
4801 /* Determine the return value convention being used. */
4803 static enum return_value_convention
4804 mips_eabi_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
4805 struct type
*type
, struct regcache
*regcache
,
4806 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4808 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
4809 int fp_return_type
= 0;
4810 int offset
, regnum
, xfer
;
4812 if (type
->length () > 2 * mips_abi_regsize (gdbarch
))
4813 return RETURN_VALUE_STRUCT_CONVENTION
;
4815 /* Floating point type? */
4816 if (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4818 if (type
->code () == TYPE_CODE_FLT
)
4820 /* Structs with a single field of float type
4821 are returned in a floating point register. */
4822 if ((type
->code () == TYPE_CODE_STRUCT
4823 || type
->code () == TYPE_CODE_UNION
)
4824 && type
->num_fields () == 1)
4826 struct type
*fieldtype
= type
->field (0).type ();
4828 if (check_typedef (fieldtype
)->code () == TYPE_CODE_FLT
)
4835 /* A floating-point value belongs in the least significant part
4838 gdb_printf (gdb_stderr
, "Return float in $fp0\n");
4839 regnum
= mips_regnum (gdbarch
)->fp0
;
4843 /* An integer value goes in V0/V1. */
4845 gdb_printf (gdb_stderr
, "Return scalar in $v0\n");
4846 regnum
= MIPS_V0_REGNUM
;
4849 offset
< type
->length ();
4850 offset
+= mips_abi_regsize (gdbarch
), regnum
++)
4852 xfer
= mips_abi_regsize (gdbarch
);
4853 if (offset
+ xfer
> type
->length ())
4854 xfer
= type
->length () - offset
;
4855 mips_xfer_register (gdbarch
, regcache
,
4856 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
4857 gdbarch_byte_order (gdbarch
), readbuf
, writebuf
,
4861 return RETURN_VALUE_REGISTER_CONVENTION
;
4865 /* N32/N64 ABI stuff. */
4867 /* Search for a naturally aligned double at OFFSET inside a struct
4868 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
4872 mips_n32n64_fp_arg_chunk_p (struct gdbarch
*gdbarch
, struct type
*arg_type
,
4877 if (arg_type
->code () != TYPE_CODE_STRUCT
)
4880 if (mips_get_fpu_type (gdbarch
) != MIPS_FPU_DOUBLE
)
4883 if (arg_type
->length () < offset
+ MIPS64_REGSIZE
)
4886 for (i
= 0; i
< arg_type
->num_fields (); i
++)
4889 struct type
*field_type
;
4891 /* We're only looking at normal fields. */
4892 if (field_is_static (&arg_type
->field (i
))
4893 || (arg_type
->field (i
).loc_bitpos () % 8) != 0)
4896 /* If we have gone past the offset, there is no double to pass. */
4897 pos
= arg_type
->field (i
).loc_bitpos () / 8;
4901 field_type
= check_typedef (arg_type
->field (i
).type ());
4903 /* If this field is entirely before the requested offset, go
4904 on to the next one. */
4905 if (pos
+ field_type
->length () <= offset
)
4908 /* If this is our special aligned double, we can stop. */
4909 if (field_type
->code () == TYPE_CODE_FLT
4910 && field_type
->length () == MIPS64_REGSIZE
)
4913 /* This field starts at or before the requested offset, and
4914 overlaps it. If it is a structure, recurse inwards. */
4915 return mips_n32n64_fp_arg_chunk_p (gdbarch
, field_type
, offset
- pos
);
4922 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4923 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4924 int nargs
, struct value
**args
, CORE_ADDR sp
,
4925 function_call_return_method return_method
,
4926 CORE_ADDR struct_addr
)
4932 int stack_offset
= 0;
4933 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4934 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4936 /* For shared libraries, "t9" needs to point at the function
4938 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4940 /* Set the return address register to point to the entry point of
4941 the program, where a breakpoint lies in wait. */
4942 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4944 /* First ensure that the stack and structure return address (if any)
4945 are properly aligned. The stack has to be at least 64-bit
4946 aligned even on 32-bit machines, because doubles must be 64-bit
4947 aligned. For n32 and n64, stack frames need to be 128-bit
4948 aligned, so we round to this widest known alignment. */
4950 sp
= align_down (sp
, 16);
4951 struct_addr
= align_down (struct_addr
, 16);
4953 /* Now make space on the stack for the args. */
4954 for (argnum
= 0; argnum
< nargs
; argnum
++)
4955 arg_space
+= align_up (value_type (args
[argnum
])->length (),
4957 sp
-= align_up (arg_space
, 16);
4960 gdb_printf (gdb_stdlog
,
4961 "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n",
4962 paddress (gdbarch
, sp
),
4963 (long) align_up (arg_space
, 16));
4965 /* Initialize the integer and float register pointers. */
4966 argreg
= MIPS_A0_REGNUM
;
4967 float_argreg
= mips_fpa0_regnum (gdbarch
);
4969 /* The struct_return pointer occupies the first parameter-passing reg. */
4970 if (return_method
== return_method_struct
)
4973 gdb_printf (gdb_stdlog
,
4974 "mips_n32n64_push_dummy_call: "
4975 "struct_return reg=%d %s\n",
4976 argreg
, paddress (gdbarch
, struct_addr
));
4977 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4980 /* Now load as many as possible of the first arguments into
4981 registers, and push the rest onto the stack. Loop thru args
4982 from first to last. */
4983 for (argnum
= 0; argnum
< nargs
; argnum
++)
4985 const gdb_byte
*val
;
4986 struct value
*arg
= args
[argnum
];
4987 struct type
*arg_type
= check_typedef (value_type (arg
));
4988 int len
= arg_type
->length ();
4989 enum type_code typecode
= arg_type
->code ();
4992 gdb_printf (gdb_stdlog
,
4993 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
4994 argnum
+ 1, len
, (int) typecode
);
4996 val
= value_contents (arg
).data ();
4998 /* A 128-bit long double value requires an even-odd pair of
4999 floating-point registers. */
5001 && fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5002 && (float_argreg
& 1))
5008 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5009 && argreg
<= mips_last_arg_regnum (gdbarch
))
5011 /* This is a floating point value that fits entirely
5012 in a single register or a pair of registers. */
5013 int reglen
= (len
<= MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
5014 LONGEST regval
= extract_unsigned_integer (val
, reglen
, byte_order
);
5016 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
5017 float_argreg
, phex (regval
, reglen
));
5018 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
5021 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
5022 argreg
, phex (regval
, reglen
));
5023 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5028 regval
= extract_unsigned_integer (val
+ reglen
,
5029 reglen
, byte_order
);
5031 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
5032 float_argreg
, phex (regval
, reglen
));
5033 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
5036 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
5037 argreg
, phex (regval
, reglen
));
5038 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5045 /* Copy the argument to general registers or the stack in
5046 register-sized pieces. Large arguments are split between
5047 registers and stack. */
5048 /* For N32/N64, structs, unions, or other composite types are
5049 treated as a sequence of doublewords, and are passed in integer
5050 or floating point registers as though they were simple scalar
5051 parameters to the extent that they fit, with any excess on the
5052 stack packed according to the normal memory layout of the
5054 The caller does not reserve space for the register arguments;
5055 the callee is responsible for reserving it if required. */
5056 /* Note: Floating-point values that didn't fit into an FP
5057 register are only written to memory. */
5060 /* Remember if the argument was written to the stack. */
5061 int stack_used_p
= 0;
5062 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
5065 gdb_printf (gdb_stdlog
, " -- partial=%d",
5068 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
5069 gdb_assert (argreg
> mips_last_arg_regnum (gdbarch
));
5071 /* Write this portion of the argument to the stack. */
5072 if (argreg
> mips_last_arg_regnum (gdbarch
))
5074 /* Should shorter than int integer values be
5075 promoted to int before being stored? */
5076 int longword_offset
= 0;
5079 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5081 if ((typecode
== TYPE_CODE_INT
5082 || typecode
== TYPE_CODE_PTR
)
5084 longword_offset
= MIPS64_REGSIZE
- len
;
5089 gdb_printf (gdb_stdlog
, " - stack_offset=%s",
5090 paddress (gdbarch
, stack_offset
));
5091 gdb_printf (gdb_stdlog
, " longword_offset=%s",
5092 paddress (gdbarch
, longword_offset
));
5095 addr
= sp
+ stack_offset
+ longword_offset
;
5100 gdb_printf (gdb_stdlog
, " @%s ",
5101 paddress (gdbarch
, addr
));
5102 for (i
= 0; i
< partial_len
; i
++)
5104 gdb_printf (gdb_stdlog
, "%02x",
5108 write_memory (addr
, val
, partial_len
);
5111 /* Note!!! This is NOT an else clause. Odd sized
5112 structs may go thru BOTH paths. */
5113 /* Write this portion of the argument to a general
5114 purpose register. */
5115 if (argreg
<= mips_last_arg_regnum (gdbarch
))
5119 /* Sign extend pointers, 32-bit integers and signed
5120 16-bit and 8-bit integers; everything else is taken
5123 if ((partial_len
== 4
5124 && (typecode
== TYPE_CODE_PTR
5125 || typecode
== TYPE_CODE_INT
))
5127 && typecode
== TYPE_CODE_INT
5128 && !arg_type
->is_unsigned ()))
5129 regval
= extract_signed_integer (val
, partial_len
,
5132 regval
= extract_unsigned_integer (val
, partial_len
,
5135 /* A non-floating-point argument being passed in a
5136 general register. If a struct or union, and if
5137 the remaining length is smaller than the register
5138 size, we have to adjust the register value on
5141 It does not seem to be necessary to do the
5142 same for integral types. */
5144 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
5145 && partial_len
< MIPS64_REGSIZE
5146 && (typecode
== TYPE_CODE_STRUCT
5147 || typecode
== TYPE_CODE_UNION
))
5148 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
5152 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
5154 phex (regval
, MIPS64_REGSIZE
));
5155 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5157 if (mips_n32n64_fp_arg_chunk_p (gdbarch
, arg_type
,
5158 arg_type
->length () - len
))
5161 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
5163 phex (regval
, MIPS64_REGSIZE
));
5164 regcache_cooked_write_unsigned (regcache
, float_argreg
,
5175 /* Compute the offset into the stack at which we will
5176 copy the next parameter.
5178 In N32 (N64?), the stack_offset only needs to be
5179 adjusted when it has been used. */
5182 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
5186 gdb_printf (gdb_stdlog
, "\n");
5189 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
5191 /* Return adjusted stack pointer. */
5195 static enum return_value_convention
5196 mips_n32n64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
5197 struct type
*type
, struct regcache
*regcache
,
5198 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5200 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
5202 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
5204 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
5205 if needed), as appropriate for the type. Composite results (struct,
5206 union, or array) are returned in $2/$f0 and $3/$f2 according to the
5209 * A struct with only one or two floating point fields is returned in $f0
5210 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
5213 * Any other composite results of at most 128 bits are returned in
5214 $2 (first 64 bits) and $3 (remainder, if necessary).
5216 * Larger composite results are handled by converting the function to a
5217 procedure with an implicit first parameter, which is a pointer to an area
5218 reserved by the caller to receive the result. [The o32-bit ABI requires
5219 that all composite results be handled by conversion to implicit first
5220 parameters. The MIPS/SGI Fortran implementation has always made a
5221 specific exception to return COMPLEX results in the floating point
5224 From MIPSpro Assembly Language Programmer's Guide, Document Number:
5229 Name fgregdef.h) Use and Linkage
5230 -----------------------------------------------------------------
5231 $f0, $f2 fv0, fv1 Hold results of floating-point type function
5232 ($f0) and complex type function ($f0 has the
5233 real part, $f2 has the imaginary part.) */
5235 if (type
->length () > 2 * MIPS64_REGSIZE
)
5236 return RETURN_VALUE_STRUCT_CONVENTION
;
5237 else if ((type
->code () == TYPE_CODE_COMPLEX
5238 || (type
->code () == TYPE_CODE_FLT
&& type
->length () == 16))
5239 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5241 /* A complex value of up to 128 bits in width as well as a 128-bit
5242 floating-point value goes in both $f0 and $f2. A single complex
5243 value is held in the lower halves only of the respective registers.
5244 The two registers are used in the same as memory order, so the
5245 bytes with the lower memory address are in $f0. */
5247 gdb_printf (gdb_stderr
, "Return float in $f0 and $f2\n");
5248 mips_xfer_register (gdbarch
, regcache
,
5249 (gdbarch_num_regs (gdbarch
)
5250 + mips_regnum (gdbarch
)->fp0
),
5251 type
->length () / 2, gdbarch_byte_order (gdbarch
),
5252 readbuf
, writebuf
, 0);
5253 mips_xfer_register (gdbarch
, regcache
,
5254 (gdbarch_num_regs (gdbarch
)
5255 + mips_regnum (gdbarch
)->fp0
+ 2),
5256 type
->length () / 2, gdbarch_byte_order (gdbarch
),
5257 readbuf
? readbuf
+ type
->length () / 2 : readbuf
,
5259 ? writebuf
+ type
->length () / 2 : writebuf
), 0);
5260 return RETURN_VALUE_REGISTER_CONVENTION
;
5262 else if (type
->code () == TYPE_CODE_FLT
5263 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5265 /* A single or double floating-point value that fits in FP0. */
5267 gdb_printf (gdb_stderr
, "Return float in $fp0\n");
5268 mips_xfer_register (gdbarch
, regcache
,
5269 (gdbarch_num_regs (gdbarch
)
5270 + mips_regnum (gdbarch
)->fp0
),
5272 gdbarch_byte_order (gdbarch
),
5273 readbuf
, writebuf
, 0);
5274 return RETURN_VALUE_REGISTER_CONVENTION
;
5276 else if (type
->code () == TYPE_CODE_STRUCT
5277 && type
->num_fields () <= 2
5278 && type
->num_fields () >= 1
5279 && ((type
->num_fields () == 1
5280 && (check_typedef (type
->field (0).type ())->code ()
5282 || (type
->num_fields () == 2
5283 && (check_typedef (type
->field (0).type ())->code ()
5285 && (check_typedef (type
->field (1).type ())->code ()
5286 == TYPE_CODE_FLT
))))
5288 /* A struct that contains one or two floats. Each value is part
5289 in the least significant part of their floating point
5290 register (or GPR, for soft float). */
5293 for (field
= 0, regnum
= (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
5294 ? mips_regnum (gdbarch
)->fp0
5296 field
< type
->num_fields (); field
++, regnum
+= 2)
5298 int offset
= type
->field (field
).loc_bitpos () / TARGET_CHAR_BIT
;
5300 gdb_printf (gdb_stderr
, "Return float struct+%d\n",
5302 if (type
->field (field
).type ()->length () == 16)
5304 /* A 16-byte long double field goes in two consecutive
5306 mips_xfer_register (gdbarch
, regcache
,
5307 gdbarch_num_regs (gdbarch
) + regnum
,
5309 gdbarch_byte_order (gdbarch
),
5310 readbuf
, writebuf
, offset
);
5311 mips_xfer_register (gdbarch
, regcache
,
5312 gdbarch_num_regs (gdbarch
) + regnum
+ 1,
5314 gdbarch_byte_order (gdbarch
),
5315 readbuf
, writebuf
, offset
+ 8);
5318 mips_xfer_register (gdbarch
, regcache
,
5319 gdbarch_num_regs (gdbarch
) + regnum
,
5320 type
->field (field
).type ()->length (),
5321 gdbarch_byte_order (gdbarch
),
5322 readbuf
, writebuf
, offset
);
5324 return RETURN_VALUE_REGISTER_CONVENTION
;
5326 else if (type
->code () == TYPE_CODE_STRUCT
5327 || type
->code () == TYPE_CODE_UNION
5328 || type
->code () == TYPE_CODE_ARRAY
)
5330 /* A composite type. Extract the left justified value,
5331 regardless of the byte order. I.e. DO NOT USE
5335 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5336 offset
< type
->length ();
5337 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5339 int xfer
= register_size (gdbarch
, regnum
);
5340 if (offset
+ xfer
> type
->length ())
5341 xfer
= type
->length () - offset
;
5343 gdb_printf (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5344 offset
, xfer
, regnum
);
5345 mips_xfer_register (gdbarch
, regcache
,
5346 gdbarch_num_regs (gdbarch
) + regnum
,
5347 xfer
, BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
,
5350 return RETURN_VALUE_REGISTER_CONVENTION
;
5354 /* A scalar extract each part but least-significant-byte
5358 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5359 offset
< type
->length ();
5360 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5362 int xfer
= register_size (gdbarch
, regnum
);
5363 if (offset
+ xfer
> type
->length ())
5364 xfer
= type
->length () - offset
;
5366 gdb_printf (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5367 offset
, xfer
, regnum
);
5368 mips_xfer_register (gdbarch
, regcache
,
5369 gdbarch_num_regs (gdbarch
) + regnum
,
5370 xfer
, gdbarch_byte_order (gdbarch
),
5371 readbuf
, writebuf
, offset
);
5373 return RETURN_VALUE_REGISTER_CONVENTION
;
5377 /* Which registers to use for passing floating-point values between
5378 function calls, one of floating-point, general and both kinds of
5379 registers. O32 and O64 use different register kinds for standard
5380 MIPS and MIPS16 code; to make the handling of cases where we may
5381 not know what kind of code is being used (e.g. no debug information)
5382 easier we sometimes use both kinds. */
5391 /* O32 ABI stuff. */
5394 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
5395 struct regcache
*regcache
, CORE_ADDR bp_addr
,
5396 int nargs
, struct value
**args
, CORE_ADDR sp
,
5397 function_call_return_method return_method
,
5398 CORE_ADDR struct_addr
)
5404 int stack_offset
= 0;
5405 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5406 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
5408 /* For shared libraries, "t9" needs to point at the function
5410 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
5412 /* Set the return address register to point to the entry point of
5413 the program, where a breakpoint lies in wait. */
5414 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
5416 /* First ensure that the stack and structure return address (if any)
5417 are properly aligned. The stack has to be at least 64-bit
5418 aligned even on 32-bit machines, because doubles must be 64-bit
5419 aligned. For n32 and n64, stack frames need to be 128-bit
5420 aligned, so we round to this widest known alignment. */
5422 sp
= align_down (sp
, 16);
5423 struct_addr
= align_down (struct_addr
, 16);
5425 /* Now make space on the stack for the args. */
5426 for (argnum
= 0; argnum
< nargs
; argnum
++)
5428 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
5430 /* Align to double-word if necessary. */
5431 if (mips_type_needs_double_align (arg_type
))
5432 arg_space
= align_up (arg_space
, MIPS32_REGSIZE
* 2);
5433 /* Allocate space on the stack. */
5434 arg_space
+= align_up (arg_type
->length (), MIPS32_REGSIZE
);
5436 sp
-= align_up (arg_space
, 16);
5439 gdb_printf (gdb_stdlog
,
5440 "mips_o32_push_dummy_call: sp=%s allocated %ld\n",
5441 paddress (gdbarch
, sp
),
5442 (long) align_up (arg_space
, 16));
5444 /* Initialize the integer and float register pointers. */
5445 argreg
= MIPS_A0_REGNUM
;
5446 float_argreg
= mips_fpa0_regnum (gdbarch
);
5448 /* The struct_return pointer occupies the first parameter-passing reg. */
5449 if (return_method
== return_method_struct
)
5452 gdb_printf (gdb_stdlog
,
5453 "mips_o32_push_dummy_call: "
5454 "struct_return reg=%d %s\n",
5455 argreg
, paddress (gdbarch
, struct_addr
));
5456 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
5457 stack_offset
+= MIPS32_REGSIZE
;
5460 /* Now load as many as possible of the first arguments into
5461 registers, and push the rest onto the stack. Loop thru args
5462 from first to last. */
5463 for (argnum
= 0; argnum
< nargs
; argnum
++)
5465 const gdb_byte
*val
;
5466 struct value
*arg
= args
[argnum
];
5467 struct type
*arg_type
= check_typedef (value_type (arg
));
5468 int len
= arg_type
->length ();
5469 enum type_code typecode
= arg_type
->code ();
5472 gdb_printf (gdb_stdlog
,
5473 "mips_o32_push_dummy_call: %d len=%d type=%d",
5474 argnum
+ 1, len
, (int) typecode
);
5476 val
= value_contents (arg
).data ();
5478 /* 32-bit ABIs always start floating point arguments in an
5479 even-numbered floating point register. Round the FP register
5480 up before the check to see if there are any FP registers
5481 left. O32 targets also pass the FP in the integer registers
5482 so also round up normal registers. */
5483 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
5485 if ((float_argreg
& 1))
5489 /* Floating point arguments passed in registers have to be
5490 treated specially. On 32-bit architectures, doubles are
5491 passed in register pairs; the even FP register gets the
5492 low word, and the odd FP register gets the high word.
5493 On O32, the first two floating point arguments are also
5494 copied to general registers, following their memory order,
5495 because MIPS16 functions don't use float registers for
5496 arguments. This duplication of arguments in general
5497 registers can't hurt non-MIPS16 functions, because those
5498 registers are normally skipped. */
5500 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5501 && float_argreg
<= mips_last_fp_arg_regnum (gdbarch
))
5503 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
5505 int freg_offset
= gdbarch_byte_order (gdbarch
)
5506 == BFD_ENDIAN_BIG
? 1 : 0;
5507 unsigned long regval
;
5510 regval
= extract_unsigned_integer (val
, 4, byte_order
);
5512 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
5513 float_argreg
+ freg_offset
,
5515 regcache_cooked_write_unsigned (regcache
,
5516 float_argreg
++ + freg_offset
,
5519 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
5520 argreg
, phex (regval
, 4));
5521 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5524 regval
= extract_unsigned_integer (val
+ 4, 4, byte_order
);
5526 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
5527 float_argreg
- freg_offset
,
5529 regcache_cooked_write_unsigned (regcache
,
5530 float_argreg
++ - freg_offset
,
5533 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
5534 argreg
, phex (regval
, 4));
5535 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5539 /* This is a floating point value that fits entirely
5540 in a single register. */
5541 /* On 32 bit ABI's the float_argreg is further adjusted
5542 above to ensure that it is even register aligned. */
5543 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
5545 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
5546 float_argreg
, phex (regval
, len
));
5547 regcache_cooked_write_unsigned (regcache
,
5548 float_argreg
++, regval
);
5549 /* Although two FP registers are reserved for each
5550 argument, only one corresponding integer register is
5553 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
5554 argreg
, phex (regval
, len
));
5555 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5557 /* Reserve space for the FP register. */
5558 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
5562 /* Copy the argument to general registers or the stack in
5563 register-sized pieces. Large arguments are split between
5564 registers and stack. */
5565 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
5566 are treated specially: Irix cc passes
5567 them in registers where gcc sometimes puts them on the
5568 stack. For maximum compatibility, we will put them in
5570 int odd_sized_struct
= (len
> MIPS32_REGSIZE
5571 && len
% MIPS32_REGSIZE
!= 0);
5572 /* Structures should be aligned to eight bytes (even arg registers)
5573 on MIPS_ABI_O32, if their first member has double precision. */
5574 if (mips_type_needs_double_align (arg_type
))
5579 stack_offset
+= MIPS32_REGSIZE
;
5584 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
5587 gdb_printf (gdb_stdlog
, " -- partial=%d",
5590 /* Write this portion of the argument to the stack. */
5591 if (argreg
> mips_last_arg_regnum (gdbarch
)
5592 || odd_sized_struct
)
5594 /* Should shorter than int integer values be
5595 promoted to int before being stored? */
5596 int longword_offset
= 0;
5601 gdb_printf (gdb_stdlog
, " - stack_offset=%s",
5602 paddress (gdbarch
, stack_offset
));
5603 gdb_printf (gdb_stdlog
, " longword_offset=%s",
5604 paddress (gdbarch
, longword_offset
));
5607 addr
= sp
+ stack_offset
+ longword_offset
;
5612 gdb_printf (gdb_stdlog
, " @%s ",
5613 paddress (gdbarch
, addr
));
5614 for (i
= 0; i
< partial_len
; i
++)
5616 gdb_printf (gdb_stdlog
, "%02x",
5620 write_memory (addr
, val
, partial_len
);
5623 /* Note!!! This is NOT an else clause. Odd sized
5624 structs may go thru BOTH paths. */
5625 /* Write this portion of the argument to a general
5626 purpose register. */
5627 if (argreg
<= mips_last_arg_regnum (gdbarch
))
5629 LONGEST regval
= extract_signed_integer (val
, partial_len
,
5631 /* Value may need to be sign extended, because
5632 mips_isa_regsize() != mips_abi_regsize(). */
5634 /* A non-floating-point argument being passed in a
5635 general register. If a struct or union, and if
5636 the remaining length is smaller than the register
5637 size, we have to adjust the register value on
5640 It does not seem to be necessary to do the
5641 same for integral types.
5643 Also don't do this adjustment on O64 binaries.
5645 cagney/2001-07-23: gdb/179: Also, GCC, when
5646 outputting LE O32 with sizeof (struct) <
5647 mips_abi_regsize(), generates a left shift
5648 as part of storing the argument in a register
5649 (the left shift isn't generated when
5650 sizeof (struct) >= mips_abi_regsize()). Since
5651 it is quite possible that this is GCC
5652 contradicting the LE/O32 ABI, GDB has not been
5653 adjusted to accommodate this. Either someone
5654 needs to demonstrate that the LE/O32 ABI
5655 specifies such a left shift OR this new ABI gets
5656 identified as such and GDB gets tweaked
5659 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
5660 && partial_len
< MIPS32_REGSIZE
5661 && (typecode
== TYPE_CODE_STRUCT
5662 || typecode
== TYPE_CODE_UNION
))
5663 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
5667 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
5669 phex (regval
, MIPS32_REGSIZE
));
5670 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5673 /* Prevent subsequent floating point arguments from
5674 being passed in floating point registers. */
5675 float_argreg
= mips_last_fp_arg_regnum (gdbarch
) + 1;
5681 /* Compute the offset into the stack at which we will
5682 copy the next parameter.
5684 In older ABIs, the caller reserved space for
5685 registers that contained arguments. This was loosely
5686 refered to as their "home". Consequently, space is
5687 always allocated. */
5689 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
5693 gdb_printf (gdb_stdlog
, "\n");
5696 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
5698 /* Return adjusted stack pointer. */
5702 static enum return_value_convention
5703 mips_o32_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
5704 struct type
*type
, struct regcache
*regcache
,
5705 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5707 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
5708 int mips16
= mips_pc_is_mips16 (gdbarch
, func_addr
);
5709 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
5710 enum mips_fval_reg fval_reg
;
5712 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
5713 if (type
->code () == TYPE_CODE_STRUCT
5714 || type
->code () == TYPE_CODE_UNION
5715 || type
->code () == TYPE_CODE_ARRAY
)
5716 return RETURN_VALUE_STRUCT_CONVENTION
;
5717 else if (type
->code () == TYPE_CODE_FLT
5718 && type
->length () == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5720 /* A single-precision floating-point value. If reading in or copying,
5721 then we get it from/put it to FP0 for standard MIPS code or GPR2
5722 for MIPS16 code. If writing out only, then we put it to both FP0
5723 and GPR2. We do not support reading in with no function known, if
5724 this safety check ever triggers, then we'll have to try harder. */
5725 gdb_assert (function
|| !readbuf
);
5730 gdb_printf (gdb_stderr
, "Return float in $fp0\n");
5733 gdb_printf (gdb_stderr
, "Return float in $2\n");
5735 case mips_fval_both
:
5736 gdb_printf (gdb_stderr
, "Return float in $fp0 and $2\n");
5739 if (fval_reg
!= mips_fval_gpr
)
5740 mips_xfer_register (gdbarch
, regcache
,
5741 (gdbarch_num_regs (gdbarch
)
5742 + mips_regnum (gdbarch
)->fp0
),
5744 gdbarch_byte_order (gdbarch
),
5745 readbuf
, writebuf
, 0);
5746 if (fval_reg
!= mips_fval_fpr
)
5747 mips_xfer_register (gdbarch
, regcache
,
5748 gdbarch_num_regs (gdbarch
) + 2,
5750 gdbarch_byte_order (gdbarch
),
5751 readbuf
, writebuf
, 0);
5752 return RETURN_VALUE_REGISTER_CONVENTION
;
5754 else if (type
->code () == TYPE_CODE_FLT
5755 && type
->length () == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5757 /* A double-precision floating-point value. If reading in or copying,
5758 then we get it from/put it to FP1 and FP0 for standard MIPS code or
5759 GPR2 and GPR3 for MIPS16 code. If writing out only, then we put it
5760 to both FP1/FP0 and GPR2/GPR3. We do not support reading in with
5761 no function known, if this safety check ever triggers, then we'll
5762 have to try harder. */
5763 gdb_assert (function
|| !readbuf
);
5768 gdb_printf (gdb_stderr
, "Return float in $fp1/$fp0\n");
5771 gdb_printf (gdb_stderr
, "Return float in $2/$3\n");
5773 case mips_fval_both
:
5774 gdb_printf (gdb_stderr
,
5775 "Return float in $fp1/$fp0 and $2/$3\n");
5778 if (fval_reg
!= mips_fval_gpr
)
5780 /* The most significant part goes in FP1, and the least significant
5782 switch (gdbarch_byte_order (gdbarch
))
5784 case BFD_ENDIAN_LITTLE
:
5785 mips_xfer_register (gdbarch
, regcache
,
5786 (gdbarch_num_regs (gdbarch
)
5787 + mips_regnum (gdbarch
)->fp0
+ 0),
5788 4, gdbarch_byte_order (gdbarch
),
5789 readbuf
, writebuf
, 0);
5790 mips_xfer_register (gdbarch
, regcache
,
5791 (gdbarch_num_regs (gdbarch
)
5792 + mips_regnum (gdbarch
)->fp0
+ 1),
5793 4, gdbarch_byte_order (gdbarch
),
5794 readbuf
, writebuf
, 4);
5796 case BFD_ENDIAN_BIG
:
5797 mips_xfer_register (gdbarch
, regcache
,
5798 (gdbarch_num_regs (gdbarch
)
5799 + mips_regnum (gdbarch
)->fp0
+ 1),
5800 4, gdbarch_byte_order (gdbarch
),
5801 readbuf
, writebuf
, 0);
5802 mips_xfer_register (gdbarch
, regcache
,
5803 (gdbarch_num_regs (gdbarch
)
5804 + mips_regnum (gdbarch
)->fp0
+ 0),
5805 4, gdbarch_byte_order (gdbarch
),
5806 readbuf
, writebuf
, 4);
5809 internal_error (__FILE__
, __LINE__
, _("bad switch"));
5812 if (fval_reg
!= mips_fval_fpr
)
5814 /* The two 32-bit parts are always placed in GPR2 and GPR3
5815 following these registers' memory order. */
5816 mips_xfer_register (gdbarch
, regcache
,
5817 gdbarch_num_regs (gdbarch
) + 2,
5818 4, gdbarch_byte_order (gdbarch
),
5819 readbuf
, writebuf
, 0);
5820 mips_xfer_register (gdbarch
, regcache
,
5821 gdbarch_num_regs (gdbarch
) + 3,
5822 4, gdbarch_byte_order (gdbarch
),
5823 readbuf
, writebuf
, 4);
5825 return RETURN_VALUE_REGISTER_CONVENTION
;
5828 else if (type
->code () == TYPE_CODE_STRUCT
5829 && type
->num_fields () <= 2
5830 && type
->num_fields () >= 1
5831 && ((type
->num_fields () == 1
5832 && (TYPE_CODE (type
->field (0).type ())
5834 || (type
->num_fields () == 2
5835 && (TYPE_CODE (type
->field (0).type ())
5837 && (TYPE_CODE (type
->field (1).type ())
5839 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5841 /* A struct that contains one or two floats. Each value is part
5842 in the least significant part of their floating point
5846 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
5847 field
< type
->num_fields (); field
++, regnum
+= 2)
5849 int offset
= (type
->fields ()[field
].loc_bitpos () / TARGET_CHAR_BIT
);
5851 gdb_printf (gdb_stderr
, "Return float struct+%d\n",
5853 mips_xfer_register (gdbarch
, regcache
,
5854 gdbarch_num_regs (gdbarch
) + regnum
,
5855 TYPE_LENGTH (type
->field (field
).type ()),
5856 gdbarch_byte_order (gdbarch
),
5857 readbuf
, writebuf
, offset
);
5859 return RETURN_VALUE_REGISTER_CONVENTION
;
5863 else if (type
->code () == TYPE_CODE_STRUCT
5864 || type
->code () == TYPE_CODE_UNION
)
5866 /* A structure or union. Extract the left justified value,
5867 regardless of the byte order. I.e. DO NOT USE
5871 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5872 offset
< type
->length ();
5873 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5875 int xfer
= register_size (gdbarch
, regnum
);
5876 if (offset
+ xfer
> type
->length ())
5877 xfer
= type
->length () - offset
;
5879 gdb_printf (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5880 offset
, xfer
, regnum
);
5881 mips_xfer_register (gdbarch
, regcache
,
5882 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
5883 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
5885 return RETURN_VALUE_REGISTER_CONVENTION
;
5890 /* A scalar extract each part but least-significant-byte
5891 justified. o32 thinks registers are 4 byte, regardless of
5895 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5896 offset
< type
->length ();
5897 offset
+= MIPS32_REGSIZE
, regnum
++)
5899 int xfer
= MIPS32_REGSIZE
;
5900 if (offset
+ xfer
> type
->length ())
5901 xfer
= type
->length () - offset
;
5903 gdb_printf (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5904 offset
, xfer
, regnum
);
5905 mips_xfer_register (gdbarch
, regcache
,
5906 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
5907 gdbarch_byte_order (gdbarch
),
5908 readbuf
, writebuf
, offset
);
5910 return RETURN_VALUE_REGISTER_CONVENTION
;
5914 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
5918 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
5919 struct regcache
*regcache
, CORE_ADDR bp_addr
,
5921 struct value
**args
, CORE_ADDR sp
,
5922 function_call_return_method return_method
, CORE_ADDR struct_addr
)
5928 int stack_offset
= 0;
5929 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5930 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
5932 /* For shared libraries, "t9" needs to point at the function
5934 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
5936 /* Set the return address register to point to the entry point of
5937 the program, where a breakpoint lies in wait. */
5938 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
5940 /* First ensure that the stack and structure return address (if any)
5941 are properly aligned. The stack has to be at least 64-bit
5942 aligned even on 32-bit machines, because doubles must be 64-bit
5943 aligned. For n32 and n64, stack frames need to be 128-bit
5944 aligned, so we round to this widest known alignment. */
5946 sp
= align_down (sp
, 16);
5947 struct_addr
= align_down (struct_addr
, 16);
5949 /* Now make space on the stack for the args. */
5950 for (argnum
= 0; argnum
< nargs
; argnum
++)
5952 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
5954 /* Allocate space on the stack. */
5955 arg_space
+= align_up (arg_type
->length (), MIPS64_REGSIZE
);
5957 sp
-= align_up (arg_space
, 16);
5960 gdb_printf (gdb_stdlog
,
5961 "mips_o64_push_dummy_call: sp=%s allocated %ld\n",
5962 paddress (gdbarch
, sp
),
5963 (long) align_up (arg_space
, 16));
5965 /* Initialize the integer and float register pointers. */
5966 argreg
= MIPS_A0_REGNUM
;
5967 float_argreg
= mips_fpa0_regnum (gdbarch
);
5969 /* The struct_return pointer occupies the first parameter-passing reg. */
5970 if (return_method
== return_method_struct
)
5973 gdb_printf (gdb_stdlog
,
5974 "mips_o64_push_dummy_call: "
5975 "struct_return reg=%d %s\n",
5976 argreg
, paddress (gdbarch
, struct_addr
));
5977 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
5978 stack_offset
+= MIPS64_REGSIZE
;
5981 /* Now load as many as possible of the first arguments into
5982 registers, and push the rest onto the stack. Loop thru args
5983 from first to last. */
5984 for (argnum
= 0; argnum
< nargs
; argnum
++)
5986 const gdb_byte
*val
;
5987 struct value
*arg
= args
[argnum
];
5988 struct type
*arg_type
= check_typedef (value_type (arg
));
5989 int len
= arg_type
->length ();
5990 enum type_code typecode
= arg_type
->code ();
5993 gdb_printf (gdb_stdlog
,
5994 "mips_o64_push_dummy_call: %d len=%d type=%d",
5995 argnum
+ 1, len
, (int) typecode
);
5997 val
= value_contents (arg
).data ();
5999 /* Floating point arguments passed in registers have to be
6000 treated specially. On 32-bit architectures, doubles are
6001 passed in register pairs; the even FP register gets the
6002 low word, and the odd FP register gets the high word.
6003 On O64, the first two floating point arguments are also
6004 copied to general registers, because MIPS16 functions
6005 don't use float registers for arguments. This duplication
6006 of arguments in general registers can't hurt non-MIPS16
6007 functions because those registers are normally skipped. */
6009 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
6010 && float_argreg
<= mips_last_fp_arg_regnum (gdbarch
))
6012 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
6014 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
6015 float_argreg
, phex (regval
, len
));
6016 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
6018 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
6019 argreg
, phex (regval
, len
));
6020 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
6022 /* Reserve space for the FP register. */
6023 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
6027 /* Copy the argument to general registers or the stack in
6028 register-sized pieces. Large arguments are split between
6029 registers and stack. */
6030 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
6031 are treated specially: Irix cc passes them in registers
6032 where gcc sometimes puts them on the stack. For maximum
6033 compatibility, we will put them in both places. */
6034 int odd_sized_struct
= (len
> MIPS64_REGSIZE
6035 && len
% MIPS64_REGSIZE
!= 0);
6038 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
6041 gdb_printf (gdb_stdlog
, " -- partial=%d",
6044 /* Write this portion of the argument to the stack. */
6045 if (argreg
> mips_last_arg_regnum (gdbarch
)
6046 || odd_sized_struct
)
6048 /* Should shorter than int integer values be
6049 promoted to int before being stored? */
6050 int longword_offset
= 0;
6052 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6054 if ((typecode
== TYPE_CODE_INT
6055 || typecode
== TYPE_CODE_PTR
6056 || typecode
== TYPE_CODE_FLT
)
6058 longword_offset
= MIPS64_REGSIZE
- len
;
6063 gdb_printf (gdb_stdlog
, " - stack_offset=%s",
6064 paddress (gdbarch
, stack_offset
));
6065 gdb_printf (gdb_stdlog
, " longword_offset=%s",
6066 paddress (gdbarch
, longword_offset
));
6069 addr
= sp
+ stack_offset
+ longword_offset
;
6074 gdb_printf (gdb_stdlog
, " @%s ",
6075 paddress (gdbarch
, addr
));
6076 for (i
= 0; i
< partial_len
; i
++)
6078 gdb_printf (gdb_stdlog
, "%02x",
6082 write_memory (addr
, val
, partial_len
);
6085 /* Note!!! This is NOT an else clause. Odd sized
6086 structs may go thru BOTH paths. */
6087 /* Write this portion of the argument to a general
6088 purpose register. */
6089 if (argreg
<= mips_last_arg_regnum (gdbarch
))
6091 LONGEST regval
= extract_signed_integer (val
, partial_len
,
6093 /* Value may need to be sign extended, because
6094 mips_isa_regsize() != mips_abi_regsize(). */
6096 /* A non-floating-point argument being passed in a
6097 general register. If a struct or union, and if
6098 the remaining length is smaller than the register
6099 size, we have to adjust the register value on
6102 It does not seem to be necessary to do the
6103 same for integral types. */
6105 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
6106 && partial_len
< MIPS64_REGSIZE
6107 && (typecode
== TYPE_CODE_STRUCT
6108 || typecode
== TYPE_CODE_UNION
))
6109 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
6113 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
6115 phex (regval
, MIPS64_REGSIZE
));
6116 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
6119 /* Prevent subsequent floating point arguments from
6120 being passed in floating point registers. */
6121 float_argreg
= mips_last_fp_arg_regnum (gdbarch
) + 1;
6127 /* Compute the offset into the stack at which we will
6128 copy the next parameter.
6130 In older ABIs, the caller reserved space for
6131 registers that contained arguments. This was loosely
6132 refered to as their "home". Consequently, space is
6133 always allocated. */
6135 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
6139 gdb_printf (gdb_stdlog
, "\n");
6142 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
6144 /* Return adjusted stack pointer. */
6148 static enum return_value_convention
6149 mips_o64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
6150 struct type
*type
, struct regcache
*regcache
,
6151 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
6153 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
6154 int mips16
= mips_pc_is_mips16 (gdbarch
, func_addr
);
6155 enum mips_fval_reg fval_reg
;
6157 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
6158 if (type
->code () == TYPE_CODE_STRUCT
6159 || type
->code () == TYPE_CODE_UNION
6160 || type
->code () == TYPE_CODE_ARRAY
)
6161 return RETURN_VALUE_STRUCT_CONVENTION
;
6162 else if (fp_register_arg_p (gdbarch
, type
->code (), type
))
6164 /* A floating-point value. If reading in or copying, then we get it
6165 from/put it to FP0 for standard MIPS code or GPR2 for MIPS16 code.
6166 If writing out only, then we put it to both FP0 and GPR2. We do
6167 not support reading in with no function known, if this safety
6168 check ever triggers, then we'll have to try harder. */
6169 gdb_assert (function
|| !readbuf
);
6174 gdb_printf (gdb_stderr
, "Return float in $fp0\n");
6177 gdb_printf (gdb_stderr
, "Return float in $2\n");
6179 case mips_fval_both
:
6180 gdb_printf (gdb_stderr
, "Return float in $fp0 and $2\n");
6183 if (fval_reg
!= mips_fval_gpr
)
6184 mips_xfer_register (gdbarch
, regcache
,
6185 (gdbarch_num_regs (gdbarch
)
6186 + mips_regnum (gdbarch
)->fp0
),
6188 gdbarch_byte_order (gdbarch
),
6189 readbuf
, writebuf
, 0);
6190 if (fval_reg
!= mips_fval_fpr
)
6191 mips_xfer_register (gdbarch
, regcache
,
6192 gdbarch_num_regs (gdbarch
) + 2,
6194 gdbarch_byte_order (gdbarch
),
6195 readbuf
, writebuf
, 0);
6196 return RETURN_VALUE_REGISTER_CONVENTION
;
6200 /* A scalar extract each part but least-significant-byte
6204 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
6205 offset
< type
->length ();
6206 offset
+= MIPS64_REGSIZE
, regnum
++)
6208 int xfer
= MIPS64_REGSIZE
;
6209 if (offset
+ xfer
> type
->length ())
6210 xfer
= type
->length () - offset
;
6212 gdb_printf (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
6213 offset
, xfer
, regnum
);
6214 mips_xfer_register (gdbarch
, regcache
,
6215 gdbarch_num_regs (gdbarch
) + regnum
,
6216 xfer
, gdbarch_byte_order (gdbarch
),
6217 readbuf
, writebuf
, offset
);
6219 return RETURN_VALUE_REGISTER_CONVENTION
;
6223 /* Floating point register management.
6225 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
6226 64bit operations, these early MIPS cpus treat fp register pairs
6227 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
6228 registers and offer a compatibility mode that emulates the MIPS2 fp
6229 model. When operating in MIPS2 fp compat mode, later cpu's split
6230 double precision floats into two 32-bit chunks and store them in
6231 consecutive fp regs. To display 64-bit floats stored in this
6232 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
6233 Throw in user-configurable endianness and you have a real mess.
6235 The way this works is:
6236 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
6237 double-precision value will be split across two logical registers.
6238 The lower-numbered logical register will hold the low-order bits,
6239 regardless of the processor's endianness.
6240 - If we are on a 64-bit processor, and we are looking for a
6241 single-precision value, it will be in the low ordered bits
6242 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
6243 save slot in memory.
6244 - If we are in 64-bit mode, everything is straightforward.
6246 Note that this code only deals with "live" registers at the top of the
6247 stack. We will attempt to deal with saved registers later, when
6248 the raw/cooked register interface is in place. (We need a general
6249 interface that can deal with dynamic saved register sizes -- fp
6250 regs could be 32 bits wide in one frame and 64 on the frame above
6253 /* Copy a 32-bit single-precision value from the current frame
6254 into rare_buffer. */
6257 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
6258 gdb_byte
*rare_buffer
)
6260 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6261 int raw_size
= register_size (gdbarch
, regno
);
6262 gdb_byte
*raw_buffer
= (gdb_byte
*) alloca (raw_size
);
6264 if (!deprecated_frame_register_read (frame
, regno
, raw_buffer
))
6265 error (_("can't read register %d (%s)"),
6266 regno
, gdbarch_register_name (gdbarch
, regno
));
6269 /* We have a 64-bit value for this register. Find the low-order
6273 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6278 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
6282 memcpy (rare_buffer
, raw_buffer
, 4);
6286 /* Copy a 64-bit double-precision value from the current frame into
6287 rare_buffer. This may include getting half of it from the next
6291 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
6292 gdb_byte
*rare_buffer
)
6294 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6295 int raw_size
= register_size (gdbarch
, regno
);
6297 if (raw_size
== 8 && !mips2_fp_compat (frame
))
6299 /* We have a 64-bit value for this register, and we should use
6301 if (!deprecated_frame_register_read (frame
, regno
, rare_buffer
))
6302 error (_("can't read register %d (%s)"),
6303 regno
, gdbarch_register_name (gdbarch
, regno
));
6307 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
6309 if ((rawnum
- mips_regnum (gdbarch
)->fp0
) & 1)
6310 internal_error (__FILE__
, __LINE__
,
6311 _("mips_read_fp_register_double: bad access to "
6312 "odd-numbered FP register"));
6314 /* mips_read_fp_register_single will find the correct 32 bits from
6316 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6318 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
6319 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
6323 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
6324 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
6330 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
6332 { /* Do values for FP (float) regs. */
6333 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6334 gdb_byte
*raw_buffer
;
6335 std::string flt_str
, dbl_str
;
6337 const struct type
*flt_type
= builtin_type (gdbarch
)->builtin_float
;
6338 const struct type
*dbl_type
= builtin_type (gdbarch
)->builtin_double
;
6342 alloca (2 * register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
)));
6344 gdb_printf (file
, "%s:", gdbarch_register_name (gdbarch
, regnum
));
6345 gdb_printf (file
, "%*s",
6346 4 - (int) strlen (gdbarch_register_name (gdbarch
, regnum
)),
6349 if (register_size (gdbarch
, regnum
) == 4 || mips2_fp_compat (frame
))
6351 struct value_print_options opts
;
6353 /* 4-byte registers: Print hex and floating. Also print even
6354 numbered registers as doubles. */
6355 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
6356 flt_str
= target_float_to_string (raw_buffer
, flt_type
, "%-17.9g");
6358 get_formatted_print_options (&opts
, 'x');
6359 print_scalar_formatted (raw_buffer
,
6360 builtin_type (gdbarch
)->builtin_uint32
,
6363 gdb_printf (file
, " flt: %s", flt_str
.c_str ());
6365 if ((regnum
- gdbarch_num_regs (gdbarch
)) % 2 == 0)
6367 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
6368 dbl_str
= target_float_to_string (raw_buffer
, dbl_type
, "%-24.17g");
6370 gdb_printf (file
, " dbl: %s", dbl_str
.c_str ());
6375 struct value_print_options opts
;
6377 /* Eight byte registers: print each one as hex, float and double. */
6378 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
6379 flt_str
= target_float_to_string (raw_buffer
, flt_type
, "%-17.9g");
6381 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
6382 dbl_str
= target_float_to_string (raw_buffer
, dbl_type
, "%-24.17g");
6384 get_formatted_print_options (&opts
, 'x');
6385 print_scalar_formatted (raw_buffer
,
6386 builtin_type (gdbarch
)->builtin_uint64
,
6389 gdb_printf (file
, " flt: %s", flt_str
.c_str ());
6390 gdb_printf (file
, " dbl: %s", dbl_str
.c_str ());
6395 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
6398 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6399 struct value_print_options opts
;
6402 if (mips_float_register_p (gdbarch
, regnum
))
6404 mips_print_fp_register (file
, frame
, regnum
);
6408 val
= get_frame_register_value (frame
, regnum
);
6410 gdb_puts (gdbarch_register_name (gdbarch
, regnum
), file
);
6412 /* The problem with printing numeric register names (r26, etc.) is that
6413 the user can't use them on input. Probably the best solution is to
6414 fix it so that either the numeric or the funky (a2, etc.) names
6415 are accepted on input. */
6416 if (regnum
< MIPS_NUMREGS
)
6417 gdb_printf (file
, "(r%d): ", regnum
);
6419 gdb_printf (file
, ": ");
6421 get_formatted_print_options (&opts
, 'x');
6422 value_print_scalar_formatted (val
, &opts
, 0, file
);
6425 /* Print IEEE exception condition bits in FLAGS. */
6428 print_fpu_flags (struct ui_file
*file
, int flags
)
6430 if (flags
& (1 << 0))
6431 gdb_puts (" inexact", file
);
6432 if (flags
& (1 << 1))
6433 gdb_puts (" uflow", file
);
6434 if (flags
& (1 << 2))
6435 gdb_puts (" oflow", file
);
6436 if (flags
& (1 << 3))
6437 gdb_puts (" div0", file
);
6438 if (flags
& (1 << 4))
6439 gdb_puts (" inval", file
);
6440 if (flags
& (1 << 5))
6441 gdb_puts (" unimp", file
);
6442 gdb_putc ('\n', file
);
6445 /* Print interesting information about the floating point processor
6446 (if present) or emulator. */
6449 mips_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
6450 struct frame_info
*frame
, const char *args
)
6452 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
6453 enum mips_fpu_type type
= mips_get_fpu_type (gdbarch
);
6457 if (fcsr
== -1 || !read_frame_register_unsigned (frame
, fcsr
, &fcs
))
6458 type
= MIPS_FPU_NONE
;
6460 gdb_printf (file
, "fpu type: %s\n",
6461 type
== MIPS_FPU_DOUBLE
? "double-precision"
6462 : type
== MIPS_FPU_SINGLE
? "single-precision"
6465 if (type
== MIPS_FPU_NONE
)
6468 gdb_printf (file
, "reg size: %d bits\n",
6469 register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) * 8);
6471 gdb_puts ("cond :", file
);
6472 if (fcs
& (1 << 23))
6473 gdb_puts (" 0", file
);
6474 for (i
= 1; i
<= 7; i
++)
6475 if (fcs
& (1 << (24 + i
)))
6476 gdb_printf (file
, " %d", i
);
6477 gdb_putc ('\n', file
);
6479 gdb_puts ("cause :", file
);
6480 print_fpu_flags (file
, (fcs
>> 12) & 0x3f);
6481 fputs ("mask :", stdout
);
6482 print_fpu_flags (file
, (fcs
>> 7) & 0x1f);
6483 fputs ("flags :", stdout
);
6484 print_fpu_flags (file
, (fcs
>> 2) & 0x1f);
6486 gdb_puts ("rounding: ", file
);
6489 case 0: gdb_puts ("nearest\n", file
); break;
6490 case 1: gdb_puts ("zero\n", file
); break;
6491 case 2: gdb_puts ("+inf\n", file
); break;
6492 case 3: gdb_puts ("-inf\n", file
); break;
6495 gdb_puts ("flush :", file
);
6496 if (fcs
& (1 << 21))
6497 gdb_puts (" nearest", file
);
6498 if (fcs
& (1 << 22))
6499 gdb_puts (" override", file
);
6500 if (fcs
& (1 << 24))
6501 gdb_puts (" zero", file
);
6502 if ((fcs
& (0xb << 21)) == 0)
6503 gdb_puts (" no", file
);
6504 gdb_putc ('\n', file
);
6506 gdb_printf (file
, "nan2008 : %s\n", fcs
& (1 << 18) ? "yes" : "no");
6507 gdb_printf (file
, "abs2008 : %s\n", fcs
& (1 << 19) ? "yes" : "no");
6508 gdb_putc ('\n', file
);
6510 default_print_float_info (gdbarch
, file
, frame
, args
);
6513 /* Replacement for generic do_registers_info.
6514 Print regs in pretty columns. */
6517 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
6520 gdb_printf (file
, " ");
6521 mips_print_fp_register (file
, frame
, regnum
);
6522 gdb_printf (file
, "\n");
6527 /* Print a row's worth of GP (int) registers, with name labels above. */
6530 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
6533 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6534 /* Do values for GP (int) regs. */
6535 const gdb_byte
*raw_buffer
;
6536 struct value
*value
;
6537 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols
6542 /* For GP registers, we print a separate row of names above the vals. */
6543 for (col
= 0, regnum
= start_regnum
;
6544 col
< ncols
&& regnum
< gdbarch_num_cooked_regs (gdbarch
);
6547 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
6548 continue; /* unused register */
6549 if (mips_float_register_p (gdbarch
, regnum
))
6550 break; /* End the row: reached FP register. */
6551 /* Large registers are handled separately. */
6552 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
6555 break; /* End the row before this register. */
6557 /* Print this register on a row by itself. */
6558 mips_print_register (file
, frame
, regnum
);
6559 gdb_printf (file
, "\n");
6563 gdb_printf (file
, " ");
6565 mips_abi_regsize (gdbarch
) == 8 ? "%17s" : "%9s",
6566 gdbarch_register_name (gdbarch
, regnum
));
6573 /* Print the R0 to R31 names. */
6574 if ((start_regnum
% gdbarch_num_regs (gdbarch
)) < MIPS_NUMREGS
)
6575 gdb_printf (file
, "\n R%-4d",
6576 start_regnum
% gdbarch_num_regs (gdbarch
));
6578 gdb_printf (file
, "\n ");
6580 /* Now print the values in hex, 4 or 8 to the row. */
6581 for (col
= 0, regnum
= start_regnum
;
6582 col
< ncols
&& regnum
< gdbarch_num_cooked_regs (gdbarch
);
6585 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
6586 continue; /* unused register */
6587 if (mips_float_register_p (gdbarch
, regnum
))
6588 break; /* End row: reached FP register. */
6589 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
6590 break; /* End row: large register. */
6592 /* OK: get the data in raw format. */
6593 value
= get_frame_register_value (frame
, regnum
);
6594 if (value_optimized_out (value
)
6595 || !value_entirely_available (value
))
6597 gdb_printf (file
, "%*s ",
6598 (int) mips_abi_regsize (gdbarch
) * 2,
6599 (mips_abi_regsize (gdbarch
) == 4 ? "<unavl>"
6600 : "<unavailable>"));
6604 raw_buffer
= value_contents_all (value
).data ();
6605 /* pad small registers */
6607 byte
< (mips_abi_regsize (gdbarch
)
6608 - register_size (gdbarch
, regnum
)); byte
++)
6609 gdb_printf (file
, " ");
6610 /* Now print the register value in hex, endian order. */
6611 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6613 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
6614 byte
< register_size (gdbarch
, regnum
); byte
++)
6615 gdb_printf (file
, "%02x", raw_buffer
[byte
]);
6617 for (byte
= register_size (gdbarch
, regnum
) - 1;
6619 gdb_printf (file
, "%02x", raw_buffer
[byte
]);
6620 gdb_printf (file
, " ");
6623 if (col
> 0) /* ie. if we actually printed anything... */
6624 gdb_printf (file
, "\n");
6629 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */
6632 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
6633 struct frame_info
*frame
, int regnum
, int all
)
6635 if (regnum
!= -1) /* Do one specified register. */
6637 gdb_assert (regnum
>= gdbarch_num_regs (gdbarch
));
6638 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
6639 error (_("Not a valid register for the current processor type"));
6641 mips_print_register (file
, frame
, regnum
);
6642 gdb_printf (file
, "\n");
6645 /* Do all (or most) registers. */
6647 regnum
= gdbarch_num_regs (gdbarch
);
6648 while (regnum
< gdbarch_num_cooked_regs (gdbarch
))
6650 if (mips_float_register_p (gdbarch
, regnum
))
6652 if (all
) /* True for "INFO ALL-REGISTERS" command. */
6653 regnum
= print_fp_register_row (file
, frame
, regnum
);
6655 regnum
+= MIPS_NUMREGS
; /* Skip floating point regs. */
6658 regnum
= print_gp_register_row (file
, frame
, regnum
);
6664 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
6665 struct frame_info
*frame
)
6667 CORE_ADDR pc
= get_frame_pc (frame
);
6672 if ((mips_pc_is_mips (pc
)
6673 && !mips32_insn_at_pc_has_delay_slot (gdbarch
, pc
))
6674 || (mips_pc_is_micromips (gdbarch
, pc
)
6675 && !micromips_insn_at_pc_has_delay_slot (gdbarch
, pc
, 0))
6676 || (mips_pc_is_mips16 (gdbarch
, pc
)
6677 && !mips16_insn_at_pc_has_delay_slot (gdbarch
, pc
, 0)))
6680 isa
= mips_pc_isa (gdbarch
, pc
);
6681 /* _has_delay_slot above will have validated the read. */
6682 insn
= mips_fetch_instruction (gdbarch
, isa
, pc
, NULL
);
6683 size
= mips_insn_size (isa
, insn
);
6685 const address_space
*aspace
= get_frame_address_space (frame
);
6687 return breakpoint_here_p (aspace
, pc
+ size
) != no_breakpoint_here
;
6690 /* To skip prologues, I use this predicate. Returns either PC itself
6691 if the code at PC does not look like a function prologue; otherwise
6692 returns an address that (if we're lucky) follows the prologue. If
6693 LENIENT, then we must skip everything which is involved in setting
6694 up the frame (it's OK to skip more, just so long as we don't skip
6695 anything which might clobber the registers which are being saved.
6696 We must skip more in the case where part of the prologue is in the
6697 delay slot of a non-prologue instruction). */
6700 mips_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6703 CORE_ADDR func_addr
;
6705 /* See if we can determine the end of the prologue via the symbol table.
6706 If so, then return either PC, or the PC after the prologue, whichever
6708 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
6710 CORE_ADDR post_prologue_pc
6711 = skip_prologue_using_sal (gdbarch
, func_addr
);
6712 if (post_prologue_pc
!= 0)
6713 return std::max (pc
, post_prologue_pc
);
6716 /* Can't determine prologue from the symbol table, need to examine
6719 /* Find an upper limit on the function prologue using the debug
6720 information. If the debug information could not be used to provide
6721 that bound, then use an arbitrary large number as the upper bound. */
6722 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
6724 limit_pc
= pc
+ 100; /* Magic. */
6726 if (mips_pc_is_mips16 (gdbarch
, pc
))
6727 return mips16_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6728 else if (mips_pc_is_micromips (gdbarch
, pc
))
6729 return micromips_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6731 return mips32_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6734 /* Implement the stack_frame_destroyed_p gdbarch method (32-bit version).
6735 This is a helper function for mips_stack_frame_destroyed_p. */
6738 mips32_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6740 CORE_ADDR func_addr
= 0, func_end
= 0;
6742 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6744 /* The MIPS epilogue is max. 12 bytes long. */
6745 CORE_ADDR addr
= func_end
- 12;
6747 if (addr
< func_addr
+ 4)
6748 addr
= func_addr
+ 4;
6752 for (; pc
< func_end
; pc
+= MIPS_INSN32_SIZE
)
6754 unsigned long high_word
;
6757 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
6758 high_word
= (inst
>> 16) & 0xffff;
6760 if (high_word
!= 0x27bd /* addiu $sp,$sp,offset */
6761 && high_word
!= 0x67bd /* daddiu $sp,$sp,offset */
6762 && inst
!= 0x03e00008 /* jr $ra */
6763 && inst
!= 0x00000000) /* nop */
6773 /* Implement the stack_frame_destroyed_p gdbarch method (microMIPS version).
6774 This is a helper function for mips_stack_frame_destroyed_p. */
6777 micromips_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6779 CORE_ADDR func_addr
= 0;
6780 CORE_ADDR func_end
= 0;
6788 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6791 /* The microMIPS epilogue is max. 12 bytes long. */
6792 addr
= func_end
- 12;
6794 if (addr
< func_addr
+ 2)
6795 addr
= func_addr
+ 2;
6799 for (; pc
< func_end
; pc
+= loc
)
6802 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
6803 loc
+= MIPS_INSN16_SIZE
;
6804 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
6806 /* 32-bit instructions. */
6807 case 2 * MIPS_INSN16_SIZE
:
6809 insn
|= mips_fetch_instruction (gdbarch
,
6810 ISA_MICROMIPS
, pc
+ loc
, NULL
);
6811 loc
+= MIPS_INSN16_SIZE
;
6812 switch (micromips_op (insn
>> 16))
6814 case 0xc: /* ADDIU: bits 001100 */
6815 case 0x17: /* DADDIU: bits 010111 */
6816 sreg
= b0s5_reg (insn
>> 16);
6817 dreg
= b5s5_reg (insn
>> 16);
6818 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
6819 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
6820 /* (D)ADDIU $sp, imm */
6830 /* 16-bit instructions. */
6831 case MIPS_INSN16_SIZE
:
6832 switch (micromips_op (insn
))
6834 case 0x3: /* MOVE: bits 000011 */
6835 sreg
= b0s5_reg (insn
);
6836 dreg
= b5s5_reg (insn
);
6837 if (sreg
== 0 && dreg
== 0)
6838 /* MOVE $zero, $zero aka NOP */
6842 case 0x11: /* POOL16C: bits 010001 */
6843 if (b5s5_op (insn
) == 0x18
6844 /* JRADDIUSP: bits 010011 11000 */
6845 || (b5s5_op (insn
) == 0xd
6846 /* JRC: bits 010011 01101 */
6847 && b0s5_reg (insn
) == MIPS_RA_REGNUM
))
6852 case 0x13: /* POOL16D: bits 010011 */
6853 offset
= micromips_decode_imm9 (b1s9_imm (insn
));
6854 if ((insn
& 0x1) == 0x1
6855 /* ADDIUSP: bits 010011 1 */
6869 /* Implement the stack_frame_destroyed_p gdbarch method (16-bit version).
6870 This is a helper function for mips_stack_frame_destroyed_p. */
6873 mips16_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6875 CORE_ADDR func_addr
= 0, func_end
= 0;
6877 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6879 /* The MIPS epilogue is max. 12 bytes long. */
6880 CORE_ADDR addr
= func_end
- 12;
6882 if (addr
< func_addr
+ 4)
6883 addr
= func_addr
+ 4;
6887 for (; pc
< func_end
; pc
+= MIPS_INSN16_SIZE
)
6889 unsigned short inst
;
6891 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, pc
, NULL
);
6893 if ((inst
& 0xf800) == 0xf000) /* extend */
6896 if (inst
!= 0x6300 /* addiu $sp,offset */
6897 && inst
!= 0xfb00 /* daddiu $sp,$sp,offset */
6898 && inst
!= 0xe820 /* jr $ra */
6899 && inst
!= 0xe8a0 /* jrc $ra */
6900 && inst
!= 0x6500) /* nop */
6910 /* Implement the stack_frame_destroyed_p gdbarch method.
6912 The epilogue is defined here as the area at the end of a function,
6913 after an instruction which destroys the function's stack frame. */
6916 mips_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6918 if (mips_pc_is_mips16 (gdbarch
, pc
))
6919 return mips16_stack_frame_destroyed_p (gdbarch
, pc
);
6920 else if (mips_pc_is_micromips (gdbarch
, pc
))
6921 return micromips_stack_frame_destroyed_p (gdbarch
, pc
);
6923 return mips32_stack_frame_destroyed_p (gdbarch
, pc
);
6926 /* Commands to show/set the MIPS FPU type. */
6929 show_mipsfpu_command (const char *args
, int from_tty
)
6933 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_mips
)
6936 ("The MIPS floating-point coprocessor is unknown "
6937 "because the current architecture is not MIPS.\n");
6941 switch (mips_get_fpu_type (target_gdbarch ()))
6943 case MIPS_FPU_SINGLE
:
6944 fpu
= "single-precision";
6946 case MIPS_FPU_DOUBLE
:
6947 fpu
= "double-precision";
6950 fpu
= "absent (none)";
6953 internal_error (__FILE__
, __LINE__
, _("bad switch"));
6955 if (mips_fpu_type_auto
)
6956 gdb_printf ("The MIPS floating-point coprocessor "
6957 "is set automatically (currently %s)\n",
6961 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
6966 set_mipsfpu_single_command (const char *args
, int from_tty
)
6968 struct gdbarch_info info
;
6969 mips_fpu_type
= MIPS_FPU_SINGLE
;
6970 mips_fpu_type_auto
= 0;
6971 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6972 instead of relying on globals. Doing that would let generic code
6973 handle the search for this specific architecture. */
6974 if (!gdbarch_update_p (info
))
6975 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6979 set_mipsfpu_double_command (const char *args
, int from_tty
)
6981 struct gdbarch_info info
;
6982 mips_fpu_type
= MIPS_FPU_DOUBLE
;
6983 mips_fpu_type_auto
= 0;
6984 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6985 instead of relying on globals. Doing that would let generic code
6986 handle the search for this specific architecture. */
6987 if (!gdbarch_update_p (info
))
6988 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6992 set_mipsfpu_none_command (const char *args
, int from_tty
)
6994 struct gdbarch_info info
;
6995 mips_fpu_type
= MIPS_FPU_NONE
;
6996 mips_fpu_type_auto
= 0;
6997 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6998 instead of relying on globals. Doing that would let generic code
6999 handle the search for this specific architecture. */
7000 if (!gdbarch_update_p (info
))
7001 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
7005 set_mipsfpu_auto_command (const char *args
, int from_tty
)
7007 mips_fpu_type_auto
= 1;
7010 /* Just like reinit_frame_cache, but with the right arguments to be
7011 callable as an sfunc. */
7014 reinit_frame_cache_sfunc (const char *args
, int from_tty
,
7015 struct cmd_list_element
*c
)
7017 reinit_frame_cache ();
7021 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
7023 gdb_disassemble_info
*di
7024 = static_cast<gdb_disassemble_info
*> (info
->application_data
);
7025 struct gdbarch
*gdbarch
= di
->arch ();
7027 /* FIXME: cagney/2003-06-26: Is this even necessary? The
7028 disassembler needs to be able to locally determine the ISA, and
7029 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
7031 if (mips_pc_is_mips16 (gdbarch
, memaddr
))
7032 info
->mach
= bfd_mach_mips16
;
7033 else if (mips_pc_is_micromips (gdbarch
, memaddr
))
7034 info
->mach
= bfd_mach_mips_micromips
;
7036 /* Round down the instruction address to the appropriate boundary. */
7037 memaddr
&= (info
->mach
== bfd_mach_mips16
7038 || info
->mach
== bfd_mach_mips_micromips
) ? ~1 : ~3;
7040 return default_print_insn (memaddr
, info
);
7043 /* Implement the breakpoint_kind_from_pc gdbarch method. */
7046 mips_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
7048 CORE_ADDR pc
= *pcptr
;
7050 if (mips_pc_is_mips16 (gdbarch
, pc
))
7052 *pcptr
= unmake_compact_addr (pc
);
7053 return MIPS_BP_KIND_MIPS16
;
7055 else if (mips_pc_is_micromips (gdbarch
, pc
))
7060 *pcptr
= unmake_compact_addr (pc
);
7061 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, &status
);
7062 if (status
|| (mips_insn_size (ISA_MICROMIPS
, insn
) == 2))
7063 return MIPS_BP_KIND_MICROMIPS16
;
7065 return MIPS_BP_KIND_MICROMIPS32
;
7068 return MIPS_BP_KIND_MIPS32
;
7071 /* Implement the sw_breakpoint_from_kind gdbarch method. */
7073 static const gdb_byte
*
7074 mips_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
7076 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
7080 case MIPS_BP_KIND_MIPS16
:
7082 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
7083 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
7086 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7087 return mips16_big_breakpoint
;
7089 return mips16_little_breakpoint
;
7091 case MIPS_BP_KIND_MICROMIPS16
:
7093 static gdb_byte micromips16_big_breakpoint
[] = { 0x46, 0x85 };
7094 static gdb_byte micromips16_little_breakpoint
[] = { 0x85, 0x46 };
7098 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7099 return micromips16_big_breakpoint
;
7101 return micromips16_little_breakpoint
;
7103 case MIPS_BP_KIND_MICROMIPS32
:
7105 static gdb_byte micromips32_big_breakpoint
[] = { 0, 0x5, 0, 0x7 };
7106 static gdb_byte micromips32_little_breakpoint
[] = { 0x5, 0, 0x7, 0 };
7109 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7110 return micromips32_big_breakpoint
;
7112 return micromips32_little_breakpoint
;
7114 case MIPS_BP_KIND_MIPS32
:
7116 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
7117 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
7120 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7121 return big_breakpoint
;
7123 return little_breakpoint
;
7126 gdb_assert_not_reached ("unexpected mips breakpoint kind");
7130 /* Return non-zero if the standard MIPS instruction INST has a branch
7131 delay slot (i.e. it is a jump or branch instruction). This function
7132 is based on mips32_next_pc. */
7135 mips32_instruction_has_delay_slot (struct gdbarch
*gdbarch
, ULONGEST inst
)
7141 op
= itype_op (inst
);
7142 if ((inst
& 0xe0000000) != 0)
7144 rs
= itype_rs (inst
);
7145 rt
= itype_rt (inst
);
7146 return (is_octeon_bbit_op (op
, gdbarch
)
7147 || op
>> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
7148 || op
== 29 /* JALX: bits 011101 */
7151 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
7152 || (rs
== 9 && (rt
& 0x2) == 0)
7153 /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */
7154 || (rs
== 10 && (rt
& 0x2) == 0))));
7155 /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */
7158 switch (op
& 0x07) /* extract bits 28,27,26 */
7160 case 0: /* SPECIAL */
7161 op
= rtype_funct (inst
);
7162 return (op
== 8 /* JR */
7163 || op
== 9); /* JALR */
7164 break; /* end SPECIAL */
7165 case 1: /* REGIMM */
7166 rs
= itype_rs (inst
);
7167 rt
= itype_rt (inst
); /* branch condition */
7168 return ((rt
& 0xc) == 0
7169 /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */
7170 /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */
7171 || ((rt
& 0x1e) == 0x1c && rs
== 0));
7172 /* BPOSGE32, BPOSGE64: bits 1110x */
7173 break; /* end REGIMM */
7174 default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */
7180 /* Return non-zero if a standard MIPS instruction at ADDR has a branch
7181 delay slot (i.e. it is a jump or branch instruction). */
7184 mips32_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
7189 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, addr
, &status
);
7193 return mips32_instruction_has_delay_slot (gdbarch
, insn
);
7196 /* Return non-zero if the microMIPS instruction INSN, comprising the
7197 16-bit major opcode word in the high 16 bits and any second word
7198 in the low 16 bits, has a branch delay slot (i.e. it is a non-compact
7199 jump or branch instruction). The instruction must be 32-bit if
7200 MUSTBE32 is set or can be any instruction otherwise. */
7203 micromips_instruction_has_delay_slot (ULONGEST insn
, int mustbe32
)
7205 ULONGEST major
= insn
>> 16;
7207 switch (micromips_op (major
))
7209 /* 16-bit instructions. */
7210 case 0x33: /* B16: bits 110011 */
7211 case 0x2b: /* BNEZ16: bits 101011 */
7212 case 0x23: /* BEQZ16: bits 100011 */
7214 case 0x11: /* POOL16C: bits 010001 */
7216 && ((b5s5_op (major
) == 0xc
7217 /* JR16: bits 010001 01100 */
7218 || (b5s5_op (major
) & 0x1e) == 0xe)));
7219 /* JALR16, JALRS16: bits 010001 0111x */
7220 /* 32-bit instructions. */
7221 case 0x3d: /* JAL: bits 111101 */
7222 case 0x3c: /* JALX: bits 111100 */
7223 case 0x35: /* J: bits 110101 */
7224 case 0x2d: /* BNE: bits 101101 */
7225 case 0x25: /* BEQ: bits 100101 */
7226 case 0x1d: /* JALS: bits 011101 */
7228 case 0x10: /* POOL32I: bits 010000 */
7229 return ((b5s5_op (major
) & 0x1c) == 0x0
7230 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
7231 || (b5s5_op (major
) & 0x1d) == 0x4
7232 /* BLEZ, BGTZ: bits 010000 001x0 */
7233 || (b5s5_op (major
) & 0x1d) == 0x11
7234 /* BLTZALS, BGEZALS: bits 010000 100x1 */
7235 || ((b5s5_op (major
) & 0x1e) == 0x14
7236 && (major
& 0x3) == 0x0)
7237 /* BC2F, BC2T: bits 010000 1010x xxx00 */
7238 || (b5s5_op (major
) & 0x1e) == 0x1a
7239 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
7240 || ((b5s5_op (major
) & 0x1e) == 0x1c
7241 && (major
& 0x3) == 0x0)
7242 /* BC1F, BC1T: bits 010000 1110x xxx00 */
7243 || ((b5s5_op (major
) & 0x1c) == 0x1c
7244 && (major
& 0x3) == 0x1));
7245 /* BC1ANY*: bits 010000 111xx xxx01 */
7246 case 0x0: /* POOL32A: bits 000000 */
7247 return (b0s6_op (insn
) == 0x3c
7248 /* POOL32Axf: bits 000000 ... 111100 */
7249 && (b6s10_ext (insn
) & 0x2bf) == 0x3c);
7250 /* JALR, JALR.HB: 000000 000x111100 111100 */
7251 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
7257 /* Return non-zero if a microMIPS instruction at ADDR has a branch delay
7258 slot (i.e. it is a non-compact jump instruction). The instruction
7259 must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */
7262 micromips_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
7263 CORE_ADDR addr
, int mustbe32
)
7269 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, addr
, &status
);
7272 size
= mips_insn_size (ISA_MICROMIPS
, insn
);
7274 if (size
== 2 * MIPS_INSN16_SIZE
)
7276 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, addr
, &status
);
7281 return micromips_instruction_has_delay_slot (insn
, mustbe32
);
7284 /* Return non-zero if the MIPS16 instruction INST, which must be
7285 a 32-bit instruction if MUSTBE32 is set or can be any instruction
7286 otherwise, has a branch delay slot (i.e. it is a non-compact jump
7287 instruction). This function is based on mips16_next_pc. */
7290 mips16_instruction_has_delay_slot (unsigned short inst
, int mustbe32
)
7292 if ((inst
& 0xf89f) == 0xe800) /* JR/JALR (16-bit instruction) */
7294 return (inst
& 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */
7297 /* Return non-zero if a MIPS16 instruction at ADDR has a branch delay
7298 slot (i.e. it is a non-compact jump instruction). The instruction
7299 must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */
7302 mips16_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
7303 CORE_ADDR addr
, int mustbe32
)
7305 unsigned short insn
;
7308 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, addr
, &status
);
7312 return mips16_instruction_has_delay_slot (insn
, mustbe32
);
7315 /* Calculate the starting address of the MIPS memory segment BPADDR is in.
7316 This assumes KSSEG exists. */
7319 mips_segment_boundary (CORE_ADDR bpaddr
)
7321 CORE_ADDR mask
= CORE_ADDR_MAX
;
7324 if (sizeof (CORE_ADDR
) == 8)
7325 /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid
7326 a compiler warning produced where CORE_ADDR is a 32-bit type even
7327 though in that case this is dead code). */
7328 switch (bpaddr
>> ((sizeof (CORE_ADDR
) << 3) - 2) & 3)
7331 if (bpaddr
== (bfd_signed_vma
) (int32_t) bpaddr
)
7332 segsize
= 29; /* 32-bit compatibility segment */
7334 segsize
= 62; /* xkseg */
7336 case 2: /* xkphys */
7339 default: /* xksseg (1), xkuseg/kuseg (0) */
7343 else if (bpaddr
& 0x80000000) /* kernel segment */
7346 segsize
= 31; /* user segment */
7348 return bpaddr
& mask
;
7351 /* Move the breakpoint at BPADDR out of any branch delay slot by shifting
7352 it backwards if necessary. Return the address of the new location. */
7355 mips_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
7357 CORE_ADDR prev_addr
;
7359 CORE_ADDR func_addr
;
7361 /* If a breakpoint is set on the instruction in a branch delay slot,
7362 GDB gets confused. When the breakpoint is hit, the PC isn't on
7363 the instruction in the branch delay slot, the PC will point to
7364 the branch instruction. Since the PC doesn't match any known
7365 breakpoints, GDB reports a trap exception.
7367 There are two possible fixes for this problem.
7369 1) When the breakpoint gets hit, see if the BD bit is set in the
7370 Cause register (which indicates the last exception occurred in a
7371 branch delay slot). If the BD bit is set, fix the PC to point to
7372 the instruction in the branch delay slot.
7374 2) When the user sets the breakpoint, don't allow him to set the
7375 breakpoint on the instruction in the branch delay slot. Instead
7376 move the breakpoint to the branch instruction (which will have
7379 The problem with the first solution is that if the user then
7380 single-steps the processor, the branch instruction will get
7381 skipped (since GDB thinks the PC is on the instruction in the
7384 So, we'll use the second solution. To do this we need to know if
7385 the instruction we're trying to set the breakpoint on is in the
7386 branch delay slot. */
7388 boundary
= mips_segment_boundary (bpaddr
);
7390 /* Make sure we don't scan back before the beginning of the current
7391 function, since we may fetch constant data or insns that look like
7392 a jump. Of course we might do that anyway if the compiler has
7393 moved constants inline. :-( */
7394 if (find_pc_partial_function (bpaddr
, NULL
, &func_addr
, NULL
)
7395 && func_addr
> boundary
&& func_addr
<= bpaddr
)
7396 boundary
= func_addr
;
7398 if (mips_pc_is_mips (bpaddr
))
7400 if (bpaddr
== boundary
)
7403 /* If the previous instruction has a branch delay slot, we have
7404 to move the breakpoint to the branch instruction. */
7405 prev_addr
= bpaddr
- 4;
7406 if (mips32_insn_at_pc_has_delay_slot (gdbarch
, prev_addr
))
7411 int (*insn_at_pc_has_delay_slot
) (struct gdbarch
*, CORE_ADDR
, int);
7412 CORE_ADDR addr
, jmpaddr
;
7415 boundary
= unmake_compact_addr (boundary
);
7417 /* The only MIPS16 instructions with delay slots are JAL, JALX,
7418 JALR and JR. An absolute JAL/JALX is always 4 bytes long,
7419 so try for that first, then try the 2 byte JALR/JR.
7420 The microMIPS ASE has a whole range of jumps and branches
7421 with delay slots, some of which take 4 bytes and some take
7422 2 bytes, so the idea is the same.
7423 FIXME: We have to assume that bpaddr is not the second half
7424 of an extended instruction. */
7425 insn_at_pc_has_delay_slot
= (mips_pc_is_micromips (gdbarch
, bpaddr
)
7426 ? micromips_insn_at_pc_has_delay_slot
7427 : mips16_insn_at_pc_has_delay_slot
);
7431 for (i
= 1; i
< 4; i
++)
7433 if (unmake_compact_addr (addr
) == boundary
)
7435 addr
-= MIPS_INSN16_SIZE
;
7436 if (i
== 1 && insn_at_pc_has_delay_slot (gdbarch
, addr
, 0))
7437 /* Looks like a JR/JALR at [target-1], but it could be
7438 the second word of a previous JAL/JALX, so record it
7439 and check back one more. */
7441 else if (i
> 1 && insn_at_pc_has_delay_slot (gdbarch
, addr
, 1))
7444 /* Looks like a JAL/JALX at [target-2], but it could also
7445 be the second word of a previous JAL/JALX, record it,
7446 and check back one more. */
7449 /* Looks like a JAL/JALX at [target-3], so any previously
7450 recorded JAL/JALX or JR/JALR must be wrong, because:
7453 -2: JAL-ext (can't be JAL/JALX)
7454 -1: bdslot (can't be JR/JALR)
7457 Of course it could be another JAL-ext which looks
7458 like a JAL, but in that case we'd have broken out
7459 of this loop at [target-2]:
7463 -2: bdslot (can't be jmp)
7470 /* Not a jump instruction: if we're at [target-1] this
7471 could be the second word of a JAL/JALX, so continue;
7472 otherwise we're done. */
7485 /* Return non-zero if SUFFIX is one of the numeric suffixes used for MIPS16
7486 call stubs, one of 1, 2, 5, 6, 9, 10, or, if ZERO is non-zero, also 0. */
7489 mips_is_stub_suffix (const char *suffix
, int zero
)
7494 return zero
&& suffix
[1] == '\0';
7496 return suffix
[1] == '\0' || (suffix
[1] == '0' && suffix
[2] == '\0');
7501 return suffix
[1] == '\0';
7507 /* Return non-zero if MODE is one of the mode infixes used for MIPS16
7508 call stubs, one of sf, df, sc, or dc. */
7511 mips_is_stub_mode (const char *mode
)
7513 return ((mode
[0] == 's' || mode
[0] == 'd')
7514 && (mode
[1] == 'f' || mode
[1] == 'c'));
7517 /* Code at PC is a compiler-generated stub. Such a stub for a function
7518 bar might have a name like __fn_stub_bar, and might look like this:
7525 followed by (or interspersed with):
7532 addiu $25, $25, %lo(bar)
7535 ($1 may be used in old code; for robustness we accept any register)
7538 lui $28, %hi(_gp_disp)
7539 addiu $28, $28, %lo(_gp_disp)
7542 addiu $25, $25, %lo(bar)
7545 In the case of a __call_stub_bar stub, the sequence to set up
7546 arguments might look like this:
7553 followed by (or interspersed with) one of the jump sequences above.
7555 In the case of a __call_stub_fp_bar stub, JAL or JALR is used instead
7556 of J or JR, respectively, followed by:
7562 We are at the beginning of the stub here, and scan down and extract
7563 the target address from the jump immediate instruction or, if a jump
7564 register instruction is used, from the register referred. Return
7565 the value of PC calculated or 0 if inconclusive.
7567 The limit on the search is arbitrarily set to 20 instructions. FIXME. */
7570 mips_get_mips16_fn_stub_pc (struct frame_info
*frame
, CORE_ADDR pc
)
7572 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7573 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7574 int addrreg
= MIPS_ZERO_REGNUM
;
7575 CORE_ADDR start_pc
= pc
;
7576 CORE_ADDR target_pc
= 0;
7583 status
== 0 && target_pc
== 0 && i
< 20;
7584 i
++, pc
+= MIPS_INSN32_SIZE
)
7586 ULONGEST inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
7592 switch (itype_op (inst
))
7594 case 0: /* SPECIAL */
7595 switch (rtype_funct (inst
))
7599 rs
= rtype_rs (inst
);
7600 if (rs
== MIPS_GP_REGNUM
)
7601 target_pc
= gp
; /* Hmm... */
7602 else if (rs
== addrreg
)
7606 case 0x21: /* ADDU */
7607 rt
= rtype_rt (inst
);
7608 rs
= rtype_rs (inst
);
7609 rd
= rtype_rd (inst
);
7610 if (rd
== MIPS_GP_REGNUM
7611 && ((rs
== MIPS_GP_REGNUM
&& rt
== MIPS_T9_REGNUM
)
7612 || (rs
== MIPS_T9_REGNUM
&& rt
== MIPS_GP_REGNUM
)))
7620 target_pc
= jtype_target (inst
) << 2;
7621 target_pc
+= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
7625 rt
= itype_rt (inst
);
7626 rs
= itype_rs (inst
);
7629 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
7630 if (rt
== MIPS_GP_REGNUM
)
7632 else if (rt
== addrreg
)
7638 rt
= itype_rt (inst
);
7639 imm
= ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 16;
7640 if (rt
== MIPS_GP_REGNUM
)
7642 else if (rt
!= MIPS_ZERO_REGNUM
)
7650 rt
= itype_rt (inst
);
7651 rs
= itype_rs (inst
);
7652 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
7653 if (gp
!= 0 && rs
== MIPS_GP_REGNUM
)
7657 memset (buf
, 0, sizeof (buf
));
7658 status
= target_read_memory (gp
+ imm
, buf
, sizeof (buf
));
7660 addr
= extract_signed_integer (buf
, sizeof (buf
), byte_order
);
7669 /* If PC is in a MIPS16 call or return stub, return the address of the
7670 target PC, which is either the callee or the caller. There are several
7671 cases which must be handled:
7673 * If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7674 and the target PC is in $31 ($ra).
7675 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7676 and the target PC is in $2.
7677 * If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7678 i.e. before the JALR instruction, this is effectively a call stub
7679 and the target PC is in $2. Otherwise this is effectively
7680 a return stub and the target PC is in $18.
7681 * If the PC is at the start of __call_stub_fp_*, i.e. before the
7682 JAL or JALR instruction, this is effectively a call stub and the
7683 target PC is buried in the instruction stream. Otherwise this
7684 is effectively a return stub and the target PC is in $18.
7685 * If the PC is in __call_stub_* or in __fn_stub_*, this is a call
7686 stub and the target PC is buried in the instruction stream.
7688 See the source code for the stubs in gcc/config/mips/mips16.S, or the
7689 stub builder in gcc/config/mips/mips.c (mips16_build_call_stub) for the
7693 mips_skip_mips16_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7695 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7696 CORE_ADDR start_addr
;
7700 /* Find the starting address and name of the function containing the PC. */
7701 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
7704 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7705 and the target PC is in $31 ($ra). */
7706 prefixlen
= strlen (mips_str_mips16_ret_stub
);
7707 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
7708 && mips_is_stub_mode (name
+ prefixlen
)
7709 && name
[prefixlen
+ 2] == '\0')
7710 return get_frame_register_signed
7711 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
7713 /* If the PC is in __mips16_call_stub_*, this is one of the call
7714 call/return stubs. */
7715 prefixlen
= strlen (mips_str_mips16_call_stub
);
7716 if (strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0)
7718 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7719 and the target PC is in $2. */
7720 if (mips_is_stub_suffix (name
+ prefixlen
, 0))
7721 return get_frame_register_signed
7722 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
7724 /* If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7725 i.e. before the JALR instruction, this is effectively a call stub
7726 and the target PC is in $2. Otherwise this is effectively
7727 a return stub and the target PC is in $18. */
7728 else if (mips_is_stub_mode (name
+ prefixlen
)
7729 && name
[prefixlen
+ 2] == '_'
7730 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 0))
7732 if (pc
== start_addr
)
7733 /* This is the 'call' part of a call stub. The return
7734 address is in $2. */
7735 return get_frame_register_signed
7736 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
7738 /* This is the 'return' part of a call stub. The return
7739 address is in $18. */
7740 return get_frame_register_signed
7741 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
7744 return 0; /* Not a stub. */
7747 /* If the PC is in __call_stub_* or __fn_stub*, this is one of the
7748 compiler-generated call or call/return stubs. */
7749 if (startswith (name
, mips_str_fn_stub
)
7750 || startswith (name
, mips_str_call_stub
))
7752 if (pc
== start_addr
)
7753 /* This is the 'call' part of a call stub. Call this helper
7754 to scan through this code for interesting instructions
7755 and determine the final PC. */
7756 return mips_get_mips16_fn_stub_pc (frame
, pc
);
7758 /* This is the 'return' part of a call stub. The return address
7760 return get_frame_register_signed
7761 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
7764 return 0; /* Not a stub. */
7767 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
7768 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
7771 mips_in_return_stub (struct gdbarch
*gdbarch
, CORE_ADDR pc
, const char *name
)
7773 CORE_ADDR start_addr
;
7776 /* Find the starting address of the function containing the PC. */
7777 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
7780 /* If the PC is in __mips16_call_stub_{s,d}{f,c}_{0..10} but not at
7781 the start, i.e. after the JALR instruction, this is effectively
7783 prefixlen
= strlen (mips_str_mips16_call_stub
);
7784 if (pc
!= start_addr
7785 && strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0
7786 && mips_is_stub_mode (name
+ prefixlen
)
7787 && name
[prefixlen
+ 2] == '_'
7788 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 1))
7791 /* If the PC is in __call_stub_fp_* but not at the start, i.e. after
7792 the JAL or JALR instruction, this is effectively a return stub. */
7793 prefixlen
= strlen (mips_str_call_fp_stub
);
7794 if (pc
!= start_addr
7795 && strncmp (name
, mips_str_call_fp_stub
, prefixlen
) == 0)
7798 /* Consume the .pic. prefix of any PIC stub, this function must return
7799 true when the PC is in a PIC stub of a __mips16_ret_{d,s}{f,c} stub
7800 or the call stub path will trigger in handle_inferior_event causing
7802 prefixlen
= strlen (mips_str_pic
);
7803 if (strncmp (name
, mips_str_pic
, prefixlen
) == 0)
7806 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub. */
7807 prefixlen
= strlen (mips_str_mips16_ret_stub
);
7808 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
7809 && mips_is_stub_mode (name
+ prefixlen
)
7810 && name
[prefixlen
+ 2] == '\0')
7813 return 0; /* Not a stub. */
7816 /* If the current PC is the start of a non-PIC-to-PIC stub, return the
7817 PC of the stub target. The stub just loads $t9 and jumps to it,
7818 so that $t9 has the correct value at function entry. */
7821 mips_skip_pic_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7823 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7824 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7825 struct bound_minimal_symbol msym
;
7827 gdb_byte stub_code
[16];
7828 int32_t stub_words
[4];
7830 /* The stub for foo is named ".pic.foo", and is either two
7831 instructions inserted before foo or a three instruction sequence
7832 which jumps to foo. */
7833 msym
= lookup_minimal_symbol_by_pc (pc
);
7834 if (msym
.minsym
== NULL
7835 || msym
.value_address () != pc
7836 || msym
.minsym
->linkage_name () == NULL
7837 || !startswith (msym
.minsym
->linkage_name (), ".pic."))
7840 /* A two-instruction header. */
7841 if (msym
.minsym
->size () == 8)
7844 /* A three-instruction (plus delay slot) trampoline. */
7845 if (msym
.minsym
->size () == 16)
7847 if (target_read_memory (pc
, stub_code
, 16) != 0)
7849 for (i
= 0; i
< 4; i
++)
7850 stub_words
[i
] = extract_unsigned_integer (stub_code
+ i
* 4,
7853 /* A stub contains these instructions:
7856 addiu t9, t9, %lo(target)
7859 This works even for N64, since stubs are only generated with
7861 if ((stub_words
[0] & 0xffff0000U
) == 0x3c190000
7862 && (stub_words
[1] & 0xfc000000U
) == 0x08000000
7863 && (stub_words
[2] & 0xffff0000U
) == 0x27390000
7864 && stub_words
[3] == 0x00000000)
7865 return ((((stub_words
[0] & 0x0000ffff) << 16)
7866 + (stub_words
[2] & 0x0000ffff)) ^ 0x8000) - 0x8000;
7869 /* Not a recognized stub. */
7874 mips_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7876 CORE_ADDR requested_pc
= pc
;
7877 CORE_ADDR target_pc
;
7884 new_pc
= mips_skip_mips16_trampoline_code (frame
, pc
);
7888 new_pc
= find_solib_trampoline_target (frame
, pc
);
7892 new_pc
= mips_skip_pic_trampoline_code (frame
, pc
);
7896 while (pc
!= target_pc
);
7898 return pc
!= requested_pc
? pc
: 0;
7901 /* Convert a dbx stab register number (from `r' declaration) to a GDB
7902 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7905 mips_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
7908 if (num
>= 0 && num
< 32)
7910 else if (num
>= 38 && num
< 70)
7911 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 38;
7913 regnum
= mips_regnum (gdbarch
)->hi
;
7915 regnum
= mips_regnum (gdbarch
)->lo
;
7916 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 72 && num
< 78)
7917 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 72;
7920 return gdbarch_num_regs (gdbarch
) + regnum
;
7924 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
7925 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7928 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
7931 if (num
>= 0 && num
< 32)
7933 else if (num
>= 32 && num
< 64)
7934 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 32;
7936 regnum
= mips_regnum (gdbarch
)->hi
;
7938 regnum
= mips_regnum (gdbarch
)->lo
;
7939 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 66 && num
< 72)
7940 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 66;
7943 return gdbarch_num_regs (gdbarch
) + regnum
;
7947 mips_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
7949 /* Only makes sense to supply raw registers. */
7950 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
));
7951 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
7952 decide if it is valid. Should instead define a standard sim/gdb
7953 register numbering scheme. */
7954 if (gdbarch_register_name (gdbarch
,
7955 gdbarch_num_regs (gdbarch
) + regnum
) != NULL
7956 && gdbarch_register_name (gdbarch
,
7957 gdbarch_num_regs (gdbarch
)
7958 + regnum
)[0] != '\0')
7961 return LEGACY_SIM_REGNO_IGNORE
;
7965 /* Convert an integer into an address. Extracting the value signed
7966 guarantees a correctly sign extended address. */
7969 mips_integer_to_address (struct gdbarch
*gdbarch
,
7970 struct type
*type
, const gdb_byte
*buf
)
7972 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7973 return extract_signed_integer (buf
, type
->length (), byte_order
);
7976 /* Dummy virtual frame pointer method. This is no more or less accurate
7977 than most other architectures; we just need to be explicit about it,
7978 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
7979 an assertion failure. */
7982 mips_virtual_frame_pointer (struct gdbarch
*gdbarch
,
7983 CORE_ADDR pc
, int *reg
, LONGEST
*offset
)
7985 *reg
= MIPS_SP_REGNUM
;
7990 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
7992 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
7993 const char *name
= bfd_section_name (sect
);
7995 if (*abip
!= MIPS_ABI_UNKNOWN
)
7998 if (!startswith (name
, ".mdebug."))
8001 if (strcmp (name
, ".mdebug.abi32") == 0)
8002 *abip
= MIPS_ABI_O32
;
8003 else if (strcmp (name
, ".mdebug.abiN32") == 0)
8004 *abip
= MIPS_ABI_N32
;
8005 else if (strcmp (name
, ".mdebug.abi64") == 0)
8006 *abip
= MIPS_ABI_N64
;
8007 else if (strcmp (name
, ".mdebug.abiO64") == 0)
8008 *abip
= MIPS_ABI_O64
;
8009 else if (strcmp (name
, ".mdebug.eabi32") == 0)
8010 *abip
= MIPS_ABI_EABI32
;
8011 else if (strcmp (name
, ".mdebug.eabi64") == 0)
8012 *abip
= MIPS_ABI_EABI64
;
8014 warning (_("unsupported ABI %s."), name
+ 8);
8018 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
8020 int *lbp
= (int *) obj
;
8021 const char *name
= bfd_section_name (sect
);
8023 if (startswith (name
, ".gcc_compiled_long32"))
8025 else if (startswith (name
, ".gcc_compiled_long64"))
8027 else if (startswith (name
, ".gcc_compiled_long"))
8028 warning (_("unrecognized .gcc_compiled_longXX"));
8031 static enum mips_abi
8032 global_mips_abi (void)
8036 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
8037 if (mips_abi_strings
[i
] == mips_abi_string
)
8038 return (enum mips_abi
) i
;
8040 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
8043 /* Return the default compressed instruction set, either of MIPS16
8044 or microMIPS, selected when none could have been determined from
8045 the ELF header of the binary being executed (or no binary has been
8048 static enum mips_isa
8049 global_mips_compression (void)
8053 for (i
= 0; mips_compression_strings
[i
] != NULL
; i
++)
8054 if (mips_compression_strings
[i
] == mips_compression_string
)
8055 return (enum mips_isa
) i
;
8057 internal_error (__FILE__
, __LINE__
, _("unknown compressed ISA string"));
8061 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
8063 /* If the size matches the set of 32-bit or 64-bit integer registers,
8064 assume that's what we've got. */
8065 register_remote_g_packet_guess (gdbarch
, 38 * 4, mips_tdesc_gp32
);
8066 register_remote_g_packet_guess (gdbarch
, 38 * 8, mips_tdesc_gp64
);
8068 /* If the size matches the full set of registers GDB traditionally
8069 knows about, including floating point, for either 32-bit or
8070 64-bit, assume that's what we've got. */
8071 register_remote_g_packet_guess (gdbarch
, 90 * 4, mips_tdesc_gp32
);
8072 register_remote_g_packet_guess (gdbarch
, 90 * 8, mips_tdesc_gp64
);
8074 /* Otherwise we don't have a useful guess. */
8077 static struct value
*
8078 value_of_mips_user_reg (struct frame_info
*frame
, const void *baton
)
8080 const int *reg_p
= (const int *) baton
;
8081 return value_of_register (*reg_p
, frame
);
8084 static struct gdbarch
*
8085 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
8087 struct gdbarch
*gdbarch
;
8089 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
8091 enum mips_fpu_type fpu_type
;
8092 tdesc_arch_data_up tdesc_data
;
8093 int elf_fpu_type
= Val_GNU_MIPS_ABI_FP_ANY
;
8094 const char * const *reg_names
;
8095 struct mips_regnum mips_regnum
, *regnum
;
8096 enum mips_isa mips_isa
;
8100 /* First of all, extract the elf_flags, if available. */
8101 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
8102 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
8103 else if (arches
!= NULL
)
8105 mips_gdbarch_tdep
*tdep
8106 = gdbarch_tdep
<mips_gdbarch_tdep
> (arches
->gdbarch
);
8107 elf_flags
= tdep
->elf_flags
;
8112 gdb_printf (gdb_stdlog
,
8113 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
8115 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
8116 switch ((elf_flags
& EF_MIPS_ABI
))
8118 case E_MIPS_ABI_O32
:
8119 found_abi
= MIPS_ABI_O32
;
8121 case E_MIPS_ABI_O64
:
8122 found_abi
= MIPS_ABI_O64
;
8124 case E_MIPS_ABI_EABI32
:
8125 found_abi
= MIPS_ABI_EABI32
;
8127 case E_MIPS_ABI_EABI64
:
8128 found_abi
= MIPS_ABI_EABI64
;
8131 if ((elf_flags
& EF_MIPS_ABI2
))
8132 found_abi
= MIPS_ABI_N32
;
8134 found_abi
= MIPS_ABI_UNKNOWN
;
8138 /* GCC creates a pseudo-section whose name describes the ABI. */
8139 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
8140 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
8142 /* If we have no useful BFD information, use the ABI from the last
8143 MIPS architecture (if there is one). */
8144 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
8146 mips_gdbarch_tdep
*tdep
8147 = gdbarch_tdep
<mips_gdbarch_tdep
> (arches
->gdbarch
);
8148 found_abi
= tdep
->found_abi
;
8151 /* Try the architecture for any hint of the correct ABI. */
8152 if (found_abi
== MIPS_ABI_UNKNOWN
8153 && info
.bfd_arch_info
!= NULL
8154 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
8156 switch (info
.bfd_arch_info
->mach
)
8158 case bfd_mach_mips3900
:
8159 found_abi
= MIPS_ABI_EABI32
;
8161 case bfd_mach_mips4100
:
8162 case bfd_mach_mips5000
:
8163 found_abi
= MIPS_ABI_EABI64
;
8165 case bfd_mach_mips8000
:
8166 case bfd_mach_mips10000
:
8167 /* On Irix, ELF64 executables use the N64 ABI. The
8168 pseudo-sections which describe the ABI aren't present
8169 on IRIX. (Even for executables created by gcc.) */
8170 if (info
.abfd
!= NULL
8171 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
8172 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
8173 found_abi
= MIPS_ABI_N64
;
8175 found_abi
= MIPS_ABI_N32
;
8180 /* Default 64-bit objects to N64 instead of O32. */
8181 if (found_abi
== MIPS_ABI_UNKNOWN
8182 && info
.abfd
!= NULL
8183 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
8184 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
8185 found_abi
= MIPS_ABI_N64
;
8188 gdb_printf (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
8191 /* What has the user specified from the command line? */
8192 wanted_abi
= global_mips_abi ();
8194 gdb_printf (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
8197 /* Now that we have found what the ABI for this binary would be,
8198 check whether the user is overriding it. */
8199 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
8200 mips_abi
= wanted_abi
;
8201 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
8202 mips_abi
= found_abi
;
8204 mips_abi
= MIPS_ABI_O32
;
8206 gdb_printf (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
8209 /* Make sure we don't use a 32-bit architecture with a 64-bit ABI. */
8210 if (mips_abi
!= MIPS_ABI_EABI32
8211 && mips_abi
!= MIPS_ABI_O32
8212 && info
.bfd_arch_info
!= NULL
8213 && info
.bfd_arch_info
->arch
== bfd_arch_mips
8214 && info
.bfd_arch_info
->bits_per_word
< 64)
8215 info
.bfd_arch_info
= bfd_lookup_arch (bfd_arch_mips
, bfd_mach_mips4000
);
8217 /* Determine the default compressed ISA. */
8218 if ((elf_flags
& EF_MIPS_ARCH_ASE_MICROMIPS
) != 0
8219 && (elf_flags
& EF_MIPS_ARCH_ASE_M16
) == 0)
8220 mips_isa
= ISA_MICROMIPS
;
8221 else if ((elf_flags
& EF_MIPS_ARCH_ASE_M16
) != 0
8222 && (elf_flags
& EF_MIPS_ARCH_ASE_MICROMIPS
) == 0)
8223 mips_isa
= ISA_MIPS16
;
8225 mips_isa
= global_mips_compression ();
8226 mips_compression_string
= mips_compression_strings
[mips_isa
];
8228 /* Also used when doing an architecture lookup. */
8230 gdb_printf (gdb_stdlog
,
8231 "mips_gdbarch_init: "
8232 "mips64_transfers_32bit_regs_p = %d\n",
8233 mips64_transfers_32bit_regs_p
);
8235 /* Determine the MIPS FPU type. */
8238 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
8239 elf_fpu_type
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
8240 Tag_GNU_MIPS_ABI_FP
);
8241 #endif /* HAVE_ELF */
8243 if (!mips_fpu_type_auto
)
8244 fpu_type
= mips_fpu_type
;
8245 else if (elf_fpu_type
!= Val_GNU_MIPS_ABI_FP_ANY
)
8247 switch (elf_fpu_type
)
8249 case Val_GNU_MIPS_ABI_FP_DOUBLE
:
8250 fpu_type
= MIPS_FPU_DOUBLE
;
8252 case Val_GNU_MIPS_ABI_FP_SINGLE
:
8253 fpu_type
= MIPS_FPU_SINGLE
;
8255 case Val_GNU_MIPS_ABI_FP_SOFT
:
8257 /* Soft float or unknown. */
8258 fpu_type
= MIPS_FPU_NONE
;
8262 else if (info
.bfd_arch_info
!= NULL
8263 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
8264 switch (info
.bfd_arch_info
->mach
)
8266 case bfd_mach_mips3900
:
8267 case bfd_mach_mips4100
:
8268 case bfd_mach_mips4111
:
8269 case bfd_mach_mips4120
:
8270 fpu_type
= MIPS_FPU_NONE
;
8272 case bfd_mach_mips4650
:
8273 fpu_type
= MIPS_FPU_SINGLE
;
8276 fpu_type
= MIPS_FPU_DOUBLE
;
8279 else if (arches
!= NULL
)
8280 fpu_type
= mips_get_fpu_type (arches
->gdbarch
);
8282 fpu_type
= MIPS_FPU_DOUBLE
;
8284 gdb_printf (gdb_stdlog
,
8285 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
8287 /* Check for blatant incompatibilities. */
8289 /* If we have only 32-bit registers, then we can't debug a 64-bit
8291 if (info
.target_desc
8292 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
8293 && mips_abi
!= MIPS_ABI_EABI32
8294 && mips_abi
!= MIPS_ABI_O32
)
8297 /* Fill in the OS dependent register numbers and names. */
8298 if (info
.osabi
== GDB_OSABI_LINUX
)
8300 mips_regnum
.fp0
= 38;
8301 mips_regnum
.pc
= 37;
8302 mips_regnum
.cause
= 36;
8303 mips_regnum
.badvaddr
= 35;
8304 mips_regnum
.hi
= 34;
8305 mips_regnum
.lo
= 33;
8306 mips_regnum
.fp_control_status
= 70;
8307 mips_regnum
.fp_implementation_revision
= 71;
8308 mips_regnum
.dspacc
= -1;
8309 mips_regnum
.dspctl
= -1;
8313 reg_names
= mips_linux_reg_names
;
8317 mips_regnum
.lo
= MIPS_EMBED_LO_REGNUM
;
8318 mips_regnum
.hi
= MIPS_EMBED_HI_REGNUM
;
8319 mips_regnum
.badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
8320 mips_regnum
.cause
= MIPS_EMBED_CAUSE_REGNUM
;
8321 mips_regnum
.pc
= MIPS_EMBED_PC_REGNUM
;
8322 mips_regnum
.fp0
= MIPS_EMBED_FP0_REGNUM
;
8323 mips_regnum
.fp_control_status
= 70;
8324 mips_regnum
.fp_implementation_revision
= 71;
8325 mips_regnum
.dspacc
= dspacc
= -1;
8326 mips_regnum
.dspctl
= dspctl
= -1;
8327 num_regs
= MIPS_LAST_EMBED_REGNUM
+ 1;
8328 if (info
.bfd_arch_info
!= NULL
8329 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
8330 reg_names
= mips_tx39_reg_names
;
8332 reg_names
= mips_generic_reg_names
;
8335 /* Check any target description for validity. */
8336 if (tdesc_has_registers (info
.target_desc
))
8338 static const char *const mips_gprs
[] = {
8339 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
8340 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
8341 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
8342 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
8344 static const char *const mips_fprs
[] = {
8345 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
8346 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
8347 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
8348 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
8351 const struct tdesc_feature
*feature
;
8354 feature
= tdesc_find_feature (info
.target_desc
,
8355 "org.gnu.gdb.mips.cpu");
8356 if (feature
== NULL
)
8359 tdesc_data
= tdesc_data_alloc ();
8362 for (i
= MIPS_ZERO_REGNUM
; i
<= MIPS_RA_REGNUM
; i
++)
8363 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (), i
,
8367 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8368 mips_regnum
.lo
, "lo");
8369 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8370 mips_regnum
.hi
, "hi");
8371 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8372 mips_regnum
.pc
, "pc");
8377 feature
= tdesc_find_feature (info
.target_desc
,
8378 "org.gnu.gdb.mips.cp0");
8379 if (feature
== NULL
)
8383 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8384 mips_regnum
.badvaddr
, "badvaddr");
8385 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8386 MIPS_PS_REGNUM
, "status");
8387 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8388 mips_regnum
.cause
, "cause");
8393 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
8394 backend is not prepared for that, though. */
8395 feature
= tdesc_find_feature (info
.target_desc
,
8396 "org.gnu.gdb.mips.fpu");
8397 if (feature
== NULL
)
8401 for (i
= 0; i
< 32; i
++)
8402 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8403 i
+ mips_regnum
.fp0
, mips_fprs
[i
]);
8405 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8406 mips_regnum
.fp_control_status
,
8409 &= tdesc_numbered_register (feature
, tdesc_data
.get (),
8410 mips_regnum
.fp_implementation_revision
,
8416 num_regs
= mips_regnum
.fp_implementation_revision
+ 1;
8420 feature
= tdesc_find_feature (info
.target_desc
,
8421 "org.gnu.gdb.mips.dsp");
8422 /* The DSP registers are optional; it's OK if they are absent. */
8423 if (feature
!= NULL
)
8427 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8428 dspacc
+ i
++, "hi1");
8429 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8430 dspacc
+ i
++, "lo1");
8431 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8432 dspacc
+ i
++, "hi2");
8433 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8434 dspacc
+ i
++, "lo2");
8435 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8436 dspacc
+ i
++, "hi3");
8437 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8438 dspacc
+ i
++, "lo3");
8440 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8446 mips_regnum
.dspacc
= dspacc
;
8447 mips_regnum
.dspctl
= dspctl
;
8449 num_regs
= mips_regnum
.dspctl
+ 1;
8453 /* It would be nice to detect an attempt to use a 64-bit ABI
8454 when only 32-bit registers are provided. */
8458 /* Try to find a pre-existing architecture. */
8459 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
8461 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
8463 mips_gdbarch_tdep
*tdep
8464 = gdbarch_tdep
<mips_gdbarch_tdep
> (arches
->gdbarch
);
8466 /* MIPS needs to be pedantic about which ABI and the compressed
8467 ISA variation the object is using. */
8468 if (tdep
->elf_flags
!= elf_flags
)
8470 if (tdep
->mips_abi
!= mips_abi
)
8472 if (tdep
->mips_isa
!= mips_isa
)
8474 /* Need to be pedantic about which register virtual size is
8476 if (tdep
->mips64_transfers_32bit_regs_p
8477 != mips64_transfers_32bit_regs_p
)
8479 /* Be pedantic about which FPU is selected. */
8480 if (mips_get_fpu_type (arches
->gdbarch
) != fpu_type
)
8483 return arches
->gdbarch
;
8486 /* Need a new architecture. Fill in a target specific vector. */
8487 mips_gdbarch_tdep
*tdep
= new mips_gdbarch_tdep
;
8488 gdbarch
= gdbarch_alloc (&info
, tdep
);
8489 tdep
->elf_flags
= elf_flags
;
8490 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
8491 tdep
->found_abi
= found_abi
;
8492 tdep
->mips_abi
= mips_abi
;
8493 tdep
->mips_isa
= mips_isa
;
8494 tdep
->mips_fpu_type
= fpu_type
;
8495 tdep
->register_size_valid_p
= 0;
8496 tdep
->register_size
= 0;
8498 if (info
.target_desc
)
8500 /* Some useful properties can be inferred from the target. */
8501 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
8503 tdep
->register_size_valid_p
= 1;
8504 tdep
->register_size
= 4;
8506 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
8508 tdep
->register_size_valid_p
= 1;
8509 tdep
->register_size
= 8;
8513 /* Initially set everything according to the default ABI/ISA. */
8514 set_gdbarch_short_bit (gdbarch
, 16);
8515 set_gdbarch_int_bit (gdbarch
, 32);
8516 set_gdbarch_float_bit (gdbarch
, 32);
8517 set_gdbarch_double_bit (gdbarch
, 64);
8518 set_gdbarch_long_double_bit (gdbarch
, 64);
8519 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
8520 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
8521 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
8523 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
8524 mips_ax_pseudo_register_collect
);
8525 set_gdbarch_ax_pseudo_register_push_stack
8526 (gdbarch
, mips_ax_pseudo_register_push_stack
);
8528 set_gdbarch_elf_make_msymbol_special (gdbarch
,
8529 mips_elf_make_msymbol_special
);
8530 set_gdbarch_make_symbol_special (gdbarch
, mips_make_symbol_special
);
8531 set_gdbarch_adjust_dwarf2_addr (gdbarch
, mips_adjust_dwarf2_addr
);
8532 set_gdbarch_adjust_dwarf2_line (gdbarch
, mips_adjust_dwarf2_line
);
8534 regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
, struct mips_regnum
);
8535 *regnum
= mips_regnum
;
8536 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
8537 set_gdbarch_num_regs (gdbarch
, num_regs
);
8538 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
8539 set_gdbarch_register_name (gdbarch
, mips_register_name
);
8540 set_gdbarch_virtual_frame_pointer (gdbarch
, mips_virtual_frame_pointer
);
8541 tdep
->mips_processor_reg_names
= reg_names
;
8542 tdep
->regnum
= regnum
;
8547 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
8548 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
8549 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
8550 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
8551 tdep
->default_mask_address_p
= 0;
8552 set_gdbarch_long_bit (gdbarch
, 32);
8553 set_gdbarch_ptr_bit (gdbarch
, 32);
8554 set_gdbarch_long_long_bit (gdbarch
, 64);
8557 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
8558 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
8559 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
8560 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
8561 tdep
->default_mask_address_p
= 0;
8562 set_gdbarch_long_bit (gdbarch
, 32);
8563 set_gdbarch_ptr_bit (gdbarch
, 32);
8564 set_gdbarch_long_long_bit (gdbarch
, 64);
8566 case MIPS_ABI_EABI32
:
8567 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
8568 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
8569 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8570 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8571 tdep
->default_mask_address_p
= 0;
8572 set_gdbarch_long_bit (gdbarch
, 32);
8573 set_gdbarch_ptr_bit (gdbarch
, 32);
8574 set_gdbarch_long_long_bit (gdbarch
, 64);
8576 case MIPS_ABI_EABI64
:
8577 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
8578 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
8579 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8580 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8581 tdep
->default_mask_address_p
= 0;
8582 set_gdbarch_long_bit (gdbarch
, 64);
8583 set_gdbarch_ptr_bit (gdbarch
, 64);
8584 set_gdbarch_long_long_bit (gdbarch
, 64);
8587 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
8588 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
8589 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8590 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8591 tdep
->default_mask_address_p
= 0;
8592 set_gdbarch_long_bit (gdbarch
, 32);
8593 set_gdbarch_ptr_bit (gdbarch
, 32);
8594 set_gdbarch_long_long_bit (gdbarch
, 64);
8595 set_gdbarch_long_double_bit (gdbarch
, 128);
8596 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
8599 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
8600 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
8601 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8602 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8603 tdep
->default_mask_address_p
= 0;
8604 set_gdbarch_long_bit (gdbarch
, 64);
8605 set_gdbarch_ptr_bit (gdbarch
, 64);
8606 set_gdbarch_long_long_bit (gdbarch
, 64);
8607 set_gdbarch_long_double_bit (gdbarch
, 128);
8608 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
8611 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
8614 /* GCC creates a pseudo-section whose name specifies the size of
8615 longs, since -mlong32 or -mlong64 may be used independent of
8616 other options. How those options affect pointer sizes is ABI and
8617 architecture dependent, so use them to override the default sizes
8618 set by the ABI. This table shows the relationship between ABI,
8619 -mlongXX, and size of pointers:
8621 ABI -mlongXX ptr bits
8622 --- -------- --------
8636 Note that for o32 and eabi32, pointers are always 32 bits
8637 regardless of any -mlongXX option. For all others, pointers and
8638 longs are the same, as set by -mlongXX or set by defaults. */
8640 if (info
.abfd
!= NULL
)
8644 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
8647 set_gdbarch_long_bit (gdbarch
, long_bit
);
8651 case MIPS_ABI_EABI32
:
8656 case MIPS_ABI_EABI64
:
8657 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
8660 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
8665 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
8666 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
8669 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
8670 flag in object files because to do so would make it impossible to
8671 link with libraries compiled without "-gp32". This is
8672 unnecessarily restrictive.
8674 We could solve this problem by adding "-gp32" multilibs to gcc,
8675 but to set this flag before gcc is built with such multilibs will
8676 break too many systems.''
8678 But even more unhelpfully, the default linker output target for
8679 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
8680 for 64-bit programs - you need to change the ABI to change this,
8681 and not all gcc targets support that currently. Therefore using
8682 this flag to detect 32-bit mode would do the wrong thing given
8683 the current gcc - it would make GDB treat these 64-bit programs
8684 as 32-bit programs by default. */
8686 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
8687 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
8689 /* Add/remove bits from an address. The MIPS needs be careful to
8690 ensure that all 32 bit addresses are sign extended to 64 bits. */
8691 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
8693 /* Unwind the frame. */
8694 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
8695 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
8696 set_gdbarch_dummy_id (gdbarch
, mips_dummy_id
);
8698 /* Map debug register numbers onto internal register numbers. */
8699 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
8700 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
8701 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
8702 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
8703 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
8704 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
8706 /* MIPS version of CALL_DUMMY. */
8708 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
8709 set_gdbarch_push_dummy_code (gdbarch
, mips_push_dummy_code
);
8710 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
8712 set_gdbarch_print_float_info (gdbarch
, mips_print_float_info
);
8714 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
8715 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
8716 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
8718 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
8719 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, mips_breakpoint_kind_from_pc
);
8720 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, mips_sw_breakpoint_from_kind
);
8721 set_gdbarch_adjust_breakpoint_address (gdbarch
,
8722 mips_adjust_breakpoint_address
);
8724 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
8726 set_gdbarch_stack_frame_destroyed_p (gdbarch
, mips_stack_frame_destroyed_p
);
8728 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
8729 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
8730 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
8732 set_gdbarch_register_type (gdbarch
, mips_register_type
);
8734 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
8736 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
8737 if (mips_abi
== MIPS_ABI_N64
)
8738 set_gdbarch_disassembler_options_implicit
8739 (gdbarch
, (const char *) mips_disassembler_options_n64
);
8740 else if (mips_abi
== MIPS_ABI_N32
)
8741 set_gdbarch_disassembler_options_implicit
8742 (gdbarch
, (const char *) mips_disassembler_options_n32
);
8744 set_gdbarch_disassembler_options_implicit
8745 (gdbarch
, (const char *) mips_disassembler_options_o32
);
8746 set_gdbarch_disassembler_options (gdbarch
, &mips_disassembler_options
);
8747 set_gdbarch_valid_disassembler_options (gdbarch
,
8748 disassembler_options_mips ());
8750 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint,
8751 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint
8752 need to all be folded into the target vector. Since they are
8753 being used as guards for target_stopped_by_watchpoint, why not have
8754 target_stopped_by_watchpoint return the type of watchpoint that the code
8756 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
8758 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
8760 /* NOTE drow/2012-04-25: We overload the core solib trampoline code
8761 to support MIPS16. This is a bad thing. Make sure not to do it
8762 if we have an OS ABI that actually supports shared libraries, since
8763 shared library support is more important. If we have an OS someday
8764 that supports both shared libraries and MIPS16, we'll have to find
8765 a better place for these.
8766 macro/2012-04-25: But that applies to return trampolines only and
8767 currently no MIPS OS ABI uses shared libraries that have them. */
8768 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
8770 set_gdbarch_single_step_through_delay (gdbarch
,
8771 mips_single_step_through_delay
);
8773 /* Virtual tables. */
8774 set_gdbarch_vbit_in_delta (gdbarch
, 1);
8776 mips_register_g_packet_guesses (gdbarch
);
8778 /* Hook in OS ABI-specific overrides, if they have been registered. */
8779 info
.tdesc_data
= tdesc_data
.get ();
8780 gdbarch_init_osabi (info
, gdbarch
);
8782 /* The hook may have adjusted num_regs, fetch the final value and
8783 set pc_regnum and sp_regnum now that it has been fixed. */
8784 num_regs
= gdbarch_num_regs (gdbarch
);
8785 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
8786 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
8788 /* Unwind the frame. */
8789 dwarf2_append_unwinders (gdbarch
);
8790 frame_unwind_append_unwinder (gdbarch
, &mips_stub_frame_unwind
);
8791 frame_unwind_append_unwinder (gdbarch
, &mips_insn16_frame_unwind
);
8792 frame_unwind_append_unwinder (gdbarch
, &mips_micro_frame_unwind
);
8793 frame_unwind_append_unwinder (gdbarch
, &mips_insn32_frame_unwind
);
8794 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
8795 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
8796 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
8797 frame_base_append_sniffer (gdbarch
, mips_micro_frame_base_sniffer
);
8798 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
8800 if (tdesc_data
!= nullptr)
8802 set_tdesc_pseudo_register_type (gdbarch
, mips_pseudo_register_type
);
8803 tdesc_use_registers (gdbarch
, info
.target_desc
, std::move (tdesc_data
));
8805 /* Override the normal target description methods to handle our
8806 dual real and pseudo registers. */
8807 set_gdbarch_register_name (gdbarch
, mips_register_name
);
8808 set_gdbarch_register_reggroup_p (gdbarch
,
8809 mips_tdesc_register_reggroup_p
);
8811 num_regs
= gdbarch_num_regs (gdbarch
);
8812 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
8813 set_gdbarch_pc_regnum (gdbarch
, tdep
->regnum
->pc
+ num_regs
);
8814 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
8817 /* Add ABI-specific aliases for the registers. */
8818 if (mips_abi
== MIPS_ABI_N32
|| mips_abi
== MIPS_ABI_N64
)
8819 for (i
= 0; i
< ARRAY_SIZE (mips_n32_n64_aliases
); i
++)
8820 user_reg_add (gdbarch
, mips_n32_n64_aliases
[i
].name
,
8821 value_of_mips_user_reg
, &mips_n32_n64_aliases
[i
].regnum
);
8823 for (i
= 0; i
< ARRAY_SIZE (mips_o32_aliases
); i
++)
8824 user_reg_add (gdbarch
, mips_o32_aliases
[i
].name
,
8825 value_of_mips_user_reg
, &mips_o32_aliases
[i
].regnum
);
8827 /* Add some other standard aliases. */
8828 for (i
= 0; i
< ARRAY_SIZE (mips_register_aliases
); i
++)
8829 user_reg_add (gdbarch
, mips_register_aliases
[i
].name
,
8830 value_of_mips_user_reg
, &mips_register_aliases
[i
].regnum
);
8832 for (i
= 0; i
< ARRAY_SIZE (mips_numeric_register_aliases
); i
++)
8833 user_reg_add (gdbarch
, mips_numeric_register_aliases
[i
].name
,
8834 value_of_mips_user_reg
,
8835 &mips_numeric_register_aliases
[i
].regnum
);
8841 mips_abi_update (const char *ignore_args
,
8842 int from_tty
, struct cmd_list_element
*c
)
8844 struct gdbarch_info info
;
8846 /* Force the architecture to update, and (if it's a MIPS architecture)
8847 mips_gdbarch_init will take care of the rest. */
8848 gdbarch_update_p (info
);
8851 /* Print out which MIPS ABI is in use. */
8854 show_mips_abi (struct ui_file
*file
,
8856 struct cmd_list_element
*ignored_cmd
,
8857 const char *ignored_value
)
8859 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_mips
)
8862 "The MIPS ABI is unknown because the current architecture "
8866 enum mips_abi global_abi
= global_mips_abi ();
8867 enum mips_abi actual_abi
= mips_abi (target_gdbarch ());
8868 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
8870 if (global_abi
== MIPS_ABI_UNKNOWN
)
8873 "The MIPS ABI is set automatically (currently \"%s\").\n",
8875 else if (global_abi
== actual_abi
)
8878 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
8882 /* Probably shouldn't happen... */
8884 "The (auto detected) MIPS ABI \"%s\" is in use "
8885 "even though the user setting was \"%s\".\n",
8886 actual_abi_str
, mips_abi_strings
[global_abi
]);
8891 /* Print out which MIPS compressed ISA encoding is used. */
8894 show_mips_compression (struct ui_file
*file
, int from_tty
,
8895 struct cmd_list_element
*c
, const char *value
)
8897 gdb_printf (file
, _("The compressed ISA encoding used is %s.\n"),
8901 /* Return a textual name for MIPS FPU type FPU_TYPE. */
8904 mips_fpu_type_str (enum mips_fpu_type fpu_type
)
8910 case MIPS_FPU_SINGLE
:
8912 case MIPS_FPU_DOUBLE
:
8920 mips_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
8922 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
8926 int ef_mips_32bitmode
;
8927 /* Determine the ISA. */
8928 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
8946 /* Determine the size of a pointer. */
8947 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
8949 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
8952 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
8955 "mips_dump_tdep: ef_mips_arch = %d\n",
8958 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
8959 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
8962 "mips_mask_address_p() %d (default %d)\n",
8963 mips_mask_address_p (tdep
),
8964 tdep
->default_mask_address_p
);
8967 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
8968 MIPS_DEFAULT_FPU_TYPE
,
8969 mips_fpu_type_str (MIPS_DEFAULT_FPU_TYPE
));
8970 gdb_printf (file
, "mips_dump_tdep: MIPS_EABI = %d\n",
8971 mips_eabi (gdbarch
));
8973 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
8974 mips_get_fpu_type (gdbarch
),
8975 mips_fpu_type_str (mips_get_fpu_type (gdbarch
)));
8978 void _initialize_mips_tdep ();
8980 _initialize_mips_tdep ()
8982 static struct cmd_list_element
*mipsfpulist
= NULL
;
8984 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
8985 if (MIPS_ABI_LAST
+ 1
8986 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
8987 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
8989 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
8991 /* Create feature sets with the appropriate properties. The values
8992 are not important. */
8993 mips_tdesc_gp32
= allocate_target_description ().release ();
8994 set_tdesc_property (mips_tdesc_gp32
, PROPERTY_GP32
, "");
8996 mips_tdesc_gp64
= allocate_target_description ().release ();
8997 set_tdesc_property (mips_tdesc_gp64
, PROPERTY_GP64
, "");
8999 /* Add root prefix command for all "set mips"/"show mips" commands. */
9000 add_setshow_prefix_cmd ("mips", no_class
,
9001 _("Various MIPS specific commands."),
9002 _("Various MIPS specific commands."),
9003 &setmipscmdlist
, &showmipscmdlist
,
9004 &setlist
, &showlist
);
9006 /* Allow the user to override the ABI. */
9007 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
9008 &mips_abi_string
, _("\
9009 Set the MIPS ABI used by this program."), _("\
9010 Show the MIPS ABI used by this program."), _("\
9011 This option can be set to one of:\n\
9012 auto - the default ABI associated with the current binary\n\
9021 &setmipscmdlist
, &showmipscmdlist
);
9023 /* Allow the user to set the ISA to assume for compressed code if ELF
9024 file flags don't tell or there is no program file selected. This
9025 setting is updated whenever unambiguous ELF file flags are interpreted,
9026 and carried over to subsequent sessions. */
9027 add_setshow_enum_cmd ("compression", class_obscure
, mips_compression_strings
,
9028 &mips_compression_string
, _("\
9029 Set the compressed ISA encoding used by MIPS code."), _("\
9030 Show the compressed ISA encoding used by MIPS code."), _("\
9031 Select the compressed ISA encoding used in functions that have no symbol\n\
9032 information available. The encoding can be set to either of:\n\
9035 and is updated automatically from ELF file flags if available."),
9037 show_mips_compression
,
9038 &setmipscmdlist
, &showmipscmdlist
);
9040 /* Let the user turn off floating point and set the fence post for
9041 heuristic_proc_start. */
9043 add_basic_prefix_cmd ("mipsfpu", class_support
,
9044 _("Set use of MIPS floating-point coprocessor."),
9045 &mipsfpulist
, 0, &setlist
);
9046 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
9047 _("Select single-precision MIPS floating-point coprocessor."),
9049 cmd_list_element
*set_mipsfpu_double_cmd
9050 = add_cmd ("double", class_support
, set_mipsfpu_double_command
,
9051 _("Select double-precision MIPS floating-point coprocessor."),
9053 add_alias_cmd ("on", set_mipsfpu_double_cmd
, class_support
, 1, &mipsfpulist
);
9054 add_alias_cmd ("yes", set_mipsfpu_double_cmd
, class_support
, 1, &mipsfpulist
);
9055 add_alias_cmd ("1", set_mipsfpu_double_cmd
, class_support
, 1, &mipsfpulist
);
9057 cmd_list_element
*set_mipsfpu_none_cmd
9058 = add_cmd ("none", class_support
, set_mipsfpu_none_command
,
9059 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
9060 add_alias_cmd ("off", set_mipsfpu_none_cmd
, class_support
, 1, &mipsfpulist
);
9061 add_alias_cmd ("no", set_mipsfpu_none_cmd
, class_support
, 1, &mipsfpulist
);
9062 add_alias_cmd ("0", set_mipsfpu_none_cmd
, class_support
, 1, &mipsfpulist
);
9063 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
9064 _("Select MIPS floating-point coprocessor automatically."),
9066 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
9067 _("Show current use of MIPS floating-point coprocessor target."),
9070 /* We really would like to have both "0" and "unlimited" work, but
9071 command.c doesn't deal with that. So make it a var_zinteger
9072 because the user can always use "999999" or some such for unlimited. */
9073 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
9074 &heuristic_fence_post
, _("\
9075 Set the distance searched for the start of a function."), _("\
9076 Show the distance searched for the start of a function."), _("\
9077 If you are debugging a stripped executable, GDB needs to search through the\n\
9078 program for the start of a function. This command sets the distance of the\n\
9079 search. The only need to set it is when debugging a stripped executable."),
9080 reinit_frame_cache_sfunc
,
9081 NULL
, /* FIXME: i18n: The distance searched for
9082 the start of a function is %s. */
9083 &setlist
, &showlist
);
9085 /* Allow the user to control whether the upper bits of 64-bit
9086 addresses should be zeroed. */
9087 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
9088 &mask_address_var
, _("\
9089 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
9090 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
9091 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\
9092 allow GDB to determine the correct value."),
9093 NULL
, show_mask_address
,
9094 &setmipscmdlist
, &showmipscmdlist
);
9096 /* Allow the user to control the size of 32 bit registers within the
9097 raw remote packet. */
9098 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
9099 &mips64_transfers_32bit_regs_p
, _("\
9100 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
9102 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
9104 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
9105 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
9106 64 bits for others. Use \"off\" to disable compatibility mode"),
9107 set_mips64_transfers_32bit_regs
,
9108 NULL
, /* FIXME: i18n: Compatibility with 64-bit
9109 MIPS target that transfers 32-bit
9110 quantities is %s. */
9111 &setlist
, &showlist
);
9113 /* Debug this files internals. */
9114 add_setshow_zuinteger_cmd ("mips", class_maintenance
,
9116 Set mips debugging."), _("\
9117 Show mips debugging."), _("\
9118 When non-zero, mips specific debugging is enabled."),
9120 NULL
, /* FIXME: i18n: Mips debugging is
9122 &setdebuglist
, &showdebuglist
);