gdb/nat/aarch64-linux-hw-point.h

   1 /* Copyright (C) 2009-2022 Free Software Foundation, Inc.
   2    Contributed by ARM Ltd.
   3
   4    This file is part of GDB.
   5
   6    This program is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3 of the License, or
   9    (at your option) any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  18
  19 #ifndef NAT_AARCH64_LINUX_HW_POINT_H
  20 #define NAT_AARCH64_LINUX_HW_POINT_H
  21
  22 #include "gdbsupport/break-common.h" /* For enum target_hw_bp_type.  */
  23
  24 /* Macro definitions, data structures, and code for the hardware
  25    breakpoint and hardware watchpoint support follow.  We use the
  26    following abbreviations throughout the code:
  27
  28    hw - hardware
  29    bp - breakpoint
  30    wp - watchpoint  */
  31
  32 /* Maximum number of hardware breakpoint and watchpoint registers.
  33    Neither of these values may exceed the width of dr_changed_t
  34    measured in bits.  */
  35
  36 #define AARCH64_HBP_MAX_NUM 16
  37 #define AARCH64_HWP_MAX_NUM 16
  38
  39 /* Alignment requirement in bytes for addresses written to
  40    hardware breakpoint and watchpoint value registers.
  41
  42    A ptrace call attempting to set an address that does not meet the
  43    alignment criteria will fail.  Limited support has been provided in
  44    this port for unaligned watchpoints, such that from a GDB user
  45    perspective, an unaligned watchpoint may be requested.
  46
  47    This is achieved by minimally enlarging the watched area to meet the
  48    alignment requirement, and if necessary, splitting the watchpoint
  49    over several hardware watchpoint registers.  */
  50
  51 #define AARCH64_HBP_ALIGNMENT 4
  52 #define AARCH64_HWP_ALIGNMENT 8
  53
  54 /* The maximum length of a memory region that can be watched by one
  55    hardware watchpoint register.  */
  56
  57 #define AARCH64_HWP_MAX_LEN_PER_REG 8
  58
  59 /* ptrace hardware breakpoint resource info is formatted as follows:
  60
  61    31             24             16               8              0
  62    +---------------+--------------+---------------+---------------+
  63    |   RESERVED    |   RESERVED   |   DEBUG_ARCH  |  NUM_SLOTS    |
  64    +---------------+--------------+---------------+---------------+  */
  65
  66
  67 /* Macros to extract fields from the hardware debug information word.  */
  68 #define AARCH64_DEBUG_NUM_SLOTS(x) ((x) & 0xff)
  69 #define AARCH64_DEBUG_ARCH(x) (((x) >> 8) & 0xff)
  70
  71 /* Macro for the expected version of the ARMv8-A debug architecture.  */
  72 #define AARCH64_DEBUG_ARCH_V8 0x6
  73 #define AARCH64_DEBUG_ARCH_V8_1 0x7
  74 #define AARCH64_DEBUG_ARCH_V8_2 0x8
  75 #define AARCH64_DEBUG_ARCH_V8_4 0x9
  76
  77 /* ptrace expects control registers to be formatted as follows:
  78
  79    31                             13          5      3      1     0
  80    +--------------------------------+----------+------+------+----+
  81    |         RESERVED (SBZ)         |   MASK   | TYPE | PRIV | EN |
  82    +--------------------------------+----------+------+------+----+
  83
  84    The TYPE field is ignored for breakpoints.  */
  85
  86 #define DR_CONTROL_ENABLED(ctrl)        (((ctrl) & 0x1) == 1)
  87 #define DR_CONTROL_MASK(ctrl)           (((ctrl) >> 5) & 0xff)
  88
  89 /* Each bit of a variable of this type is used to indicate whether a
  90    hardware breakpoint or watchpoint setting has been changed since
  91    the last update.
  92
  93    Bit N corresponds to the Nth hardware breakpoint or watchpoint
  94    setting which is managed in aarch64_debug_reg_state, where N is
  95    valid between 0 and the total number of the hardware breakpoint or
  96    watchpoint debug registers minus 1.
  97
  98    When bit N is 1, the corresponding breakpoint or watchpoint setting
  99    has changed, and therefore the corresponding hardware debug
 100    register needs to be updated via the ptrace interface.
 101
 102    In the per-thread arch-specific data area, we define two such
 103    variables for per-thread hardware breakpoint and watchpoint
 104    settings respectively.
 105
 106    This type is part of the mechanism which helps reduce the number of
 107    ptrace calls to the kernel, i.e. avoid asking the kernel to write
 108    to the debug registers with unchanged values.  */
 109
 110 typedef ULONGEST dr_changed_t;
 111
 112 /* Set each of the lower M bits of X to 1; assert X is wide enough.  */
 113
 114 #define DR_MARK_ALL_CHANGED(x, m)                                       \
 115   do                                                                    \
 116     {                                                                   \
 117       gdb_assert (sizeof ((x)) * 8 >= (m));                             \
 118       (x) = (((dr_changed_t)1 << (m)) - 1);                             \
 119     } while (0)
 120
 121 #define DR_MARK_N_CHANGED(x, n)                                         \
 122   do                                                                    \
 123     {                                                                   \
 124       (x) |= ((dr_changed_t)1 << (n));                                  \
 125     } while (0)
 126
 127 #define DR_CLEAR_CHANGED(x)                                             \
 128   do                                                                    \
 129     {                                                                   \
 130       (x) = 0;                                                          \
 131     } while (0)
 132
 133 #define DR_HAS_CHANGED(x) ((x) != 0)
 134 #define DR_N_HAS_CHANGED(x, n) ((x) & ((dr_changed_t)1 << (n)))
 135
 136 /* Structure for managing the hardware breakpoint/watchpoint resources.
 137    DR_ADDR_* stores the address, DR_CTRL_* stores the control register
 138    content, and DR_REF_COUNT_* counts the numbers of references to the
 139    corresponding bp/wp, by which way the limited hardware resources
 140    are not wasted on duplicated bp/wp settings (though so far gdb has
 141    done a good job by not sending duplicated bp/wp requests).  */
 142
 143 struct aarch64_debug_reg_state
 144 {
 145   /* hardware breakpoint */
 146   CORE_ADDR dr_addr_bp[AARCH64_HBP_MAX_NUM];
 147   unsigned int dr_ctrl_bp[AARCH64_HBP_MAX_NUM];
 148   unsigned int dr_ref_count_bp[AARCH64_HBP_MAX_NUM];
 149
 150   /* hardware watchpoint */
 151   /* Address aligned down to AARCH64_HWP_ALIGNMENT.  */
 152   CORE_ADDR dr_addr_wp[AARCH64_HWP_MAX_NUM];
 153   /* Address as entered by user without any forced alignment.  */
 154   CORE_ADDR dr_addr_orig_wp[AARCH64_HWP_MAX_NUM];
 155   unsigned int dr_ctrl_wp[AARCH64_HWP_MAX_NUM];
 156   unsigned int dr_ref_count_wp[AARCH64_HWP_MAX_NUM];
 157 };
 158
 159 /* Per-thread arch-specific data we want to keep.  */
 160
 161 struct arch_lwp_info
 162 {
 163   /* When bit N is 1, it indicates the Nth hardware breakpoint or
 164      watchpoint register pair needs to be updated when the thread is
 165      resumed; see aarch64_linux_prepare_to_resume.  */
 166   dr_changed_t dr_changed_bp;
 167   dr_changed_t dr_changed_wp;
 168 };
 169
 170 extern int aarch64_num_bp_regs;
 171 extern int aarch64_num_wp_regs;
 172
 173 unsigned int aarch64_watchpoint_offset (unsigned int ctrl);
 174 unsigned int aarch64_watchpoint_length (unsigned int ctrl);
 175
 176 int aarch64_handle_breakpoint (enum target_hw_bp_type type, CORE_ADDR addr,
 177                                int len, int is_insert,
 178                                struct aarch64_debug_reg_state *state);
 179 int aarch64_handle_watchpoint (enum target_hw_bp_type type, CORE_ADDR addr,
 180                                int len, int is_insert,
 181                                struct aarch64_debug_reg_state *state);
 182
 183 void aarch64_linux_set_debug_regs (struct aarch64_debug_reg_state *state,
 184                                    int tid, int watchpoint);
 185
 186 /* Return TRUE if there are any hardware breakpoints.  If WATCHPOINT is TRUE,
 187    check hardware watchpoints instead.  */
 188 bool aarch64_linux_any_set_debug_regs_state (aarch64_debug_reg_state *state,
 189                                              bool watchpoint);
 190
 191 void aarch64_show_debug_reg_state (struct aarch64_debug_reg_state *state,
 192                                    const char *func, CORE_ADDR addr,
 193                                    int len, enum target_hw_bp_type type);
 194
 195 void aarch64_linux_get_debug_reg_capacity (int tid);
 196
 197 struct aarch64_debug_reg_state *aarch64_get_debug_reg_state (pid_t pid);
 198
 199 int aarch64_linux_region_ok_for_watchpoint (CORE_ADDR addr, int len);
 200
 201 #endif /* NAT_AARCH64_LINUX_HW_POINT_H */