1 /* Debug register code for x86 (i386 and x86-64).
3 Copyright (C) 2001-2014 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
26 #include "x86-dregs.h"
28 /* Support for hardware watchpoints and breakpoints using the x86
31 This provides several functions for inserting and removing
32 hardware-assisted breakpoints and watchpoints, testing if one or
33 more of the watchpoints triggered and at what address, checking
34 whether a given region can be watched, etc.
36 The functions below implement debug registers sharing by reference
37 counts, and allow to watch regions up to 16 bytes long. */
39 /* Accessor macros for low-level function vector. */
41 /* Can we update the inferior's debug registers? */
42 #define x86_dr_low_can_set_addr() (x86_dr_low.set_addr != NULL)
44 /* Update the inferior's debug register REGNUM from STATE. */
45 #define x86_dr_low_set_addr(new_state, i) \
46 (x86_dr_low.set_addr ((i), (new_state)->dr_mirror[(i)]))
48 /* Return the inferior's debug register REGNUM. */
49 #define x86_dr_low_get_addr(i) (x86_dr_low.get_addr ((i)))
51 /* Can we update the inferior's DR7 control register? */
52 #define x86_dr_low_can_set_control() (x86_dr_low.set_control != NULL)
54 /* Update the inferior's DR7 debug control register from STATE. */
55 #define x86_dr_low_set_control(new_state) \
56 (x86_dr_low.set_control ((new_state)->dr_control_mirror))
58 /* Return the value of the inferior's DR7 debug control register. */
59 #define x86_dr_low_get_control() (x86_dr_low.get_control ())
61 /* Return the value of the inferior's DR6 debug status register. */
62 #define x86_dr_low_get_status() (x86_dr_low.get_status ())
64 /* Return the debug register size, in bytes. */
65 #define x86_get_debug_register_length() \
66 (x86_dr_low.debug_register_length)
68 /* Support for 8-byte wide hw watchpoints. */
69 #define TARGET_HAS_DR_LEN_8 (x86_get_debug_register_length () == 8)
71 /* DR7 Debug Control register fields. */
73 /* How many bits to skip in DR7 to get to R/W and LEN fields. */
74 #define DR_CONTROL_SHIFT 16
75 /* How many bits in DR7 per R/W and LEN field for each watchpoint. */
76 #define DR_CONTROL_SIZE 4
78 /* Watchpoint/breakpoint read/write fields in DR7. */
79 #define DR_RW_EXECUTE (0x0) /* Break on instruction execution. */
80 #define DR_RW_WRITE (0x1) /* Break on data writes. */
81 #define DR_RW_READ (0x3) /* Break on data reads or writes. */
83 /* This is here for completeness. No platform supports this
84 functionality yet (as of March 2001). Note that the DE flag in the
85 CR4 register needs to be set to support this. */
87 #define DR_RW_IORW (0x2) /* Break on I/O reads or writes. */
90 /* Watchpoint/breakpoint length fields in DR7. The 2-bit left shift
91 is so we could OR this with the read/write field defined above. */
92 #define DR_LEN_1 (0x0 << 2) /* 1-byte region watch or breakpoint. */
93 #define DR_LEN_2 (0x1 << 2) /* 2-byte region watch. */
94 #define DR_LEN_4 (0x3 << 2) /* 4-byte region watch. */
95 #define DR_LEN_8 (0x2 << 2) /* 8-byte region watch (AMD64). */
97 /* Local and Global Enable flags in DR7.
99 When the Local Enable flag is set, the breakpoint/watchpoint is
100 enabled only for the current task; the processor automatically
101 clears this flag on every task switch. When the Global Enable flag
102 is set, the breakpoint/watchpoint is enabled for all tasks; the
103 processor never clears this flag.
105 Currently, all watchpoint are locally enabled. If you need to
106 enable them globally, read the comment which pertains to this in
107 x86_insert_aligned_watchpoint below. */
108 #define DR_LOCAL_ENABLE_SHIFT 0 /* Extra shift to the local enable bit. */
109 #define DR_GLOBAL_ENABLE_SHIFT 1 /* Extra shift to the global enable bit. */
110 #define DR_ENABLE_SIZE 2 /* Two enable bits per debug register. */
112 /* Local and global exact breakpoint enable flags (a.k.a. slowdown
113 flags). These are only required on i386, to allow detection of the
114 exact instruction which caused a watchpoint to break; i486 and
115 later processors do that automatically. We set these flags for
116 backwards compatibility. */
117 #define DR_LOCAL_SLOWDOWN (0x100)
118 #define DR_GLOBAL_SLOWDOWN (0x200)
120 /* Fields reserved by Intel. This includes the GD (General Detect
121 Enable) flag, which causes a debug exception to be generated when a
122 MOV instruction accesses one of the debug registers.
124 FIXME: My Intel manual says we should use 0xF800, not 0xFC00. */
125 #define DR_CONTROL_RESERVED (0xFC00)
127 /* Auxiliary helper macros. */
129 /* A value that masks all fields in DR7 that are reserved by Intel. */
130 #define X86_DR_CONTROL_MASK (~DR_CONTROL_RESERVED)
132 /* The I'th debug register is vacant if its Local and Global Enable
133 bits are reset in the Debug Control register. */
134 #define X86_DR_VACANT(state, i) \
135 (((state)->dr_control_mirror & (3 << (DR_ENABLE_SIZE * (i)))) == 0)
137 /* Locally enable the break/watchpoint in the I'th debug register. */
138 #define X86_DR_LOCAL_ENABLE(state, i) \
140 (state)->dr_control_mirror |= \
141 (1 << (DR_LOCAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \
144 /* Globally enable the break/watchpoint in the I'th debug register. */
145 #define X86_DR_GLOBAL_ENABLE(state, i) \
147 (state)->dr_control_mirror |= \
148 (1 << (DR_GLOBAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \
151 /* Disable the break/watchpoint in the I'th debug register. */
152 #define X86_DR_DISABLE(state, i) \
154 (state)->dr_control_mirror &= \
155 ~(3 << (DR_ENABLE_SIZE * (i))); \
158 /* Set in DR7 the RW and LEN fields for the I'th debug register. */
159 #define X86_DR_SET_RW_LEN(state, i, rwlen) \
161 (state)->dr_control_mirror &= \
162 ~(0x0f << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \
163 (state)->dr_control_mirror |= \
164 ((rwlen) << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \
167 /* Get from DR7 the RW and LEN fields for the I'th debug register. */
168 #define X86_DR_GET_RW_LEN(dr7, i) \
170 >> (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))) & 0x0f)
172 /* Did the watchpoint whose address is in the I'th register break? */
173 #define X86_DR_WATCH_HIT(dr6, i) ((dr6) & (1 << (i)))
175 /* Types of operations supported by x86_handle_nonaligned_watchpoint. */
176 typedef enum { WP_INSERT
, WP_REMOVE
, WP_COUNT
} x86_wp_op_t
;
179 /* Whether or not to print the mirrored debug registers. */
180 extern int debug_hw_points
;
183 /* Print the values of the mirrored debug registers. */
186 x86_show_dr (struct x86_debug_reg_state
*state
,
187 const char *func
, CORE_ADDR addr
,
188 int len
, enum target_hw_bp_type type
)
192 debug_printf ("%s", func
);
194 debug_printf (" (addr=%s, len=%d, type=%s)",
196 type
== hw_write
? "data-write"
197 : (type
== hw_read
? "data-read"
198 : (type
== hw_access
? "data-read/write"
199 : (type
== hw_execute
? "instruction-execute"
200 /* FIXME: if/when I/O read/write
201 watchpoints are supported, add them
204 debug_printf (":\n");
205 debug_printf ("\tCONTROL (DR7): %s STATUS (DR6): %s\n",
206 phex (state
->dr_control_mirror
, 8),
207 phex (state
->dr_status_mirror
, 8));
208 ALL_DEBUG_REGISTERS (i
)
211 \tDR%d: addr=0x%s, ref.count=%d DR%d: addr=0x%s, ref.count=%d\n",
212 i
, phex (state
->dr_mirror
[i
],
213 x86_get_debug_register_length ()),
214 state
->dr_ref_count
[i
],
215 i
+ 1, phex (state
->dr_mirror
[i
+ 1],
216 x86_get_debug_register_length ()),
217 state
->dr_ref_count
[i
+ 1]);
222 /* Return the value of a 4-bit field for DR7 suitable for watching a
223 region of LEN bytes for accesses of type TYPE. LEN is assumed to
224 have the value of 1, 2, or 4. */
227 x86_length_and_rw_bits (int len
, enum target_hw_bp_type type
)
240 internal_error (__FILE__
, __LINE__
,
241 _("The i386 doesn't support "
242 "data-read watchpoints.\n"));
247 /* Not yet supported. */
253 internal_error (__FILE__
, __LINE__
, _("\
254 Invalid hardware breakpoint type %d in x86_length_and_rw_bits.\n"),
261 return (DR_LEN_1
| rw
);
263 return (DR_LEN_2
| rw
);
265 return (DR_LEN_4
| rw
);
267 if (TARGET_HAS_DR_LEN_8
)
268 return (DR_LEN_8
| rw
);
269 /* ELSE FALL THROUGH */
271 internal_error (__FILE__
, __LINE__
, _("\
272 Invalid hardware breakpoint length %d in x86_length_and_rw_bits.\n"), len
);
276 /* Insert a watchpoint at address ADDR, which is assumed to be aligned
277 according to the length of the region to watch. LEN_RW_BITS is the
278 value of the bits from DR7 which describes the length and access
279 type of the region to be watched by this watchpoint. Return 0 on
280 success, -1 on failure. */
283 x86_insert_aligned_watchpoint (struct x86_debug_reg_state
*state
,
284 CORE_ADDR addr
, unsigned len_rw_bits
)
288 if (!x86_dr_low_can_set_addr () || !x86_dr_low_can_set_control ())
291 /* First, look for an occupied debug register with the same address
292 and the same RW and LEN definitions. If we find one, we can
293 reuse it for this watchpoint as well (and save a register). */
294 ALL_DEBUG_REGISTERS (i
)
296 if (!X86_DR_VACANT (state
, i
)
297 && state
->dr_mirror
[i
] == addr
298 && X86_DR_GET_RW_LEN (state
->dr_control_mirror
, i
) == len_rw_bits
)
300 state
->dr_ref_count
[i
]++;
305 /* Next, look for a vacant debug register. */
306 ALL_DEBUG_REGISTERS (i
)
308 if (X86_DR_VACANT (state
, i
))
312 /* No more debug registers! */
316 /* Now set up the register I to watch our region. */
318 /* Record the info in our local mirrored array. */
319 state
->dr_mirror
[i
] = addr
;
320 state
->dr_ref_count
[i
] = 1;
321 X86_DR_SET_RW_LEN (state
, i
, len_rw_bits
);
322 /* Note: we only enable the watchpoint locally, i.e. in the current
323 task. Currently, no x86 target allows or supports global
324 watchpoints; however, if any target would want that in the
325 future, GDB should probably provide a command to control whether
326 to enable watchpoints globally or locally, and the code below
327 should use global or local enable and slow-down flags as
329 X86_DR_LOCAL_ENABLE (state
, i
);
330 state
->dr_control_mirror
|= DR_LOCAL_SLOWDOWN
;
331 state
->dr_control_mirror
&= X86_DR_CONTROL_MASK
;
336 /* Remove a watchpoint at address ADDR, which is assumed to be aligned
337 according to the length of the region to watch. LEN_RW_BITS is the
338 value of the bits from DR7 which describes the length and access
339 type of the region watched by this watchpoint. Return 0 on
340 success, -1 on failure. */
343 x86_remove_aligned_watchpoint (struct x86_debug_reg_state
*state
,
344 CORE_ADDR addr
, unsigned len_rw_bits
)
349 ALL_DEBUG_REGISTERS (i
)
351 if (!X86_DR_VACANT (state
, i
)
352 && state
->dr_mirror
[i
] == addr
353 && X86_DR_GET_RW_LEN (state
->dr_control_mirror
, i
) == len_rw_bits
)
355 if (--state
->dr_ref_count
[i
] == 0) /* No longer in use? */
357 /* Reset our mirror. */
358 state
->dr_mirror
[i
] = 0;
359 X86_DR_DISABLE (state
, i
);
360 /* Even though not strictly necessary, clear out all
361 bits in DR_CONTROL related to this debug register.
362 Debug output is clearer when we don't have stale bits
363 in place. This also allows the assertion below. */
364 X86_DR_SET_RW_LEN (state
, i
, 0);
369 if (!X86_DR_VACANT (state
, i
))
375 /* Even though not strictly necessary, clear out all of
376 DR_CONTROL, so that when we have no debug registers in use,
377 we end up with DR_CONTROL == 0. The Linux support relies on
378 this for an optimization. Plus, it makes for clearer debug
380 state
->dr_control_mirror
&= ~DR_LOCAL_SLOWDOWN
;
382 gdb_assert (state
->dr_control_mirror
== 0);
387 /* Insert or remove a (possibly non-aligned) watchpoint, or count the
388 number of debug registers required to watch a region at address
389 ADDR whose length is LEN for accesses of type TYPE. Return 0 on
390 successful insertion or removal, a positive number when queried
391 about the number of registers, or -1 on failure. If WHAT is not a
392 valid value, bombs through internal_error. */
395 x86_handle_nonaligned_watchpoint (struct x86_debug_reg_state
*state
,
396 x86_wp_op_t what
, CORE_ADDR addr
, int len
,
397 enum target_hw_bp_type type
)
400 int max_wp_len
= TARGET_HAS_DR_LEN_8
? 8 : 4;
402 static const int size_try_array
[8][8] =
404 {1, 1, 1, 1, 1, 1, 1, 1}, /* Trying size one. */
405 {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size two. */
406 {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size three. */
407 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size four. */
408 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size five. */
409 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size six. */
410 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size seven. */
411 {8, 1, 2, 1, 4, 1, 2, 1}, /* Trying size eight. */
416 int align
= addr
% max_wp_len
;
417 /* Four (eight on AMD64) is the maximum length a debug register
419 int try = (len
> max_wp_len
? (max_wp_len
- 1) : len
- 1);
420 int size
= size_try_array
[try][align
];
422 if (what
== WP_COUNT
)
424 /* size_try_array[] is defined such that each iteration
425 through the loop is guaranteed to produce an address and a
426 size that can be watched with a single debug register.
427 Thus, for counting the registers required to watch a
428 region, we simply need to increment the count on each
434 unsigned len_rw
= x86_length_and_rw_bits (size
, type
);
436 if (what
== WP_INSERT
)
437 retval
= x86_insert_aligned_watchpoint (state
, addr
, len_rw
);
438 else if (what
== WP_REMOVE
)
439 retval
= x86_remove_aligned_watchpoint (state
, addr
, len_rw
);
441 internal_error (__FILE__
, __LINE__
, _("\
442 Invalid value %d of operation in x86_handle_nonaligned_watchpoint.\n"),
455 /* Update the inferior debug registers state, in STATE, with the
456 new debug registers state, in NEW_STATE. */
459 x86_update_inferior_debug_regs (struct x86_debug_reg_state
*state
,
460 struct x86_debug_reg_state
*new_state
)
464 ALL_DEBUG_REGISTERS (i
)
466 if (X86_DR_VACANT (new_state
, i
) != X86_DR_VACANT (state
, i
))
467 x86_dr_low_set_addr (new_state
, i
);
469 gdb_assert (new_state
->dr_mirror
[i
] == state
->dr_mirror
[i
]);
472 if (new_state
->dr_control_mirror
!= state
->dr_control_mirror
)
473 x86_dr_low_set_control (new_state
);
478 /* Insert a watchpoint to watch a memory region which starts at
479 address ADDR and whose length is LEN bytes. Watch memory accesses
480 of the type TYPE. Return 0 on success, -1 on failure. */
483 x86_dr_insert_watchpoint (struct x86_debug_reg_state
*state
,
484 enum target_hw_bp_type type
,
485 CORE_ADDR addr
, int len
)
488 /* Work on a local copy of the debug registers, and on success,
489 commit the change back to the inferior. */
490 struct x86_debug_reg_state local_state
= *state
;
493 return 1; /* unsupported */
495 if (((len
!= 1 && len
!= 2 && len
!= 4)
496 && !(TARGET_HAS_DR_LEN_8
&& len
== 8))
499 retval
= x86_handle_nonaligned_watchpoint (&local_state
,
505 unsigned len_rw
= x86_length_and_rw_bits (len
, type
);
507 retval
= x86_insert_aligned_watchpoint (&local_state
,
512 x86_update_inferior_debug_regs (state
, &local_state
);
515 x86_show_dr (state
, "insert_watchpoint", addr
, len
, type
);
520 /* Remove a watchpoint that watched the memory region which starts at
521 address ADDR, whose length is LEN bytes, and for accesses of the
522 type TYPE. Return 0 on success, -1 on failure. */
525 x86_dr_remove_watchpoint (struct x86_debug_reg_state
*state
,
526 enum target_hw_bp_type type
,
527 CORE_ADDR addr
, int len
)
530 /* Work on a local copy of the debug registers, and on success,
531 commit the change back to the inferior. */
532 struct x86_debug_reg_state local_state
= *state
;
534 if (((len
!= 1 && len
!= 2 && len
!= 4)
535 && !(TARGET_HAS_DR_LEN_8
&& len
== 8))
538 retval
= x86_handle_nonaligned_watchpoint (&local_state
,
544 unsigned len_rw
= x86_length_and_rw_bits (len
, type
);
546 retval
= x86_remove_aligned_watchpoint (&local_state
,
551 x86_update_inferior_debug_regs (state
, &local_state
);
554 x86_show_dr (state
, "remove_watchpoint", addr
, len
, type
);
559 /* Return non-zero if we can watch a memory region that starts at
560 address ADDR and whose length is LEN bytes. */
563 x86_dr_region_ok_for_watchpoint (struct x86_debug_reg_state
*state
,
564 CORE_ADDR addr
, int len
)
568 /* Compute how many aligned watchpoints we would need to cover this
570 nregs
= x86_handle_nonaligned_watchpoint (state
, WP_COUNT
,
571 addr
, len
, hw_write
);
572 return nregs
<= DR_NADDR
? 1 : 0;
575 /* If the inferior has some break/watchpoint that triggered, set the
576 address associated with that break/watchpoint and return non-zero.
577 Otherwise, return zero. */
580 x86_dr_stopped_data_address (struct x86_debug_reg_state
*state
,
586 /* The current thread's DR_STATUS. We always need to read this to
587 check whether some watchpoint caused the trap. */
589 /* We need DR_CONTROL as well, but only iff DR_STATUS indicates a
590 data breakpoint trap. Only fetch it when necessary, to avoid an
591 unnecessary extra syscall when no watchpoint triggered. */
593 unsigned control
= 0;
595 /* In non-stop/async, threads can be running while we change the
596 global dr_mirror (and friends). Say, we set a watchpoint, and
597 let threads resume. Now, say you delete the watchpoint, or
598 add/remove watchpoints such that dr_mirror changes while threads
599 are running. On targets that support non-stop,
600 inserting/deleting watchpoints updates the global dr_mirror only.
601 It does not update the real thread's debug registers; that's only
602 done prior to resume. Instead, if threads are running when the
603 mirror changes, a temporary and transparent stop on all threads
604 is forced so they can get their copy of the debug registers
605 updated on re-resume. Now, say, a thread hit a watchpoint before
606 having been updated with the new dr_mirror contents, and we
607 haven't yet handled the corresponding SIGTRAP. If we trusted
608 dr_mirror below, we'd mistake the real trapped address (from the
609 last time we had updated debug registers in the thread) with
610 whatever was currently in dr_mirror. So to fix this, dr_mirror
611 always represents intention, what we _want_ threads to have in
612 debug registers. To get at the address and cause of the trap, we
613 need to read the state the thread still has in its debug
616 In sum, always get the current debug register values the current
617 thread has, instead of trusting the global mirror. If the thread
618 was running when we last changed watchpoints, the mirror no
619 longer represents what was set in this thread's debug
621 status
= x86_dr_low_get_status ();
623 ALL_DEBUG_REGISTERS (i
)
625 if (!X86_DR_WATCH_HIT (status
, i
))
630 control
= x86_dr_low_get_control ();
634 /* This second condition makes sure DRi is set up for a data
635 watchpoint, not a hardware breakpoint. The reason is that
636 GDB doesn't call the target_stopped_data_address method
637 except for data watchpoints. In other words, I'm being
639 if (X86_DR_GET_RW_LEN (control
, i
) != 0)
641 addr
= x86_dr_low_get_addr (i
);
644 x86_show_dr (state
, "watchpoint_hit", addr
, -1, hw_write
);
648 if (debug_hw_points
&& addr
== 0)
649 x86_show_dr (state
, "stopped_data_addr", 0, 0, hw_write
);
656 /* Return non-zero if the inferior has some watchpoint that triggered.
657 Otherwise return zero. */
660 x86_dr_stopped_by_watchpoint (struct x86_debug_reg_state
*state
)
663 return x86_dr_stopped_data_address (state
, &addr
);