gdb/nds32-tdep.c

   1 /* Target-dependent code for the NDS32 architecture, for GDB.
   2
   3    Copyright (C) 2013-2022 Free Software Foundation, Inc.
   4    Contributed by Andes Technology Corporation.
   5
   6    This file is part of GDB.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  20
  21 #include "defs.h"
  22 #include "frame.h"
  23 #include "frame-unwind.h"
  24 #include "frame-base.h"
  25 #include "symtab.h"
  26 #include "gdbtypes.h"
  27 #include "gdbcore.h"
  28 #include "value.h"
  29 #include "reggroups.h"
  30 #include "inferior.h"
  31 #include "osabi.h"
  32 #include "arch-utils.h"
  33 #include "regcache.h"
  34 #include "dis-asm.h"
  35 #include "user-regs.h"
  36 #include "elf-bfd.h"
  37 #include "dwarf2/frame.h"
  38 #include "remote.h"
  39 #include "target-descriptions.h"
  40
  41 #include "nds32-tdep.h"
  42 #include "elf/nds32.h"
  43 #include "opcode/nds32.h"
  44 #include <algorithm>
  45
  46 #include "features/nds32.c"
  47
  48 /* Simple macros for instruction analysis.  */
  49 #define CHOP_BITS(insn, n)      (insn & ~__MASK (n))
  50 #define N32_LSMW_ENABLE4(insn)  (((insn) >> 6) & 0xf)
  51 #define N32_SMW_ADM \
  52         N32_TYPE4 (LSMW, 0, 0, 0, 1, (N32_LSMW_ADM << 2) | N32_LSMW_LSMW)
  53 #define N32_LMW_BIM \
  54         N32_TYPE4 (LSMW, 0, 0, 0, 0, (N32_LSMW_BIM << 2) | N32_LSMW_LSMW)
  55 #define N32_FLDI_SP \
  56         N32_TYPE2 (LDC, 0, REG_SP, 0)
  57
  58 /* Use an invalid address value as 'not available' marker.  */
  59 enum { REG_UNAVAIL = (CORE_ADDR) -1 };
  60
  61 /* Use an impossible value as invalid offset.  */
  62 enum { INVALID_OFFSET = (CORE_ADDR) -1 };
  63
  64 /* Instruction groups for NDS32 epilogue analysis.  */
  65 enum
  66 {
  67   /* Instructions used everywhere, not only in epilogue.  */
  68   INSN_NORMAL,
  69   /* Instructions used to reset sp for local vars, arguments, etc.  */
  70   INSN_RESET_SP,
  71   /* Instructions used to recover saved regs and to recover padding.  */
  72   INSN_RECOVER,
  73   /* Instructions used to return to the caller.  */
  74   INSN_RETURN,
  75   /* Instructions used to recover saved regs and to return to the caller.  */
  76   INSN_RECOVER_RETURN,
  77 };
  78
  79 static const char *const nds32_register_names[] =
  80 {
  81   /* 32 GPRs.  */
  82   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
  83   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
  84   "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
  85   "r24", "r25", "r26", "r27", "fp", "gp", "lp", "sp",
  86   /* PC.  */
  87   "pc",
  88 };
  89
  90 static const char *const nds32_fdr_register_names[] =
  91 {
  92   "fd0", "fd1", "fd2", "fd3", "fd4", "fd5", "fd6", "fd7",
  93   "fd8", "fd9", "fd10", "fd11", "fd12", "fd13", "fd14", "fd15",
  94   "fd16", "fd17", "fd18", "fd19", "fd20", "fd21", "fd22", "fd23",
  95   "fd24", "fd25", "fd26", "fd27", "fd28", "fd29", "fd30", "fd31"
  96 };
  97
  98 static const char *const nds32_fsr_register_names[] =
  99 {
 100   "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",
 101   "fs8", "fs9", "fs10", "fs11", "fs12", "fs13", "fs14", "fs15",
 102   "fs16", "fs17", "fs18", "fs19", "fs20", "fs21", "fs22", "fs23",
 103   "fs24", "fs25", "fs26", "fs27", "fs28", "fs29", "fs30", "fs31"
 104 };
 105
 106 /* The number of registers for four FPU configuration options.  */
 107 const int num_fdr_map[] = { 4, 8, 16, 32 };
 108 const int num_fsr_map[] = { 8, 16, 32, 32 };
 109
 110 /* Aliases for registers.  */
 111 static const struct
 112 {
 113   const char *name;
 114   const char *alias;
 115 } nds32_register_aliases[] =
 116 {
 117   {"r15", "ta"},
 118   {"r26", "p0"},
 119   {"r27", "p1"},
 120   {"fp", "r28"},
 121   {"gp", "r29"},
 122   {"lp", "r30"},
 123   {"sp", "r31"},
 124
 125   {"cr0", "cpu_ver"},
 126   {"cr1", "icm_cfg"},
 127   {"cr2", "dcm_cfg"},
 128   {"cr3", "mmu_cfg"},
 129   {"cr4", "msc_cfg"},
 130   {"cr5", "core_id"},
 131   {"cr6", "fucop_exist"},
 132   {"cr7", "msc_cfg2"},
 133
 134   {"ir0", "psw"},
 135   {"ir1", "ipsw"},
 136   {"ir2", "p_psw"},
 137   {"ir3", "ivb"},
 138   {"ir4", "eva"},
 139   {"ir5", "p_eva"},
 140   {"ir6", "itype"},
 141   {"ir7", "p_itype"},
 142   {"ir8", "merr"},
 143   {"ir9", "ipc"},
 144   {"ir10", "p_ipc"},
 145   {"ir11", "oipc"},
 146   {"ir12", "p_p0"},
 147   {"ir13", "p_p1"},
 148   {"ir14", "int_mask"},
 149   {"ir15", "int_pend"},
 150   {"ir16", "sp_usr"},
 151   {"ir17", "sp_priv"},
 152   {"ir18", "int_pri"},
 153   {"ir19", "int_ctrl"},
 154   {"ir20", "sp_usr1"},
 155   {"ir21", "sp_priv1"},
 156   {"ir22", "sp_usr2"},
 157   {"ir23", "sp_priv2"},
 158   {"ir24", "sp_usr3"},
 159   {"ir25", "sp_priv3"},
 160   {"ir26", "int_mask2"},
 161   {"ir27", "int_pend2"},
 162   {"ir28", "int_pri2"},
 163   {"ir29", "int_trigger"},
 164
 165   {"mr0", "mmu_ctl"},
 166   {"mr1", "l1_pptb"},
 167   {"mr2", "tlb_vpn"},
 168   {"mr3", "tlb_data"},
 169   {"mr4", "tlb_misc"},
 170   {"mr5", "vlpt_idx"},
 171   {"mr6", "ilmb"},
 172   {"mr7", "dlmb"},
 173   {"mr8", "cache_ctl"},
 174   {"mr9", "hsmp_saddr"},
 175   {"mr10", "hsmp_eaddr"},
 176   {"mr11", "bg_region"},
 177
 178   {"dr0", "bpc0"},
 179   {"dr1", "bpc1"},
 180   {"dr2", "bpc2"},
 181   {"dr3", "bpc3"},
 182   {"dr4", "bpc4"},
 183   {"dr5", "bpc5"},
 184   {"dr6", "bpc6"},
 185   {"dr7", "bpc7"},
 186   {"dr8", "bpa0"},
 187   {"dr9", "bpa1"},
 188   {"dr10", "bpa2"},
 189   {"dr11", "bpa3"},
 190   {"dr12", "bpa4"},
 191   {"dr13", "bpa5"},
 192   {"dr14", "bpa6"},
 193   {"dr15", "bpa7"},
 194   {"dr16", "bpam0"},
 195   {"dr17", "bpam1"},
 196   {"dr18", "bpam2"},
 197   {"dr19", "bpam3"},
 198   {"dr20", "bpam4"},
 199   {"dr21", "bpam5"},
 200   {"dr22", "bpam6"},
 201   {"dr23", "bpam7"},
 202   {"dr24", "bpv0"},
 203   {"dr25", "bpv1"},
 204   {"dr26", "bpv2"},
 205   {"dr27", "bpv3"},
 206   {"dr28", "bpv4"},
 207   {"dr29", "bpv5"},
 208   {"dr30", "bpv6"},
 209   {"dr31", "bpv7"},
 210   {"dr32", "bpcid0"},
 211   {"dr33", "bpcid1"},
 212   {"dr34", "bpcid2"},
 213   {"dr35", "bpcid3"},
 214   {"dr36", "bpcid4"},
 215   {"dr37", "bpcid5"},
 216   {"dr38", "bpcid6"},
 217   {"dr39", "bpcid7"},
 218   {"dr40", "edm_cfg"},
 219   {"dr41", "edmsw"},
 220   {"dr42", "edm_ctl"},
 221   {"dr43", "edm_dtr"},
 222   {"dr44", "bpmtc"},
 223   {"dr45", "dimbr"},
 224   {"dr46", "tecr0"},
 225   {"dr47", "tecr1"},
 226
 227   {"hspr0", "hsp_ctl"},
 228   {"hspr1", "sp_bound"},
 229   {"hspr2", "sp_bound_priv"},
 230
 231   {"pfr0", "pfmc0"},
 232   {"pfr1", "pfmc1"},
 233   {"pfr2", "pfmc2"},
 234   {"pfr3", "pfm_ctl"},
 235   {"pfr4", "pft_ctl"},
 236
 237   {"dmar0", "dma_cfg"},
 238   {"dmar1", "dma_gcsw"},
 239   {"dmar2", "dma_chnsel"},
 240   {"dmar3", "dma_act"},
 241   {"dmar4", "dma_setup"},
 242   {"dmar5", "dma_isaddr"},
 243   {"dmar6", "dma_esaddr"},
 244   {"dmar7", "dma_tcnt"},
 245   {"dmar8", "dma_status"},
 246   {"dmar9", "dma_2dset"},
 247   {"dmar10", "dma_2dsctl"},
 248   {"dmar11", "dma_rcnt"},
 249   {"dmar12", "dma_hstatus"},
 250
 251   {"racr0", "prusr_acc_ctl"},
 252   {"fucpr", "fucop_ctl"},
 253
 254   {"idr0", "sdz_ctl"},
 255   {"idr1", "misc_ctl"},
 256   {"idr2", "ecc_misc"},
 257
 258   {"secur0", "sfcr"},
 259   {"secur1", "sign"},
 260   {"secur2", "isign"},
 261   {"secur3", "p_isign"},
 262 };
 263
 264 /* Value of a register alias.  BATON is the regnum of the corresponding
 265    register.  */
 266
 267 static struct value *
 268 value_of_nds32_reg (frame_info_ptr frame, const void *baton)
 269 {
 270   return value_of_register ((int) (intptr_t) baton, frame);
 271 }
 272 \f
 273 /* Implement the "frame_align" gdbarch method.  */
 274
 275 static CORE_ADDR
 276 nds32_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
 277 {
 278   /* 8-byte aligned.  */
 279   return align_down (sp, 8);
 280 }
 281
 282 /* The same insn machine code is used for little-endian and big-endian.  */
 283 constexpr gdb_byte nds32_break_insn[] = { 0xEA, 0x00 };
 284
 285 typedef BP_MANIPULATION (nds32_break_insn) nds32_breakpoint;
 286
 287 /* Implement the "dwarf2_reg_to_regnum" gdbarch method.  */
 288
 289 static int
 290 nds32_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int num)
 291 {
 292   nds32_gdbarch_tdep *tdep = gdbarch_tdep<nds32_gdbarch_tdep> (gdbarch);
 293   const int FSR = 38;
 294   const int FDR = FSR + 32;
 295
 296   if (num >= 0 && num < 32)
 297     {
 298       /* General-purpose registers (R0 - R31).  */
 299       return num;
 300     }
 301   else if (num >= FSR && num < FSR + 32)
 302     {
 303       /* Single precision floating-point registers (FS0 - FS31).  */
 304       return num - FSR + tdep->fs0_regnum;
 305     }
 306   else if (num >= FDR && num < FDR + 32)
 307     {
 308       /* Double precision floating-point registers (FD0 - FD31).  */
 309       return num - FDR + NDS32_FD0_REGNUM;
 310     }
 311
 312   /* No match, return a inaccessible register number.  */
 313   return -1;
 314 }
 315 \f
 316 /* NDS32 register groups.  */
 317 static const reggroup *nds32_cr_reggroup;
 318 static const reggroup *nds32_ir_reggroup;
 319 static const reggroup *nds32_mr_reggroup;
 320 static const reggroup *nds32_dr_reggroup;
 321 static const reggroup *nds32_pfr_reggroup;
 322 static const reggroup *nds32_hspr_reggroup;
 323 static const reggroup *nds32_dmar_reggroup;
 324 static const reggroup *nds32_racr_reggroup;
 325 static const reggroup *nds32_idr_reggroup;
 326 static const reggroup *nds32_secur_reggroup;
 327
 328 static void
 329 nds32_init_reggroups (void)
 330 {
 331   nds32_cr_reggroup = reggroup_new ("cr", USER_REGGROUP);
 332   nds32_ir_reggroup = reggroup_new ("ir", USER_REGGROUP);
 333   nds32_mr_reggroup = reggroup_new ("mr", USER_REGGROUP);
 334   nds32_dr_reggroup = reggroup_new ("dr", USER_REGGROUP);
 335   nds32_pfr_reggroup = reggroup_new ("pfr", USER_REGGROUP);
 336   nds32_hspr_reggroup = reggroup_new ("hspr", USER_REGGROUP);
 337   nds32_dmar_reggroup = reggroup_new ("dmar", USER_REGGROUP);
 338   nds32_racr_reggroup = reggroup_new ("racr", USER_REGGROUP);
 339   nds32_idr_reggroup = reggroup_new ("idr", USER_REGGROUP);
 340   nds32_secur_reggroup = reggroup_new ("secur", USER_REGGROUP);
 341 }
 342
 343 static void
 344 nds32_add_reggroups (struct gdbarch *gdbarch)
 345 {
 346   /* Add NDS32 register groups.  */
 347   reggroup_add (gdbarch, nds32_cr_reggroup);
 348   reggroup_add (gdbarch, nds32_ir_reggroup);
 349   reggroup_add (gdbarch, nds32_mr_reggroup);
 350   reggroup_add (gdbarch, nds32_dr_reggroup);
 351   reggroup_add (gdbarch, nds32_pfr_reggroup);
 352   reggroup_add (gdbarch, nds32_hspr_reggroup);
 353   reggroup_add (gdbarch, nds32_dmar_reggroup);
 354   reggroup_add (gdbarch, nds32_racr_reggroup);
 355   reggroup_add (gdbarch, nds32_idr_reggroup);
 356   reggroup_add (gdbarch, nds32_secur_reggroup);
 357 }
 358
 359 /* Implement the "register_reggroup_p" gdbarch method.  */
 360
 361 static int
 362 nds32_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
 363                            const struct reggroup *reggroup)
 364 {
 365   const char *reg_name;
 366   const char *group_name;
 367   int ret;
 368
 369   if (reggroup == all_reggroup)
 370     return 1;
 371
 372   /* General reggroup contains only GPRs and PC.  */
 373   if (reggroup == general_reggroup)
 374     return regnum <= NDS32_PC_REGNUM;
 375
 376   if (reggroup == float_reggroup || reggroup == save_reggroup
 377       || reggroup == restore_reggroup)
 378     {
 379       ret = tdesc_register_in_reggroup_p (gdbarch, regnum, reggroup);
 380       if (ret != -1)
 381         return ret;
 382
 383       return default_register_reggroup_p (gdbarch, regnum, reggroup);
 384     }
 385
 386   if (reggroup == system_reggroup)
 387     return (regnum > NDS32_PC_REGNUM)
 388             && !nds32_register_reggroup_p (gdbarch, regnum, float_reggroup);
 389
 390   /* The NDS32 reggroup contains registers whose name is prefixed
 391      by reggroup name.  */
 392   reg_name = gdbarch_register_name (gdbarch, regnum);
 393   group_name = reggroup->name ();
 394   return !strncmp (reg_name, group_name, strlen (group_name));
 395 }
 396 \f
 397 /* Implement the "pseudo_register_type" tdesc_arch_data method.  */
 398
 399 static struct type *
 400 nds32_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
 401 {
 402   regnum -= gdbarch_num_regs (gdbarch);
 403
 404   /* Currently, only FSRs could be defined as pseudo registers.  */
 405   if (regnum < gdbarch_num_pseudo_regs (gdbarch))
 406     return arch_float_type (gdbarch, -1, "builtin_type_ieee_single",
 407                             floatformats_ieee_single);
 408
 409   warning (_("Unknown nds32 pseudo register %d."), regnum);
 410   return NULL;
 411 }
 412
 413 /* Implement the "pseudo_register_name" tdesc_arch_data method.  */
 414
 415 static const char *
 416 nds32_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
 417 {
 418   regnum -= gdbarch_num_regs (gdbarch);
 419
 420   /* Currently, only FSRs could be defined as pseudo registers.  */
 421   gdb_assert (regnum < gdbarch_num_pseudo_regs (gdbarch));
 422   return nds32_fsr_register_names[regnum];
 423 }
 424
 425 /* Implement the "pseudo_register_read" gdbarch method.  */
 426
 427 static enum register_status
 428 nds32_pseudo_register_read (struct gdbarch *gdbarch,
 429                             readable_regcache *regcache, int regnum,
 430                             gdb_byte *buf)
 431 {
 432   nds32_gdbarch_tdep *tdep = gdbarch_tdep<nds32_gdbarch_tdep> (gdbarch);
 433   gdb_byte reg_buf[8];
 434   int offset, fdr_regnum;
 435   enum register_status status;
 436
 437   /* This function is registered in nds32_gdbarch_init only after these are
 438      set.  */
 439   gdb_assert (tdep->fpu_freg != -1);
 440   gdb_assert (tdep->use_pseudo_fsrs != 0);
 441
 442   regnum -= gdbarch_num_regs (gdbarch);
 443
 444   /* Currently, only FSRs could be defined as pseudo registers.  */
 445   if (regnum < gdbarch_num_pseudo_regs (gdbarch))
 446     {
 447       /* fs0 is always the most significant half of fd0.  */
 448       if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
 449         offset = (regnum & 1) ? 4 : 0;
 450       else
 451         offset = (regnum & 1) ? 0 : 4;
 452
 453       fdr_regnum = NDS32_FD0_REGNUM + (regnum >> 1);
 454       status = regcache->raw_read (fdr_regnum, reg_buf);
 455       if (status == REG_VALID)
 456         memcpy (buf, reg_buf + offset, 4);
 457
 458       return status;
 459     }
 460
 461   gdb_assert_not_reached ("invalid pseudo register number");
 462 }
 463
 464 /* Implement the "pseudo_register_write" gdbarch method.  */
 465
 466 static void
 467 nds32_pseudo_register_write (struct gdbarch *gdbarch,
 468                              struct regcache *regcache, int regnum,
 469                              const gdb_byte *buf)
 470 {
 471   nds32_gdbarch_tdep *tdep = gdbarch_tdep<nds32_gdbarch_tdep> (gdbarch);
 472   gdb_byte reg_buf[8];
 473   int offset, fdr_regnum;
 474
 475   /* This function is registered in nds32_gdbarch_init only after these are
 476      set.  */
 477   gdb_assert (tdep->fpu_freg != -1);
 478   gdb_assert (tdep->use_pseudo_fsrs != 0);
 479
 480   regnum -= gdbarch_num_regs (gdbarch);
 481
 482   /* Currently, only FSRs could be defined as pseudo registers.  */
 483   if (regnum < gdbarch_num_pseudo_regs (gdbarch))
 484     {
 485       /* fs0 is always the most significant half of fd0.  */
 486       if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
 487         offset = (regnum & 1) ? 4 : 0;
 488       else
 489         offset = (regnum & 1) ? 0 : 4;
 490
 491       fdr_regnum = NDS32_FD0_REGNUM + (regnum >> 1);
 492       regcache->raw_read (fdr_regnum, reg_buf);
 493       memcpy (reg_buf + offset, buf, 4);
 494       regcache->raw_write (fdr_regnum, reg_buf);
 495       return;
 496     }
 497
 498   gdb_assert_not_reached ("invalid pseudo register number");
 499 }
 500 \f
 501 /* Helper function for NDS32 ABI.  Return true if FPRs can be used
 502    to pass function arguments and return value.  */
 503
 504 static int
 505 nds32_abi_use_fpr (int elf_abi)
 506 {
 507   return elf_abi == E_NDS_ABI_V2FP_PLUS;
 508 }
 509
 510 /* Helper function for NDS32 ABI.  Return true if GPRs and stack
 511    can be used together to pass an argument.  */
 512
 513 static int
 514 nds32_abi_split (int elf_abi)
 515 {
 516   return elf_abi == E_NDS_ABI_AABI;
 517 }
 518
 519 #define NDS32_NUM_SAVED_REGS (NDS32_LP_REGNUM + 1)
 520
 521 struct nds32_frame_cache
 522 {
 523   /* The previous frame's inner most stack address.  Used as this
 524      frame ID's stack_addr.  */
 525   CORE_ADDR prev_sp;
 526
 527   /* The frame's base, optionally used by the high-level debug info.  */
 528   CORE_ADDR base;
 529
 530   /* During prologue analysis, keep how far the SP and FP have been offset
 531      from the start of the stack frame (as defined by the previous frame's
 532      stack pointer).
 533      During epilogue analysis, keep how far the SP has been offset from the
 534      current stack pointer.  */
 535   CORE_ADDR sp_offset;
 536   CORE_ADDR fp_offset;
 537
 538   /* The address of the first instruction in this function.  */
 539   CORE_ADDR pc;
 540
 541   /* Saved registers.  */
 542   CORE_ADDR saved_regs[NDS32_NUM_SAVED_REGS];
 543 };
 544
 545 /* Allocate and initialize a frame cache.  */
 546
 547 static struct nds32_frame_cache *
 548 nds32_alloc_frame_cache (void)
 549 {
 550   struct nds32_frame_cache *cache;
 551   int i;
 552
 553   cache = FRAME_OBSTACK_ZALLOC (struct nds32_frame_cache);
 554
 555   /* Initialize fp_offset to check if FP is set in prologue.  */
 556   cache->fp_offset = INVALID_OFFSET;
 557
 558   /* Saved registers.  We initialize these to -1 since zero is a valid
 559      offset.  */
 560   for (i = 0; i < NDS32_NUM_SAVED_REGS; i++)
 561     cache->saved_regs[i] = REG_UNAVAIL;
 562
 563   return cache;
 564 }
 565
 566 /* Helper function for instructions used to push multiple words.  */
 567
 568 static void
 569 nds32_push_multiple_words (struct nds32_frame_cache *cache, int rb, int re,
 570                            int enable4)
 571 {
 572   CORE_ADDR sp_offset = cache->sp_offset;
 573   int i;
 574
 575   /* Check LP, GP, FP in enable4.  */
 576   for (i = 1; i <= 3; i++)
 577     {
 578       if ((enable4 >> i) & 0x1)
 579         {
 580           sp_offset += 4;
 581           cache->saved_regs[NDS32_SP_REGNUM - i] = sp_offset;
 582         }
 583     }
 584
 585   /* Skip case where re == rb == sp.  */
 586   if ((rb < REG_FP) && (re < REG_FP))
 587     {
 588       for (i = re; i >= rb; i--)
 589         {
 590           sp_offset += 4;
 591           cache->saved_regs[i] = sp_offset;
 592         }
 593     }
 594
 595   /* For sp, update the offset.  */
 596   cache->sp_offset = sp_offset;
 597 }
 598
 599 /* Analyze the instructions within the given address range.  If CACHE
 600    is non-NULL, fill it in.  Return the first address beyond the given
 601    address range.  If CACHE is NULL, return the first address not
 602    recognized as a prologue instruction.  */
 603
 604 static CORE_ADDR
 605 nds32_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,
 606                         CORE_ADDR limit_pc, struct nds32_frame_cache *cache)
 607 {
 608   nds32_gdbarch_tdep *tdep = gdbarch_tdep<nds32_gdbarch_tdep> (gdbarch);
 609   int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
 610   /* Current scanning status.  */
 611   int in_prologue_bb = 0;
 612   int val_ta = 0;
 613   uint32_t insn, insn_len;
 614
 615   for (; pc < limit_pc; pc += insn_len)
 616     {
 617       insn = read_memory_unsigned_integer (pc, 4, BFD_ENDIAN_BIG);
 618
 619       if ((insn & 0x80000000) == 0)
 620         {
 621           /* 32-bit instruction */
 622           insn_len = 4;
 623
 624           if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_SP, REG_SP, 0))
 625             {
 626               /* addi $sp, $sp, imm15s */
 627               int imm15s = N32_IMM15S (insn);
 628
 629               if (imm15s < 0)
 630                 {
 631                   if (cache != NULL)
 632                     cache->sp_offset += -imm15s;
 633
 634                   in_prologue_bb = 1;
 635                   continue;
 636                 }
 637             }
 638           else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_FP, REG_SP, 0))
 639             {
 640               /* addi $fp, $sp, imm15s */
 641               int imm15s = N32_IMM15S (insn);
 642
 643               if (imm15s > 0)
 644                 {
 645                   if (cache != NULL)
 646                     cache->fp_offset = cache->sp_offset - imm15s;
 647
 648                   in_prologue_bb = 1;
 649                   continue;
 650                 }
 651             }
 652           else if ((insn & ~(__MASK (19) << 6)) == N32_SMW_ADM
 653                    && N32_RA5 (insn) == REG_SP)
 654             {
 655               /* smw.adm Rb, [$sp], Re, enable4 */
 656               if (cache != NULL)
 657                 nds32_push_multiple_words (cache, N32_RT5 (insn),
 658                                            N32_RB5 (insn),
 659                                            N32_LSMW_ENABLE4 (insn));
 660               in_prologue_bb = 1;
 661               continue;
 662             }
 663           else if (insn == N32_ALU1 (ADD, REG_SP, REG_SP, REG_TA)
 664                    || insn == N32_ALU1 (ADD, REG_SP, REG_TA, REG_SP))
 665             {
 666               /* add $sp, $sp, $ta */
 667               /* add $sp, $ta, $sp */
 668               if (val_ta < 0)
 669                 {
 670                   if (cache != NULL)
 671                     cache->sp_offset += -val_ta;
 672
 673                   in_prologue_bb = 1;
 674                   continue;
 675                 }
 676             }
 677           else if (CHOP_BITS (insn, 20) == N32_TYPE1 (MOVI, REG_TA, 0))
 678             {
 679               /* movi $ta, imm20s */
 680               if (cache != NULL)
 681                 val_ta = N32_IMM20S (insn);
 682
 683               continue;
 684             }
 685           else if (CHOP_BITS (insn, 20) == N32_TYPE1 (SETHI, REG_TA, 0))
 686             {
 687               /* sethi $ta, imm20u */
 688               if (cache != NULL)
 689                 val_ta = N32_IMM20U (insn) << 12;
 690
 691               continue;
 692             }
 693           else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ORI, REG_TA, REG_TA, 0))
 694             {
 695               /* ori $ta, $ta, imm15u */
 696               if (cache != NULL)
 697                 val_ta |= N32_IMM15U (insn);
 698
 699               continue;
 700             }
 701           else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_TA, REG_TA, 0))
 702             {
 703               /* addi $ta, $ta, imm15s */
 704               if (cache != NULL)
 705                 val_ta += N32_IMM15S (insn);
 706
 707               continue;
 708             }
 709           if (insn == N32_ALU1 (ADD, REG_GP, REG_TA, REG_GP)
 710               || insn == N32_ALU1 (ADD, REG_GP, REG_GP, REG_TA))
 711             {
 712               /* add $gp, $ta, $gp */
 713               /* add $gp, $gp, $ta */
 714               in_prologue_bb = 1;
 715               continue;
 716             }
 717           else if (CHOP_BITS (insn, 20) == N32_TYPE1 (MOVI, REG_GP, 0))
 718             {
 719               /* movi $gp, imm20s */
 720               in_prologue_bb = 1;
 721               continue;
 722             }
 723           else if (CHOP_BITS (insn, 20) == N32_TYPE1 (SETHI, REG_GP, 0))
 724             {
 725               /* sethi $gp, imm20u */
 726               in_prologue_bb = 1;
 727               continue;
 728             }
 729           else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ORI, REG_GP, REG_GP, 0))
 730             {
 731               /* ori $gp, $gp, imm15u */
 732               in_prologue_bb = 1;
 733               continue;
 734             }
 735           else
 736             {
 737               /* Jump/Branch insns never appear in prologue basic block.
 738                  The loop can be escaped early when these insns are met.  */
 739               if (in_prologue_bb == 1)
 740                 {
 741                   int op = N32_OP6 (insn);
 742
 743                   if (op == N32_OP6_JI
 744                       || op == N32_OP6_JREG
 745                       || op == N32_OP6_BR1
 746                       || op == N32_OP6_BR2
 747                       || op == N32_OP6_BR3)
 748                     break;
 749                 }
 750             }
 751
 752           if (abi_use_fpr && N32_OP6 (insn) == N32_OP6_SDC
 753               && __GF (insn, 12, 3) == 0)
 754             {
 755               /* For FPU insns, CP (bit [13:14]) should be CP0,  and only
 756                  normal form (bit [12] == 0) is used.  */
 757
 758               /* fsdi FDt, [$sp + (imm12s << 2)] */
 759               if (N32_RA5 (insn) == REG_SP)
 760                 continue;
 761             }
 762
 763           /* The optimizer might shove anything into the prologue, if
 764              we build up cache (cache != NULL) from analyzing prologue,
 765              we just skip what we don't recognize and analyze further to
 766              make cache as complete as possible.  However, if we skip
 767              prologue, we'll stop immediately on unrecognized
 768              instruction.  */
 769           if (cache == NULL)
 770             break;
 771         }
 772       else
 773         {
 774           /* 16-bit instruction */
 775           insn_len = 2;
 776
 777           insn >>= 16;
 778
 779           if (CHOP_BITS (insn, 10) == N16_TYPE10 (ADDI10S, 0))
 780             {
 781               /* addi10s.sp */
 782               int imm10s = N16_IMM10S (insn);
 783
 784               if (imm10s < 0)
 785                 {
 786                   if (cache != NULL)
 787                     cache->sp_offset += -imm10s;
 788
 789                   in_prologue_bb = 1;
 790                   continue;
 791                 }
 792             }
 793           else if (__GF (insn, 7, 8) == N16_T25_PUSH25)
 794             {
 795               /* push25 */
 796               if (cache != NULL)
 797                 {
 798                   int imm8u = (insn & 0x1f) << 3;
 799                   int re = (insn >> 5) & 0x3;
 800                   const int reg_map[] = { 6, 8, 10, 14 };
 801
 802                   /* Operation 1 -- smw.adm R6, [$sp], Re, #0xe */
 803                   nds32_push_multiple_words (cache, 6, reg_map[re], 0xe);
 804
 805                   /* Operation 2 -- sp = sp - (imm5u << 3) */
 806                   cache->sp_offset += imm8u;
 807                 }
 808
 809               in_prologue_bb = 1;
 810               continue;
 811             }
 812           else if (insn == N16_TYPE5 (ADD5PC, REG_GP))
 813             {
 814               /* add5.pc $gp */
 815               in_prologue_bb = 1;
 816               continue;
 817             }
 818           else if (CHOP_BITS (insn, 5) == N16_TYPE55 (MOVI55, REG_GP, 0))
 819             {
 820               /* movi55 $gp, imm5s */
 821               in_prologue_bb = 1;
 822               continue;
 823             }
 824           else
 825             {
 826               /* Jump/Branch insns never appear in prologue basic block.
 827                  The loop can be escaped early when these insns are met.  */
 828               if (in_prologue_bb == 1)
 829                 {
 830                   uint32_t insn5 = CHOP_BITS (insn, 5);
 831                   uint32_t insn8 = CHOP_BITS (insn, 8);
 832                   uint32_t insn38 = CHOP_BITS (insn, 11);
 833
 834                   if (insn5 == N16_TYPE5 (JR5, 0)
 835                       || insn5 == N16_TYPE5 (JRAL5, 0)
 836                       || insn5 == N16_TYPE5 (RET5, 0)
 837                       || insn8 == N16_TYPE8 (J8, 0)
 838                       || insn8 == N16_TYPE8 (BEQZS8, 0)
 839                       || insn8 == N16_TYPE8 (BNEZS8, 0)
 840                       || insn38 == N16_TYPE38 (BEQZ38, 0, 0)
 841                       || insn38 == N16_TYPE38 (BNEZ38, 0, 0)
 842                       || insn38 == N16_TYPE38 (BEQS38, 0, 0)
 843                       || insn38 == N16_TYPE38 (BNES38, 0, 0))
 844                     break;
 845                 }
 846             }
 847
 848           /* The optimizer might shove anything into the prologue, if
 849              we build up cache (cache != NULL) from analyzing prologue,
 850              we just skip what we don't recognize and analyze further to
 851              make cache as complete as possible.  However, if we skip
 852              prologue, we'll stop immediately on unrecognized
 853              instruction.  */
 854           if (cache == NULL)
 855             break;
 856         }
 857     }
 858
 859   return pc;
 860 }
 861
 862 /* Implement the "skip_prologue" gdbarch method.
 863
 864    Find the end of function prologue.  */
 865
 866 static CORE_ADDR
 867 nds32_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
 868 {
 869   CORE_ADDR func_addr, limit_pc;
 870
 871   /* See if we can determine the end of the prologue via the symbol table.
 872      If so, then return either PC, or the PC after the prologue, whichever
 873      is greater.  */
 874   if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
 875     {
 876       CORE_ADDR post_prologue_pc
 877         = skip_prologue_using_sal (gdbarch, func_addr);
 878       if (post_prologue_pc != 0)
 879         return std::max (pc, post_prologue_pc);
 880     }
 881
 882   /* Can't determine prologue from the symbol table, need to examine
 883      instructions.  */
 884
 885   /* Find an upper limit on the function prologue using the debug
 886      information.  If the debug information could not be used to provide
 887      that bound, then use an arbitrary large number as the upper bound.  */
 888   limit_pc = skip_prologue_using_sal (gdbarch, pc);
 889   if (limit_pc == 0)
 890     limit_pc = pc + 128;        /* Magic.  */
 891
 892   /* Find the end of prologue.  */
 893   return nds32_analyze_prologue (gdbarch, pc, limit_pc, NULL);
 894 }
 895
 896 /* Allocate and fill in *THIS_CACHE with information about the prologue of
 897    *THIS_FRAME.  Do not do this if *THIS_CACHE was already allocated.  Return
 898    a pointer to the current nds32_frame_cache in *THIS_CACHE.  */
 899
 900 static struct nds32_frame_cache *
 901 nds32_frame_cache (frame_info_ptr this_frame, void **this_cache)
 902 {
 903   struct gdbarch *gdbarch = get_frame_arch (this_frame);
 904   struct nds32_frame_cache *cache;
 905   CORE_ADDR current_pc;
 906   ULONGEST prev_sp;
 907   ULONGEST this_base;
 908   int i;
 909
 910   if (*this_cache)
 911     return (struct nds32_frame_cache *) *this_cache;
 912
 913   cache = nds32_alloc_frame_cache ();
 914   *this_cache = cache;
 915
 916   cache->pc = get_frame_func (this_frame);
 917   current_pc = get_frame_pc (this_frame);
 918   nds32_analyze_prologue (gdbarch, cache->pc, current_pc, cache);
 919
 920   /* Compute the previous frame's stack pointer (which is also the
 921      frame's ID's stack address), and this frame's base pointer.  */
 922   if (cache->fp_offset != INVALID_OFFSET)
 923     {
 924       /* FP is set in prologue, so it can be used to calculate other info.  */
 925       this_base = get_frame_register_unsigned (this_frame, NDS32_FP_REGNUM);
 926       prev_sp = this_base + cache->fp_offset;
 927     }
 928   else
 929     {
 930       this_base = get_frame_register_unsigned (this_frame, NDS32_SP_REGNUM);
 931       prev_sp = this_base + cache->sp_offset;
 932     }
 933
 934   cache->prev_sp = prev_sp;
 935   cache->base = this_base;
 936
 937   /* Adjust all the saved registers such that they contain addresses
 938      instead of offsets.  */
 939   for (i = 0; i < NDS32_NUM_SAVED_REGS; i++)
 940     if (cache->saved_regs[i] != REG_UNAVAIL)
 941       cache->saved_regs[i] = cache->prev_sp - cache->saved_regs[i];
 942
 943   return cache;
 944 }
 945
 946 /* Implement the "this_id" frame_unwind method.
 947
 948    Our frame ID for a normal frame is the current function's starting
 949    PC and the caller's SP when we were called.  */
 950
 951 static void
 952 nds32_frame_this_id (frame_info_ptr this_frame,
 953                      void **this_cache, struct frame_id *this_id)
 954 {
 955   struct nds32_frame_cache *cache = nds32_frame_cache (this_frame, this_cache);
 956
 957   /* This marks the outermost frame.  */
 958   if (cache->prev_sp == 0)
 959     return;
 960
 961   *this_id = frame_id_build (cache->prev_sp, cache->pc);
 962 }
 963
 964 /* Implement the "prev_register" frame_unwind method.  */
 965
 966 static struct value *
 967 nds32_frame_prev_register (frame_info_ptr this_frame, void **this_cache,
 968                            int regnum)
 969 {
 970   struct nds32_frame_cache *cache = nds32_frame_cache (this_frame, this_cache);
 971
 972   if (regnum == NDS32_SP_REGNUM)
 973     return frame_unwind_got_constant (this_frame, regnum, cache->prev_sp);
 974
 975   /* The PC of the previous frame is stored in the LP register of
 976      the current frame.  */
 977   if (regnum == NDS32_PC_REGNUM)
 978     regnum = NDS32_LP_REGNUM;
 979
 980   if (regnum < NDS32_NUM_SAVED_REGS && cache->saved_regs[regnum] != REG_UNAVAIL)
 981     return frame_unwind_got_memory (this_frame, regnum,
 982                                     cache->saved_regs[regnum]);
 983
 984   return frame_unwind_got_register (this_frame, regnum, regnum);
 985 }
 986
 987 static const struct frame_unwind nds32_frame_unwind =
 988 {
 989   "nds32 prologue",
 990   NORMAL_FRAME,
 991   default_frame_unwind_stop_reason,
 992   nds32_frame_this_id,
 993   nds32_frame_prev_register,
 994   NULL,
 995   default_frame_sniffer,
 996 };
 997
 998 /* Return the frame base address of *THIS_FRAME.  */
 999
1000 static CORE_ADDR
1001 nds32_frame_base_address (frame_info_ptr this_frame, void **this_cache)
1002 {
1003   struct nds32_frame_cache *cache = nds32_frame_cache (this_frame, this_cache);
1004
1005   return cache->base;
1006 }
1007
1008 static const struct frame_base nds32_frame_base =
1009 {
1010   &nds32_frame_unwind,
1011   nds32_frame_base_address,
1012   nds32_frame_base_address,
1013   nds32_frame_base_address
1014 };
1015 \f
1016 /* Helper function for instructions used to pop multiple words.  */
1017
1018 static void
1019 nds32_pop_multiple_words (struct nds32_frame_cache *cache, int rb, int re,
1020                           int enable4)
1021 {
1022   CORE_ADDR sp_offset = cache->sp_offset;
1023   int i;
1024
1025   /* Skip case where re == rb == sp.  */
1026   if ((rb < REG_FP) && (re < REG_FP))
1027     {
1028       for (i = rb; i <= re; i++)
1029         {
1030           cache->saved_regs[i] = sp_offset;
1031           sp_offset += 4;
1032         }
1033     }
1034
1035   /* Check FP, GP, LP in enable4.  */
1036   for (i = 3; i >= 1; i--)
1037     {
1038       if ((enable4 >> i) & 0x1)
1039         {
1040           cache->saved_regs[NDS32_SP_REGNUM - i] = sp_offset;
1041           sp_offset += 4;
1042         }
1043     }
1044
1045   /* For sp, update the offset.  */
1046   cache->sp_offset = sp_offset;
1047 }
1048
1049 /* The instruction sequences in NDS32 epilogue are
1050
1051    INSN_RESET_SP  (optional)
1052                   (If exists, this must be the first instruction in epilogue
1053                    and the stack has not been destroyed.).
1054    INSN_RECOVER  (optional).
1055    INSN_RETURN/INSN_RECOVER_RETURN  (required).  */
1056
1057 /* Helper function for analyzing the given 32-bit INSN.  If CACHE is non-NULL,
1058    the necessary information will be recorded.  */
1059
1060 static inline int
1061 nds32_analyze_epilogue_insn32 (int abi_use_fpr, uint32_t insn,
1062                                struct nds32_frame_cache *cache)
1063 {
1064   if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_SP, REG_SP, 0)
1065       && N32_IMM15S (insn) > 0)
1066     /* addi $sp, $sp, imm15s */
1067     return INSN_RESET_SP;
1068   else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_SP, REG_FP, 0)
1069            && N32_IMM15S (insn) < 0)
1070     /* addi $sp, $fp, imm15s */
1071     return INSN_RESET_SP;
1072   else if ((insn & ~(__MASK (19) << 6)) == N32_LMW_BIM
1073            && N32_RA5 (insn) == REG_SP)
1074     {
1075       /* lmw.bim Rb, [$sp], Re, enable4 */
1076       if (cache != NULL)
1077         nds32_pop_multiple_words (cache, N32_RT5 (insn),
1078                                   N32_RB5 (insn), N32_LSMW_ENABLE4 (insn));
1079
1080       return INSN_RECOVER;
1081     }
1082   else if (insn == N32_JREG (JR, 0, REG_LP, 0, 1))
1083     /* ret $lp */
1084     return INSN_RETURN;
1085   else if (insn == N32_ALU1 (ADD, REG_SP, REG_SP, REG_TA)
1086            || insn == N32_ALU1 (ADD, REG_SP, REG_TA, REG_SP))
1087     /* add $sp, $sp, $ta */
1088     /* add $sp, $ta, $sp */
1089     return INSN_RESET_SP;
1090   else if (abi_use_fpr
1091            && (insn & ~(__MASK (5) << 20 | __MASK (13))) == N32_FLDI_SP)
1092     {
1093       if (__GF (insn, 12, 1) == 0)
1094         /* fldi FDt, [$sp + (imm12s << 2)] */
1095         return INSN_RECOVER;
1096       else
1097         {
1098           /* fldi.bi FDt, [$sp], (imm12s << 2) */
1099           int offset = N32_IMM12S (insn) << 2;
1100
1101           if (offset == 8 || offset == 12)
1102             {
1103               if (cache != NULL)
1104                 cache->sp_offset += offset;
1105
1106               return INSN_RECOVER;
1107             }
1108         }
1109     }
1110
1111   return INSN_NORMAL;
1112 }
1113
1114 /* Helper function for analyzing the given 16-bit INSN.  If CACHE is non-NULL,
1115    the necessary information will be recorded.  */
1116
1117 static inline int
1118 nds32_analyze_epilogue_insn16 (uint32_t insn, struct nds32_frame_cache *cache)
1119 {
1120   if (insn == N16_TYPE5 (RET5, REG_LP))
1121     /* ret5 $lp */
1122     return INSN_RETURN;
1123   else if (CHOP_BITS (insn, 10) == N16_TYPE10 (ADDI10S, 0))
1124     {
1125       /* addi10s.sp */
1126       int imm10s = N16_IMM10S (insn);
1127
1128       if (imm10s > 0)
1129         {
1130           if (cache != NULL)
1131             cache->sp_offset += imm10s;
1132
1133           return INSN_RECOVER;
1134         }
1135     }
1136   else if (__GF (insn, 7, 8) == N16_T25_POP25)
1137     {
1138       /* pop25 */
1139       if (cache != NULL)
1140         {
1141           int imm8u = (insn & 0x1f) << 3;
1142           int re = (insn >> 5) & 0x3;
1143           const int reg_map[] = { 6, 8, 10, 14 };
1144
1145           /* Operation 1 -- sp = sp + (imm5u << 3) */
1146           cache->sp_offset += imm8u;
1147
1148           /* Operation 2 -- lmw.bim R6, [$sp], Re, #0xe */
1149           nds32_pop_multiple_words (cache, 6, reg_map[re], 0xe);
1150         }
1151
1152       /* Operation 3 -- ret $lp */
1153       return INSN_RECOVER_RETURN;
1154     }
1155
1156   return INSN_NORMAL;
1157 }
1158
1159 /* Analyze a reasonable amount of instructions from the given PC to find
1160    the instruction used to return to the caller.  Return 1 if the 'return'
1161    instruction could be found, 0 otherwise.
1162
1163    If CACHE is non-NULL, fill it in.  */
1164
1165 static int
1166 nds32_analyze_epilogue (struct gdbarch *gdbarch, CORE_ADDR pc,
1167                         struct nds32_frame_cache *cache)
1168 {
1169   nds32_gdbarch_tdep *tdep = gdbarch_tdep<nds32_gdbarch_tdep> (gdbarch);
1170   int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
1171   CORE_ADDR limit_pc;
1172   uint32_t insn, insn_len;
1173   int insn_type = INSN_NORMAL;
1174
1175   if (abi_use_fpr)
1176     limit_pc = pc + 48;
1177   else
1178     limit_pc = pc + 16;
1179
1180   for (; pc < limit_pc; pc += insn_len)
1181     {
1182       insn = read_memory_unsigned_integer (pc, 4, BFD_ENDIAN_BIG);
1183
1184       if ((insn & 0x80000000) == 0)
1185         {
1186           /* 32-bit instruction */
1187           insn_len = 4;
1188
1189           insn_type = nds32_analyze_epilogue_insn32 (abi_use_fpr, insn, cache);
1190           if (insn_type == INSN_RETURN)
1191             return 1;
1192           else if (insn_type == INSN_RECOVER)
1193             continue;
1194         }
1195       else
1196         {
1197           /* 16-bit instruction */
1198           insn_len = 2;
1199
1200           insn >>= 16;
1201           insn_type = nds32_analyze_epilogue_insn16 (insn, cache);
1202           if (insn_type == INSN_RETURN || insn_type == INSN_RECOVER_RETURN)
1203             return 1;
1204           else if (insn_type == INSN_RECOVER)
1205             continue;
1206         }
1207
1208       /* Stop the scan if this is an unexpected instruction.  */
1209       break;
1210     }
1211
1212   return 0;
1213 }
1214
1215 /* Implement the "stack_frame_destroyed_p" gdbarch method.  */
1216
1217 static int
1218 nds32_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR addr)
1219 {
1220   nds32_gdbarch_tdep *tdep = gdbarch_tdep<nds32_gdbarch_tdep> (gdbarch);
1221   int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
1222   int insn_type = INSN_NORMAL;
1223   int ret_found = 0;
1224   uint32_t insn;
1225
1226   insn = read_memory_unsigned_integer (addr, 4, BFD_ENDIAN_BIG);
1227
1228   if ((insn & 0x80000000) == 0)
1229     {
1230       /* 32-bit instruction */
1231
1232       insn_type = nds32_analyze_epilogue_insn32 (abi_use_fpr, insn, NULL);
1233     }
1234   else
1235     {
1236       /* 16-bit instruction */
1237
1238       insn >>= 16;
1239       insn_type = nds32_analyze_epilogue_insn16 (insn, NULL);
1240     }
1241
1242   if (insn_type == INSN_NORMAL || insn_type == INSN_RESET_SP)
1243     return 0;
1244
1245   /* Search the required 'return' instruction within the following reasonable
1246      instructions.  */
1247   ret_found = nds32_analyze_epilogue (gdbarch, addr, NULL);
1248   if (ret_found == 0)
1249     return 0;
1250
1251   /* Scan backwards to make sure that the last instruction has adjusted
1252      stack.  Both a 16-bit and a 32-bit instruction will be tried.  This is
1253      just a heuristic, so the false positives will be acceptable.  */
1254   insn = read_memory_unsigned_integer (addr - 2, 4, BFD_ENDIAN_BIG);
1255
1256   /* Only 16-bit instructions are possible at addr - 2.  */
1257   if ((insn & 0x80000000) != 0)
1258     {
1259       /* This may be a 16-bit instruction or part of a 32-bit instruction.  */
1260
1261       insn_type = nds32_analyze_epilogue_insn16 (insn >> 16, NULL);
1262       if (insn_type == INSN_RECOVER)
1263         return 1;
1264     }
1265
1266   insn = read_memory_unsigned_integer (addr - 4, 4, BFD_ENDIAN_BIG);
1267
1268   /* If this is a 16-bit instruction at addr - 4, then there must be another
1269      16-bit instruction at addr - 2, so only 32-bit instructions need to
1270      be analyzed here.  */
1271   if ((insn & 0x80000000) == 0)
1272     {
1273       /* This may be a 32-bit instruction or part of a 32-bit instruction.  */
1274
1275       insn_type = nds32_analyze_epilogue_insn32 (abi_use_fpr, insn, NULL);
1276       if (insn_type == INSN_RECOVER || insn_type == INSN_RESET_SP)
1277         return 1;
1278     }
1279
1280   return 0;
1281 }
1282
1283 /* Implement the "sniffer" frame_unwind method.  */
1284
1285 static int
1286 nds32_epilogue_frame_sniffer (const struct frame_unwind *self,
1287                               frame_info_ptr this_frame, void **this_cache)
1288 {
1289   if (frame_relative_level (this_frame) == 0)
1290     return nds32_stack_frame_destroyed_p (get_frame_arch (this_frame),
1291                                           get_frame_pc (this_frame));
1292   else
1293     return 0;
1294 }
1295
1296 /* Allocate and fill in *THIS_CACHE with information needed to unwind
1297    *THIS_FRAME within epilogue.  Do not do this if *THIS_CACHE was already
1298    allocated.  Return a pointer to the current nds32_frame_cache in
1299    *THIS_CACHE.  */
1300
1301 static struct nds32_frame_cache *
1302 nds32_epilogue_frame_cache (frame_info_ptr this_frame, void **this_cache)
1303 {
1304   struct gdbarch *gdbarch = get_frame_arch (this_frame);
1305   struct nds32_frame_cache *cache;
1306   CORE_ADDR current_pc, current_sp;
1307   int i;
1308
1309   if (*this_cache)
1310     return (struct nds32_frame_cache *) *this_cache;
1311
1312   cache = nds32_alloc_frame_cache ();
1313   *this_cache = cache;
1314
1315   cache->pc = get_frame_func (this_frame);
1316   current_pc = get_frame_pc (this_frame);
1317   nds32_analyze_epilogue (gdbarch, current_pc, cache);
1318
1319   current_sp = get_frame_register_unsigned (this_frame, NDS32_SP_REGNUM);
1320   cache->prev_sp = current_sp + cache->sp_offset;
1321
1322   /* Adjust all the saved registers such that they contain addresses
1323      instead of offsets.  */
1324   for (i = 0; i < NDS32_NUM_SAVED_REGS; i++)
1325     if (cache->saved_regs[i] != REG_UNAVAIL)
1326       cache->saved_regs[i] = current_sp + cache->saved_regs[i];
1327
1328   return cache;
1329 }
1330
1331 /* Implement the "this_id" frame_unwind method.  */
1332
1333 static void
1334 nds32_epilogue_frame_this_id (frame_info_ptr this_frame,
1335                               void **this_cache, struct frame_id *this_id)
1336 {
1337   struct nds32_frame_cache *cache
1338     = nds32_epilogue_frame_cache (this_frame, this_cache);
1339
1340   /* This marks the outermost frame.  */
1341   if (cache->prev_sp == 0)
1342     return;
1343
1344   *this_id = frame_id_build (cache->prev_sp, cache->pc);
1345 }
1346
1347 /* Implement the "prev_register" frame_unwind method.  */
1348
1349 static struct value *
1350 nds32_epilogue_frame_prev_register (frame_info_ptr this_frame,
1351                                     void **this_cache, int regnum)
1352 {
1353   struct nds32_frame_cache *cache
1354     = nds32_epilogue_frame_cache (this_frame, this_cache);
1355
1356   if (regnum == NDS32_SP_REGNUM)
1357     return frame_unwind_got_constant (this_frame, regnum, cache->prev_sp);
1358
1359   /* The PC of the previous frame is stored in the LP register of
1360      the current frame.  */
1361   if (regnum == NDS32_PC_REGNUM)
1362     regnum = NDS32_LP_REGNUM;
1363
1364   if (regnum < NDS32_NUM_SAVED_REGS && cache->saved_regs[regnum] != REG_UNAVAIL)
1365     return frame_unwind_got_memory (this_frame, regnum,
1366                                     cache->saved_regs[regnum]);
1367
1368   return frame_unwind_got_register (this_frame, regnum, regnum);
1369 }
1370
1371 static const struct frame_unwind nds32_epilogue_frame_unwind =
1372 {
1373   "nds32 epilogue",
1374   NORMAL_FRAME,
1375   default_frame_unwind_stop_reason,
1376   nds32_epilogue_frame_this_id,
1377   nds32_epilogue_frame_prev_register,
1378   NULL,
1379   nds32_epilogue_frame_sniffer
1380 };
1381
1382 \f
1383 /* Floating type and struct type that has only one floating type member
1384    can pass value using FPU registers (when FPU ABI is used).  */
1385
1386 static int
1387 nds32_check_calling_use_fpr (struct type *type)
1388 {
1389   struct type *t;
1390   enum type_code typecode;
1391
1392   t = type;
1393   while (1)
1394     {
1395       t = check_typedef (t);
1396       typecode = t->code ();
1397       if (typecode != TYPE_CODE_STRUCT)
1398         break;
1399       else if (t->num_fields () != 1)
1400         return 0;
1401       else
1402         t = t->field (0).type ();
1403     }
1404
1405   return typecode == TYPE_CODE_FLT;
1406 }
1407
1408 /* Implement the "push_dummy_call" gdbarch method.  */
1409
1410 static CORE_ADDR
1411 nds32_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1412                        struct regcache *regcache, CORE_ADDR bp_addr,
1413                        int nargs, struct value **args, CORE_ADDR sp,
1414                        function_call_return_method return_method,
1415                        CORE_ADDR struct_addr)
1416 {
1417   const int REND = 6;           /* End for register offset.  */
1418   int goff = 0;                 /* Current gpr offset for argument.  */
1419   int foff = 0;                 /* Current fpr offset for argument.  */
1420   int soff = 0;                 /* Current stack offset for argument.  */
1421   int i;
1422   ULONGEST regval;
1423   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1424   nds32_gdbarch_tdep *tdep = gdbarch_tdep<nds32_gdbarch_tdep> (gdbarch);
1425   struct type *func_type = value_type (function);
1426   int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
1427   int abi_split = nds32_abi_split (tdep->elf_abi);
1428
1429   /* Set the return address.  For the NDS32, the return breakpoint is
1430      always at BP_ADDR.  */
1431   regcache_cooked_write_unsigned (regcache, NDS32_LP_REGNUM, bp_addr);
1432
1433   /* If STRUCT_RETURN is true, then the struct return address (in
1434      STRUCT_ADDR) will consume the first argument-passing register.
1435      Both adjust the register count and store that value.  */
1436   if (return_method == return_method_struct)
1437     {
1438       regcache_cooked_write_unsigned (regcache, NDS32_R0_REGNUM, struct_addr);
1439       goff++;
1440     }
1441
1442   /* Now make sure there's space on the stack */
1443   for (i = 0; i < nargs; i++)
1444     {
1445       struct type *type = value_type (args[i]);
1446       int align = type_align (type);
1447
1448       /* If align is zero, it may be an empty struct.
1449          Just ignore the argument of empty struct.  */
1450       if (align == 0)
1451         continue;
1452
1453       sp -= type->length ();
1454       sp = align_down (sp, align);
1455     }
1456
1457   /* Stack must be 8-byte aligned.  */
1458   sp = align_down (sp, 8);
1459
1460   soff = 0;
1461   for (i = 0; i < nargs; i++)
1462     {
1463       const gdb_byte *val;
1464       int align, len;
1465       struct type *type;
1466       int calling_use_fpr;
1467       int use_fpr = 0;
1468
1469       type = value_type (args[i]);
1470       calling_use_fpr = nds32_check_calling_use_fpr (type);
1471       len = type->length ();
1472       align = type_align (type);
1473       val = value_contents (args[i]).data ();
1474
1475       /* The size of a composite type larger than 4 bytes will be rounded
1476          up to the nearest multiple of 4.  */
1477       if (len > 4)
1478         len = align_up (len, 4);
1479
1480       /* Variadic functions are handled differently between AABI and ABI2FP+.
1481
1482          For AABI, the caller pushes arguments in registers, callee stores
1483          unnamed arguments in stack, and then va_arg fetch arguments in stack.
1484          Therefore, we don't have to handle variadic functions specially.
1485
1486          For ABI2FP+, the caller pushes only named arguments in registers
1487          and pushes all unnamed arguments in stack.  */
1488
1489       if (abi_use_fpr && func_type->has_varargs ()
1490           && i >= func_type->num_fields ())
1491         goto use_stack;
1492
1493       /* Try to use FPRs to pass arguments only when
1494          1. The program is built using toolchain with FPU support.
1495          2. The type of this argument can use FPR to pass value.  */
1496       use_fpr = abi_use_fpr && calling_use_fpr;
1497
1498       if (use_fpr)
1499         {
1500           if (tdep->fpu_freg == -1)
1501             goto error_no_fpr;
1502
1503           /* Adjust alignment.  */
1504           if ((align >> 2) > 0)
1505             foff = align_up (foff, align >> 2);
1506
1507           if (foff < REND)
1508             {
1509               switch (len)
1510                 {
1511                 case 4:
1512                   regcache->cooked_write (tdep->fs0_regnum + foff, val);
1513                   foff++;
1514                   break;
1515                 case 8:
1516                   regcache->cooked_write (NDS32_FD0_REGNUM + (foff >> 1), val);
1517                   foff += 2;
1518                   break;
1519                 default:
1520                   /* Long double?  */
1521                   internal_error (__FILE__, __LINE__,
1522                                   "Do not know how to handle %d-byte double.\n",
1523                                   len);
1524                   break;
1525                 }
1526               continue;
1527             }
1528         }
1529       else
1530         {
1531           /*
1532              When passing arguments using GPRs,
1533
1534              * A composite type not larger than 4 bytes is passed in $rN.
1535                The format is as if the value is loaded with load instruction
1536                of corresponding size (e.g., LB, LH, LW).
1537
1538                For example,
1539
1540                        r0
1541                        31      0
1542                LITTLE: [x x b a]
1543                   BIG: [x x a b]
1544
1545              * Otherwise, a composite type is passed in consecutive registers.
1546                The size is rounded up to the nearest multiple of 4.
1547                The successive registers hold the parts of the argument as if
1548                were loaded using lmw instructions.
1549
1550                For example,
1551
1552                        r0        r1
1553                        31      0 31      0
1554                LITTLE: [d c b a] [x x x e]
1555                   BIG: [a b c d] [e x x x]
1556            */
1557
1558           /* Adjust alignment.  */
1559           if ((align >> 2) > 0)
1560             goff = align_up (goff, align >> 2);
1561
1562           if (len <= (REND - goff) * 4)
1563             {
1564               /* This argument can be passed wholly via GPRs.  */
1565               while (len > 0)
1566                 {
1567                   regval = extract_unsigned_integer (val, (len > 4) ? 4 : len,
1568                                                      byte_order);
1569                   regcache_cooked_write_unsigned (regcache,
1570                                                   NDS32_R0_REGNUM + goff,
1571                                                   regval);
1572                   len -= 4;
1573                   val += 4;
1574                   goff++;
1575                 }
1576               continue;
1577             }
1578           else if (abi_split)
1579             {
1580               /* Some parts of this argument can be passed via GPRs.  */
1581               while (goff < REND)
1582                 {
1583                   regval = extract_unsigned_integer (val, (len > 4) ? 4 : len,
1584                                                      byte_order);
1585                   regcache_cooked_write_unsigned (regcache,
1586                                                   NDS32_R0_REGNUM + goff,
1587                                                   regval);
1588                   len -= 4;
1589                   val += 4;
1590                   goff++;
1591                 }
1592             }
1593         }
1594
1595 use_stack:
1596       /*
1597          When pushing (split parts of) an argument into stack,
1598
1599          * A composite type not larger than 4 bytes is copied to different
1600            base address.
1601            In little-endian, the first byte of this argument is aligned
1602            at the low address of the next free word.
1603            In big-endian, the last byte of this argument is aligned
1604            at the high address of the next free word.
1605
1606            For example,
1607
1608            sp [ - ]  [ c ] hi
1609               [ c ]  [ b ]
1610               [ b ]  [ a ]
1611               [ a ]  [ - ] lo
1612              LITTLE   BIG
1613        */
1614
1615       /* Adjust alignment.  */
1616       soff = align_up (soff, align);
1617
1618       while (len > 0)
1619         {
1620           int rlen = (len > 4) ? 4 : len;
1621
1622           if (byte_order == BFD_ENDIAN_BIG)
1623             write_memory (sp + soff + 4 - rlen, val, rlen);
1624           else
1625             write_memory (sp + soff, val, rlen);
1626
1627           len -= 4;
1628           val += 4;
1629           soff += 4;
1630         }
1631     }
1632
1633   /* Finally, update the SP register.  */
1634   regcache_cooked_write_unsigned (regcache, NDS32_SP_REGNUM, sp);
1635
1636   return sp;
1637
1638 error_no_fpr:
1639   /* If use_fpr, but no floating-point register exists,
1640      then it is an error.  */
1641   error (_("Fail to call. FPU registers are required."));
1642 }
1643 \f
1644 /* Read, for architecture GDBARCH, a function return value of TYPE
1645    from REGCACHE, and copy that into VALBUF.  */
1646
1647 static void
1648 nds32_extract_return_value (struct gdbarch *gdbarch, struct type *type,
1649                             struct regcache *regcache, gdb_byte *valbuf)
1650 {
1651   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1652   nds32_gdbarch_tdep *tdep = gdbarch_tdep<nds32_gdbarch_tdep> (gdbarch);
1653   int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
1654   int calling_use_fpr;
1655   int len;
1656
1657   calling_use_fpr = nds32_check_calling_use_fpr (type);
1658   len = type->length ();
1659
1660   if (abi_use_fpr && calling_use_fpr)
1661     {
1662       if (len == 4)
1663         regcache->cooked_read (tdep->fs0_regnum, valbuf);
1664       else if (len == 8)
1665         regcache->cooked_read (NDS32_FD0_REGNUM, valbuf);
1666       else
1667         internal_error (__FILE__, __LINE__,
1668                         _("Cannot extract return value of %d bytes "
1669                           "long floating-point."), len);
1670     }
1671   else
1672     {
1673       /*
1674          When returning result,
1675
1676          * A composite type not larger than 4 bytes is returned in $r0.
1677            The format is as if the result is loaded with load instruction
1678            of corresponding size (e.g., LB, LH, LW).
1679
1680            For example,
1681
1682                    r0
1683                    31      0
1684            LITTLE: [x x b a]
1685               BIG: [x x a b]
1686
1687          * Otherwise, a composite type not larger than 8 bytes is returned
1688            in $r0 and $r1.
1689            In little-endian, the first word is loaded in $r0.
1690            In big-endian, the last word is loaded in $r1.
1691
1692            For example,
1693
1694                    r0        r1
1695                    31      0 31      0
1696            LITTLE: [d c b a] [x x x e]
1697               BIG: [x x x a] [b c d e]
1698        */
1699
1700       ULONGEST tmp;
1701
1702       if (len < 4)
1703         {
1704           /* By using store_unsigned_integer we avoid having to do
1705              anything special for small big-endian values.  */
1706           regcache_cooked_read_unsigned (regcache, NDS32_R0_REGNUM, &tmp);
1707           store_unsigned_integer (valbuf, len, byte_order, tmp);
1708         }
1709       else if (len == 4)
1710         {
1711           regcache->cooked_read (NDS32_R0_REGNUM, valbuf);
1712         }
1713       else if (len < 8)
1714         {
1715           int len1, len2;
1716
1717           len1 = byte_order == BFD_ENDIAN_BIG ? len - 4 : 4;
1718           len2 = len - len1;
1719
1720           regcache_cooked_read_unsigned (regcache, NDS32_R0_REGNUM, &tmp);
1721           store_unsigned_integer (valbuf, len1, byte_order, tmp);
1722
1723           regcache_cooked_read_unsigned (regcache, NDS32_R0_REGNUM + 1, &tmp);
1724           store_unsigned_integer (valbuf + len1, len2, byte_order, tmp);
1725         }
1726       else
1727         {
1728           regcache->cooked_read (NDS32_R0_REGNUM, valbuf);
1729           regcache->cooked_read (NDS32_R0_REGNUM + 1, valbuf + 4);
1730         }
1731     }
1732 }
1733
1734 /* Write, for architecture GDBARCH, a function return value of TYPE
1735    from VALBUF into REGCACHE.  */
1736
1737 static void
1738 nds32_store_return_value (struct gdbarch *gdbarch, struct type *type,
1739                           struct regcache *regcache, const gdb_byte *valbuf)
1740 {
1741   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1742   nds32_gdbarch_tdep *tdep = gdbarch_tdep<nds32_gdbarch_tdep> (gdbarch);
1743   int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
1744   int calling_use_fpr;
1745   int len;
1746
1747   calling_use_fpr = nds32_check_calling_use_fpr (type);
1748   len = type->length ();
1749
1750   if (abi_use_fpr && calling_use_fpr)
1751     {
1752       if (len == 4)
1753         regcache->cooked_write (tdep->fs0_regnum, valbuf);
1754       else if (len == 8)
1755         regcache->cooked_write (NDS32_FD0_REGNUM, valbuf);
1756       else
1757         internal_error (__FILE__, __LINE__,
1758                         _("Cannot store return value of %d bytes "
1759                           "long floating-point."), len);
1760     }
1761   else
1762     {
1763       ULONGEST regval;
1764
1765       if (len < 4)
1766         {
1767           regval = extract_unsigned_integer (valbuf, len, byte_order);
1768           regcache_cooked_write_unsigned (regcache, NDS32_R0_REGNUM, regval);
1769         }
1770       else if (len == 4)
1771         {
1772           regcache->cooked_write (NDS32_R0_REGNUM, valbuf);
1773         }
1774       else if (len < 8)
1775         {
1776           int len1, len2;
1777
1778           len1 = byte_order == BFD_ENDIAN_BIG ? len - 4 : 4;
1779           len2 = len - len1;
1780
1781           regval = extract_unsigned_integer (valbuf, len1, byte_order);
1782           regcache_cooked_write_unsigned (regcache, NDS32_R0_REGNUM, regval);
1783
1784           regval = extract_unsigned_integer (valbuf + len1, len2, byte_order);
1785           regcache_cooked_write_unsigned (regcache, NDS32_R0_REGNUM + 1,
1786                                           regval);
1787         }
1788       else
1789         {
1790           regcache->cooked_write (NDS32_R0_REGNUM, valbuf);
1791           regcache->cooked_write (NDS32_R0_REGNUM + 1, valbuf + 4);
1792         }
1793     }
1794 }
1795
1796 /* Implement the "return_value" gdbarch method.
1797
1798    Determine, for architecture GDBARCH, how a return value of TYPE
1799    should be returned.  If it is supposed to be returned in registers,
1800    and READBUF is non-zero, read the appropriate value from REGCACHE,
1801    and copy it into READBUF.  If WRITEBUF is non-zero, write the value
1802    from WRITEBUF into REGCACHE.  */
1803
1804 static enum return_value_convention
1805 nds32_return_value (struct gdbarch *gdbarch, struct value *func_type,
1806                     struct type *type, struct regcache *regcache,
1807                     gdb_byte *readbuf, const gdb_byte *writebuf)
1808 {
1809   if (type->length () > 8)
1810     {
1811       return RETURN_VALUE_STRUCT_CONVENTION;
1812     }
1813   else
1814     {
1815       if (readbuf != NULL)
1816         nds32_extract_return_value (gdbarch, type, regcache, readbuf);
1817       if (writebuf != NULL)
1818         nds32_store_return_value (gdbarch, type, regcache, writebuf);
1819
1820       return RETURN_VALUE_REGISTER_CONVENTION;
1821     }
1822 }
1823 \f
1824 /* Implement the "get_longjmp_target" gdbarch method.  */
1825
1826 static int
1827 nds32_get_longjmp_target (frame_info_ptr frame, CORE_ADDR *pc)
1828 {
1829   gdb_byte buf[4];
1830   CORE_ADDR jb_addr;
1831   struct gdbarch *gdbarch = get_frame_arch (frame);
1832   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1833
1834   jb_addr = get_frame_register_unsigned (frame, NDS32_R0_REGNUM);
1835
1836   if (target_read_memory (jb_addr + 11 * 4, buf, 4))
1837     return 0;
1838
1839   *pc = extract_unsigned_integer (buf, 4, byte_order);
1840   return 1;
1841 }
1842 \f
1843 /* Validate the given TDESC, and fixed-number some registers in it.
1844    Return 0 if the given TDESC does not contain the required feature
1845    or not contain required registers.  */
1846
1847 static int
1848 nds32_validate_tdesc_p (const struct target_desc *tdesc,
1849                         struct tdesc_arch_data *tdesc_data,
1850                         int *fpu_freg, int *use_pseudo_fsrs)
1851 {
1852   const struct tdesc_feature *feature;
1853   int i, valid_p;
1854
1855   feature = tdesc_find_feature (tdesc, "org.gnu.gdb.nds32.core");
1856   if (feature == NULL)
1857     return 0;
1858
1859   valid_p = 1;
1860   /* Validate and fixed-number R0-R10.  */
1861   for (i = NDS32_R0_REGNUM; i <= NDS32_R0_REGNUM + 10; i++)
1862     valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
1863                                         nds32_register_names[i]);
1864
1865   /* Validate R15.  */
1866   valid_p &= tdesc_unnumbered_register (feature,
1867                                         nds32_register_names[NDS32_TA_REGNUM]);
1868
1869   /* Validate and fixed-number FP, GP, LP, SP, PC.  */
1870   for (i = NDS32_FP_REGNUM; i <= NDS32_PC_REGNUM; i++)
1871     valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
1872                                         nds32_register_names[i]);
1873
1874   if (!valid_p)
1875     return 0;
1876
1877   /* Fixed-number R11-R27.  */
1878   for (i = NDS32_R0_REGNUM + 11; i <= NDS32_R0_REGNUM + 27; i++)
1879     tdesc_numbered_register (feature, tdesc_data, i, nds32_register_names[i]);
1880
1881   feature = tdesc_find_feature (tdesc, "org.gnu.gdb.nds32.fpu");
1882   if (feature != NULL)
1883     {
1884       int num_fdr_regs, num_fsr_regs, fs0_regnum, num_listed_fsr;
1885       int freg = -1;
1886
1887       /* Guess FPU configuration via listed registers.  */
1888       if (tdesc_unnumbered_register (feature, "fd31"))
1889         freg = 3;
1890       else if (tdesc_unnumbered_register (feature, "fd15"))
1891         freg = 2;
1892       else if (tdesc_unnumbered_register (feature, "fd7"))
1893         freg = 1;
1894       else if (tdesc_unnumbered_register (feature, "fd3"))
1895         freg = 0;
1896
1897       if (freg == -1)
1898         /* Required FDR is not found.  */
1899         return 0;
1900       else
1901         *fpu_freg = freg;
1902
1903       /* Validate and fixed-number required FDRs.  */
1904       num_fdr_regs = num_fdr_map[freg];
1905       for (i = 0; i < num_fdr_regs; i++)
1906         valid_p &= tdesc_numbered_register (feature, tdesc_data,
1907                                             NDS32_FD0_REGNUM + i,
1908                                             nds32_fdr_register_names[i]);
1909       if (!valid_p)
1910         return 0;
1911
1912       /* Count the number of listed FSRs, and fixed-number them if present.  */
1913       num_fsr_regs = num_fsr_map[freg];
1914       fs0_regnum = NDS32_FD0_REGNUM + num_fdr_regs;
1915       num_listed_fsr = 0;
1916       for (i = 0; i < num_fsr_regs; i++)
1917         num_listed_fsr += tdesc_numbered_register (feature, tdesc_data,
1918                                                    fs0_regnum + i,
1919                                                    nds32_fsr_register_names[i]);
1920
1921       if (num_listed_fsr == 0)
1922         /* No required FSRs are listed explicitly,  make them pseudo registers
1923            of FDRs.  */
1924         *use_pseudo_fsrs = 1;
1925       else if (num_listed_fsr == num_fsr_regs)
1926         /* All required FSRs are listed explicitly.  */
1927         *use_pseudo_fsrs = 0;
1928       else
1929         /* Some required FSRs are missing.  */
1930         return 0;
1931     }
1932
1933   return 1;
1934 }
1935
1936 /* Initialize the current architecture based on INFO.  If possible,
1937    re-use an architecture from ARCHES, which is a list of
1938    architectures already created during this debugging session.
1939
1940    Called e.g. at program startup, when reading a core file, and when
1941    reading a binary file.  */
1942
1943 static struct gdbarch *
1944 nds32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1945 {
1946   struct gdbarch *gdbarch;
1947   struct gdbarch_list *best_arch;
1948   tdesc_arch_data_up tdesc_data;
1949   const struct target_desc *tdesc = info.target_desc;
1950   int elf_abi = E_NDS_ABI_AABI;
1951   int fpu_freg = -1;
1952   int use_pseudo_fsrs = 0;
1953   int i, num_regs, maxregs;
1954
1955   /* Extract the elf_flags if available.  */
1956   if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
1957     elf_abi = elf_elfheader (info.abfd)->e_flags & EF_NDS_ABI;
1958
1959   /* If there is already a candidate, use it.  */
1960   for (best_arch = gdbarch_list_lookup_by_info (arches, &info);
1961        best_arch != NULL;
1962        best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info))
1963     {
1964       nds32_gdbarch_tdep *idep
1965         = gdbarch_tdep<nds32_gdbarch_tdep> (best_arch->gdbarch);
1966
1967       if (idep->elf_abi != elf_abi)
1968         continue;
1969
1970       /* Found a match.  */
1971       break;
1972     }
1973
1974   if (best_arch != NULL)
1975     return best_arch->gdbarch;
1976
1977   if (!tdesc_has_registers (tdesc))
1978     tdesc = tdesc_nds32;
1979
1980   tdesc_data = tdesc_data_alloc ();
1981
1982   if (!nds32_validate_tdesc_p (tdesc, tdesc_data.get (), &fpu_freg,
1983                                &use_pseudo_fsrs))
1984     return NULL;
1985
1986   /* Allocate space for the new architecture.  */
1987   nds32_gdbarch_tdep *tdep = new nds32_gdbarch_tdep;
1988   tdep->fpu_freg = fpu_freg;
1989   tdep->use_pseudo_fsrs = use_pseudo_fsrs;
1990   tdep->fs0_regnum = -1;
1991   tdep->elf_abi = elf_abi;
1992
1993   gdbarch = gdbarch_alloc (&info, tdep);
1994
1995   set_gdbarch_wchar_bit (gdbarch, 16);
1996   set_gdbarch_wchar_signed (gdbarch, 0);
1997
1998   if (fpu_freg == -1)
1999     num_regs = NDS32_NUM_REGS;
2000   else if (use_pseudo_fsrs == 1)
2001     {
2002       set_gdbarch_pseudo_register_read (gdbarch, nds32_pseudo_register_read);
2003       set_gdbarch_pseudo_register_write (gdbarch, nds32_pseudo_register_write);
2004       set_tdesc_pseudo_register_name (gdbarch, nds32_pseudo_register_name);
2005       set_tdesc_pseudo_register_type (gdbarch, nds32_pseudo_register_type);
2006       set_gdbarch_num_pseudo_regs (gdbarch, num_fsr_map[fpu_freg]);
2007
2008       num_regs = NDS32_NUM_REGS + num_fdr_map[fpu_freg];
2009     }
2010   else
2011     num_regs = NDS32_NUM_REGS + num_fdr_map[fpu_freg] + num_fsr_map[fpu_freg];
2012
2013   set_gdbarch_num_regs (gdbarch, num_regs);
2014   tdesc_use_registers (gdbarch, tdesc, std::move (tdesc_data));
2015
2016   /* Cache the register number of fs0.  */
2017   if (fpu_freg != -1)
2018     tdep->fs0_regnum = user_reg_map_name_to_regnum (gdbarch, "fs0", -1);
2019
2020   /* Add NDS32 register aliases.  To avoid search in user register name space,
2021      user_reg_map_name_to_regnum is not used.  */
2022   maxregs = gdbarch_num_cooked_regs (gdbarch);
2023   for (i = 0; i < ARRAY_SIZE (nds32_register_aliases); i++)
2024     {
2025       int regnum, j;
2026
2027       regnum = -1;
2028       /* Search register name space.  */
2029       for (j = 0; j < maxregs; j++)
2030         {
2031           const char *regname = gdbarch_register_name (gdbarch, j);
2032
2033           if (strcmp (regname, nds32_register_aliases[i].name) == 0)
2034             {
2035               regnum = j;
2036               break;
2037             }
2038         }
2039
2040       /* Try next alias entry if the given name can not be found in register
2041          name space.  */
2042       if (regnum == -1)
2043         continue;
2044
2045       user_reg_add (gdbarch, nds32_register_aliases[i].alias,
2046                     value_of_nds32_reg, (const void *) (intptr_t) regnum);
2047     }
2048
2049   nds32_add_reggroups (gdbarch);
2050
2051   /* Hook in ABI-specific overrides, if they have been registered.  */
2052   info.tdesc_data = tdesc_data.get ();
2053   gdbarch_init_osabi (info, gdbarch);
2054
2055   /* Override tdesc_register callbacks for system registers.  */
2056   set_gdbarch_register_reggroup_p (gdbarch, nds32_register_reggroup_p);
2057
2058   set_gdbarch_sp_regnum (gdbarch, NDS32_SP_REGNUM);
2059   set_gdbarch_pc_regnum (gdbarch, NDS32_PC_REGNUM);
2060   set_gdbarch_stack_frame_destroyed_p (gdbarch, nds32_stack_frame_destroyed_p);
2061   set_gdbarch_dwarf2_reg_to_regnum (gdbarch, nds32_dwarf2_reg_to_regnum);
2062
2063   set_gdbarch_push_dummy_call (gdbarch, nds32_push_dummy_call);
2064   set_gdbarch_return_value (gdbarch, nds32_return_value);
2065
2066   set_gdbarch_skip_prologue (gdbarch, nds32_skip_prologue);
2067   set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2068   set_gdbarch_breakpoint_kind_from_pc (gdbarch,
2069                                        nds32_breakpoint::kind_from_pc);
2070   set_gdbarch_sw_breakpoint_from_kind (gdbarch,
2071                                        nds32_breakpoint::bp_from_kind);
2072
2073   set_gdbarch_frame_align (gdbarch, nds32_frame_align);
2074   frame_base_set_default (gdbarch, &nds32_frame_base);
2075
2076   /* Handle longjmp.  */
2077   set_gdbarch_get_longjmp_target (gdbarch, nds32_get_longjmp_target);
2078
2079   /* The order of appending is the order it check frame.  */
2080   dwarf2_append_unwinders (gdbarch);
2081   frame_unwind_append_unwinder (gdbarch, &nds32_epilogue_frame_unwind);
2082   frame_unwind_append_unwinder (gdbarch, &nds32_frame_unwind);
2083
2084   return gdbarch;
2085 }
2086
2087 void _initialize_nds32_tdep ();
2088 void
2089 _initialize_nds32_tdep ()
2090 {
2091   /* Initialize gdbarch.  */
2092   gdbarch_register (bfd_arch_nds32, nds32_gdbarch_init);
2093
2094   initialize_tdesc_nds32 ();
2095   nds32_init_reggroups ();
2096 }