gdb/ppcobsd-tdep.c

   1 /* Target-dependent code for OpenBSD/powerpc.
   2
   3    Copyright 2004 Free Software Foundation, Inc.
   4
   5    This file is part of GDB.
   6
   7    This program is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 2 of the License, or
  10    (at your option) any later version.
  11
  12    This program is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program; if not, write to the Free Software
  19    Foundation, Inc., 59 Temple Place - Suite 330,
  20    Boston, MA 02111-1307, USA.  */
  21
  22 #include "defs.h"
  23 #include "arch-utils.h"
  24 #include "osabi.h"
  25 #include "regcache.h"
  26 #include "regset.h"
  27 #include "gdb_assert.h"
  28
  29 #include "gdb_string.h"
  30
  31 #include "ppc-tdep.h"
  32 #include "ppcobsd-tdep.h"
  33 #include "solib-svr4.h"
  34
  35 /* Register offsets from <machine/reg.h>.  */
  36 struct ppc_reg_offsets ppcobsd_reg_offsets;
  37 \f
  38
  39 /* Core file support.  */
  40
  41 /* Supply register REGNUM in the general-purpose register set REGSET
  42    from the buffer specified by GREGS and LEN to register cache
  43    REGCACHE.  If REGNUM is -1, do this for all registers in REGSET.  */
  44
  45 void
  46 ppcobsd_supply_gregset (const struct regset *regset,
  47                         struct regcache *regcache, int regnum,
  48                         const void *gregs, size_t len)
  49 {
  50   /* FIXME: jimb/2004-05-05: Some PPC variants don't have
  51      floating-point registers.  For such variants,
  52      tdep->ppc_fp0_regnum and tdep->ppc_fpscr_regnum will be -1.  I
  53      don't think OpenBSD runs on any of those chips, but we can at
  54      least make sure that if someone tries it, they'll get a proper
  55      notification.  */
  56   gdb_assert (ppc_floating_point_unit_p (current_gdbarch));
  57
  58   ppc_supply_gregset (regset, regcache, regnum, gregs, len);
  59   ppc_supply_fpregset (regset, regcache, regnum, gregs, len);
  60 }
  61
  62 /* Collect register REGNUM in the general-purpose register set
  63    REGSET. from register cache REGCACHE into the buffer specified by
  64    GREGS and LEN.  If REGNUM is -1, do this for all registers in
  65    REGSET.  */
  66
  67 void
  68 ppcobsd_collect_gregset (const struct regset *regset,
  69                          const struct regcache *regcache, int regnum,
  70                          void *gregs, size_t len)
  71 {
  72   /* FIXME: jimb/2004-05-05: Some PPC variants don't have
  73      floating-point registers.  For such variants,
  74      tdep->ppc_fp0_regnum and tdep->ppc_fpscr_regnum will be -1.  I
  75      don't think OpenBSD runs on any of those chips, but we can at
  76      least make sure that if someone tries it, they'll get a proper
  77      notification.  */
  78   gdb_assert (ppc_floating_point_unit_p (current_gdbarch));
  79
  80   ppc_collect_gregset (regset, regcache, regnum, gregs, len);
  81   ppc_collect_fpregset (regset, regcache, regnum, gregs, len);
  82 }
  83
  84 /* OpenBS/powerpc register set.  */
  85
  86 struct regset ppcobsd_gregset =
  87 {
  88   &ppcobsd_reg_offsets,
  89   ppcobsd_supply_gregset
  90 };
  91
  92 /* Return the appropriate register set for the core section identified
  93    by SECT_NAME and SECT_SIZE.  */
  94
  95 static const struct regset *
  96 ppcobsd_regset_from_core_section (struct gdbarch *gdbarch,
  97                                   const char *sect_name, size_t sect_size)
  98 {
  99   if (strcmp (sect_name, ".reg") == 0 && sect_size >= 412)
 100     return &ppcobsd_gregset;
 101
 102   return NULL;
 103 }
 104 \f
 105
 106 static void
 107 ppcobsd_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
 108 {
 109   /* OpenBSD uses SVR4-style shared libraries.  */
 110   set_gdbarch_in_solib_call_trampoline
 111     (gdbarch, generic_in_solib_call_trampoline);
 112   set_solib_svr4_fetch_link_map_offsets
 113     (gdbarch, svr4_ilp32_fetch_link_map_offsets);
 114
 115   set_gdbarch_regset_from_core_section
 116     (gdbarch, ppcobsd_regset_from_core_section);
 117 }
 118 \f
 119
 120 /* OpenBSD uses uses the traditional NetBSD core file format, even for
 121    ports that use ELF.  */
 122 #define GDB_OSABI_NETBSD_CORE GDB_OSABI_OPENBSD_ELF
 123
 124 static enum gdb_osabi
 125 ppcobsd_core_osabi_sniffer (bfd *abfd)
 126 {
 127   if (strcmp (bfd_get_target (abfd), "netbsd-core") == 0)
 128     return GDB_OSABI_NETBSD_CORE;
 129
 130   return GDB_OSABI_UNKNOWN;
 131 }
 132 \f
 133
 134 /* Provide a prototype to silence -Wmissing-prototypes.  */
 135 void _initialize_ppcobsd_tdep (void);
 136
 137 void
 138 _initialize_ppcobsd_tdep (void)
 139 {
 140   /* BFD doesn't set a flavour for NetBSD style a.out core files.  */
 141   gdbarch_register_osabi_sniffer (bfd_arch_powerpc, bfd_target_unknown_flavour,
 142                                   ppcobsd_core_osabi_sniffer);
 143
 144   gdbarch_register_osabi (bfd_arch_powerpc, 0, GDB_OSABI_OPENBSD_ELF,
 145                           ppcobsd_init_abi);
 146
 147   /* Avoid initializing the register offsets again if they were
 148      already initailized by ppcobsd-nat.c.  */
 149   if (ppcobsd_reg_offsets.pc_offset == 0)
 150     {
 151       /* General-purpose registers.  */
 152       ppcobsd_reg_offsets.r0_offset = 0;
 153       ppcobsd_reg_offsets.pc_offset = 384;
 154       ppcobsd_reg_offsets.ps_offset = 388;
 155       ppcobsd_reg_offsets.cr_offset = 392;
 156       ppcobsd_reg_offsets.lr_offset = 396;
 157       ppcobsd_reg_offsets.ctr_offset = 400;
 158       ppcobsd_reg_offsets.xer_offset = 404;
 159       ppcobsd_reg_offsets.mq_offset = 408;
 160
 161       /* Floating-point registers.  */
 162       ppcobsd_reg_offsets.f0_offset = 128;
 163       ppcobsd_reg_offsets.fpscr_offset = -1;
 164
 165       /* AltiVec registers.  */
 166       ppcobsd_reg_offsets.vr0_offset = 0;
 167       ppcobsd_reg_offsets.vscr_offset = 512;
 168       ppcobsd_reg_offsets.vrsave_offset = 520;
 169     }
 170 }