1 /* Target-dependent code for the RISC-V architecture, for GDB.
3 Copyright (C) 2018-2023 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
32 #include "arch-utils.h"
35 #include "riscv-tdep.h"
37 #include "reggroups.h"
38 #include "opcode/riscv.h"
39 #include "elf/riscv.h"
43 #include "frame-unwind.h"
44 #include "frame-base.h"
45 #include "trad-frame.h"
47 #include "floatformat.h"
49 #include "target-descriptions.h"
50 #include "dwarf2/frame.h"
51 #include "user-regs.h"
53 #include "gdbsupport/common-defs.h"
54 #include "opcode/riscv-opc.h"
55 #include "cli/cli-decode.h"
56 #include "observable.h"
57 #include "prologue-value.h"
58 #include "arch/riscv.h"
59 #include "riscv-ravenscar-thread.h"
61 /* The stack must be 16-byte aligned. */
62 #define SP_ALIGNMENT 16
64 /* The biggest alignment that the target supports. */
65 #define BIGGEST_ALIGNMENT 16
67 /* Define a series of is_XXX_insn functions to check if the value INSN
68 is an instance of instruction XXX. */
69 #define DECLARE_INSN(INSN_NAME, INSN_MATCH, INSN_MASK) \
70 static inline bool is_ ## INSN_NAME ## _insn (long insn) \
72 return (insn & INSN_MASK) == INSN_MATCH; \
74 #include "opcode/riscv-opc.h"
77 /* When this is set to non-zero debugging information about breakpoint
78 kinds will be printed. */
80 static unsigned int riscv_debug_breakpoints
= 0;
82 /* When this is set to non-zero debugging information about inferior calls
85 static unsigned int riscv_debug_infcall
= 0;
87 /* When this is set to non-zero debugging information about stack unwinding
90 static unsigned int riscv_debug_unwinder
= 0;
92 /* When this is set to non-zero debugging information about gdbarch
93 initialisation will be printed. */
95 static unsigned int riscv_debug_gdbarch
= 0;
97 /* The names of the RISC-V target description features. */
98 const char *riscv_feature_name_csr
= "org.gnu.gdb.riscv.csr";
99 static const char *riscv_feature_name_cpu
= "org.gnu.gdb.riscv.cpu";
100 static const char *riscv_feature_name_fpu
= "org.gnu.gdb.riscv.fpu";
101 static const char *riscv_feature_name_virtual
= "org.gnu.gdb.riscv.virtual";
102 static const char *riscv_feature_name_vector
= "org.gnu.gdb.riscv.vector";
104 /* The current set of options to be passed to the disassembler. */
105 static char *riscv_disassembler_options
;
107 /* Cached information about a frame. */
109 struct riscv_unwind_cache
111 /* The register from which we can calculate the frame base. This is
112 usually $sp or $fp. */
115 /* The offset from the current value in register FRAME_BASE_REG to the
116 actual frame base address. */
117 int frame_base_offset
;
119 /* Information about previous register values. */
120 trad_frame_saved_reg
*regs
;
122 /* The id for this frame. */
123 struct frame_id this_id
;
125 /* The base (stack) address for this frame. This is the stack pointer
126 value on entry to this frame before any adjustments are made. */
127 CORE_ADDR frame_base
;
130 /* RISC-V specific register group for CSRs. */
132 static const reggroup
*csr_reggroup
= nullptr;
134 /* Callback function for user_reg_add. */
136 static struct value
*
137 value_of_riscv_user_reg (frame_info_ptr frame
, const void *baton
)
139 const int *reg_p
= (const int *) baton
;
140 return value_of_register (*reg_p
, frame
);
143 /* Information about a register alias that needs to be set up for this
144 target. These are collected when the target's XML description is
145 analysed, and then processed later, once the gdbarch has been created. */
147 class riscv_pending_register_alias
152 riscv_pending_register_alias (const char *name
, const void *baton
)
157 /* Convert this into a user register for GDBARCH. */
159 void create (struct gdbarch
*gdbarch
) const
161 user_reg_add (gdbarch
, m_name
, value_of_riscv_user_reg
, m_baton
);
165 /* The name for this alias. */
168 /* The baton value for passing to user_reg_add. This must point to some
169 data that will live for at least as long as the gdbarch object to
170 which the user register is attached. */
174 /* A set of registers that we expect to find in a tdesc_feature. These
175 are use in RISCV_GDBARCH_INIT when processing the target description. */
177 struct riscv_register_feature
179 explicit riscv_register_feature (const char *feature_name
)
180 : m_feature_name (feature_name
)
183 riscv_register_feature () = delete;
184 DISABLE_COPY_AND_ASSIGN (riscv_register_feature
);
186 /* Information for a single register. */
189 /* The GDB register number for this register. */
192 /* List of names for this register. The first name in this list is the
193 preferred name, the name GDB should use when describing this
195 std::vector
<const char *> names
;
197 /* Look in FEATURE for a register with a name from this classes names
198 list. If the register is found then register its number with
199 TDESC_DATA and add all its aliases to the ALIASES list.
200 PREFER_FIRST_NAME_P is used when deciding which aliases to create. */
201 bool check (struct tdesc_arch_data
*tdesc_data
,
202 const struct tdesc_feature
*feature
,
203 bool prefer_first_name_p
,
204 std::vector
<riscv_pending_register_alias
> *aliases
) const;
207 /* Return the name of this feature. */
208 const char *name () const
209 { return m_feature_name
; }
213 /* Return a target description feature extracted from TDESC for this
214 register feature. Will return nullptr if there is no feature in TDESC
215 with the name M_FEATURE_NAME. */
216 const struct tdesc_feature
*tdesc_feature (const struct target_desc
*tdesc
) const
218 return tdesc_find_feature (tdesc
, name ());
221 /* List of all the registers that we expect that we might find in this
223 std::vector
<struct register_info
> m_registers
;
227 /* The name for this feature. This is the name used to find this feature
228 within the target description. */
229 const char *m_feature_name
;
232 /* See description in the class declaration above. */
235 riscv_register_feature::register_info::check
236 (struct tdesc_arch_data
*tdesc_data
,
237 const struct tdesc_feature
*feature
,
238 bool prefer_first_name_p
,
239 std::vector
<riscv_pending_register_alias
> *aliases
) const
241 for (const char *name
: this->names
)
243 bool found
= tdesc_numbered_register (feature
, tdesc_data
,
247 /* We know that the target description mentions this
248 register. In RISCV_REGISTER_NAME we ensure that GDB
249 always uses the first name for each register, so here we
250 add aliases for all of the remaining names. */
251 int start_index
= prefer_first_name_p
? 1 : 0;
252 for (int i
= start_index
; i
< this->names
.size (); ++i
)
254 const char *alias
= this->names
[i
];
255 if (alias
== name
&& !prefer_first_name_p
)
257 aliases
->emplace_back (alias
, (void *) &this->regnum
);
265 /* Class representing the x-registers feature set. */
267 struct riscv_xreg_feature
: public riscv_register_feature
269 riscv_xreg_feature ()
270 : riscv_register_feature (riscv_feature_name_cpu
)
273 { RISCV_ZERO_REGNUM
+ 0, { "zero", "x0" } },
274 { RISCV_ZERO_REGNUM
+ 1, { "ra", "x1" } },
275 { RISCV_ZERO_REGNUM
+ 2, { "sp", "x2" } },
276 { RISCV_ZERO_REGNUM
+ 3, { "gp", "x3" } },
277 { RISCV_ZERO_REGNUM
+ 4, { "tp", "x4" } },
278 { RISCV_ZERO_REGNUM
+ 5, { "t0", "x5" } },
279 { RISCV_ZERO_REGNUM
+ 6, { "t1", "x6" } },
280 { RISCV_ZERO_REGNUM
+ 7, { "t2", "x7" } },
281 { RISCV_ZERO_REGNUM
+ 8, { "fp", "x8", "s0" } },
282 { RISCV_ZERO_REGNUM
+ 9, { "s1", "x9" } },
283 { RISCV_ZERO_REGNUM
+ 10, { "a0", "x10" } },
284 { RISCV_ZERO_REGNUM
+ 11, { "a1", "x11" } },
285 { RISCV_ZERO_REGNUM
+ 12, { "a2", "x12" } },
286 { RISCV_ZERO_REGNUM
+ 13, { "a3", "x13" } },
287 { RISCV_ZERO_REGNUM
+ 14, { "a4", "x14" } },
288 { RISCV_ZERO_REGNUM
+ 15, { "a5", "x15" } },
289 { RISCV_ZERO_REGNUM
+ 16, { "a6", "x16" } },
290 { RISCV_ZERO_REGNUM
+ 17, { "a7", "x17" } },
291 { RISCV_ZERO_REGNUM
+ 18, { "s2", "x18" } },
292 { RISCV_ZERO_REGNUM
+ 19, { "s3", "x19" } },
293 { RISCV_ZERO_REGNUM
+ 20, { "s4", "x20" } },
294 { RISCV_ZERO_REGNUM
+ 21, { "s5", "x21" } },
295 { RISCV_ZERO_REGNUM
+ 22, { "s6", "x22" } },
296 { RISCV_ZERO_REGNUM
+ 23, { "s7", "x23" } },
297 { RISCV_ZERO_REGNUM
+ 24, { "s8", "x24" } },
298 { RISCV_ZERO_REGNUM
+ 25, { "s9", "x25" } },
299 { RISCV_ZERO_REGNUM
+ 26, { "s10", "x26" } },
300 { RISCV_ZERO_REGNUM
+ 27, { "s11", "x27" } },
301 { RISCV_ZERO_REGNUM
+ 28, { "t3", "x28" } },
302 { RISCV_ZERO_REGNUM
+ 29, { "t4", "x29" } },
303 { RISCV_ZERO_REGNUM
+ 30, { "t5", "x30" } },
304 { RISCV_ZERO_REGNUM
+ 31, { "t6", "x31" } },
305 { RISCV_ZERO_REGNUM
+ 32, { "pc" } }
309 /* Return the preferred name for the register with gdb register number
310 REGNUM, which must be in the inclusive range RISCV_ZERO_REGNUM to
312 const char *register_name (int regnum
) const
314 gdb_assert (regnum
>= RISCV_ZERO_REGNUM
&& regnum
<= m_registers
.size ());
315 return m_registers
[regnum
].names
[0];
318 /* Check this feature within TDESC, record the registers from this
319 feature into TDESC_DATA and update ALIASES and FEATURES. */
320 bool check (const struct target_desc
*tdesc
,
321 struct tdesc_arch_data
*tdesc_data
,
322 std::vector
<riscv_pending_register_alias
> *aliases
,
323 struct riscv_gdbarch_features
*features
) const
325 const struct tdesc_feature
*feature_cpu
= tdesc_feature (tdesc
);
327 if (feature_cpu
== nullptr)
330 bool seen_an_optional_reg_p
= false;
331 for (const auto ®
: m_registers
)
333 bool found
= reg
.check (tdesc_data
, feature_cpu
, true, aliases
);
335 bool is_optional_reg_p
= (reg
.regnum
>= RISCV_ZERO_REGNUM
+ 16
336 && reg
.regnum
< RISCV_ZERO_REGNUM
+ 32);
338 if (!found
&& (!is_optional_reg_p
|| seen_an_optional_reg_p
))
340 else if (found
&& is_optional_reg_p
)
341 seen_an_optional_reg_p
= true;
344 /* Check that all of the core cpu registers have the same bitsize. */
345 int xlen_bitsize
= tdesc_register_bitsize (feature_cpu
, "pc");
348 for (auto &tdesc_reg
: feature_cpu
->registers
)
349 valid_p
&= (tdesc_reg
->bitsize
== xlen_bitsize
);
351 features
->xlen
= (xlen_bitsize
/ 8);
352 features
->embedded
= !seen_an_optional_reg_p
;
358 /* An instance of the x-register feature set. */
360 static const struct riscv_xreg_feature riscv_xreg_feature
;
362 /* Class representing the f-registers feature set. */
364 struct riscv_freg_feature
: public riscv_register_feature
366 riscv_freg_feature ()
367 : riscv_register_feature (riscv_feature_name_fpu
)
370 { RISCV_FIRST_FP_REGNUM
+ 0, { "ft0", "f0" } },
371 { RISCV_FIRST_FP_REGNUM
+ 1, { "ft1", "f1" } },
372 { RISCV_FIRST_FP_REGNUM
+ 2, { "ft2", "f2" } },
373 { RISCV_FIRST_FP_REGNUM
+ 3, { "ft3", "f3" } },
374 { RISCV_FIRST_FP_REGNUM
+ 4, { "ft4", "f4" } },
375 { RISCV_FIRST_FP_REGNUM
+ 5, { "ft5", "f5" } },
376 { RISCV_FIRST_FP_REGNUM
+ 6, { "ft6", "f6" } },
377 { RISCV_FIRST_FP_REGNUM
+ 7, { "ft7", "f7" } },
378 { RISCV_FIRST_FP_REGNUM
+ 8, { "fs0", "f8" } },
379 { RISCV_FIRST_FP_REGNUM
+ 9, { "fs1", "f9" } },
380 { RISCV_FIRST_FP_REGNUM
+ 10, { "fa0", "f10" } },
381 { RISCV_FIRST_FP_REGNUM
+ 11, { "fa1", "f11" } },
382 { RISCV_FIRST_FP_REGNUM
+ 12, { "fa2", "f12" } },
383 { RISCV_FIRST_FP_REGNUM
+ 13, { "fa3", "f13" } },
384 { RISCV_FIRST_FP_REGNUM
+ 14, { "fa4", "f14" } },
385 { RISCV_FIRST_FP_REGNUM
+ 15, { "fa5", "f15" } },
386 { RISCV_FIRST_FP_REGNUM
+ 16, { "fa6", "f16" } },
387 { RISCV_FIRST_FP_REGNUM
+ 17, { "fa7", "f17" } },
388 { RISCV_FIRST_FP_REGNUM
+ 18, { "fs2", "f18" } },
389 { RISCV_FIRST_FP_REGNUM
+ 19, { "fs3", "f19" } },
390 { RISCV_FIRST_FP_REGNUM
+ 20, { "fs4", "f20" } },
391 { RISCV_FIRST_FP_REGNUM
+ 21, { "fs5", "f21" } },
392 { RISCV_FIRST_FP_REGNUM
+ 22, { "fs6", "f22" } },
393 { RISCV_FIRST_FP_REGNUM
+ 23, { "fs7", "f23" } },
394 { RISCV_FIRST_FP_REGNUM
+ 24, { "fs8", "f24" } },
395 { RISCV_FIRST_FP_REGNUM
+ 25, { "fs9", "f25" } },
396 { RISCV_FIRST_FP_REGNUM
+ 26, { "fs10", "f26" } },
397 { RISCV_FIRST_FP_REGNUM
+ 27, { "fs11", "f27" } },
398 { RISCV_FIRST_FP_REGNUM
+ 28, { "ft8", "f28" } },
399 { RISCV_FIRST_FP_REGNUM
+ 29, { "ft9", "f29" } },
400 { RISCV_FIRST_FP_REGNUM
+ 30, { "ft10", "f30" } },
401 { RISCV_FIRST_FP_REGNUM
+ 31, { "ft11", "f31" } },
402 { RISCV_CSR_FFLAGS_REGNUM
, { "fflags", "csr1" } },
403 { RISCV_CSR_FRM_REGNUM
, { "frm", "csr2" } },
404 { RISCV_CSR_FCSR_REGNUM
, { "fcsr", "csr3" } },
408 /* Return the preferred name for the register with gdb register number
409 REGNUM, which must be in the inclusive range RISCV_FIRST_FP_REGNUM to
410 RISCV_LAST_FP_REGNUM. */
411 const char *register_name (int regnum
) const
413 gdb_static_assert (RISCV_LAST_FP_REGNUM
== RISCV_FIRST_FP_REGNUM
+ 31);
414 gdb_assert (regnum
>= RISCV_FIRST_FP_REGNUM
415 && regnum
<= RISCV_LAST_FP_REGNUM
);
416 regnum
-= RISCV_FIRST_FP_REGNUM
;
417 return m_registers
[regnum
].names
[0];
420 /* Check this feature within TDESC, record the registers from this
421 feature into TDESC_DATA and update ALIASES and FEATURES. */
422 bool check (const struct target_desc
*tdesc
,
423 struct tdesc_arch_data
*tdesc_data
,
424 std::vector
<riscv_pending_register_alias
> *aliases
,
425 struct riscv_gdbarch_features
*features
) const
427 const struct tdesc_feature
*feature_fpu
= tdesc_feature (tdesc
);
429 /* It's fine if this feature is missing. Update the architecture
430 feature set and return. */
431 if (feature_fpu
== nullptr)
437 /* Check all of the floating pointer registers are present. We also
438 check that the floating point CSRs are present too, though if these
439 are missing this is not fatal. */
440 for (const auto ®
: m_registers
)
442 bool found
= reg
.check (tdesc_data
, feature_fpu
, true, aliases
);
444 bool is_ctrl_reg_p
= reg
.regnum
> RISCV_LAST_FP_REGNUM
;
446 if (!found
&& !is_ctrl_reg_p
)
450 /* Look through all of the floating point registers (not the FP CSRs
451 though), and check they all have the same bitsize. Use this bitsize
452 to update the feature set for this gdbarch. */
454 for (const auto ®
: m_registers
)
456 /* Stop once we get to the CSRs which are at the end of the
458 if (reg
.regnum
> RISCV_LAST_FP_REGNUM
)
461 int reg_bitsize
= -1;
462 for (const char *name
: reg
.names
)
464 if (tdesc_unnumbered_register (feature_fpu
, name
))
466 reg_bitsize
= tdesc_register_bitsize (feature_fpu
, name
);
470 gdb_assert (reg_bitsize
!= -1);
471 if (fp_bitsize
== -1)
472 fp_bitsize
= reg_bitsize
;
473 else if (fp_bitsize
!= reg_bitsize
)
477 features
->flen
= (fp_bitsize
/ 8);
482 /* An instance of the f-register feature set. */
484 static const struct riscv_freg_feature riscv_freg_feature
;
486 /* Class representing the virtual registers. These are not physical
487 registers on the hardware, but might be available from the target.
488 These are not pseudo registers, reading these really does result in a
489 register read from the target, it is just that there might not be a
490 physical register backing the result. */
492 struct riscv_virtual_feature
: public riscv_register_feature
494 riscv_virtual_feature ()
495 : riscv_register_feature (riscv_feature_name_virtual
)
498 { RISCV_PRIV_REGNUM
, { "priv" } }
502 bool check (const struct target_desc
*tdesc
,
503 struct tdesc_arch_data
*tdesc_data
,
504 std::vector
<riscv_pending_register_alias
> *aliases
,
505 struct riscv_gdbarch_features
*features
) const
507 const struct tdesc_feature
*feature_virtual
= tdesc_feature (tdesc
);
509 /* It's fine if this feature is missing. */
510 if (feature_virtual
== nullptr)
513 /* We don't check the return value from the call to check here, all the
514 registers in this feature are optional. */
515 for (const auto ®
: m_registers
)
516 reg
.check (tdesc_data
, feature_virtual
, true, aliases
);
522 /* An instance of the virtual register feature. */
524 static const struct riscv_virtual_feature riscv_virtual_feature
;
526 /* Class representing the CSR feature. */
528 struct riscv_csr_feature
: public riscv_register_feature
531 : riscv_register_feature (riscv_feature_name_csr
)
534 #define DECLARE_CSR(NAME,VALUE,CLASS,DEFINE_VER,ABORT_VER) \
535 { RISCV_ ## VALUE ## _REGNUM, { # NAME } },
536 #include "opcode/riscv-opc.h"
539 riscv_create_csr_aliases ();
542 bool check (const struct target_desc
*tdesc
,
543 struct tdesc_arch_data
*tdesc_data
,
544 std::vector
<riscv_pending_register_alias
> *aliases
,
545 struct riscv_gdbarch_features
*features
) const
547 const struct tdesc_feature
*feature_csr
= tdesc_feature (tdesc
);
549 /* It's fine if this feature is missing. */
550 if (feature_csr
== nullptr)
553 /* We don't check the return value from the call to check here, all the
554 registers in this feature are optional. */
555 for (const auto ®
: m_registers
)
556 reg
.check (tdesc_data
, feature_csr
, true, aliases
);
563 /* Complete RISCV_CSR_FEATURE, building the CSR alias names and adding them
564 to the name list for each register. */
567 riscv_create_csr_aliases ()
569 for (auto ®
: m_registers
)
571 int csr_num
= reg
.regnum
- RISCV_FIRST_CSR_REGNUM
;
572 gdb::unique_xmalloc_ptr
<char> alias
= xstrprintf ("csr%d", csr_num
);
573 reg
.names
.push_back (alias
.release ());
578 /* An instance of the csr register feature. */
580 static const struct riscv_csr_feature riscv_csr_feature
;
582 /* Class representing the v-registers feature set. */
584 struct riscv_vector_feature
: public riscv_register_feature
586 riscv_vector_feature ()
587 : riscv_register_feature (riscv_feature_name_vector
)
590 { RISCV_V0_REGNUM
+ 0, { "v0" } },
591 { RISCV_V0_REGNUM
+ 1, { "v1" } },
592 { RISCV_V0_REGNUM
+ 2, { "v2" } },
593 { RISCV_V0_REGNUM
+ 3, { "v3" } },
594 { RISCV_V0_REGNUM
+ 4, { "v4" } },
595 { RISCV_V0_REGNUM
+ 5, { "v5" } },
596 { RISCV_V0_REGNUM
+ 6, { "v6" } },
597 { RISCV_V0_REGNUM
+ 7, { "v7" } },
598 { RISCV_V0_REGNUM
+ 8, { "v8" } },
599 { RISCV_V0_REGNUM
+ 9, { "v9" } },
600 { RISCV_V0_REGNUM
+ 10, { "v10" } },
601 { RISCV_V0_REGNUM
+ 11, { "v11" } },
602 { RISCV_V0_REGNUM
+ 12, { "v12" } },
603 { RISCV_V0_REGNUM
+ 13, { "v13" } },
604 { RISCV_V0_REGNUM
+ 14, { "v14" } },
605 { RISCV_V0_REGNUM
+ 15, { "v15" } },
606 { RISCV_V0_REGNUM
+ 16, { "v16" } },
607 { RISCV_V0_REGNUM
+ 17, { "v17" } },
608 { RISCV_V0_REGNUM
+ 18, { "v18" } },
609 { RISCV_V0_REGNUM
+ 19, { "v19" } },
610 { RISCV_V0_REGNUM
+ 20, { "v20" } },
611 { RISCV_V0_REGNUM
+ 21, { "v21" } },
612 { RISCV_V0_REGNUM
+ 22, { "v22" } },
613 { RISCV_V0_REGNUM
+ 23, { "v23" } },
614 { RISCV_V0_REGNUM
+ 24, { "v24" } },
615 { RISCV_V0_REGNUM
+ 25, { "v25" } },
616 { RISCV_V0_REGNUM
+ 26, { "v26" } },
617 { RISCV_V0_REGNUM
+ 27, { "v27" } },
618 { RISCV_V0_REGNUM
+ 28, { "v28" } },
619 { RISCV_V0_REGNUM
+ 29, { "v29" } },
620 { RISCV_V0_REGNUM
+ 30, { "v30" } },
621 { RISCV_V0_REGNUM
+ 31, { "v31" } },
625 /* Return the preferred name for the register with gdb register number
626 REGNUM, which must be in the inclusive range RISCV_V0_REGNUM to
627 RISCV_V0_REGNUM + 31. */
628 const char *register_name (int regnum
) const
630 gdb_assert (regnum
>= RISCV_V0_REGNUM
631 && regnum
<= RISCV_V0_REGNUM
+ 31);
632 regnum
-= RISCV_V0_REGNUM
;
633 return m_registers
[regnum
].names
[0];
636 /* Check this feature within TDESC, record the registers from this
637 feature into TDESC_DATA and update ALIASES and FEATURES. */
638 bool check (const struct target_desc
*tdesc
,
639 struct tdesc_arch_data
*tdesc_data
,
640 std::vector
<riscv_pending_register_alias
> *aliases
,
641 struct riscv_gdbarch_features
*features
) const
643 const struct tdesc_feature
*feature_vector
= tdesc_feature (tdesc
);
645 /* It's fine if this feature is missing. Update the architecture
646 feature set and return. */
647 if (feature_vector
== nullptr)
653 /* Check all of the vector registers are present. */
654 for (const auto ®
: m_registers
)
656 if (!reg
.check (tdesc_data
, feature_vector
, true, aliases
))
660 /* Look through all of the vector registers and check they all have the
661 same bitsize. Use this bitsize to update the feature set for this
663 int vector_bitsize
= -1;
664 for (const auto ®
: m_registers
)
666 int reg_bitsize
= -1;
667 for (const char *name
: reg
.names
)
669 if (tdesc_unnumbered_register (feature_vector
, name
))
671 reg_bitsize
= tdesc_register_bitsize (feature_vector
, name
);
675 gdb_assert (reg_bitsize
!= -1);
676 if (vector_bitsize
== -1)
677 vector_bitsize
= reg_bitsize
;
678 else if (vector_bitsize
!= reg_bitsize
)
682 features
->vlen
= (vector_bitsize
/ 8);
687 /* An instance of the v-register feature set. */
689 static const struct riscv_vector_feature riscv_vector_feature
;
691 /* Controls whether we place compressed breakpoints or not. When in auto
692 mode GDB tries to determine if the target supports compressed
693 breakpoints, and uses them if it does. */
695 static enum auto_boolean use_compressed_breakpoints
;
697 /* The show callback for 'show riscv use-compressed-breakpoints'. */
700 show_use_compressed_breakpoints (struct ui_file
*file
, int from_tty
,
701 struct cmd_list_element
*c
,
705 _("Debugger's use of compressed breakpoints is set "
709 /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
711 static struct cmd_list_element
*setriscvcmdlist
= NULL
;
712 static struct cmd_list_element
*showriscvcmdlist
= NULL
;
714 /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
716 static struct cmd_list_element
*setdebugriscvcmdlist
= NULL
;
717 static struct cmd_list_element
*showdebugriscvcmdlist
= NULL
;
719 /* The show callback for all 'show debug riscv VARNAME' variables. */
722 show_riscv_debug_variable (struct ui_file
*file
, int from_tty
,
723 struct cmd_list_element
*c
,
727 _("RiscV debug variable `%s' is set to: %s\n"),
731 /* See riscv-tdep.h. */
734 riscv_isa_xlen (struct gdbarch
*gdbarch
)
736 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
737 return tdep
->isa_features
.xlen
;
740 /* See riscv-tdep.h. */
743 riscv_abi_xlen (struct gdbarch
*gdbarch
)
745 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
746 return tdep
->abi_features
.xlen
;
749 /* See riscv-tdep.h. */
752 riscv_isa_flen (struct gdbarch
*gdbarch
)
754 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
755 return tdep
->isa_features
.flen
;
758 /* See riscv-tdep.h. */
761 riscv_abi_flen (struct gdbarch
*gdbarch
)
763 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
764 return tdep
->abi_features
.flen
;
767 /* See riscv-tdep.h. */
770 riscv_abi_embedded (struct gdbarch
*gdbarch
)
772 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
773 return tdep
->abi_features
.embedded
;
776 /* Return true if the target for GDBARCH has floating point hardware. */
779 riscv_has_fp_regs (struct gdbarch
*gdbarch
)
781 return (riscv_isa_flen (gdbarch
) > 0);
784 /* Return true if GDBARCH is using any of the floating point hardware ABIs. */
787 riscv_has_fp_abi (struct gdbarch
*gdbarch
)
789 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
790 return tdep
->abi_features
.flen
> 0;
793 /* Return true if REGNO is a floating pointer register. */
796 riscv_is_fp_regno_p (int regno
)
798 return (regno
>= RISCV_FIRST_FP_REGNUM
799 && regno
<= RISCV_LAST_FP_REGNUM
);
802 /* Implement the breakpoint_kind_from_pc gdbarch method. */
805 riscv_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
807 if (use_compressed_breakpoints
== AUTO_BOOLEAN_AUTO
)
809 bool unaligned_p
= false;
812 /* Some targets don't support unaligned reads. The address can only
813 be unaligned if the C extension is supported. So it is safe to
814 use a compressed breakpoint in this case. */
819 /* Read the opcode byte to determine the instruction length. If
820 the read fails this may be because we tried to set the
821 breakpoint at an invalid address, in this case we provide a
822 fake result which will give a breakpoint length of 4.
823 Hopefully when we try to actually insert the breakpoint we
824 will see a failure then too which will be reported to the
826 if (target_read_code (*pcptr
, buf
, 1) == -1)
830 if (riscv_debug_breakpoints
)
832 const char *bp
= (unaligned_p
|| riscv_insn_length (buf
[0]) == 2
833 ? "C.EBREAK" : "EBREAK");
835 gdb_printf (gdb_stdlog
, "Using %s for breakpoint at %s ",
836 bp
, paddress (gdbarch
, *pcptr
));
838 gdb_printf (gdb_stdlog
, "(unaligned address)\n");
840 gdb_printf (gdb_stdlog
, "(instruction length %d)\n",
841 riscv_insn_length (buf
[0]));
843 if (unaligned_p
|| riscv_insn_length (buf
[0]) == 2)
848 else if (use_compressed_breakpoints
== AUTO_BOOLEAN_TRUE
)
854 /* Implement the sw_breakpoint_from_kind gdbarch method. */
856 static const gdb_byte
*
857 riscv_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
859 static const gdb_byte ebreak
[] = { 0x73, 0x00, 0x10, 0x00, };
860 static const gdb_byte c_ebreak
[] = { 0x02, 0x90 };
870 gdb_assert_not_reached ("unhandled breakpoint kind");
874 /* Implement the register_name gdbarch method. This is used instead of
875 the function supplied by calling TDESC_USE_REGISTERS so that we can
876 ensure the preferred names are offered for x-regs and f-regs. */
879 riscv_register_name (struct gdbarch
*gdbarch
, int regnum
)
881 /* Lookup the name through the target description. If we get back NULL
882 then this is an unknown register. If we do get a name back then we
883 look up the registers preferred name below. */
884 const char *name
= tdesc_register_name (gdbarch
, regnum
);
885 gdb_assert (name
!= nullptr);
889 /* We want GDB to use the ABI names for registers even if the target
890 gives us a target description with the architectural name. For
891 example we want to see 'ra' instead of 'x1' whatever the target
892 description called it. */
893 if (regnum
>= RISCV_ZERO_REGNUM
&& regnum
< RISCV_FIRST_FP_REGNUM
)
894 return riscv_xreg_feature
.register_name (regnum
);
896 /* Like with the x-regs we prefer the abi names for the floating point
897 registers. If the target doesn't have floating point registers then
898 the tdesc_register_name call above should have returned an empty
900 if (regnum
>= RISCV_FIRST_FP_REGNUM
&& regnum
<= RISCV_LAST_FP_REGNUM
)
902 gdb_assert (riscv_has_fp_regs (gdbarch
));
903 return riscv_freg_feature
.register_name (regnum
);
906 /* Some targets (QEMU) are reporting these three registers twice, once
907 in the FPU feature, and once in the CSR feature. Both of these read
908 the same underlying state inside the target, but naming the register
909 twice in the target description results in GDB having two registers
910 with the same name, only one of which can ever be accessed, but both
911 will show up in 'info register all'. Unless, we identify the
912 duplicate copies of these registers (in riscv_tdesc_unknown_reg) and
913 then hide the registers here by giving them no name. */
914 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
915 if (tdep
->duplicate_fflags_regnum
== regnum
916 || tdep
->duplicate_frm_regnum
== regnum
917 || tdep
->duplicate_fcsr_regnum
== regnum
)
920 /* The remaining registers are different. For all other registers on the
921 machine we prefer to see the names that the target description
922 provides. This is particularly important for CSRs which might be
923 renamed over time. If GDB keeps track of the "latest" name, but a
924 particular target provides an older name then we don't want to force
925 users to see the newer name in register output.
927 The other case that reaches here are any registers that the target
928 provided that GDB is completely unaware of. For these we have no
929 choice but to accept the target description name.
931 Just accept whatever name TDESC_REGISTER_NAME returned. */
935 /* Implement gdbarch_pseudo_register_read. Read pseudo-register REGNUM
936 from REGCACHE and place the register value into BUF. BUF is sized
937 based on the type of register REGNUM, all of BUF should be written too,
938 the result should be sign or zero extended as appropriate. */
940 static enum register_status
941 riscv_pseudo_register_read (struct gdbarch
*gdbarch
,
942 readable_regcache
*regcache
,
943 int regnum
, gdb_byte
*buf
)
945 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
947 if (regnum
== tdep
->fflags_regnum
|| regnum
== tdep
->frm_regnum
)
950 memset (buf
, 0, register_size (gdbarch
, regnum
));
952 /* Read the first byte of the fcsr register, this contains both frm
954 enum register_status status
955 = regcache
->raw_read_part (RISCV_CSR_FCSR_REGNUM
, 0, 1, buf
);
957 if (status
!= REG_VALID
)
960 /* Extract the appropriate parts. */
961 if (regnum
== tdep
->fflags_regnum
)
963 else if (regnum
== tdep
->frm_regnum
)
964 buf
[0] = (buf
[0] >> 5) & 0x7;
972 /* Implement gdbarch_pseudo_register_write. Write the contents of BUF into
973 pseudo-register REGNUM in REGCACHE. BUF is sized based on the type of
977 riscv_pseudo_register_write (struct gdbarch
*gdbarch
,
978 struct regcache
*regcache
, int regnum
,
981 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
983 if (regnum
== tdep
->fflags_regnum
|| regnum
== tdep
->frm_regnum
)
985 int fcsr_regnum
= RISCV_CSR_FCSR_REGNUM
;
986 gdb_byte raw_buf
[register_size (gdbarch
, fcsr_regnum
)];
988 regcache
->raw_read (fcsr_regnum
, raw_buf
);
990 if (regnum
== tdep
->fflags_regnum
)
991 raw_buf
[0] = (raw_buf
[0] & ~0x1f) | (buf
[0] & 0x1f);
992 else if (regnum
== tdep
->frm_regnum
)
993 raw_buf
[0] = (raw_buf
[0] & ~(0x7 << 5)) | ((buf
[0] & 0x7) << 5);
995 regcache
->raw_write (fcsr_regnum
, raw_buf
);
998 gdb_assert_not_reached ("unknown pseudo register %d", regnum
);
1001 /* Implement the cannot_store_register gdbarch method. The zero register
1002 (x0) is read-only on RISC-V. */
1005 riscv_cannot_store_register (struct gdbarch
*gdbarch
, int regnum
)
1007 return regnum
== RISCV_ZERO_REGNUM
;
1010 /* Construct a type for 64-bit FP registers. */
1012 static struct type
*
1013 riscv_fpreg_d_type (struct gdbarch
*gdbarch
)
1015 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
1017 if (tdep
->riscv_fpreg_d_type
== nullptr)
1019 const struct builtin_type
*bt
= builtin_type (gdbarch
);
1021 /* The type we're building is this: */
1023 union __gdb_builtin_type_fpreg_d
1032 t
= arch_composite_type (gdbarch
,
1033 "__gdb_builtin_type_fpreg_d", TYPE_CODE_UNION
);
1034 append_composite_type_field (t
, "float", bt
->builtin_float
);
1035 append_composite_type_field (t
, "double", bt
->builtin_double
);
1036 t
->set_is_vector (true);
1037 t
->set_name ("builtin_type_fpreg_d");
1038 tdep
->riscv_fpreg_d_type
= t
;
1041 return tdep
->riscv_fpreg_d_type
;
1044 /* Implement the register_type gdbarch method. This is installed as an
1045 for the override setup by TDESC_USE_REGISTERS, for most registers we
1046 delegate the type choice to the target description, but for a few
1047 registers we try to improve the types if the target description has
1048 taken a simplistic approach. */
1050 static struct type
*
1051 riscv_register_type (struct gdbarch
*gdbarch
, int regnum
)
1053 struct type
*type
= tdesc_register_type (gdbarch
, regnum
);
1054 int xlen
= riscv_isa_xlen (gdbarch
);
1056 /* We want to perform some specific type "fixes" in cases where we feel
1057 that we really can do better than the target description. For all
1058 other cases we just return what the target description says. */
1059 if (riscv_is_fp_regno_p (regnum
))
1061 /* This spots the case for RV64 where the double is defined as
1062 either 'ieee_double' or 'float' (which is the generic name that
1063 converts to 'double' on 64-bit). In these cases its better to
1064 present the registers using a union type. */
1065 int flen
= riscv_isa_flen (gdbarch
);
1067 && type
->code () == TYPE_CODE_FLT
1068 && type
->length () == flen
1069 && (strcmp (type
->name (), "builtin_type_ieee_double") == 0
1070 || strcmp (type
->name (), "double") == 0))
1071 type
= riscv_fpreg_d_type (gdbarch
);
1074 if ((regnum
== gdbarch_pc_regnum (gdbarch
)
1075 || regnum
== RISCV_RA_REGNUM
1076 || regnum
== RISCV_FP_REGNUM
1077 || regnum
== RISCV_SP_REGNUM
1078 || regnum
== RISCV_GP_REGNUM
1079 || regnum
== RISCV_TP_REGNUM
)
1080 && type
->code () == TYPE_CODE_INT
1081 && type
->length () == xlen
)
1083 /* This spots the case where some interesting registers are defined
1084 as simple integers of the expected size, we force these registers
1085 to be pointers as we believe that is more useful. */
1086 if (regnum
== gdbarch_pc_regnum (gdbarch
)
1087 || regnum
== RISCV_RA_REGNUM
)
1088 type
= builtin_type (gdbarch
)->builtin_func_ptr
;
1089 else if (regnum
== RISCV_FP_REGNUM
1090 || regnum
== RISCV_SP_REGNUM
1091 || regnum
== RISCV_GP_REGNUM
1092 || regnum
== RISCV_TP_REGNUM
)
1093 type
= builtin_type (gdbarch
)->builtin_data_ptr
;
1099 /* Helper for riscv_print_registers_info, prints info for a single register
1103 riscv_print_one_register_info (struct gdbarch
*gdbarch
,
1104 struct ui_file
*file
,
1105 frame_info_ptr frame
,
1108 const char *name
= gdbarch_register_name (gdbarch
, regnum
);
1110 struct type
*regtype
;
1111 int print_raw_format
;
1112 enum tab_stops
{ value_column_1
= 15 };
1114 gdb_puts (name
, file
);
1115 print_spaces (value_column_1
- strlen (name
), file
);
1119 val
= value_of_register (regnum
, frame
);
1120 regtype
= value_type (val
);
1122 catch (const gdb_exception_error
&ex
)
1124 /* Handle failure to read a register without interrupting the entire
1125 'info registers' flow. */
1126 gdb_printf (file
, "%s\n", ex
.what ());
1130 print_raw_format
= (value_entirely_available (val
)
1131 && !value_optimized_out (val
));
1133 if (regtype
->code () == TYPE_CODE_FLT
1134 || (regtype
->code () == TYPE_CODE_UNION
1135 && regtype
->num_fields () == 2
1136 && regtype
->field (0).type ()->code () == TYPE_CODE_FLT
1137 && regtype
->field (1).type ()->code () == TYPE_CODE_FLT
)
1138 || (regtype
->code () == TYPE_CODE_UNION
1139 && regtype
->num_fields () == 3
1140 && regtype
->field (0).type ()->code () == TYPE_CODE_FLT
1141 && regtype
->field (1).type ()->code () == TYPE_CODE_FLT
1142 && regtype
->field (2).type ()->code () == TYPE_CODE_FLT
))
1144 struct value_print_options opts
;
1145 const gdb_byte
*valaddr
= value_contents_for_printing (val
).data ();
1146 enum bfd_endian byte_order
= type_byte_order (regtype
);
1148 get_user_print_options (&opts
);
1149 opts
.deref_ref
= true;
1151 common_val_print (val
, file
, 0, &opts
, current_language
);
1153 if (print_raw_format
)
1155 gdb_printf (file
, "\t(raw ");
1156 print_hex_chars (file
, valaddr
, regtype
->length (), byte_order
,
1158 gdb_printf (file
, ")");
1163 struct value_print_options opts
;
1164 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
1166 /* Print the register in hex. */
1167 get_formatted_print_options (&opts
, 'x');
1168 opts
.deref_ref
= true;
1169 common_val_print (val
, file
, 0, &opts
, current_language
);
1171 if (print_raw_format
)
1173 if (regnum
== RISCV_CSR_MSTATUS_REGNUM
)
1176 int size
= register_size (gdbarch
, regnum
);
1179 /* The SD field is always in the upper bit of MSTATUS, regardless
1180 of the number of bits in MSTATUS. */
1181 d
= value_as_long (val
);
1184 "\tSD:%X VM:%02X MXR:%X PUM:%X MPRV:%X XS:%X "
1185 "FS:%X MPP:%x HPP:%X SPP:%X MPIE:%X HPIE:%X "
1186 "SPIE:%X UPIE:%X MIE:%X HIE:%X SIE:%X UIE:%X",
1187 (int) ((d
>> (xlen
- 1)) & 0x1),
1188 (int) ((d
>> 24) & 0x1f),
1189 (int) ((d
>> 19) & 0x1),
1190 (int) ((d
>> 18) & 0x1),
1191 (int) ((d
>> 17) & 0x1),
1192 (int) ((d
>> 15) & 0x3),
1193 (int) ((d
>> 13) & 0x3),
1194 (int) ((d
>> 11) & 0x3),
1195 (int) ((d
>> 9) & 0x3),
1196 (int) ((d
>> 8) & 0x1),
1197 (int) ((d
>> 7) & 0x1),
1198 (int) ((d
>> 6) & 0x1),
1199 (int) ((d
>> 5) & 0x1),
1200 (int) ((d
>> 4) & 0x1),
1201 (int) ((d
>> 3) & 0x1),
1202 (int) ((d
>> 2) & 0x1),
1203 (int) ((d
>> 1) & 0x1),
1204 (int) ((d
>> 0) & 0x1));
1206 else if (regnum
== RISCV_CSR_MISA_REGNUM
)
1211 int size
= register_size (gdbarch
, regnum
);
1213 /* The MXL field is always in the upper two bits of MISA,
1214 regardless of the number of bits in MISA. Mask out other
1215 bits to ensure we have a positive value. */
1216 d
= value_as_long (val
);
1217 base
= (d
>> ((size
* 8) - 2)) & 0x3;
1220 for (; base
> 0; base
--)
1222 gdb_printf (file
, "\tRV%d", xlen
);
1224 for (i
= 0; i
< 26; i
++)
1227 gdb_printf (file
, "%c", 'A' + i
);
1230 else if (regnum
== RISCV_CSR_FCSR_REGNUM
1231 || regnum
== tdep
->fflags_regnum
1232 || regnum
== tdep
->frm_regnum
)
1234 LONGEST d
= value_as_long (val
);
1236 gdb_printf (file
, "\t");
1237 if (regnum
!= tdep
->frm_regnum
)
1239 "NV:%d DZ:%d OF:%d UF:%d NX:%d",
1240 (int) ((d
>> 4) & 0x1),
1241 (int) ((d
>> 3) & 0x1),
1242 (int) ((d
>> 2) & 0x1),
1243 (int) ((d
>> 1) & 0x1),
1244 (int) ((d
>> 0) & 0x1));
1246 if (regnum
!= tdep
->fflags_regnum
)
1248 static const char * const sfrm
[] =
1250 _("RNE (round to nearest; ties to even)"),
1251 _("RTZ (Round towards zero)"),
1252 _("RDN (Round down towards -INF)"),
1253 _("RUP (Round up towards +INF)"),
1254 _("RMM (Round to nearest; ties to max magnitude)"),
1257 /* A value of 0x7 indicates dynamic rounding mode when
1258 used within an instructions rounding-mode field, but
1259 is invalid within the FRM register. */
1260 _("INVALID[7] (Dynamic rounding mode)"),
1262 int frm
= ((regnum
== RISCV_CSR_FCSR_REGNUM
)
1263 ? (d
>> 5) : d
) & 0x7;
1265 gdb_printf (file
, "%sFRM:%i [%s]",
1266 (regnum
== RISCV_CSR_FCSR_REGNUM
1271 else if (regnum
== RISCV_PRIV_REGNUM
)
1276 d
= value_as_long (val
);
1281 static const char * const sprv
[] =
1288 gdb_printf (file
, "\tprv:%d [%s]",
1292 gdb_printf (file
, "\tprv:%d [INVALID]", priv
);
1296 /* If not a vector register, print it also according to its
1298 if (regtype
->is_vector () == 0)
1300 get_user_print_options (&opts
);
1301 opts
.deref_ref
= true;
1302 gdb_printf (file
, "\t");
1303 common_val_print (val
, file
, 0, &opts
, current_language
);
1308 gdb_printf (file
, "\n");
1311 /* Return true if REGNUM is a valid CSR register. The CSR register space
1312 is sparsely populated, so not every number is a named CSR. */
1315 riscv_is_regnum_a_named_csr (int regnum
)
1317 gdb_assert (regnum
>= RISCV_FIRST_CSR_REGNUM
1318 && regnum
<= RISCV_LAST_CSR_REGNUM
);
1322 #define DECLARE_CSR(name, num, class, define_ver, abort_ver) case RISCV_ ## num ## _REGNUM:
1323 #include "opcode/riscv-opc.h"
1332 /* Return true if REGNUM is an unknown CSR identified in
1333 riscv_tdesc_unknown_reg for GDBARCH. */
1336 riscv_is_unknown_csr (struct gdbarch
*gdbarch
, int regnum
)
1338 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
1339 return (regnum
>= tdep
->unknown_csrs_first_regnum
1340 && regnum
< (tdep
->unknown_csrs_first_regnum
1341 + tdep
->unknown_csrs_count
));
1344 /* Implement the register_reggroup_p gdbarch method. Is REGNUM a member
1348 riscv_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
1349 const struct reggroup
*reggroup
)
1351 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
1353 /* Used by 'info registers' and 'info registers <groupname>'. */
1355 if (gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
1358 if (regnum
> RISCV_LAST_REGNUM
&& regnum
< gdbarch_num_regs (gdbarch
))
1360 /* Any extra registers from the CSR tdesc_feature (identified in
1361 riscv_tdesc_unknown_reg) are removed from the save/restore groups
1362 as some targets (QEMU) report CSRs which then can't be read and
1363 having unreadable registers in the save/restore group breaks
1364 things like inferior calls.
1366 The unknown CSRs are also removed from the general group, and
1367 added into both the csr and system group. This is inline with the
1368 known CSRs (see below). */
1369 if (riscv_is_unknown_csr (gdbarch
, regnum
))
1371 if (reggroup
== restore_reggroup
|| reggroup
== save_reggroup
1372 || reggroup
== general_reggroup
)
1374 else if (reggroup
== system_reggroup
|| reggroup
== csr_reggroup
)
1378 /* This is some other unknown register from the target description.
1379 In this case we trust whatever the target description says about
1380 which groups this register should be in. */
1381 int ret
= tdesc_register_in_reggroup_p (gdbarch
, regnum
, reggroup
);
1385 return default_register_reggroup_p (gdbarch
, regnum
, reggroup
);
1388 if (reggroup
== all_reggroup
)
1390 if (regnum
< RISCV_FIRST_CSR_REGNUM
|| regnum
>= RISCV_PRIV_REGNUM
)
1392 if (riscv_is_regnum_a_named_csr (regnum
))
1396 else if (reggroup
== float_reggroup
)
1397 return (riscv_is_fp_regno_p (regnum
)
1398 || regnum
== RISCV_CSR_FCSR_REGNUM
1399 || regnum
== tdep
->fflags_regnum
1400 || regnum
== tdep
->frm_regnum
);
1401 else if (reggroup
== general_reggroup
)
1402 return regnum
< RISCV_FIRST_FP_REGNUM
;
1403 else if (reggroup
== restore_reggroup
|| reggroup
== save_reggroup
)
1405 if (riscv_has_fp_regs (gdbarch
))
1406 return (regnum
<= RISCV_LAST_FP_REGNUM
1407 || regnum
== RISCV_CSR_FCSR_REGNUM
1408 || regnum
== tdep
->fflags_regnum
1409 || regnum
== tdep
->frm_regnum
);
1411 return regnum
< RISCV_FIRST_FP_REGNUM
;
1413 else if (reggroup
== system_reggroup
|| reggroup
== csr_reggroup
)
1415 if (regnum
== RISCV_PRIV_REGNUM
)
1417 if (regnum
< RISCV_FIRST_CSR_REGNUM
|| regnum
> RISCV_LAST_CSR_REGNUM
)
1419 if (riscv_is_regnum_a_named_csr (regnum
))
1423 else if (reggroup
== vector_reggroup
)
1424 return (regnum
>= RISCV_V0_REGNUM
&& regnum
<= RISCV_V31_REGNUM
);
1429 /* Return the name for pseudo-register REGNUM for GDBARCH. */
1432 riscv_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
1434 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
1436 if (regnum
== tdep
->fflags_regnum
)
1438 else if (regnum
== tdep
->frm_regnum
)
1441 gdb_assert_not_reached ("unknown pseudo register number %d", regnum
);
1444 /* Return the type for pseudo-register REGNUM for GDBARCH. */
1446 static struct type
*
1447 riscv_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
1449 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
1451 if (regnum
== tdep
->fflags_regnum
|| regnum
== tdep
->frm_regnum
)
1452 return builtin_type (gdbarch
)->builtin_int32
;
1454 gdb_assert_not_reached ("unknown pseudo register number %d", regnum
);
1457 /* Return true (non-zero) if pseudo-register REGNUM from GDBARCH is a
1458 member of REGGROUP, otherwise return false (zero). */
1461 riscv_pseudo_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
1462 const struct reggroup
*reggroup
)
1464 /* The standard function will also work for pseudo-registers. */
1465 return riscv_register_reggroup_p (gdbarch
, regnum
, reggroup
);
1468 /* Implement the print_registers_info gdbarch method. This is used by
1469 'info registers' and 'info all-registers'. */
1472 riscv_print_registers_info (struct gdbarch
*gdbarch
,
1473 struct ui_file
*file
,
1474 frame_info_ptr frame
,
1475 int regnum
, int print_all
)
1479 /* Print one specified register. */
1480 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
1481 error (_("Not a valid register for the current processor type"));
1482 riscv_print_one_register_info (gdbarch
, file
, frame
, regnum
);
1486 const struct reggroup
*reggroup
;
1489 reggroup
= all_reggroup
;
1491 reggroup
= general_reggroup
;
1493 for (regnum
= 0; regnum
< gdbarch_num_cooked_regs (gdbarch
); ++regnum
)
1495 /* Zero never changes, so might as well hide by default. */
1496 if (regnum
== RISCV_ZERO_REGNUM
&& !print_all
)
1499 /* Registers with no name are not valid on this ISA. */
1500 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
1503 /* Is the register in the group we're interested in? */
1504 if (!gdbarch_register_reggroup_p (gdbarch
, regnum
, reggroup
))
1507 riscv_print_one_register_info (gdbarch
, file
, frame
, regnum
);
1512 /* Class that handles one decoded RiscV instruction. */
1518 /* Enum of all the opcodes that GDB cares about during the prologue scan. */
1521 /* Unknown value is used at initialisation time. */
1524 /* These instructions are all the ones we are interested in during the
1537 /* These are needed for software breakpoint support. */
1546 /* These are needed for stepping over atomic sequences. */
1549 /* This instruction is used to do a syscall. */
1552 /* Other instructions are not interesting during the prologue scan, and
1567 void decode (struct gdbarch
*gdbarch
, CORE_ADDR pc
);
1569 /* Get the length of the instruction in bytes. */
1571 { return m_length
; }
1573 /* Get the opcode for this instruction. */
1574 enum opcode
opcode () const
1575 { return m_opcode
; }
1577 /* Get destination register field for this instruction. This is only
1578 valid if the OPCODE implies there is such a field for this
1583 /* Get the RS1 register field for this instruction. This is only valid
1584 if the OPCODE implies there is such a field for this instruction. */
1588 /* Get the RS2 register field for this instruction. This is only valid
1589 if the OPCODE implies there is such a field for this instruction. */
1593 /* Get the immediate for this instruction in signed form. This is only
1594 valid if the OPCODE implies there is such a field for this
1596 int imm_signed () const
1601 /* Extract 5 bit register field at OFFSET from instruction OPCODE. */
1602 int decode_register_index (unsigned long opcode
, int offset
)
1604 return (opcode
>> offset
) & 0x1F;
1607 /* Extract 5 bit register field at OFFSET from instruction OPCODE. */
1608 int decode_register_index_short (unsigned long opcode
, int offset
)
1610 return ((opcode
>> offset
) & 0x7) + 8;
1613 /* Helper for DECODE, decode 32-bit R-type instruction. */
1614 void decode_r_type_insn (enum opcode opcode
, ULONGEST ival
)
1617 m_rd
= decode_register_index (ival
, OP_SH_RD
);
1618 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
1619 m_rs2
= decode_register_index (ival
, OP_SH_RS2
);
1622 /* Helper for DECODE, decode 16-bit compressed R-type instruction. */
1623 void decode_cr_type_insn (enum opcode opcode
, ULONGEST ival
)
1626 m_rd
= m_rs1
= decode_register_index (ival
, OP_SH_CRS1S
);
1627 m_rs2
= decode_register_index (ival
, OP_SH_CRS2
);
1630 /* Helper for DECODE, decode 32-bit I-type instruction. */
1631 void decode_i_type_insn (enum opcode opcode
, ULONGEST ival
)
1634 m_rd
= decode_register_index (ival
, OP_SH_RD
);
1635 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
1636 m_imm
.s
= EXTRACT_ITYPE_IMM (ival
);
1639 /* Helper for DECODE, decode 16-bit compressed I-type instruction. */
1640 void decode_ci_type_insn (enum opcode opcode
, ULONGEST ival
)
1643 m_rd
= m_rs1
= decode_register_index (ival
, OP_SH_CRS1S
);
1644 m_imm
.s
= EXTRACT_CITYPE_IMM (ival
);
1647 /* Helper for DECODE, decode 16-bit compressed CL-type instruction. */
1648 void decode_cl_type_insn (enum opcode opcode
, ULONGEST ival
)
1651 m_rd
= decode_register_index_short (ival
, OP_SH_CRS2S
);
1652 m_rs1
= decode_register_index_short (ival
, OP_SH_CRS1S
);
1653 m_imm
.s
= EXTRACT_CLTYPE_IMM (ival
);
1656 /* Helper for DECODE, decode 32-bit S-type instruction. */
1657 void decode_s_type_insn (enum opcode opcode
, ULONGEST ival
)
1660 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
1661 m_rs2
= decode_register_index (ival
, OP_SH_RS2
);
1662 m_imm
.s
= EXTRACT_STYPE_IMM (ival
);
1665 /* Helper for DECODE, decode 16-bit CS-type instruction. The immediate
1666 encoding is different for each CS format instruction, so extracting
1667 the immediate is left up to the caller, who should pass the extracted
1668 immediate value through in IMM. */
1669 void decode_cs_type_insn (enum opcode opcode
, ULONGEST ival
, int imm
)
1673 m_rs1
= decode_register_index_short (ival
, OP_SH_CRS1S
);
1674 m_rs2
= decode_register_index_short (ival
, OP_SH_CRS2S
);
1677 /* Helper for DECODE, decode 16-bit CSS-type instruction. The immediate
1678 encoding is different for each CSS format instruction, so extracting
1679 the immediate is left up to the caller, who should pass the extracted
1680 immediate value through in IMM. */
1681 void decode_css_type_insn (enum opcode opcode
, ULONGEST ival
, int imm
)
1685 m_rs1
= RISCV_SP_REGNUM
;
1686 /* Not a compressed register number in this case. */
1687 m_rs2
= decode_register_index (ival
, OP_SH_CRS2
);
1690 /* Helper for DECODE, decode 32-bit U-type instruction. */
1691 void decode_u_type_insn (enum opcode opcode
, ULONGEST ival
)
1694 m_rd
= decode_register_index (ival
, OP_SH_RD
);
1695 m_imm
.s
= EXTRACT_UTYPE_IMM (ival
);
1698 /* Helper for DECODE, decode 32-bit J-type instruction. */
1699 void decode_j_type_insn (enum opcode opcode
, ULONGEST ival
)
1702 m_rd
= decode_register_index (ival
, OP_SH_RD
);
1703 m_imm
.s
= EXTRACT_JTYPE_IMM (ival
);
1706 /* Helper for DECODE, decode 32-bit J-type instruction. */
1707 void decode_cj_type_insn (enum opcode opcode
, ULONGEST ival
)
1710 m_imm
.s
= EXTRACT_CJTYPE_IMM (ival
);
1713 void decode_b_type_insn (enum opcode opcode
, ULONGEST ival
)
1716 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
1717 m_rs2
= decode_register_index (ival
, OP_SH_RS2
);
1718 m_imm
.s
= EXTRACT_BTYPE_IMM (ival
);
1721 void decode_cb_type_insn (enum opcode opcode
, ULONGEST ival
)
1724 m_rs1
= decode_register_index_short (ival
, OP_SH_CRS1S
);
1725 m_imm
.s
= EXTRACT_CBTYPE_IMM (ival
);
1728 /* Fetch instruction from target memory at ADDR, return the content of
1729 the instruction, and update LEN with the instruction length. */
1730 static ULONGEST
fetch_instruction (struct gdbarch
*gdbarch
,
1731 CORE_ADDR addr
, int *len
);
1733 /* The length of the instruction in bytes. Should be 2 or 4. */
1736 /* The instruction opcode. */
1737 enum opcode m_opcode
;
1739 /* The three possible registers an instruction might reference. Not
1740 every instruction fills in all of these registers. Which fields are
1741 valid depends on the opcode. The naming of these fields matches the
1742 naming in the riscv isa manual. */
1747 /* Possible instruction immediate. This is only valid if the instruction
1748 format contains an immediate, not all instruction, whether this is
1749 valid depends on the opcode. Despite only having one format for now
1750 the immediate is packed into a union, later instructions might require
1751 an unsigned formatted immediate, having the union in place now will
1752 reduce the need for code churn later. */
1753 union riscv_insn_immediate
1755 riscv_insn_immediate ()
1765 /* Fetch instruction from target memory at ADDR, return the content of the
1766 instruction, and update LEN with the instruction length. */
1769 riscv_insn::fetch_instruction (struct gdbarch
*gdbarch
,
1770 CORE_ADDR addr
, int *len
)
1772 enum bfd_endian byte_order
= gdbarch_byte_order_for_code (gdbarch
);
1773 gdb_byte buf
[RISCV_MAX_INSN_LEN
];
1774 int instlen
, status
;
1776 /* All insns are at least 16 bits. */
1777 status
= target_read_memory (addr
, buf
, 2);
1779 memory_error (TARGET_XFER_E_IO
, addr
);
1781 /* If we need more, grab it now. */
1782 instlen
= riscv_insn_length (buf
[0]);
1783 gdb_assert (instlen
<= sizeof (buf
));
1788 status
= target_read_memory (addr
+ 2, buf
+ 2, instlen
- 2);
1790 memory_error (TARGET_XFER_E_IO
, addr
+ 2);
1793 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1796 /* Fetch from target memory an instruction at PC and decode it. This can
1797 throw an error if the memory access fails, callers are responsible for
1798 handling this error if that is appropriate. */
1801 riscv_insn::decode (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1805 /* Fetch the instruction, and the instructions length. */
1806 ival
= fetch_instruction (gdbarch
, pc
, &m_length
);
1810 if (is_add_insn (ival
))
1811 decode_r_type_insn (ADD
, ival
);
1812 else if (is_addw_insn (ival
))
1813 decode_r_type_insn (ADDW
, ival
);
1814 else if (is_addi_insn (ival
))
1815 decode_i_type_insn (ADDI
, ival
);
1816 else if (is_addiw_insn (ival
))
1817 decode_i_type_insn (ADDIW
, ival
);
1818 else if (is_auipc_insn (ival
))
1819 decode_u_type_insn (AUIPC
, ival
);
1820 else if (is_lui_insn (ival
))
1821 decode_u_type_insn (LUI
, ival
);
1822 else if (is_sd_insn (ival
))
1823 decode_s_type_insn (SD
, ival
);
1824 else if (is_sw_insn (ival
))
1825 decode_s_type_insn (SW
, ival
);
1826 else if (is_jal_insn (ival
))
1827 decode_j_type_insn (JAL
, ival
);
1828 else if (is_jalr_insn (ival
))
1829 decode_i_type_insn (JALR
, ival
);
1830 else if (is_beq_insn (ival
))
1831 decode_b_type_insn (BEQ
, ival
);
1832 else if (is_bne_insn (ival
))
1833 decode_b_type_insn (BNE
, ival
);
1834 else if (is_blt_insn (ival
))
1835 decode_b_type_insn (BLT
, ival
);
1836 else if (is_bge_insn (ival
))
1837 decode_b_type_insn (BGE
, ival
);
1838 else if (is_bltu_insn (ival
))
1839 decode_b_type_insn (BLTU
, ival
);
1840 else if (is_bgeu_insn (ival
))
1841 decode_b_type_insn (BGEU
, ival
);
1842 else if (is_lr_w_insn (ival
))
1843 decode_r_type_insn (LR
, ival
);
1844 else if (is_lr_d_insn (ival
))
1845 decode_r_type_insn (LR
, ival
);
1846 else if (is_sc_w_insn (ival
))
1847 decode_r_type_insn (SC
, ival
);
1848 else if (is_sc_d_insn (ival
))
1849 decode_r_type_insn (SC
, ival
);
1850 else if (is_ecall_insn (ival
))
1851 decode_i_type_insn (ECALL
, ival
);
1852 else if (is_ld_insn (ival
))
1853 decode_i_type_insn (LD
, ival
);
1854 else if (is_lw_insn (ival
))
1855 decode_i_type_insn (LW
, ival
);
1857 /* None of the other fields are valid in this case. */
1860 else if (m_length
== 2)
1862 int xlen
= riscv_isa_xlen (gdbarch
);
1864 /* C_ADD and C_JALR have the same opcode. If RS2 is 0, then this is a
1865 C_JALR. So must try to match C_JALR first as it has more bits in
1867 if (is_c_jalr_insn (ival
))
1868 decode_cr_type_insn (JALR
, ival
);
1869 else if (is_c_add_insn (ival
))
1870 decode_cr_type_insn (ADD
, ival
);
1871 /* C_ADDW is RV64 and RV128 only. */
1872 else if (xlen
!= 4 && is_c_addw_insn (ival
))
1873 decode_cr_type_insn (ADDW
, ival
);
1874 else if (is_c_addi_insn (ival
))
1875 decode_ci_type_insn (ADDI
, ival
);
1876 /* C_ADDIW and C_JAL have the same opcode. C_ADDIW is RV64 and RV128
1877 only and C_JAL is RV32 only. */
1878 else if (xlen
!= 4 && is_c_addiw_insn (ival
))
1879 decode_ci_type_insn (ADDIW
, ival
);
1880 else if (xlen
== 4 && is_c_jal_insn (ival
))
1881 decode_cj_type_insn (JAL
, ival
);
1882 /* C_ADDI16SP and C_LUI have the same opcode. If RD is 2, then this is a
1883 C_ADDI16SP. So must try to match C_ADDI16SP first as it has more bits
1885 else if (is_c_addi16sp_insn (ival
))
1888 m_rd
= m_rs1
= decode_register_index (ival
, OP_SH_RD
);
1889 m_imm
.s
= EXTRACT_CITYPE_ADDI16SP_IMM (ival
);
1891 else if (is_c_addi4spn_insn (ival
))
1894 m_rd
= decode_register_index_short (ival
, OP_SH_CRS2S
);
1895 m_rs1
= RISCV_SP_REGNUM
;
1896 m_imm
.s
= EXTRACT_CIWTYPE_ADDI4SPN_IMM (ival
);
1898 else if (is_c_lui_insn (ival
))
1901 m_rd
= decode_register_index (ival
, OP_SH_CRS1S
);
1902 m_imm
.s
= EXTRACT_CITYPE_LUI_IMM (ival
);
1904 /* C_SD and C_FSW have the same opcode. C_SD is RV64 and RV128 only,
1905 and C_FSW is RV32 only. */
1906 else if (xlen
!= 4 && is_c_sd_insn (ival
))
1907 decode_cs_type_insn (SD
, ival
, EXTRACT_CLTYPE_LD_IMM (ival
));
1908 else if (is_c_sw_insn (ival
))
1909 decode_cs_type_insn (SW
, ival
, EXTRACT_CLTYPE_LW_IMM (ival
));
1910 else if (is_c_swsp_insn (ival
))
1911 decode_css_type_insn (SW
, ival
, EXTRACT_CSSTYPE_SWSP_IMM (ival
));
1912 else if (xlen
!= 4 && is_c_sdsp_insn (ival
))
1913 decode_css_type_insn (SD
, ival
, EXTRACT_CSSTYPE_SDSP_IMM (ival
));
1914 /* C_JR and C_MV have the same opcode. If RS2 is 0, then this is a C_JR.
1915 So must try to match C_JR first as it has more bits in mask. */
1916 else if (is_c_jr_insn (ival
))
1917 decode_cr_type_insn (JALR
, ival
);
1918 else if (is_c_mv_insn (ival
))
1919 decode_cr_type_insn (MV
, ival
);
1920 else if (is_c_j_insn (ival
))
1921 decode_cj_type_insn (JAL
, ival
);
1922 else if (is_c_beqz_insn (ival
))
1923 decode_cb_type_insn (BEQ
, ival
);
1924 else if (is_c_bnez_insn (ival
))
1925 decode_cb_type_insn (BNE
, ival
);
1926 else if (is_c_ld_insn (ival
))
1927 decode_cl_type_insn (LD
, ival
);
1928 else if (is_c_lw_insn (ival
))
1929 decode_cl_type_insn (LW
, ival
);
1931 /* None of the other fields of INSN are valid in this case. */
1936 /* 6 bytes or more. If the instruction is longer than 8 bytes, we don't
1937 have full instruction bits in ival. At least, such long instructions
1938 are not defined yet, so just ignore it. */
1939 gdb_assert (m_length
> 0 && m_length
% 2 == 0);
1944 /* The prologue scanner. This is currently only used for skipping the
1945 prologue of a function when the DWARF information is not sufficient.
1946 However, it is written with filling of the frame cache in mind, which
1947 is why different groups of stack setup instructions are split apart
1948 during the core of the inner loop. In the future, the intention is to
1949 extend this function to fully support building up a frame cache that
1950 can unwind register values when there is no DWARF information. */
1953 riscv_scan_prologue (struct gdbarch
*gdbarch
,
1954 CORE_ADDR start_pc
, CORE_ADDR end_pc
,
1955 struct riscv_unwind_cache
*cache
)
1957 CORE_ADDR cur_pc
, next_pc
, after_prologue_pc
;
1958 CORE_ADDR end_prologue_addr
= 0;
1960 /* Find an upper limit on the function prologue using the debug
1961 information. If the debug information could not be used to provide
1962 that bound, then use an arbitrary large number as the upper bound. */
1963 after_prologue_pc
= skip_prologue_using_sal (gdbarch
, start_pc
);
1964 if (after_prologue_pc
== 0)
1965 after_prologue_pc
= start_pc
+ 100; /* Arbitrary large number. */
1966 if (after_prologue_pc
< end_pc
)
1967 end_pc
= after_prologue_pc
;
1969 pv_t regs
[RISCV_NUM_INTEGER_REGS
]; /* Number of GPR. */
1970 for (int regno
= 0; regno
< RISCV_NUM_INTEGER_REGS
; regno
++)
1971 regs
[regno
] = pv_register (regno
, 0);
1972 pv_area
stack (RISCV_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
1974 if (riscv_debug_unwinder
)
1977 "Prologue scan for function starting at %s (limit %s)\n",
1978 core_addr_to_string (start_pc
),
1979 core_addr_to_string (end_pc
));
1981 for (next_pc
= cur_pc
= start_pc
; cur_pc
< end_pc
; cur_pc
= next_pc
)
1983 struct riscv_insn insn
;
1985 /* Decode the current instruction, and decide where the next
1986 instruction lives based on the size of this instruction. */
1987 insn
.decode (gdbarch
, cur_pc
);
1988 gdb_assert (insn
.length () > 0);
1989 next_pc
= cur_pc
+ insn
.length ();
1991 /* Look for common stack adjustment insns. */
1992 if ((insn
.opcode () == riscv_insn::ADDI
1993 || insn
.opcode () == riscv_insn::ADDIW
)
1994 && insn
.rd () == RISCV_SP_REGNUM
1995 && insn
.rs1 () == RISCV_SP_REGNUM
)
1997 /* Handle: addi sp, sp, -i
1998 or: addiw sp, sp, -i */
1999 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
2000 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
2002 = pv_add_constant (regs
[insn
.rs1 ()], insn
.imm_signed ());
2004 else if ((insn
.opcode () == riscv_insn::SW
2005 || insn
.opcode () == riscv_insn::SD
)
2006 && (insn
.rs1 () == RISCV_SP_REGNUM
2007 || insn
.rs1 () == RISCV_FP_REGNUM
))
2009 /* Handle: sw reg, offset(sp)
2010 or: sd reg, offset(sp)
2011 or: sw reg, offset(s0)
2012 or: sd reg, offset(s0) */
2013 /* Instruction storing a register onto the stack. */
2014 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
2015 gdb_assert (insn
.rs2 () < RISCV_NUM_INTEGER_REGS
);
2016 stack
.store (pv_add_constant (regs
[insn
.rs1 ()], insn
.imm_signed ()),
2017 (insn
.opcode () == riscv_insn::SW
? 4 : 8),
2020 else if (insn
.opcode () == riscv_insn::ADDI
2021 && insn
.rd () == RISCV_FP_REGNUM
2022 && insn
.rs1 () == RISCV_SP_REGNUM
)
2024 /* Handle: addi s0, sp, size */
2025 /* Instructions setting up the frame pointer. */
2026 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
2027 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
2029 = pv_add_constant (regs
[insn
.rs1 ()], insn
.imm_signed ());
2031 else if ((insn
.opcode () == riscv_insn::ADD
2032 || insn
.opcode () == riscv_insn::ADDW
)
2033 && insn
.rd () == RISCV_FP_REGNUM
2034 && insn
.rs1 () == RISCV_SP_REGNUM
2035 && insn
.rs2 () == RISCV_ZERO_REGNUM
)
2037 /* Handle: add s0, sp, 0
2038 or: addw s0, sp, 0 */
2039 /* Instructions setting up the frame pointer. */
2040 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
2041 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
2042 regs
[insn
.rd ()] = pv_add_constant (regs
[insn
.rs1 ()], 0);
2044 else if ((insn
.opcode () == riscv_insn::ADDI
2045 && insn
.rd () == RISCV_ZERO_REGNUM
2046 && insn
.rs1 () == RISCV_ZERO_REGNUM
2047 && insn
.imm_signed () == 0))
2049 /* Handle: add x0, x0, 0 (NOP) */
2051 else if (insn
.opcode () == riscv_insn::AUIPC
)
2053 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
2054 regs
[insn
.rd ()] = pv_constant (cur_pc
+ insn
.imm_signed ());
2056 else if (insn
.opcode () == riscv_insn::LUI
)
2058 /* Handle: lui REG, n
2059 Where REG is not gp register. */
2060 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
2061 regs
[insn
.rd ()] = pv_constant (insn
.imm_signed ());
2063 else if (insn
.opcode () == riscv_insn::ADDI
)
2065 /* Handle: addi REG1, REG2, IMM */
2066 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
2067 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
2069 = pv_add_constant (regs
[insn
.rs1 ()], insn
.imm_signed ());
2071 else if (insn
.opcode () == riscv_insn::ADD
)
2073 /* Handle: add REG1, REG2, REG3 */
2074 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
2075 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
2076 gdb_assert (insn
.rs2 () < RISCV_NUM_INTEGER_REGS
);
2077 regs
[insn
.rd ()] = pv_add (regs
[insn
.rs1 ()], regs
[insn
.rs2 ()]);
2079 else if (insn
.opcode () == riscv_insn::LD
2080 || insn
.opcode () == riscv_insn::LW
)
2082 /* Handle: ld reg, offset(rs1)
2083 or: c.ld reg, offset(rs1)
2084 or: lw reg, offset(rs1)
2085 or: c.lw reg, offset(rs1) */
2086 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
2087 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
2089 = stack
.fetch (pv_add_constant (regs
[insn
.rs1 ()],
2090 insn
.imm_signed ()),
2091 (insn
.opcode () == riscv_insn::LW
? 4 : 8));
2093 else if (insn
.opcode () == riscv_insn::MV
)
2095 /* Handle: c.mv RD, RS2 */
2096 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
2097 gdb_assert (insn
.rs2 () < RISCV_NUM_INTEGER_REGS
);
2098 gdb_assert (insn
.rs2 () > 0);
2099 regs
[insn
.rd ()] = regs
[insn
.rs2 ()];
2103 end_prologue_addr
= cur_pc
;
2108 if (end_prologue_addr
== 0)
2109 end_prologue_addr
= cur_pc
;
2111 if (riscv_debug_unwinder
)
2112 gdb_printf (gdb_stdlog
, "End of prologue at %s\n",
2113 core_addr_to_string (end_prologue_addr
));
2117 /* Figure out if it is a frame pointer or just a stack pointer. Also
2118 the offset held in the pv_t is from the original register value to
2119 the current value, which for a grows down stack means a negative
2120 value. The FRAME_BASE_OFFSET is the negation of this, how to get
2121 from the current value to the original value. */
2122 if (pv_is_register (regs
[RISCV_FP_REGNUM
], RISCV_SP_REGNUM
))
2124 cache
->frame_base_reg
= RISCV_FP_REGNUM
;
2125 cache
->frame_base_offset
= -regs
[RISCV_FP_REGNUM
].k
;
2129 cache
->frame_base_reg
= RISCV_SP_REGNUM
;
2130 cache
->frame_base_offset
= -regs
[RISCV_SP_REGNUM
].k
;
2133 /* Assign offset from old SP to all saved registers. As we don't
2134 have the previous value for the frame base register at this
2135 point, we store the offset as the address in the trad_frame, and
2136 then convert this to an actual address later. */
2137 for (int i
= 0; i
<= RISCV_NUM_INTEGER_REGS
; i
++)
2140 if (stack
.find_reg (gdbarch
, i
, &offset
))
2142 if (riscv_debug_unwinder
)
2144 /* Display OFFSET as a signed value, the offsets are from
2145 the frame base address to the registers location on
2146 the stack, with a descending stack this means the
2147 offsets are always negative. */
2148 gdb_printf (gdb_stdlog
,
2149 "Register $%s at stack offset %s\n",
2150 gdbarch_register_name (gdbarch
, i
),
2151 plongest ((LONGEST
) offset
));
2153 cache
->regs
[i
].set_addr (offset
);
2158 return end_prologue_addr
;
2161 /* Implement the riscv_skip_prologue gdbarch method. */
2164 riscv_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2166 CORE_ADDR func_addr
;
2168 /* See if we can determine the end of the prologue via the symbol
2169 table. If so, then return either PC, or the PC after the
2170 prologue, whichever is greater. */
2171 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
2173 CORE_ADDR post_prologue_pc
2174 = skip_prologue_using_sal (gdbarch
, func_addr
);
2176 if (post_prologue_pc
!= 0)
2177 return std::max (pc
, post_prologue_pc
);
2180 /* Can't determine prologue from the symbol table, need to examine
2181 instructions. Pass -1 for the end address to indicate the prologue
2182 scanner can scan as far as it needs to find the end of the prologue. */
2183 return riscv_scan_prologue (gdbarch
, pc
, ((CORE_ADDR
) -1), NULL
);
2186 /* Implement the gdbarch push dummy code callback. */
2189 riscv_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
2190 CORE_ADDR funaddr
, struct value
**args
, int nargs
,
2191 struct type
*value_type
, CORE_ADDR
*real_pc
,
2192 CORE_ADDR
*bp_addr
, struct regcache
*regcache
)
2194 /* A nop instruction is 'add x0, x0, 0'. */
2195 static const gdb_byte nop_insn
[] = { 0x13, 0x00, 0x00, 0x00 };
2197 /* Allocate space for a breakpoint, and keep the stack correctly
2198 aligned. The space allocated here must be at least big enough to
2199 accommodate the NOP_INSN defined above. */
2204 /* When we insert a breakpoint we select whether to use a compressed
2205 breakpoint or not based on the existing contents of the memory.
2207 If the breakpoint is being placed onto the stack as part of setting up
2208 for an inferior call from GDB, then the existing stack contents may
2209 randomly appear to be a compressed instruction, causing GDB to insert
2210 a compressed breakpoint. If this happens on a target that does not
2211 support compressed instructions then this could cause problems.
2213 To prevent this issue we write an uncompressed nop onto the stack at
2214 the location where the breakpoint will be inserted. In this way we
2215 ensure that we always use an uncompressed breakpoint, which should
2216 work on all targets.
2218 We call TARGET_WRITE_MEMORY here so that if the write fails we don't
2219 throw an exception. Instead we ignore the error and move on. The
2220 assumption is that either GDB will error later when actually trying to
2221 insert a software breakpoint, or GDB will use hardware breakpoints and
2222 there will be no need to write to memory later. */
2223 int status
= target_write_memory (*bp_addr
, nop_insn
, sizeof (nop_insn
));
2225 if (riscv_debug_breakpoints
|| riscv_debug_infcall
)
2226 gdb_printf (gdb_stdlog
,
2227 "Writing %s-byte nop instruction to %s: %s\n",
2228 plongest (sizeof (nop_insn
)),
2229 paddress (gdbarch
, *bp_addr
),
2230 (status
== 0 ? "success" : "failed"));
2235 /* Implement the gdbarch type alignment method, overrides the generic
2236 alignment algorithm for anything that is RISC-V specific. */
2239 riscv_type_align (gdbarch
*gdbarch
, type
*type
)
2241 type
= check_typedef (type
);
2242 if (type
->code () == TYPE_CODE_ARRAY
&& type
->is_vector ())
2243 return std::min (type
->length (), (ULONGEST
) BIGGEST_ALIGNMENT
);
2245 /* Anything else will be aligned by the generic code. */
2249 /* Holds information about a single argument either being passed to an
2250 inferior function, or returned from an inferior function. This includes
2251 information about the size, type, etc of the argument, and also
2252 information about how the argument will be passed (or returned). */
2254 struct riscv_arg_info
2256 /* Contents of the argument. */
2257 const gdb_byte
*contents
;
2259 /* Length of argument. */
2262 /* Alignment required for an argument of this type. */
2265 /* The type for this argument. */
2268 /* Each argument can have either 1 or 2 locations assigned to it. Each
2269 location describes where part of the argument will be placed. The
2270 second location is valid based on the LOC_TYPE and C_LENGTH fields
2271 of the first location (which is always valid). */
2274 /* What type of location this is. */
2277 /* Argument passed in a register. */
2280 /* Argument passed as an on stack argument. */
2283 /* Argument passed by reference. The second location is always
2284 valid for a BY_REF argument, and describes where the address
2285 of the BY_REF argument should be placed. */
2289 /* Information that depends on the location type. */
2292 /* Which register number to use. */
2295 /* The offset into the stack region. */
2299 /* The length of contents covered by this location. If this is less
2300 than the total length of the argument, then the second location
2301 will be valid, and will describe where the rest of the argument
2305 /* The offset within CONTENTS for this part of the argument. This can
2306 be non-zero even for the first part (the first field of a struct can
2307 have a non-zero offset due to padding). For the second part of the
2308 argument, this might be the C_LENGTH value of the first part,
2309 however, if we are passing a structure in two registers, and there's
2310 is padding between the first and second field, then this offset
2311 might be greater than the length of the first argument part. When
2312 the second argument location is not holding part of the argument
2313 value, but is instead holding the address of a reference argument,
2314 then this offset will be set to 0. */
2318 /* TRUE if this is an unnamed argument. */
2322 /* Information about a set of registers being used for passing arguments as
2323 part of a function call. The register set must be numerically
2324 sequential from NEXT_REGNUM to LAST_REGNUM. The register set can be
2325 disabled from use by setting NEXT_REGNUM greater than LAST_REGNUM. */
2327 struct riscv_arg_reg
2329 riscv_arg_reg (int first
, int last
)
2330 : next_regnum (first
),
2336 /* The GDB register number to use in this set. */
2339 /* The last GDB register number to use in this set. */
2343 /* Arguments can be passed as on stack arguments, or by reference. The
2344 on stack arguments must be in a continuous region starting from $sp,
2345 while the by reference arguments can be anywhere, but we'll put them
2346 on the stack after (at higher address) the on stack arguments.
2348 This might not be the right approach to take. The ABI is clear that
2349 an argument passed by reference can be modified by the callee, which
2350 us placing the argument (temporarily) onto the stack will not achieve
2351 (changes will be lost). There's also the possibility that very large
2352 arguments could overflow the stack.
2354 This struct is used to track offset into these two areas for where
2355 arguments are to be placed. */
2356 struct riscv_memory_offsets
2358 riscv_memory_offsets ()
2365 /* Offset into on stack argument area. */
2368 /* Offset into the pass by reference area. */
2372 /* Holds information about where arguments to a call will be placed. This
2373 is updated as arguments are added onto the call, and can be used to
2374 figure out where the next argument should be placed. */
2376 struct riscv_call_info
2378 riscv_call_info (struct gdbarch
*gdbarch
)
2379 : int_regs (RISCV_A0_REGNUM
, RISCV_A0_REGNUM
+ 7),
2380 float_regs (RISCV_FA0_REGNUM
, RISCV_FA0_REGNUM
+ 7)
2382 xlen
= riscv_abi_xlen (gdbarch
);
2383 flen
= riscv_abi_flen (gdbarch
);
2385 /* Reduce the number of integer argument registers when using the
2386 embedded abi (i.e. rv32e). */
2387 if (riscv_abi_embedded (gdbarch
))
2388 int_regs
.last_regnum
= RISCV_A0_REGNUM
+ 5;
2390 /* Disable use of floating point registers if needed. */
2391 if (!riscv_has_fp_abi (gdbarch
))
2392 float_regs
.next_regnum
= float_regs
.last_regnum
+ 1;
2395 /* Track the memory areas used for holding in-memory arguments to a
2397 struct riscv_memory_offsets memory
;
2399 /* Holds information about the next integer register to use for passing
2401 struct riscv_arg_reg int_regs
;
2403 /* Holds information about the next floating point register to use for
2404 passing an argument. */
2405 struct riscv_arg_reg float_regs
;
2407 /* The XLEN and FLEN are copied in to this structure for convenience, and
2408 are just the results of calling RISCV_ABI_XLEN and RISCV_ABI_FLEN. */
2413 /* Return the number of registers available for use as parameters in the
2414 register set REG. Returned value can be 0 or more. */
2417 riscv_arg_regs_available (struct riscv_arg_reg
*reg
)
2419 if (reg
->next_regnum
> reg
->last_regnum
)
2422 return (reg
->last_regnum
- reg
->next_regnum
+ 1);
2425 /* If there is at least one register available in the register set REG then
2426 the next register from REG is assigned to LOC and the length field of
2427 LOC is updated to LENGTH. The register set REG is updated to indicate
2428 that the assigned register is no longer available and the function
2431 If there are no registers available in REG then the function returns
2432 false, and LOC and REG are unchanged. */
2435 riscv_assign_reg_location (struct riscv_arg_info::location
*loc
,
2436 struct riscv_arg_reg
*reg
,
2437 int length
, int offset
)
2439 if (reg
->next_regnum
<= reg
->last_regnum
)
2441 loc
->loc_type
= riscv_arg_info::location::in_reg
;
2442 loc
->loc_data
.regno
= reg
->next_regnum
;
2444 loc
->c_length
= length
;
2445 loc
->c_offset
= offset
;
2452 /* Assign LOC a location as the next stack parameter, and update MEMORY to
2453 record that an area of stack has been used to hold the parameter
2456 The length field of LOC is updated to LENGTH, the length of the
2457 parameter being stored, and ALIGN is the alignment required by the
2458 parameter, which will affect how memory is allocated out of MEMORY. */
2461 riscv_assign_stack_location (struct riscv_arg_info::location
*loc
,
2462 struct riscv_memory_offsets
*memory
,
2463 int length
, int align
)
2465 loc
->loc_type
= riscv_arg_info::location::on_stack
;
2467 = align_up (memory
->arg_offset
, align
);
2468 loc
->loc_data
.offset
= memory
->arg_offset
;
2469 memory
->arg_offset
+= length
;
2470 loc
->c_length
= length
;
2472 /* Offset is always 0, either we're the first location part, in which
2473 case we're reading content from the start of the argument, or we're
2474 passing the address of a reference argument, so 0. */
2478 /* Update AINFO, which describes an argument that should be passed or
2479 returned using the integer ABI. The argloc fields within AINFO are
2480 updated to describe the location in which the argument will be passed to
2481 a function, or returned from a function.
2483 The CINFO structure contains the ongoing call information, the holds
2484 information such as which argument registers are remaining to be
2485 assigned to parameter, and how much memory has been used by parameters
2488 By examining the state of CINFO a suitable location can be selected,
2489 and assigned to AINFO. */
2492 riscv_call_arg_scalar_int (struct riscv_arg_info
*ainfo
,
2493 struct riscv_call_info
*cinfo
)
2495 if (TYPE_HAS_DYNAMIC_LENGTH (ainfo
->type
)
2496 || ainfo
->length
> (2 * cinfo
->xlen
))
2498 /* Argument is going to be passed by reference. */
2499 ainfo
->argloc
[0].loc_type
2500 = riscv_arg_info::location::by_ref
;
2501 cinfo
->memory
.ref_offset
2502 = align_up (cinfo
->memory
.ref_offset
, ainfo
->align
);
2503 ainfo
->argloc
[0].loc_data
.offset
= cinfo
->memory
.ref_offset
;
2504 cinfo
->memory
.ref_offset
+= ainfo
->length
;
2505 ainfo
->argloc
[0].c_length
= ainfo
->length
;
2507 /* The second location for this argument is given over to holding the
2508 address of the by-reference data. Pass 0 for the offset as this
2509 is not part of the actual argument value. */
2510 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
2513 riscv_assign_stack_location (&ainfo
->argloc
[1],
2514 &cinfo
->memory
, cinfo
->xlen
,
2519 int len
= std::min (ainfo
->length
, cinfo
->xlen
);
2520 int align
= std::max (ainfo
->align
, cinfo
->xlen
);
2522 /* Unnamed arguments in registers that require 2*XLEN alignment are
2523 passed in an aligned register pair. */
2524 if (ainfo
->is_unnamed
&& (align
== cinfo
->xlen
* 2)
2525 && cinfo
->int_regs
.next_regnum
& 1)
2526 cinfo
->int_regs
.next_regnum
++;
2528 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
2529 &cinfo
->int_regs
, len
, 0))
2530 riscv_assign_stack_location (&ainfo
->argloc
[0],
2531 &cinfo
->memory
, len
, align
);
2533 if (len
< ainfo
->length
)
2535 len
= ainfo
->length
- len
;
2536 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
2537 &cinfo
->int_regs
, len
,
2539 riscv_assign_stack_location (&ainfo
->argloc
[1],
2540 &cinfo
->memory
, len
, cinfo
->xlen
);
2545 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
2546 is being passed with the floating point ABI. */
2549 riscv_call_arg_scalar_float (struct riscv_arg_info
*ainfo
,
2550 struct riscv_call_info
*cinfo
)
2552 if (ainfo
->length
> cinfo
->flen
|| ainfo
->is_unnamed
)
2553 return riscv_call_arg_scalar_int (ainfo
, cinfo
);
2556 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
2559 return riscv_call_arg_scalar_int (ainfo
, cinfo
);
2563 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
2564 is a complex floating point argument, and is therefore handled
2565 differently to other argument types. */
2568 riscv_call_arg_complex_float (struct riscv_arg_info
*ainfo
,
2569 struct riscv_call_info
*cinfo
)
2571 if (ainfo
->length
<= (2 * cinfo
->flen
)
2572 && riscv_arg_regs_available (&cinfo
->float_regs
) >= 2
2573 && !ainfo
->is_unnamed
)
2576 int len
= ainfo
->length
/ 2;
2578 result
= riscv_assign_reg_location (&ainfo
->argloc
[0],
2579 &cinfo
->float_regs
, len
, 0);
2580 gdb_assert (result
);
2582 result
= riscv_assign_reg_location (&ainfo
->argloc
[1],
2583 &cinfo
->float_regs
, len
, len
);
2584 gdb_assert (result
);
2587 return riscv_call_arg_scalar_int (ainfo
, cinfo
);
2590 /* A structure used for holding information about a structure type within
2591 the inferior program. The RiscV ABI has special rules for handling some
2592 structures with a single field or with two fields. The counting of
2593 fields here is done after flattening out all nested structures. */
2595 class riscv_struct_info
2598 riscv_struct_info ()
2599 : m_number_of_fields (0),
2600 m_types
{ nullptr, nullptr },
2606 /* Analyse TYPE descending into nested structures, count the number of
2607 scalar fields and record the types of the first two fields found. */
2608 void analyse (struct type
*type
)
2610 analyse_inner (type
, 0);
2613 /* The number of scalar fields found in the analysed type. This is
2614 currently only accurate if the value returned is 0, 1, or 2 as the
2615 analysis stops counting when the number of fields is 3. This is
2616 because the RiscV ABI only has special cases for 1 or 2 fields,
2617 anything else we just don't care about. */
2618 int number_of_fields () const
2619 { return m_number_of_fields
; }
2621 /* Return the type for scalar field INDEX within the analysed type. Will
2622 return nullptr if there is no field at that index. Only INDEX values
2623 0 and 1 can be requested as the RiscV ABI only has special cases for
2624 structures with 1 or 2 fields. */
2625 struct type
*field_type (int index
) const
2627 gdb_assert (index
< (sizeof (m_types
) / sizeof (m_types
[0])));
2628 return m_types
[index
];
2631 /* Return the offset of scalar field INDEX within the analysed type. Will
2632 return 0 if there is no field at that index. Only INDEX values 0 and
2633 1 can be requested as the RiscV ABI only has special cases for
2634 structures with 1 or 2 fields. */
2635 int field_offset (int index
) const
2637 gdb_assert (index
< (sizeof (m_offsets
) / sizeof (m_offsets
[0])));
2638 return m_offsets
[index
];
2642 /* The number of scalar fields found within the structure after recursing
2643 into nested structures. */
2644 int m_number_of_fields
;
2646 /* The types of the first two scalar fields found within the structure
2647 after recursing into nested structures. */
2648 struct type
*m_types
[2];
2650 /* The offsets of the first two scalar fields found within the structure
2651 after recursing into nested structures. */
2654 /* Recursive core for ANALYSE, the OFFSET parameter tracks the byte
2655 offset from the start of the top level structure being analysed. */
2656 void analyse_inner (struct type
*type
, int offset
);
2659 /* See description in class declaration. */
2662 riscv_struct_info::analyse_inner (struct type
*type
, int offset
)
2664 unsigned int count
= type
->num_fields ();
2667 for (i
= 0; i
< count
; ++i
)
2669 if (type
->field (i
).loc_kind () != FIELD_LOC_KIND_BITPOS
)
2672 struct type
*field_type
= type
->field (i
).type ();
2673 field_type
= check_typedef (field_type
);
2675 = offset
+ type
->field (i
).loc_bitpos () / TARGET_CHAR_BIT
;
2677 switch (field_type
->code ())
2679 case TYPE_CODE_STRUCT
:
2680 analyse_inner (field_type
, field_offset
);
2684 /* RiscV only flattens out structures. Anything else does not
2685 need to be flattened, we just record the type, and when we
2686 look at the analysis results we'll realise this is not a
2687 structure we can special case, and pass the structure in
2689 if (m_number_of_fields
< 2)
2691 m_types
[m_number_of_fields
] = field_type
;
2692 m_offsets
[m_number_of_fields
] = field_offset
;
2694 m_number_of_fields
++;
2698 /* RiscV only has special handling for structures with 1 or 2 scalar
2699 fields, any more than that and the structure is just passed in
2700 memory. We can safely drop out early when we find 3 or more
2703 if (m_number_of_fields
> 2)
2708 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
2709 is a structure. Small structures on RiscV have some special case
2710 handling in order that the structure might be passed in register.
2711 Larger structures are passed in memory. After assigning location
2712 information to AINFO, CINFO will have been updated. */
2715 riscv_call_arg_struct (struct riscv_arg_info
*ainfo
,
2716 struct riscv_call_info
*cinfo
)
2718 if (riscv_arg_regs_available (&cinfo
->float_regs
) >= 1)
2720 struct riscv_struct_info sinfo
;
2722 sinfo
.analyse (ainfo
->type
);
2723 if (sinfo
.number_of_fields () == 1
2724 && sinfo
.field_type(0)->code () == TYPE_CODE_COMPLEX
)
2726 /* The following is similar to RISCV_CALL_ARG_COMPLEX_FLOAT,
2727 except we use the type of the complex field instead of the
2728 type from AINFO, and the first location might be at a non-zero
2730 if (sinfo
.field_type (0)->length () <= (2 * cinfo
->flen
)
2731 && riscv_arg_regs_available (&cinfo
->float_regs
) >= 2
2732 && !ainfo
->is_unnamed
)
2735 int len
= sinfo
.field_type (0)->length () / 2;
2736 int offset
= sinfo
.field_offset (0);
2738 result
= riscv_assign_reg_location (&ainfo
->argloc
[0],
2739 &cinfo
->float_regs
, len
,
2741 gdb_assert (result
);
2743 result
= riscv_assign_reg_location (&ainfo
->argloc
[1],
2744 &cinfo
->float_regs
, len
,
2746 gdb_assert (result
);
2749 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2753 if (sinfo
.number_of_fields () == 1
2754 && sinfo
.field_type(0)->code () == TYPE_CODE_FLT
)
2756 /* The following is similar to RISCV_CALL_ARG_SCALAR_FLOAT,
2757 except we use the type of the first scalar field instead of
2758 the type from AINFO. Also the location might be at a non-zero
2760 if (sinfo
.field_type (0)->length () > cinfo
->flen
2761 || ainfo
->is_unnamed
)
2762 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2765 int offset
= sinfo
.field_offset (0);
2766 int len
= sinfo
.field_type (0)->length ();
2768 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
2771 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2776 if (sinfo
.number_of_fields () == 2
2777 && sinfo
.field_type(0)->code () == TYPE_CODE_FLT
2778 && sinfo
.field_type (0)->length () <= cinfo
->flen
2779 && sinfo
.field_type(1)->code () == TYPE_CODE_FLT
2780 && sinfo
.field_type (1)->length () <= cinfo
->flen
2781 && riscv_arg_regs_available (&cinfo
->float_regs
) >= 2)
2783 int len0
= sinfo
.field_type (0)->length ();
2784 int offset
= sinfo
.field_offset (0);
2785 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
2786 &cinfo
->float_regs
, len0
, offset
))
2787 error (_("failed during argument setup"));
2789 int len1
= sinfo
.field_type (1)->length ();
2790 offset
= sinfo
.field_offset (1);
2791 gdb_assert (len1
<= (ainfo
->type
->length ()
2792 - sinfo
.field_type (0)->length ()));
2794 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
2797 error (_("failed during argument setup"));
2801 if (sinfo
.number_of_fields () == 2
2802 && riscv_arg_regs_available (&cinfo
->int_regs
) >= 1
2803 && (sinfo
.field_type(0)->code () == TYPE_CODE_FLT
2804 && sinfo
.field_type (0)->length () <= cinfo
->flen
2805 && is_integral_type (sinfo
.field_type (1))
2806 && sinfo
.field_type (1)->length () <= cinfo
->xlen
))
2808 int len0
= sinfo
.field_type (0)->length ();
2809 int offset
= sinfo
.field_offset (0);
2810 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
2811 &cinfo
->float_regs
, len0
, offset
))
2812 error (_("failed during argument setup"));
2814 int len1
= sinfo
.field_type (1)->length ();
2815 offset
= sinfo
.field_offset (1);
2816 gdb_assert (len1
<= cinfo
->xlen
);
2817 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
2818 &cinfo
->int_regs
, len1
, offset
))
2819 error (_("failed during argument setup"));
2823 if (sinfo
.number_of_fields () == 2
2824 && riscv_arg_regs_available (&cinfo
->int_regs
) >= 1
2825 && (is_integral_type (sinfo
.field_type (0))
2826 && sinfo
.field_type (0)->length () <= cinfo
->xlen
2827 && sinfo
.field_type(1)->code () == TYPE_CODE_FLT
2828 && sinfo
.field_type (1)->length () <= cinfo
->flen
))
2830 int len0
= sinfo
.field_type (0)->length ();
2831 int len1
= sinfo
.field_type (1)->length ();
2833 gdb_assert (len0
<= cinfo
->xlen
);
2834 gdb_assert (len1
<= cinfo
->flen
);
2836 int offset
= sinfo
.field_offset (0);
2837 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
2838 &cinfo
->int_regs
, len0
, offset
))
2839 error (_("failed during argument setup"));
2841 offset
= sinfo
.field_offset (1);
2842 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
2845 error (_("failed during argument setup"));
2851 /* Non of the structure flattening cases apply, so we just pass using
2853 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2856 /* Assign a location to call (or return) argument AINFO, the location is
2857 selected from CINFO which holds information about what call argument
2858 locations are available for use next. The TYPE is the type of the
2859 argument being passed, this information is recorded into AINFO (along
2860 with some additional information derived from the type). IS_UNNAMED
2861 is true if this is an unnamed (stdarg) argument, this info is also
2862 recorded into AINFO.
2864 After assigning a location to AINFO, CINFO will have been updated. */
2867 riscv_arg_location (struct gdbarch
*gdbarch
,
2868 struct riscv_arg_info
*ainfo
,
2869 struct riscv_call_info
*cinfo
,
2870 struct type
*type
, bool is_unnamed
)
2873 ainfo
->length
= ainfo
->type
->length ();
2874 ainfo
->align
= type_align (ainfo
->type
);
2875 ainfo
->is_unnamed
= is_unnamed
;
2876 ainfo
->contents
= nullptr;
2877 ainfo
->argloc
[0].c_length
= 0;
2878 ainfo
->argloc
[1].c_length
= 0;
2880 switch (ainfo
->type
->code ())
2883 case TYPE_CODE_BOOL
:
2884 case TYPE_CODE_CHAR
:
2885 case TYPE_CODE_RANGE
:
2886 case TYPE_CODE_ENUM
:
2888 case TYPE_CODE_FIXED_POINT
:
2889 if (ainfo
->length
<= cinfo
->xlen
)
2891 ainfo
->type
= builtin_type (gdbarch
)->builtin_long
;
2892 ainfo
->length
= cinfo
->xlen
;
2894 else if (ainfo
->length
<= (2 * cinfo
->xlen
))
2896 ainfo
->type
= builtin_type (gdbarch
)->builtin_long_long
;
2897 ainfo
->length
= 2 * cinfo
->xlen
;
2900 /* Recalculate the alignment requirement. */
2901 ainfo
->align
= type_align (ainfo
->type
);
2902 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2906 riscv_call_arg_scalar_float (ainfo
, cinfo
);
2909 case TYPE_CODE_COMPLEX
:
2910 riscv_call_arg_complex_float (ainfo
, cinfo
);
2913 case TYPE_CODE_STRUCT
:
2914 if (!TYPE_HAS_DYNAMIC_LENGTH (ainfo
->type
))
2916 riscv_call_arg_struct (ainfo
, cinfo
);
2922 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2927 /* Used for printing debug information about the call argument location in
2928 INFO to STREAM. The addresses in SP_REFS and SP_ARGS are the base
2929 addresses for the location of pass-by-reference and
2930 arguments-on-the-stack memory areas. */
2933 riscv_print_arg_location (ui_file
*stream
, struct gdbarch
*gdbarch
,
2934 struct riscv_arg_info
*info
,
2935 CORE_ADDR sp_refs
, CORE_ADDR sp_args
)
2937 gdb_printf (stream
, "type: '%s', length: 0x%x, alignment: 0x%x",
2938 TYPE_SAFE_NAME (info
->type
), info
->length
, info
->align
);
2939 switch (info
->argloc
[0].loc_type
)
2941 case riscv_arg_info::location::in_reg
:
2943 (stream
, ", register %s",
2944 gdbarch_register_name (gdbarch
, info
->argloc
[0].loc_data
.regno
));
2945 if (info
->argloc
[0].c_length
< info
->length
)
2947 switch (info
->argloc
[1].loc_type
)
2949 case riscv_arg_info::location::in_reg
:
2951 (stream
, ", register %s",
2952 gdbarch_register_name (gdbarch
,
2953 info
->argloc
[1].loc_data
.regno
));
2956 case riscv_arg_info::location::on_stack
:
2957 gdb_printf (stream
, ", on stack at offset 0x%x",
2958 info
->argloc
[1].loc_data
.offset
);
2961 case riscv_arg_info::location::by_ref
:
2963 /* The second location should never be a reference, any
2964 argument being passed by reference just places its address
2965 in the first location and is done. */
2966 error (_("invalid argument location"));
2970 if (info
->argloc
[1].c_offset
> info
->argloc
[0].c_length
)
2971 gdb_printf (stream
, " (offset 0x%x)",
2972 info
->argloc
[1].c_offset
);
2976 case riscv_arg_info::location::on_stack
:
2977 gdb_printf (stream
, ", on stack at offset 0x%x",
2978 info
->argloc
[0].loc_data
.offset
);
2981 case riscv_arg_info::location::by_ref
:
2983 (stream
, ", by reference, data at offset 0x%x (%s)",
2984 info
->argloc
[0].loc_data
.offset
,
2985 core_addr_to_string (sp_refs
+ info
->argloc
[0].loc_data
.offset
));
2986 if (info
->argloc
[1].loc_type
2987 == riscv_arg_info::location::in_reg
)
2989 (stream
, ", address in register %s",
2990 gdbarch_register_name (gdbarch
, info
->argloc
[1].loc_data
.regno
));
2993 gdb_assert (info
->argloc
[1].loc_type
2994 == riscv_arg_info::location::on_stack
);
2996 (stream
, ", address on stack at offset 0x%x (%s)",
2997 info
->argloc
[1].loc_data
.offset
,
2998 core_addr_to_string (sp_args
+ info
->argloc
[1].loc_data
.offset
));
3003 gdb_assert_not_reached ("unknown argument location type");
3007 /* Wrapper around REGCACHE->cooked_write. Places the LEN bytes of DATA
3008 into a buffer that is at least as big as the register REGNUM, padding
3009 out the DATA with either 0x00, or 0xff. For floating point registers
3010 0xff is used, for everyone else 0x00 is used. */
3013 riscv_regcache_cooked_write (int regnum
, const gdb_byte
*data
, int len
,
3014 struct regcache
*regcache
, int flen
)
3016 gdb_byte tmp
[sizeof (ULONGEST
)];
3018 /* FP values in FP registers must be NaN-boxed. */
3019 if (riscv_is_fp_regno_p (regnum
) && len
< flen
)
3020 memset (tmp
, -1, sizeof (tmp
));
3022 memset (tmp
, 0, sizeof (tmp
));
3023 memcpy (tmp
, data
, len
);
3024 regcache
->cooked_write (regnum
, tmp
);
3027 /* Implement the push dummy call gdbarch callback. */
3030 riscv_push_dummy_call (struct gdbarch
*gdbarch
,
3031 struct value
*function
,
3032 struct regcache
*regcache
,
3035 struct value
**args
,
3037 function_call_return_method return_method
,
3038 CORE_ADDR struct_addr
)
3041 CORE_ADDR sp_args
, sp_refs
;
3042 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3044 struct riscv_arg_info
*arg_info
=
3045 (struct riscv_arg_info
*) alloca (nargs
* sizeof (struct riscv_arg_info
));
3047 struct riscv_call_info
call_info (gdbarch
);
3051 struct type
*ftype
= check_typedef (value_type (function
));
3053 if (ftype
->code () == TYPE_CODE_PTR
)
3054 ftype
= check_typedef (ftype
->target_type ());
3056 /* We'll use register $a0 if we're returning a struct. */
3057 if (return_method
== return_method_struct
)
3058 ++call_info
.int_regs
.next_regnum
;
3060 for (i
= 0; i
< nargs
; ++i
)
3062 struct value
*arg_value
;
3063 struct type
*arg_type
;
3064 struct riscv_arg_info
*info
= &arg_info
[i
];
3066 arg_value
= args
[i
];
3067 arg_type
= check_typedef (value_type (arg_value
));
3069 riscv_arg_location (gdbarch
, info
, &call_info
, arg_type
,
3070 ftype
->has_varargs () && i
>= ftype
->num_fields ());
3072 if (info
->type
!= arg_type
)
3073 arg_value
= value_cast (info
->type
, arg_value
);
3074 info
->contents
= value_contents (arg_value
).data ();
3077 /* Adjust the stack pointer and align it. */
3078 sp
= sp_refs
= align_down (sp
- call_info
.memory
.ref_offset
, SP_ALIGNMENT
);
3079 sp
= sp_args
= align_down (sp
- call_info
.memory
.arg_offset
, SP_ALIGNMENT
);
3081 if (riscv_debug_infcall
> 0)
3083 gdb_printf (gdb_stdlog
, "dummy call args:\n");
3084 gdb_printf (gdb_stdlog
, ": floating point ABI %s in use\n",
3085 (riscv_has_fp_abi (gdbarch
) ? "is" : "is not"));
3086 gdb_printf (gdb_stdlog
, ": xlen: %d\n: flen: %d\n",
3087 call_info
.xlen
, call_info
.flen
);
3088 if (return_method
== return_method_struct
)
3089 gdb_printf (gdb_stdlog
,
3090 "[*] struct return pointer in register $A0\n");
3091 for (i
= 0; i
< nargs
; ++i
)
3093 struct riscv_arg_info
*info
= &arg_info
[i
];
3095 gdb_printf (gdb_stdlog
, "[%2d] ", i
);
3096 riscv_print_arg_location (gdb_stdlog
, gdbarch
, info
, sp_refs
, sp_args
);
3097 gdb_printf (gdb_stdlog
, "\n");
3099 if (call_info
.memory
.arg_offset
> 0
3100 || call_info
.memory
.ref_offset
> 0)
3102 gdb_printf (gdb_stdlog
, " Original sp: %s\n",
3103 core_addr_to_string (osp
));
3104 gdb_printf (gdb_stdlog
, "Stack required (for args): 0x%x\n",
3105 call_info
.memory
.arg_offset
);
3106 gdb_printf (gdb_stdlog
, "Stack required (for refs): 0x%x\n",
3107 call_info
.memory
.ref_offset
);
3108 gdb_printf (gdb_stdlog
, " Stack allocated: %s\n",
3109 core_addr_to_string_nz (osp
- sp
));
3113 /* Now load the argument into registers, or onto the stack. */
3115 if (return_method
== return_method_struct
)
3117 gdb_byte buf
[sizeof (LONGEST
)];
3119 store_unsigned_integer (buf
, call_info
.xlen
, byte_order
, struct_addr
);
3120 regcache
->cooked_write (RISCV_A0_REGNUM
, buf
);
3123 for (i
= 0; i
< nargs
; ++i
)
3126 int second_arg_length
= 0;
3127 const gdb_byte
*second_arg_data
;
3128 struct riscv_arg_info
*info
= &arg_info
[i
];
3130 gdb_assert (info
->length
> 0);
3132 switch (info
->argloc
[0].loc_type
)
3134 case riscv_arg_info::location::in_reg
:
3136 gdb_assert (info
->argloc
[0].c_length
<= info
->length
);
3138 riscv_regcache_cooked_write (info
->argloc
[0].loc_data
.regno
,
3140 + info
->argloc
[0].c_offset
),
3141 info
->argloc
[0].c_length
,
3142 regcache
, call_info
.flen
);
3144 (((info
->argloc
[0].c_length
+ info
->argloc
[0].c_offset
) < info
->length
)
3145 ? info
->argloc
[1].c_length
: 0);
3146 second_arg_data
= info
->contents
+ info
->argloc
[1].c_offset
;
3150 case riscv_arg_info::location::on_stack
:
3151 dst
= sp_args
+ info
->argloc
[0].loc_data
.offset
;
3152 write_memory (dst
, info
->contents
, info
->length
);
3153 second_arg_length
= 0;
3156 case riscv_arg_info::location::by_ref
:
3157 dst
= sp_refs
+ info
->argloc
[0].loc_data
.offset
;
3158 write_memory (dst
, info
->contents
, info
->length
);
3160 second_arg_length
= call_info
.xlen
;
3161 second_arg_data
= (gdb_byte
*) &dst
;
3165 gdb_assert_not_reached ("unknown argument location type");
3168 if (second_arg_length
> 0)
3170 switch (info
->argloc
[1].loc_type
)
3172 case riscv_arg_info::location::in_reg
:
3174 gdb_assert ((riscv_is_fp_regno_p (info
->argloc
[1].loc_data
.regno
)
3175 && second_arg_length
<= call_info
.flen
)
3176 || second_arg_length
<= call_info
.xlen
);
3177 riscv_regcache_cooked_write (info
->argloc
[1].loc_data
.regno
,
3180 regcache
, call_info
.flen
);
3184 case riscv_arg_info::location::on_stack
:
3188 arg_addr
= sp_args
+ info
->argloc
[1].loc_data
.offset
;
3189 write_memory (arg_addr
, second_arg_data
, second_arg_length
);
3193 case riscv_arg_info::location::by_ref
:
3195 /* The second location should never be a reference, any
3196 argument being passed by reference just places its address
3197 in the first location and is done. */
3198 error (_("invalid argument location"));
3204 /* Set the dummy return value to bp_addr.
3205 A dummy breakpoint will be setup to execute the call. */
3207 if (riscv_debug_infcall
> 0)
3208 gdb_printf (gdb_stdlog
, ": writing $ra = %s\n",
3209 core_addr_to_string (bp_addr
));
3210 regcache_cooked_write_unsigned (regcache
, RISCV_RA_REGNUM
, bp_addr
);
3212 /* Finally, update the stack pointer. */
3214 if (riscv_debug_infcall
> 0)
3215 gdb_printf (gdb_stdlog
, ": writing $sp = %s\n",
3216 core_addr_to_string (sp
));
3217 regcache_cooked_write_unsigned (regcache
, RISCV_SP_REGNUM
, sp
);
3222 /* Implement the return_value gdbarch method. */
3224 static enum return_value_convention
3225 riscv_return_value (struct gdbarch
*gdbarch
,
3226 struct value
*function
,
3228 struct regcache
*regcache
,
3229 struct value
**read_value
,
3230 const gdb_byte
*writebuf
)
3232 struct riscv_call_info
call_info (gdbarch
);
3233 struct riscv_arg_info info
;
3234 struct type
*arg_type
;
3236 arg_type
= check_typedef (type
);
3237 riscv_arg_location (gdbarch
, &info
, &call_info
, arg_type
, false);
3239 if (riscv_debug_infcall
> 0)
3241 gdb_printf (gdb_stdlog
, "riscv return value:\n");
3242 gdb_printf (gdb_stdlog
, "[R] ");
3243 riscv_print_arg_location (gdb_stdlog
, gdbarch
, &info
, 0, 0);
3244 gdb_printf (gdb_stdlog
, "\n");
3247 if (read_value
!= nullptr || writebuf
!= nullptr)
3249 unsigned int arg_len
;
3250 struct value
*abi_val
;
3251 gdb_byte
*readbuf
= nullptr;
3254 /* We only do one thing at a time. */
3255 gdb_assert (read_value
== nullptr || writebuf
== nullptr);
3257 /* In some cases the argument is not returned as the declared type,
3258 and we need to cast to or from the ABI type in order to
3259 correctly access the argument. When writing to the machine we
3260 do the cast here, when reading from the machine the cast occurs
3261 later, after extracting the value. As the ABI type can be
3262 larger than the declared type, then the read or write buffers
3263 passed in might be too small. Here we ensure that we are using
3264 buffers of sufficient size. */
3265 if (writebuf
!= nullptr)
3267 struct value
*arg_val
;
3269 if (is_fixed_point_type (arg_type
))
3271 /* Convert the argument to the type used to pass
3272 the return value, but being careful to preserve
3273 the fact that the value needs to be returned
3277 unscaled
.read (gdb::make_array_view (writebuf
,
3278 arg_type
->length ()),
3279 type_byte_order (arg_type
),
3280 arg_type
->is_unsigned ());
3281 abi_val
= allocate_value (info
.type
);
3282 unscaled
.write (value_contents_raw (abi_val
),
3283 type_byte_order (info
.type
),
3284 info
.type
->is_unsigned ());
3288 arg_val
= value_from_contents (arg_type
, writebuf
);
3289 abi_val
= value_cast (info
.type
, arg_val
);
3291 writebuf
= value_contents_raw (abi_val
).data ();
3295 abi_val
= allocate_value (info
.type
);
3296 readbuf
= value_contents_raw (abi_val
).data ();
3298 arg_len
= info
.type
->length ();
3300 switch (info
.argloc
[0].loc_type
)
3302 /* Return value in register(s). */
3303 case riscv_arg_info::location::in_reg
:
3305 regnum
= info
.argloc
[0].loc_data
.regno
;
3306 gdb_assert (info
.argloc
[0].c_length
<= arg_len
);
3307 gdb_assert (info
.argloc
[0].c_length
3308 <= register_size (gdbarch
, regnum
));
3312 gdb_byte
*ptr
= readbuf
+ info
.argloc
[0].c_offset
;
3313 regcache
->cooked_read_part (regnum
, 0,
3314 info
.argloc
[0].c_length
,
3320 const gdb_byte
*ptr
= writebuf
+ info
.argloc
[0].c_offset
;
3321 riscv_regcache_cooked_write (regnum
, ptr
,
3322 info
.argloc
[0].c_length
,
3323 regcache
, call_info
.flen
);
3326 /* A return value in register can have a second part in a
3328 if (info
.argloc
[1].c_length
> 0)
3330 switch (info
.argloc
[1].loc_type
)
3332 case riscv_arg_info::location::in_reg
:
3333 regnum
= info
.argloc
[1].loc_data
.regno
;
3335 gdb_assert ((info
.argloc
[0].c_length
3336 + info
.argloc
[1].c_length
) <= arg_len
);
3337 gdb_assert (info
.argloc
[1].c_length
3338 <= register_size (gdbarch
, regnum
));
3342 readbuf
+= info
.argloc
[1].c_offset
;
3343 regcache
->cooked_read_part (regnum
, 0,
3344 info
.argloc
[1].c_length
,
3351 = writebuf
+ info
.argloc
[1].c_offset
;
3352 riscv_regcache_cooked_write
3353 (regnum
, ptr
, info
.argloc
[1].c_length
,
3354 regcache
, call_info
.flen
);
3358 case riscv_arg_info::location::by_ref
:
3359 case riscv_arg_info::location::on_stack
:
3361 error (_("invalid argument location"));
3368 /* Return value by reference will have its address in A0. */
3369 case riscv_arg_info::location::by_ref
:
3373 regcache_cooked_read_unsigned (regcache
, RISCV_A0_REGNUM
,
3375 if (read_value
!= nullptr)
3377 abi_val
= value_at_non_lval (type
, addr
);
3378 /* Also reset the expected type, so that the cast
3379 later on is a no-op. If the cast is not a no-op,
3380 and if the return type is variably-sized, then the
3381 type of ABI_VAL will differ from ARG_TYPE due to
3382 dynamic type resolution, and so will most likely
3384 arg_type
= value_type (abi_val
);
3386 if (writebuf
!= nullptr)
3387 write_memory (addr
, writebuf
, info
.length
);
3391 case riscv_arg_info::location::on_stack
:
3393 error (_("invalid argument location"));
3397 /* This completes the cast from abi type back to the declared type
3398 in the case that we are reading from the machine. See the
3399 comment at the head of this block for more details. */
3400 if (read_value
!= nullptr)
3402 if (is_fixed_point_type (arg_type
))
3404 /* Convert abi_val to the actual return type, but
3405 being careful to preserve the fact that abi_val
3409 unscaled
.read (value_contents (abi_val
),
3410 type_byte_order (info
.type
),
3411 info
.type
->is_unsigned ());
3412 *read_value
= allocate_value (arg_type
);
3413 unscaled
.write (value_contents_raw (*read_value
),
3414 type_byte_order (arg_type
),
3415 arg_type
->is_unsigned ());
3418 *read_value
= value_cast (arg_type
, abi_val
);
3422 switch (info
.argloc
[0].loc_type
)
3424 case riscv_arg_info::location::in_reg
:
3425 return RETURN_VALUE_REGISTER_CONVENTION
;
3426 case riscv_arg_info::location::by_ref
:
3427 return RETURN_VALUE_ABI_PRESERVES_ADDRESS
;
3428 case riscv_arg_info::location::on_stack
:
3430 error (_("invalid argument location"));
3434 /* Implement the frame_align gdbarch method. */
3437 riscv_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
3439 return align_down (addr
, 16);
3442 /* Generate, or return the cached frame cache for the RiscV frame
3445 static struct riscv_unwind_cache
*
3446 riscv_frame_cache (frame_info_ptr this_frame
, void **this_cache
)
3448 CORE_ADDR pc
, start_addr
;
3449 struct riscv_unwind_cache
*cache
;
3450 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3453 if ((*this_cache
) != NULL
)
3454 return (struct riscv_unwind_cache
*) *this_cache
;
3456 cache
= FRAME_OBSTACK_ZALLOC (struct riscv_unwind_cache
);
3457 cache
->regs
= trad_frame_alloc_saved_regs (this_frame
);
3458 (*this_cache
) = cache
;
3460 /* Scan the prologue, filling in the cache. */
3461 start_addr
= get_frame_func (this_frame
);
3462 pc
= get_frame_pc (this_frame
);
3463 riscv_scan_prologue (gdbarch
, start_addr
, pc
, cache
);
3465 /* We can now calculate the frame base address. */
3467 = (get_frame_register_unsigned (this_frame
, cache
->frame_base_reg
)
3468 + cache
->frame_base_offset
);
3469 if (riscv_debug_unwinder
)
3470 gdb_printf (gdb_stdlog
, "Frame base is %s ($%s + 0x%x)\n",
3471 core_addr_to_string (cache
->frame_base
),
3472 gdbarch_register_name (gdbarch
,
3473 cache
->frame_base_reg
),
3474 cache
->frame_base_offset
);
3476 /* The prologue scanner sets the address of registers stored to the stack
3477 as the offset of that register from the frame base. The prologue
3478 scanner doesn't know the actual frame base value, and so is unable to
3479 compute the exact address. We do now know the frame base value, so
3480 update the address of registers stored to the stack. */
3481 numregs
= gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
3482 for (regno
= 0; regno
< numregs
; ++regno
)
3484 if (cache
->regs
[regno
].is_addr ())
3485 cache
->regs
[regno
].set_addr (cache
->regs
[regno
].addr ()
3486 + cache
->frame_base
);
3489 /* The previous $pc can be found wherever the $ra value can be found.
3490 The previous $ra value is gone, this would have been stored be the
3491 previous frame if required. */
3492 cache
->regs
[gdbarch_pc_regnum (gdbarch
)] = cache
->regs
[RISCV_RA_REGNUM
];
3493 cache
->regs
[RISCV_RA_REGNUM
].set_unknown ();
3495 /* Build the frame id. */
3496 cache
->this_id
= frame_id_build (cache
->frame_base
, start_addr
);
3498 /* The previous $sp value is the frame base value. */
3499 cache
->regs
[gdbarch_sp_regnum (gdbarch
)].set_value (cache
->frame_base
);
3504 /* Implement the this_id callback for RiscV frame unwinder. */
3507 riscv_frame_this_id (frame_info_ptr this_frame
,
3508 void **prologue_cache
,
3509 struct frame_id
*this_id
)
3511 struct riscv_unwind_cache
*cache
;
3515 cache
= riscv_frame_cache (this_frame
, prologue_cache
);
3516 *this_id
= cache
->this_id
;
3518 catch (const gdb_exception_error
&ex
)
3520 /* Ignore errors, this leaves the frame id as the predefined outer
3521 frame id which terminates the backtrace at this point. */
3525 /* Implement the prev_register callback for RiscV frame unwinder. */
3527 static struct value
*
3528 riscv_frame_prev_register (frame_info_ptr this_frame
,
3529 void **prologue_cache
,
3532 struct riscv_unwind_cache
*cache
;
3534 cache
= riscv_frame_cache (this_frame
, prologue_cache
);
3535 return trad_frame_get_prev_register (this_frame
, cache
->regs
, regnum
);
3538 /* Structure defining the RiscV normal frame unwind functions. Since we
3539 are the fallback unwinder (DWARF unwinder is used first), we use the
3540 default frame sniffer, which always accepts the frame. */
3542 static const struct frame_unwind riscv_frame_unwind
=
3544 /*.name =*/ "riscv prologue",
3545 /*.type =*/ NORMAL_FRAME
,
3546 /*.stop_reason =*/ default_frame_unwind_stop_reason
,
3547 /*.this_id =*/ riscv_frame_this_id
,
3548 /*.prev_register =*/ riscv_frame_prev_register
,
3549 /*.unwind_data =*/ NULL
,
3550 /*.sniffer =*/ default_frame_sniffer
,
3551 /*.dealloc_cache =*/ NULL
,
3552 /*.prev_arch =*/ NULL
,
3555 /* Extract a set of required target features out of ABFD. If ABFD is
3556 nullptr then a RISCV_GDBARCH_FEATURES is returned in its default state. */
3558 static struct riscv_gdbarch_features
3559 riscv_features_from_bfd (const bfd
*abfd
)
3561 struct riscv_gdbarch_features features
;
3563 /* Now try to improve on the defaults by looking at the binary we are
3564 going to execute. We assume the user knows what they are doing and
3565 that the target will match the binary. Remember, this code path is
3566 only used at all if the target hasn't given us a description, so this
3567 is really a last ditched effort to do something sane before giving
3569 if (abfd
!= nullptr && bfd_get_flavour (abfd
) == bfd_target_elf_flavour
)
3571 unsigned char eclass
= elf_elfheader (abfd
)->e_ident
[EI_CLASS
];
3572 int e_flags
= elf_elfheader (abfd
)->e_flags
;
3574 if (eclass
== ELFCLASS32
)
3576 else if (eclass
== ELFCLASS64
)
3579 internal_error (_("unknown ELF header class %d"), eclass
);
3581 if (e_flags
& EF_RISCV_FLOAT_ABI_DOUBLE
)
3583 else if (e_flags
& EF_RISCV_FLOAT_ABI_SINGLE
)
3586 if (e_flags
& EF_RISCV_RVE
)
3588 if (features
.xlen
== 8)
3590 warning (_("64-bit ELF with RV32E flag set! Assuming 32-bit"));
3593 features
.embedded
= true;
3600 /* Find a suitable default target description. Use the contents of INFO,
3601 specifically the bfd object being executed, to guide the selection of a
3602 suitable default target description. */
3604 static const struct target_desc
*
3605 riscv_find_default_target_description (const struct gdbarch_info info
)
3607 /* Extract desired feature set from INFO. */
3608 struct riscv_gdbarch_features features
3609 = riscv_features_from_bfd (info
.abfd
);
3611 /* If the XLEN field is still 0 then we got nothing useful from INFO.BFD,
3612 maybe there was no bfd object. In this case we fall back to a minimal
3613 useful target with no floating point, the x-register size is selected
3614 based on the architecture from INFO. */
3615 if (features
.xlen
== 0)
3616 features
.xlen
= info
.bfd_arch_info
->bits_per_word
== 32 ? 4 : 8;
3618 /* Now build a target description based on the feature set. */
3619 return riscv_lookup_target_description (features
);
3622 /* Add all the RISC-V specific register groups into GDBARCH. */
3625 riscv_add_reggroups (struct gdbarch
*gdbarch
)
3627 reggroup_add (gdbarch
, csr_reggroup
);
3630 /* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
3633 riscv_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
3635 if (reg
<= RISCV_DWARF_REGNUM_X31
)
3636 return RISCV_ZERO_REGNUM
+ (reg
- RISCV_DWARF_REGNUM_X0
);
3638 else if (reg
<= RISCV_DWARF_REGNUM_F31
)
3639 return RISCV_FIRST_FP_REGNUM
+ (reg
- RISCV_DWARF_REGNUM_F0
);
3641 else if (reg
>= RISCV_DWARF_FIRST_CSR
&& reg
<= RISCV_DWARF_LAST_CSR
)
3642 return RISCV_FIRST_CSR_REGNUM
+ (reg
- RISCV_DWARF_FIRST_CSR
);
3644 else if (reg
>= RISCV_DWARF_REGNUM_V0
&& reg
<= RISCV_DWARF_REGNUM_V31
)
3645 return RISCV_V0_REGNUM
+ (reg
- RISCV_DWARF_REGNUM_V0
);
3650 /* Implement the gcc_target_options method. We have to select the arch and abi
3651 from the feature info. We have enough feature info to select the abi, but
3652 not enough info for the arch given all of the possible architecture
3653 extensions. So choose reasonable defaults for now. */
3656 riscv_gcc_target_options (struct gdbarch
*gdbarch
)
3658 int isa_xlen
= riscv_isa_xlen (gdbarch
);
3659 int isa_flen
= riscv_isa_flen (gdbarch
);
3660 int abi_xlen
= riscv_abi_xlen (gdbarch
);
3661 int abi_flen
= riscv_abi_flen (gdbarch
);
3662 std::string target_options
;
3664 target_options
= "-march=rv";
3666 target_options
+= "64";
3668 target_options
+= "32";
3670 target_options
+= "gc";
3671 else if (isa_flen
== 4)
3672 target_options
+= "imafc";
3674 target_options
+= "imac";
3676 target_options
+= " -mabi=";
3678 target_options
+= "lp64";
3680 target_options
+= "ilp32";
3682 target_options
+= "d";
3683 else if (abi_flen
== 4)
3684 target_options
+= "f";
3686 /* The gdb loader doesn't handle link-time relaxation relocations. */
3687 target_options
+= " -mno-relax";
3689 return target_options
;
3692 /* Call back from tdesc_use_registers, called for each unknown register
3693 found in the target description.
3695 See target-description.h (typedef tdesc_unknown_register_ftype) for a
3696 discussion of the arguments and return values. */
3699 riscv_tdesc_unknown_reg (struct gdbarch
*gdbarch
, tdesc_feature
*feature
,
3700 const char *reg_name
, int possible_regnum
)
3702 /* At one point in time GDB had an incorrect default target description
3703 that duplicated the fflags, frm, and fcsr registers in both the FPU
3704 and CSR register sets.
3706 Some targets (QEMU) copied these target descriptions into their source
3707 tree, and so we're now stuck working with some versions of QEMU that
3708 declare the same registers twice.
3710 To make matters worse, if GDB tries to read or write to these
3711 registers using the register number assigned in the FPU feature set,
3712 then QEMU will fail to read the register, so we must use the register
3713 number declared in the CSR feature set.
3715 Luckily, GDB scans the FPU feature first, and then the CSR feature,
3716 which means that the CSR feature will be the one we end up using, the
3717 versions of these registers in the FPU feature will appear as unknown
3718 registers and will be passed through to this code.
3720 To prevent these duplicate registers showing up in any of the register
3721 lists, and to prevent GDB every trying to access the FPU feature copies,
3722 we spot the three problematic registers here, and record the register
3723 number that GDB has assigned them. Then in riscv_register_name we will
3724 return no name for the three duplicates, this hides the duplicates from
3726 if (strcmp (tdesc_feature_name (feature
), riscv_freg_feature
.name ()) == 0)
3728 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
3729 int *regnum_ptr
= nullptr;
3731 if (strcmp (reg_name
, "fflags") == 0)
3732 regnum_ptr
= &tdep
->duplicate_fflags_regnum
;
3733 else if (strcmp (reg_name
, "frm") == 0)
3734 regnum_ptr
= &tdep
->duplicate_frm_regnum
;
3735 else if (strcmp (reg_name
, "fcsr") == 0)
3736 regnum_ptr
= &tdep
->duplicate_fcsr_regnum
;
3738 if (regnum_ptr
!= nullptr)
3740 /* This means the register appears more than twice in the target
3741 description. Just let GDB add this as another register.
3742 We'll have duplicates in the register name list, but there's
3743 not much more we can do. */
3744 if (*regnum_ptr
!= -1)
3747 /* Record the number assigned to this register, then return the
3748 number (so it actually gets assigned to this register). */
3749 *regnum_ptr
= possible_regnum
;
3750 return possible_regnum
;
3754 /* Any unknown registers in the CSR feature are recorded within a single
3755 block so we can easily identify these registers when making choices
3756 about register groups in riscv_register_reggroup_p. */
3757 if (strcmp (tdesc_feature_name (feature
), riscv_csr_feature
.name ()) == 0)
3759 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
3760 if (tdep
->unknown_csrs_first_regnum
== -1)
3761 tdep
->unknown_csrs_first_regnum
= possible_regnum
;
3762 gdb_assert (tdep
->unknown_csrs_first_regnum
3763 + tdep
->unknown_csrs_count
== possible_regnum
);
3764 tdep
->unknown_csrs_count
++;
3765 return possible_regnum
;
3768 /* Some other unknown register. Don't assign this a number now, it will
3769 be assigned a number automatically later by the target description
3774 /* Implement the gnu_triplet_regexp method. A single compiler supports both
3775 32-bit and 64-bit code, and may be named riscv32 or riscv64 or (not
3776 recommended) riscv. */
3779 riscv_gnu_triplet_regexp (struct gdbarch
*gdbarch
)
3781 return "riscv(32|64)?";
3784 /* Initialize the current architecture based on INFO. If possible,
3785 re-use an architecture from ARCHES, which is a list of
3786 architectures already created during this debugging session.
3788 Called e.g. at program startup, when reading a core file, and when
3789 reading a binary file. */
3791 static struct gdbarch
*
3792 riscv_gdbarch_init (struct gdbarch_info info
,
3793 struct gdbarch_list
*arches
)
3795 struct riscv_gdbarch_features features
;
3796 const struct target_desc
*tdesc
= info
.target_desc
;
3798 /* Ensure we always have a target description. */
3799 if (!tdesc_has_registers (tdesc
))
3800 tdesc
= riscv_find_default_target_description (info
);
3801 gdb_assert (tdesc
!= nullptr);
3803 if (riscv_debug_gdbarch
)
3804 gdb_printf (gdb_stdlog
, "Have got a target description\n");
3806 tdesc_arch_data_up tdesc_data
= tdesc_data_alloc ();
3807 std::vector
<riscv_pending_register_alias
> pending_aliases
;
3809 bool valid_p
= (riscv_xreg_feature
.check (tdesc
, tdesc_data
.get (),
3810 &pending_aliases
, &features
)
3811 && riscv_freg_feature
.check (tdesc
, tdesc_data
.get (),
3812 &pending_aliases
, &features
)
3813 && riscv_virtual_feature
.check (tdesc
, tdesc_data
.get (),
3814 &pending_aliases
, &features
)
3815 && riscv_csr_feature
.check (tdesc
, tdesc_data
.get (),
3816 &pending_aliases
, &features
)
3817 && riscv_vector_feature
.check (tdesc
, tdesc_data
.get (),
3818 &pending_aliases
, &features
));
3821 if (riscv_debug_gdbarch
)
3822 gdb_printf (gdb_stdlog
, "Target description is not valid\n");
3826 if (tdesc_found_register (tdesc_data
.get (), RISCV_CSR_FFLAGS_REGNUM
))
3827 features
.has_fflags_reg
= true;
3828 if (tdesc_found_register (tdesc_data
.get (), RISCV_CSR_FRM_REGNUM
))
3829 features
.has_frm_reg
= true;
3830 if (tdesc_found_register (tdesc_data
.get (), RISCV_CSR_FCSR_REGNUM
))
3831 features
.has_fcsr_reg
= true;
3833 /* Have a look at what the supplied (if any) bfd object requires of the
3834 target, then check that this matches with what the target is
3836 struct riscv_gdbarch_features abi_features
3837 = riscv_features_from_bfd (info
.abfd
);
3839 /* If the ABI_FEATURES xlen is 0 then this indicates we got no useful abi
3840 features from the INFO object. In this case we just treat the
3841 hardware features as defining the abi. */
3842 if (abi_features
.xlen
== 0)
3843 abi_features
= features
;
3845 /* In theory a binary compiled for RV32 could run on an RV64 target,
3846 however, this has not been tested in GDB yet, so for now we require
3847 that the requested xlen match the targets xlen. */
3848 if (abi_features
.xlen
!= features
.xlen
)
3849 error (_("bfd requires xlen %d, but target has xlen %d"),
3850 abi_features
.xlen
, features
.xlen
);
3851 /* We do support running binaries compiled for 32-bit float on targets
3852 with 64-bit float, so we only complain if the binary requires more
3853 than the target has available. */
3854 if (abi_features
.flen
> features
.flen
)
3855 error (_("bfd requires flen %d, but target has flen %d"),
3856 abi_features
.flen
, features
.flen
);
3858 /* Find a candidate among the list of pre-declared architectures. */
3859 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
3861 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
3863 /* Check that the feature set of the ARCHES matches the feature set
3864 we are looking for. If it doesn't then we can't reuse this
3866 riscv_gdbarch_tdep
*other_tdep
3867 = gdbarch_tdep
<riscv_gdbarch_tdep
> (arches
->gdbarch
);
3869 if (other_tdep
->isa_features
!= features
3870 || other_tdep
->abi_features
!= abi_features
)
3877 return arches
->gdbarch
;
3879 /* None found, so create a new architecture from the information provided. */
3881 = gdbarch_alloc (&info
, gdbarch_tdep_up (new riscv_gdbarch_tdep
));
3882 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
3884 tdep
->isa_features
= features
;
3885 tdep
->abi_features
= abi_features
;
3887 /* Target data types. */
3888 set_gdbarch_short_bit (gdbarch
, 16);
3889 set_gdbarch_int_bit (gdbarch
, 32);
3890 set_gdbarch_long_bit (gdbarch
, riscv_isa_xlen (gdbarch
) * 8);
3891 set_gdbarch_long_long_bit (gdbarch
, 64);
3892 set_gdbarch_float_bit (gdbarch
, 32);
3893 set_gdbarch_double_bit (gdbarch
, 64);
3894 set_gdbarch_long_double_bit (gdbarch
, 128);
3895 set_gdbarch_long_double_format (gdbarch
, floatformats_ieee_quad
);
3896 set_gdbarch_ptr_bit (gdbarch
, riscv_isa_xlen (gdbarch
) * 8);
3897 set_gdbarch_char_signed (gdbarch
, 0);
3898 set_gdbarch_type_align (gdbarch
, riscv_type_align
);
3900 /* Information about the target architecture. */
3901 set_gdbarch_return_value_as_value (gdbarch
, riscv_return_value
);
3902 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, riscv_breakpoint_kind_from_pc
);
3903 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, riscv_sw_breakpoint_from_kind
);
3904 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
3906 /* Functions to analyze frames. */
3907 set_gdbarch_skip_prologue (gdbarch
, riscv_skip_prologue
);
3908 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
3909 set_gdbarch_frame_align (gdbarch
, riscv_frame_align
);
3911 /* Functions handling dummy frames. */
3912 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
3913 set_gdbarch_push_dummy_code (gdbarch
, riscv_push_dummy_code
);
3914 set_gdbarch_push_dummy_call (gdbarch
, riscv_push_dummy_call
);
3916 /* Frame unwinders. Use DWARF debug info if available, otherwise use our own
3918 dwarf2_append_unwinders (gdbarch
);
3919 frame_unwind_append_unwinder (gdbarch
, &riscv_frame_unwind
);
3921 /* Register architecture. */
3922 riscv_add_reggroups (gdbarch
);
3924 /* Internal <-> external register number maps. */
3925 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, riscv_dwarf_reg_to_regnum
);
3927 /* We reserve all possible register numbers for the known registers.
3928 This means the target description mechanism will add any target
3929 specific registers after this number. This helps make debugging GDB
3930 just a little easier. */
3931 set_gdbarch_num_regs (gdbarch
, RISCV_LAST_REGNUM
+ 1);
3933 /* Some specific register numbers GDB likes to know about. */
3934 set_gdbarch_sp_regnum (gdbarch
, RISCV_SP_REGNUM
);
3935 set_gdbarch_pc_regnum (gdbarch
, RISCV_PC_REGNUM
);
3937 set_gdbarch_print_registers_info (gdbarch
, riscv_print_registers_info
);
3939 set_tdesc_pseudo_register_name (gdbarch
, riscv_pseudo_register_name
);
3940 set_tdesc_pseudo_register_type (gdbarch
, riscv_pseudo_register_type
);
3941 set_tdesc_pseudo_register_reggroup_p (gdbarch
,
3942 riscv_pseudo_register_reggroup_p
);
3943 set_gdbarch_pseudo_register_read (gdbarch
, riscv_pseudo_register_read
);
3944 set_gdbarch_pseudo_register_write (gdbarch
, riscv_pseudo_register_write
);
3946 /* Finalise the target description registers. */
3947 tdesc_use_registers (gdbarch
, tdesc
, std::move (tdesc_data
),
3948 riscv_tdesc_unknown_reg
);
3950 /* Calculate the number of pseudo registers we need. The fflags and frm
3951 registers are sub-fields of the fcsr CSR register (csr3). However,
3952 these registers can also be accessed directly as separate CSR
3953 registers (fflags is csr1, and frm is csr2). And so, some targets
3954 might choose to offer direct access to all three registers in the
3955 target description, while other targets might choose to only offer
3958 As we scan the target description we spot which of fcsr, fflags, and
3959 frm are available. If fcsr is available but either of fflags and/or
3960 frm are not available, then we add pseudo-registers to provide the
3961 missing functionality.
3963 This has to be done after the call to tdesc_use_registers as we don't
3964 know the final register number until after that call, and the pseudo
3965 register numbers need to be after the physical registers. */
3966 int num_pseudo_regs
= 0;
3967 int next_pseudo_regnum
= gdbarch_num_regs (gdbarch
);
3969 if (features
.has_fflags_reg
)
3970 tdep
->fflags_regnum
= RISCV_CSR_FFLAGS_REGNUM
;
3971 else if (features
.has_fcsr_reg
)
3973 tdep
->fflags_regnum
= next_pseudo_regnum
;
3974 pending_aliases
.emplace_back ("csr1", (void *) &tdep
->fflags_regnum
);
3975 next_pseudo_regnum
++;
3979 if (features
.has_frm_reg
)
3980 tdep
->frm_regnum
= RISCV_CSR_FRM_REGNUM
;
3981 else if (features
.has_fcsr_reg
)
3983 tdep
->frm_regnum
= next_pseudo_regnum
;
3984 pending_aliases
.emplace_back ("csr2", (void *) &tdep
->frm_regnum
);
3985 next_pseudo_regnum
++;
3989 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudo_regs
);
3991 /* Override the register type callback setup by the target description
3992 mechanism. This allows us to provide special type for floating point
3994 set_gdbarch_register_type (gdbarch
, riscv_register_type
);
3996 /* Override the register name callback setup by the target description
3997 mechanism. This allows us to force our preferred names for the
3998 registers, no matter what the target description called them. */
3999 set_gdbarch_register_name (gdbarch
, riscv_register_name
);
4001 /* Tell GDB which RISC-V registers are read-only. */
4002 set_gdbarch_cannot_store_register (gdbarch
, riscv_cannot_store_register
);
4004 /* Override the register group callback setup by the target description
4005 mechanism. This allows us to force registers into the groups we
4006 want, ignoring what the target tells us. */
4007 set_gdbarch_register_reggroup_p (gdbarch
, riscv_register_reggroup_p
);
4009 /* Create register aliases for alternative register names. We only
4010 create aliases for registers which were mentioned in the target
4012 for (const auto &alias
: pending_aliases
)
4013 alias
.create (gdbarch
);
4015 /* Compile command hooks. */
4016 set_gdbarch_gcc_target_options (gdbarch
, riscv_gcc_target_options
);
4017 set_gdbarch_gnu_triplet_regexp (gdbarch
, riscv_gnu_triplet_regexp
);
4019 /* Disassembler options support. */
4020 set_gdbarch_valid_disassembler_options (gdbarch
,
4021 disassembler_options_riscv ());
4022 set_gdbarch_disassembler_options (gdbarch
, &riscv_disassembler_options
);
4024 /* Hook in OS ABI-specific overrides, if they have been registered. */
4025 gdbarch_init_osabi (info
, gdbarch
);
4027 register_riscv_ravenscar_ops (gdbarch
);
4032 /* This decodes the current instruction and determines the address of the
4033 next instruction. */
4036 riscv_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
4038 struct gdbarch
*gdbarch
= regcache
->arch ();
4039 const riscv_gdbarch_tdep
*tdep
4040 = gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
4041 struct riscv_insn insn
;
4044 insn
.decode (gdbarch
, pc
);
4045 next_pc
= pc
+ insn
.length ();
4047 if (insn
.opcode () == riscv_insn::JAL
)
4048 next_pc
= pc
+ insn
.imm_signed ();
4049 else if (insn
.opcode () == riscv_insn::JALR
)
4052 regcache
->cooked_read (insn
.rs1 (), &source
);
4053 next_pc
= (source
+ insn
.imm_signed ()) & ~(CORE_ADDR
) 0x1;
4055 else if (insn
.opcode () == riscv_insn::BEQ
)
4058 regcache
->cooked_read (insn
.rs1 (), &src1
);
4059 regcache
->cooked_read (insn
.rs2 (), &src2
);
4061 next_pc
= pc
+ insn
.imm_signed ();
4063 else if (insn
.opcode () == riscv_insn::BNE
)
4066 regcache
->cooked_read (insn
.rs1 (), &src1
);
4067 regcache
->cooked_read (insn
.rs2 (), &src2
);
4069 next_pc
= pc
+ insn
.imm_signed ();
4071 else if (insn
.opcode () == riscv_insn::BLT
)
4074 regcache
->cooked_read (insn
.rs1 (), &src1
);
4075 regcache
->cooked_read (insn
.rs2 (), &src2
);
4077 next_pc
= pc
+ insn
.imm_signed ();
4079 else if (insn
.opcode () == riscv_insn::BGE
)
4082 regcache
->cooked_read (insn
.rs1 (), &src1
);
4083 regcache
->cooked_read (insn
.rs2 (), &src2
);
4085 next_pc
= pc
+ insn
.imm_signed ();
4087 else if (insn
.opcode () == riscv_insn::BLTU
)
4089 ULONGEST src1
, src2
;
4090 regcache
->cooked_read (insn
.rs1 (), &src1
);
4091 regcache
->cooked_read (insn
.rs2 (), &src2
);
4093 next_pc
= pc
+ insn
.imm_signed ();
4095 else if (insn
.opcode () == riscv_insn::BGEU
)
4097 ULONGEST src1
, src2
;
4098 regcache
->cooked_read (insn
.rs1 (), &src1
);
4099 regcache
->cooked_read (insn
.rs2 (), &src2
);
4101 next_pc
= pc
+ insn
.imm_signed ();
4103 else if (insn
.opcode () == riscv_insn::ECALL
)
4105 if (tdep
->syscall_next_pc
!= nullptr)
4106 next_pc
= tdep
->syscall_next_pc (get_current_frame ());
4112 /* We can't put a breakpoint in the middle of a lr/sc atomic sequence, so look
4113 for the end of the sequence and put the breakpoint there. */
4116 riscv_next_pc_atomic_sequence (struct regcache
*regcache
, CORE_ADDR pc
,
4119 struct gdbarch
*gdbarch
= regcache
->arch ();
4120 struct riscv_insn insn
;
4121 CORE_ADDR cur_step_pc
= pc
;
4122 CORE_ADDR last_addr
= 0;
4124 /* First instruction has to be a load reserved. */
4125 insn
.decode (gdbarch
, cur_step_pc
);
4126 if (insn
.opcode () != riscv_insn::LR
)
4128 cur_step_pc
= cur_step_pc
+ insn
.length ();
4130 /* Next instruction should be branch to exit. */
4131 insn
.decode (gdbarch
, cur_step_pc
);
4132 if (insn
.opcode () != riscv_insn::BNE
)
4134 last_addr
= cur_step_pc
+ insn
.imm_signed ();
4135 cur_step_pc
= cur_step_pc
+ insn
.length ();
4137 /* Next instruction should be store conditional. */
4138 insn
.decode (gdbarch
, cur_step_pc
);
4139 if (insn
.opcode () != riscv_insn::SC
)
4141 cur_step_pc
= cur_step_pc
+ insn
.length ();
4143 /* Next instruction should be branch to start. */
4144 insn
.decode (gdbarch
, cur_step_pc
);
4145 if (insn
.opcode () != riscv_insn::BNE
)
4147 if (pc
!= (cur_step_pc
+ insn
.imm_signed ()))
4149 cur_step_pc
= cur_step_pc
+ insn
.length ();
4151 /* We should now be at the end of the sequence. */
4152 if (cur_step_pc
!= last_addr
)
4155 *next_pc
= cur_step_pc
;
4159 /* This is called just before we want to resume the inferior, if we want to
4160 single-step it but there is no hardware or kernel single-step support. We
4161 find the target of the coming instruction and breakpoint it. */
4163 std::vector
<CORE_ADDR
>
4164 riscv_software_single_step (struct regcache
*regcache
)
4166 CORE_ADDR pc
, next_pc
;
4168 pc
= regcache_read_pc (regcache
);
4170 if (riscv_next_pc_atomic_sequence (regcache
, pc
, &next_pc
))
4173 next_pc
= riscv_next_pc (regcache
, pc
);
4178 /* Create RISC-V specific reggroups. */
4181 riscv_init_reggroups ()
4183 csr_reggroup
= reggroup_new ("csr", USER_REGGROUP
);
4186 /* See riscv-tdep.h. */
4189 riscv_supply_regset (const struct regset
*regset
,
4190 struct regcache
*regcache
, int regnum
,
4191 const void *regs
, size_t len
)
4193 regcache
->supply_regset (regset
, regnum
, regs
, len
);
4195 if (regnum
== -1 || regnum
== RISCV_ZERO_REGNUM
)
4196 regcache
->raw_supply_zeroed (RISCV_ZERO_REGNUM
);
4198 struct gdbarch
*gdbarch
= regcache
->arch ();
4199 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
4202 || regnum
== tdep
->fflags_regnum
4203 || regnum
== tdep
->frm_regnum
)
4205 int fcsr_regnum
= RISCV_CSR_FCSR_REGNUM
;
4207 /* Ensure that FCSR has been read into REGCACHE. */
4209 regcache
->supply_regset (regset
, fcsr_regnum
, regs
, len
);
4211 /* Grab the FCSR value if it is now in the regcache. We must check
4212 the status first as, if the register was not supplied by REGSET,
4213 this call will trigger a recursive attempt to fetch the
4215 if (regcache
->get_register_status (fcsr_regnum
) == REG_VALID
)
4217 /* If we have an fcsr register then we should have fflags and frm
4218 too, either provided by the target, or provided as a pseudo
4220 gdb_assert (tdep
->fflags_regnum
>= 0);
4221 gdb_assert (tdep
->frm_regnum
>= 0);
4224 regcache
->raw_read (fcsr_regnum
, &fcsr_val
);
4226 /* Extract the fflags and frm values. */
4227 ULONGEST fflags_val
= fcsr_val
& 0x1f;
4228 ULONGEST frm_val
= (fcsr_val
>> 5) & 0x7;
4230 /* And supply these if needed. We can only supply real
4231 registers, so don't try to supply fflags or frm if they are
4232 implemented as pseudo-registers. */
4233 if ((regnum
== -1 || regnum
== tdep
->fflags_regnum
)
4234 && tdep
->fflags_regnum
< gdbarch_num_regs (gdbarch
))
4235 regcache
->raw_supply_integer (tdep
->fflags_regnum
,
4236 (gdb_byte
*) &fflags_val
,
4237 sizeof (fflags_val
),
4238 /* is_signed */ false);
4240 if ((regnum
== -1 || regnum
== tdep
->frm_regnum
)
4241 && tdep
->frm_regnum
< gdbarch_num_regs (gdbarch
))
4242 regcache
->raw_supply_integer (tdep
->frm_regnum
,
4243 (gdb_byte
*)&frm_val
,
4244 sizeof (fflags_val
),
4245 /* is_signed */ false);
4250 void _initialize_riscv_tdep ();
4252 _initialize_riscv_tdep ()
4254 riscv_init_reggroups ();
4256 gdbarch_register (bfd_arch_riscv
, riscv_gdbarch_init
, NULL
);
4258 /* Add root prefix command for all "set debug riscv" and "show debug
4260 add_setshow_prefix_cmd ("riscv", no_class
,
4261 _("RISC-V specific debug commands."),
4262 _("RISC-V specific debug commands."),
4263 &setdebugriscvcmdlist
, &showdebugriscvcmdlist
,
4264 &setdebuglist
, &showdebuglist
);
4266 add_setshow_zuinteger_cmd ("breakpoints", class_maintenance
,
4267 &riscv_debug_breakpoints
, _("\
4268 Set riscv breakpoint debugging."), _("\
4269 Show riscv breakpoint debugging."), _("\
4270 When non-zero, print debugging information for the riscv specific parts\n\
4271 of the breakpoint mechanism."),
4273 show_riscv_debug_variable
,
4274 &setdebugriscvcmdlist
, &showdebugriscvcmdlist
);
4276 add_setshow_zuinteger_cmd ("infcall", class_maintenance
,
4277 &riscv_debug_infcall
, _("\
4278 Set riscv inferior call debugging."), _("\
4279 Show riscv inferior call debugging."), _("\
4280 When non-zero, print debugging information for the riscv specific parts\n\
4281 of the inferior call mechanism."),
4283 show_riscv_debug_variable
,
4284 &setdebugriscvcmdlist
, &showdebugriscvcmdlist
);
4286 add_setshow_zuinteger_cmd ("unwinder", class_maintenance
,
4287 &riscv_debug_unwinder
, _("\
4288 Set riscv stack unwinding debugging."), _("\
4289 Show riscv stack unwinding debugging."), _("\
4290 When non-zero, print debugging information for the riscv specific parts\n\
4291 of the stack unwinding mechanism."),
4293 show_riscv_debug_variable
,
4294 &setdebugriscvcmdlist
, &showdebugriscvcmdlist
);
4296 add_setshow_zuinteger_cmd ("gdbarch", class_maintenance
,
4297 &riscv_debug_gdbarch
, _("\
4298 Set riscv gdbarch initialisation debugging."), _("\
4299 Show riscv gdbarch initialisation debugging."), _("\
4300 When non-zero, print debugging information for the riscv gdbarch\n\
4301 initialisation process."),
4303 show_riscv_debug_variable
,
4304 &setdebugriscvcmdlist
, &showdebugriscvcmdlist
);
4306 /* Add root prefix command for all "set riscv" and "show riscv" commands. */
4307 add_setshow_prefix_cmd ("riscv", no_class
,
4308 _("RISC-V specific commands."),
4309 _("RISC-V specific commands."),
4310 &setriscvcmdlist
, &showriscvcmdlist
,
4311 &setlist
, &showlist
);
4314 use_compressed_breakpoints
= AUTO_BOOLEAN_AUTO
;
4315 add_setshow_auto_boolean_cmd ("use-compressed-breakpoints", no_class
,
4316 &use_compressed_breakpoints
,
4318 Set debugger's use of compressed breakpoints."), _(" \
4319 Show debugger's use of compressed breakpoints."), _("\
4320 Debugging compressed code requires compressed breakpoints to be used. If\n\
4321 left to 'auto' then gdb will use them if the existing instruction is a\n\
4322 compressed instruction. If that doesn't give the correct behavior, then\n\
4323 this option can be used."),
4325 show_use_compressed_breakpoints
,