1 /* Target-dependent code for the RISC-V architecture, for GDB.
3 Copyright (C) 2018-2022 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
32 #include "arch-utils.h"
35 #include "riscv-tdep.h"
37 #include "reggroups.h"
38 #include "opcode/riscv.h"
39 #include "elf/riscv.h"
43 #include "frame-unwind.h"
44 #include "frame-base.h"
45 #include "trad-frame.h"
47 #include "floatformat.h"
49 #include "target-descriptions.h"
50 #include "dwarf2/frame.h"
51 #include "user-regs.h"
53 #include "gdbsupport/common-defs.h"
54 #include "opcode/riscv-opc.h"
55 #include "cli/cli-decode.h"
56 #include "observable.h"
57 #include "prologue-value.h"
58 #include "arch/riscv.h"
59 #include "riscv-ravenscar-thread.h"
61 /* The stack must be 16-byte aligned. */
62 #define SP_ALIGNMENT 16
64 /* The biggest alignment that the target supports. */
65 #define BIGGEST_ALIGNMENT 16
67 /* Define a series of is_XXX_insn functions to check if the value INSN
68 is an instance of instruction XXX. */
69 #define DECLARE_INSN(INSN_NAME, INSN_MATCH, INSN_MASK) \
70 static inline bool is_ ## INSN_NAME ## _insn (long insn) \
72 return (insn & INSN_MASK) == INSN_MATCH; \
74 #include "opcode/riscv-opc.h"
77 /* When this is set to non-zero debugging information about breakpoint
78 kinds will be printed. */
80 static unsigned int riscv_debug_breakpoints
= 0;
82 /* When this is set to non-zero debugging information about inferior calls
85 static unsigned int riscv_debug_infcall
= 0;
87 /* When this is set to non-zero debugging information about stack unwinding
90 static unsigned int riscv_debug_unwinder
= 0;
92 /* When this is set to non-zero debugging information about gdbarch
93 initialisation will be printed. */
95 static unsigned int riscv_debug_gdbarch
= 0;
97 /* The names of the RISC-V target description features. */
98 const char *riscv_feature_name_csr
= "org.gnu.gdb.riscv.csr";
99 static const char *riscv_feature_name_cpu
= "org.gnu.gdb.riscv.cpu";
100 static const char *riscv_feature_name_fpu
= "org.gnu.gdb.riscv.fpu";
101 static const char *riscv_feature_name_virtual
= "org.gnu.gdb.riscv.virtual";
102 static const char *riscv_feature_name_vector
= "org.gnu.gdb.riscv.vector";
104 /* The current set of options to be passed to the disassembler. */
105 static char *riscv_disassembler_options
;
107 /* Cached information about a frame. */
109 struct riscv_unwind_cache
111 /* The register from which we can calculate the frame base. This is
112 usually $sp or $fp. */
115 /* The offset from the current value in register FRAME_BASE_REG to the
116 actual frame base address. */
117 int frame_base_offset
;
119 /* Information about previous register values. */
120 trad_frame_saved_reg
*regs
;
122 /* The id for this frame. */
123 struct frame_id this_id
;
125 /* The base (stack) address for this frame. This is the stack pointer
126 value on entry to this frame before any adjustments are made. */
127 CORE_ADDR frame_base
;
130 /* RISC-V specific register group for CSRs. */
132 static const reggroup
*csr_reggroup
= nullptr;
134 /* Callback function for user_reg_add. */
136 static struct value
*
137 value_of_riscv_user_reg (struct frame_info
*frame
, const void *baton
)
139 const int *reg_p
= (const int *) baton
;
140 return value_of_register (*reg_p
, frame
);
143 /* Information about a register alias that needs to be set up for this
144 target. These are collected when the target's XML description is
145 analysed, and then processed later, once the gdbarch has been created. */
147 class riscv_pending_register_alias
152 riscv_pending_register_alias (const char *name
, const void *baton
)
157 /* Convert this into a user register for GDBARCH. */
159 void create (struct gdbarch
*gdbarch
) const
161 user_reg_add (gdbarch
, m_name
, value_of_riscv_user_reg
, m_baton
);
165 /* The name for this alias. */
168 /* The baton value for passing to user_reg_add. This must point to some
169 data that will live for at least as long as the gdbarch object to
170 which the user register is attached. */
174 /* A set of registers that we expect to find in a tdesc_feature. These
175 are use in RISCV_GDBARCH_INIT when processing the target description. */
177 struct riscv_register_feature
179 explicit riscv_register_feature (const char *feature_name
)
180 : m_feature_name (feature_name
)
183 riscv_register_feature () = delete;
184 DISABLE_COPY_AND_ASSIGN (riscv_register_feature
);
186 /* Information for a single register. */
189 /* The GDB register number for this register. */
192 /* List of names for this register. The first name in this list is the
193 preferred name, the name GDB should use when describing this
195 std::vector
<const char *> names
;
197 /* Look in FEATURE for a register with a name from this classes names
198 list. If the register is found then register its number with
199 TDESC_DATA and add all its aliases to the ALIASES list.
200 PREFER_FIRST_NAME_P is used when deciding which aliases to create. */
201 bool check (struct tdesc_arch_data
*tdesc_data
,
202 const struct tdesc_feature
*feature
,
203 bool prefer_first_name_p
,
204 std::vector
<riscv_pending_register_alias
> *aliases
) const;
207 /* Return the name of this feature. */
208 const char *name () const
209 { return m_feature_name
; }
213 /* Return a target description feature extracted from TDESC for this
214 register feature. Will return nullptr if there is no feature in TDESC
215 with the name M_FEATURE_NAME. */
216 const struct tdesc_feature
*tdesc_feature (const struct target_desc
*tdesc
) const
218 return tdesc_find_feature (tdesc
, name ());
221 /* List of all the registers that we expect that we might find in this
223 std::vector
<struct register_info
> m_registers
;
227 /* The name for this feature. This is the name used to find this feature
228 within the target description. */
229 const char *m_feature_name
;
232 /* See description in the class declaration above. */
235 riscv_register_feature::register_info::check
236 (struct tdesc_arch_data
*tdesc_data
,
237 const struct tdesc_feature
*feature
,
238 bool prefer_first_name_p
,
239 std::vector
<riscv_pending_register_alias
> *aliases
) const
241 for (const char *name
: this->names
)
243 bool found
= tdesc_numbered_register (feature
, tdesc_data
,
247 /* We know that the target description mentions this
248 register. In RISCV_REGISTER_NAME we ensure that GDB
249 always uses the first name for each register, so here we
250 add aliases for all of the remaining names. */
251 int start_index
= prefer_first_name_p
? 1 : 0;
252 for (int i
= start_index
; i
< this->names
.size (); ++i
)
254 const char *alias
= this->names
[i
];
255 if (alias
== name
&& !prefer_first_name_p
)
257 aliases
->emplace_back (alias
, (void *) &this->regnum
);
265 /* Class representing the x-registers feature set. */
267 struct riscv_xreg_feature
: public riscv_register_feature
269 riscv_xreg_feature ()
270 : riscv_register_feature (riscv_feature_name_cpu
)
273 { RISCV_ZERO_REGNUM
+ 0, { "zero", "x0" } },
274 { RISCV_ZERO_REGNUM
+ 1, { "ra", "x1" } },
275 { RISCV_ZERO_REGNUM
+ 2, { "sp", "x2" } },
276 { RISCV_ZERO_REGNUM
+ 3, { "gp", "x3" } },
277 { RISCV_ZERO_REGNUM
+ 4, { "tp", "x4" } },
278 { RISCV_ZERO_REGNUM
+ 5, { "t0", "x5" } },
279 { RISCV_ZERO_REGNUM
+ 6, { "t1", "x6" } },
280 { RISCV_ZERO_REGNUM
+ 7, { "t2", "x7" } },
281 { RISCV_ZERO_REGNUM
+ 8, { "fp", "x8", "s0" } },
282 { RISCV_ZERO_REGNUM
+ 9, { "s1", "x9" } },
283 { RISCV_ZERO_REGNUM
+ 10, { "a0", "x10" } },
284 { RISCV_ZERO_REGNUM
+ 11, { "a1", "x11" } },
285 { RISCV_ZERO_REGNUM
+ 12, { "a2", "x12" } },
286 { RISCV_ZERO_REGNUM
+ 13, { "a3", "x13" } },
287 { RISCV_ZERO_REGNUM
+ 14, { "a4", "x14" } },
288 { RISCV_ZERO_REGNUM
+ 15, { "a5", "x15" } },
289 { RISCV_ZERO_REGNUM
+ 16, { "a6", "x16" } },
290 { RISCV_ZERO_REGNUM
+ 17, { "a7", "x17" } },
291 { RISCV_ZERO_REGNUM
+ 18, { "s2", "x18" } },
292 { RISCV_ZERO_REGNUM
+ 19, { "s3", "x19" } },
293 { RISCV_ZERO_REGNUM
+ 20, { "s4", "x20" } },
294 { RISCV_ZERO_REGNUM
+ 21, { "s5", "x21" } },
295 { RISCV_ZERO_REGNUM
+ 22, { "s6", "x22" } },
296 { RISCV_ZERO_REGNUM
+ 23, { "s7", "x23" } },
297 { RISCV_ZERO_REGNUM
+ 24, { "s8", "x24" } },
298 { RISCV_ZERO_REGNUM
+ 25, { "s9", "x25" } },
299 { RISCV_ZERO_REGNUM
+ 26, { "s10", "x26" } },
300 { RISCV_ZERO_REGNUM
+ 27, { "s11", "x27" } },
301 { RISCV_ZERO_REGNUM
+ 28, { "t3", "x28" } },
302 { RISCV_ZERO_REGNUM
+ 29, { "t4", "x29" } },
303 { RISCV_ZERO_REGNUM
+ 30, { "t5", "x30" } },
304 { RISCV_ZERO_REGNUM
+ 31, { "t6", "x31" } },
305 { RISCV_ZERO_REGNUM
+ 32, { "pc" } }
309 /* Return the preferred name for the register with gdb register number
310 REGNUM, which must be in the inclusive range RISCV_ZERO_REGNUM to
312 const char *register_name (int regnum
) const
314 gdb_assert (regnum
>= RISCV_ZERO_REGNUM
&& regnum
<= m_registers
.size ());
315 return m_registers
[regnum
].names
[0];
318 /* Check this feature within TDESC, record the registers from this
319 feature into TDESC_DATA and update ALIASES and FEATURES. */
320 bool check (const struct target_desc
*tdesc
,
321 struct tdesc_arch_data
*tdesc_data
,
322 std::vector
<riscv_pending_register_alias
> *aliases
,
323 struct riscv_gdbarch_features
*features
) const
325 const struct tdesc_feature
*feature_cpu
= tdesc_feature (tdesc
);
327 if (feature_cpu
== nullptr)
330 bool seen_an_optional_reg_p
= false;
331 for (const auto ®
: m_registers
)
333 bool found
= reg
.check (tdesc_data
, feature_cpu
, true, aliases
);
335 bool is_optional_reg_p
= (reg
.regnum
>= RISCV_ZERO_REGNUM
+ 16
336 && reg
.regnum
< RISCV_ZERO_REGNUM
+ 32);
338 if (!found
&& (!is_optional_reg_p
|| seen_an_optional_reg_p
))
340 else if (found
&& is_optional_reg_p
)
341 seen_an_optional_reg_p
= true;
344 /* Check that all of the core cpu registers have the same bitsize. */
345 int xlen_bitsize
= tdesc_register_bitsize (feature_cpu
, "pc");
348 for (auto &tdesc_reg
: feature_cpu
->registers
)
349 valid_p
&= (tdesc_reg
->bitsize
== xlen_bitsize
);
351 features
->xlen
= (xlen_bitsize
/ 8);
352 features
->embedded
= !seen_an_optional_reg_p
;
358 /* An instance of the x-register feature set. */
360 static const struct riscv_xreg_feature riscv_xreg_feature
;
362 /* Class representing the f-registers feature set. */
364 struct riscv_freg_feature
: public riscv_register_feature
366 riscv_freg_feature ()
367 : riscv_register_feature (riscv_feature_name_fpu
)
370 { RISCV_FIRST_FP_REGNUM
+ 0, { "ft0", "f0" } },
371 { RISCV_FIRST_FP_REGNUM
+ 1, { "ft1", "f1" } },
372 { RISCV_FIRST_FP_REGNUM
+ 2, { "ft2", "f2" } },
373 { RISCV_FIRST_FP_REGNUM
+ 3, { "ft3", "f3" } },
374 { RISCV_FIRST_FP_REGNUM
+ 4, { "ft4", "f4" } },
375 { RISCV_FIRST_FP_REGNUM
+ 5, { "ft5", "f5" } },
376 { RISCV_FIRST_FP_REGNUM
+ 6, { "ft6", "f6" } },
377 { RISCV_FIRST_FP_REGNUM
+ 7, { "ft7", "f7" } },
378 { RISCV_FIRST_FP_REGNUM
+ 8, { "fs0", "f8" } },
379 { RISCV_FIRST_FP_REGNUM
+ 9, { "fs1", "f9" } },
380 { RISCV_FIRST_FP_REGNUM
+ 10, { "fa0", "f10" } },
381 { RISCV_FIRST_FP_REGNUM
+ 11, { "fa1", "f11" } },
382 { RISCV_FIRST_FP_REGNUM
+ 12, { "fa2", "f12" } },
383 { RISCV_FIRST_FP_REGNUM
+ 13, { "fa3", "f13" } },
384 { RISCV_FIRST_FP_REGNUM
+ 14, { "fa4", "f14" } },
385 { RISCV_FIRST_FP_REGNUM
+ 15, { "fa5", "f15" } },
386 { RISCV_FIRST_FP_REGNUM
+ 16, { "fa6", "f16" } },
387 { RISCV_FIRST_FP_REGNUM
+ 17, { "fa7", "f17" } },
388 { RISCV_FIRST_FP_REGNUM
+ 18, { "fs2", "f18" } },
389 { RISCV_FIRST_FP_REGNUM
+ 19, { "fs3", "f19" } },
390 { RISCV_FIRST_FP_REGNUM
+ 20, { "fs4", "f20" } },
391 { RISCV_FIRST_FP_REGNUM
+ 21, { "fs5", "f21" } },
392 { RISCV_FIRST_FP_REGNUM
+ 22, { "fs6", "f22" } },
393 { RISCV_FIRST_FP_REGNUM
+ 23, { "fs7", "f23" } },
394 { RISCV_FIRST_FP_REGNUM
+ 24, { "fs8", "f24" } },
395 { RISCV_FIRST_FP_REGNUM
+ 25, { "fs9", "f25" } },
396 { RISCV_FIRST_FP_REGNUM
+ 26, { "fs10", "f26" } },
397 { RISCV_FIRST_FP_REGNUM
+ 27, { "fs11", "f27" } },
398 { RISCV_FIRST_FP_REGNUM
+ 28, { "ft8", "f28" } },
399 { RISCV_FIRST_FP_REGNUM
+ 29, { "ft9", "f29" } },
400 { RISCV_FIRST_FP_REGNUM
+ 30, { "ft10", "f30" } },
401 { RISCV_FIRST_FP_REGNUM
+ 31, { "ft11", "f31" } },
402 { RISCV_CSR_FFLAGS_REGNUM
, { "fflags", "csr1" } },
403 { RISCV_CSR_FRM_REGNUM
, { "frm", "csr2" } },
404 { RISCV_CSR_FCSR_REGNUM
, { "fcsr", "csr3" } },
408 /* Return the preferred name for the register with gdb register number
409 REGNUM, which must be in the inclusive range RISCV_FIRST_FP_REGNUM to
410 RISCV_LAST_FP_REGNUM. */
411 const char *register_name (int regnum
) const
413 gdb_static_assert (RISCV_LAST_FP_REGNUM
== RISCV_FIRST_FP_REGNUM
+ 31);
414 gdb_assert (regnum
>= RISCV_FIRST_FP_REGNUM
415 && regnum
<= RISCV_LAST_FP_REGNUM
);
416 regnum
-= RISCV_FIRST_FP_REGNUM
;
417 return m_registers
[regnum
].names
[0];
420 /* Check this feature within TDESC, record the registers from this
421 feature into TDESC_DATA and update ALIASES and FEATURES. */
422 bool check (const struct target_desc
*tdesc
,
423 struct tdesc_arch_data
*tdesc_data
,
424 std::vector
<riscv_pending_register_alias
> *aliases
,
425 struct riscv_gdbarch_features
*features
) const
427 const struct tdesc_feature
*feature_fpu
= tdesc_feature (tdesc
);
429 /* It's fine if this feature is missing. Update the architecture
430 feature set and return. */
431 if (feature_fpu
== nullptr)
437 /* Check all of the floating pointer registers are present. We also
438 check that the floating point CSRs are present too, though if these
439 are missing this is not fatal. */
440 for (const auto ®
: m_registers
)
442 bool found
= reg
.check (tdesc_data
, feature_fpu
, true, aliases
);
444 bool is_ctrl_reg_p
= reg
.regnum
> RISCV_LAST_FP_REGNUM
;
446 if (!found
&& !is_ctrl_reg_p
)
450 /* Look through all of the floating point registers (not the FP CSRs
451 though), and check they all have the same bitsize. Use this bitsize
452 to update the feature set for this gdbarch. */
454 for (const auto ®
: m_registers
)
456 /* Stop once we get to the CSRs which are at the end of the
458 if (reg
.regnum
> RISCV_LAST_FP_REGNUM
)
461 int reg_bitsize
= -1;
462 for (const char *name
: reg
.names
)
464 if (tdesc_unnumbered_register (feature_fpu
, name
))
466 reg_bitsize
= tdesc_register_bitsize (feature_fpu
, name
);
470 gdb_assert (reg_bitsize
!= -1);
471 if (fp_bitsize
== -1)
472 fp_bitsize
= reg_bitsize
;
473 else if (fp_bitsize
!= reg_bitsize
)
477 features
->flen
= (fp_bitsize
/ 8);
482 /* An instance of the f-register feature set. */
484 static const struct riscv_freg_feature riscv_freg_feature
;
486 /* Class representing the virtual registers. These are not physical
487 registers on the hardware, but might be available from the target.
488 These are not pseudo registers, reading these really does result in a
489 register read from the target, it is just that there might not be a
490 physical register backing the result. */
492 struct riscv_virtual_feature
: public riscv_register_feature
494 riscv_virtual_feature ()
495 : riscv_register_feature (riscv_feature_name_virtual
)
498 { RISCV_PRIV_REGNUM
, { "priv" } }
502 bool check (const struct target_desc
*tdesc
,
503 struct tdesc_arch_data
*tdesc_data
,
504 std::vector
<riscv_pending_register_alias
> *aliases
,
505 struct riscv_gdbarch_features
*features
) const
507 const struct tdesc_feature
*feature_virtual
= tdesc_feature (tdesc
);
509 /* It's fine if this feature is missing. */
510 if (feature_virtual
== nullptr)
513 /* We don't check the return value from the call to check here, all the
514 registers in this feature are optional. */
515 for (const auto ®
: m_registers
)
516 reg
.check (tdesc_data
, feature_virtual
, true, aliases
);
522 /* An instance of the virtual register feature. */
524 static const struct riscv_virtual_feature riscv_virtual_feature
;
526 /* Class representing the CSR feature. */
528 struct riscv_csr_feature
: public riscv_register_feature
531 : riscv_register_feature (riscv_feature_name_csr
)
534 #define DECLARE_CSR(NAME,VALUE,CLASS,DEFINE_VER,ABORT_VER) \
535 { RISCV_ ## VALUE ## _REGNUM, { # NAME } },
536 #include "opcode/riscv-opc.h"
539 riscv_create_csr_aliases ();
542 bool check (const struct target_desc
*tdesc
,
543 struct tdesc_arch_data
*tdesc_data
,
544 std::vector
<riscv_pending_register_alias
> *aliases
,
545 struct riscv_gdbarch_features
*features
) const
547 const struct tdesc_feature
*feature_csr
= tdesc_feature (tdesc
);
549 /* It's fine if this feature is missing. */
550 if (feature_csr
== nullptr)
553 /* We don't check the return value from the call to check here, all the
554 registers in this feature are optional. */
555 for (const auto ®
: m_registers
)
556 reg
.check (tdesc_data
, feature_csr
, true, aliases
);
563 /* Complete RISCV_CSR_FEATURE, building the CSR alias names and adding them
564 to the name list for each register. */
567 riscv_create_csr_aliases ()
569 for (auto ®
: m_registers
)
571 int csr_num
= reg
.regnum
- RISCV_FIRST_CSR_REGNUM
;
572 gdb::unique_xmalloc_ptr
<char> alias
= xstrprintf ("csr%d", csr_num
);
573 reg
.names
.push_back (alias
.release ());
578 /* An instance of the csr register feature. */
580 static const struct riscv_csr_feature riscv_csr_feature
;
582 /* Class representing the v-registers feature set. */
584 struct riscv_vector_feature
: public riscv_register_feature
586 riscv_vector_feature ()
587 : riscv_register_feature (riscv_feature_name_vector
)
590 { RISCV_V0_REGNUM
+ 0, { "v0" } },
591 { RISCV_V0_REGNUM
+ 1, { "v1" } },
592 { RISCV_V0_REGNUM
+ 2, { "v2" } },
593 { RISCV_V0_REGNUM
+ 3, { "v3" } },
594 { RISCV_V0_REGNUM
+ 4, { "v4" } },
595 { RISCV_V0_REGNUM
+ 5, { "v5" } },
596 { RISCV_V0_REGNUM
+ 6, { "v6" } },
597 { RISCV_V0_REGNUM
+ 7, { "v7" } },
598 { RISCV_V0_REGNUM
+ 8, { "v8" } },
599 { RISCV_V0_REGNUM
+ 9, { "v9" } },
600 { RISCV_V0_REGNUM
+ 10, { "v10" } },
601 { RISCV_V0_REGNUM
+ 11, { "v11" } },
602 { RISCV_V0_REGNUM
+ 12, { "v12" } },
603 { RISCV_V0_REGNUM
+ 13, { "v13" } },
604 { RISCV_V0_REGNUM
+ 14, { "v14" } },
605 { RISCV_V0_REGNUM
+ 15, { "v15" } },
606 { RISCV_V0_REGNUM
+ 16, { "v16" } },
607 { RISCV_V0_REGNUM
+ 17, { "v17" } },
608 { RISCV_V0_REGNUM
+ 18, { "v18" } },
609 { RISCV_V0_REGNUM
+ 19, { "v19" } },
610 { RISCV_V0_REGNUM
+ 20, { "v20" } },
611 { RISCV_V0_REGNUM
+ 21, { "v21" } },
612 { RISCV_V0_REGNUM
+ 22, { "v22" } },
613 { RISCV_V0_REGNUM
+ 23, { "v23" } },
614 { RISCV_V0_REGNUM
+ 24, { "v24" } },
615 { RISCV_V0_REGNUM
+ 25, { "v25" } },
616 { RISCV_V0_REGNUM
+ 26, { "v26" } },
617 { RISCV_V0_REGNUM
+ 27, { "v27" } },
618 { RISCV_V0_REGNUM
+ 28, { "v28" } },
619 { RISCV_V0_REGNUM
+ 29, { "v29" } },
620 { RISCV_V0_REGNUM
+ 30, { "v30" } },
621 { RISCV_V0_REGNUM
+ 31, { "v31" } },
625 /* Return the preferred name for the register with gdb register number
626 REGNUM, which must be in the inclusive range RISCV_V0_REGNUM to
627 RISCV_V0_REGNUM + 31. */
628 const char *register_name (int regnum
) const
630 gdb_assert (regnum
>= RISCV_V0_REGNUM
631 && regnum
<= RISCV_V0_REGNUM
+ 31);
632 regnum
-= RISCV_V0_REGNUM
;
633 return m_registers
[regnum
].names
[0];
636 /* Check this feature within TDESC, record the registers from this
637 feature into TDESC_DATA and update ALIASES and FEATURES. */
638 bool check (const struct target_desc
*tdesc
,
639 struct tdesc_arch_data
*tdesc_data
,
640 std::vector
<riscv_pending_register_alias
> *aliases
,
641 struct riscv_gdbarch_features
*features
) const
643 const struct tdesc_feature
*feature_vector
= tdesc_feature (tdesc
);
645 /* It's fine if this feature is missing. Update the architecture
646 feature set and return. */
647 if (feature_vector
== nullptr)
653 /* Check all of the vector registers are present. */
654 for (const auto ®
: m_registers
)
656 if (!reg
.check (tdesc_data
, feature_vector
, true, aliases
))
660 /* Look through all of the vector registers and check they all have the
661 same bitsize. Use this bitsize to update the feature set for this
663 int vector_bitsize
= -1;
664 for (const auto ®
: m_registers
)
666 int reg_bitsize
= -1;
667 for (const char *name
: reg
.names
)
669 if (tdesc_unnumbered_register (feature_vector
, name
))
671 reg_bitsize
= tdesc_register_bitsize (feature_vector
, name
);
675 gdb_assert (reg_bitsize
!= -1);
676 if (vector_bitsize
== -1)
677 vector_bitsize
= reg_bitsize
;
678 else if (vector_bitsize
!= reg_bitsize
)
682 features
->vlen
= (vector_bitsize
/ 8);
687 /* An instance of the v-register feature set. */
689 static const struct riscv_vector_feature riscv_vector_feature
;
691 /* Controls whether we place compressed breakpoints or not. When in auto
692 mode GDB tries to determine if the target supports compressed
693 breakpoints, and uses them if it does. */
695 static enum auto_boolean use_compressed_breakpoints
;
697 /* The show callback for 'show riscv use-compressed-breakpoints'. */
700 show_use_compressed_breakpoints (struct ui_file
*file
, int from_tty
,
701 struct cmd_list_element
*c
,
705 _("Debugger's use of compressed breakpoints is set "
709 /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
711 static struct cmd_list_element
*setriscvcmdlist
= NULL
;
712 static struct cmd_list_element
*showriscvcmdlist
= NULL
;
714 /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
716 static struct cmd_list_element
*setdebugriscvcmdlist
= NULL
;
717 static struct cmd_list_element
*showdebugriscvcmdlist
= NULL
;
719 /* The show callback for all 'show debug riscv VARNAME' variables. */
722 show_riscv_debug_variable (struct ui_file
*file
, int from_tty
,
723 struct cmd_list_element
*c
,
727 _("RiscV debug variable `%s' is set to: %s\n"),
731 /* See riscv-tdep.h. */
734 riscv_isa_xlen (struct gdbarch
*gdbarch
)
736 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
737 return tdep
->isa_features
.xlen
;
740 /* See riscv-tdep.h. */
743 riscv_abi_xlen (struct gdbarch
*gdbarch
)
745 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
746 return tdep
->abi_features
.xlen
;
749 /* See riscv-tdep.h. */
752 riscv_isa_flen (struct gdbarch
*gdbarch
)
754 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
755 return tdep
->isa_features
.flen
;
758 /* See riscv-tdep.h. */
761 riscv_abi_flen (struct gdbarch
*gdbarch
)
763 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
764 return tdep
->abi_features
.flen
;
767 /* See riscv-tdep.h. */
770 riscv_abi_embedded (struct gdbarch
*gdbarch
)
772 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
773 return tdep
->abi_features
.embedded
;
776 /* Return true if the target for GDBARCH has floating point hardware. */
779 riscv_has_fp_regs (struct gdbarch
*gdbarch
)
781 return (riscv_isa_flen (gdbarch
) > 0);
784 /* Return true if GDBARCH is using any of the floating point hardware ABIs. */
787 riscv_has_fp_abi (struct gdbarch
*gdbarch
)
789 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
790 return tdep
->abi_features
.flen
> 0;
793 /* Return true if REGNO is a floating pointer register. */
796 riscv_is_fp_regno_p (int regno
)
798 return (regno
>= RISCV_FIRST_FP_REGNUM
799 && regno
<= RISCV_LAST_FP_REGNUM
);
802 /* Implement the breakpoint_kind_from_pc gdbarch method. */
805 riscv_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
807 if (use_compressed_breakpoints
== AUTO_BOOLEAN_AUTO
)
809 bool unaligned_p
= false;
812 /* Some targets don't support unaligned reads. The address can only
813 be unaligned if the C extension is supported. So it is safe to
814 use a compressed breakpoint in this case. */
819 /* Read the opcode byte to determine the instruction length. If
820 the read fails this may be because we tried to set the
821 breakpoint at an invalid address, in this case we provide a
822 fake result which will give a breakpoint length of 4.
823 Hopefully when we try to actually insert the breakpoint we
824 will see a failure then too which will be reported to the
826 if (target_read_code (*pcptr
, buf
, 1) == -1)
830 if (riscv_debug_breakpoints
)
832 const char *bp
= (unaligned_p
|| riscv_insn_length (buf
[0]) == 2
833 ? "C.EBREAK" : "EBREAK");
835 gdb_printf (gdb_stdlog
, "Using %s for breakpoint at %s ",
836 bp
, paddress (gdbarch
, *pcptr
));
838 gdb_printf (gdb_stdlog
, "(unaligned address)\n");
840 gdb_printf (gdb_stdlog
, "(instruction length %d)\n",
841 riscv_insn_length (buf
[0]));
843 if (unaligned_p
|| riscv_insn_length (buf
[0]) == 2)
848 else if (use_compressed_breakpoints
== AUTO_BOOLEAN_TRUE
)
854 /* Implement the sw_breakpoint_from_kind gdbarch method. */
856 static const gdb_byte
*
857 riscv_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
859 static const gdb_byte ebreak
[] = { 0x73, 0x00, 0x10, 0x00, };
860 static const gdb_byte c_ebreak
[] = { 0x02, 0x90 };
870 gdb_assert_not_reached ("unhandled breakpoint kind");
874 /* Implement the register_name gdbarch method. This is used instead of
875 the function supplied by calling TDESC_USE_REGISTERS so that we can
876 ensure the preferred names are offered for x-regs and f-regs. */
879 riscv_register_name (struct gdbarch
*gdbarch
, int regnum
)
881 /* Lookup the name through the target description. If we get back NULL
882 then this is an unknown register. If we do get a name back then we
883 look up the registers preferred name below. */
884 const char *name
= tdesc_register_name (gdbarch
, regnum
);
885 gdb_assert (name
!= nullptr);
889 /* We want GDB to use the ABI names for registers even if the target
890 gives us a target description with the architectural name. For
891 example we want to see 'ra' instead of 'x1' whatever the target
892 description called it. */
893 if (regnum
>= RISCV_ZERO_REGNUM
&& regnum
< RISCV_FIRST_FP_REGNUM
)
894 return riscv_xreg_feature
.register_name (regnum
);
896 /* Like with the x-regs we prefer the abi names for the floating point
897 registers. If the target doesn't have floating point registers then
898 the tdesc_register_name call above should have returned an empty
900 if (regnum
>= RISCV_FIRST_FP_REGNUM
&& regnum
<= RISCV_LAST_FP_REGNUM
)
902 gdb_assert (riscv_has_fp_regs (gdbarch
));
903 return riscv_freg_feature
.register_name (regnum
);
906 /* Some targets (QEMU) are reporting these three registers twice, once
907 in the FPU feature, and once in the CSR feature. Both of these read
908 the same underlying state inside the target, but naming the register
909 twice in the target description results in GDB having two registers
910 with the same name, only one of which can ever be accessed, but both
911 will show up in 'info register all'. Unless, we identify the
912 duplicate copies of these registers (in riscv_tdesc_unknown_reg) and
913 then hide the registers here by giving them no name. */
914 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
915 if (tdep
->duplicate_fflags_regnum
== regnum
916 || tdep
->duplicate_frm_regnum
== regnum
917 || tdep
->duplicate_fcsr_regnum
== regnum
)
920 /* The remaining registers are different. For all other registers on the
921 machine we prefer to see the names that the target description
922 provides. This is particularly important for CSRs which might be
923 renamed over time. If GDB keeps track of the "latest" name, but a
924 particular target provides an older name then we don't want to force
925 users to see the newer name in register output.
927 The other case that reaches here are any registers that the target
928 provided that GDB is completely unaware of. For these we have no
929 choice but to accept the target description name.
931 Just accept whatever name TDESC_REGISTER_NAME returned. */
935 /* Implement gdbarch_pseudo_register_read. Read pseudo-register REGNUM
936 from REGCACHE and place the register value into BUF. BUF is sized
937 based on the type of register REGNUM, all of BUF should be written too,
938 the result should be sign or zero extended as appropriate. */
940 static enum register_status
941 riscv_pseudo_register_read (struct gdbarch
*gdbarch
,
942 readable_regcache
*regcache
,
943 int regnum
, gdb_byte
*buf
)
945 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
947 if (regnum
== tdep
->fflags_regnum
|| regnum
== tdep
->frm_regnum
)
950 memset (buf
, 0, register_size (gdbarch
, regnum
));
952 /* Read the first byte of the fcsr register, this contains both frm
954 enum register_status status
955 = regcache
->raw_read_part (RISCV_CSR_FCSR_REGNUM
, 0, 1, buf
);
957 if (status
!= REG_VALID
)
960 /* Extract the appropriate parts. */
961 if (regnum
== tdep
->fflags_regnum
)
963 else if (regnum
== tdep
->frm_regnum
)
964 buf
[0] = (buf
[0] >> 5) & 0x7;
972 /* Implement gdbarch_pseudo_register_write. Write the contents of BUF into
973 pseudo-register REGNUM in REGCACHE. BUF is sized based on the type of
977 riscv_pseudo_register_write (struct gdbarch
*gdbarch
,
978 struct regcache
*regcache
, int regnum
,
981 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
983 if (regnum
== tdep
->fflags_regnum
|| regnum
== tdep
->frm_regnum
)
985 int fcsr_regnum
= RISCV_CSR_FCSR_REGNUM
;
986 gdb_byte raw_buf
[register_size (gdbarch
, fcsr_regnum
)];
988 regcache
->raw_read (fcsr_regnum
, raw_buf
);
990 if (regnum
== tdep
->fflags_regnum
)
991 raw_buf
[0] = (raw_buf
[0] & ~0x1f) | (buf
[0] & 0x1f);
992 else if (regnum
== tdep
->frm_regnum
)
993 raw_buf
[0] = (raw_buf
[0] & ~(0x7 << 5)) | ((buf
[0] & 0x7) << 5);
995 regcache
->raw_write (fcsr_regnum
, raw_buf
);
998 gdb_assert_not_reached ("unknown pseudo register %d", regnum
);
1001 /* Implement the cannot_store_register gdbarch method. The zero register
1002 (x0) is read-only on RISC-V. */
1005 riscv_cannot_store_register (struct gdbarch
*gdbarch
, int regnum
)
1007 return regnum
== RISCV_ZERO_REGNUM
;
1010 /* Construct a type for 64-bit FP registers. */
1012 static struct type
*
1013 riscv_fpreg_d_type (struct gdbarch
*gdbarch
)
1015 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
1017 if (tdep
->riscv_fpreg_d_type
== nullptr)
1019 const struct builtin_type
*bt
= builtin_type (gdbarch
);
1021 /* The type we're building is this: */
1023 union __gdb_builtin_type_fpreg_d
1032 t
= arch_composite_type (gdbarch
,
1033 "__gdb_builtin_type_fpreg_d", TYPE_CODE_UNION
);
1034 append_composite_type_field (t
, "float", bt
->builtin_float
);
1035 append_composite_type_field (t
, "double", bt
->builtin_double
);
1036 t
->set_is_vector (true);
1037 t
->set_name ("builtin_type_fpreg_d");
1038 tdep
->riscv_fpreg_d_type
= t
;
1041 return tdep
->riscv_fpreg_d_type
;
1044 /* Implement the register_type gdbarch method. This is installed as an
1045 for the override setup by TDESC_USE_REGISTERS, for most registers we
1046 delegate the type choice to the target description, but for a few
1047 registers we try to improve the types if the target description has
1048 taken a simplistic approach. */
1050 static struct type
*
1051 riscv_register_type (struct gdbarch
*gdbarch
, int regnum
)
1053 struct type
*type
= tdesc_register_type (gdbarch
, regnum
);
1054 int xlen
= riscv_isa_xlen (gdbarch
);
1056 /* We want to perform some specific type "fixes" in cases where we feel
1057 that we really can do better than the target description. For all
1058 other cases we just return what the target description says. */
1059 if (riscv_is_fp_regno_p (regnum
))
1061 /* This spots the case for RV64 where the double is defined as
1062 either 'ieee_double' or 'float' (which is the generic name that
1063 converts to 'double' on 64-bit). In these cases its better to
1064 present the registers using a union type. */
1065 int flen
= riscv_isa_flen (gdbarch
);
1067 && type
->code () == TYPE_CODE_FLT
1068 && type
->length () == flen
1069 && (strcmp (type
->name (), "builtin_type_ieee_double") == 0
1070 || strcmp (type
->name (), "double") == 0))
1071 type
= riscv_fpreg_d_type (gdbarch
);
1074 if ((regnum
== gdbarch_pc_regnum (gdbarch
)
1075 || regnum
== RISCV_RA_REGNUM
1076 || regnum
== RISCV_FP_REGNUM
1077 || regnum
== RISCV_SP_REGNUM
1078 || regnum
== RISCV_GP_REGNUM
1079 || regnum
== RISCV_TP_REGNUM
)
1080 && type
->code () == TYPE_CODE_INT
1081 && type
->length () == xlen
)
1083 /* This spots the case where some interesting registers are defined
1084 as simple integers of the expected size, we force these registers
1085 to be pointers as we believe that is more useful. */
1086 if (regnum
== gdbarch_pc_regnum (gdbarch
)
1087 || regnum
== RISCV_RA_REGNUM
)
1088 type
= builtin_type (gdbarch
)->builtin_func_ptr
;
1089 else if (regnum
== RISCV_FP_REGNUM
1090 || regnum
== RISCV_SP_REGNUM
1091 || regnum
== RISCV_GP_REGNUM
1092 || regnum
== RISCV_TP_REGNUM
)
1093 type
= builtin_type (gdbarch
)->builtin_data_ptr
;
1099 /* Helper for riscv_print_registers_info, prints info for a single register
1103 riscv_print_one_register_info (struct gdbarch
*gdbarch
,
1104 struct ui_file
*file
,
1105 struct frame_info
*frame
,
1108 const char *name
= gdbarch_register_name (gdbarch
, regnum
);
1110 struct type
*regtype
;
1111 int print_raw_format
;
1112 enum tab_stops
{ value_column_1
= 15 };
1114 gdb_puts (name
, file
);
1115 print_spaces (value_column_1
- strlen (name
), file
);
1119 val
= value_of_register (regnum
, frame
);
1120 regtype
= value_type (val
);
1122 catch (const gdb_exception_error
&ex
)
1124 /* Handle failure to read a register without interrupting the entire
1125 'info registers' flow. */
1126 gdb_printf (file
, "%s\n", ex
.what ());
1130 print_raw_format
= (value_entirely_available (val
)
1131 && !value_optimized_out (val
));
1133 if (regtype
->code () == TYPE_CODE_FLT
1134 || (regtype
->code () == TYPE_CODE_UNION
1135 && regtype
->num_fields () == 2
1136 && regtype
->field (0).type ()->code () == TYPE_CODE_FLT
1137 && regtype
->field (1).type ()->code () == TYPE_CODE_FLT
)
1138 || (regtype
->code () == TYPE_CODE_UNION
1139 && regtype
->num_fields () == 3
1140 && regtype
->field (0).type ()->code () == TYPE_CODE_FLT
1141 && regtype
->field (1).type ()->code () == TYPE_CODE_FLT
1142 && regtype
->field (2).type ()->code () == TYPE_CODE_FLT
))
1144 struct value_print_options opts
;
1145 const gdb_byte
*valaddr
= value_contents_for_printing (val
).data ();
1146 enum bfd_endian byte_order
= type_byte_order (regtype
);
1148 get_user_print_options (&opts
);
1151 common_val_print (val
, file
, 0, &opts
, current_language
);
1153 if (print_raw_format
)
1155 gdb_printf (file
, "\t(raw ");
1156 print_hex_chars (file
, valaddr
, regtype
->length (), byte_order
,
1158 gdb_printf (file
, ")");
1163 struct value_print_options opts
;
1164 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
1166 /* Print the register in hex. */
1167 get_formatted_print_options (&opts
, 'x');
1169 common_val_print (val
, file
, 0, &opts
, current_language
);
1171 if (print_raw_format
)
1173 if (regnum
== RISCV_CSR_MSTATUS_REGNUM
)
1176 int size
= register_size (gdbarch
, regnum
);
1179 /* The SD field is always in the upper bit of MSTATUS, regardless
1180 of the number of bits in MSTATUS. */
1181 d
= value_as_long (val
);
1184 "\tSD:%X VM:%02X MXR:%X PUM:%X MPRV:%X XS:%X "
1185 "FS:%X MPP:%x HPP:%X SPP:%X MPIE:%X HPIE:%X "
1186 "SPIE:%X UPIE:%X MIE:%X HIE:%X SIE:%X UIE:%X",
1187 (int) ((d
>> (xlen
- 1)) & 0x1),
1188 (int) ((d
>> 24) & 0x1f),
1189 (int) ((d
>> 19) & 0x1),
1190 (int) ((d
>> 18) & 0x1),
1191 (int) ((d
>> 17) & 0x1),
1192 (int) ((d
>> 15) & 0x3),
1193 (int) ((d
>> 13) & 0x3),
1194 (int) ((d
>> 11) & 0x3),
1195 (int) ((d
>> 9) & 0x3),
1196 (int) ((d
>> 8) & 0x1),
1197 (int) ((d
>> 7) & 0x1),
1198 (int) ((d
>> 6) & 0x1),
1199 (int) ((d
>> 5) & 0x1),
1200 (int) ((d
>> 4) & 0x1),
1201 (int) ((d
>> 3) & 0x1),
1202 (int) ((d
>> 2) & 0x1),
1203 (int) ((d
>> 1) & 0x1),
1204 (int) ((d
>> 0) & 0x1));
1206 else if (regnum
== RISCV_CSR_MISA_REGNUM
)
1211 int size
= register_size (gdbarch
, regnum
);
1213 /* The MXL field is always in the upper two bits of MISA,
1214 regardless of the number of bits in MISA. Mask out other
1215 bits to ensure we have a positive value. */
1216 d
= value_as_long (val
);
1217 base
= (d
>> ((size
* 8) - 2)) & 0x3;
1220 for (; base
> 0; base
--)
1222 gdb_printf (file
, "\tRV%d", xlen
);
1224 for (i
= 0; i
< 26; i
++)
1227 gdb_printf (file
, "%c", 'A' + i
);
1230 else if (regnum
== RISCV_CSR_FCSR_REGNUM
1231 || regnum
== tdep
->fflags_regnum
1232 || regnum
== tdep
->frm_regnum
)
1234 LONGEST d
= value_as_long (val
);
1236 gdb_printf (file
, "\t");
1237 if (regnum
!= tdep
->frm_regnum
)
1239 "NV:%d DZ:%d OF:%d UF:%d NX:%d",
1240 (int) ((d
>> 4) & 0x1),
1241 (int) ((d
>> 3) & 0x1),
1242 (int) ((d
>> 2) & 0x1),
1243 (int) ((d
>> 1) & 0x1),
1244 (int) ((d
>> 0) & 0x1));
1246 if (regnum
!= tdep
->fflags_regnum
)
1248 static const char * const sfrm
[] =
1250 _("RNE (round to nearest; ties to even)"),
1251 _("RTZ (Round towards zero)"),
1252 _("RDN (Round down towards -INF)"),
1253 _("RUP (Round up towards +INF)"),
1254 _("RMM (Round to nearest; ties to max magnitude)"),
1257 /* A value of 0x7 indicates dynamic rounding mode when
1258 used within an instructions rounding-mode field, but
1259 is invalid within the FRM register. */
1260 _("INVALID[7] (Dynamic rounding mode)"),
1262 int frm
= ((regnum
== RISCV_CSR_FCSR_REGNUM
)
1263 ? (d
>> 5) : d
) & 0x7;
1265 gdb_printf (file
, "%sFRM:%i [%s]",
1266 (regnum
== RISCV_CSR_FCSR_REGNUM
1271 else if (regnum
== RISCV_PRIV_REGNUM
)
1276 d
= value_as_long (val
);
1281 static const char * const sprv
[] =
1288 gdb_printf (file
, "\tprv:%d [%s]",
1292 gdb_printf (file
, "\tprv:%d [INVALID]", priv
);
1296 /* If not a vector register, print it also according to its
1298 if (regtype
->is_vector () == 0)
1300 get_user_print_options (&opts
);
1302 gdb_printf (file
, "\t");
1303 common_val_print (val
, file
, 0, &opts
, current_language
);
1308 gdb_printf (file
, "\n");
1311 /* Return true if REGNUM is a valid CSR register. The CSR register space
1312 is sparsely populated, so not every number is a named CSR. */
1315 riscv_is_regnum_a_named_csr (int regnum
)
1317 gdb_assert (regnum
>= RISCV_FIRST_CSR_REGNUM
1318 && regnum
<= RISCV_LAST_CSR_REGNUM
);
1322 #define DECLARE_CSR(name, num, class, define_ver, abort_ver) case RISCV_ ## num ## _REGNUM:
1323 #include "opcode/riscv-opc.h"
1332 /* Return true if REGNUM is an unknown CSR identified in
1333 riscv_tdesc_unknown_reg for GDBARCH. */
1336 riscv_is_unknown_csr (struct gdbarch
*gdbarch
, int regnum
)
1338 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
1339 return (regnum
>= tdep
->unknown_csrs_first_regnum
1340 && regnum
< (tdep
->unknown_csrs_first_regnum
1341 + tdep
->unknown_csrs_count
));
1344 /* Implement the register_reggroup_p gdbarch method. Is REGNUM a member
1348 riscv_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
1349 const struct reggroup
*reggroup
)
1351 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
1353 /* Used by 'info registers' and 'info registers <groupname>'. */
1355 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
1356 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
1359 if (regnum
> RISCV_LAST_REGNUM
&& regnum
< gdbarch_num_regs (gdbarch
))
1361 /* Any extra registers from the CSR tdesc_feature (identified in
1362 riscv_tdesc_unknown_reg) are removed from the save/restore groups
1363 as some targets (QEMU) report CSRs which then can't be read and
1364 having unreadable registers in the save/restore group breaks
1365 things like inferior calls.
1367 The unknown CSRs are also removed from the general group, and
1368 added into both the csr and system group. This is inline with the
1369 known CSRs (see below). */
1370 if (riscv_is_unknown_csr (gdbarch
, regnum
))
1372 if (reggroup
== restore_reggroup
|| reggroup
== save_reggroup
1373 || reggroup
== general_reggroup
)
1375 else if (reggroup
== system_reggroup
|| reggroup
== csr_reggroup
)
1379 /* This is some other unknown register from the target description.
1380 In this case we trust whatever the target description says about
1381 which groups this register should be in. */
1382 int ret
= tdesc_register_in_reggroup_p (gdbarch
, regnum
, reggroup
);
1386 return default_register_reggroup_p (gdbarch
, regnum
, reggroup
);
1389 if (reggroup
== all_reggroup
)
1391 if (regnum
< RISCV_FIRST_CSR_REGNUM
|| regnum
>= RISCV_PRIV_REGNUM
)
1393 if (riscv_is_regnum_a_named_csr (regnum
))
1397 else if (reggroup
== float_reggroup
)
1398 return (riscv_is_fp_regno_p (regnum
)
1399 || regnum
== RISCV_CSR_FCSR_REGNUM
1400 || regnum
== tdep
->fflags_regnum
1401 || regnum
== tdep
->frm_regnum
);
1402 else if (reggroup
== general_reggroup
)
1403 return regnum
< RISCV_FIRST_FP_REGNUM
;
1404 else if (reggroup
== restore_reggroup
|| reggroup
== save_reggroup
)
1406 if (riscv_has_fp_regs (gdbarch
))
1407 return (regnum
<= RISCV_LAST_FP_REGNUM
1408 || regnum
== RISCV_CSR_FCSR_REGNUM
1409 || regnum
== tdep
->fflags_regnum
1410 || regnum
== tdep
->frm_regnum
);
1412 return regnum
< RISCV_FIRST_FP_REGNUM
;
1414 else if (reggroup
== system_reggroup
|| reggroup
== csr_reggroup
)
1416 if (regnum
== RISCV_PRIV_REGNUM
)
1418 if (regnum
< RISCV_FIRST_CSR_REGNUM
|| regnum
> RISCV_LAST_CSR_REGNUM
)
1420 if (riscv_is_regnum_a_named_csr (regnum
))
1424 else if (reggroup
== vector_reggroup
)
1425 return (regnum
>= RISCV_V0_REGNUM
&& regnum
<= RISCV_V31_REGNUM
);
1430 /* Return the name for pseudo-register REGNUM for GDBARCH. */
1433 riscv_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
1435 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
1437 if (regnum
== tdep
->fflags_regnum
)
1439 else if (regnum
== tdep
->frm_regnum
)
1442 gdb_assert_not_reached ("unknown pseudo register number %d", regnum
);
1445 /* Return the type for pseudo-register REGNUM for GDBARCH. */
1447 static struct type
*
1448 riscv_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
1450 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
1452 if (regnum
== tdep
->fflags_regnum
|| regnum
== tdep
->frm_regnum
)
1453 return builtin_type (gdbarch
)->builtin_int32
;
1455 gdb_assert_not_reached ("unknown pseudo register number %d", regnum
);
1458 /* Return true (non-zero) if pseudo-register REGNUM from GDBARCH is a
1459 member of REGGROUP, otherwise return false (zero). */
1462 riscv_pseudo_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
1463 const struct reggroup
*reggroup
)
1465 /* The standard function will also work for pseudo-registers. */
1466 return riscv_register_reggroup_p (gdbarch
, regnum
, reggroup
);
1469 /* Implement the print_registers_info gdbarch method. This is used by
1470 'info registers' and 'info all-registers'. */
1473 riscv_print_registers_info (struct gdbarch
*gdbarch
,
1474 struct ui_file
*file
,
1475 struct frame_info
*frame
,
1476 int regnum
, int print_all
)
1480 /* Print one specified register. */
1481 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
1482 || *(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
1483 error (_("Not a valid register for the current processor type"));
1484 riscv_print_one_register_info (gdbarch
, file
, frame
, regnum
);
1488 const struct reggroup
*reggroup
;
1491 reggroup
= all_reggroup
;
1493 reggroup
= general_reggroup
;
1495 for (regnum
= 0; regnum
< gdbarch_num_cooked_regs (gdbarch
); ++regnum
)
1497 /* Zero never changes, so might as well hide by default. */
1498 if (regnum
== RISCV_ZERO_REGNUM
&& !print_all
)
1501 /* Registers with no name are not valid on this ISA. */
1502 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
1503 || *(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
1506 /* Is the register in the group we're interested in? */
1507 if (!gdbarch_register_reggroup_p (gdbarch
, regnum
, reggroup
))
1510 riscv_print_one_register_info (gdbarch
, file
, frame
, regnum
);
1515 /* Class that handles one decoded RiscV instruction. */
1521 /* Enum of all the opcodes that GDB cares about during the prologue scan. */
1524 /* Unknown value is used at initialisation time. */
1527 /* These instructions are all the ones we are interested in during the
1540 /* These are needed for software breakpoint support. */
1549 /* These are needed for stepping over atomic sequences. */
1552 /* This instruction is used to do a syscall. */
1555 /* Other instructions are not interesting during the prologue scan, and
1570 void decode (struct gdbarch
*gdbarch
, CORE_ADDR pc
);
1572 /* Get the length of the instruction in bytes. */
1574 { return m_length
; }
1576 /* Get the opcode for this instruction. */
1577 enum opcode
opcode () const
1578 { return m_opcode
; }
1580 /* Get destination register field for this instruction. This is only
1581 valid if the OPCODE implies there is such a field for this
1586 /* Get the RS1 register field for this instruction. This is only valid
1587 if the OPCODE implies there is such a field for this instruction. */
1591 /* Get the RS2 register field for this instruction. This is only valid
1592 if the OPCODE implies there is such a field for this instruction. */
1596 /* Get the immediate for this instruction in signed form. This is only
1597 valid if the OPCODE implies there is such a field for this
1599 int imm_signed () const
1604 /* Extract 5 bit register field at OFFSET from instruction OPCODE. */
1605 int decode_register_index (unsigned long opcode
, int offset
)
1607 return (opcode
>> offset
) & 0x1F;
1610 /* Extract 5 bit register field at OFFSET from instruction OPCODE. */
1611 int decode_register_index_short (unsigned long opcode
, int offset
)
1613 return ((opcode
>> offset
) & 0x7) + 8;
1616 /* Helper for DECODE, decode 32-bit R-type instruction. */
1617 void decode_r_type_insn (enum opcode opcode
, ULONGEST ival
)
1620 m_rd
= decode_register_index (ival
, OP_SH_RD
);
1621 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
1622 m_rs2
= decode_register_index (ival
, OP_SH_RS2
);
1625 /* Helper for DECODE, decode 16-bit compressed R-type instruction. */
1626 void decode_cr_type_insn (enum opcode opcode
, ULONGEST ival
)
1629 m_rd
= m_rs1
= decode_register_index (ival
, OP_SH_CRS1S
);
1630 m_rs2
= decode_register_index (ival
, OP_SH_CRS2
);
1633 /* Helper for DECODE, decode 32-bit I-type instruction. */
1634 void decode_i_type_insn (enum opcode opcode
, ULONGEST ival
)
1637 m_rd
= decode_register_index (ival
, OP_SH_RD
);
1638 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
1639 m_imm
.s
= EXTRACT_ITYPE_IMM (ival
);
1642 /* Helper for DECODE, decode 16-bit compressed I-type instruction. */
1643 void decode_ci_type_insn (enum opcode opcode
, ULONGEST ival
)
1646 m_rd
= m_rs1
= decode_register_index (ival
, OP_SH_CRS1S
);
1647 m_imm
.s
= EXTRACT_CITYPE_IMM (ival
);
1650 /* Helper for DECODE, decode 16-bit compressed CL-type instruction. */
1651 void decode_cl_type_insn (enum opcode opcode
, ULONGEST ival
)
1654 m_rd
= decode_register_index_short (ival
, OP_SH_CRS2S
);
1655 m_rs1
= decode_register_index_short (ival
, OP_SH_CRS1S
);
1656 m_imm
.s
= EXTRACT_CLTYPE_IMM (ival
);
1659 /* Helper for DECODE, decode 32-bit S-type instruction. */
1660 void decode_s_type_insn (enum opcode opcode
, ULONGEST ival
)
1663 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
1664 m_rs2
= decode_register_index (ival
, OP_SH_RS2
);
1665 m_imm
.s
= EXTRACT_STYPE_IMM (ival
);
1668 /* Helper for DECODE, decode 16-bit CS-type instruction. The immediate
1669 encoding is different for each CS format instruction, so extracting
1670 the immediate is left up to the caller, who should pass the extracted
1671 immediate value through in IMM. */
1672 void decode_cs_type_insn (enum opcode opcode
, ULONGEST ival
, int imm
)
1676 m_rs1
= decode_register_index_short (ival
, OP_SH_CRS1S
);
1677 m_rs2
= decode_register_index_short (ival
, OP_SH_CRS2S
);
1680 /* Helper for DECODE, decode 16-bit CSS-type instruction. The immediate
1681 encoding is different for each CSS format instruction, so extracting
1682 the immediate is left up to the caller, who should pass the extracted
1683 immediate value through in IMM. */
1684 void decode_css_type_insn (enum opcode opcode
, ULONGEST ival
, int imm
)
1688 m_rs1
= RISCV_SP_REGNUM
;
1689 /* Not a compressed register number in this case. */
1690 m_rs2
= decode_register_index (ival
, OP_SH_CRS2
);
1693 /* Helper for DECODE, decode 32-bit U-type instruction. */
1694 void decode_u_type_insn (enum opcode opcode
, ULONGEST ival
)
1697 m_rd
= decode_register_index (ival
, OP_SH_RD
);
1698 m_imm
.s
= EXTRACT_UTYPE_IMM (ival
);
1701 /* Helper for DECODE, decode 32-bit J-type instruction. */
1702 void decode_j_type_insn (enum opcode opcode
, ULONGEST ival
)
1705 m_rd
= decode_register_index (ival
, OP_SH_RD
);
1706 m_imm
.s
= EXTRACT_JTYPE_IMM (ival
);
1709 /* Helper for DECODE, decode 32-bit J-type instruction. */
1710 void decode_cj_type_insn (enum opcode opcode
, ULONGEST ival
)
1713 m_imm
.s
= EXTRACT_CJTYPE_IMM (ival
);
1716 void decode_b_type_insn (enum opcode opcode
, ULONGEST ival
)
1719 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
1720 m_rs2
= decode_register_index (ival
, OP_SH_RS2
);
1721 m_imm
.s
= EXTRACT_BTYPE_IMM (ival
);
1724 void decode_cb_type_insn (enum opcode opcode
, ULONGEST ival
)
1727 m_rs1
= decode_register_index_short (ival
, OP_SH_CRS1S
);
1728 m_imm
.s
= EXTRACT_CBTYPE_IMM (ival
);
1731 /* Fetch instruction from target memory at ADDR, return the content of
1732 the instruction, and update LEN with the instruction length. */
1733 static ULONGEST
fetch_instruction (struct gdbarch
*gdbarch
,
1734 CORE_ADDR addr
, int *len
);
1736 /* The length of the instruction in bytes. Should be 2 or 4. */
1739 /* The instruction opcode. */
1740 enum opcode m_opcode
;
1742 /* The three possible registers an instruction might reference. Not
1743 every instruction fills in all of these registers. Which fields are
1744 valid depends on the opcode. The naming of these fields matches the
1745 naming in the riscv isa manual. */
1750 /* Possible instruction immediate. This is only valid if the instruction
1751 format contains an immediate, not all instruction, whether this is
1752 valid depends on the opcode. Despite only having one format for now
1753 the immediate is packed into a union, later instructions might require
1754 an unsigned formatted immediate, having the union in place now will
1755 reduce the need for code churn later. */
1756 union riscv_insn_immediate
1758 riscv_insn_immediate ()
1768 /* Fetch instruction from target memory at ADDR, return the content of the
1769 instruction, and update LEN with the instruction length. */
1772 riscv_insn::fetch_instruction (struct gdbarch
*gdbarch
,
1773 CORE_ADDR addr
, int *len
)
1775 enum bfd_endian byte_order
= gdbarch_byte_order_for_code (gdbarch
);
1777 int instlen
, status
;
1779 /* All insns are at least 16 bits. */
1780 status
= target_read_memory (addr
, buf
, 2);
1782 memory_error (TARGET_XFER_E_IO
, addr
);
1784 /* If we need more, grab it now. */
1785 instlen
= riscv_insn_length (buf
[0]);
1786 gdb_assert (instlen
<= sizeof (buf
));
1791 status
= target_read_memory (addr
+ 2, buf
+ 2, instlen
- 2);
1793 memory_error (TARGET_XFER_E_IO
, addr
+ 2);
1796 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1799 /* Fetch from target memory an instruction at PC and decode it. This can
1800 throw an error if the memory access fails, callers are responsible for
1801 handling this error if that is appropriate. */
1804 riscv_insn::decode (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1808 /* Fetch the instruction, and the instructions length. */
1809 ival
= fetch_instruction (gdbarch
, pc
, &m_length
);
1813 if (is_add_insn (ival
))
1814 decode_r_type_insn (ADD
, ival
);
1815 else if (is_addw_insn (ival
))
1816 decode_r_type_insn (ADDW
, ival
);
1817 else if (is_addi_insn (ival
))
1818 decode_i_type_insn (ADDI
, ival
);
1819 else if (is_addiw_insn (ival
))
1820 decode_i_type_insn (ADDIW
, ival
);
1821 else if (is_auipc_insn (ival
))
1822 decode_u_type_insn (AUIPC
, ival
);
1823 else if (is_lui_insn (ival
))
1824 decode_u_type_insn (LUI
, ival
);
1825 else if (is_sd_insn (ival
))
1826 decode_s_type_insn (SD
, ival
);
1827 else if (is_sw_insn (ival
))
1828 decode_s_type_insn (SW
, ival
);
1829 else if (is_jal_insn (ival
))
1830 decode_j_type_insn (JAL
, ival
);
1831 else if (is_jalr_insn (ival
))
1832 decode_i_type_insn (JALR
, ival
);
1833 else if (is_beq_insn (ival
))
1834 decode_b_type_insn (BEQ
, ival
);
1835 else if (is_bne_insn (ival
))
1836 decode_b_type_insn (BNE
, ival
);
1837 else if (is_blt_insn (ival
))
1838 decode_b_type_insn (BLT
, ival
);
1839 else if (is_bge_insn (ival
))
1840 decode_b_type_insn (BGE
, ival
);
1841 else if (is_bltu_insn (ival
))
1842 decode_b_type_insn (BLTU
, ival
);
1843 else if (is_bgeu_insn (ival
))
1844 decode_b_type_insn (BGEU
, ival
);
1845 else if (is_lr_w_insn (ival
))
1846 decode_r_type_insn (LR
, ival
);
1847 else if (is_lr_d_insn (ival
))
1848 decode_r_type_insn (LR
, ival
);
1849 else if (is_sc_w_insn (ival
))
1850 decode_r_type_insn (SC
, ival
);
1851 else if (is_sc_d_insn (ival
))
1852 decode_r_type_insn (SC
, ival
);
1853 else if (is_ecall_insn (ival
))
1854 decode_i_type_insn (ECALL
, ival
);
1855 else if (is_ld_insn (ival
))
1856 decode_i_type_insn (LD
, ival
);
1857 else if (is_lw_insn (ival
))
1858 decode_i_type_insn (LW
, ival
);
1860 /* None of the other fields are valid in this case. */
1863 else if (m_length
== 2)
1865 int xlen
= riscv_isa_xlen (gdbarch
);
1867 /* C_ADD and C_JALR have the same opcode. If RS2 is 0, then this is a
1868 C_JALR. So must try to match C_JALR first as it has more bits in
1870 if (is_c_jalr_insn (ival
))
1871 decode_cr_type_insn (JALR
, ival
);
1872 else if (is_c_add_insn (ival
))
1873 decode_cr_type_insn (ADD
, ival
);
1874 /* C_ADDW is RV64 and RV128 only. */
1875 else if (xlen
!= 4 && is_c_addw_insn (ival
))
1876 decode_cr_type_insn (ADDW
, ival
);
1877 else if (is_c_addi_insn (ival
))
1878 decode_ci_type_insn (ADDI
, ival
);
1879 /* C_ADDIW and C_JAL have the same opcode. C_ADDIW is RV64 and RV128
1880 only and C_JAL is RV32 only. */
1881 else if (xlen
!= 4 && is_c_addiw_insn (ival
))
1882 decode_ci_type_insn (ADDIW
, ival
);
1883 else if (xlen
== 4 && is_c_jal_insn (ival
))
1884 decode_cj_type_insn (JAL
, ival
);
1885 /* C_ADDI16SP and C_LUI have the same opcode. If RD is 2, then this is a
1886 C_ADDI16SP. So must try to match C_ADDI16SP first as it has more bits
1888 else if (is_c_addi16sp_insn (ival
))
1891 m_rd
= m_rs1
= decode_register_index (ival
, OP_SH_RD
);
1892 m_imm
.s
= EXTRACT_CITYPE_ADDI16SP_IMM (ival
);
1894 else if (is_c_addi4spn_insn (ival
))
1897 m_rd
= decode_register_index_short (ival
, OP_SH_CRS2S
);
1898 m_rs1
= RISCV_SP_REGNUM
;
1899 m_imm
.s
= EXTRACT_CIWTYPE_ADDI4SPN_IMM (ival
);
1901 else if (is_c_lui_insn (ival
))
1904 m_rd
= decode_register_index (ival
, OP_SH_CRS1S
);
1905 m_imm
.s
= EXTRACT_CITYPE_LUI_IMM (ival
);
1907 /* C_SD and C_FSW have the same opcode. C_SD is RV64 and RV128 only,
1908 and C_FSW is RV32 only. */
1909 else if (xlen
!= 4 && is_c_sd_insn (ival
))
1910 decode_cs_type_insn (SD
, ival
, EXTRACT_CLTYPE_LD_IMM (ival
));
1911 else if (is_c_sw_insn (ival
))
1912 decode_cs_type_insn (SW
, ival
, EXTRACT_CLTYPE_LW_IMM (ival
));
1913 else if (is_c_swsp_insn (ival
))
1914 decode_css_type_insn (SW
, ival
, EXTRACT_CSSTYPE_SWSP_IMM (ival
));
1915 else if (xlen
!= 4 && is_c_sdsp_insn (ival
))
1916 decode_css_type_insn (SD
, ival
, EXTRACT_CSSTYPE_SDSP_IMM (ival
));
1917 /* C_JR and C_MV have the same opcode. If RS2 is 0, then this is a C_JR.
1918 So must try to match C_JR first as it has more bits in mask. */
1919 else if (is_c_jr_insn (ival
))
1920 decode_cr_type_insn (JALR
, ival
);
1921 else if (is_c_mv_insn (ival
))
1922 decode_cr_type_insn (MV
, ival
);
1923 else if (is_c_j_insn (ival
))
1924 decode_cj_type_insn (JAL
, ival
);
1925 else if (is_c_beqz_insn (ival
))
1926 decode_cb_type_insn (BEQ
, ival
);
1927 else if (is_c_bnez_insn (ival
))
1928 decode_cb_type_insn (BNE
, ival
);
1929 else if (is_c_ld_insn (ival
))
1930 decode_cl_type_insn (LD
, ival
);
1931 else if (is_c_lw_insn (ival
))
1932 decode_cl_type_insn (LW
, ival
);
1934 /* None of the other fields of INSN are valid in this case. */
1939 /* This must be a 6 or 8 byte instruction, we don't currently decode
1940 any of these, so just ignore it. */
1941 gdb_assert (m_length
== 6 || m_length
== 8);
1946 /* The prologue scanner. This is currently only used for skipping the
1947 prologue of a function when the DWARF information is not sufficient.
1948 However, it is written with filling of the frame cache in mind, which
1949 is why different groups of stack setup instructions are split apart
1950 during the core of the inner loop. In the future, the intention is to
1951 extend this function to fully support building up a frame cache that
1952 can unwind register values when there is no DWARF information. */
1955 riscv_scan_prologue (struct gdbarch
*gdbarch
,
1956 CORE_ADDR start_pc
, CORE_ADDR end_pc
,
1957 struct riscv_unwind_cache
*cache
)
1959 CORE_ADDR cur_pc
, next_pc
, after_prologue_pc
;
1960 CORE_ADDR end_prologue_addr
= 0;
1962 /* Find an upper limit on the function prologue using the debug
1963 information. If the debug information could not be used to provide
1964 that bound, then use an arbitrary large number as the upper bound. */
1965 after_prologue_pc
= skip_prologue_using_sal (gdbarch
, start_pc
);
1966 if (after_prologue_pc
== 0)
1967 after_prologue_pc
= start_pc
+ 100; /* Arbitrary large number. */
1968 if (after_prologue_pc
< end_pc
)
1969 end_pc
= after_prologue_pc
;
1971 pv_t regs
[RISCV_NUM_INTEGER_REGS
]; /* Number of GPR. */
1972 for (int regno
= 0; regno
< RISCV_NUM_INTEGER_REGS
; regno
++)
1973 regs
[regno
] = pv_register (regno
, 0);
1974 pv_area
stack (RISCV_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
1976 if (riscv_debug_unwinder
)
1979 "Prologue scan for function starting at %s (limit %s)\n",
1980 core_addr_to_string (start_pc
),
1981 core_addr_to_string (end_pc
));
1983 for (next_pc
= cur_pc
= start_pc
; cur_pc
< end_pc
; cur_pc
= next_pc
)
1985 struct riscv_insn insn
;
1987 /* Decode the current instruction, and decide where the next
1988 instruction lives based on the size of this instruction. */
1989 insn
.decode (gdbarch
, cur_pc
);
1990 gdb_assert (insn
.length () > 0);
1991 next_pc
= cur_pc
+ insn
.length ();
1993 /* Look for common stack adjustment insns. */
1994 if ((insn
.opcode () == riscv_insn::ADDI
1995 || insn
.opcode () == riscv_insn::ADDIW
)
1996 && insn
.rd () == RISCV_SP_REGNUM
1997 && insn
.rs1 () == RISCV_SP_REGNUM
)
1999 /* Handle: addi sp, sp, -i
2000 or: addiw sp, sp, -i */
2001 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
2002 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
2004 = pv_add_constant (regs
[insn
.rs1 ()], insn
.imm_signed ());
2006 else if ((insn
.opcode () == riscv_insn::SW
2007 || insn
.opcode () == riscv_insn::SD
)
2008 && (insn
.rs1 () == RISCV_SP_REGNUM
2009 || insn
.rs1 () == RISCV_FP_REGNUM
))
2011 /* Handle: sw reg, offset(sp)
2012 or: sd reg, offset(sp)
2013 or: sw reg, offset(s0)
2014 or: sd reg, offset(s0) */
2015 /* Instruction storing a register onto the stack. */
2016 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
2017 gdb_assert (insn
.rs2 () < RISCV_NUM_INTEGER_REGS
);
2018 stack
.store (pv_add_constant (regs
[insn
.rs1 ()], insn
.imm_signed ()),
2019 (insn
.opcode () == riscv_insn::SW
? 4 : 8),
2022 else if (insn
.opcode () == riscv_insn::ADDI
2023 && insn
.rd () == RISCV_FP_REGNUM
2024 && insn
.rs1 () == RISCV_SP_REGNUM
)
2026 /* Handle: addi s0, sp, size */
2027 /* Instructions setting up the frame pointer. */
2028 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
2029 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
2031 = pv_add_constant (regs
[insn
.rs1 ()], insn
.imm_signed ());
2033 else if ((insn
.opcode () == riscv_insn::ADD
2034 || insn
.opcode () == riscv_insn::ADDW
)
2035 && insn
.rd () == RISCV_FP_REGNUM
2036 && insn
.rs1 () == RISCV_SP_REGNUM
2037 && insn
.rs2 () == RISCV_ZERO_REGNUM
)
2039 /* Handle: add s0, sp, 0
2040 or: addw s0, sp, 0 */
2041 /* Instructions setting up the frame pointer. */
2042 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
2043 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
2044 regs
[insn
.rd ()] = pv_add_constant (regs
[insn
.rs1 ()], 0);
2046 else if ((insn
.opcode () == riscv_insn::ADDI
2047 && insn
.rd () == RISCV_ZERO_REGNUM
2048 && insn
.rs1 () == RISCV_ZERO_REGNUM
2049 && insn
.imm_signed () == 0))
2051 /* Handle: add x0, x0, 0 (NOP) */
2053 else if (insn
.opcode () == riscv_insn::AUIPC
)
2055 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
2056 regs
[insn
.rd ()] = pv_constant (cur_pc
+ insn
.imm_signed ());
2058 else if (insn
.opcode () == riscv_insn::LUI
)
2060 /* Handle: lui REG, n
2061 Where REG is not gp register. */
2062 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
2063 regs
[insn
.rd ()] = pv_constant (insn
.imm_signed ());
2065 else if (insn
.opcode () == riscv_insn::ADDI
)
2067 /* Handle: addi REG1, REG2, IMM */
2068 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
2069 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
2071 = pv_add_constant (regs
[insn
.rs1 ()], insn
.imm_signed ());
2073 else if (insn
.opcode () == riscv_insn::ADD
)
2075 /* Handle: add REG1, REG2, REG3 */
2076 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
2077 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
2078 gdb_assert (insn
.rs2 () < RISCV_NUM_INTEGER_REGS
);
2079 regs
[insn
.rd ()] = pv_add (regs
[insn
.rs1 ()], regs
[insn
.rs2 ()]);
2081 else if (insn
.opcode () == riscv_insn::LD
2082 || insn
.opcode () == riscv_insn::LW
)
2084 /* Handle: ld reg, offset(rs1)
2085 or: c.ld reg, offset(rs1)
2086 or: lw reg, offset(rs1)
2087 or: c.lw reg, offset(rs1) */
2088 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
2089 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
2091 = stack
.fetch (pv_add_constant (regs
[insn
.rs1 ()],
2092 insn
.imm_signed ()),
2093 (insn
.opcode () == riscv_insn::LW
? 4 : 8));
2095 else if (insn
.opcode () == riscv_insn::MV
)
2097 /* Handle: c.mv RD, RS2 */
2098 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
2099 gdb_assert (insn
.rs2 () < RISCV_NUM_INTEGER_REGS
);
2100 gdb_assert (insn
.rs2 () > 0);
2101 regs
[insn
.rd ()] = regs
[insn
.rs2 ()];
2105 end_prologue_addr
= cur_pc
;
2110 if (end_prologue_addr
== 0)
2111 end_prologue_addr
= cur_pc
;
2113 if (riscv_debug_unwinder
)
2114 gdb_printf (gdb_stdlog
, "End of prologue at %s\n",
2115 core_addr_to_string (end_prologue_addr
));
2119 /* Figure out if it is a frame pointer or just a stack pointer. Also
2120 the offset held in the pv_t is from the original register value to
2121 the current value, which for a grows down stack means a negative
2122 value. The FRAME_BASE_OFFSET is the negation of this, how to get
2123 from the current value to the original value. */
2124 if (pv_is_register (regs
[RISCV_FP_REGNUM
], RISCV_SP_REGNUM
))
2126 cache
->frame_base_reg
= RISCV_FP_REGNUM
;
2127 cache
->frame_base_offset
= -regs
[RISCV_FP_REGNUM
].k
;
2131 cache
->frame_base_reg
= RISCV_SP_REGNUM
;
2132 cache
->frame_base_offset
= -regs
[RISCV_SP_REGNUM
].k
;
2135 /* Assign offset from old SP to all saved registers. As we don't
2136 have the previous value for the frame base register at this
2137 point, we store the offset as the address in the trad_frame, and
2138 then convert this to an actual address later. */
2139 for (int i
= 0; i
<= RISCV_NUM_INTEGER_REGS
; i
++)
2142 if (stack
.find_reg (gdbarch
, i
, &offset
))
2144 if (riscv_debug_unwinder
)
2146 /* Display OFFSET as a signed value, the offsets are from
2147 the frame base address to the registers location on
2148 the stack, with a descending stack this means the
2149 offsets are always negative. */
2150 gdb_printf (gdb_stdlog
,
2151 "Register $%s at stack offset %s\n",
2152 gdbarch_register_name (gdbarch
, i
),
2153 plongest ((LONGEST
) offset
));
2155 cache
->regs
[i
].set_addr (offset
);
2160 return end_prologue_addr
;
2163 /* Implement the riscv_skip_prologue gdbarch method. */
2166 riscv_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2168 CORE_ADDR func_addr
;
2170 /* See if we can determine the end of the prologue via the symbol
2171 table. If so, then return either PC, or the PC after the
2172 prologue, whichever is greater. */
2173 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
2175 CORE_ADDR post_prologue_pc
2176 = skip_prologue_using_sal (gdbarch
, func_addr
);
2178 if (post_prologue_pc
!= 0)
2179 return std::max (pc
, post_prologue_pc
);
2182 /* Can't determine prologue from the symbol table, need to examine
2183 instructions. Pass -1 for the end address to indicate the prologue
2184 scanner can scan as far as it needs to find the end of the prologue. */
2185 return riscv_scan_prologue (gdbarch
, pc
, ((CORE_ADDR
) -1), NULL
);
2188 /* Implement the gdbarch push dummy code callback. */
2191 riscv_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
2192 CORE_ADDR funaddr
, struct value
**args
, int nargs
,
2193 struct type
*value_type
, CORE_ADDR
*real_pc
,
2194 CORE_ADDR
*bp_addr
, struct regcache
*regcache
)
2196 /* A nop instruction is 'add x0, x0, 0'. */
2197 static const gdb_byte nop_insn
[] = { 0x13, 0x00, 0x00, 0x00 };
2199 /* Allocate space for a breakpoint, and keep the stack correctly
2200 aligned. The space allocated here must be at least big enough to
2201 accommodate the NOP_INSN defined above. */
2206 /* When we insert a breakpoint we select whether to use a compressed
2207 breakpoint or not based on the existing contents of the memory.
2209 If the breakpoint is being placed onto the stack as part of setting up
2210 for an inferior call from GDB, then the existing stack contents may
2211 randomly appear to be a compressed instruction, causing GDB to insert
2212 a compressed breakpoint. If this happens on a target that does not
2213 support compressed instructions then this could cause problems.
2215 To prevent this issue we write an uncompressed nop onto the stack at
2216 the location where the breakpoint will be inserted. In this way we
2217 ensure that we always use an uncompressed breakpoint, which should
2218 work on all targets.
2220 We call TARGET_WRITE_MEMORY here so that if the write fails we don't
2221 throw an exception. Instead we ignore the error and move on. The
2222 assumption is that either GDB will error later when actually trying to
2223 insert a software breakpoint, or GDB will use hardware breakpoints and
2224 there will be no need to write to memory later. */
2225 int status
= target_write_memory (*bp_addr
, nop_insn
, sizeof (nop_insn
));
2227 if (riscv_debug_breakpoints
|| riscv_debug_infcall
)
2228 gdb_printf (gdb_stdlog
,
2229 "Writing %s-byte nop instruction to %s: %s\n",
2230 plongest (sizeof (nop_insn
)),
2231 paddress (gdbarch
, *bp_addr
),
2232 (status
== 0 ? "success" : "failed"));
2237 /* Implement the gdbarch type alignment method, overrides the generic
2238 alignment algorithm for anything that is RISC-V specific. */
2241 riscv_type_align (gdbarch
*gdbarch
, type
*type
)
2243 type
= check_typedef (type
);
2244 if (type
->code () == TYPE_CODE_ARRAY
&& type
->is_vector ())
2245 return std::min (type
->length (), (ULONGEST
) BIGGEST_ALIGNMENT
);
2247 /* Anything else will be aligned by the generic code. */
2251 /* Holds information about a single argument either being passed to an
2252 inferior function, or returned from an inferior function. This includes
2253 information about the size, type, etc of the argument, and also
2254 information about how the argument will be passed (or returned). */
2256 struct riscv_arg_info
2258 /* Contents of the argument. */
2259 const gdb_byte
*contents
;
2261 /* Length of argument. */
2264 /* Alignment required for an argument of this type. */
2267 /* The type for this argument. */
2270 /* Each argument can have either 1 or 2 locations assigned to it. Each
2271 location describes where part of the argument will be placed. The
2272 second location is valid based on the LOC_TYPE and C_LENGTH fields
2273 of the first location (which is always valid). */
2276 /* What type of location this is. */
2279 /* Argument passed in a register. */
2282 /* Argument passed as an on stack argument. */
2285 /* Argument passed by reference. The second location is always
2286 valid for a BY_REF argument, and describes where the address
2287 of the BY_REF argument should be placed. */
2291 /* Information that depends on the location type. */
2294 /* Which register number to use. */
2297 /* The offset into the stack region. */
2301 /* The length of contents covered by this location. If this is less
2302 than the total length of the argument, then the second location
2303 will be valid, and will describe where the rest of the argument
2307 /* The offset within CONTENTS for this part of the argument. This can
2308 be non-zero even for the first part (the first field of a struct can
2309 have a non-zero offset due to padding). For the second part of the
2310 argument, this might be the C_LENGTH value of the first part,
2311 however, if we are passing a structure in two registers, and there's
2312 is padding between the first and second field, then this offset
2313 might be greater than the length of the first argument part. When
2314 the second argument location is not holding part of the argument
2315 value, but is instead holding the address of a reference argument,
2316 then this offset will be set to 0. */
2320 /* TRUE if this is an unnamed argument. */
2324 /* Information about a set of registers being used for passing arguments as
2325 part of a function call. The register set must be numerically
2326 sequential from NEXT_REGNUM to LAST_REGNUM. The register set can be
2327 disabled from use by setting NEXT_REGNUM greater than LAST_REGNUM. */
2329 struct riscv_arg_reg
2331 riscv_arg_reg (int first
, int last
)
2332 : next_regnum (first
),
2338 /* The GDB register number to use in this set. */
2341 /* The last GDB register number to use in this set. */
2345 /* Arguments can be passed as on stack arguments, or by reference. The
2346 on stack arguments must be in a continuous region starting from $sp,
2347 while the by reference arguments can be anywhere, but we'll put them
2348 on the stack after (at higher address) the on stack arguments.
2350 This might not be the right approach to take. The ABI is clear that
2351 an argument passed by reference can be modified by the callee, which
2352 us placing the argument (temporarily) onto the stack will not achieve
2353 (changes will be lost). There's also the possibility that very large
2354 arguments could overflow the stack.
2356 This struct is used to track offset into these two areas for where
2357 arguments are to be placed. */
2358 struct riscv_memory_offsets
2360 riscv_memory_offsets ()
2367 /* Offset into on stack argument area. */
2370 /* Offset into the pass by reference area. */
2374 /* Holds information about where arguments to a call will be placed. This
2375 is updated as arguments are added onto the call, and can be used to
2376 figure out where the next argument should be placed. */
2378 struct riscv_call_info
2380 riscv_call_info (struct gdbarch
*gdbarch
)
2381 : int_regs (RISCV_A0_REGNUM
, RISCV_A0_REGNUM
+ 7),
2382 float_regs (RISCV_FA0_REGNUM
, RISCV_FA0_REGNUM
+ 7)
2384 xlen
= riscv_abi_xlen (gdbarch
);
2385 flen
= riscv_abi_flen (gdbarch
);
2387 /* Reduce the number of integer argument registers when using the
2388 embedded abi (i.e. rv32e). */
2389 if (riscv_abi_embedded (gdbarch
))
2390 int_regs
.last_regnum
= RISCV_A0_REGNUM
+ 5;
2392 /* Disable use of floating point registers if needed. */
2393 if (!riscv_has_fp_abi (gdbarch
))
2394 float_regs
.next_regnum
= float_regs
.last_regnum
+ 1;
2397 /* Track the memory areas used for holding in-memory arguments to a
2399 struct riscv_memory_offsets memory
;
2401 /* Holds information about the next integer register to use for passing
2403 struct riscv_arg_reg int_regs
;
2405 /* Holds information about the next floating point register to use for
2406 passing an argument. */
2407 struct riscv_arg_reg float_regs
;
2409 /* The XLEN and FLEN are copied in to this structure for convenience, and
2410 are just the results of calling RISCV_ABI_XLEN and RISCV_ABI_FLEN. */
2415 /* Return the number of registers available for use as parameters in the
2416 register set REG. Returned value can be 0 or more. */
2419 riscv_arg_regs_available (struct riscv_arg_reg
*reg
)
2421 if (reg
->next_regnum
> reg
->last_regnum
)
2424 return (reg
->last_regnum
- reg
->next_regnum
+ 1);
2427 /* If there is at least one register available in the register set REG then
2428 the next register from REG is assigned to LOC and the length field of
2429 LOC is updated to LENGTH. The register set REG is updated to indicate
2430 that the assigned register is no longer available and the function
2433 If there are no registers available in REG then the function returns
2434 false, and LOC and REG are unchanged. */
2437 riscv_assign_reg_location (struct riscv_arg_info::location
*loc
,
2438 struct riscv_arg_reg
*reg
,
2439 int length
, int offset
)
2441 if (reg
->next_regnum
<= reg
->last_regnum
)
2443 loc
->loc_type
= riscv_arg_info::location::in_reg
;
2444 loc
->loc_data
.regno
= reg
->next_regnum
;
2446 loc
->c_length
= length
;
2447 loc
->c_offset
= offset
;
2454 /* Assign LOC a location as the next stack parameter, and update MEMORY to
2455 record that an area of stack has been used to hold the parameter
2458 The length field of LOC is updated to LENGTH, the length of the
2459 parameter being stored, and ALIGN is the alignment required by the
2460 parameter, which will affect how memory is allocated out of MEMORY. */
2463 riscv_assign_stack_location (struct riscv_arg_info::location
*loc
,
2464 struct riscv_memory_offsets
*memory
,
2465 int length
, int align
)
2467 loc
->loc_type
= riscv_arg_info::location::on_stack
;
2469 = align_up (memory
->arg_offset
, align
);
2470 loc
->loc_data
.offset
= memory
->arg_offset
;
2471 memory
->arg_offset
+= length
;
2472 loc
->c_length
= length
;
2474 /* Offset is always 0, either we're the first location part, in which
2475 case we're reading content from the start of the argument, or we're
2476 passing the address of a reference argument, so 0. */
2480 /* Update AINFO, which describes an argument that should be passed or
2481 returned using the integer ABI. The argloc fields within AINFO are
2482 updated to describe the location in which the argument will be passed to
2483 a function, or returned from a function.
2485 The CINFO structure contains the ongoing call information, the holds
2486 information such as which argument registers are remaining to be
2487 assigned to parameter, and how much memory has been used by parameters
2490 By examining the state of CINFO a suitable location can be selected,
2491 and assigned to AINFO. */
2494 riscv_call_arg_scalar_int (struct riscv_arg_info
*ainfo
,
2495 struct riscv_call_info
*cinfo
)
2497 if (ainfo
->length
> (2 * cinfo
->xlen
))
2499 /* Argument is going to be passed by reference. */
2500 ainfo
->argloc
[0].loc_type
2501 = riscv_arg_info::location::by_ref
;
2502 cinfo
->memory
.ref_offset
2503 = align_up (cinfo
->memory
.ref_offset
, ainfo
->align
);
2504 ainfo
->argloc
[0].loc_data
.offset
= cinfo
->memory
.ref_offset
;
2505 cinfo
->memory
.ref_offset
+= ainfo
->length
;
2506 ainfo
->argloc
[0].c_length
= ainfo
->length
;
2508 /* The second location for this argument is given over to holding the
2509 address of the by-reference data. Pass 0 for the offset as this
2510 is not part of the actual argument value. */
2511 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
2514 riscv_assign_stack_location (&ainfo
->argloc
[1],
2515 &cinfo
->memory
, cinfo
->xlen
,
2520 int len
= std::min (ainfo
->length
, cinfo
->xlen
);
2521 int align
= std::max (ainfo
->align
, cinfo
->xlen
);
2523 /* Unnamed arguments in registers that require 2*XLEN alignment are
2524 passed in an aligned register pair. */
2525 if (ainfo
->is_unnamed
&& (align
== cinfo
->xlen
* 2)
2526 && cinfo
->int_regs
.next_regnum
& 1)
2527 cinfo
->int_regs
.next_regnum
++;
2529 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
2530 &cinfo
->int_regs
, len
, 0))
2531 riscv_assign_stack_location (&ainfo
->argloc
[0],
2532 &cinfo
->memory
, len
, align
);
2534 if (len
< ainfo
->length
)
2536 len
= ainfo
->length
- len
;
2537 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
2538 &cinfo
->int_regs
, len
,
2540 riscv_assign_stack_location (&ainfo
->argloc
[1],
2541 &cinfo
->memory
, len
, cinfo
->xlen
);
2546 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
2547 is being passed with the floating point ABI. */
2550 riscv_call_arg_scalar_float (struct riscv_arg_info
*ainfo
,
2551 struct riscv_call_info
*cinfo
)
2553 if (ainfo
->length
> cinfo
->flen
|| ainfo
->is_unnamed
)
2554 return riscv_call_arg_scalar_int (ainfo
, cinfo
);
2557 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
2560 return riscv_call_arg_scalar_int (ainfo
, cinfo
);
2564 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
2565 is a complex floating point argument, and is therefore handled
2566 differently to other argument types. */
2569 riscv_call_arg_complex_float (struct riscv_arg_info
*ainfo
,
2570 struct riscv_call_info
*cinfo
)
2572 if (ainfo
->length
<= (2 * cinfo
->flen
)
2573 && riscv_arg_regs_available (&cinfo
->float_regs
) >= 2
2574 && !ainfo
->is_unnamed
)
2577 int len
= ainfo
->length
/ 2;
2579 result
= riscv_assign_reg_location (&ainfo
->argloc
[0],
2580 &cinfo
->float_regs
, len
, 0);
2581 gdb_assert (result
);
2583 result
= riscv_assign_reg_location (&ainfo
->argloc
[1],
2584 &cinfo
->float_regs
, len
, len
);
2585 gdb_assert (result
);
2588 return riscv_call_arg_scalar_int (ainfo
, cinfo
);
2591 /* A structure used for holding information about a structure type within
2592 the inferior program. The RiscV ABI has special rules for handling some
2593 structures with a single field or with two fields. The counting of
2594 fields here is done after flattening out all nested structures. */
2596 class riscv_struct_info
2599 riscv_struct_info ()
2600 : m_number_of_fields (0),
2601 m_types
{ nullptr, nullptr },
2607 /* Analyse TYPE descending into nested structures, count the number of
2608 scalar fields and record the types of the first two fields found. */
2609 void analyse (struct type
*type
)
2611 analyse_inner (type
, 0);
2614 /* The number of scalar fields found in the analysed type. This is
2615 currently only accurate if the value returned is 0, 1, or 2 as the
2616 analysis stops counting when the number of fields is 3. This is
2617 because the RiscV ABI only has special cases for 1 or 2 fields,
2618 anything else we just don't care about. */
2619 int number_of_fields () const
2620 { return m_number_of_fields
; }
2622 /* Return the type for scalar field INDEX within the analysed type. Will
2623 return nullptr if there is no field at that index. Only INDEX values
2624 0 and 1 can be requested as the RiscV ABI only has special cases for
2625 structures with 1 or 2 fields. */
2626 struct type
*field_type (int index
) const
2628 gdb_assert (index
< (sizeof (m_types
) / sizeof (m_types
[0])));
2629 return m_types
[index
];
2632 /* Return the offset of scalar field INDEX within the analysed type. Will
2633 return 0 if there is no field at that index. Only INDEX values 0 and
2634 1 can be requested as the RiscV ABI only has special cases for
2635 structures with 1 or 2 fields. */
2636 int field_offset (int index
) const
2638 gdb_assert (index
< (sizeof (m_offsets
) / sizeof (m_offsets
[0])));
2639 return m_offsets
[index
];
2643 /* The number of scalar fields found within the structure after recursing
2644 into nested structures. */
2645 int m_number_of_fields
;
2647 /* The types of the first two scalar fields found within the structure
2648 after recursing into nested structures. */
2649 struct type
*m_types
[2];
2651 /* The offsets of the first two scalar fields found within the structure
2652 after recursing into nested structures. */
2655 /* Recursive core for ANALYSE, the OFFSET parameter tracks the byte
2656 offset from the start of the top level structure being analysed. */
2657 void analyse_inner (struct type
*type
, int offset
);
2660 /* See description in class declaration. */
2663 riscv_struct_info::analyse_inner (struct type
*type
, int offset
)
2665 unsigned int count
= type
->num_fields ();
2668 for (i
= 0; i
< count
; ++i
)
2670 if (type
->field (i
).loc_kind () != FIELD_LOC_KIND_BITPOS
)
2673 struct type
*field_type
= type
->field (i
).type ();
2674 field_type
= check_typedef (field_type
);
2676 = offset
+ type
->field (i
).loc_bitpos () / TARGET_CHAR_BIT
;
2678 switch (field_type
->code ())
2680 case TYPE_CODE_STRUCT
:
2681 analyse_inner (field_type
, field_offset
);
2685 /* RiscV only flattens out structures. Anything else does not
2686 need to be flattened, we just record the type, and when we
2687 look at the analysis results we'll realise this is not a
2688 structure we can special case, and pass the structure in
2690 if (m_number_of_fields
< 2)
2692 m_types
[m_number_of_fields
] = field_type
;
2693 m_offsets
[m_number_of_fields
] = field_offset
;
2695 m_number_of_fields
++;
2699 /* RiscV only has special handling for structures with 1 or 2 scalar
2700 fields, any more than that and the structure is just passed in
2701 memory. We can safely drop out early when we find 3 or more
2704 if (m_number_of_fields
> 2)
2709 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
2710 is a structure. Small structures on RiscV have some special case
2711 handling in order that the structure might be passed in register.
2712 Larger structures are passed in memory. After assigning location
2713 information to AINFO, CINFO will have been updated. */
2716 riscv_call_arg_struct (struct riscv_arg_info
*ainfo
,
2717 struct riscv_call_info
*cinfo
)
2719 if (riscv_arg_regs_available (&cinfo
->float_regs
) >= 1)
2721 struct riscv_struct_info sinfo
;
2723 sinfo
.analyse (ainfo
->type
);
2724 if (sinfo
.number_of_fields () == 1
2725 && sinfo
.field_type(0)->code () == TYPE_CODE_COMPLEX
)
2727 /* The following is similar to RISCV_CALL_ARG_COMPLEX_FLOAT,
2728 except we use the type of the complex field instead of the
2729 type from AINFO, and the first location might be at a non-zero
2731 if (sinfo
.field_type (0)->length () <= (2 * cinfo
->flen
)
2732 && riscv_arg_regs_available (&cinfo
->float_regs
) >= 2
2733 && !ainfo
->is_unnamed
)
2736 int len
= sinfo
.field_type (0)->length () / 2;
2737 int offset
= sinfo
.field_offset (0);
2739 result
= riscv_assign_reg_location (&ainfo
->argloc
[0],
2740 &cinfo
->float_regs
, len
,
2742 gdb_assert (result
);
2744 result
= riscv_assign_reg_location (&ainfo
->argloc
[1],
2745 &cinfo
->float_regs
, len
,
2747 gdb_assert (result
);
2750 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2754 if (sinfo
.number_of_fields () == 1
2755 && sinfo
.field_type(0)->code () == TYPE_CODE_FLT
)
2757 /* The following is similar to RISCV_CALL_ARG_SCALAR_FLOAT,
2758 except we use the type of the first scalar field instead of
2759 the type from AINFO. Also the location might be at a non-zero
2761 if (sinfo
.field_type (0)->length () > cinfo
->flen
2762 || ainfo
->is_unnamed
)
2763 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2766 int offset
= sinfo
.field_offset (0);
2767 int len
= sinfo
.field_type (0)->length ();
2769 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
2772 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2777 if (sinfo
.number_of_fields () == 2
2778 && sinfo
.field_type(0)->code () == TYPE_CODE_FLT
2779 && sinfo
.field_type (0)->length () <= cinfo
->flen
2780 && sinfo
.field_type(1)->code () == TYPE_CODE_FLT
2781 && sinfo
.field_type (1)->length () <= cinfo
->flen
2782 && riscv_arg_regs_available (&cinfo
->float_regs
) >= 2)
2784 int len0
= sinfo
.field_type (0)->length ();
2785 int offset
= sinfo
.field_offset (0);
2786 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
2787 &cinfo
->float_regs
, len0
, offset
))
2788 error (_("failed during argument setup"));
2790 int len1
= sinfo
.field_type (1)->length ();
2791 offset
= sinfo
.field_offset (1);
2792 gdb_assert (len1
<= (ainfo
->type
->length ()
2793 - sinfo
.field_type (0)->length ()));
2795 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
2798 error (_("failed during argument setup"));
2802 if (sinfo
.number_of_fields () == 2
2803 && riscv_arg_regs_available (&cinfo
->int_regs
) >= 1
2804 && (sinfo
.field_type(0)->code () == TYPE_CODE_FLT
2805 && sinfo
.field_type (0)->length () <= cinfo
->flen
2806 && is_integral_type (sinfo
.field_type (1))
2807 && sinfo
.field_type (1)->length () <= cinfo
->xlen
))
2809 int len0
= sinfo
.field_type (0)->length ();
2810 int offset
= sinfo
.field_offset (0);
2811 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
2812 &cinfo
->float_regs
, len0
, offset
))
2813 error (_("failed during argument setup"));
2815 int len1
= sinfo
.field_type (1)->length ();
2816 offset
= sinfo
.field_offset (1);
2817 gdb_assert (len1
<= cinfo
->xlen
);
2818 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
2819 &cinfo
->int_regs
, len1
, offset
))
2820 error (_("failed during argument setup"));
2824 if (sinfo
.number_of_fields () == 2
2825 && riscv_arg_regs_available (&cinfo
->int_regs
) >= 1
2826 && (is_integral_type (sinfo
.field_type (0))
2827 && sinfo
.field_type (0)->length () <= cinfo
->xlen
2828 && sinfo
.field_type(1)->code () == TYPE_CODE_FLT
2829 && sinfo
.field_type (1)->length () <= cinfo
->flen
))
2831 int len0
= sinfo
.field_type (0)->length ();
2832 int len1
= sinfo
.field_type (1)->length ();
2834 gdb_assert (len0
<= cinfo
->xlen
);
2835 gdb_assert (len1
<= cinfo
->flen
);
2837 int offset
= sinfo
.field_offset (0);
2838 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
2839 &cinfo
->int_regs
, len0
, offset
))
2840 error (_("failed during argument setup"));
2842 offset
= sinfo
.field_offset (1);
2843 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
2846 error (_("failed during argument setup"));
2852 /* Non of the structure flattening cases apply, so we just pass using
2854 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2857 /* Assign a location to call (or return) argument AINFO, the location is
2858 selected from CINFO which holds information about what call argument
2859 locations are available for use next. The TYPE is the type of the
2860 argument being passed, this information is recorded into AINFO (along
2861 with some additional information derived from the type). IS_UNNAMED
2862 is true if this is an unnamed (stdarg) argument, this info is also
2863 recorded into AINFO.
2865 After assigning a location to AINFO, CINFO will have been updated. */
2868 riscv_arg_location (struct gdbarch
*gdbarch
,
2869 struct riscv_arg_info
*ainfo
,
2870 struct riscv_call_info
*cinfo
,
2871 struct type
*type
, bool is_unnamed
)
2874 ainfo
->length
= ainfo
->type
->length ();
2875 ainfo
->align
= type_align (ainfo
->type
);
2876 ainfo
->is_unnamed
= is_unnamed
;
2877 ainfo
->contents
= nullptr;
2878 ainfo
->argloc
[0].c_length
= 0;
2879 ainfo
->argloc
[1].c_length
= 0;
2881 switch (ainfo
->type
->code ())
2884 case TYPE_CODE_BOOL
:
2885 case TYPE_CODE_CHAR
:
2886 case TYPE_CODE_RANGE
:
2887 case TYPE_CODE_ENUM
:
2889 case TYPE_CODE_FIXED_POINT
:
2890 if (ainfo
->length
<= cinfo
->xlen
)
2892 ainfo
->type
= builtin_type (gdbarch
)->builtin_long
;
2893 ainfo
->length
= cinfo
->xlen
;
2895 else if (ainfo
->length
<= (2 * cinfo
->xlen
))
2897 ainfo
->type
= builtin_type (gdbarch
)->builtin_long_long
;
2898 ainfo
->length
= 2 * cinfo
->xlen
;
2901 /* Recalculate the alignment requirement. */
2902 ainfo
->align
= type_align (ainfo
->type
);
2903 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2907 riscv_call_arg_scalar_float (ainfo
, cinfo
);
2910 case TYPE_CODE_COMPLEX
:
2911 riscv_call_arg_complex_float (ainfo
, cinfo
);
2914 case TYPE_CODE_STRUCT
:
2915 riscv_call_arg_struct (ainfo
, cinfo
);
2919 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2924 /* Used for printing debug information about the call argument location in
2925 INFO to STREAM. The addresses in SP_REFS and SP_ARGS are the base
2926 addresses for the location of pass-by-reference and
2927 arguments-on-the-stack memory areas. */
2930 riscv_print_arg_location (ui_file
*stream
, struct gdbarch
*gdbarch
,
2931 struct riscv_arg_info
*info
,
2932 CORE_ADDR sp_refs
, CORE_ADDR sp_args
)
2934 gdb_printf (stream
, "type: '%s', length: 0x%x, alignment: 0x%x",
2935 TYPE_SAFE_NAME (info
->type
), info
->length
, info
->align
);
2936 switch (info
->argloc
[0].loc_type
)
2938 case riscv_arg_info::location::in_reg
:
2940 (stream
, ", register %s",
2941 gdbarch_register_name (gdbarch
, info
->argloc
[0].loc_data
.regno
));
2942 if (info
->argloc
[0].c_length
< info
->length
)
2944 switch (info
->argloc
[1].loc_type
)
2946 case riscv_arg_info::location::in_reg
:
2948 (stream
, ", register %s",
2949 gdbarch_register_name (gdbarch
,
2950 info
->argloc
[1].loc_data
.regno
));
2953 case riscv_arg_info::location::on_stack
:
2954 gdb_printf (stream
, ", on stack at offset 0x%x",
2955 info
->argloc
[1].loc_data
.offset
);
2958 case riscv_arg_info::location::by_ref
:
2960 /* The second location should never be a reference, any
2961 argument being passed by reference just places its address
2962 in the first location and is done. */
2963 error (_("invalid argument location"));
2967 if (info
->argloc
[1].c_offset
> info
->argloc
[0].c_length
)
2968 gdb_printf (stream
, " (offset 0x%x)",
2969 info
->argloc
[1].c_offset
);
2973 case riscv_arg_info::location::on_stack
:
2974 gdb_printf (stream
, ", on stack at offset 0x%x",
2975 info
->argloc
[0].loc_data
.offset
);
2978 case riscv_arg_info::location::by_ref
:
2980 (stream
, ", by reference, data at offset 0x%x (%s)",
2981 info
->argloc
[0].loc_data
.offset
,
2982 core_addr_to_string (sp_refs
+ info
->argloc
[0].loc_data
.offset
));
2983 if (info
->argloc
[1].loc_type
2984 == riscv_arg_info::location::in_reg
)
2986 (stream
, ", address in register %s",
2987 gdbarch_register_name (gdbarch
, info
->argloc
[1].loc_data
.regno
));
2990 gdb_assert (info
->argloc
[1].loc_type
2991 == riscv_arg_info::location::on_stack
);
2993 (stream
, ", address on stack at offset 0x%x (%s)",
2994 info
->argloc
[1].loc_data
.offset
,
2995 core_addr_to_string (sp_args
+ info
->argloc
[1].loc_data
.offset
));
3000 gdb_assert_not_reached ("unknown argument location type");
3004 /* Wrapper around REGCACHE->cooked_write. Places the LEN bytes of DATA
3005 into a buffer that is at least as big as the register REGNUM, padding
3006 out the DATA with either 0x00, or 0xff. For floating point registers
3007 0xff is used, for everyone else 0x00 is used. */
3010 riscv_regcache_cooked_write (int regnum
, const gdb_byte
*data
, int len
,
3011 struct regcache
*regcache
, int flen
)
3013 gdb_byte tmp
[sizeof (ULONGEST
)];
3015 /* FP values in FP registers must be NaN-boxed. */
3016 if (riscv_is_fp_regno_p (regnum
) && len
< flen
)
3017 memset (tmp
, -1, sizeof (tmp
));
3019 memset (tmp
, 0, sizeof (tmp
));
3020 memcpy (tmp
, data
, len
);
3021 regcache
->cooked_write (regnum
, tmp
);
3024 /* Implement the push dummy call gdbarch callback. */
3027 riscv_push_dummy_call (struct gdbarch
*gdbarch
,
3028 struct value
*function
,
3029 struct regcache
*regcache
,
3032 struct value
**args
,
3034 function_call_return_method return_method
,
3035 CORE_ADDR struct_addr
)
3038 CORE_ADDR sp_args
, sp_refs
;
3039 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3041 struct riscv_arg_info
*arg_info
=
3042 (struct riscv_arg_info
*) alloca (nargs
* sizeof (struct riscv_arg_info
));
3044 struct riscv_call_info
call_info (gdbarch
);
3048 struct type
*ftype
= check_typedef (value_type (function
));
3050 if (ftype
->code () == TYPE_CODE_PTR
)
3051 ftype
= check_typedef (ftype
->target_type ());
3053 /* We'll use register $a0 if we're returning a struct. */
3054 if (return_method
== return_method_struct
)
3055 ++call_info
.int_regs
.next_regnum
;
3057 for (i
= 0; i
< nargs
; ++i
)
3059 struct value
*arg_value
;
3060 struct type
*arg_type
;
3061 struct riscv_arg_info
*info
= &arg_info
[i
];
3063 arg_value
= args
[i
];
3064 arg_type
= check_typedef (value_type (arg_value
));
3066 riscv_arg_location (gdbarch
, info
, &call_info
, arg_type
,
3067 ftype
->has_varargs () && i
>= ftype
->num_fields ());
3069 if (info
->type
!= arg_type
)
3070 arg_value
= value_cast (info
->type
, arg_value
);
3071 info
->contents
= value_contents (arg_value
).data ();
3074 /* Adjust the stack pointer and align it. */
3075 sp
= sp_refs
= align_down (sp
- call_info
.memory
.ref_offset
, SP_ALIGNMENT
);
3076 sp
= sp_args
= align_down (sp
- call_info
.memory
.arg_offset
, SP_ALIGNMENT
);
3078 if (riscv_debug_infcall
> 0)
3080 gdb_printf (gdb_stdlog
, "dummy call args:\n");
3081 gdb_printf (gdb_stdlog
, ": floating point ABI %s in use\n",
3082 (riscv_has_fp_abi (gdbarch
) ? "is" : "is not"));
3083 gdb_printf (gdb_stdlog
, ": xlen: %d\n: flen: %d\n",
3084 call_info
.xlen
, call_info
.flen
);
3085 if (return_method
== return_method_struct
)
3086 gdb_printf (gdb_stdlog
,
3087 "[*] struct return pointer in register $A0\n");
3088 for (i
= 0; i
< nargs
; ++i
)
3090 struct riscv_arg_info
*info
= &arg_info
[i
];
3092 gdb_printf (gdb_stdlog
, "[%2d] ", i
);
3093 riscv_print_arg_location (gdb_stdlog
, gdbarch
, info
, sp_refs
, sp_args
);
3094 gdb_printf (gdb_stdlog
, "\n");
3096 if (call_info
.memory
.arg_offset
> 0
3097 || call_info
.memory
.ref_offset
> 0)
3099 gdb_printf (gdb_stdlog
, " Original sp: %s\n",
3100 core_addr_to_string (osp
));
3101 gdb_printf (gdb_stdlog
, "Stack required (for args): 0x%x\n",
3102 call_info
.memory
.arg_offset
);
3103 gdb_printf (gdb_stdlog
, "Stack required (for refs): 0x%x\n",
3104 call_info
.memory
.ref_offset
);
3105 gdb_printf (gdb_stdlog
, " Stack allocated: %s\n",
3106 core_addr_to_string_nz (osp
- sp
));
3110 /* Now load the argument into registers, or onto the stack. */
3112 if (return_method
== return_method_struct
)
3114 gdb_byte buf
[sizeof (LONGEST
)];
3116 store_unsigned_integer (buf
, call_info
.xlen
, byte_order
, struct_addr
);
3117 regcache
->cooked_write (RISCV_A0_REGNUM
, buf
);
3120 for (i
= 0; i
< nargs
; ++i
)
3123 int second_arg_length
= 0;
3124 const gdb_byte
*second_arg_data
;
3125 struct riscv_arg_info
*info
= &arg_info
[i
];
3127 gdb_assert (info
->length
> 0);
3129 switch (info
->argloc
[0].loc_type
)
3131 case riscv_arg_info::location::in_reg
:
3133 gdb_assert (info
->argloc
[0].c_length
<= info
->length
);
3135 riscv_regcache_cooked_write (info
->argloc
[0].loc_data
.regno
,
3137 + info
->argloc
[0].c_offset
),
3138 info
->argloc
[0].c_length
,
3139 regcache
, call_info
.flen
);
3141 (((info
->argloc
[0].c_length
+ info
->argloc
[0].c_offset
) < info
->length
)
3142 ? info
->argloc
[1].c_length
: 0);
3143 second_arg_data
= info
->contents
+ info
->argloc
[1].c_offset
;
3147 case riscv_arg_info::location::on_stack
:
3148 dst
= sp_args
+ info
->argloc
[0].loc_data
.offset
;
3149 write_memory (dst
, info
->contents
, info
->length
);
3150 second_arg_length
= 0;
3153 case riscv_arg_info::location::by_ref
:
3154 dst
= sp_refs
+ info
->argloc
[0].loc_data
.offset
;
3155 write_memory (dst
, info
->contents
, info
->length
);
3157 second_arg_length
= call_info
.xlen
;
3158 second_arg_data
= (gdb_byte
*) &dst
;
3162 gdb_assert_not_reached ("unknown argument location type");
3165 if (second_arg_length
> 0)
3167 switch (info
->argloc
[1].loc_type
)
3169 case riscv_arg_info::location::in_reg
:
3171 gdb_assert ((riscv_is_fp_regno_p (info
->argloc
[1].loc_data
.regno
)
3172 && second_arg_length
<= call_info
.flen
)
3173 || second_arg_length
<= call_info
.xlen
);
3174 riscv_regcache_cooked_write (info
->argloc
[1].loc_data
.regno
,
3177 regcache
, call_info
.flen
);
3181 case riscv_arg_info::location::on_stack
:
3185 arg_addr
= sp_args
+ info
->argloc
[1].loc_data
.offset
;
3186 write_memory (arg_addr
, second_arg_data
, second_arg_length
);
3190 case riscv_arg_info::location::by_ref
:
3192 /* The second location should never be a reference, any
3193 argument being passed by reference just places its address
3194 in the first location and is done. */
3195 error (_("invalid argument location"));
3201 /* Set the dummy return value to bp_addr.
3202 A dummy breakpoint will be setup to execute the call. */
3204 if (riscv_debug_infcall
> 0)
3205 gdb_printf (gdb_stdlog
, ": writing $ra = %s\n",
3206 core_addr_to_string (bp_addr
));
3207 regcache_cooked_write_unsigned (regcache
, RISCV_RA_REGNUM
, bp_addr
);
3209 /* Finally, update the stack pointer. */
3211 if (riscv_debug_infcall
> 0)
3212 gdb_printf (gdb_stdlog
, ": writing $sp = %s\n",
3213 core_addr_to_string (sp
));
3214 regcache_cooked_write_unsigned (regcache
, RISCV_SP_REGNUM
, sp
);
3219 /* Implement the return_value gdbarch method. */
3221 static enum return_value_convention
3222 riscv_return_value (struct gdbarch
*gdbarch
,
3223 struct value
*function
,
3225 struct regcache
*regcache
,
3227 const gdb_byte
*writebuf
)
3229 struct riscv_call_info
call_info (gdbarch
);
3230 struct riscv_arg_info info
;
3231 struct type
*arg_type
;
3233 arg_type
= check_typedef (type
);
3234 riscv_arg_location (gdbarch
, &info
, &call_info
, arg_type
, false);
3236 if (riscv_debug_infcall
> 0)
3238 gdb_printf (gdb_stdlog
, "riscv return value:\n");
3239 gdb_printf (gdb_stdlog
, "[R] ");
3240 riscv_print_arg_location (gdb_stdlog
, gdbarch
, &info
, 0, 0);
3241 gdb_printf (gdb_stdlog
, "\n");
3244 if (readbuf
!= nullptr || writebuf
!= nullptr)
3246 unsigned int arg_len
;
3247 struct value
*abi_val
;
3248 gdb_byte
*old_readbuf
= nullptr;
3251 /* We only do one thing at a time. */
3252 gdb_assert (readbuf
== nullptr || writebuf
== nullptr);
3254 /* In some cases the argument is not returned as the declared type,
3255 and we need to cast to or from the ABI type in order to
3256 correctly access the argument. When writing to the machine we
3257 do the cast here, when reading from the machine the cast occurs
3258 later, after extracting the value. As the ABI type can be
3259 larger than the declared type, then the read or write buffers
3260 passed in might be too small. Here we ensure that we are using
3261 buffers of sufficient size. */
3262 if (writebuf
!= nullptr)
3264 struct value
*arg_val
;
3266 if (is_fixed_point_type (arg_type
))
3268 /* Convert the argument to the type used to pass
3269 the return value, but being careful to preserve
3270 the fact that the value needs to be returned
3274 unscaled
.read (gdb::make_array_view (writebuf
,
3275 arg_type
->length ()),
3276 type_byte_order (arg_type
),
3277 arg_type
->is_unsigned ());
3278 abi_val
= allocate_value (info
.type
);
3279 unscaled
.write (value_contents_raw (abi_val
),
3280 type_byte_order (info
.type
),
3281 info
.type
->is_unsigned ());
3285 arg_val
= value_from_contents (arg_type
, writebuf
);
3286 abi_val
= value_cast (info
.type
, arg_val
);
3288 writebuf
= value_contents_raw (abi_val
).data ();
3292 abi_val
= allocate_value (info
.type
);
3293 old_readbuf
= readbuf
;
3294 readbuf
= value_contents_raw (abi_val
).data ();
3296 arg_len
= info
.type
->length ();
3298 switch (info
.argloc
[0].loc_type
)
3300 /* Return value in register(s). */
3301 case riscv_arg_info::location::in_reg
:
3303 regnum
= info
.argloc
[0].loc_data
.regno
;
3304 gdb_assert (info
.argloc
[0].c_length
<= arg_len
);
3305 gdb_assert (info
.argloc
[0].c_length
3306 <= register_size (gdbarch
, regnum
));
3310 gdb_byte
*ptr
= readbuf
+ info
.argloc
[0].c_offset
;
3311 regcache
->cooked_read_part (regnum
, 0,
3312 info
.argloc
[0].c_length
,
3318 const gdb_byte
*ptr
= writebuf
+ info
.argloc
[0].c_offset
;
3319 riscv_regcache_cooked_write (regnum
, ptr
,
3320 info
.argloc
[0].c_length
,
3321 regcache
, call_info
.flen
);
3324 /* A return value in register can have a second part in a
3326 if (info
.argloc
[1].c_length
> 0)
3328 switch (info
.argloc
[1].loc_type
)
3330 case riscv_arg_info::location::in_reg
:
3331 regnum
= info
.argloc
[1].loc_data
.regno
;
3333 gdb_assert ((info
.argloc
[0].c_length
3334 + info
.argloc
[1].c_length
) <= arg_len
);
3335 gdb_assert (info
.argloc
[1].c_length
3336 <= register_size (gdbarch
, regnum
));
3340 readbuf
+= info
.argloc
[1].c_offset
;
3341 regcache
->cooked_read_part (regnum
, 0,
3342 info
.argloc
[1].c_length
,
3349 = writebuf
+ info
.argloc
[1].c_offset
;
3350 riscv_regcache_cooked_write
3351 (regnum
, ptr
, info
.argloc
[1].c_length
,
3352 regcache
, call_info
.flen
);
3356 case riscv_arg_info::location::by_ref
:
3357 case riscv_arg_info::location::on_stack
:
3359 error (_("invalid argument location"));
3366 /* Return value by reference will have its address in A0. */
3367 case riscv_arg_info::location::by_ref
:
3371 regcache_cooked_read_unsigned (regcache
, RISCV_A0_REGNUM
,
3373 if (readbuf
!= nullptr)
3374 read_memory (addr
, readbuf
, info
.length
);
3375 if (writebuf
!= nullptr)
3376 write_memory (addr
, writebuf
, info
.length
);
3380 case riscv_arg_info::location::on_stack
:
3382 error (_("invalid argument location"));
3386 /* This completes the cast from abi type back to the declared type
3387 in the case that we are reading from the machine. See the
3388 comment at the head of this block for more details. */
3389 if (readbuf
!= nullptr)
3391 struct value
*arg_val
;
3393 if (is_fixed_point_type (arg_type
))
3395 /* Convert abi_val to the actual return type, but
3396 being careful to preserve the fact that abi_val
3400 unscaled
.read (value_contents (abi_val
),
3401 type_byte_order (info
.type
),
3402 info
.type
->is_unsigned ());
3403 arg_val
= allocate_value (arg_type
);
3404 unscaled
.write (value_contents_raw (arg_val
),
3405 type_byte_order (arg_type
),
3406 arg_type
->is_unsigned ());
3409 arg_val
= value_cast (arg_type
, abi_val
);
3410 memcpy (old_readbuf
, value_contents_raw (arg_val
).data (),
3411 arg_type
->length ());
3415 switch (info
.argloc
[0].loc_type
)
3417 case riscv_arg_info::location::in_reg
:
3418 return RETURN_VALUE_REGISTER_CONVENTION
;
3419 case riscv_arg_info::location::by_ref
:
3420 return RETURN_VALUE_ABI_PRESERVES_ADDRESS
;
3421 case riscv_arg_info::location::on_stack
:
3423 error (_("invalid argument location"));
3427 /* Implement the frame_align gdbarch method. */
3430 riscv_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
3432 return align_down (addr
, 16);
3435 /* Generate, or return the cached frame cache for the RiscV frame
3438 static struct riscv_unwind_cache
*
3439 riscv_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3441 CORE_ADDR pc
, start_addr
;
3442 struct riscv_unwind_cache
*cache
;
3443 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3446 if ((*this_cache
) != NULL
)
3447 return (struct riscv_unwind_cache
*) *this_cache
;
3449 cache
= FRAME_OBSTACK_ZALLOC (struct riscv_unwind_cache
);
3450 cache
->regs
= trad_frame_alloc_saved_regs (this_frame
);
3451 (*this_cache
) = cache
;
3453 /* Scan the prologue, filling in the cache. */
3454 start_addr
= get_frame_func (this_frame
);
3455 pc
= get_frame_pc (this_frame
);
3456 riscv_scan_prologue (gdbarch
, start_addr
, pc
, cache
);
3458 /* We can now calculate the frame base address. */
3460 = (get_frame_register_unsigned (this_frame
, cache
->frame_base_reg
)
3461 + cache
->frame_base_offset
);
3462 if (riscv_debug_unwinder
)
3463 gdb_printf (gdb_stdlog
, "Frame base is %s ($%s + 0x%x)\n",
3464 core_addr_to_string (cache
->frame_base
),
3465 gdbarch_register_name (gdbarch
,
3466 cache
->frame_base_reg
),
3467 cache
->frame_base_offset
);
3469 /* The prologue scanner sets the address of registers stored to the stack
3470 as the offset of that register from the frame base. The prologue
3471 scanner doesn't know the actual frame base value, and so is unable to
3472 compute the exact address. We do now know the frame base value, so
3473 update the address of registers stored to the stack. */
3474 numregs
= gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
3475 for (regno
= 0; regno
< numregs
; ++regno
)
3477 if (cache
->regs
[regno
].is_addr ())
3478 cache
->regs
[regno
].set_addr (cache
->regs
[regno
].addr ()
3479 + cache
->frame_base
);
3482 /* The previous $pc can be found wherever the $ra value can be found.
3483 The previous $ra value is gone, this would have been stored be the
3484 previous frame if required. */
3485 cache
->regs
[gdbarch_pc_regnum (gdbarch
)] = cache
->regs
[RISCV_RA_REGNUM
];
3486 cache
->regs
[RISCV_RA_REGNUM
].set_unknown ();
3488 /* Build the frame id. */
3489 cache
->this_id
= frame_id_build (cache
->frame_base
, start_addr
);
3491 /* The previous $sp value is the frame base value. */
3492 cache
->regs
[gdbarch_sp_regnum (gdbarch
)].set_value (cache
->frame_base
);
3497 /* Implement the this_id callback for RiscV frame unwinder. */
3500 riscv_frame_this_id (struct frame_info
*this_frame
,
3501 void **prologue_cache
,
3502 struct frame_id
*this_id
)
3504 struct riscv_unwind_cache
*cache
;
3508 cache
= riscv_frame_cache (this_frame
, prologue_cache
);
3509 *this_id
= cache
->this_id
;
3511 catch (const gdb_exception_error
&ex
)
3513 /* Ignore errors, this leaves the frame id as the predefined outer
3514 frame id which terminates the backtrace at this point. */
3518 /* Implement the prev_register callback for RiscV frame unwinder. */
3520 static struct value
*
3521 riscv_frame_prev_register (struct frame_info
*this_frame
,
3522 void **prologue_cache
,
3525 struct riscv_unwind_cache
*cache
;
3527 cache
= riscv_frame_cache (this_frame
, prologue_cache
);
3528 return trad_frame_get_prev_register (this_frame
, cache
->regs
, regnum
);
3531 /* Structure defining the RiscV normal frame unwind functions. Since we
3532 are the fallback unwinder (DWARF unwinder is used first), we use the
3533 default frame sniffer, which always accepts the frame. */
3535 static const struct frame_unwind riscv_frame_unwind
=
3537 /*.name =*/ "riscv prologue",
3538 /*.type =*/ NORMAL_FRAME
,
3539 /*.stop_reason =*/ default_frame_unwind_stop_reason
,
3540 /*.this_id =*/ riscv_frame_this_id
,
3541 /*.prev_register =*/ riscv_frame_prev_register
,
3542 /*.unwind_data =*/ NULL
,
3543 /*.sniffer =*/ default_frame_sniffer
,
3544 /*.dealloc_cache =*/ NULL
,
3545 /*.prev_arch =*/ NULL
,
3548 /* Extract a set of required target features out of ABFD. If ABFD is
3549 nullptr then a RISCV_GDBARCH_FEATURES is returned in its default state. */
3551 static struct riscv_gdbarch_features
3552 riscv_features_from_bfd (const bfd
*abfd
)
3554 struct riscv_gdbarch_features features
;
3556 /* Now try to improve on the defaults by looking at the binary we are
3557 going to execute. We assume the user knows what they are doing and
3558 that the target will match the binary. Remember, this code path is
3559 only used at all if the target hasn't given us a description, so this
3560 is really a last ditched effort to do something sane before giving
3562 if (abfd
!= nullptr && bfd_get_flavour (abfd
) == bfd_target_elf_flavour
)
3564 unsigned char eclass
= elf_elfheader (abfd
)->e_ident
[EI_CLASS
];
3565 int e_flags
= elf_elfheader (abfd
)->e_flags
;
3567 if (eclass
== ELFCLASS32
)
3569 else if (eclass
== ELFCLASS64
)
3572 internal_error (__FILE__
, __LINE__
,
3573 _("unknown ELF header class %d"), eclass
);
3575 if (e_flags
& EF_RISCV_FLOAT_ABI_DOUBLE
)
3577 else if (e_flags
& EF_RISCV_FLOAT_ABI_SINGLE
)
3580 if (e_flags
& EF_RISCV_RVE
)
3582 if (features
.xlen
== 8)
3584 warning (_("64-bit ELF with RV32E flag set! Assuming 32-bit"));
3587 features
.embedded
= true;
3594 /* Find a suitable default target description. Use the contents of INFO,
3595 specifically the bfd object being executed, to guide the selection of a
3596 suitable default target description. */
3598 static const struct target_desc
*
3599 riscv_find_default_target_description (const struct gdbarch_info info
)
3601 /* Extract desired feature set from INFO. */
3602 struct riscv_gdbarch_features features
3603 = riscv_features_from_bfd (info
.abfd
);
3605 /* If the XLEN field is still 0 then we got nothing useful from INFO.BFD,
3606 maybe there was no bfd object. In this case we fall back to a minimal
3607 useful target with no floating point, the x-register size is selected
3608 based on the architecture from INFO. */
3609 if (features
.xlen
== 0)
3610 features
.xlen
= info
.bfd_arch_info
->bits_per_word
== 32 ? 4 : 8;
3612 /* Now build a target description based on the feature set. */
3613 return riscv_lookup_target_description (features
);
3616 /* Add all the RISC-V specific register groups into GDBARCH. */
3619 riscv_add_reggroups (struct gdbarch
*gdbarch
)
3621 reggroup_add (gdbarch
, csr_reggroup
);
3624 /* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
3627 riscv_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
3629 if (reg
< RISCV_DWARF_REGNUM_X31
)
3630 return RISCV_ZERO_REGNUM
+ (reg
- RISCV_DWARF_REGNUM_X0
);
3632 else if (reg
< RISCV_DWARF_REGNUM_F31
)
3633 return RISCV_FIRST_FP_REGNUM
+ (reg
- RISCV_DWARF_REGNUM_F0
);
3635 else if (reg
>= RISCV_DWARF_FIRST_CSR
&& reg
<= RISCV_DWARF_LAST_CSR
)
3636 return RISCV_FIRST_CSR_REGNUM
+ (reg
- RISCV_DWARF_FIRST_CSR
);
3638 else if (reg
>= RISCV_DWARF_REGNUM_V0
&& reg
<= RISCV_DWARF_REGNUM_V31
)
3639 return RISCV_V0_REGNUM
+ (reg
- RISCV_DWARF_REGNUM_V0
);
3644 /* Implement the gcc_target_options method. We have to select the arch and abi
3645 from the feature info. We have enough feature info to select the abi, but
3646 not enough info for the arch given all of the possible architecture
3647 extensions. So choose reasonable defaults for now. */
3650 riscv_gcc_target_options (struct gdbarch
*gdbarch
)
3652 int isa_xlen
= riscv_isa_xlen (gdbarch
);
3653 int isa_flen
= riscv_isa_flen (gdbarch
);
3654 int abi_xlen
= riscv_abi_xlen (gdbarch
);
3655 int abi_flen
= riscv_abi_flen (gdbarch
);
3656 std::string target_options
;
3658 target_options
= "-march=rv";
3660 target_options
+= "64";
3662 target_options
+= "32";
3664 target_options
+= "gc";
3665 else if (isa_flen
== 4)
3666 target_options
+= "imafc";
3668 target_options
+= "imac";
3670 target_options
+= " -mabi=";
3672 target_options
+= "lp64";
3674 target_options
+= "ilp32";
3676 target_options
+= "d";
3677 else if (abi_flen
== 4)
3678 target_options
+= "f";
3680 /* The gdb loader doesn't handle link-time relaxation relocations. */
3681 target_options
+= " -mno-relax";
3683 return target_options
;
3686 /* Call back from tdesc_use_registers, called for each unknown register
3687 found in the target description.
3689 See target-description.h (typedef tdesc_unknown_register_ftype) for a
3690 discussion of the arguments and return values. */
3693 riscv_tdesc_unknown_reg (struct gdbarch
*gdbarch
, tdesc_feature
*feature
,
3694 const char *reg_name
, int possible_regnum
)
3696 /* At one point in time GDB had an incorrect default target description
3697 that duplicated the fflags, frm, and fcsr registers in both the FPU
3698 and CSR register sets.
3700 Some targets (QEMU) copied these target descriptions into their source
3701 tree, and so we're now stuck working with some versions of QEMU that
3702 declare the same registers twice.
3704 To make matters worse, if GDB tries to read or write to these
3705 registers using the register number assigned in the FPU feature set,
3706 then QEMU will fail to read the register, so we must use the register
3707 number declared in the CSR feature set.
3709 Luckily, GDB scans the FPU feature first, and then the CSR feature,
3710 which means that the CSR feature will be the one we end up using, the
3711 versions of these registers in the FPU feature will appear as unknown
3712 registers and will be passed through to this code.
3714 To prevent these duplicate registers showing up in any of the register
3715 lists, and to prevent GDB every trying to access the FPU feature copies,
3716 we spot the three problematic registers here, and record the register
3717 number that GDB has assigned them. Then in riscv_register_name we will
3718 return no name for the three duplicates, this hides the duplicates from
3720 if (strcmp (tdesc_feature_name (feature
), riscv_freg_feature
.name ()) == 0)
3722 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
3723 int *regnum_ptr
= nullptr;
3725 if (strcmp (reg_name
, "fflags") == 0)
3726 regnum_ptr
= &tdep
->duplicate_fflags_regnum
;
3727 else if (strcmp (reg_name
, "frm") == 0)
3728 regnum_ptr
= &tdep
->duplicate_frm_regnum
;
3729 else if (strcmp (reg_name
, "fcsr") == 0)
3730 regnum_ptr
= &tdep
->duplicate_fcsr_regnum
;
3732 if (regnum_ptr
!= nullptr)
3734 /* This means the register appears more than twice in the target
3735 description. Just let GDB add this as another register.
3736 We'll have duplicates in the register name list, but there's
3737 not much more we can do. */
3738 if (*regnum_ptr
!= -1)
3741 /* Record the number assigned to this register, then return the
3742 number (so it actually gets assigned to this register). */
3743 *regnum_ptr
= possible_regnum
;
3744 return possible_regnum
;
3748 /* Any unknown registers in the CSR feature are recorded within a single
3749 block so we can easily identify these registers when making choices
3750 about register groups in riscv_register_reggroup_p. */
3751 if (strcmp (tdesc_feature_name (feature
), riscv_csr_feature
.name ()) == 0)
3753 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
3754 if (tdep
->unknown_csrs_first_regnum
== -1)
3755 tdep
->unknown_csrs_first_regnum
= possible_regnum
;
3756 gdb_assert (tdep
->unknown_csrs_first_regnum
3757 + tdep
->unknown_csrs_count
== possible_regnum
);
3758 tdep
->unknown_csrs_count
++;
3759 return possible_regnum
;
3762 /* Some other unknown register. Don't assign this a number now, it will
3763 be assigned a number automatically later by the target description
3768 /* Implement the gnu_triplet_regexp method. A single compiler supports both
3769 32-bit and 64-bit code, and may be named riscv32 or riscv64 or (not
3770 recommended) riscv. */
3773 riscv_gnu_triplet_regexp (struct gdbarch
*gdbarch
)
3775 return "riscv(32|64)?";
3778 /* Initialize the current architecture based on INFO. If possible,
3779 re-use an architecture from ARCHES, which is a list of
3780 architectures already created during this debugging session.
3782 Called e.g. at program startup, when reading a core file, and when
3783 reading a binary file. */
3785 static struct gdbarch
*
3786 riscv_gdbarch_init (struct gdbarch_info info
,
3787 struct gdbarch_list
*arches
)
3789 struct gdbarch
*gdbarch
;
3790 struct riscv_gdbarch_features features
;
3791 const struct target_desc
*tdesc
= info
.target_desc
;
3793 /* Ensure we always have a target description. */
3794 if (!tdesc_has_registers (tdesc
))
3795 tdesc
= riscv_find_default_target_description (info
);
3796 gdb_assert (tdesc
!= nullptr);
3798 if (riscv_debug_gdbarch
)
3799 gdb_printf (gdb_stdlog
, "Have got a target description\n");
3801 tdesc_arch_data_up tdesc_data
= tdesc_data_alloc ();
3802 std::vector
<riscv_pending_register_alias
> pending_aliases
;
3804 bool valid_p
= (riscv_xreg_feature
.check (tdesc
, tdesc_data
.get (),
3805 &pending_aliases
, &features
)
3806 && riscv_freg_feature
.check (tdesc
, tdesc_data
.get (),
3807 &pending_aliases
, &features
)
3808 && riscv_virtual_feature
.check (tdesc
, tdesc_data
.get (),
3809 &pending_aliases
, &features
)
3810 && riscv_csr_feature
.check (tdesc
, tdesc_data
.get (),
3811 &pending_aliases
, &features
)
3812 && riscv_vector_feature
.check (tdesc
, tdesc_data
.get (),
3813 &pending_aliases
, &features
));
3816 if (riscv_debug_gdbarch
)
3817 gdb_printf (gdb_stdlog
, "Target description is not valid\n");
3821 if (tdesc_found_register (tdesc_data
.get (), RISCV_CSR_FFLAGS_REGNUM
))
3822 features
.has_fflags_reg
= true;
3823 if (tdesc_found_register (tdesc_data
.get (), RISCV_CSR_FRM_REGNUM
))
3824 features
.has_frm_reg
= true;
3825 if (tdesc_found_register (tdesc_data
.get (), RISCV_CSR_FCSR_REGNUM
))
3826 features
.has_fcsr_reg
= true;
3828 /* Have a look at what the supplied (if any) bfd object requires of the
3829 target, then check that this matches with what the target is
3831 struct riscv_gdbarch_features abi_features
3832 = riscv_features_from_bfd (info
.abfd
);
3834 /* If the ABI_FEATURES xlen is 0 then this indicates we got no useful abi
3835 features from the INFO object. In this case we just treat the
3836 hardware features as defining the abi. */
3837 if (abi_features
.xlen
== 0)
3838 abi_features
= features
;
3840 /* In theory a binary compiled for RV32 could run on an RV64 target,
3841 however, this has not been tested in GDB yet, so for now we require
3842 that the requested xlen match the targets xlen. */
3843 if (abi_features
.xlen
!= features
.xlen
)
3844 error (_("bfd requires xlen %d, but target has xlen %d"),
3845 abi_features
.xlen
, features
.xlen
);
3846 /* We do support running binaries compiled for 32-bit float on targets
3847 with 64-bit float, so we only complain if the binary requires more
3848 than the target has available. */
3849 if (abi_features
.flen
> features
.flen
)
3850 error (_("bfd requires flen %d, but target has flen %d"),
3851 abi_features
.flen
, features
.flen
);
3853 /* Find a candidate among the list of pre-declared architectures. */
3854 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
3856 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
3858 /* Check that the feature set of the ARCHES matches the feature set
3859 we are looking for. If it doesn't then we can't reuse this
3861 riscv_gdbarch_tdep
*other_tdep
3862 = gdbarch_tdep
<riscv_gdbarch_tdep
> (arches
->gdbarch
);
3864 if (other_tdep
->isa_features
!= features
3865 || other_tdep
->abi_features
!= abi_features
)
3872 return arches
->gdbarch
;
3874 /* None found, so create a new architecture from the information provided. */
3875 riscv_gdbarch_tdep
*tdep
= new riscv_gdbarch_tdep
;
3876 gdbarch
= gdbarch_alloc (&info
, tdep
);
3877 tdep
->isa_features
= features
;
3878 tdep
->abi_features
= abi_features
;
3880 /* Target data types. */
3881 set_gdbarch_short_bit (gdbarch
, 16);
3882 set_gdbarch_int_bit (gdbarch
, 32);
3883 set_gdbarch_long_bit (gdbarch
, riscv_isa_xlen (gdbarch
) * 8);
3884 set_gdbarch_long_long_bit (gdbarch
, 64);
3885 set_gdbarch_float_bit (gdbarch
, 32);
3886 set_gdbarch_double_bit (gdbarch
, 64);
3887 set_gdbarch_long_double_bit (gdbarch
, 128);
3888 set_gdbarch_long_double_format (gdbarch
, floatformats_ieee_quad
);
3889 set_gdbarch_ptr_bit (gdbarch
, riscv_isa_xlen (gdbarch
) * 8);
3890 set_gdbarch_char_signed (gdbarch
, 0);
3891 set_gdbarch_type_align (gdbarch
, riscv_type_align
);
3893 /* Information about the target architecture. */
3894 set_gdbarch_return_value (gdbarch
, riscv_return_value
);
3895 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, riscv_breakpoint_kind_from_pc
);
3896 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, riscv_sw_breakpoint_from_kind
);
3897 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
3899 /* Functions to analyze frames. */
3900 set_gdbarch_skip_prologue (gdbarch
, riscv_skip_prologue
);
3901 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
3902 set_gdbarch_frame_align (gdbarch
, riscv_frame_align
);
3904 /* Functions handling dummy frames. */
3905 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
3906 set_gdbarch_push_dummy_code (gdbarch
, riscv_push_dummy_code
);
3907 set_gdbarch_push_dummy_call (gdbarch
, riscv_push_dummy_call
);
3909 /* Frame unwinders. Use DWARF debug info if available, otherwise use our own
3911 dwarf2_append_unwinders (gdbarch
);
3912 frame_unwind_append_unwinder (gdbarch
, &riscv_frame_unwind
);
3914 /* Register architecture. */
3915 riscv_add_reggroups (gdbarch
);
3917 /* Internal <-> external register number maps. */
3918 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, riscv_dwarf_reg_to_regnum
);
3920 /* We reserve all possible register numbers for the known registers.
3921 This means the target description mechanism will add any target
3922 specific registers after this number. This helps make debugging GDB
3923 just a little easier. */
3924 set_gdbarch_num_regs (gdbarch
, RISCV_LAST_REGNUM
+ 1);
3926 /* Some specific register numbers GDB likes to know about. */
3927 set_gdbarch_sp_regnum (gdbarch
, RISCV_SP_REGNUM
);
3928 set_gdbarch_pc_regnum (gdbarch
, RISCV_PC_REGNUM
);
3930 set_gdbarch_print_registers_info (gdbarch
, riscv_print_registers_info
);
3932 set_tdesc_pseudo_register_name (gdbarch
, riscv_pseudo_register_name
);
3933 set_tdesc_pseudo_register_type (gdbarch
, riscv_pseudo_register_type
);
3934 set_tdesc_pseudo_register_reggroup_p (gdbarch
,
3935 riscv_pseudo_register_reggroup_p
);
3936 set_gdbarch_pseudo_register_read (gdbarch
, riscv_pseudo_register_read
);
3937 set_gdbarch_pseudo_register_write (gdbarch
, riscv_pseudo_register_write
);
3939 /* Finalise the target description registers. */
3940 tdesc_use_registers (gdbarch
, tdesc
, std::move (tdesc_data
),
3941 riscv_tdesc_unknown_reg
);
3943 /* Calculate the number of pseudo registers we need. The fflags and frm
3944 registers are sub-fields of the fcsr CSR register (csr3). However,
3945 these registers can also be accessed directly as separate CSR
3946 registers (fflags is csr1, and frm is csr2). And so, some targets
3947 might choose to offer direct access to all three registers in the
3948 target description, while other targets might choose to only offer
3951 As we scan the target description we spot which of fcsr, fflags, and
3952 frm are available. If fcsr is available but either of fflags and/or
3953 frm are not available, then we add pseudo-registers to provide the
3954 missing functionality.
3956 This has to be done after the call to tdesc_use_registers as we don't
3957 know the final register number until after that call, and the pseudo
3958 register numbers need to be after the physical registers. */
3959 int num_pseudo_regs
= 0;
3960 int next_pseudo_regnum
= gdbarch_num_regs (gdbarch
);
3962 if (features
.has_fflags_reg
)
3963 tdep
->fflags_regnum
= RISCV_CSR_FFLAGS_REGNUM
;
3964 else if (features
.has_fcsr_reg
)
3966 tdep
->fflags_regnum
= next_pseudo_regnum
;
3967 pending_aliases
.emplace_back ("csr1", (void *) &tdep
->fflags_regnum
);
3968 next_pseudo_regnum
++;
3972 if (features
.has_frm_reg
)
3973 tdep
->frm_regnum
= RISCV_CSR_FRM_REGNUM
;
3974 else if (features
.has_fcsr_reg
)
3976 tdep
->frm_regnum
= next_pseudo_regnum
;
3977 pending_aliases
.emplace_back ("csr2", (void *) &tdep
->frm_regnum
);
3978 next_pseudo_regnum
++;
3982 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudo_regs
);
3984 /* Override the register type callback setup by the target description
3985 mechanism. This allows us to provide special type for floating point
3987 set_gdbarch_register_type (gdbarch
, riscv_register_type
);
3989 /* Override the register name callback setup by the target description
3990 mechanism. This allows us to force our preferred names for the
3991 registers, no matter what the target description called them. */
3992 set_gdbarch_register_name (gdbarch
, riscv_register_name
);
3994 /* Tell GDB which RISC-V registers are read-only. */
3995 set_gdbarch_cannot_store_register (gdbarch
, riscv_cannot_store_register
);
3997 /* Override the register group callback setup by the target description
3998 mechanism. This allows us to force registers into the groups we
3999 want, ignoring what the target tells us. */
4000 set_gdbarch_register_reggroup_p (gdbarch
, riscv_register_reggroup_p
);
4002 /* Create register aliases for alternative register names. We only
4003 create aliases for registers which were mentioned in the target
4005 for (const auto &alias
: pending_aliases
)
4006 alias
.create (gdbarch
);
4008 /* Compile command hooks. */
4009 set_gdbarch_gcc_target_options (gdbarch
, riscv_gcc_target_options
);
4010 set_gdbarch_gnu_triplet_regexp (gdbarch
, riscv_gnu_triplet_regexp
);
4012 /* Disassembler options support. */
4013 set_gdbarch_valid_disassembler_options (gdbarch
,
4014 disassembler_options_riscv ());
4015 set_gdbarch_disassembler_options (gdbarch
, &riscv_disassembler_options
);
4017 /* Hook in OS ABI-specific overrides, if they have been registered. */
4018 gdbarch_init_osabi (info
, gdbarch
);
4020 register_riscv_ravenscar_ops (gdbarch
);
4025 /* This decodes the current instruction and determines the address of the
4026 next instruction. */
4029 riscv_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
4031 struct gdbarch
*gdbarch
= regcache
->arch ();
4032 const riscv_gdbarch_tdep
*tdep
4033 = gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
4034 struct riscv_insn insn
;
4037 insn
.decode (gdbarch
, pc
);
4038 next_pc
= pc
+ insn
.length ();
4040 if (insn
.opcode () == riscv_insn::JAL
)
4041 next_pc
= pc
+ insn
.imm_signed ();
4042 else if (insn
.opcode () == riscv_insn::JALR
)
4045 regcache
->cooked_read (insn
.rs1 (), &source
);
4046 next_pc
= (source
+ insn
.imm_signed ()) & ~(CORE_ADDR
) 0x1;
4048 else if (insn
.opcode () == riscv_insn::BEQ
)
4051 regcache
->cooked_read (insn
.rs1 (), &src1
);
4052 regcache
->cooked_read (insn
.rs2 (), &src2
);
4054 next_pc
= pc
+ insn
.imm_signed ();
4056 else if (insn
.opcode () == riscv_insn::BNE
)
4059 regcache
->cooked_read (insn
.rs1 (), &src1
);
4060 regcache
->cooked_read (insn
.rs2 (), &src2
);
4062 next_pc
= pc
+ insn
.imm_signed ();
4064 else if (insn
.opcode () == riscv_insn::BLT
)
4067 regcache
->cooked_read (insn
.rs1 (), &src1
);
4068 regcache
->cooked_read (insn
.rs2 (), &src2
);
4070 next_pc
= pc
+ insn
.imm_signed ();
4072 else if (insn
.opcode () == riscv_insn::BGE
)
4075 regcache
->cooked_read (insn
.rs1 (), &src1
);
4076 regcache
->cooked_read (insn
.rs2 (), &src2
);
4078 next_pc
= pc
+ insn
.imm_signed ();
4080 else if (insn
.opcode () == riscv_insn::BLTU
)
4082 ULONGEST src1
, src2
;
4083 regcache
->cooked_read (insn
.rs1 (), &src1
);
4084 regcache
->cooked_read (insn
.rs2 (), &src2
);
4086 next_pc
= pc
+ insn
.imm_signed ();
4088 else if (insn
.opcode () == riscv_insn::BGEU
)
4090 ULONGEST src1
, src2
;
4091 regcache
->cooked_read (insn
.rs1 (), &src1
);
4092 regcache
->cooked_read (insn
.rs2 (), &src2
);
4094 next_pc
= pc
+ insn
.imm_signed ();
4096 else if (insn
.opcode () == riscv_insn::ECALL
)
4098 if (tdep
->syscall_next_pc
!= nullptr)
4099 next_pc
= tdep
->syscall_next_pc (get_current_frame ());
4105 /* We can't put a breakpoint in the middle of a lr/sc atomic sequence, so look
4106 for the end of the sequence and put the breakpoint there. */
4109 riscv_next_pc_atomic_sequence (struct regcache
*regcache
, CORE_ADDR pc
,
4112 struct gdbarch
*gdbarch
= regcache
->arch ();
4113 struct riscv_insn insn
;
4114 CORE_ADDR cur_step_pc
= pc
;
4115 CORE_ADDR last_addr
= 0;
4117 /* First instruction has to be a load reserved. */
4118 insn
.decode (gdbarch
, cur_step_pc
);
4119 if (insn
.opcode () != riscv_insn::LR
)
4121 cur_step_pc
= cur_step_pc
+ insn
.length ();
4123 /* Next instruction should be branch to exit. */
4124 insn
.decode (gdbarch
, cur_step_pc
);
4125 if (insn
.opcode () != riscv_insn::BNE
)
4127 last_addr
= cur_step_pc
+ insn
.imm_signed ();
4128 cur_step_pc
= cur_step_pc
+ insn
.length ();
4130 /* Next instruction should be store conditional. */
4131 insn
.decode (gdbarch
, cur_step_pc
);
4132 if (insn
.opcode () != riscv_insn::SC
)
4134 cur_step_pc
= cur_step_pc
+ insn
.length ();
4136 /* Next instruction should be branch to start. */
4137 insn
.decode (gdbarch
, cur_step_pc
);
4138 if (insn
.opcode () != riscv_insn::BNE
)
4140 if (pc
!= (cur_step_pc
+ insn
.imm_signed ()))
4142 cur_step_pc
= cur_step_pc
+ insn
.length ();
4144 /* We should now be at the end of the sequence. */
4145 if (cur_step_pc
!= last_addr
)
4148 *next_pc
= cur_step_pc
;
4152 /* This is called just before we want to resume the inferior, if we want to
4153 single-step it but there is no hardware or kernel single-step support. We
4154 find the target of the coming instruction and breakpoint it. */
4156 std::vector
<CORE_ADDR
>
4157 riscv_software_single_step (struct regcache
*regcache
)
4159 CORE_ADDR pc
, next_pc
;
4161 pc
= regcache_read_pc (regcache
);
4163 if (riscv_next_pc_atomic_sequence (regcache
, pc
, &next_pc
))
4166 next_pc
= riscv_next_pc (regcache
, pc
);
4171 /* Create RISC-V specific reggroups. */
4174 riscv_init_reggroups ()
4176 csr_reggroup
= reggroup_new ("csr", USER_REGGROUP
);
4179 /* See riscv-tdep.h. */
4182 riscv_supply_regset (const struct regset
*regset
,
4183 struct regcache
*regcache
, int regnum
,
4184 const void *regs
, size_t len
)
4186 regcache
->supply_regset (regset
, regnum
, regs
, len
);
4188 if (regnum
== -1 || regnum
== RISCV_ZERO_REGNUM
)
4189 regcache
->raw_supply_zeroed (RISCV_ZERO_REGNUM
);
4191 struct gdbarch
*gdbarch
= regcache
->arch ();
4192 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
4195 || regnum
== tdep
->fflags_regnum
4196 || regnum
== tdep
->frm_regnum
)
4198 int fcsr_regnum
= RISCV_CSR_FCSR_REGNUM
;
4200 /* Ensure that FCSR has been read into REGCACHE. */
4202 regcache
->supply_regset (regset
, fcsr_regnum
, regs
, len
);
4204 /* Grab the FCSR value if it is now in the regcache. We must check
4205 the status first as, if the register was not supplied by REGSET,
4206 this call will trigger a recursive attempt to fetch the
4208 if (regcache
->get_register_status (fcsr_regnum
) == REG_VALID
)
4210 /* If we have an fcsr register then we should have fflags and frm
4211 too, either provided by the target, or provided as a pseudo
4213 gdb_assert (tdep
->fflags_regnum
>= 0);
4214 gdb_assert (tdep
->frm_regnum
>= 0);
4217 regcache
->raw_read (fcsr_regnum
, &fcsr_val
);
4219 /* Extract the fflags and frm values. */
4220 ULONGEST fflags_val
= fcsr_val
& 0x1f;
4221 ULONGEST frm_val
= (fcsr_val
>> 5) & 0x7;
4223 /* And supply these if needed. We can only supply real
4224 registers, so don't try to supply fflags or frm if they are
4225 implemented as pseudo-registers. */
4226 if ((regnum
== -1 || regnum
== tdep
->fflags_regnum
)
4227 && tdep
->fflags_regnum
< gdbarch_num_regs (gdbarch
))
4228 regcache
->raw_supply_integer (tdep
->fflags_regnum
,
4229 (gdb_byte
*) &fflags_val
,
4230 sizeof (fflags_val
),
4231 /* is_signed */ false);
4233 if ((regnum
== -1 || regnum
== tdep
->frm_regnum
)
4234 && tdep
->frm_regnum
< gdbarch_num_regs (gdbarch
))
4235 regcache
->raw_supply_integer (tdep
->frm_regnum
,
4236 (gdb_byte
*)&frm_val
,
4237 sizeof (fflags_val
),
4238 /* is_signed */ false);
4243 void _initialize_riscv_tdep ();
4245 _initialize_riscv_tdep ()
4247 riscv_init_reggroups ();
4249 gdbarch_register (bfd_arch_riscv
, riscv_gdbarch_init
, NULL
);
4251 /* Add root prefix command for all "set debug riscv" and "show debug
4253 add_setshow_prefix_cmd ("riscv", no_class
,
4254 _("RISC-V specific debug commands."),
4255 _("RISC-V specific debug commands."),
4256 &setdebugriscvcmdlist
, &showdebugriscvcmdlist
,
4257 &setdebuglist
, &showdebuglist
);
4259 add_setshow_zuinteger_cmd ("breakpoints", class_maintenance
,
4260 &riscv_debug_breakpoints
, _("\
4261 Set riscv breakpoint debugging."), _("\
4262 Show riscv breakpoint debugging."), _("\
4263 When non-zero, print debugging information for the riscv specific parts\n\
4264 of the breakpoint mechanism."),
4266 show_riscv_debug_variable
,
4267 &setdebugriscvcmdlist
, &showdebugriscvcmdlist
);
4269 add_setshow_zuinteger_cmd ("infcall", class_maintenance
,
4270 &riscv_debug_infcall
, _("\
4271 Set riscv inferior call debugging."), _("\
4272 Show riscv inferior call debugging."), _("\
4273 When non-zero, print debugging information for the riscv specific parts\n\
4274 of the inferior call mechanism."),
4276 show_riscv_debug_variable
,
4277 &setdebugriscvcmdlist
, &showdebugriscvcmdlist
);
4279 add_setshow_zuinteger_cmd ("unwinder", class_maintenance
,
4280 &riscv_debug_unwinder
, _("\
4281 Set riscv stack unwinding debugging."), _("\
4282 Show riscv stack unwinding debugging."), _("\
4283 When non-zero, print debugging information for the riscv specific parts\n\
4284 of the stack unwinding mechanism."),
4286 show_riscv_debug_variable
,
4287 &setdebugriscvcmdlist
, &showdebugriscvcmdlist
);
4289 add_setshow_zuinteger_cmd ("gdbarch", class_maintenance
,
4290 &riscv_debug_gdbarch
, _("\
4291 Set riscv gdbarch initialisation debugging."), _("\
4292 Show riscv gdbarch initialisation debugging."), _("\
4293 When non-zero, print debugging information for the riscv gdbarch\n\
4294 initialisation process."),
4296 show_riscv_debug_variable
,
4297 &setdebugriscvcmdlist
, &showdebugriscvcmdlist
);
4299 /* Add root prefix command for all "set riscv" and "show riscv" commands. */
4300 add_setshow_prefix_cmd ("riscv", no_class
,
4301 _("RISC-V specific commands."),
4302 _("RISC-V specific commands."),
4303 &setriscvcmdlist
, &showriscvcmdlist
,
4304 &setlist
, &showlist
);
4307 use_compressed_breakpoints
= AUTO_BOOLEAN_AUTO
;
4308 add_setshow_auto_boolean_cmd ("use-compressed-breakpoints", no_class
,
4309 &use_compressed_breakpoints
,
4311 Set debugger's use of compressed breakpoints."), _(" \
4312 Show debugger's use of compressed breakpoints."), _("\
4313 Debugging compressed code requires compressed breakpoints to be used. If\n\
4314 left to 'auto' then gdb will use them if the existing instruction is a\n\
4315 compressed instruction. If that doesn't give the correct behavior, then\n\
4316 this option can be used."),
4318 show_use_compressed_breakpoints
,