1 /* Target-dependent code for the RISC-V architecture, for GDB.
3 Copyright (C) 2018-2022 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
32 #include "arch-utils.h"
35 #include "riscv-tdep.h"
37 #include "reggroups.h"
38 #include "opcode/riscv.h"
39 #include "elf/riscv.h"
43 #include "frame-unwind.h"
44 #include "frame-base.h"
45 #include "trad-frame.h"
47 #include "floatformat.h"
49 #include "target-descriptions.h"
50 #include "dwarf2/frame.h"
51 #include "user-regs.h"
53 #include "gdbsupport/common-defs.h"
54 #include "opcode/riscv-opc.h"
55 #include "cli/cli-decode.h"
56 #include "observable.h"
57 #include "prologue-value.h"
58 #include "arch/riscv.h"
59 #include "riscv-ravenscar-thread.h"
61 /* The stack must be 16-byte aligned. */
62 #define SP_ALIGNMENT 16
64 /* The biggest alignment that the target supports. */
65 #define BIGGEST_ALIGNMENT 16
67 /* Define a series of is_XXX_insn functions to check if the value INSN
68 is an instance of instruction XXX. */
69 #define DECLARE_INSN(INSN_NAME, INSN_MATCH, INSN_MASK) \
70 static inline bool is_ ## INSN_NAME ## _insn (long insn) \
72 return (insn & INSN_MASK) == INSN_MATCH; \
74 #include "opcode/riscv-opc.h"
77 /* When this is set to non-zero debugging information about breakpoint
78 kinds will be printed. */
80 static unsigned int riscv_debug_breakpoints
= 0;
82 /* When this is set to non-zero debugging information about inferior calls
85 static unsigned int riscv_debug_infcall
= 0;
87 /* When this is set to non-zero debugging information about stack unwinding
90 static unsigned int riscv_debug_unwinder
= 0;
92 /* When this is set to non-zero debugging information about gdbarch
93 initialisation will be printed. */
95 static unsigned int riscv_debug_gdbarch
= 0;
97 /* The names of the RISC-V target description features. */
98 const char *riscv_feature_name_csr
= "org.gnu.gdb.riscv.csr";
99 static const char *riscv_feature_name_cpu
= "org.gnu.gdb.riscv.cpu";
100 static const char *riscv_feature_name_fpu
= "org.gnu.gdb.riscv.fpu";
101 static const char *riscv_feature_name_virtual
= "org.gnu.gdb.riscv.virtual";
102 static const char *riscv_feature_name_vector
= "org.gnu.gdb.riscv.vector";
104 /* The current set of options to be passed to the disassembler. */
105 static char *riscv_disassembler_options
;
107 /* Cached information about a frame. */
109 struct riscv_unwind_cache
111 /* The register from which we can calculate the frame base. This is
112 usually $sp or $fp. */
115 /* The offset from the current value in register FRAME_BASE_REG to the
116 actual frame base address. */
117 int frame_base_offset
;
119 /* Information about previous register values. */
120 trad_frame_saved_reg
*regs
;
122 /* The id for this frame. */
123 struct frame_id this_id
;
125 /* The base (stack) address for this frame. This is the stack pointer
126 value on entry to this frame before any adjustments are made. */
127 CORE_ADDR frame_base
;
130 /* RISC-V specific register group for CSRs. */
132 static const reggroup
*csr_reggroup
= nullptr;
134 /* Callback function for user_reg_add. */
136 static struct value
*
137 value_of_riscv_user_reg (struct frame_info
*frame
, const void *baton
)
139 const int *reg_p
= (const int *) baton
;
140 return value_of_register (*reg_p
, frame
);
143 /* Information about a register alias that needs to be set up for this
144 target. These are collected when the target's XML description is
145 analysed, and then processed later, once the gdbarch has been created. */
147 class riscv_pending_register_alias
152 riscv_pending_register_alias (const char *name
, const void *baton
)
157 /* Convert this into a user register for GDBARCH. */
159 void create (struct gdbarch
*gdbarch
) const
161 user_reg_add (gdbarch
, m_name
, value_of_riscv_user_reg
, m_baton
);
165 /* The name for this alias. */
168 /* The baton value for passing to user_reg_add. This must point to some
169 data that will live for at least as long as the gdbarch object to
170 which the user register is attached. */
174 /* A set of registers that we expect to find in a tdesc_feature. These
175 are use in RISCV_GDBARCH_INIT when processing the target description. */
177 struct riscv_register_feature
179 explicit riscv_register_feature (const char *feature_name
)
180 : m_feature_name (feature_name
)
183 riscv_register_feature () = delete;
184 DISABLE_COPY_AND_ASSIGN (riscv_register_feature
);
186 /* Information for a single register. */
189 /* The GDB register number for this register. */
192 /* List of names for this register. The first name in this list is the
193 preferred name, the name GDB should use when describing this
195 std::vector
<const char *> names
;
197 /* Look in FEATURE for a register with a name from this classes names
198 list. If the register is found then register its number with
199 TDESC_DATA and add all its aliases to the ALIASES list.
200 PREFER_FIRST_NAME_P is used when deciding which aliases to create. */
201 bool check (struct tdesc_arch_data
*tdesc_data
,
202 const struct tdesc_feature
*feature
,
203 bool prefer_first_name_p
,
204 std::vector
<riscv_pending_register_alias
> *aliases
) const;
207 /* Return the name of this feature. */
208 const char *name () const
209 { return m_feature_name
; }
213 /* Return a target description feature extracted from TDESC for this
214 register feature. Will return nullptr if there is no feature in TDESC
215 with the name M_FEATURE_NAME. */
216 const struct tdesc_feature
*tdesc_feature (const struct target_desc
*tdesc
) const
218 return tdesc_find_feature (tdesc
, name ());
221 /* List of all the registers that we expect that we might find in this
223 std::vector
<struct register_info
> m_registers
;
227 /* The name for this feature. This is the name used to find this feature
228 within the target description. */
229 const char *m_feature_name
;
232 /* See description in the class declaration above. */
235 riscv_register_feature::register_info::check
236 (struct tdesc_arch_data
*tdesc_data
,
237 const struct tdesc_feature
*feature
,
238 bool prefer_first_name_p
,
239 std::vector
<riscv_pending_register_alias
> *aliases
) const
241 for (const char *name
: this->names
)
243 bool found
= tdesc_numbered_register (feature
, tdesc_data
,
247 /* We know that the target description mentions this
248 register. In RISCV_REGISTER_NAME we ensure that GDB
249 always uses the first name for each register, so here we
250 add aliases for all of the remaining names. */
251 int start_index
= prefer_first_name_p
? 1 : 0;
252 for (int i
= start_index
; i
< this->names
.size (); ++i
)
254 const char *alias
= this->names
[i
];
255 if (alias
== name
&& !prefer_first_name_p
)
257 aliases
->emplace_back (alias
, (void *) &this->regnum
);
265 /* Class representing the x-registers feature set. */
267 struct riscv_xreg_feature
: public riscv_register_feature
269 riscv_xreg_feature ()
270 : riscv_register_feature (riscv_feature_name_cpu
)
273 { RISCV_ZERO_REGNUM
+ 0, { "zero", "x0" } },
274 { RISCV_ZERO_REGNUM
+ 1, { "ra", "x1" } },
275 { RISCV_ZERO_REGNUM
+ 2, { "sp", "x2" } },
276 { RISCV_ZERO_REGNUM
+ 3, { "gp", "x3" } },
277 { RISCV_ZERO_REGNUM
+ 4, { "tp", "x4" } },
278 { RISCV_ZERO_REGNUM
+ 5, { "t0", "x5" } },
279 { RISCV_ZERO_REGNUM
+ 6, { "t1", "x6" } },
280 { RISCV_ZERO_REGNUM
+ 7, { "t2", "x7" } },
281 { RISCV_ZERO_REGNUM
+ 8, { "fp", "x8", "s0" } },
282 { RISCV_ZERO_REGNUM
+ 9, { "s1", "x9" } },
283 { RISCV_ZERO_REGNUM
+ 10, { "a0", "x10" } },
284 { RISCV_ZERO_REGNUM
+ 11, { "a1", "x11" } },
285 { RISCV_ZERO_REGNUM
+ 12, { "a2", "x12" } },
286 { RISCV_ZERO_REGNUM
+ 13, { "a3", "x13" } },
287 { RISCV_ZERO_REGNUM
+ 14, { "a4", "x14" } },
288 { RISCV_ZERO_REGNUM
+ 15, { "a5", "x15" } },
289 { RISCV_ZERO_REGNUM
+ 16, { "a6", "x16" } },
290 { RISCV_ZERO_REGNUM
+ 17, { "a7", "x17" } },
291 { RISCV_ZERO_REGNUM
+ 18, { "s2", "x18" } },
292 { RISCV_ZERO_REGNUM
+ 19, { "s3", "x19" } },
293 { RISCV_ZERO_REGNUM
+ 20, { "s4", "x20" } },
294 { RISCV_ZERO_REGNUM
+ 21, { "s5", "x21" } },
295 { RISCV_ZERO_REGNUM
+ 22, { "s6", "x22" } },
296 { RISCV_ZERO_REGNUM
+ 23, { "s7", "x23" } },
297 { RISCV_ZERO_REGNUM
+ 24, { "s8", "x24" } },
298 { RISCV_ZERO_REGNUM
+ 25, { "s9", "x25" } },
299 { RISCV_ZERO_REGNUM
+ 26, { "s10", "x26" } },
300 { RISCV_ZERO_REGNUM
+ 27, { "s11", "x27" } },
301 { RISCV_ZERO_REGNUM
+ 28, { "t3", "x28" } },
302 { RISCV_ZERO_REGNUM
+ 29, { "t4", "x29" } },
303 { RISCV_ZERO_REGNUM
+ 30, { "t5", "x30" } },
304 { RISCV_ZERO_REGNUM
+ 31, { "t6", "x31" } },
305 { RISCV_ZERO_REGNUM
+ 32, { "pc" } }
309 /* Return the preferred name for the register with gdb register number
310 REGNUM, which must be in the inclusive range RISCV_ZERO_REGNUM to
312 const char *register_name (int regnum
) const
314 gdb_assert (regnum
>= RISCV_ZERO_REGNUM
&& regnum
<= m_registers
.size ());
315 return m_registers
[regnum
].names
[0];
318 /* Check this feature within TDESC, record the registers from this
319 feature into TDESC_DATA and update ALIASES and FEATURES. */
320 bool check (const struct target_desc
*tdesc
,
321 struct tdesc_arch_data
*tdesc_data
,
322 std::vector
<riscv_pending_register_alias
> *aliases
,
323 struct riscv_gdbarch_features
*features
) const
325 const struct tdesc_feature
*feature_cpu
= tdesc_feature (tdesc
);
327 if (feature_cpu
== nullptr)
330 bool seen_an_optional_reg_p
= false;
331 for (const auto ®
: m_registers
)
333 bool found
= reg
.check (tdesc_data
, feature_cpu
, true, aliases
);
335 bool is_optional_reg_p
= (reg
.regnum
>= RISCV_ZERO_REGNUM
+ 16
336 && reg
.regnum
< RISCV_ZERO_REGNUM
+ 32);
338 if (!found
&& (!is_optional_reg_p
|| seen_an_optional_reg_p
))
340 else if (found
&& is_optional_reg_p
)
341 seen_an_optional_reg_p
= true;
344 /* Check that all of the core cpu registers have the same bitsize. */
345 int xlen_bitsize
= tdesc_register_bitsize (feature_cpu
, "pc");
348 for (auto &tdesc_reg
: feature_cpu
->registers
)
349 valid_p
&= (tdesc_reg
->bitsize
== xlen_bitsize
);
351 features
->xlen
= (xlen_bitsize
/ 8);
352 features
->embedded
= !seen_an_optional_reg_p
;
358 /* An instance of the x-register feature set. */
360 static const struct riscv_xreg_feature riscv_xreg_feature
;
362 /* Class representing the f-registers feature set. */
364 struct riscv_freg_feature
: public riscv_register_feature
366 riscv_freg_feature ()
367 : riscv_register_feature (riscv_feature_name_fpu
)
370 { RISCV_FIRST_FP_REGNUM
+ 0, { "ft0", "f0" } },
371 { RISCV_FIRST_FP_REGNUM
+ 1, { "ft1", "f1" } },
372 { RISCV_FIRST_FP_REGNUM
+ 2, { "ft2", "f2" } },
373 { RISCV_FIRST_FP_REGNUM
+ 3, { "ft3", "f3" } },
374 { RISCV_FIRST_FP_REGNUM
+ 4, { "ft4", "f4" } },
375 { RISCV_FIRST_FP_REGNUM
+ 5, { "ft5", "f5" } },
376 { RISCV_FIRST_FP_REGNUM
+ 6, { "ft6", "f6" } },
377 { RISCV_FIRST_FP_REGNUM
+ 7, { "ft7", "f7" } },
378 { RISCV_FIRST_FP_REGNUM
+ 8, { "fs0", "f8" } },
379 { RISCV_FIRST_FP_REGNUM
+ 9, { "fs1", "f9" } },
380 { RISCV_FIRST_FP_REGNUM
+ 10, { "fa0", "f10" } },
381 { RISCV_FIRST_FP_REGNUM
+ 11, { "fa1", "f11" } },
382 { RISCV_FIRST_FP_REGNUM
+ 12, { "fa2", "f12" } },
383 { RISCV_FIRST_FP_REGNUM
+ 13, { "fa3", "f13" } },
384 { RISCV_FIRST_FP_REGNUM
+ 14, { "fa4", "f14" } },
385 { RISCV_FIRST_FP_REGNUM
+ 15, { "fa5", "f15" } },
386 { RISCV_FIRST_FP_REGNUM
+ 16, { "fa6", "f16" } },
387 { RISCV_FIRST_FP_REGNUM
+ 17, { "fa7", "f17" } },
388 { RISCV_FIRST_FP_REGNUM
+ 18, { "fs2", "f18" } },
389 { RISCV_FIRST_FP_REGNUM
+ 19, { "fs3", "f19" } },
390 { RISCV_FIRST_FP_REGNUM
+ 20, { "fs4", "f20" } },
391 { RISCV_FIRST_FP_REGNUM
+ 21, { "fs5", "f21" } },
392 { RISCV_FIRST_FP_REGNUM
+ 22, { "fs6", "f22" } },
393 { RISCV_FIRST_FP_REGNUM
+ 23, { "fs7", "f23" } },
394 { RISCV_FIRST_FP_REGNUM
+ 24, { "fs8", "f24" } },
395 { RISCV_FIRST_FP_REGNUM
+ 25, { "fs9", "f25" } },
396 { RISCV_FIRST_FP_REGNUM
+ 26, { "fs10", "f26" } },
397 { RISCV_FIRST_FP_REGNUM
+ 27, { "fs11", "f27" } },
398 { RISCV_FIRST_FP_REGNUM
+ 28, { "ft8", "f28" } },
399 { RISCV_FIRST_FP_REGNUM
+ 29, { "ft9", "f29" } },
400 { RISCV_FIRST_FP_REGNUM
+ 30, { "ft10", "f30" } },
401 { RISCV_FIRST_FP_REGNUM
+ 31, { "ft11", "f31" } },
402 { RISCV_CSR_FFLAGS_REGNUM
, { "fflags", "csr1" } },
403 { RISCV_CSR_FRM_REGNUM
, { "frm", "csr2" } },
404 { RISCV_CSR_FCSR_REGNUM
, { "fcsr", "csr3" } },
408 /* Return the preferred name for the register with gdb register number
409 REGNUM, which must be in the inclusive range RISCV_FIRST_FP_REGNUM to
410 RISCV_LAST_FP_REGNUM. */
411 const char *register_name (int regnum
) const
413 gdb_static_assert (RISCV_LAST_FP_REGNUM
== RISCV_FIRST_FP_REGNUM
+ 31);
414 gdb_assert (regnum
>= RISCV_FIRST_FP_REGNUM
415 && regnum
<= RISCV_LAST_FP_REGNUM
);
416 regnum
-= RISCV_FIRST_FP_REGNUM
;
417 return m_registers
[regnum
].names
[0];
420 /* Check this feature within TDESC, record the registers from this
421 feature into TDESC_DATA and update ALIASES and FEATURES. */
422 bool check (const struct target_desc
*tdesc
,
423 struct tdesc_arch_data
*tdesc_data
,
424 std::vector
<riscv_pending_register_alias
> *aliases
,
425 struct riscv_gdbarch_features
*features
) const
427 const struct tdesc_feature
*feature_fpu
= tdesc_feature (tdesc
);
429 /* It's fine if this feature is missing. Update the architecture
430 feature set and return. */
431 if (feature_fpu
== nullptr)
437 /* Check all of the floating pointer registers are present. We also
438 check that the floating point CSRs are present too, though if these
439 are missing this is not fatal. */
440 for (const auto ®
: m_registers
)
442 bool found
= reg
.check (tdesc_data
, feature_fpu
, true, aliases
);
444 bool is_ctrl_reg_p
= reg
.regnum
> RISCV_LAST_FP_REGNUM
;
446 if (!found
&& !is_ctrl_reg_p
)
450 /* Look through all of the floating point registers (not the FP CSRs
451 though), and check they all have the same bitsize. Use this bitsize
452 to update the feature set for this gdbarch. */
454 for (const auto ®
: m_registers
)
456 /* Stop once we get to the CSRs which are at the end of the
458 if (reg
.regnum
> RISCV_LAST_FP_REGNUM
)
461 int reg_bitsize
= -1;
462 for (const char *name
: reg
.names
)
464 if (tdesc_unnumbered_register (feature_fpu
, name
))
466 reg_bitsize
= tdesc_register_bitsize (feature_fpu
, name
);
470 gdb_assert (reg_bitsize
!= -1);
471 if (fp_bitsize
== -1)
472 fp_bitsize
= reg_bitsize
;
473 else if (fp_bitsize
!= reg_bitsize
)
477 features
->flen
= (fp_bitsize
/ 8);
482 /* An instance of the f-register feature set. */
484 static const struct riscv_freg_feature riscv_freg_feature
;
486 /* Class representing the virtual registers. These are not physical
487 registers on the hardware, but might be available from the target.
488 These are not pseudo registers, reading these really does result in a
489 register read from the target, it is just that there might not be a
490 physical register backing the result. */
492 struct riscv_virtual_feature
: public riscv_register_feature
494 riscv_virtual_feature ()
495 : riscv_register_feature (riscv_feature_name_virtual
)
498 { RISCV_PRIV_REGNUM
, { "priv" } }
502 bool check (const struct target_desc
*tdesc
,
503 struct tdesc_arch_data
*tdesc_data
,
504 std::vector
<riscv_pending_register_alias
> *aliases
,
505 struct riscv_gdbarch_features
*features
) const
507 const struct tdesc_feature
*feature_virtual
= tdesc_feature (tdesc
);
509 /* It's fine if this feature is missing. */
510 if (feature_virtual
== nullptr)
513 /* We don't check the return value from the call to check here, all the
514 registers in this feature are optional. */
515 for (const auto ®
: m_registers
)
516 reg
.check (tdesc_data
, feature_virtual
, true, aliases
);
522 /* An instance of the virtual register feature. */
524 static const struct riscv_virtual_feature riscv_virtual_feature
;
526 /* Class representing the CSR feature. */
528 struct riscv_csr_feature
: public riscv_register_feature
531 : riscv_register_feature (riscv_feature_name_csr
)
534 #define DECLARE_CSR(NAME,VALUE,CLASS,DEFINE_VER,ABORT_VER) \
535 { RISCV_ ## VALUE ## _REGNUM, { # NAME } },
536 #include "opcode/riscv-opc.h"
539 riscv_create_csr_aliases ();
542 bool check (const struct target_desc
*tdesc
,
543 struct tdesc_arch_data
*tdesc_data
,
544 std::vector
<riscv_pending_register_alias
> *aliases
,
545 struct riscv_gdbarch_features
*features
) const
547 const struct tdesc_feature
*feature_csr
= tdesc_feature (tdesc
);
549 /* It's fine if this feature is missing. */
550 if (feature_csr
== nullptr)
553 /* We don't check the return value from the call to check here, all the
554 registers in this feature are optional. */
555 for (const auto ®
: m_registers
)
556 reg
.check (tdesc_data
, feature_csr
, true, aliases
);
563 /* Complete RISCV_CSR_FEATURE, building the CSR alias names and adding them
564 to the name list for each register. */
567 riscv_create_csr_aliases ()
569 for (auto ®
: m_registers
)
571 int csr_num
= reg
.regnum
- RISCV_FIRST_CSR_REGNUM
;
572 gdb::unique_xmalloc_ptr
<char> alias
= xstrprintf ("csr%d", csr_num
);
573 reg
.names
.push_back (alias
.release ());
578 /* An instance of the csr register feature. */
580 static const struct riscv_csr_feature riscv_csr_feature
;
582 /* Class representing the v-registers feature set. */
584 struct riscv_vector_feature
: public riscv_register_feature
586 riscv_vector_feature ()
587 : riscv_register_feature (riscv_feature_name_vector
)
590 { RISCV_V0_REGNUM
+ 0, { "v0" } },
591 { RISCV_V0_REGNUM
+ 1, { "v1" } },
592 { RISCV_V0_REGNUM
+ 2, { "v2" } },
593 { RISCV_V0_REGNUM
+ 3, { "v3" } },
594 { RISCV_V0_REGNUM
+ 4, { "v4" } },
595 { RISCV_V0_REGNUM
+ 5, { "v5" } },
596 { RISCV_V0_REGNUM
+ 6, { "v6" } },
597 { RISCV_V0_REGNUM
+ 7, { "v7" } },
598 { RISCV_V0_REGNUM
+ 8, { "v8" } },
599 { RISCV_V0_REGNUM
+ 9, { "v9" } },
600 { RISCV_V0_REGNUM
+ 10, { "v10" } },
601 { RISCV_V0_REGNUM
+ 11, { "v11" } },
602 { RISCV_V0_REGNUM
+ 12, { "v12" } },
603 { RISCV_V0_REGNUM
+ 13, { "v13" } },
604 { RISCV_V0_REGNUM
+ 14, { "v14" } },
605 { RISCV_V0_REGNUM
+ 15, { "v15" } },
606 { RISCV_V0_REGNUM
+ 16, { "v16" } },
607 { RISCV_V0_REGNUM
+ 17, { "v17" } },
608 { RISCV_V0_REGNUM
+ 18, { "v18" } },
609 { RISCV_V0_REGNUM
+ 19, { "v19" } },
610 { RISCV_V0_REGNUM
+ 20, { "v20" } },
611 { RISCV_V0_REGNUM
+ 21, { "v21" } },
612 { RISCV_V0_REGNUM
+ 22, { "v22" } },
613 { RISCV_V0_REGNUM
+ 23, { "v23" } },
614 { RISCV_V0_REGNUM
+ 24, { "v24" } },
615 { RISCV_V0_REGNUM
+ 25, { "v25" } },
616 { RISCV_V0_REGNUM
+ 26, { "v26" } },
617 { RISCV_V0_REGNUM
+ 27, { "v27" } },
618 { RISCV_V0_REGNUM
+ 28, { "v28" } },
619 { RISCV_V0_REGNUM
+ 29, { "v29" } },
620 { RISCV_V0_REGNUM
+ 30, { "v30" } },
621 { RISCV_V0_REGNUM
+ 31, { "v31" } },
625 /* Return the preferred name for the register with gdb register number
626 REGNUM, which must be in the inclusive range RISCV_V0_REGNUM to
627 RISCV_V0_REGNUM + 31. */
628 const char *register_name (int regnum
) const
630 gdb_assert (regnum
>= RISCV_V0_REGNUM
631 && regnum
<= RISCV_V0_REGNUM
+ 31);
632 regnum
-= RISCV_V0_REGNUM
;
633 return m_registers
[regnum
].names
[0];
636 /* Check this feature within TDESC, record the registers from this
637 feature into TDESC_DATA and update ALIASES and FEATURES. */
638 bool check (const struct target_desc
*tdesc
,
639 struct tdesc_arch_data
*tdesc_data
,
640 std::vector
<riscv_pending_register_alias
> *aliases
,
641 struct riscv_gdbarch_features
*features
) const
643 const struct tdesc_feature
*feature_vector
= tdesc_feature (tdesc
);
645 /* It's fine if this feature is missing. Update the architecture
646 feature set and return. */
647 if (feature_vector
== nullptr)
653 /* Check all of the vector registers are present. */
654 for (const auto ®
: m_registers
)
656 if (!reg
.check (tdesc_data
, feature_vector
, true, aliases
))
660 /* Look through all of the vector registers and check they all have the
661 same bitsize. Use this bitsize to update the feature set for this
663 int vector_bitsize
= -1;
664 for (const auto ®
: m_registers
)
666 int reg_bitsize
= -1;
667 for (const char *name
: reg
.names
)
669 if (tdesc_unnumbered_register (feature_vector
, name
))
671 reg_bitsize
= tdesc_register_bitsize (feature_vector
, name
);
675 gdb_assert (reg_bitsize
!= -1);
676 if (vector_bitsize
== -1)
677 vector_bitsize
= reg_bitsize
;
678 else if (vector_bitsize
!= reg_bitsize
)
682 features
->vlen
= (vector_bitsize
/ 8);
687 /* An instance of the v-register feature set. */
689 static const struct riscv_vector_feature riscv_vector_feature
;
691 /* Controls whether we place compressed breakpoints or not. When in auto
692 mode GDB tries to determine if the target supports compressed
693 breakpoints, and uses them if it does. */
695 static enum auto_boolean use_compressed_breakpoints
;
697 /* The show callback for 'show riscv use-compressed-breakpoints'. */
700 show_use_compressed_breakpoints (struct ui_file
*file
, int from_tty
,
701 struct cmd_list_element
*c
,
705 _("Debugger's use of compressed breakpoints is set "
709 /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
711 static struct cmd_list_element
*setriscvcmdlist
= NULL
;
712 static struct cmd_list_element
*showriscvcmdlist
= NULL
;
714 /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
716 static struct cmd_list_element
*setdebugriscvcmdlist
= NULL
;
717 static struct cmd_list_element
*showdebugriscvcmdlist
= NULL
;
719 /* The show callback for all 'show debug riscv VARNAME' variables. */
722 show_riscv_debug_variable (struct ui_file
*file
, int from_tty
,
723 struct cmd_list_element
*c
,
727 _("RiscV debug variable `%s' is set to: %s\n"),
731 /* See riscv-tdep.h. */
734 riscv_isa_xlen (struct gdbarch
*gdbarch
)
736 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
737 return tdep
->isa_features
.xlen
;
740 /* See riscv-tdep.h. */
743 riscv_abi_xlen (struct gdbarch
*gdbarch
)
745 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
746 return tdep
->abi_features
.xlen
;
749 /* See riscv-tdep.h. */
752 riscv_isa_flen (struct gdbarch
*gdbarch
)
754 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
755 return tdep
->isa_features
.flen
;
758 /* See riscv-tdep.h. */
761 riscv_abi_flen (struct gdbarch
*gdbarch
)
763 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
764 return tdep
->abi_features
.flen
;
767 /* See riscv-tdep.h. */
770 riscv_abi_embedded (struct gdbarch
*gdbarch
)
772 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
773 return tdep
->abi_features
.embedded
;
776 /* Return true if the target for GDBARCH has floating point hardware. */
779 riscv_has_fp_regs (struct gdbarch
*gdbarch
)
781 return (riscv_isa_flen (gdbarch
) > 0);
784 /* Return true if GDBARCH is using any of the floating point hardware ABIs. */
787 riscv_has_fp_abi (struct gdbarch
*gdbarch
)
789 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
790 return tdep
->abi_features
.flen
> 0;
793 /* Return true if REGNO is a floating pointer register. */
796 riscv_is_fp_regno_p (int regno
)
798 return (regno
>= RISCV_FIRST_FP_REGNUM
799 && regno
<= RISCV_LAST_FP_REGNUM
);
802 /* Implement the breakpoint_kind_from_pc gdbarch method. */
805 riscv_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
807 if (use_compressed_breakpoints
== AUTO_BOOLEAN_AUTO
)
809 bool unaligned_p
= false;
812 /* Some targets don't support unaligned reads. The address can only
813 be unaligned if the C extension is supported. So it is safe to
814 use a compressed breakpoint in this case. */
819 /* Read the opcode byte to determine the instruction length. If
820 the read fails this may be because we tried to set the
821 breakpoint at an invalid address, in this case we provide a
822 fake result which will give a breakpoint length of 4.
823 Hopefully when we try to actually insert the breakpoint we
824 will see a failure then too which will be reported to the
826 if (target_read_code (*pcptr
, buf
, 1) == -1)
830 if (riscv_debug_breakpoints
)
832 const char *bp
= (unaligned_p
|| riscv_insn_length (buf
[0]) == 2
833 ? "C.EBREAK" : "EBREAK");
835 gdb_printf (gdb_stdlog
, "Using %s for breakpoint at %s ",
836 bp
, paddress (gdbarch
, *pcptr
));
838 gdb_printf (gdb_stdlog
, "(unaligned address)\n");
840 gdb_printf (gdb_stdlog
, "(instruction length %d)\n",
841 riscv_insn_length (buf
[0]));
843 if (unaligned_p
|| riscv_insn_length (buf
[0]) == 2)
848 else if (use_compressed_breakpoints
== AUTO_BOOLEAN_TRUE
)
854 /* Implement the sw_breakpoint_from_kind gdbarch method. */
856 static const gdb_byte
*
857 riscv_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
859 static const gdb_byte ebreak
[] = { 0x73, 0x00, 0x10, 0x00, };
860 static const gdb_byte c_ebreak
[] = { 0x02, 0x90 };
870 gdb_assert_not_reached ("unhandled breakpoint kind");
874 /* Implement the register_name gdbarch method. This is used instead of
875 the function supplied by calling TDESC_USE_REGISTERS so that we can
876 ensure the preferred names are offered for x-regs and f-regs. */
879 riscv_register_name (struct gdbarch
*gdbarch
, int regnum
)
881 /* Lookup the name through the target description. If we get back NULL
882 then this is an unknown register. If we do get a name back then we
883 look up the registers preferred name below. */
884 const char *name
= tdesc_register_name (gdbarch
, regnum
);
885 if (name
== NULL
|| name
[0] == '\0')
888 /* We want GDB to use the ABI names for registers even if the target
889 gives us a target description with the architectural name. For
890 example we want to see 'ra' instead of 'x1' whatever the target
891 description called it. */
892 if (regnum
>= RISCV_ZERO_REGNUM
&& regnum
< RISCV_FIRST_FP_REGNUM
)
893 return riscv_xreg_feature
.register_name (regnum
);
895 /* Like with the x-regs we prefer the abi names for the floating point
897 if (regnum
>= RISCV_FIRST_FP_REGNUM
&& regnum
<= RISCV_LAST_FP_REGNUM
)
899 if (riscv_has_fp_regs (gdbarch
))
900 return riscv_freg_feature
.register_name (regnum
);
905 /* Some targets (QEMU) are reporting these three registers twice, once
906 in the FPU feature, and once in the CSR feature. Both of these read
907 the same underlying state inside the target, but naming the register
908 twice in the target description results in GDB having two registers
909 with the same name, only one of which can ever be accessed, but both
910 will show up in 'info register all'. Unless, we identify the
911 duplicate copies of these registers (in riscv_tdesc_unknown_reg) and
912 then hide the registers here by giving them no name. */
913 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
914 if (tdep
->duplicate_fflags_regnum
== regnum
)
916 if (tdep
->duplicate_frm_regnum
== regnum
)
918 if (tdep
->duplicate_fcsr_regnum
== regnum
)
921 /* The remaining registers are different. For all other registers on the
922 machine we prefer to see the names that the target description
923 provides. This is particularly important for CSRs which might be
924 renamed over time. If GDB keeps track of the "latest" name, but a
925 particular target provides an older name then we don't want to force
926 users to see the newer name in register output.
928 The other case that reaches here are any registers that the target
929 provided that GDB is completely unaware of. For these we have no
930 choice but to accept the target description name.
932 Just accept whatever name TDESC_REGISTER_NAME returned. */
936 /* Implement gdbarch_pseudo_register_read. Read pseudo-register REGNUM
937 from REGCACHE and place the register value into BUF. BUF is sized
938 based on the type of register REGNUM, all of BUF should be written too,
939 the result should be sign or zero extended as appropriate. */
941 static enum register_status
942 riscv_pseudo_register_read (struct gdbarch
*gdbarch
,
943 readable_regcache
*regcache
,
944 int regnum
, gdb_byte
*buf
)
946 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
948 if (regnum
== tdep
->fflags_regnum
|| regnum
== tdep
->frm_regnum
)
951 memset (buf
, 0, register_size (gdbarch
, regnum
));
953 /* Read the first byte of the fcsr register, this contains both frm
955 enum register_status status
956 = regcache
->raw_read_part (RISCV_CSR_FCSR_REGNUM
, 0, 1, buf
);
958 if (status
!= REG_VALID
)
961 /* Extract the appropriate parts. */
962 if (regnum
== tdep
->fflags_regnum
)
964 else if (regnum
== tdep
->frm_regnum
)
965 buf
[0] = (buf
[0] >> 5) & 0x7;
973 /* Implement gdbarch_pseudo_register_write. Write the contents of BUF into
974 pseudo-register REGNUM in REGCACHE. BUF is sized based on the type of
978 riscv_pseudo_register_write (struct gdbarch
*gdbarch
,
979 struct regcache
*regcache
, int regnum
,
982 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
984 if (regnum
== tdep
->fflags_regnum
|| regnum
== tdep
->frm_regnum
)
986 int fcsr_regnum
= RISCV_CSR_FCSR_REGNUM
;
987 gdb_byte raw_buf
[register_size (gdbarch
, fcsr_regnum
)];
989 regcache
->raw_read (fcsr_regnum
, raw_buf
);
991 if (regnum
== tdep
->fflags_regnum
)
992 raw_buf
[0] = (raw_buf
[0] & ~0x1f) | (buf
[0] & 0x1f);
993 else if (regnum
== tdep
->frm_regnum
)
994 raw_buf
[0] = (raw_buf
[0] & ~(0x7 << 5)) | ((buf
[0] & 0x7) << 5);
996 regcache
->raw_write (fcsr_regnum
, raw_buf
);
999 gdb_assert_not_reached ("unknown pseudo register %d", regnum
);
1002 /* Implement the cannot_store_register gdbarch method. The zero register
1003 (x0) is read-only on RISC-V. */
1006 riscv_cannot_store_register (struct gdbarch
*gdbarch
, int regnum
)
1008 return regnum
== RISCV_ZERO_REGNUM
;
1011 /* Construct a type for 64-bit FP registers. */
1013 static struct type
*
1014 riscv_fpreg_d_type (struct gdbarch
*gdbarch
)
1016 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
1018 if (tdep
->riscv_fpreg_d_type
== nullptr)
1020 const struct builtin_type
*bt
= builtin_type (gdbarch
);
1022 /* The type we're building is this: */
1024 union __gdb_builtin_type_fpreg_d
1033 t
= arch_composite_type (gdbarch
,
1034 "__gdb_builtin_type_fpreg_d", TYPE_CODE_UNION
);
1035 append_composite_type_field (t
, "float", bt
->builtin_float
);
1036 append_composite_type_field (t
, "double", bt
->builtin_double
);
1037 t
->set_is_vector (true);
1038 t
->set_name ("builtin_type_fpreg_d");
1039 tdep
->riscv_fpreg_d_type
= t
;
1042 return tdep
->riscv_fpreg_d_type
;
1045 /* Implement the register_type gdbarch method. This is installed as an
1046 for the override setup by TDESC_USE_REGISTERS, for most registers we
1047 delegate the type choice to the target description, but for a few
1048 registers we try to improve the types if the target description has
1049 taken a simplistic approach. */
1051 static struct type
*
1052 riscv_register_type (struct gdbarch
*gdbarch
, int regnum
)
1054 struct type
*type
= tdesc_register_type (gdbarch
, regnum
);
1055 int xlen
= riscv_isa_xlen (gdbarch
);
1057 /* We want to perform some specific type "fixes" in cases where we feel
1058 that we really can do better than the target description. For all
1059 other cases we just return what the target description says. */
1060 if (riscv_is_fp_regno_p (regnum
))
1062 /* This spots the case for RV64 where the double is defined as
1063 either 'ieee_double' or 'float' (which is the generic name that
1064 converts to 'double' on 64-bit). In these cases its better to
1065 present the registers using a union type. */
1066 int flen
= riscv_isa_flen (gdbarch
);
1068 && type
->code () == TYPE_CODE_FLT
1069 && TYPE_LENGTH (type
) == flen
1070 && (strcmp (type
->name (), "builtin_type_ieee_double") == 0
1071 || strcmp (type
->name (), "double") == 0))
1072 type
= riscv_fpreg_d_type (gdbarch
);
1075 if ((regnum
== gdbarch_pc_regnum (gdbarch
)
1076 || regnum
== RISCV_RA_REGNUM
1077 || regnum
== RISCV_FP_REGNUM
1078 || regnum
== RISCV_SP_REGNUM
1079 || regnum
== RISCV_GP_REGNUM
1080 || regnum
== RISCV_TP_REGNUM
)
1081 && type
->code () == TYPE_CODE_INT
1082 && TYPE_LENGTH (type
) == xlen
)
1084 /* This spots the case where some interesting registers are defined
1085 as simple integers of the expected size, we force these registers
1086 to be pointers as we believe that is more useful. */
1087 if (regnum
== gdbarch_pc_regnum (gdbarch
)
1088 || regnum
== RISCV_RA_REGNUM
)
1089 type
= builtin_type (gdbarch
)->builtin_func_ptr
;
1090 else if (regnum
== RISCV_FP_REGNUM
1091 || regnum
== RISCV_SP_REGNUM
1092 || regnum
== RISCV_GP_REGNUM
1093 || regnum
== RISCV_TP_REGNUM
)
1094 type
= builtin_type (gdbarch
)->builtin_data_ptr
;
1100 /* Helper for riscv_print_registers_info, prints info for a single register
1104 riscv_print_one_register_info (struct gdbarch
*gdbarch
,
1105 struct ui_file
*file
,
1106 struct frame_info
*frame
,
1109 const char *name
= gdbarch_register_name (gdbarch
, regnum
);
1111 struct type
*regtype
;
1112 int print_raw_format
;
1113 enum tab_stops
{ value_column_1
= 15 };
1115 gdb_puts (name
, file
);
1116 print_spaces (value_column_1
- strlen (name
), file
);
1120 val
= value_of_register (regnum
, frame
);
1121 regtype
= value_type (val
);
1123 catch (const gdb_exception_error
&ex
)
1125 /* Handle failure to read a register without interrupting the entire
1126 'info registers' flow. */
1127 gdb_printf (file
, "%s\n", ex
.what ());
1131 print_raw_format
= (value_entirely_available (val
)
1132 && !value_optimized_out (val
));
1134 if (regtype
->code () == TYPE_CODE_FLT
1135 || (regtype
->code () == TYPE_CODE_UNION
1136 && regtype
->num_fields () == 2
1137 && regtype
->field (0).type ()->code () == TYPE_CODE_FLT
1138 && regtype
->field (1).type ()->code () == TYPE_CODE_FLT
)
1139 || (regtype
->code () == TYPE_CODE_UNION
1140 && regtype
->num_fields () == 3
1141 && regtype
->field (0).type ()->code () == TYPE_CODE_FLT
1142 && regtype
->field (1).type ()->code () == TYPE_CODE_FLT
1143 && regtype
->field (2).type ()->code () == TYPE_CODE_FLT
))
1145 struct value_print_options opts
;
1146 const gdb_byte
*valaddr
= value_contents_for_printing (val
).data ();
1147 enum bfd_endian byte_order
= type_byte_order (regtype
);
1149 get_user_print_options (&opts
);
1152 common_val_print (val
, file
, 0, &opts
, current_language
);
1154 if (print_raw_format
)
1156 gdb_printf (file
, "\t(raw ");
1157 print_hex_chars (file
, valaddr
, TYPE_LENGTH (regtype
), byte_order
,
1159 gdb_printf (file
, ")");
1164 struct value_print_options opts
;
1165 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
1167 /* Print the register in hex. */
1168 get_formatted_print_options (&opts
, 'x');
1170 common_val_print (val
, file
, 0, &opts
, current_language
);
1172 if (print_raw_format
)
1174 if (regnum
== RISCV_CSR_MSTATUS_REGNUM
)
1177 int size
= register_size (gdbarch
, regnum
);
1180 /* The SD field is always in the upper bit of MSTATUS, regardless
1181 of the number of bits in MSTATUS. */
1182 d
= value_as_long (val
);
1185 "\tSD:%X VM:%02X MXR:%X PUM:%X MPRV:%X XS:%X "
1186 "FS:%X MPP:%x HPP:%X SPP:%X MPIE:%X HPIE:%X "
1187 "SPIE:%X UPIE:%X MIE:%X HIE:%X SIE:%X UIE:%X",
1188 (int) ((d
>> (xlen
- 1)) & 0x1),
1189 (int) ((d
>> 24) & 0x1f),
1190 (int) ((d
>> 19) & 0x1),
1191 (int) ((d
>> 18) & 0x1),
1192 (int) ((d
>> 17) & 0x1),
1193 (int) ((d
>> 15) & 0x3),
1194 (int) ((d
>> 13) & 0x3),
1195 (int) ((d
>> 11) & 0x3),
1196 (int) ((d
>> 9) & 0x3),
1197 (int) ((d
>> 8) & 0x1),
1198 (int) ((d
>> 7) & 0x1),
1199 (int) ((d
>> 6) & 0x1),
1200 (int) ((d
>> 5) & 0x1),
1201 (int) ((d
>> 4) & 0x1),
1202 (int) ((d
>> 3) & 0x1),
1203 (int) ((d
>> 2) & 0x1),
1204 (int) ((d
>> 1) & 0x1),
1205 (int) ((d
>> 0) & 0x1));
1207 else if (regnum
== RISCV_CSR_MISA_REGNUM
)
1212 int size
= register_size (gdbarch
, regnum
);
1214 /* The MXL field is always in the upper two bits of MISA,
1215 regardless of the number of bits in MISA. Mask out other
1216 bits to ensure we have a positive value. */
1217 d
= value_as_long (val
);
1218 base
= (d
>> ((size
* 8) - 2)) & 0x3;
1221 for (; base
> 0; base
--)
1223 gdb_printf (file
, "\tRV%d", xlen
);
1225 for (i
= 0; i
< 26; i
++)
1228 gdb_printf (file
, "%c", 'A' + i
);
1231 else if (regnum
== RISCV_CSR_FCSR_REGNUM
1232 || regnum
== tdep
->fflags_regnum
1233 || regnum
== tdep
->frm_regnum
)
1235 LONGEST d
= value_as_long (val
);
1237 gdb_printf (file
, "\t");
1238 if (regnum
!= tdep
->frm_regnum
)
1240 "NV:%d DZ:%d OF:%d UF:%d NX:%d",
1241 (int) ((d
>> 4) & 0x1),
1242 (int) ((d
>> 3) & 0x1),
1243 (int) ((d
>> 2) & 0x1),
1244 (int) ((d
>> 1) & 0x1),
1245 (int) ((d
>> 0) & 0x1));
1247 if (regnum
!= tdep
->fflags_regnum
)
1249 static const char * const sfrm
[] =
1251 _("RNE (round to nearest; ties to even)"),
1252 _("RTZ (Round towards zero)"),
1253 _("RDN (Round down towards -INF)"),
1254 _("RUP (Round up towards +INF)"),
1255 _("RMM (Round to nearest; ties to max magnitude)"),
1258 /* A value of 0x7 indicates dynamic rounding mode when
1259 used within an instructions rounding-mode field, but
1260 is invalid within the FRM register. */
1261 _("INVALID[7] (Dynamic rounding mode)"),
1263 int frm
= ((regnum
== RISCV_CSR_FCSR_REGNUM
)
1264 ? (d
>> 5) : d
) & 0x7;
1266 gdb_printf (file
, "%sFRM:%i [%s]",
1267 (regnum
== RISCV_CSR_FCSR_REGNUM
1272 else if (regnum
== RISCV_PRIV_REGNUM
)
1277 d
= value_as_long (val
);
1282 static const char * const sprv
[] =
1289 gdb_printf (file
, "\tprv:%d [%s]",
1293 gdb_printf (file
, "\tprv:%d [INVALID]", priv
);
1297 /* If not a vector register, print it also according to its
1299 if (regtype
->is_vector () == 0)
1301 get_user_print_options (&opts
);
1303 gdb_printf (file
, "\t");
1304 common_val_print (val
, file
, 0, &opts
, current_language
);
1309 gdb_printf (file
, "\n");
1312 /* Return true if REGNUM is a valid CSR register. The CSR register space
1313 is sparsely populated, so not every number is a named CSR. */
1316 riscv_is_regnum_a_named_csr (int regnum
)
1318 gdb_assert (regnum
>= RISCV_FIRST_CSR_REGNUM
1319 && regnum
<= RISCV_LAST_CSR_REGNUM
);
1323 #define DECLARE_CSR(name, num, class, define_ver, abort_ver) case RISCV_ ## num ## _REGNUM:
1324 #include "opcode/riscv-opc.h"
1333 /* Return true if REGNUM is an unknown CSR identified in
1334 riscv_tdesc_unknown_reg for GDBARCH. */
1337 riscv_is_unknown_csr (struct gdbarch
*gdbarch
, int regnum
)
1339 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
1340 return (regnum
>= tdep
->unknown_csrs_first_regnum
1341 && regnum
< (tdep
->unknown_csrs_first_regnum
1342 + tdep
->unknown_csrs_count
));
1345 /* Implement the register_reggroup_p gdbarch method. Is REGNUM a member
1349 riscv_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
1350 const struct reggroup
*reggroup
)
1352 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
1354 /* Used by 'info registers' and 'info registers <groupname>'. */
1356 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
1357 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
1360 if (regnum
> RISCV_LAST_REGNUM
&& regnum
< gdbarch_num_regs (gdbarch
))
1362 /* Any extra registers from the CSR tdesc_feature (identified in
1363 riscv_tdesc_unknown_reg) are removed from the save/restore groups
1364 as some targets (QEMU) report CSRs which then can't be read and
1365 having unreadable registers in the save/restore group breaks
1366 things like inferior calls.
1368 The unknown CSRs are also removed from the general group, and
1369 added into both the csr and system group. This is inline with the
1370 known CSRs (see below). */
1371 if (riscv_is_unknown_csr (gdbarch
, regnum
))
1373 if (reggroup
== restore_reggroup
|| reggroup
== save_reggroup
1374 || reggroup
== general_reggroup
)
1376 else if (reggroup
== system_reggroup
|| reggroup
== csr_reggroup
)
1380 /* This is some other unknown register from the target description.
1381 In this case we trust whatever the target description says about
1382 which groups this register should be in. */
1383 int ret
= tdesc_register_in_reggroup_p (gdbarch
, regnum
, reggroup
);
1387 return default_register_reggroup_p (gdbarch
, regnum
, reggroup
);
1390 if (reggroup
== all_reggroup
)
1392 if (regnum
< RISCV_FIRST_CSR_REGNUM
|| regnum
>= RISCV_PRIV_REGNUM
)
1394 if (riscv_is_regnum_a_named_csr (regnum
))
1398 else if (reggroup
== float_reggroup
)
1399 return (riscv_is_fp_regno_p (regnum
)
1400 || regnum
== RISCV_CSR_FCSR_REGNUM
1401 || regnum
== tdep
->fflags_regnum
1402 || regnum
== tdep
->frm_regnum
);
1403 else if (reggroup
== general_reggroup
)
1404 return regnum
< RISCV_FIRST_FP_REGNUM
;
1405 else if (reggroup
== restore_reggroup
|| reggroup
== save_reggroup
)
1407 if (riscv_has_fp_regs (gdbarch
))
1408 return (regnum
<= RISCV_LAST_FP_REGNUM
1409 || regnum
== RISCV_CSR_FCSR_REGNUM
1410 || regnum
== tdep
->fflags_regnum
1411 || regnum
== tdep
->frm_regnum
);
1413 return regnum
< RISCV_FIRST_FP_REGNUM
;
1415 else if (reggroup
== system_reggroup
|| reggroup
== csr_reggroup
)
1417 if (regnum
== RISCV_PRIV_REGNUM
)
1419 if (regnum
< RISCV_FIRST_CSR_REGNUM
|| regnum
> RISCV_LAST_CSR_REGNUM
)
1421 if (riscv_is_regnum_a_named_csr (regnum
))
1425 else if (reggroup
== vector_reggroup
)
1426 return (regnum
>= RISCV_V0_REGNUM
&& regnum
<= RISCV_V31_REGNUM
);
1431 /* Return the name for pseudo-register REGNUM for GDBARCH. */
1434 riscv_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
1436 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
1438 if (regnum
== tdep
->fflags_regnum
)
1440 else if (regnum
== tdep
->frm_regnum
)
1443 gdb_assert_not_reached ("unknown pseudo register number %d", regnum
);
1446 /* Return the type for pseudo-register REGNUM for GDBARCH. */
1448 static struct type
*
1449 riscv_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
1451 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
1453 if (regnum
== tdep
->fflags_regnum
|| regnum
== tdep
->frm_regnum
)
1454 return builtin_type (gdbarch
)->builtin_int32
;
1456 gdb_assert_not_reached ("unknown pseudo register number %d", regnum
);
1459 /* Return true (non-zero) if pseudo-register REGNUM from GDBARCH is a
1460 member of REGGROUP, otherwise return false (zero). */
1463 riscv_pseudo_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
1464 const struct reggroup
*reggroup
)
1466 /* The standard function will also work for pseudo-registers. */
1467 return riscv_register_reggroup_p (gdbarch
, regnum
, reggroup
);
1470 /* Implement the print_registers_info gdbarch method. This is used by
1471 'info registers' and 'info all-registers'. */
1474 riscv_print_registers_info (struct gdbarch
*gdbarch
,
1475 struct ui_file
*file
,
1476 struct frame_info
*frame
,
1477 int regnum
, int print_all
)
1481 /* Print one specified register. */
1482 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
1483 || *(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
1484 error (_("Not a valid register for the current processor type"));
1485 riscv_print_one_register_info (gdbarch
, file
, frame
, regnum
);
1489 const struct reggroup
*reggroup
;
1492 reggroup
= all_reggroup
;
1494 reggroup
= general_reggroup
;
1496 for (regnum
= 0; regnum
< gdbarch_num_cooked_regs (gdbarch
); ++regnum
)
1498 /* Zero never changes, so might as well hide by default. */
1499 if (regnum
== RISCV_ZERO_REGNUM
&& !print_all
)
1502 /* Registers with no name are not valid on this ISA. */
1503 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
1504 || *(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
1507 /* Is the register in the group we're interested in? */
1508 if (!gdbarch_register_reggroup_p (gdbarch
, regnum
, reggroup
))
1511 riscv_print_one_register_info (gdbarch
, file
, frame
, regnum
);
1516 /* Class that handles one decoded RiscV instruction. */
1522 /* Enum of all the opcodes that GDB cares about during the prologue scan. */
1525 /* Unknown value is used at initialisation time. */
1528 /* These instructions are all the ones we are interested in during the
1541 /* These are needed for software breakpoint support. */
1550 /* These are needed for stepping over atomic sequences. */
1553 /* This instruction is used to do a syscall. */
1556 /* Other instructions are not interesting during the prologue scan, and
1571 void decode (struct gdbarch
*gdbarch
, CORE_ADDR pc
);
1573 /* Get the length of the instruction in bytes. */
1575 { return m_length
; }
1577 /* Get the opcode for this instruction. */
1578 enum opcode
opcode () const
1579 { return m_opcode
; }
1581 /* Get destination register field for this instruction. This is only
1582 valid if the OPCODE implies there is such a field for this
1587 /* Get the RS1 register field for this instruction. This is only valid
1588 if the OPCODE implies there is such a field for this instruction. */
1592 /* Get the RS2 register field for this instruction. This is only valid
1593 if the OPCODE implies there is such a field for this instruction. */
1597 /* Get the immediate for this instruction in signed form. This is only
1598 valid if the OPCODE implies there is such a field for this
1600 int imm_signed () const
1605 /* Extract 5 bit register field at OFFSET from instruction OPCODE. */
1606 int decode_register_index (unsigned long opcode
, int offset
)
1608 return (opcode
>> offset
) & 0x1F;
1611 /* Extract 5 bit register field at OFFSET from instruction OPCODE. */
1612 int decode_register_index_short (unsigned long opcode
, int offset
)
1614 return ((opcode
>> offset
) & 0x7) + 8;
1617 /* Helper for DECODE, decode 32-bit R-type instruction. */
1618 void decode_r_type_insn (enum opcode opcode
, ULONGEST ival
)
1621 m_rd
= decode_register_index (ival
, OP_SH_RD
);
1622 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
1623 m_rs2
= decode_register_index (ival
, OP_SH_RS2
);
1626 /* Helper for DECODE, decode 16-bit compressed R-type instruction. */
1627 void decode_cr_type_insn (enum opcode opcode
, ULONGEST ival
)
1630 m_rd
= m_rs1
= decode_register_index (ival
, OP_SH_CRS1S
);
1631 m_rs2
= decode_register_index (ival
, OP_SH_CRS2
);
1634 /* Helper for DECODE, decode 32-bit I-type instruction. */
1635 void decode_i_type_insn (enum opcode opcode
, ULONGEST ival
)
1638 m_rd
= decode_register_index (ival
, OP_SH_RD
);
1639 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
1640 m_imm
.s
= EXTRACT_ITYPE_IMM (ival
);
1643 /* Helper for DECODE, decode 16-bit compressed I-type instruction. */
1644 void decode_ci_type_insn (enum opcode opcode
, ULONGEST ival
)
1647 m_rd
= m_rs1
= decode_register_index (ival
, OP_SH_CRS1S
);
1648 m_imm
.s
= EXTRACT_CITYPE_IMM (ival
);
1651 /* Helper for DECODE, decode 16-bit compressed CL-type instruction. */
1652 void decode_cl_type_insn (enum opcode opcode
, ULONGEST ival
)
1655 m_rd
= decode_register_index_short (ival
, OP_SH_CRS2S
);
1656 m_rs1
= decode_register_index_short (ival
, OP_SH_CRS1S
);
1657 m_imm
.s
= EXTRACT_CLTYPE_IMM (ival
);
1660 /* Helper for DECODE, decode 32-bit S-type instruction. */
1661 void decode_s_type_insn (enum opcode opcode
, ULONGEST ival
)
1664 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
1665 m_rs2
= decode_register_index (ival
, OP_SH_RS2
);
1666 m_imm
.s
= EXTRACT_STYPE_IMM (ival
);
1669 /* Helper for DECODE, decode 16-bit CS-type instruction. The immediate
1670 encoding is different for each CS format instruction, so extracting
1671 the immediate is left up to the caller, who should pass the extracted
1672 immediate value through in IMM. */
1673 void decode_cs_type_insn (enum opcode opcode
, ULONGEST ival
, int imm
)
1677 m_rs1
= decode_register_index_short (ival
, OP_SH_CRS1S
);
1678 m_rs2
= decode_register_index_short (ival
, OP_SH_CRS2S
);
1681 /* Helper for DECODE, decode 16-bit CSS-type instruction. The immediate
1682 encoding is different for each CSS format instruction, so extracting
1683 the immediate is left up to the caller, who should pass the extracted
1684 immediate value through in IMM. */
1685 void decode_css_type_insn (enum opcode opcode
, ULONGEST ival
, int imm
)
1689 m_rs1
= RISCV_SP_REGNUM
;
1690 /* Not a compressed register number in this case. */
1691 m_rs2
= decode_register_index (ival
, OP_SH_CRS2
);
1694 /* Helper for DECODE, decode 32-bit U-type instruction. */
1695 void decode_u_type_insn (enum opcode opcode
, ULONGEST ival
)
1698 m_rd
= decode_register_index (ival
, OP_SH_RD
);
1699 m_imm
.s
= EXTRACT_UTYPE_IMM (ival
);
1702 /* Helper for DECODE, decode 32-bit J-type instruction. */
1703 void decode_j_type_insn (enum opcode opcode
, ULONGEST ival
)
1706 m_rd
= decode_register_index (ival
, OP_SH_RD
);
1707 m_imm
.s
= EXTRACT_JTYPE_IMM (ival
);
1710 /* Helper for DECODE, decode 32-bit J-type instruction. */
1711 void decode_cj_type_insn (enum opcode opcode
, ULONGEST ival
)
1714 m_imm
.s
= EXTRACT_CJTYPE_IMM (ival
);
1717 void decode_b_type_insn (enum opcode opcode
, ULONGEST ival
)
1720 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
1721 m_rs2
= decode_register_index (ival
, OP_SH_RS2
);
1722 m_imm
.s
= EXTRACT_BTYPE_IMM (ival
);
1725 void decode_cb_type_insn (enum opcode opcode
, ULONGEST ival
)
1728 m_rs1
= decode_register_index_short (ival
, OP_SH_CRS1S
);
1729 m_imm
.s
= EXTRACT_CBTYPE_IMM (ival
);
1732 /* Fetch instruction from target memory at ADDR, return the content of
1733 the instruction, and update LEN with the instruction length. */
1734 static ULONGEST
fetch_instruction (struct gdbarch
*gdbarch
,
1735 CORE_ADDR addr
, int *len
);
1737 /* The length of the instruction in bytes. Should be 2 or 4. */
1740 /* The instruction opcode. */
1741 enum opcode m_opcode
;
1743 /* The three possible registers an instruction might reference. Not
1744 every instruction fills in all of these registers. Which fields are
1745 valid depends on the opcode. The naming of these fields matches the
1746 naming in the riscv isa manual. */
1751 /* Possible instruction immediate. This is only valid if the instruction
1752 format contains an immediate, not all instruction, whether this is
1753 valid depends on the opcode. Despite only having one format for now
1754 the immediate is packed into a union, later instructions might require
1755 an unsigned formatted immediate, having the union in place now will
1756 reduce the need for code churn later. */
1757 union riscv_insn_immediate
1759 riscv_insn_immediate ()
1769 /* Fetch instruction from target memory at ADDR, return the content of the
1770 instruction, and update LEN with the instruction length. */
1773 riscv_insn::fetch_instruction (struct gdbarch
*gdbarch
,
1774 CORE_ADDR addr
, int *len
)
1776 enum bfd_endian byte_order
= gdbarch_byte_order_for_code (gdbarch
);
1778 int instlen
, status
;
1780 /* All insns are at least 16 bits. */
1781 status
= target_read_memory (addr
, buf
, 2);
1783 memory_error (TARGET_XFER_E_IO
, addr
);
1785 /* If we need more, grab it now. */
1786 instlen
= riscv_insn_length (buf
[0]);
1787 gdb_assert (instlen
<= sizeof (buf
));
1792 status
= target_read_memory (addr
+ 2, buf
+ 2, instlen
- 2);
1794 memory_error (TARGET_XFER_E_IO
, addr
+ 2);
1797 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1800 /* Fetch from target memory an instruction at PC and decode it. This can
1801 throw an error if the memory access fails, callers are responsible for
1802 handling this error if that is appropriate. */
1805 riscv_insn::decode (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1809 /* Fetch the instruction, and the instructions length. */
1810 ival
= fetch_instruction (gdbarch
, pc
, &m_length
);
1814 if (is_add_insn (ival
))
1815 decode_r_type_insn (ADD
, ival
);
1816 else if (is_addw_insn (ival
))
1817 decode_r_type_insn (ADDW
, ival
);
1818 else if (is_addi_insn (ival
))
1819 decode_i_type_insn (ADDI
, ival
);
1820 else if (is_addiw_insn (ival
))
1821 decode_i_type_insn (ADDIW
, ival
);
1822 else if (is_auipc_insn (ival
))
1823 decode_u_type_insn (AUIPC
, ival
);
1824 else if (is_lui_insn (ival
))
1825 decode_u_type_insn (LUI
, ival
);
1826 else if (is_sd_insn (ival
))
1827 decode_s_type_insn (SD
, ival
);
1828 else if (is_sw_insn (ival
))
1829 decode_s_type_insn (SW
, ival
);
1830 else if (is_jal_insn (ival
))
1831 decode_j_type_insn (JAL
, ival
);
1832 else if (is_jalr_insn (ival
))
1833 decode_i_type_insn (JALR
, ival
);
1834 else if (is_beq_insn (ival
))
1835 decode_b_type_insn (BEQ
, ival
);
1836 else if (is_bne_insn (ival
))
1837 decode_b_type_insn (BNE
, ival
);
1838 else if (is_blt_insn (ival
))
1839 decode_b_type_insn (BLT
, ival
);
1840 else if (is_bge_insn (ival
))
1841 decode_b_type_insn (BGE
, ival
);
1842 else if (is_bltu_insn (ival
))
1843 decode_b_type_insn (BLTU
, ival
);
1844 else if (is_bgeu_insn (ival
))
1845 decode_b_type_insn (BGEU
, ival
);
1846 else if (is_lr_w_insn (ival
))
1847 decode_r_type_insn (LR
, ival
);
1848 else if (is_lr_d_insn (ival
))
1849 decode_r_type_insn (LR
, ival
);
1850 else if (is_sc_w_insn (ival
))
1851 decode_r_type_insn (SC
, ival
);
1852 else if (is_sc_d_insn (ival
))
1853 decode_r_type_insn (SC
, ival
);
1854 else if (is_ecall_insn (ival
))
1855 decode_i_type_insn (ECALL
, ival
);
1856 else if (is_ld_insn (ival
))
1857 decode_i_type_insn (LD
, ival
);
1858 else if (is_lw_insn (ival
))
1859 decode_i_type_insn (LW
, ival
);
1861 /* None of the other fields are valid in this case. */
1864 else if (m_length
== 2)
1866 int xlen
= riscv_isa_xlen (gdbarch
);
1868 /* C_ADD and C_JALR have the same opcode. If RS2 is 0, then this is a
1869 C_JALR. So must try to match C_JALR first as it has more bits in
1871 if (is_c_jalr_insn (ival
))
1872 decode_cr_type_insn (JALR
, ival
);
1873 else if (is_c_add_insn (ival
))
1874 decode_cr_type_insn (ADD
, ival
);
1875 /* C_ADDW is RV64 and RV128 only. */
1876 else if (xlen
!= 4 && is_c_addw_insn (ival
))
1877 decode_cr_type_insn (ADDW
, ival
);
1878 else if (is_c_addi_insn (ival
))
1879 decode_ci_type_insn (ADDI
, ival
);
1880 /* C_ADDIW and C_JAL have the same opcode. C_ADDIW is RV64 and RV128
1881 only and C_JAL is RV32 only. */
1882 else if (xlen
!= 4 && is_c_addiw_insn (ival
))
1883 decode_ci_type_insn (ADDIW
, ival
);
1884 else if (xlen
== 4 && is_c_jal_insn (ival
))
1885 decode_cj_type_insn (JAL
, ival
);
1886 /* C_ADDI16SP and C_LUI have the same opcode. If RD is 2, then this is a
1887 C_ADDI16SP. So must try to match C_ADDI16SP first as it has more bits
1889 else if (is_c_addi16sp_insn (ival
))
1892 m_rd
= m_rs1
= decode_register_index (ival
, OP_SH_RD
);
1893 m_imm
.s
= EXTRACT_CITYPE_ADDI16SP_IMM (ival
);
1895 else if (is_c_addi4spn_insn (ival
))
1898 m_rd
= decode_register_index_short (ival
, OP_SH_CRS2S
);
1899 m_rs1
= RISCV_SP_REGNUM
;
1900 m_imm
.s
= EXTRACT_CIWTYPE_ADDI4SPN_IMM (ival
);
1902 else if (is_c_lui_insn (ival
))
1905 m_rd
= decode_register_index (ival
, OP_SH_CRS1S
);
1906 m_imm
.s
= EXTRACT_CITYPE_LUI_IMM (ival
);
1908 /* C_SD and C_FSW have the same opcode. C_SD is RV64 and RV128 only,
1909 and C_FSW is RV32 only. */
1910 else if (xlen
!= 4 && is_c_sd_insn (ival
))
1911 decode_cs_type_insn (SD
, ival
, EXTRACT_CLTYPE_LD_IMM (ival
));
1912 else if (is_c_sw_insn (ival
))
1913 decode_cs_type_insn (SW
, ival
, EXTRACT_CLTYPE_LW_IMM (ival
));
1914 else if (is_c_swsp_insn (ival
))
1915 decode_css_type_insn (SW
, ival
, EXTRACT_CSSTYPE_SWSP_IMM (ival
));
1916 else if (xlen
!= 4 && is_c_sdsp_insn (ival
))
1917 decode_css_type_insn (SD
, ival
, EXTRACT_CSSTYPE_SDSP_IMM (ival
));
1918 /* C_JR and C_MV have the same opcode. If RS2 is 0, then this is a C_JR.
1919 So must try to match C_JR first as it has more bits in mask. */
1920 else if (is_c_jr_insn (ival
))
1921 decode_cr_type_insn (JALR
, ival
);
1922 else if (is_c_mv_insn (ival
))
1923 decode_cr_type_insn (MV
, ival
);
1924 else if (is_c_j_insn (ival
))
1925 decode_cj_type_insn (JAL
, ival
);
1926 else if (is_c_beqz_insn (ival
))
1927 decode_cb_type_insn (BEQ
, ival
);
1928 else if (is_c_bnez_insn (ival
))
1929 decode_cb_type_insn (BNE
, ival
);
1930 else if (is_c_ld_insn (ival
))
1931 decode_cl_type_insn (LD
, ival
);
1932 else if (is_c_lw_insn (ival
))
1933 decode_cl_type_insn (LW
, ival
);
1935 /* None of the other fields of INSN are valid in this case. */
1940 /* This must be a 6 or 8 byte instruction, we don't currently decode
1941 any of these, so just ignore it. */
1942 gdb_assert (m_length
== 6 || m_length
== 8);
1947 /* The prologue scanner. This is currently only used for skipping the
1948 prologue of a function when the DWARF information is not sufficient.
1949 However, it is written with filling of the frame cache in mind, which
1950 is why different groups of stack setup instructions are split apart
1951 during the core of the inner loop. In the future, the intention is to
1952 extend this function to fully support building up a frame cache that
1953 can unwind register values when there is no DWARF information. */
1956 riscv_scan_prologue (struct gdbarch
*gdbarch
,
1957 CORE_ADDR start_pc
, CORE_ADDR end_pc
,
1958 struct riscv_unwind_cache
*cache
)
1960 CORE_ADDR cur_pc
, next_pc
, after_prologue_pc
;
1961 CORE_ADDR end_prologue_addr
= 0;
1963 /* Find an upper limit on the function prologue using the debug
1964 information. If the debug information could not be used to provide
1965 that bound, then use an arbitrary large number as the upper bound. */
1966 after_prologue_pc
= skip_prologue_using_sal (gdbarch
, start_pc
);
1967 if (after_prologue_pc
== 0)
1968 after_prologue_pc
= start_pc
+ 100; /* Arbitrary large number. */
1969 if (after_prologue_pc
< end_pc
)
1970 end_pc
= after_prologue_pc
;
1972 pv_t regs
[RISCV_NUM_INTEGER_REGS
]; /* Number of GPR. */
1973 for (int regno
= 0; regno
< RISCV_NUM_INTEGER_REGS
; regno
++)
1974 regs
[regno
] = pv_register (regno
, 0);
1975 pv_area
stack (RISCV_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
1977 if (riscv_debug_unwinder
)
1980 "Prologue scan for function starting at %s (limit %s)\n",
1981 core_addr_to_string (start_pc
),
1982 core_addr_to_string (end_pc
));
1984 for (next_pc
= cur_pc
= start_pc
; cur_pc
< end_pc
; cur_pc
= next_pc
)
1986 struct riscv_insn insn
;
1988 /* Decode the current instruction, and decide where the next
1989 instruction lives based on the size of this instruction. */
1990 insn
.decode (gdbarch
, cur_pc
);
1991 gdb_assert (insn
.length () > 0);
1992 next_pc
= cur_pc
+ insn
.length ();
1994 /* Look for common stack adjustment insns. */
1995 if ((insn
.opcode () == riscv_insn::ADDI
1996 || insn
.opcode () == riscv_insn::ADDIW
)
1997 && insn
.rd () == RISCV_SP_REGNUM
1998 && insn
.rs1 () == RISCV_SP_REGNUM
)
2000 /* Handle: addi sp, sp, -i
2001 or: addiw sp, sp, -i */
2002 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
2003 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
2005 = pv_add_constant (regs
[insn
.rs1 ()], insn
.imm_signed ());
2007 else if ((insn
.opcode () == riscv_insn::SW
2008 || insn
.opcode () == riscv_insn::SD
)
2009 && (insn
.rs1 () == RISCV_SP_REGNUM
2010 || insn
.rs1 () == RISCV_FP_REGNUM
))
2012 /* Handle: sw reg, offset(sp)
2013 or: sd reg, offset(sp)
2014 or: sw reg, offset(s0)
2015 or: sd reg, offset(s0) */
2016 /* Instruction storing a register onto the stack. */
2017 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
2018 gdb_assert (insn
.rs2 () < RISCV_NUM_INTEGER_REGS
);
2019 stack
.store (pv_add_constant (regs
[insn
.rs1 ()], insn
.imm_signed ()),
2020 (insn
.opcode () == riscv_insn::SW
? 4 : 8),
2023 else if (insn
.opcode () == riscv_insn::ADDI
2024 && insn
.rd () == RISCV_FP_REGNUM
2025 && insn
.rs1 () == RISCV_SP_REGNUM
)
2027 /* Handle: addi s0, sp, size */
2028 /* Instructions setting up the frame pointer. */
2029 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
2030 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
2032 = pv_add_constant (regs
[insn
.rs1 ()], insn
.imm_signed ());
2034 else if ((insn
.opcode () == riscv_insn::ADD
2035 || insn
.opcode () == riscv_insn::ADDW
)
2036 && insn
.rd () == RISCV_FP_REGNUM
2037 && insn
.rs1 () == RISCV_SP_REGNUM
2038 && insn
.rs2 () == RISCV_ZERO_REGNUM
)
2040 /* Handle: add s0, sp, 0
2041 or: addw s0, sp, 0 */
2042 /* Instructions setting up the frame pointer. */
2043 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
2044 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
2045 regs
[insn
.rd ()] = pv_add_constant (regs
[insn
.rs1 ()], 0);
2047 else if ((insn
.opcode () == riscv_insn::ADDI
2048 && insn
.rd () == RISCV_ZERO_REGNUM
2049 && insn
.rs1 () == RISCV_ZERO_REGNUM
2050 && insn
.imm_signed () == 0))
2052 /* Handle: add x0, x0, 0 (NOP) */
2054 else if (insn
.opcode () == riscv_insn::AUIPC
)
2056 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
2057 regs
[insn
.rd ()] = pv_constant (cur_pc
+ insn
.imm_signed ());
2059 else if (insn
.opcode () == riscv_insn::LUI
)
2061 /* Handle: lui REG, n
2062 Where REG is not gp register. */
2063 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
2064 regs
[insn
.rd ()] = pv_constant (insn
.imm_signed ());
2066 else if (insn
.opcode () == riscv_insn::ADDI
)
2068 /* Handle: addi REG1, REG2, IMM */
2069 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
2070 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
2072 = pv_add_constant (regs
[insn
.rs1 ()], insn
.imm_signed ());
2074 else if (insn
.opcode () == riscv_insn::ADD
)
2076 /* Handle: add REG1, REG2, REG3 */
2077 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
2078 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
2079 gdb_assert (insn
.rs2 () < RISCV_NUM_INTEGER_REGS
);
2080 regs
[insn
.rd ()] = pv_add (regs
[insn
.rs1 ()], regs
[insn
.rs2 ()]);
2082 else if (insn
.opcode () == riscv_insn::LD
2083 || insn
.opcode () == riscv_insn::LW
)
2085 /* Handle: ld reg, offset(rs1)
2086 or: c.ld reg, offset(rs1)
2087 or: lw reg, offset(rs1)
2088 or: c.lw reg, offset(rs1) */
2089 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
2090 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
2092 = stack
.fetch (pv_add_constant (regs
[insn
.rs1 ()],
2093 insn
.imm_signed ()),
2094 (insn
.opcode () == riscv_insn::LW
? 4 : 8));
2096 else if (insn
.opcode () == riscv_insn::MV
)
2098 /* Handle: c.mv RD, RS2 */
2099 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
2100 gdb_assert (insn
.rs2 () < RISCV_NUM_INTEGER_REGS
);
2101 gdb_assert (insn
.rs2 () > 0);
2102 regs
[insn
.rd ()] = regs
[insn
.rs2 ()];
2106 end_prologue_addr
= cur_pc
;
2111 if (end_prologue_addr
== 0)
2112 end_prologue_addr
= cur_pc
;
2114 if (riscv_debug_unwinder
)
2115 gdb_printf (gdb_stdlog
, "End of prologue at %s\n",
2116 core_addr_to_string (end_prologue_addr
));
2120 /* Figure out if it is a frame pointer or just a stack pointer. Also
2121 the offset held in the pv_t is from the original register value to
2122 the current value, which for a grows down stack means a negative
2123 value. The FRAME_BASE_OFFSET is the negation of this, how to get
2124 from the current value to the original value. */
2125 if (pv_is_register (regs
[RISCV_FP_REGNUM
], RISCV_SP_REGNUM
))
2127 cache
->frame_base_reg
= RISCV_FP_REGNUM
;
2128 cache
->frame_base_offset
= -regs
[RISCV_FP_REGNUM
].k
;
2132 cache
->frame_base_reg
= RISCV_SP_REGNUM
;
2133 cache
->frame_base_offset
= -regs
[RISCV_SP_REGNUM
].k
;
2136 /* Assign offset from old SP to all saved registers. As we don't
2137 have the previous value for the frame base register at this
2138 point, we store the offset as the address in the trad_frame, and
2139 then convert this to an actual address later. */
2140 for (int i
= 0; i
<= RISCV_NUM_INTEGER_REGS
; i
++)
2143 if (stack
.find_reg (gdbarch
, i
, &offset
))
2145 if (riscv_debug_unwinder
)
2147 /* Display OFFSET as a signed value, the offsets are from
2148 the frame base address to the registers location on
2149 the stack, with a descending stack this means the
2150 offsets are always negative. */
2151 gdb_printf (gdb_stdlog
,
2152 "Register $%s at stack offset %s\n",
2153 gdbarch_register_name (gdbarch
, i
),
2154 plongest ((LONGEST
) offset
));
2156 cache
->regs
[i
].set_addr (offset
);
2161 return end_prologue_addr
;
2164 /* Implement the riscv_skip_prologue gdbarch method. */
2167 riscv_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2169 CORE_ADDR func_addr
;
2171 /* See if we can determine the end of the prologue via the symbol
2172 table. If so, then return either PC, or the PC after the
2173 prologue, whichever is greater. */
2174 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
2176 CORE_ADDR post_prologue_pc
2177 = skip_prologue_using_sal (gdbarch
, func_addr
);
2179 if (post_prologue_pc
!= 0)
2180 return std::max (pc
, post_prologue_pc
);
2183 /* Can't determine prologue from the symbol table, need to examine
2184 instructions. Pass -1 for the end address to indicate the prologue
2185 scanner can scan as far as it needs to find the end of the prologue. */
2186 return riscv_scan_prologue (gdbarch
, pc
, ((CORE_ADDR
) -1), NULL
);
2189 /* Implement the gdbarch push dummy code callback. */
2192 riscv_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
2193 CORE_ADDR funaddr
, struct value
**args
, int nargs
,
2194 struct type
*value_type
, CORE_ADDR
*real_pc
,
2195 CORE_ADDR
*bp_addr
, struct regcache
*regcache
)
2197 /* A nop instruction is 'add x0, x0, 0'. */
2198 static const gdb_byte nop_insn
[] = { 0x13, 0x00, 0x00, 0x00 };
2200 /* Allocate space for a breakpoint, and keep the stack correctly
2201 aligned. The space allocated here must be at least big enough to
2202 accommodate the NOP_INSN defined above. */
2207 /* When we insert a breakpoint we select whether to use a compressed
2208 breakpoint or not based on the existing contents of the memory.
2210 If the breakpoint is being placed onto the stack as part of setting up
2211 for an inferior call from GDB, then the existing stack contents may
2212 randomly appear to be a compressed instruction, causing GDB to insert
2213 a compressed breakpoint. If this happens on a target that does not
2214 support compressed instructions then this could cause problems.
2216 To prevent this issue we write an uncompressed nop onto the stack at
2217 the location where the breakpoint will be inserted. In this way we
2218 ensure that we always use an uncompressed breakpoint, which should
2219 work on all targets.
2221 We call TARGET_WRITE_MEMORY here so that if the write fails we don't
2222 throw an exception. Instead we ignore the error and move on. The
2223 assumption is that either GDB will error later when actually trying to
2224 insert a software breakpoint, or GDB will use hardware breakpoints and
2225 there will be no need to write to memory later. */
2226 int status
= target_write_memory (*bp_addr
, nop_insn
, sizeof (nop_insn
));
2228 if (riscv_debug_breakpoints
|| riscv_debug_infcall
)
2229 gdb_printf (gdb_stdlog
,
2230 "Writing %s-byte nop instruction to %s: %s\n",
2231 plongest (sizeof (nop_insn
)),
2232 paddress (gdbarch
, *bp_addr
),
2233 (status
== 0 ? "success" : "failed"));
2238 /* Implement the gdbarch type alignment method, overrides the generic
2239 alignment algorithm for anything that is RISC-V specific. */
2242 riscv_type_align (gdbarch
*gdbarch
, type
*type
)
2244 type
= check_typedef (type
);
2245 if (type
->code () == TYPE_CODE_ARRAY
&& type
->is_vector ())
2246 return std::min (TYPE_LENGTH (type
), (ULONGEST
) BIGGEST_ALIGNMENT
);
2248 /* Anything else will be aligned by the generic code. */
2252 /* Holds information about a single argument either being passed to an
2253 inferior function, or returned from an inferior function. This includes
2254 information about the size, type, etc of the argument, and also
2255 information about how the argument will be passed (or returned). */
2257 struct riscv_arg_info
2259 /* Contents of the argument. */
2260 const gdb_byte
*contents
;
2262 /* Length of argument. */
2265 /* Alignment required for an argument of this type. */
2268 /* The type for this argument. */
2271 /* Each argument can have either 1 or 2 locations assigned to it. Each
2272 location describes where part of the argument will be placed. The
2273 second location is valid based on the LOC_TYPE and C_LENGTH fields
2274 of the first location (which is always valid). */
2277 /* What type of location this is. */
2280 /* Argument passed in a register. */
2283 /* Argument passed as an on stack argument. */
2286 /* Argument passed by reference. The second location is always
2287 valid for a BY_REF argument, and describes where the address
2288 of the BY_REF argument should be placed. */
2292 /* Information that depends on the location type. */
2295 /* Which register number to use. */
2298 /* The offset into the stack region. */
2302 /* The length of contents covered by this location. If this is less
2303 than the total length of the argument, then the second location
2304 will be valid, and will describe where the rest of the argument
2308 /* The offset within CONTENTS for this part of the argument. This can
2309 be non-zero even for the first part (the first field of a struct can
2310 have a non-zero offset due to padding). For the second part of the
2311 argument, this might be the C_LENGTH value of the first part,
2312 however, if we are passing a structure in two registers, and there's
2313 is padding between the first and second field, then this offset
2314 might be greater than the length of the first argument part. When
2315 the second argument location is not holding part of the argument
2316 value, but is instead holding the address of a reference argument,
2317 then this offset will be set to 0. */
2321 /* TRUE if this is an unnamed argument. */
2325 /* Information about a set of registers being used for passing arguments as
2326 part of a function call. The register set must be numerically
2327 sequential from NEXT_REGNUM to LAST_REGNUM. The register set can be
2328 disabled from use by setting NEXT_REGNUM greater than LAST_REGNUM. */
2330 struct riscv_arg_reg
2332 riscv_arg_reg (int first
, int last
)
2333 : next_regnum (first
),
2339 /* The GDB register number to use in this set. */
2342 /* The last GDB register number to use in this set. */
2346 /* Arguments can be passed as on stack arguments, or by reference. The
2347 on stack arguments must be in a continuous region starting from $sp,
2348 while the by reference arguments can be anywhere, but we'll put them
2349 on the stack after (at higher address) the on stack arguments.
2351 This might not be the right approach to take. The ABI is clear that
2352 an argument passed by reference can be modified by the callee, which
2353 us placing the argument (temporarily) onto the stack will not achieve
2354 (changes will be lost). There's also the possibility that very large
2355 arguments could overflow the stack.
2357 This struct is used to track offset into these two areas for where
2358 arguments are to be placed. */
2359 struct riscv_memory_offsets
2361 riscv_memory_offsets ()
2368 /* Offset into on stack argument area. */
2371 /* Offset into the pass by reference area. */
2375 /* Holds information about where arguments to a call will be placed. This
2376 is updated as arguments are added onto the call, and can be used to
2377 figure out where the next argument should be placed. */
2379 struct riscv_call_info
2381 riscv_call_info (struct gdbarch
*gdbarch
)
2382 : int_regs (RISCV_A0_REGNUM
, RISCV_A0_REGNUM
+ 7),
2383 float_regs (RISCV_FA0_REGNUM
, RISCV_FA0_REGNUM
+ 7)
2385 xlen
= riscv_abi_xlen (gdbarch
);
2386 flen
= riscv_abi_flen (gdbarch
);
2388 /* Reduce the number of integer argument registers when using the
2389 embedded abi (i.e. rv32e). */
2390 if (riscv_abi_embedded (gdbarch
))
2391 int_regs
.last_regnum
= RISCV_A0_REGNUM
+ 5;
2393 /* Disable use of floating point registers if needed. */
2394 if (!riscv_has_fp_abi (gdbarch
))
2395 float_regs
.next_regnum
= float_regs
.last_regnum
+ 1;
2398 /* Track the memory areas used for holding in-memory arguments to a
2400 struct riscv_memory_offsets memory
;
2402 /* Holds information about the next integer register to use for passing
2404 struct riscv_arg_reg int_regs
;
2406 /* Holds information about the next floating point register to use for
2407 passing an argument. */
2408 struct riscv_arg_reg float_regs
;
2410 /* The XLEN and FLEN are copied in to this structure for convenience, and
2411 are just the results of calling RISCV_ABI_XLEN and RISCV_ABI_FLEN. */
2416 /* Return the number of registers available for use as parameters in the
2417 register set REG. Returned value can be 0 or more. */
2420 riscv_arg_regs_available (struct riscv_arg_reg
*reg
)
2422 if (reg
->next_regnum
> reg
->last_regnum
)
2425 return (reg
->last_regnum
- reg
->next_regnum
+ 1);
2428 /* If there is at least one register available in the register set REG then
2429 the next register from REG is assigned to LOC and the length field of
2430 LOC is updated to LENGTH. The register set REG is updated to indicate
2431 that the assigned register is no longer available and the function
2434 If there are no registers available in REG then the function returns
2435 false, and LOC and REG are unchanged. */
2438 riscv_assign_reg_location (struct riscv_arg_info::location
*loc
,
2439 struct riscv_arg_reg
*reg
,
2440 int length
, int offset
)
2442 if (reg
->next_regnum
<= reg
->last_regnum
)
2444 loc
->loc_type
= riscv_arg_info::location::in_reg
;
2445 loc
->loc_data
.regno
= reg
->next_regnum
;
2447 loc
->c_length
= length
;
2448 loc
->c_offset
= offset
;
2455 /* Assign LOC a location as the next stack parameter, and update MEMORY to
2456 record that an area of stack has been used to hold the parameter
2459 The length field of LOC is updated to LENGTH, the length of the
2460 parameter being stored, and ALIGN is the alignment required by the
2461 parameter, which will affect how memory is allocated out of MEMORY. */
2464 riscv_assign_stack_location (struct riscv_arg_info::location
*loc
,
2465 struct riscv_memory_offsets
*memory
,
2466 int length
, int align
)
2468 loc
->loc_type
= riscv_arg_info::location::on_stack
;
2470 = align_up (memory
->arg_offset
, align
);
2471 loc
->loc_data
.offset
= memory
->arg_offset
;
2472 memory
->arg_offset
+= length
;
2473 loc
->c_length
= length
;
2475 /* Offset is always 0, either we're the first location part, in which
2476 case we're reading content from the start of the argument, or we're
2477 passing the address of a reference argument, so 0. */
2481 /* Update AINFO, which describes an argument that should be passed or
2482 returned using the integer ABI. The argloc fields within AINFO are
2483 updated to describe the location in which the argument will be passed to
2484 a function, or returned from a function.
2486 The CINFO structure contains the ongoing call information, the holds
2487 information such as which argument registers are remaining to be
2488 assigned to parameter, and how much memory has been used by parameters
2491 By examining the state of CINFO a suitable location can be selected,
2492 and assigned to AINFO. */
2495 riscv_call_arg_scalar_int (struct riscv_arg_info
*ainfo
,
2496 struct riscv_call_info
*cinfo
)
2498 if (ainfo
->length
> (2 * cinfo
->xlen
))
2500 /* Argument is going to be passed by reference. */
2501 ainfo
->argloc
[0].loc_type
2502 = riscv_arg_info::location::by_ref
;
2503 cinfo
->memory
.ref_offset
2504 = align_up (cinfo
->memory
.ref_offset
, ainfo
->align
);
2505 ainfo
->argloc
[0].loc_data
.offset
= cinfo
->memory
.ref_offset
;
2506 cinfo
->memory
.ref_offset
+= ainfo
->length
;
2507 ainfo
->argloc
[0].c_length
= ainfo
->length
;
2509 /* The second location for this argument is given over to holding the
2510 address of the by-reference data. Pass 0 for the offset as this
2511 is not part of the actual argument value. */
2512 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
2515 riscv_assign_stack_location (&ainfo
->argloc
[1],
2516 &cinfo
->memory
, cinfo
->xlen
,
2521 int len
= std::min (ainfo
->length
, cinfo
->xlen
);
2522 int align
= std::max (ainfo
->align
, cinfo
->xlen
);
2524 /* Unnamed arguments in registers that require 2*XLEN alignment are
2525 passed in an aligned register pair. */
2526 if (ainfo
->is_unnamed
&& (align
== cinfo
->xlen
* 2)
2527 && cinfo
->int_regs
.next_regnum
& 1)
2528 cinfo
->int_regs
.next_regnum
++;
2530 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
2531 &cinfo
->int_regs
, len
, 0))
2532 riscv_assign_stack_location (&ainfo
->argloc
[0],
2533 &cinfo
->memory
, len
, align
);
2535 if (len
< ainfo
->length
)
2537 len
= ainfo
->length
- len
;
2538 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
2539 &cinfo
->int_regs
, len
,
2541 riscv_assign_stack_location (&ainfo
->argloc
[1],
2542 &cinfo
->memory
, len
, cinfo
->xlen
);
2547 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
2548 is being passed with the floating point ABI. */
2551 riscv_call_arg_scalar_float (struct riscv_arg_info
*ainfo
,
2552 struct riscv_call_info
*cinfo
)
2554 if (ainfo
->length
> cinfo
->flen
|| ainfo
->is_unnamed
)
2555 return riscv_call_arg_scalar_int (ainfo
, cinfo
);
2558 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
2561 return riscv_call_arg_scalar_int (ainfo
, cinfo
);
2565 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
2566 is a complex floating point argument, and is therefore handled
2567 differently to other argument types. */
2570 riscv_call_arg_complex_float (struct riscv_arg_info
*ainfo
,
2571 struct riscv_call_info
*cinfo
)
2573 if (ainfo
->length
<= (2 * cinfo
->flen
)
2574 && riscv_arg_regs_available (&cinfo
->float_regs
) >= 2
2575 && !ainfo
->is_unnamed
)
2578 int len
= ainfo
->length
/ 2;
2580 result
= riscv_assign_reg_location (&ainfo
->argloc
[0],
2581 &cinfo
->float_regs
, len
, 0);
2582 gdb_assert (result
);
2584 result
= riscv_assign_reg_location (&ainfo
->argloc
[1],
2585 &cinfo
->float_regs
, len
, len
);
2586 gdb_assert (result
);
2589 return riscv_call_arg_scalar_int (ainfo
, cinfo
);
2592 /* A structure used for holding information about a structure type within
2593 the inferior program. The RiscV ABI has special rules for handling some
2594 structures with a single field or with two fields. The counting of
2595 fields here is done after flattening out all nested structures. */
2597 class riscv_struct_info
2600 riscv_struct_info ()
2601 : m_number_of_fields (0),
2602 m_types
{ nullptr, nullptr },
2608 /* Analyse TYPE descending into nested structures, count the number of
2609 scalar fields and record the types of the first two fields found. */
2610 void analyse (struct type
*type
)
2612 analyse_inner (type
, 0);
2615 /* The number of scalar fields found in the analysed type. This is
2616 currently only accurate if the value returned is 0, 1, or 2 as the
2617 analysis stops counting when the number of fields is 3. This is
2618 because the RiscV ABI only has special cases for 1 or 2 fields,
2619 anything else we just don't care about. */
2620 int number_of_fields () const
2621 { return m_number_of_fields
; }
2623 /* Return the type for scalar field INDEX within the analysed type. Will
2624 return nullptr if there is no field at that index. Only INDEX values
2625 0 and 1 can be requested as the RiscV ABI only has special cases for
2626 structures with 1 or 2 fields. */
2627 struct type
*field_type (int index
) const
2629 gdb_assert (index
< (sizeof (m_types
) / sizeof (m_types
[0])));
2630 return m_types
[index
];
2633 /* Return the offset of scalar field INDEX within the analysed type. Will
2634 return 0 if there is no field at that index. Only INDEX values 0 and
2635 1 can be requested as the RiscV ABI only has special cases for
2636 structures with 1 or 2 fields. */
2637 int field_offset (int index
) const
2639 gdb_assert (index
< (sizeof (m_offsets
) / sizeof (m_offsets
[0])));
2640 return m_offsets
[index
];
2644 /* The number of scalar fields found within the structure after recursing
2645 into nested structures. */
2646 int m_number_of_fields
;
2648 /* The types of the first two scalar fields found within the structure
2649 after recursing into nested structures. */
2650 struct type
*m_types
[2];
2652 /* The offsets of the first two scalar fields found within the structure
2653 after recursing into nested structures. */
2656 /* Recursive core for ANALYSE, the OFFSET parameter tracks the byte
2657 offset from the start of the top level structure being analysed. */
2658 void analyse_inner (struct type
*type
, int offset
);
2661 /* See description in class declaration. */
2664 riscv_struct_info::analyse_inner (struct type
*type
, int offset
)
2666 unsigned int count
= type
->num_fields ();
2669 for (i
= 0; i
< count
; ++i
)
2671 if (type
->field (i
).loc_kind () != FIELD_LOC_KIND_BITPOS
)
2674 struct type
*field_type
= type
->field (i
).type ();
2675 field_type
= check_typedef (field_type
);
2677 = offset
+ type
->field (i
).loc_bitpos () / TARGET_CHAR_BIT
;
2679 switch (field_type
->code ())
2681 case TYPE_CODE_STRUCT
:
2682 analyse_inner (field_type
, field_offset
);
2686 /* RiscV only flattens out structures. Anything else does not
2687 need to be flattened, we just record the type, and when we
2688 look at the analysis results we'll realise this is not a
2689 structure we can special case, and pass the structure in
2691 if (m_number_of_fields
< 2)
2693 m_types
[m_number_of_fields
] = field_type
;
2694 m_offsets
[m_number_of_fields
] = field_offset
;
2696 m_number_of_fields
++;
2700 /* RiscV only has special handling for structures with 1 or 2 scalar
2701 fields, any more than that and the structure is just passed in
2702 memory. We can safely drop out early when we find 3 or more
2705 if (m_number_of_fields
> 2)
2710 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
2711 is a structure. Small structures on RiscV have some special case
2712 handling in order that the structure might be passed in register.
2713 Larger structures are passed in memory. After assigning location
2714 information to AINFO, CINFO will have been updated. */
2717 riscv_call_arg_struct (struct riscv_arg_info
*ainfo
,
2718 struct riscv_call_info
*cinfo
)
2720 if (riscv_arg_regs_available (&cinfo
->float_regs
) >= 1)
2722 struct riscv_struct_info sinfo
;
2724 sinfo
.analyse (ainfo
->type
);
2725 if (sinfo
.number_of_fields () == 1
2726 && sinfo
.field_type(0)->code () == TYPE_CODE_COMPLEX
)
2728 /* The following is similar to RISCV_CALL_ARG_COMPLEX_FLOAT,
2729 except we use the type of the complex field instead of the
2730 type from AINFO, and the first location might be at a non-zero
2732 if (TYPE_LENGTH (sinfo
.field_type (0)) <= (2 * cinfo
->flen
)
2733 && riscv_arg_regs_available (&cinfo
->float_regs
) >= 2
2734 && !ainfo
->is_unnamed
)
2737 int len
= TYPE_LENGTH (sinfo
.field_type (0)) / 2;
2738 int offset
= sinfo
.field_offset (0);
2740 result
= riscv_assign_reg_location (&ainfo
->argloc
[0],
2741 &cinfo
->float_regs
, len
,
2743 gdb_assert (result
);
2745 result
= riscv_assign_reg_location (&ainfo
->argloc
[1],
2746 &cinfo
->float_regs
, len
,
2748 gdb_assert (result
);
2751 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2755 if (sinfo
.number_of_fields () == 1
2756 && sinfo
.field_type(0)->code () == TYPE_CODE_FLT
)
2758 /* The following is similar to RISCV_CALL_ARG_SCALAR_FLOAT,
2759 except we use the type of the first scalar field instead of
2760 the type from AINFO. Also the location might be at a non-zero
2762 if (TYPE_LENGTH (sinfo
.field_type (0)) > cinfo
->flen
2763 || ainfo
->is_unnamed
)
2764 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2767 int offset
= sinfo
.field_offset (0);
2768 int len
= TYPE_LENGTH (sinfo
.field_type (0));
2770 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
2773 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2778 if (sinfo
.number_of_fields () == 2
2779 && sinfo
.field_type(0)->code () == TYPE_CODE_FLT
2780 && TYPE_LENGTH (sinfo
.field_type (0)) <= cinfo
->flen
2781 && sinfo
.field_type(1)->code () == TYPE_CODE_FLT
2782 && TYPE_LENGTH (sinfo
.field_type (1)) <= cinfo
->flen
2783 && riscv_arg_regs_available (&cinfo
->float_regs
) >= 2)
2785 int len0
= TYPE_LENGTH (sinfo
.field_type (0));
2786 int offset
= sinfo
.field_offset (0);
2787 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
2788 &cinfo
->float_regs
, len0
, offset
))
2789 error (_("failed during argument setup"));
2791 int len1
= TYPE_LENGTH (sinfo
.field_type (1));
2792 offset
= sinfo
.field_offset (1);
2793 gdb_assert (len1
<= (TYPE_LENGTH (ainfo
->type
)
2794 - TYPE_LENGTH (sinfo
.field_type (0))));
2796 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
2799 error (_("failed during argument setup"));
2803 if (sinfo
.number_of_fields () == 2
2804 && riscv_arg_regs_available (&cinfo
->int_regs
) >= 1
2805 && (sinfo
.field_type(0)->code () == TYPE_CODE_FLT
2806 && TYPE_LENGTH (sinfo
.field_type (0)) <= cinfo
->flen
2807 && is_integral_type (sinfo
.field_type (1))
2808 && TYPE_LENGTH (sinfo
.field_type (1)) <= cinfo
->xlen
))
2810 int len0
= TYPE_LENGTH (sinfo
.field_type (0));
2811 int offset
= sinfo
.field_offset (0);
2812 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
2813 &cinfo
->float_regs
, len0
, offset
))
2814 error (_("failed during argument setup"));
2816 int len1
= TYPE_LENGTH (sinfo
.field_type (1));
2817 offset
= sinfo
.field_offset (1);
2818 gdb_assert (len1
<= cinfo
->xlen
);
2819 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
2820 &cinfo
->int_regs
, len1
, offset
))
2821 error (_("failed during argument setup"));
2825 if (sinfo
.number_of_fields () == 2
2826 && riscv_arg_regs_available (&cinfo
->int_regs
) >= 1
2827 && (is_integral_type (sinfo
.field_type (0))
2828 && TYPE_LENGTH (sinfo
.field_type (0)) <= cinfo
->xlen
2829 && sinfo
.field_type(1)->code () == TYPE_CODE_FLT
2830 && TYPE_LENGTH (sinfo
.field_type (1)) <= cinfo
->flen
))
2832 int len0
= TYPE_LENGTH (sinfo
.field_type (0));
2833 int len1
= TYPE_LENGTH (sinfo
.field_type (1));
2835 gdb_assert (len0
<= cinfo
->xlen
);
2836 gdb_assert (len1
<= cinfo
->flen
);
2838 int offset
= sinfo
.field_offset (0);
2839 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
2840 &cinfo
->int_regs
, len0
, offset
))
2841 error (_("failed during argument setup"));
2843 offset
= sinfo
.field_offset (1);
2844 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
2847 error (_("failed during argument setup"));
2853 /* Non of the structure flattening cases apply, so we just pass using
2855 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2858 /* Assign a location to call (or return) argument AINFO, the location is
2859 selected from CINFO which holds information about what call argument
2860 locations are available for use next. The TYPE is the type of the
2861 argument being passed, this information is recorded into AINFO (along
2862 with some additional information derived from the type). IS_UNNAMED
2863 is true if this is an unnamed (stdarg) argument, this info is also
2864 recorded into AINFO.
2866 After assigning a location to AINFO, CINFO will have been updated. */
2869 riscv_arg_location (struct gdbarch
*gdbarch
,
2870 struct riscv_arg_info
*ainfo
,
2871 struct riscv_call_info
*cinfo
,
2872 struct type
*type
, bool is_unnamed
)
2875 ainfo
->length
= TYPE_LENGTH (ainfo
->type
);
2876 ainfo
->align
= type_align (ainfo
->type
);
2877 ainfo
->is_unnamed
= is_unnamed
;
2878 ainfo
->contents
= nullptr;
2879 ainfo
->argloc
[0].c_length
= 0;
2880 ainfo
->argloc
[1].c_length
= 0;
2882 switch (ainfo
->type
->code ())
2885 case TYPE_CODE_BOOL
:
2886 case TYPE_CODE_CHAR
:
2887 case TYPE_CODE_RANGE
:
2888 case TYPE_CODE_ENUM
:
2890 case TYPE_CODE_FIXED_POINT
:
2891 if (ainfo
->length
<= cinfo
->xlen
)
2893 ainfo
->type
= builtin_type (gdbarch
)->builtin_long
;
2894 ainfo
->length
= cinfo
->xlen
;
2896 else if (ainfo
->length
<= (2 * cinfo
->xlen
))
2898 ainfo
->type
= builtin_type (gdbarch
)->builtin_long_long
;
2899 ainfo
->length
= 2 * cinfo
->xlen
;
2902 /* Recalculate the alignment requirement. */
2903 ainfo
->align
= type_align (ainfo
->type
);
2904 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2908 riscv_call_arg_scalar_float (ainfo
, cinfo
);
2911 case TYPE_CODE_COMPLEX
:
2912 riscv_call_arg_complex_float (ainfo
, cinfo
);
2915 case TYPE_CODE_STRUCT
:
2916 riscv_call_arg_struct (ainfo
, cinfo
);
2920 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2925 /* Used for printing debug information about the call argument location in
2926 INFO to STREAM. The addresses in SP_REFS and SP_ARGS are the base
2927 addresses for the location of pass-by-reference and
2928 arguments-on-the-stack memory areas. */
2931 riscv_print_arg_location (ui_file
*stream
, struct gdbarch
*gdbarch
,
2932 struct riscv_arg_info
*info
,
2933 CORE_ADDR sp_refs
, CORE_ADDR sp_args
)
2935 gdb_printf (stream
, "type: '%s', length: 0x%x, alignment: 0x%x",
2936 TYPE_SAFE_NAME (info
->type
), info
->length
, info
->align
);
2937 switch (info
->argloc
[0].loc_type
)
2939 case riscv_arg_info::location::in_reg
:
2941 (stream
, ", register %s",
2942 gdbarch_register_name (gdbarch
, info
->argloc
[0].loc_data
.regno
));
2943 if (info
->argloc
[0].c_length
< info
->length
)
2945 switch (info
->argloc
[1].loc_type
)
2947 case riscv_arg_info::location::in_reg
:
2949 (stream
, ", register %s",
2950 gdbarch_register_name (gdbarch
,
2951 info
->argloc
[1].loc_data
.regno
));
2954 case riscv_arg_info::location::on_stack
:
2955 gdb_printf (stream
, ", on stack at offset 0x%x",
2956 info
->argloc
[1].loc_data
.offset
);
2959 case riscv_arg_info::location::by_ref
:
2961 /* The second location should never be a reference, any
2962 argument being passed by reference just places its address
2963 in the first location and is done. */
2964 error (_("invalid argument location"));
2968 if (info
->argloc
[1].c_offset
> info
->argloc
[0].c_length
)
2969 gdb_printf (stream
, " (offset 0x%x)",
2970 info
->argloc
[1].c_offset
);
2974 case riscv_arg_info::location::on_stack
:
2975 gdb_printf (stream
, ", on stack at offset 0x%x",
2976 info
->argloc
[0].loc_data
.offset
);
2979 case riscv_arg_info::location::by_ref
:
2981 (stream
, ", by reference, data at offset 0x%x (%s)",
2982 info
->argloc
[0].loc_data
.offset
,
2983 core_addr_to_string (sp_refs
+ info
->argloc
[0].loc_data
.offset
));
2984 if (info
->argloc
[1].loc_type
2985 == riscv_arg_info::location::in_reg
)
2987 (stream
, ", address in register %s",
2988 gdbarch_register_name (gdbarch
, info
->argloc
[1].loc_data
.regno
));
2991 gdb_assert (info
->argloc
[1].loc_type
2992 == riscv_arg_info::location::on_stack
);
2994 (stream
, ", address on stack at offset 0x%x (%s)",
2995 info
->argloc
[1].loc_data
.offset
,
2996 core_addr_to_string (sp_args
+ info
->argloc
[1].loc_data
.offset
));
3001 gdb_assert_not_reached ("unknown argument location type");
3005 /* Wrapper around REGCACHE->cooked_write. Places the LEN bytes of DATA
3006 into a buffer that is at least as big as the register REGNUM, padding
3007 out the DATA with either 0x00, or 0xff. For floating point registers
3008 0xff is used, for everyone else 0x00 is used. */
3011 riscv_regcache_cooked_write (int regnum
, const gdb_byte
*data
, int len
,
3012 struct regcache
*regcache
, int flen
)
3014 gdb_byte tmp
[sizeof (ULONGEST
)];
3016 /* FP values in FP registers must be NaN-boxed. */
3017 if (riscv_is_fp_regno_p (regnum
) && len
< flen
)
3018 memset (tmp
, -1, sizeof (tmp
));
3020 memset (tmp
, 0, sizeof (tmp
));
3021 memcpy (tmp
, data
, len
);
3022 regcache
->cooked_write (regnum
, tmp
);
3025 /* Implement the push dummy call gdbarch callback. */
3028 riscv_push_dummy_call (struct gdbarch
*gdbarch
,
3029 struct value
*function
,
3030 struct regcache
*regcache
,
3033 struct value
**args
,
3035 function_call_return_method return_method
,
3036 CORE_ADDR struct_addr
)
3039 CORE_ADDR sp_args
, sp_refs
;
3040 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3042 struct riscv_arg_info
*arg_info
=
3043 (struct riscv_arg_info
*) alloca (nargs
* sizeof (struct riscv_arg_info
));
3045 struct riscv_call_info
call_info (gdbarch
);
3049 struct type
*ftype
= check_typedef (value_type (function
));
3051 if (ftype
->code () == TYPE_CODE_PTR
)
3052 ftype
= check_typedef (ftype
->target_type ());
3054 /* We'll use register $a0 if we're returning a struct. */
3055 if (return_method
== return_method_struct
)
3056 ++call_info
.int_regs
.next_regnum
;
3058 for (i
= 0; i
< nargs
; ++i
)
3060 struct value
*arg_value
;
3061 struct type
*arg_type
;
3062 struct riscv_arg_info
*info
= &arg_info
[i
];
3064 arg_value
= args
[i
];
3065 arg_type
= check_typedef (value_type (arg_value
));
3067 riscv_arg_location (gdbarch
, info
, &call_info
, arg_type
,
3068 ftype
->has_varargs () && i
>= ftype
->num_fields ());
3070 if (info
->type
!= arg_type
)
3071 arg_value
= value_cast (info
->type
, arg_value
);
3072 info
->contents
= value_contents (arg_value
).data ();
3075 /* Adjust the stack pointer and align it. */
3076 sp
= sp_refs
= align_down (sp
- call_info
.memory
.ref_offset
, SP_ALIGNMENT
);
3077 sp
= sp_args
= align_down (sp
- call_info
.memory
.arg_offset
, SP_ALIGNMENT
);
3079 if (riscv_debug_infcall
> 0)
3081 gdb_printf (gdb_stdlog
, "dummy call args:\n");
3082 gdb_printf (gdb_stdlog
, ": floating point ABI %s in use\n",
3083 (riscv_has_fp_abi (gdbarch
) ? "is" : "is not"));
3084 gdb_printf (gdb_stdlog
, ": xlen: %d\n: flen: %d\n",
3085 call_info
.xlen
, call_info
.flen
);
3086 if (return_method
== return_method_struct
)
3087 gdb_printf (gdb_stdlog
,
3088 "[*] struct return pointer in register $A0\n");
3089 for (i
= 0; i
< nargs
; ++i
)
3091 struct riscv_arg_info
*info
= &arg_info
[i
];
3093 gdb_printf (gdb_stdlog
, "[%2d] ", i
);
3094 riscv_print_arg_location (gdb_stdlog
, gdbarch
, info
, sp_refs
, sp_args
);
3095 gdb_printf (gdb_stdlog
, "\n");
3097 if (call_info
.memory
.arg_offset
> 0
3098 || call_info
.memory
.ref_offset
> 0)
3100 gdb_printf (gdb_stdlog
, " Original sp: %s\n",
3101 core_addr_to_string (osp
));
3102 gdb_printf (gdb_stdlog
, "Stack required (for args): 0x%x\n",
3103 call_info
.memory
.arg_offset
);
3104 gdb_printf (gdb_stdlog
, "Stack required (for refs): 0x%x\n",
3105 call_info
.memory
.ref_offset
);
3106 gdb_printf (gdb_stdlog
, " Stack allocated: %s\n",
3107 core_addr_to_string_nz (osp
- sp
));
3111 /* Now load the argument into registers, or onto the stack. */
3113 if (return_method
== return_method_struct
)
3115 gdb_byte buf
[sizeof (LONGEST
)];
3117 store_unsigned_integer (buf
, call_info
.xlen
, byte_order
, struct_addr
);
3118 regcache
->cooked_write (RISCV_A0_REGNUM
, buf
);
3121 for (i
= 0; i
< nargs
; ++i
)
3124 int second_arg_length
= 0;
3125 const gdb_byte
*second_arg_data
;
3126 struct riscv_arg_info
*info
= &arg_info
[i
];
3128 gdb_assert (info
->length
> 0);
3130 switch (info
->argloc
[0].loc_type
)
3132 case riscv_arg_info::location::in_reg
:
3134 gdb_assert (info
->argloc
[0].c_length
<= info
->length
);
3136 riscv_regcache_cooked_write (info
->argloc
[0].loc_data
.regno
,
3138 + info
->argloc
[0].c_offset
),
3139 info
->argloc
[0].c_length
,
3140 regcache
, call_info
.flen
);
3142 (((info
->argloc
[0].c_length
+ info
->argloc
[0].c_offset
) < info
->length
)
3143 ? info
->argloc
[1].c_length
: 0);
3144 second_arg_data
= info
->contents
+ info
->argloc
[1].c_offset
;
3148 case riscv_arg_info::location::on_stack
:
3149 dst
= sp_args
+ info
->argloc
[0].loc_data
.offset
;
3150 write_memory (dst
, info
->contents
, info
->length
);
3151 second_arg_length
= 0;
3154 case riscv_arg_info::location::by_ref
:
3155 dst
= sp_refs
+ info
->argloc
[0].loc_data
.offset
;
3156 write_memory (dst
, info
->contents
, info
->length
);
3158 second_arg_length
= call_info
.xlen
;
3159 second_arg_data
= (gdb_byte
*) &dst
;
3163 gdb_assert_not_reached ("unknown argument location type");
3166 if (second_arg_length
> 0)
3168 switch (info
->argloc
[1].loc_type
)
3170 case riscv_arg_info::location::in_reg
:
3172 gdb_assert ((riscv_is_fp_regno_p (info
->argloc
[1].loc_data
.regno
)
3173 && second_arg_length
<= call_info
.flen
)
3174 || second_arg_length
<= call_info
.xlen
);
3175 riscv_regcache_cooked_write (info
->argloc
[1].loc_data
.regno
,
3178 regcache
, call_info
.flen
);
3182 case riscv_arg_info::location::on_stack
:
3186 arg_addr
= sp_args
+ info
->argloc
[1].loc_data
.offset
;
3187 write_memory (arg_addr
, second_arg_data
, second_arg_length
);
3191 case riscv_arg_info::location::by_ref
:
3193 /* The second location should never be a reference, any
3194 argument being passed by reference just places its address
3195 in the first location and is done. */
3196 error (_("invalid argument location"));
3202 /* Set the dummy return value to bp_addr.
3203 A dummy breakpoint will be setup to execute the call. */
3205 if (riscv_debug_infcall
> 0)
3206 gdb_printf (gdb_stdlog
, ": writing $ra = %s\n",
3207 core_addr_to_string (bp_addr
));
3208 regcache_cooked_write_unsigned (regcache
, RISCV_RA_REGNUM
, bp_addr
);
3210 /* Finally, update the stack pointer. */
3212 if (riscv_debug_infcall
> 0)
3213 gdb_printf (gdb_stdlog
, ": writing $sp = %s\n",
3214 core_addr_to_string (sp
));
3215 regcache_cooked_write_unsigned (regcache
, RISCV_SP_REGNUM
, sp
);
3220 /* Implement the return_value gdbarch method. */
3222 static enum return_value_convention
3223 riscv_return_value (struct gdbarch
*gdbarch
,
3224 struct value
*function
,
3226 struct regcache
*regcache
,
3228 const gdb_byte
*writebuf
)
3230 struct riscv_call_info
call_info (gdbarch
);
3231 struct riscv_arg_info info
;
3232 struct type
*arg_type
;
3234 arg_type
= check_typedef (type
);
3235 riscv_arg_location (gdbarch
, &info
, &call_info
, arg_type
, false);
3237 if (riscv_debug_infcall
> 0)
3239 gdb_printf (gdb_stdlog
, "riscv return value:\n");
3240 gdb_printf (gdb_stdlog
, "[R] ");
3241 riscv_print_arg_location (gdb_stdlog
, gdbarch
, &info
, 0, 0);
3242 gdb_printf (gdb_stdlog
, "\n");
3245 if (readbuf
!= nullptr || writebuf
!= nullptr)
3247 unsigned int arg_len
;
3248 struct value
*abi_val
;
3249 gdb_byte
*old_readbuf
= nullptr;
3252 /* We only do one thing at a time. */
3253 gdb_assert (readbuf
== nullptr || writebuf
== nullptr);
3255 /* In some cases the argument is not returned as the declared type,
3256 and we need to cast to or from the ABI type in order to
3257 correctly access the argument. When writing to the machine we
3258 do the cast here, when reading from the machine the cast occurs
3259 later, after extracting the value. As the ABI type can be
3260 larger than the declared type, then the read or write buffers
3261 passed in might be too small. Here we ensure that we are using
3262 buffers of sufficient size. */
3263 if (writebuf
!= nullptr)
3265 struct value
*arg_val
;
3267 if (is_fixed_point_type (arg_type
))
3269 /* Convert the argument to the type used to pass
3270 the return value, but being careful to preserve
3271 the fact that the value needs to be returned
3275 unscaled
.read (gdb::make_array_view (writebuf
,
3276 TYPE_LENGTH (arg_type
)),
3277 type_byte_order (arg_type
),
3278 arg_type
->is_unsigned ());
3279 abi_val
= allocate_value (info
.type
);
3280 unscaled
.write (value_contents_raw (abi_val
),
3281 type_byte_order (info
.type
),
3282 info
.type
->is_unsigned ());
3286 arg_val
= value_from_contents (arg_type
, writebuf
);
3287 abi_val
= value_cast (info
.type
, arg_val
);
3289 writebuf
= value_contents_raw (abi_val
).data ();
3293 abi_val
= allocate_value (info
.type
);
3294 old_readbuf
= readbuf
;
3295 readbuf
= value_contents_raw (abi_val
).data ();
3297 arg_len
= TYPE_LENGTH (info
.type
);
3299 switch (info
.argloc
[0].loc_type
)
3301 /* Return value in register(s). */
3302 case riscv_arg_info::location::in_reg
:
3304 regnum
= info
.argloc
[0].loc_data
.regno
;
3305 gdb_assert (info
.argloc
[0].c_length
<= arg_len
);
3306 gdb_assert (info
.argloc
[0].c_length
3307 <= register_size (gdbarch
, regnum
));
3311 gdb_byte
*ptr
= readbuf
+ info
.argloc
[0].c_offset
;
3312 regcache
->cooked_read_part (regnum
, 0,
3313 info
.argloc
[0].c_length
,
3319 const gdb_byte
*ptr
= writebuf
+ info
.argloc
[0].c_offset
;
3320 riscv_regcache_cooked_write (regnum
, ptr
,
3321 info
.argloc
[0].c_length
,
3322 regcache
, call_info
.flen
);
3325 /* A return value in register can have a second part in a
3327 if (info
.argloc
[1].c_length
> 0)
3329 switch (info
.argloc
[1].loc_type
)
3331 case riscv_arg_info::location::in_reg
:
3332 regnum
= info
.argloc
[1].loc_data
.regno
;
3334 gdb_assert ((info
.argloc
[0].c_length
3335 + info
.argloc
[1].c_length
) <= arg_len
);
3336 gdb_assert (info
.argloc
[1].c_length
3337 <= register_size (gdbarch
, regnum
));
3341 readbuf
+= info
.argloc
[1].c_offset
;
3342 regcache
->cooked_read_part (regnum
, 0,
3343 info
.argloc
[1].c_length
,
3350 = writebuf
+ info
.argloc
[1].c_offset
;
3351 riscv_regcache_cooked_write
3352 (regnum
, ptr
, info
.argloc
[1].c_length
,
3353 regcache
, call_info
.flen
);
3357 case riscv_arg_info::location::by_ref
:
3358 case riscv_arg_info::location::on_stack
:
3360 error (_("invalid argument location"));
3367 /* Return value by reference will have its address in A0. */
3368 case riscv_arg_info::location::by_ref
:
3372 regcache_cooked_read_unsigned (regcache
, RISCV_A0_REGNUM
,
3374 if (readbuf
!= nullptr)
3375 read_memory (addr
, readbuf
, info
.length
);
3376 if (writebuf
!= nullptr)
3377 write_memory (addr
, writebuf
, info
.length
);
3381 case riscv_arg_info::location::on_stack
:
3383 error (_("invalid argument location"));
3387 /* This completes the cast from abi type back to the declared type
3388 in the case that we are reading from the machine. See the
3389 comment at the head of this block for more details. */
3390 if (readbuf
!= nullptr)
3392 struct value
*arg_val
;
3394 if (is_fixed_point_type (arg_type
))
3396 /* Convert abi_val to the actual return type, but
3397 being careful to preserve the fact that abi_val
3401 unscaled
.read (value_contents (abi_val
),
3402 type_byte_order (info
.type
),
3403 info
.type
->is_unsigned ());
3404 arg_val
= allocate_value (arg_type
);
3405 unscaled
.write (value_contents_raw (arg_val
),
3406 type_byte_order (arg_type
),
3407 arg_type
->is_unsigned ());
3410 arg_val
= value_cast (arg_type
, abi_val
);
3411 memcpy (old_readbuf
, value_contents_raw (arg_val
).data (),
3412 TYPE_LENGTH (arg_type
));
3416 switch (info
.argloc
[0].loc_type
)
3418 case riscv_arg_info::location::in_reg
:
3419 return RETURN_VALUE_REGISTER_CONVENTION
;
3420 case riscv_arg_info::location::by_ref
:
3421 return RETURN_VALUE_ABI_PRESERVES_ADDRESS
;
3422 case riscv_arg_info::location::on_stack
:
3424 error (_("invalid argument location"));
3428 /* Implement the frame_align gdbarch method. */
3431 riscv_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
3433 return align_down (addr
, 16);
3436 /* Generate, or return the cached frame cache for the RiscV frame
3439 static struct riscv_unwind_cache
*
3440 riscv_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3442 CORE_ADDR pc
, start_addr
;
3443 struct riscv_unwind_cache
*cache
;
3444 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3447 if ((*this_cache
) != NULL
)
3448 return (struct riscv_unwind_cache
*) *this_cache
;
3450 cache
= FRAME_OBSTACK_ZALLOC (struct riscv_unwind_cache
);
3451 cache
->regs
= trad_frame_alloc_saved_regs (this_frame
);
3452 (*this_cache
) = cache
;
3454 /* Scan the prologue, filling in the cache. */
3455 start_addr
= get_frame_func (this_frame
);
3456 pc
= get_frame_pc (this_frame
);
3457 riscv_scan_prologue (gdbarch
, start_addr
, pc
, cache
);
3459 /* We can now calculate the frame base address. */
3461 = (get_frame_register_unsigned (this_frame
, cache
->frame_base_reg
)
3462 + cache
->frame_base_offset
);
3463 if (riscv_debug_unwinder
)
3464 gdb_printf (gdb_stdlog
, "Frame base is %s ($%s + 0x%x)\n",
3465 core_addr_to_string (cache
->frame_base
),
3466 gdbarch_register_name (gdbarch
,
3467 cache
->frame_base_reg
),
3468 cache
->frame_base_offset
);
3470 /* The prologue scanner sets the address of registers stored to the stack
3471 as the offset of that register from the frame base. The prologue
3472 scanner doesn't know the actual frame base value, and so is unable to
3473 compute the exact address. We do now know the frame base value, so
3474 update the address of registers stored to the stack. */
3475 numregs
= gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
3476 for (regno
= 0; regno
< numregs
; ++regno
)
3478 if (cache
->regs
[regno
].is_addr ())
3479 cache
->regs
[regno
].set_addr (cache
->regs
[regno
].addr ()
3480 + cache
->frame_base
);
3483 /* The previous $pc can be found wherever the $ra value can be found.
3484 The previous $ra value is gone, this would have been stored be the
3485 previous frame if required. */
3486 cache
->regs
[gdbarch_pc_regnum (gdbarch
)] = cache
->regs
[RISCV_RA_REGNUM
];
3487 cache
->regs
[RISCV_RA_REGNUM
].set_unknown ();
3489 /* Build the frame id. */
3490 cache
->this_id
= frame_id_build (cache
->frame_base
, start_addr
);
3492 /* The previous $sp value is the frame base value. */
3493 cache
->regs
[gdbarch_sp_regnum (gdbarch
)].set_value (cache
->frame_base
);
3498 /* Implement the this_id callback for RiscV frame unwinder. */
3501 riscv_frame_this_id (struct frame_info
*this_frame
,
3502 void **prologue_cache
,
3503 struct frame_id
*this_id
)
3505 struct riscv_unwind_cache
*cache
;
3509 cache
= riscv_frame_cache (this_frame
, prologue_cache
);
3510 *this_id
= cache
->this_id
;
3512 catch (const gdb_exception_error
&ex
)
3514 /* Ignore errors, this leaves the frame id as the predefined outer
3515 frame id which terminates the backtrace at this point. */
3519 /* Implement the prev_register callback for RiscV frame unwinder. */
3521 static struct value
*
3522 riscv_frame_prev_register (struct frame_info
*this_frame
,
3523 void **prologue_cache
,
3526 struct riscv_unwind_cache
*cache
;
3528 cache
= riscv_frame_cache (this_frame
, prologue_cache
);
3529 return trad_frame_get_prev_register (this_frame
, cache
->regs
, regnum
);
3532 /* Structure defining the RiscV normal frame unwind functions. Since we
3533 are the fallback unwinder (DWARF unwinder is used first), we use the
3534 default frame sniffer, which always accepts the frame. */
3536 static const struct frame_unwind riscv_frame_unwind
=
3538 /*.name =*/ "riscv prologue",
3539 /*.type =*/ NORMAL_FRAME
,
3540 /*.stop_reason =*/ default_frame_unwind_stop_reason
,
3541 /*.this_id =*/ riscv_frame_this_id
,
3542 /*.prev_register =*/ riscv_frame_prev_register
,
3543 /*.unwind_data =*/ NULL
,
3544 /*.sniffer =*/ default_frame_sniffer
,
3545 /*.dealloc_cache =*/ NULL
,
3546 /*.prev_arch =*/ NULL
,
3549 /* Extract a set of required target features out of ABFD. If ABFD is
3550 nullptr then a RISCV_GDBARCH_FEATURES is returned in its default state. */
3552 static struct riscv_gdbarch_features
3553 riscv_features_from_bfd (const bfd
*abfd
)
3555 struct riscv_gdbarch_features features
;
3557 /* Now try to improve on the defaults by looking at the binary we are
3558 going to execute. We assume the user knows what they are doing and
3559 that the target will match the binary. Remember, this code path is
3560 only used at all if the target hasn't given us a description, so this
3561 is really a last ditched effort to do something sane before giving
3563 if (abfd
!= nullptr && bfd_get_flavour (abfd
) == bfd_target_elf_flavour
)
3565 unsigned char eclass
= elf_elfheader (abfd
)->e_ident
[EI_CLASS
];
3566 int e_flags
= elf_elfheader (abfd
)->e_flags
;
3568 if (eclass
== ELFCLASS32
)
3570 else if (eclass
== ELFCLASS64
)
3573 internal_error (__FILE__
, __LINE__
,
3574 _("unknown ELF header class %d"), eclass
);
3576 if (e_flags
& EF_RISCV_FLOAT_ABI_DOUBLE
)
3578 else if (e_flags
& EF_RISCV_FLOAT_ABI_SINGLE
)
3581 if (e_flags
& EF_RISCV_RVE
)
3583 if (features
.xlen
== 8)
3585 warning (_("64-bit ELF with RV32E flag set! Assuming 32-bit"));
3588 features
.embedded
= true;
3595 /* Find a suitable default target description. Use the contents of INFO,
3596 specifically the bfd object being executed, to guide the selection of a
3597 suitable default target description. */
3599 static const struct target_desc
*
3600 riscv_find_default_target_description (const struct gdbarch_info info
)
3602 /* Extract desired feature set from INFO. */
3603 struct riscv_gdbarch_features features
3604 = riscv_features_from_bfd (info
.abfd
);
3606 /* If the XLEN field is still 0 then we got nothing useful from INFO.BFD,
3607 maybe there was no bfd object. In this case we fall back to a minimal
3608 useful target with no floating point, the x-register size is selected
3609 based on the architecture from INFO. */
3610 if (features
.xlen
== 0)
3611 features
.xlen
= info
.bfd_arch_info
->bits_per_word
== 32 ? 4 : 8;
3613 /* Now build a target description based on the feature set. */
3614 return riscv_lookup_target_description (features
);
3617 /* Add all the RISC-V specific register groups into GDBARCH. */
3620 riscv_add_reggroups (struct gdbarch
*gdbarch
)
3622 reggroup_add (gdbarch
, csr_reggroup
);
3625 /* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
3628 riscv_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
3630 if (reg
< RISCV_DWARF_REGNUM_X31
)
3631 return RISCV_ZERO_REGNUM
+ (reg
- RISCV_DWARF_REGNUM_X0
);
3633 else if (reg
< RISCV_DWARF_REGNUM_F31
)
3634 return RISCV_FIRST_FP_REGNUM
+ (reg
- RISCV_DWARF_REGNUM_F0
);
3636 else if (reg
>= RISCV_DWARF_FIRST_CSR
&& reg
<= RISCV_DWARF_LAST_CSR
)
3637 return RISCV_FIRST_CSR_REGNUM
+ (reg
- RISCV_DWARF_FIRST_CSR
);
3639 else if (reg
>= RISCV_DWARF_REGNUM_V0
&& reg
<= RISCV_DWARF_REGNUM_V31
)
3640 return RISCV_V0_REGNUM
+ (reg
- RISCV_DWARF_REGNUM_V0
);
3645 /* Implement the gcc_target_options method. We have to select the arch and abi
3646 from the feature info. We have enough feature info to select the abi, but
3647 not enough info for the arch given all of the possible architecture
3648 extensions. So choose reasonable defaults for now. */
3651 riscv_gcc_target_options (struct gdbarch
*gdbarch
)
3653 int isa_xlen
= riscv_isa_xlen (gdbarch
);
3654 int isa_flen
= riscv_isa_flen (gdbarch
);
3655 int abi_xlen
= riscv_abi_xlen (gdbarch
);
3656 int abi_flen
= riscv_abi_flen (gdbarch
);
3657 std::string target_options
;
3659 target_options
= "-march=rv";
3661 target_options
+= "64";
3663 target_options
+= "32";
3665 target_options
+= "gc";
3666 else if (isa_flen
== 4)
3667 target_options
+= "imafc";
3669 target_options
+= "imac";
3671 target_options
+= " -mabi=";
3673 target_options
+= "lp64";
3675 target_options
+= "ilp32";
3677 target_options
+= "d";
3678 else if (abi_flen
== 4)
3679 target_options
+= "f";
3681 /* The gdb loader doesn't handle link-time relaxation relocations. */
3682 target_options
+= " -mno-relax";
3684 return target_options
;
3687 /* Call back from tdesc_use_registers, called for each unknown register
3688 found in the target description.
3690 See target-description.h (typedef tdesc_unknown_register_ftype) for a
3691 discussion of the arguments and return values. */
3694 riscv_tdesc_unknown_reg (struct gdbarch
*gdbarch
, tdesc_feature
*feature
,
3695 const char *reg_name
, int possible_regnum
)
3697 /* At one point in time GDB had an incorrect default target description
3698 that duplicated the fflags, frm, and fcsr registers in both the FPU
3699 and CSR register sets.
3701 Some targets (QEMU) copied these target descriptions into their source
3702 tree, and so we're now stuck working with some versions of QEMU that
3703 declare the same registers twice.
3705 To make matters worse, if GDB tries to read or write to these
3706 registers using the register number assigned in the FPU feature set,
3707 then QEMU will fail to read the register, so we must use the register
3708 number declared in the CSR feature set.
3710 Luckily, GDB scans the FPU feature first, and then the CSR feature,
3711 which means that the CSR feature will be the one we end up using, the
3712 versions of these registers in the FPU feature will appear as unknown
3713 registers and will be passed through to this code.
3715 To prevent these duplicate registers showing up in any of the register
3716 lists, and to prevent GDB every trying to access the FPU feature copies,
3717 we spot the three problematic registers here, and record the register
3718 number that GDB has assigned them. Then in riscv_register_name we will
3719 return no name for the three duplicates, this hides the duplicates from
3721 if (strcmp (tdesc_feature_name (feature
), riscv_freg_feature
.name ()) == 0)
3723 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
3724 int *regnum_ptr
= nullptr;
3726 if (strcmp (reg_name
, "fflags") == 0)
3727 regnum_ptr
= &tdep
->duplicate_fflags_regnum
;
3728 else if (strcmp (reg_name
, "frm") == 0)
3729 regnum_ptr
= &tdep
->duplicate_frm_regnum
;
3730 else if (strcmp (reg_name
, "fcsr") == 0)
3731 regnum_ptr
= &tdep
->duplicate_fcsr_regnum
;
3733 if (regnum_ptr
!= nullptr)
3735 /* This means the register appears more than twice in the target
3736 description. Just let GDB add this as another register.
3737 We'll have duplicates in the register name list, but there's
3738 not much more we can do. */
3739 if (*regnum_ptr
!= -1)
3742 /* Record the number assigned to this register, then return the
3743 number (so it actually gets assigned to this register). */
3744 *regnum_ptr
= possible_regnum
;
3745 return possible_regnum
;
3749 /* Any unknown registers in the CSR feature are recorded within a single
3750 block so we can easily identify these registers when making choices
3751 about register groups in riscv_register_reggroup_p. */
3752 if (strcmp (tdesc_feature_name (feature
), riscv_csr_feature
.name ()) == 0)
3754 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
3755 if (tdep
->unknown_csrs_first_regnum
== -1)
3756 tdep
->unknown_csrs_first_regnum
= possible_regnum
;
3757 gdb_assert (tdep
->unknown_csrs_first_regnum
3758 + tdep
->unknown_csrs_count
== possible_regnum
);
3759 tdep
->unknown_csrs_count
++;
3760 return possible_regnum
;
3763 /* Some other unknown register. Don't assign this a number now, it will
3764 be assigned a number automatically later by the target description
3769 /* Implement the gnu_triplet_regexp method. A single compiler supports both
3770 32-bit and 64-bit code, and may be named riscv32 or riscv64 or (not
3771 recommended) riscv. */
3774 riscv_gnu_triplet_regexp (struct gdbarch
*gdbarch
)
3776 return "riscv(32|64)?";
3779 /* Initialize the current architecture based on INFO. If possible,
3780 re-use an architecture from ARCHES, which is a list of
3781 architectures already created during this debugging session.
3783 Called e.g. at program startup, when reading a core file, and when
3784 reading a binary file. */
3786 static struct gdbarch
*
3787 riscv_gdbarch_init (struct gdbarch_info info
,
3788 struct gdbarch_list
*arches
)
3790 struct gdbarch
*gdbarch
;
3791 struct riscv_gdbarch_features features
;
3792 const struct target_desc
*tdesc
= info
.target_desc
;
3794 /* Ensure we always have a target description. */
3795 if (!tdesc_has_registers (tdesc
))
3796 tdesc
= riscv_find_default_target_description (info
);
3797 gdb_assert (tdesc
!= nullptr);
3799 if (riscv_debug_gdbarch
)
3800 gdb_printf (gdb_stdlog
, "Have got a target description\n");
3802 tdesc_arch_data_up tdesc_data
= tdesc_data_alloc ();
3803 std::vector
<riscv_pending_register_alias
> pending_aliases
;
3805 bool valid_p
= (riscv_xreg_feature
.check (tdesc
, tdesc_data
.get (),
3806 &pending_aliases
, &features
)
3807 && riscv_freg_feature
.check (tdesc
, tdesc_data
.get (),
3808 &pending_aliases
, &features
)
3809 && riscv_virtual_feature
.check (tdesc
, tdesc_data
.get (),
3810 &pending_aliases
, &features
)
3811 && riscv_csr_feature
.check (tdesc
, tdesc_data
.get (),
3812 &pending_aliases
, &features
)
3813 && riscv_vector_feature
.check (tdesc
, tdesc_data
.get (),
3814 &pending_aliases
, &features
));
3817 if (riscv_debug_gdbarch
)
3818 gdb_printf (gdb_stdlog
, "Target description is not valid\n");
3822 if (tdesc_found_register (tdesc_data
.get (), RISCV_CSR_FFLAGS_REGNUM
))
3823 features
.has_fflags_reg
= true;
3824 if (tdesc_found_register (tdesc_data
.get (), RISCV_CSR_FRM_REGNUM
))
3825 features
.has_frm_reg
= true;
3826 if (tdesc_found_register (tdesc_data
.get (), RISCV_CSR_FCSR_REGNUM
))
3827 features
.has_fcsr_reg
= true;
3829 /* Have a look at what the supplied (if any) bfd object requires of the
3830 target, then check that this matches with what the target is
3832 struct riscv_gdbarch_features abi_features
3833 = riscv_features_from_bfd (info
.abfd
);
3835 /* If the ABI_FEATURES xlen is 0 then this indicates we got no useful abi
3836 features from the INFO object. In this case we just treat the
3837 hardware features as defining the abi. */
3838 if (abi_features
.xlen
== 0)
3839 abi_features
= features
;
3841 /* In theory a binary compiled for RV32 could run on an RV64 target,
3842 however, this has not been tested in GDB yet, so for now we require
3843 that the requested xlen match the targets xlen. */
3844 if (abi_features
.xlen
!= features
.xlen
)
3845 error (_("bfd requires xlen %d, but target has xlen %d"),
3846 abi_features
.xlen
, features
.xlen
);
3847 /* We do support running binaries compiled for 32-bit float on targets
3848 with 64-bit float, so we only complain if the binary requires more
3849 than the target has available. */
3850 if (abi_features
.flen
> features
.flen
)
3851 error (_("bfd requires flen %d, but target has flen %d"),
3852 abi_features
.flen
, features
.flen
);
3854 /* Find a candidate among the list of pre-declared architectures. */
3855 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
3857 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
3859 /* Check that the feature set of the ARCHES matches the feature set
3860 we are looking for. If it doesn't then we can't reuse this
3862 riscv_gdbarch_tdep
*other_tdep
3863 = gdbarch_tdep
<riscv_gdbarch_tdep
> (arches
->gdbarch
);
3865 if (other_tdep
->isa_features
!= features
3866 || other_tdep
->abi_features
!= abi_features
)
3873 return arches
->gdbarch
;
3875 /* None found, so create a new architecture from the information provided. */
3876 riscv_gdbarch_tdep
*tdep
= new riscv_gdbarch_tdep
;
3877 gdbarch
= gdbarch_alloc (&info
, tdep
);
3878 tdep
->isa_features
= features
;
3879 tdep
->abi_features
= abi_features
;
3881 /* Target data types. */
3882 set_gdbarch_short_bit (gdbarch
, 16);
3883 set_gdbarch_int_bit (gdbarch
, 32);
3884 set_gdbarch_long_bit (gdbarch
, riscv_isa_xlen (gdbarch
) * 8);
3885 set_gdbarch_long_long_bit (gdbarch
, 64);
3886 set_gdbarch_float_bit (gdbarch
, 32);
3887 set_gdbarch_double_bit (gdbarch
, 64);
3888 set_gdbarch_long_double_bit (gdbarch
, 128);
3889 set_gdbarch_long_double_format (gdbarch
, floatformats_ieee_quad
);
3890 set_gdbarch_ptr_bit (gdbarch
, riscv_isa_xlen (gdbarch
) * 8);
3891 set_gdbarch_char_signed (gdbarch
, 0);
3892 set_gdbarch_type_align (gdbarch
, riscv_type_align
);
3894 /* Information about the target architecture. */
3895 set_gdbarch_return_value (gdbarch
, riscv_return_value
);
3896 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, riscv_breakpoint_kind_from_pc
);
3897 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, riscv_sw_breakpoint_from_kind
);
3898 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
3900 /* Functions to analyze frames. */
3901 set_gdbarch_skip_prologue (gdbarch
, riscv_skip_prologue
);
3902 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
3903 set_gdbarch_frame_align (gdbarch
, riscv_frame_align
);
3905 /* Functions handling dummy frames. */
3906 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
3907 set_gdbarch_push_dummy_code (gdbarch
, riscv_push_dummy_code
);
3908 set_gdbarch_push_dummy_call (gdbarch
, riscv_push_dummy_call
);
3910 /* Frame unwinders. Use DWARF debug info if available, otherwise use our own
3912 dwarf2_append_unwinders (gdbarch
);
3913 frame_unwind_append_unwinder (gdbarch
, &riscv_frame_unwind
);
3915 /* Register architecture. */
3916 riscv_add_reggroups (gdbarch
);
3918 /* Internal <-> external register number maps. */
3919 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, riscv_dwarf_reg_to_regnum
);
3921 /* We reserve all possible register numbers for the known registers.
3922 This means the target description mechanism will add any target
3923 specific registers after this number. This helps make debugging GDB
3924 just a little easier. */
3925 set_gdbarch_num_regs (gdbarch
, RISCV_LAST_REGNUM
+ 1);
3927 /* Some specific register numbers GDB likes to know about. */
3928 set_gdbarch_sp_regnum (gdbarch
, RISCV_SP_REGNUM
);
3929 set_gdbarch_pc_regnum (gdbarch
, RISCV_PC_REGNUM
);
3931 set_gdbarch_print_registers_info (gdbarch
, riscv_print_registers_info
);
3933 set_tdesc_pseudo_register_name (gdbarch
, riscv_pseudo_register_name
);
3934 set_tdesc_pseudo_register_type (gdbarch
, riscv_pseudo_register_type
);
3935 set_tdesc_pseudo_register_reggroup_p (gdbarch
,
3936 riscv_pseudo_register_reggroup_p
);
3937 set_gdbarch_pseudo_register_read (gdbarch
, riscv_pseudo_register_read
);
3938 set_gdbarch_pseudo_register_write (gdbarch
, riscv_pseudo_register_write
);
3940 /* Finalise the target description registers. */
3941 tdesc_use_registers (gdbarch
, tdesc
, std::move (tdesc_data
),
3942 riscv_tdesc_unknown_reg
);
3944 /* Calculate the number of pseudo registers we need. The fflags and frm
3945 registers are sub-fields of the fcsr CSR register (csr3). However,
3946 these registers can also be accessed directly as separate CSR
3947 registers (fflags is csr1, and frm is csr2). And so, some targets
3948 might choose to offer direct access to all three registers in the
3949 target description, while other targets might choose to only offer
3952 As we scan the target description we spot which of fcsr, fflags, and
3953 frm are available. If fcsr is available but either of fflags and/or
3954 frm are not available, then we add pseudo-registers to provide the
3955 missing functionality.
3957 This has to be done after the call to tdesc_use_registers as we don't
3958 know the final register number until after that call, and the pseudo
3959 register numbers need to be after the physical registers. */
3960 int num_pseudo_regs
= 0;
3961 int next_pseudo_regnum
= gdbarch_num_regs (gdbarch
);
3963 if (features
.has_fflags_reg
)
3964 tdep
->fflags_regnum
= RISCV_CSR_FFLAGS_REGNUM
;
3965 else if (features
.has_fcsr_reg
)
3967 tdep
->fflags_regnum
= next_pseudo_regnum
;
3968 pending_aliases
.emplace_back ("csr1", (void *) &tdep
->fflags_regnum
);
3969 next_pseudo_regnum
++;
3973 if (features
.has_frm_reg
)
3974 tdep
->frm_regnum
= RISCV_CSR_FRM_REGNUM
;
3975 else if (features
.has_fcsr_reg
)
3977 tdep
->frm_regnum
= next_pseudo_regnum
;
3978 pending_aliases
.emplace_back ("csr2", (void *) &tdep
->frm_regnum
);
3979 next_pseudo_regnum
++;
3983 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudo_regs
);
3985 /* Override the register type callback setup by the target description
3986 mechanism. This allows us to provide special type for floating point
3988 set_gdbarch_register_type (gdbarch
, riscv_register_type
);
3990 /* Override the register name callback setup by the target description
3991 mechanism. This allows us to force our preferred names for the
3992 registers, no matter what the target description called them. */
3993 set_gdbarch_register_name (gdbarch
, riscv_register_name
);
3995 /* Tell GDB which RISC-V registers are read-only. */
3996 set_gdbarch_cannot_store_register (gdbarch
, riscv_cannot_store_register
);
3998 /* Override the register group callback setup by the target description
3999 mechanism. This allows us to force registers into the groups we
4000 want, ignoring what the target tells us. */
4001 set_gdbarch_register_reggroup_p (gdbarch
, riscv_register_reggroup_p
);
4003 /* Create register aliases for alternative register names. We only
4004 create aliases for registers which were mentioned in the target
4006 for (const auto &alias
: pending_aliases
)
4007 alias
.create (gdbarch
);
4009 /* Compile command hooks. */
4010 set_gdbarch_gcc_target_options (gdbarch
, riscv_gcc_target_options
);
4011 set_gdbarch_gnu_triplet_regexp (gdbarch
, riscv_gnu_triplet_regexp
);
4013 /* Disassembler options support. */
4014 set_gdbarch_valid_disassembler_options (gdbarch
,
4015 disassembler_options_riscv ());
4016 set_gdbarch_disassembler_options (gdbarch
, &riscv_disassembler_options
);
4018 /* Hook in OS ABI-specific overrides, if they have been registered. */
4019 gdbarch_init_osabi (info
, gdbarch
);
4021 register_riscv_ravenscar_ops (gdbarch
);
4026 /* This decodes the current instruction and determines the address of the
4027 next instruction. */
4030 riscv_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
4032 struct gdbarch
*gdbarch
= regcache
->arch ();
4033 const riscv_gdbarch_tdep
*tdep
4034 = gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
4035 struct riscv_insn insn
;
4038 insn
.decode (gdbarch
, pc
);
4039 next_pc
= pc
+ insn
.length ();
4041 if (insn
.opcode () == riscv_insn::JAL
)
4042 next_pc
= pc
+ insn
.imm_signed ();
4043 else if (insn
.opcode () == riscv_insn::JALR
)
4046 regcache
->cooked_read (insn
.rs1 (), &source
);
4047 next_pc
= (source
+ insn
.imm_signed ()) & ~(CORE_ADDR
) 0x1;
4049 else if (insn
.opcode () == riscv_insn::BEQ
)
4052 regcache
->cooked_read (insn
.rs1 (), &src1
);
4053 regcache
->cooked_read (insn
.rs2 (), &src2
);
4055 next_pc
= pc
+ insn
.imm_signed ();
4057 else if (insn
.opcode () == riscv_insn::BNE
)
4060 regcache
->cooked_read (insn
.rs1 (), &src1
);
4061 regcache
->cooked_read (insn
.rs2 (), &src2
);
4063 next_pc
= pc
+ insn
.imm_signed ();
4065 else if (insn
.opcode () == riscv_insn::BLT
)
4068 regcache
->cooked_read (insn
.rs1 (), &src1
);
4069 regcache
->cooked_read (insn
.rs2 (), &src2
);
4071 next_pc
= pc
+ insn
.imm_signed ();
4073 else if (insn
.opcode () == riscv_insn::BGE
)
4076 regcache
->cooked_read (insn
.rs1 (), &src1
);
4077 regcache
->cooked_read (insn
.rs2 (), &src2
);
4079 next_pc
= pc
+ insn
.imm_signed ();
4081 else if (insn
.opcode () == riscv_insn::BLTU
)
4083 ULONGEST src1
, src2
;
4084 regcache
->cooked_read (insn
.rs1 (), &src1
);
4085 regcache
->cooked_read (insn
.rs2 (), &src2
);
4087 next_pc
= pc
+ insn
.imm_signed ();
4089 else if (insn
.opcode () == riscv_insn::BGEU
)
4091 ULONGEST src1
, src2
;
4092 regcache
->cooked_read (insn
.rs1 (), &src1
);
4093 regcache
->cooked_read (insn
.rs2 (), &src2
);
4095 next_pc
= pc
+ insn
.imm_signed ();
4097 else if (insn
.opcode () == riscv_insn::ECALL
)
4099 if (tdep
->syscall_next_pc
!= nullptr)
4100 next_pc
= tdep
->syscall_next_pc (get_current_frame ());
4106 /* We can't put a breakpoint in the middle of a lr/sc atomic sequence, so look
4107 for the end of the sequence and put the breakpoint there. */
4110 riscv_next_pc_atomic_sequence (struct regcache
*regcache
, CORE_ADDR pc
,
4113 struct gdbarch
*gdbarch
= regcache
->arch ();
4114 struct riscv_insn insn
;
4115 CORE_ADDR cur_step_pc
= pc
;
4116 CORE_ADDR last_addr
= 0;
4118 /* First instruction has to be a load reserved. */
4119 insn
.decode (gdbarch
, cur_step_pc
);
4120 if (insn
.opcode () != riscv_insn::LR
)
4122 cur_step_pc
= cur_step_pc
+ insn
.length ();
4124 /* Next instruction should be branch to exit. */
4125 insn
.decode (gdbarch
, cur_step_pc
);
4126 if (insn
.opcode () != riscv_insn::BNE
)
4128 last_addr
= cur_step_pc
+ insn
.imm_signed ();
4129 cur_step_pc
= cur_step_pc
+ insn
.length ();
4131 /* Next instruction should be store conditional. */
4132 insn
.decode (gdbarch
, cur_step_pc
);
4133 if (insn
.opcode () != riscv_insn::SC
)
4135 cur_step_pc
= cur_step_pc
+ insn
.length ();
4137 /* Next instruction should be branch to start. */
4138 insn
.decode (gdbarch
, cur_step_pc
);
4139 if (insn
.opcode () != riscv_insn::BNE
)
4141 if (pc
!= (cur_step_pc
+ insn
.imm_signed ()))
4143 cur_step_pc
= cur_step_pc
+ insn
.length ();
4145 /* We should now be at the end of the sequence. */
4146 if (cur_step_pc
!= last_addr
)
4149 *next_pc
= cur_step_pc
;
4153 /* This is called just before we want to resume the inferior, if we want to
4154 single-step it but there is no hardware or kernel single-step support. We
4155 find the target of the coming instruction and breakpoint it. */
4157 std::vector
<CORE_ADDR
>
4158 riscv_software_single_step (struct regcache
*regcache
)
4160 CORE_ADDR pc
, next_pc
;
4162 pc
= regcache_read_pc (regcache
);
4164 if (riscv_next_pc_atomic_sequence (regcache
, pc
, &next_pc
))
4167 next_pc
= riscv_next_pc (regcache
, pc
);
4172 /* Create RISC-V specific reggroups. */
4175 riscv_init_reggroups ()
4177 csr_reggroup
= reggroup_new ("csr", USER_REGGROUP
);
4180 /* See riscv-tdep.h. */
4183 riscv_supply_regset (const struct regset
*regset
,
4184 struct regcache
*regcache
, int regnum
,
4185 const void *regs
, size_t len
)
4187 regcache
->supply_regset (regset
, regnum
, regs
, len
);
4189 if (regnum
== -1 || regnum
== RISCV_ZERO_REGNUM
)
4190 regcache
->raw_supply_zeroed (RISCV_ZERO_REGNUM
);
4192 struct gdbarch
*gdbarch
= regcache
->arch ();
4193 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
4196 || regnum
== tdep
->fflags_regnum
4197 || regnum
== tdep
->frm_regnum
)
4199 int fcsr_regnum
= RISCV_CSR_FCSR_REGNUM
;
4201 /* Ensure that FCSR has been read into REGCACHE. */
4203 regcache
->supply_regset (regset
, fcsr_regnum
, regs
, len
);
4205 /* Grab the FCSR value if it is now in the regcache. We must check
4206 the status first as, if the register was not supplied by REGSET,
4207 this call will trigger a recursive attempt to fetch the
4209 if (regcache
->get_register_status (fcsr_regnum
) == REG_VALID
)
4211 /* If we have an fcsr register then we should have fflags and frm
4212 too, either provided by the target, or provided as a pseudo
4214 gdb_assert (tdep
->fflags_regnum
>= 0);
4215 gdb_assert (tdep
->frm_regnum
>= 0);
4218 regcache
->raw_read (fcsr_regnum
, &fcsr_val
);
4220 /* Extract the fflags and frm values. */
4221 ULONGEST fflags_val
= fcsr_val
& 0x1f;
4222 ULONGEST frm_val
= (fcsr_val
>> 5) & 0x7;
4224 /* And supply these if needed. We can only supply real
4225 registers, so don't try to supply fflags or frm if they are
4226 implemented as pseudo-registers. */
4227 if ((regnum
== -1 || regnum
== tdep
->fflags_regnum
)
4228 && tdep
->fflags_regnum
< gdbarch_num_regs (gdbarch
))
4229 regcache
->raw_supply_integer (tdep
->fflags_regnum
,
4230 (gdb_byte
*) &fflags_val
,
4231 sizeof (fflags_val
),
4232 /* is_signed */ false);
4234 if ((regnum
== -1 || regnum
== tdep
->frm_regnum
)
4235 && tdep
->frm_regnum
< gdbarch_num_regs (gdbarch
))
4236 regcache
->raw_supply_integer (tdep
->frm_regnum
,
4237 (gdb_byte
*)&frm_val
,
4238 sizeof (fflags_val
),
4239 /* is_signed */ false);
4244 void _initialize_riscv_tdep ();
4246 _initialize_riscv_tdep ()
4248 riscv_init_reggroups ();
4250 gdbarch_register (bfd_arch_riscv
, riscv_gdbarch_init
, NULL
);
4252 /* Add root prefix command for all "set debug riscv" and "show debug
4254 add_setshow_prefix_cmd ("riscv", no_class
,
4255 _("RISC-V specific debug commands."),
4256 _("RISC-V specific debug commands."),
4257 &setdebugriscvcmdlist
, &showdebugriscvcmdlist
,
4258 &setdebuglist
, &showdebuglist
);
4260 add_setshow_zuinteger_cmd ("breakpoints", class_maintenance
,
4261 &riscv_debug_breakpoints
, _("\
4262 Set riscv breakpoint debugging."), _("\
4263 Show riscv breakpoint debugging."), _("\
4264 When non-zero, print debugging information for the riscv specific parts\n\
4265 of the breakpoint mechanism."),
4267 show_riscv_debug_variable
,
4268 &setdebugriscvcmdlist
, &showdebugriscvcmdlist
);
4270 add_setshow_zuinteger_cmd ("infcall", class_maintenance
,
4271 &riscv_debug_infcall
, _("\
4272 Set riscv inferior call debugging."), _("\
4273 Show riscv inferior call debugging."), _("\
4274 When non-zero, print debugging information for the riscv specific parts\n\
4275 of the inferior call mechanism."),
4277 show_riscv_debug_variable
,
4278 &setdebugriscvcmdlist
, &showdebugriscvcmdlist
);
4280 add_setshow_zuinteger_cmd ("unwinder", class_maintenance
,
4281 &riscv_debug_unwinder
, _("\
4282 Set riscv stack unwinding debugging."), _("\
4283 Show riscv stack unwinding debugging."), _("\
4284 When non-zero, print debugging information for the riscv specific parts\n\
4285 of the stack unwinding mechanism."),
4287 show_riscv_debug_variable
,
4288 &setdebugriscvcmdlist
, &showdebugriscvcmdlist
);
4290 add_setshow_zuinteger_cmd ("gdbarch", class_maintenance
,
4291 &riscv_debug_gdbarch
, _("\
4292 Set riscv gdbarch initialisation debugging."), _("\
4293 Show riscv gdbarch initialisation debugging."), _("\
4294 When non-zero, print debugging information for the riscv gdbarch\n\
4295 initialisation process."),
4297 show_riscv_debug_variable
,
4298 &setdebugriscvcmdlist
, &showdebugriscvcmdlist
);
4300 /* Add root prefix command for all "set riscv" and "show riscv" commands. */
4301 add_setshow_prefix_cmd ("riscv", no_class
,
4302 _("RISC-V specific commands."),
4303 _("RISC-V specific commands."),
4304 &setriscvcmdlist
, &showriscvcmdlist
,
4305 &setlist
, &showlist
);
4308 use_compressed_breakpoints
= AUTO_BOOLEAN_AUTO
;
4309 add_setshow_auto_boolean_cmd ("use-compressed-breakpoints", no_class
,
4310 &use_compressed_breakpoints
,
4312 Set debugger's use of compressed breakpoints."), _(" \
4313 Show debugger's use of compressed breakpoints."), _("\
4314 Debugging compressed code requires compressed breakpoints to be used. If\n\
4315 left to 'auto' then gdb will use them if the existing instruction is a\n\
4316 compressed instruction. If that doesn't give the correct behavior, then\n\
4317 this option can be used."),
4319 show_use_compressed_breakpoints
,