1 /* Target-dependent code for the RISC-V architecture, for GDB.
3 Copyright (C) 2018-2023 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
32 #include "arch-utils.h"
35 #include "riscv-tdep.h"
36 #include "reggroups.h"
37 #include "opcode/riscv.h"
38 #include "elf/riscv.h"
42 #include "frame-unwind.h"
43 #include "frame-base.h"
44 #include "trad-frame.h"
46 #include "floatformat.h"
48 #include "target-descriptions.h"
49 #include "dwarf2/frame.h"
50 #include "user-regs.h"
52 #include "gdbsupport/common-defs.h"
53 #include "opcode/riscv-opc.h"
54 #include "cli/cli-decode.h"
55 #include "observable.h"
56 #include "prologue-value.h"
57 #include "arch/riscv.h"
58 #include "riscv-ravenscar-thread.h"
60 /* The stack must be 16-byte aligned. */
61 #define SP_ALIGNMENT 16
63 /* The biggest alignment that the target supports. */
64 #define BIGGEST_ALIGNMENT 16
66 /* Define a series of is_XXX_insn functions to check if the value INSN
67 is an instance of instruction XXX. */
68 #define DECLARE_INSN(INSN_NAME, INSN_MATCH, INSN_MASK) \
69 static inline bool is_ ## INSN_NAME ## _insn (long insn) \
71 return (insn & INSN_MASK) == INSN_MATCH; \
73 #include "opcode/riscv-opc.h"
76 /* When this is set to non-zero debugging information about breakpoint
77 kinds will be printed. */
79 static unsigned int riscv_debug_breakpoints
= 0;
81 /* When this is set to non-zero debugging information about inferior calls
84 static unsigned int riscv_debug_infcall
= 0;
86 /* When this is set to non-zero debugging information about stack unwinding
89 static unsigned int riscv_debug_unwinder
= 0;
91 /* When this is set to non-zero debugging information about gdbarch
92 initialisation will be printed. */
94 static unsigned int riscv_debug_gdbarch
= 0;
96 /* The names of the RISC-V target description features. */
97 const char *riscv_feature_name_csr
= "org.gnu.gdb.riscv.csr";
98 static const char *riscv_feature_name_cpu
= "org.gnu.gdb.riscv.cpu";
99 static const char *riscv_feature_name_fpu
= "org.gnu.gdb.riscv.fpu";
100 static const char *riscv_feature_name_virtual
= "org.gnu.gdb.riscv.virtual";
101 static const char *riscv_feature_name_vector
= "org.gnu.gdb.riscv.vector";
103 /* The current set of options to be passed to the disassembler. */
104 static char *riscv_disassembler_options
;
106 /* Cached information about a frame. */
108 struct riscv_unwind_cache
110 /* The register from which we can calculate the frame base. This is
111 usually $sp or $fp. */
114 /* The offset from the current value in register FRAME_BASE_REG to the
115 actual frame base address. */
116 int frame_base_offset
;
118 /* Information about previous register values. */
119 trad_frame_saved_reg
*regs
;
121 /* The id for this frame. */
122 struct frame_id this_id
;
124 /* The base (stack) address for this frame. This is the stack pointer
125 value on entry to this frame before any adjustments are made. */
126 CORE_ADDR frame_base
;
129 /* RISC-V specific register group for CSRs. */
131 static const reggroup
*csr_reggroup
= nullptr;
133 /* Callback function for user_reg_add. */
135 static struct value
*
136 value_of_riscv_user_reg (frame_info_ptr frame
, const void *baton
)
138 const int *reg_p
= (const int *) baton
;
139 return value_of_register (*reg_p
, frame
);
142 /* Information about a register alias that needs to be set up for this
143 target. These are collected when the target's XML description is
144 analysed, and then processed later, once the gdbarch has been created. */
146 class riscv_pending_register_alias
151 riscv_pending_register_alias (const char *name
, const void *baton
)
156 /* Convert this into a user register for GDBARCH. */
158 void create (struct gdbarch
*gdbarch
) const
160 user_reg_add (gdbarch
, m_name
, value_of_riscv_user_reg
, m_baton
);
164 /* The name for this alias. */
167 /* The baton value for passing to user_reg_add. This must point to some
168 data that will live for at least as long as the gdbarch object to
169 which the user register is attached. */
173 /* A set of registers that we expect to find in a tdesc_feature. These
174 are use in RISCV_GDBARCH_INIT when processing the target description. */
176 struct riscv_register_feature
178 explicit riscv_register_feature (const char *feature_name
)
179 : m_feature_name (feature_name
)
182 riscv_register_feature () = delete;
183 DISABLE_COPY_AND_ASSIGN (riscv_register_feature
);
185 /* Information for a single register. */
188 /* The GDB register number for this register. */
191 /* List of names for this register. The first name in this list is the
192 preferred name, the name GDB should use when describing this
194 std::vector
<const char *> names
;
196 /* Look in FEATURE for a register with a name from this classes names
197 list. If the register is found then register its number with
198 TDESC_DATA and add all its aliases to the ALIASES list.
199 PREFER_FIRST_NAME_P is used when deciding which aliases to create. */
200 bool check (struct tdesc_arch_data
*tdesc_data
,
201 const struct tdesc_feature
*feature
,
202 bool prefer_first_name_p
,
203 std::vector
<riscv_pending_register_alias
> *aliases
) const;
206 /* Return the name of this feature. */
207 const char *name () const
208 { return m_feature_name
; }
212 /* Return a target description feature extracted from TDESC for this
213 register feature. Will return nullptr if there is no feature in TDESC
214 with the name M_FEATURE_NAME. */
215 const struct tdesc_feature
*tdesc_feature (const struct target_desc
*tdesc
) const
217 return tdesc_find_feature (tdesc
, name ());
220 /* List of all the registers that we expect that we might find in this
222 std::vector
<struct register_info
> m_registers
;
226 /* The name for this feature. This is the name used to find this feature
227 within the target description. */
228 const char *m_feature_name
;
231 /* See description in the class declaration above. */
234 riscv_register_feature::register_info::check
235 (struct tdesc_arch_data
*tdesc_data
,
236 const struct tdesc_feature
*feature
,
237 bool prefer_first_name_p
,
238 std::vector
<riscv_pending_register_alias
> *aliases
) const
240 for (const char *name
: this->names
)
242 bool found
= tdesc_numbered_register (feature
, tdesc_data
,
246 /* We know that the target description mentions this
247 register. In RISCV_REGISTER_NAME we ensure that GDB
248 always uses the first name for each register, so here we
249 add aliases for all of the remaining names. */
250 int start_index
= prefer_first_name_p
? 1 : 0;
251 for (int i
= start_index
; i
< this->names
.size (); ++i
)
253 const char *alias
= this->names
[i
];
254 if (alias
== name
&& !prefer_first_name_p
)
256 aliases
->emplace_back (alias
, (void *) &this->regnum
);
264 /* Class representing the x-registers feature set. */
266 struct riscv_xreg_feature
: public riscv_register_feature
268 riscv_xreg_feature ()
269 : riscv_register_feature (riscv_feature_name_cpu
)
272 { RISCV_ZERO_REGNUM
+ 0, { "zero", "x0" } },
273 { RISCV_ZERO_REGNUM
+ 1, { "ra", "x1" } },
274 { RISCV_ZERO_REGNUM
+ 2, { "sp", "x2" } },
275 { RISCV_ZERO_REGNUM
+ 3, { "gp", "x3" } },
276 { RISCV_ZERO_REGNUM
+ 4, { "tp", "x4" } },
277 { RISCV_ZERO_REGNUM
+ 5, { "t0", "x5" } },
278 { RISCV_ZERO_REGNUM
+ 6, { "t1", "x6" } },
279 { RISCV_ZERO_REGNUM
+ 7, { "t2", "x7" } },
280 { RISCV_ZERO_REGNUM
+ 8, { "fp", "x8", "s0" } },
281 { RISCV_ZERO_REGNUM
+ 9, { "s1", "x9" } },
282 { RISCV_ZERO_REGNUM
+ 10, { "a0", "x10" } },
283 { RISCV_ZERO_REGNUM
+ 11, { "a1", "x11" } },
284 { RISCV_ZERO_REGNUM
+ 12, { "a2", "x12" } },
285 { RISCV_ZERO_REGNUM
+ 13, { "a3", "x13" } },
286 { RISCV_ZERO_REGNUM
+ 14, { "a4", "x14" } },
287 { RISCV_ZERO_REGNUM
+ 15, { "a5", "x15" } },
288 { RISCV_ZERO_REGNUM
+ 16, { "a6", "x16" } },
289 { RISCV_ZERO_REGNUM
+ 17, { "a7", "x17" } },
290 { RISCV_ZERO_REGNUM
+ 18, { "s2", "x18" } },
291 { RISCV_ZERO_REGNUM
+ 19, { "s3", "x19" } },
292 { RISCV_ZERO_REGNUM
+ 20, { "s4", "x20" } },
293 { RISCV_ZERO_REGNUM
+ 21, { "s5", "x21" } },
294 { RISCV_ZERO_REGNUM
+ 22, { "s6", "x22" } },
295 { RISCV_ZERO_REGNUM
+ 23, { "s7", "x23" } },
296 { RISCV_ZERO_REGNUM
+ 24, { "s8", "x24" } },
297 { RISCV_ZERO_REGNUM
+ 25, { "s9", "x25" } },
298 { RISCV_ZERO_REGNUM
+ 26, { "s10", "x26" } },
299 { RISCV_ZERO_REGNUM
+ 27, { "s11", "x27" } },
300 { RISCV_ZERO_REGNUM
+ 28, { "t3", "x28" } },
301 { RISCV_ZERO_REGNUM
+ 29, { "t4", "x29" } },
302 { RISCV_ZERO_REGNUM
+ 30, { "t5", "x30" } },
303 { RISCV_ZERO_REGNUM
+ 31, { "t6", "x31" } },
304 { RISCV_ZERO_REGNUM
+ 32, { "pc" } }
308 /* Return the preferred name for the register with gdb register number
309 REGNUM, which must be in the inclusive range RISCV_ZERO_REGNUM to
311 const char *register_name (int regnum
) const
313 gdb_assert (regnum
>= RISCV_ZERO_REGNUM
&& regnum
<= m_registers
.size ());
314 return m_registers
[regnum
].names
[0];
317 /* Check this feature within TDESC, record the registers from this
318 feature into TDESC_DATA and update ALIASES and FEATURES. */
319 bool check (const struct target_desc
*tdesc
,
320 struct tdesc_arch_data
*tdesc_data
,
321 std::vector
<riscv_pending_register_alias
> *aliases
,
322 struct riscv_gdbarch_features
*features
) const
324 const struct tdesc_feature
*feature_cpu
= tdesc_feature (tdesc
);
326 if (feature_cpu
== nullptr)
329 bool seen_an_optional_reg_p
= false;
330 for (const auto ®
: m_registers
)
332 bool found
= reg
.check (tdesc_data
, feature_cpu
, true, aliases
);
334 bool is_optional_reg_p
= (reg
.regnum
>= RISCV_ZERO_REGNUM
+ 16
335 && reg
.regnum
< RISCV_ZERO_REGNUM
+ 32);
337 if (!found
&& (!is_optional_reg_p
|| seen_an_optional_reg_p
))
339 else if (found
&& is_optional_reg_p
)
340 seen_an_optional_reg_p
= true;
343 /* Check that all of the core cpu registers have the same bitsize. */
344 int xlen_bitsize
= tdesc_register_bitsize (feature_cpu
, "pc");
347 for (auto &tdesc_reg
: feature_cpu
->registers
)
348 valid_p
&= (tdesc_reg
->bitsize
== xlen_bitsize
);
350 features
->xlen
= (xlen_bitsize
/ 8);
351 features
->embedded
= !seen_an_optional_reg_p
;
357 /* An instance of the x-register feature set. */
359 static const struct riscv_xreg_feature riscv_xreg_feature
;
361 /* Class representing the f-registers feature set. */
363 struct riscv_freg_feature
: public riscv_register_feature
365 riscv_freg_feature ()
366 : riscv_register_feature (riscv_feature_name_fpu
)
369 { RISCV_FIRST_FP_REGNUM
+ 0, { "ft0", "f0" } },
370 { RISCV_FIRST_FP_REGNUM
+ 1, { "ft1", "f1" } },
371 { RISCV_FIRST_FP_REGNUM
+ 2, { "ft2", "f2" } },
372 { RISCV_FIRST_FP_REGNUM
+ 3, { "ft3", "f3" } },
373 { RISCV_FIRST_FP_REGNUM
+ 4, { "ft4", "f4" } },
374 { RISCV_FIRST_FP_REGNUM
+ 5, { "ft5", "f5" } },
375 { RISCV_FIRST_FP_REGNUM
+ 6, { "ft6", "f6" } },
376 { RISCV_FIRST_FP_REGNUM
+ 7, { "ft7", "f7" } },
377 { RISCV_FIRST_FP_REGNUM
+ 8, { "fs0", "f8" } },
378 { RISCV_FIRST_FP_REGNUM
+ 9, { "fs1", "f9" } },
379 { RISCV_FIRST_FP_REGNUM
+ 10, { "fa0", "f10" } },
380 { RISCV_FIRST_FP_REGNUM
+ 11, { "fa1", "f11" } },
381 { RISCV_FIRST_FP_REGNUM
+ 12, { "fa2", "f12" } },
382 { RISCV_FIRST_FP_REGNUM
+ 13, { "fa3", "f13" } },
383 { RISCV_FIRST_FP_REGNUM
+ 14, { "fa4", "f14" } },
384 { RISCV_FIRST_FP_REGNUM
+ 15, { "fa5", "f15" } },
385 { RISCV_FIRST_FP_REGNUM
+ 16, { "fa6", "f16" } },
386 { RISCV_FIRST_FP_REGNUM
+ 17, { "fa7", "f17" } },
387 { RISCV_FIRST_FP_REGNUM
+ 18, { "fs2", "f18" } },
388 { RISCV_FIRST_FP_REGNUM
+ 19, { "fs3", "f19" } },
389 { RISCV_FIRST_FP_REGNUM
+ 20, { "fs4", "f20" } },
390 { RISCV_FIRST_FP_REGNUM
+ 21, { "fs5", "f21" } },
391 { RISCV_FIRST_FP_REGNUM
+ 22, { "fs6", "f22" } },
392 { RISCV_FIRST_FP_REGNUM
+ 23, { "fs7", "f23" } },
393 { RISCV_FIRST_FP_REGNUM
+ 24, { "fs8", "f24" } },
394 { RISCV_FIRST_FP_REGNUM
+ 25, { "fs9", "f25" } },
395 { RISCV_FIRST_FP_REGNUM
+ 26, { "fs10", "f26" } },
396 { RISCV_FIRST_FP_REGNUM
+ 27, { "fs11", "f27" } },
397 { RISCV_FIRST_FP_REGNUM
+ 28, { "ft8", "f28" } },
398 { RISCV_FIRST_FP_REGNUM
+ 29, { "ft9", "f29" } },
399 { RISCV_FIRST_FP_REGNUM
+ 30, { "ft10", "f30" } },
400 { RISCV_FIRST_FP_REGNUM
+ 31, { "ft11", "f31" } },
401 { RISCV_CSR_FFLAGS_REGNUM
, { "fflags", "csr1" } },
402 { RISCV_CSR_FRM_REGNUM
, { "frm", "csr2" } },
403 { RISCV_CSR_FCSR_REGNUM
, { "fcsr", "csr3" } },
407 /* Return the preferred name for the register with gdb register number
408 REGNUM, which must be in the inclusive range RISCV_FIRST_FP_REGNUM to
409 RISCV_LAST_FP_REGNUM. */
410 const char *register_name (int regnum
) const
412 gdb_static_assert (RISCV_LAST_FP_REGNUM
== RISCV_FIRST_FP_REGNUM
+ 31);
413 gdb_assert (regnum
>= RISCV_FIRST_FP_REGNUM
414 && regnum
<= RISCV_LAST_FP_REGNUM
);
415 regnum
-= RISCV_FIRST_FP_REGNUM
;
416 return m_registers
[regnum
].names
[0];
419 /* Check this feature within TDESC, record the registers from this
420 feature into TDESC_DATA and update ALIASES and FEATURES. */
421 bool check (const struct target_desc
*tdesc
,
422 struct tdesc_arch_data
*tdesc_data
,
423 std::vector
<riscv_pending_register_alias
> *aliases
,
424 struct riscv_gdbarch_features
*features
) const
426 const struct tdesc_feature
*feature_fpu
= tdesc_feature (tdesc
);
428 /* It's fine if this feature is missing. Update the architecture
429 feature set and return. */
430 if (feature_fpu
== nullptr)
436 /* Check all of the floating pointer registers are present. We also
437 check that the floating point CSRs are present too, though if these
438 are missing this is not fatal. */
439 for (const auto ®
: m_registers
)
441 bool found
= reg
.check (tdesc_data
, feature_fpu
, true, aliases
);
443 bool is_ctrl_reg_p
= reg
.regnum
> RISCV_LAST_FP_REGNUM
;
445 if (!found
&& !is_ctrl_reg_p
)
449 /* Look through all of the floating point registers (not the FP CSRs
450 though), and check they all have the same bitsize. Use this bitsize
451 to update the feature set for this gdbarch. */
453 for (const auto ®
: m_registers
)
455 /* Stop once we get to the CSRs which are at the end of the
457 if (reg
.regnum
> RISCV_LAST_FP_REGNUM
)
460 int reg_bitsize
= -1;
461 for (const char *name
: reg
.names
)
463 if (tdesc_unnumbered_register (feature_fpu
, name
))
465 reg_bitsize
= tdesc_register_bitsize (feature_fpu
, name
);
469 gdb_assert (reg_bitsize
!= -1);
470 if (fp_bitsize
== -1)
471 fp_bitsize
= reg_bitsize
;
472 else if (fp_bitsize
!= reg_bitsize
)
476 features
->flen
= (fp_bitsize
/ 8);
481 /* An instance of the f-register feature set. */
483 static const struct riscv_freg_feature riscv_freg_feature
;
485 /* Class representing the virtual registers. These are not physical
486 registers on the hardware, but might be available from the target.
487 These are not pseudo registers, reading these really does result in a
488 register read from the target, it is just that there might not be a
489 physical register backing the result. */
491 struct riscv_virtual_feature
: public riscv_register_feature
493 riscv_virtual_feature ()
494 : riscv_register_feature (riscv_feature_name_virtual
)
497 { RISCV_PRIV_REGNUM
, { "priv" } }
501 bool check (const struct target_desc
*tdesc
,
502 struct tdesc_arch_data
*tdesc_data
,
503 std::vector
<riscv_pending_register_alias
> *aliases
,
504 struct riscv_gdbarch_features
*features
) const
506 const struct tdesc_feature
*feature_virtual
= tdesc_feature (tdesc
);
508 /* It's fine if this feature is missing. */
509 if (feature_virtual
== nullptr)
512 /* We don't check the return value from the call to check here, all the
513 registers in this feature are optional. */
514 for (const auto ®
: m_registers
)
515 reg
.check (tdesc_data
, feature_virtual
, true, aliases
);
521 /* An instance of the virtual register feature. */
523 static const struct riscv_virtual_feature riscv_virtual_feature
;
525 /* Class representing the CSR feature. */
527 struct riscv_csr_feature
: public riscv_register_feature
530 : riscv_register_feature (riscv_feature_name_csr
)
533 #define DECLARE_CSR(NAME,VALUE,CLASS,DEFINE_VER,ABORT_VER) \
534 { RISCV_ ## VALUE ## _REGNUM, { # NAME } },
535 #include "opcode/riscv-opc.h"
538 riscv_create_csr_aliases ();
541 bool check (const struct target_desc
*tdesc
,
542 struct tdesc_arch_data
*tdesc_data
,
543 std::vector
<riscv_pending_register_alias
> *aliases
,
544 struct riscv_gdbarch_features
*features
) const
546 const struct tdesc_feature
*feature_csr
= tdesc_feature (tdesc
);
548 /* It's fine if this feature is missing. */
549 if (feature_csr
== nullptr)
552 /* We don't check the return value from the call to check here, all the
553 registers in this feature are optional. */
554 for (const auto ®
: m_registers
)
555 reg
.check (tdesc_data
, feature_csr
, true, aliases
);
562 /* Complete RISCV_CSR_FEATURE, building the CSR alias names and adding them
563 to the name list for each register. */
566 riscv_create_csr_aliases ()
568 for (auto ®
: m_registers
)
570 int csr_num
= reg
.regnum
- RISCV_FIRST_CSR_REGNUM
;
571 gdb::unique_xmalloc_ptr
<char> alias
= xstrprintf ("csr%d", csr_num
);
572 reg
.names
.push_back (alias
.release ());
577 /* An instance of the csr register feature. */
579 static const struct riscv_csr_feature riscv_csr_feature
;
581 /* Class representing the v-registers feature set. */
583 struct riscv_vector_feature
: public riscv_register_feature
585 riscv_vector_feature ()
586 : riscv_register_feature (riscv_feature_name_vector
)
589 { RISCV_V0_REGNUM
+ 0, { "v0" } },
590 { RISCV_V0_REGNUM
+ 1, { "v1" } },
591 { RISCV_V0_REGNUM
+ 2, { "v2" } },
592 { RISCV_V0_REGNUM
+ 3, { "v3" } },
593 { RISCV_V0_REGNUM
+ 4, { "v4" } },
594 { RISCV_V0_REGNUM
+ 5, { "v5" } },
595 { RISCV_V0_REGNUM
+ 6, { "v6" } },
596 { RISCV_V0_REGNUM
+ 7, { "v7" } },
597 { RISCV_V0_REGNUM
+ 8, { "v8" } },
598 { RISCV_V0_REGNUM
+ 9, { "v9" } },
599 { RISCV_V0_REGNUM
+ 10, { "v10" } },
600 { RISCV_V0_REGNUM
+ 11, { "v11" } },
601 { RISCV_V0_REGNUM
+ 12, { "v12" } },
602 { RISCV_V0_REGNUM
+ 13, { "v13" } },
603 { RISCV_V0_REGNUM
+ 14, { "v14" } },
604 { RISCV_V0_REGNUM
+ 15, { "v15" } },
605 { RISCV_V0_REGNUM
+ 16, { "v16" } },
606 { RISCV_V0_REGNUM
+ 17, { "v17" } },
607 { RISCV_V0_REGNUM
+ 18, { "v18" } },
608 { RISCV_V0_REGNUM
+ 19, { "v19" } },
609 { RISCV_V0_REGNUM
+ 20, { "v20" } },
610 { RISCV_V0_REGNUM
+ 21, { "v21" } },
611 { RISCV_V0_REGNUM
+ 22, { "v22" } },
612 { RISCV_V0_REGNUM
+ 23, { "v23" } },
613 { RISCV_V0_REGNUM
+ 24, { "v24" } },
614 { RISCV_V0_REGNUM
+ 25, { "v25" } },
615 { RISCV_V0_REGNUM
+ 26, { "v26" } },
616 { RISCV_V0_REGNUM
+ 27, { "v27" } },
617 { RISCV_V0_REGNUM
+ 28, { "v28" } },
618 { RISCV_V0_REGNUM
+ 29, { "v29" } },
619 { RISCV_V0_REGNUM
+ 30, { "v30" } },
620 { RISCV_V0_REGNUM
+ 31, { "v31" } },
624 /* Return the preferred name for the register with gdb register number
625 REGNUM, which must be in the inclusive range RISCV_V0_REGNUM to
626 RISCV_V0_REGNUM + 31. */
627 const char *register_name (int regnum
) const
629 gdb_assert (regnum
>= RISCV_V0_REGNUM
630 && regnum
<= RISCV_V0_REGNUM
+ 31);
631 regnum
-= RISCV_V0_REGNUM
;
632 return m_registers
[regnum
].names
[0];
635 /* Check this feature within TDESC, record the registers from this
636 feature into TDESC_DATA and update ALIASES and FEATURES. */
637 bool check (const struct target_desc
*tdesc
,
638 struct tdesc_arch_data
*tdesc_data
,
639 std::vector
<riscv_pending_register_alias
> *aliases
,
640 struct riscv_gdbarch_features
*features
) const
642 const struct tdesc_feature
*feature_vector
= tdesc_feature (tdesc
);
644 /* It's fine if this feature is missing. Update the architecture
645 feature set and return. */
646 if (feature_vector
== nullptr)
652 /* Check all of the vector registers are present. */
653 for (const auto ®
: m_registers
)
655 if (!reg
.check (tdesc_data
, feature_vector
, true, aliases
))
659 /* Look through all of the vector registers and check they all have the
660 same bitsize. Use this bitsize to update the feature set for this
662 int vector_bitsize
= -1;
663 for (const auto ®
: m_registers
)
665 int reg_bitsize
= -1;
666 for (const char *name
: reg
.names
)
668 if (tdesc_unnumbered_register (feature_vector
, name
))
670 reg_bitsize
= tdesc_register_bitsize (feature_vector
, name
);
674 gdb_assert (reg_bitsize
!= -1);
675 if (vector_bitsize
== -1)
676 vector_bitsize
= reg_bitsize
;
677 else if (vector_bitsize
!= reg_bitsize
)
681 features
->vlen
= (vector_bitsize
/ 8);
686 /* An instance of the v-register feature set. */
688 static const struct riscv_vector_feature riscv_vector_feature
;
690 /* Controls whether we place compressed breakpoints or not. When in auto
691 mode GDB tries to determine if the target supports compressed
692 breakpoints, and uses them if it does. */
694 static enum auto_boolean use_compressed_breakpoints
;
696 /* The show callback for 'show riscv use-compressed-breakpoints'. */
699 show_use_compressed_breakpoints (struct ui_file
*file
, int from_tty
,
700 struct cmd_list_element
*c
,
704 _("Debugger's use of compressed breakpoints is set "
708 /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
710 static struct cmd_list_element
*setriscvcmdlist
= NULL
;
711 static struct cmd_list_element
*showriscvcmdlist
= NULL
;
713 /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
715 static struct cmd_list_element
*setdebugriscvcmdlist
= NULL
;
716 static struct cmd_list_element
*showdebugriscvcmdlist
= NULL
;
718 /* The show callback for all 'show debug riscv VARNAME' variables. */
721 show_riscv_debug_variable (struct ui_file
*file
, int from_tty
,
722 struct cmd_list_element
*c
,
726 _("RiscV debug variable `%s' is set to: %s\n"),
730 /* See riscv-tdep.h. */
733 riscv_isa_xlen (struct gdbarch
*gdbarch
)
735 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
736 return tdep
->isa_features
.xlen
;
739 /* See riscv-tdep.h. */
742 riscv_abi_xlen (struct gdbarch
*gdbarch
)
744 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
745 return tdep
->abi_features
.xlen
;
748 /* See riscv-tdep.h. */
751 riscv_isa_flen (struct gdbarch
*gdbarch
)
753 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
754 return tdep
->isa_features
.flen
;
757 /* See riscv-tdep.h. */
760 riscv_abi_flen (struct gdbarch
*gdbarch
)
762 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
763 return tdep
->abi_features
.flen
;
766 /* See riscv-tdep.h. */
769 riscv_abi_embedded (struct gdbarch
*gdbarch
)
771 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
772 return tdep
->abi_features
.embedded
;
775 /* Return true if the target for GDBARCH has floating point hardware. */
778 riscv_has_fp_regs (struct gdbarch
*gdbarch
)
780 return (riscv_isa_flen (gdbarch
) > 0);
783 /* Return true if GDBARCH is using any of the floating point hardware ABIs. */
786 riscv_has_fp_abi (struct gdbarch
*gdbarch
)
788 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
789 return tdep
->abi_features
.flen
> 0;
792 /* Return true if REGNO is a floating pointer register. */
795 riscv_is_fp_regno_p (int regno
)
797 return (regno
>= RISCV_FIRST_FP_REGNUM
798 && regno
<= RISCV_LAST_FP_REGNUM
);
801 /* Implement the breakpoint_kind_from_pc gdbarch method. */
804 riscv_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
806 if (use_compressed_breakpoints
== AUTO_BOOLEAN_AUTO
)
808 bool unaligned_p
= false;
811 /* Some targets don't support unaligned reads. The address can only
812 be unaligned if the C extension is supported. So it is safe to
813 use a compressed breakpoint in this case. */
818 /* Read the opcode byte to determine the instruction length. If
819 the read fails this may be because we tried to set the
820 breakpoint at an invalid address, in this case we provide a
821 fake result which will give a breakpoint length of 4.
822 Hopefully when we try to actually insert the breakpoint we
823 will see a failure then too which will be reported to the
825 if (target_read_code (*pcptr
, buf
, 1) == -1)
829 if (riscv_debug_breakpoints
)
831 const char *bp
= (unaligned_p
|| riscv_insn_length (buf
[0]) == 2
832 ? "C.EBREAK" : "EBREAK");
834 gdb_printf (gdb_stdlog
, "Using %s for breakpoint at %s ",
835 bp
, paddress (gdbarch
, *pcptr
));
837 gdb_printf (gdb_stdlog
, "(unaligned address)\n");
839 gdb_printf (gdb_stdlog
, "(instruction length %d)\n",
840 riscv_insn_length (buf
[0]));
842 if (unaligned_p
|| riscv_insn_length (buf
[0]) == 2)
847 else if (use_compressed_breakpoints
== AUTO_BOOLEAN_TRUE
)
853 /* Implement the sw_breakpoint_from_kind gdbarch method. */
855 static const gdb_byte
*
856 riscv_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
858 static const gdb_byte ebreak
[] = { 0x73, 0x00, 0x10, 0x00, };
859 static const gdb_byte c_ebreak
[] = { 0x02, 0x90 };
869 gdb_assert_not_reached ("unhandled breakpoint kind");
873 /* Implement the register_name gdbarch method. This is used instead of
874 the function supplied by calling TDESC_USE_REGISTERS so that we can
875 ensure the preferred names are offered for x-regs and f-regs. */
878 riscv_register_name (struct gdbarch
*gdbarch
, int regnum
)
880 /* Lookup the name through the target description. If we get back NULL
881 then this is an unknown register. If we do get a name back then we
882 look up the registers preferred name below. */
883 const char *name
= tdesc_register_name (gdbarch
, regnum
);
884 gdb_assert (name
!= nullptr);
888 /* We want GDB to use the ABI names for registers even if the target
889 gives us a target description with the architectural name. For
890 example we want to see 'ra' instead of 'x1' whatever the target
891 description called it. */
892 if (regnum
>= RISCV_ZERO_REGNUM
&& regnum
< RISCV_FIRST_FP_REGNUM
)
893 return riscv_xreg_feature
.register_name (regnum
);
895 /* Like with the x-regs we prefer the abi names for the floating point
896 registers. If the target doesn't have floating point registers then
897 the tdesc_register_name call above should have returned an empty
899 if (regnum
>= RISCV_FIRST_FP_REGNUM
&& regnum
<= RISCV_LAST_FP_REGNUM
)
901 gdb_assert (riscv_has_fp_regs (gdbarch
));
902 return riscv_freg_feature
.register_name (regnum
);
905 /* Some targets (QEMU) are reporting these three registers twice, once
906 in the FPU feature, and once in the CSR feature. Both of these read
907 the same underlying state inside the target, but naming the register
908 twice in the target description results in GDB having two registers
909 with the same name, only one of which can ever be accessed, but both
910 will show up in 'info register all'. Unless, we identify the
911 duplicate copies of these registers (in riscv_tdesc_unknown_reg) and
912 then hide the registers here by giving them no name. */
913 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
914 if (tdep
->duplicate_fflags_regnum
== regnum
915 || tdep
->duplicate_frm_regnum
== regnum
916 || tdep
->duplicate_fcsr_regnum
== regnum
)
919 /* The remaining registers are different. For all other registers on the
920 machine we prefer to see the names that the target description
921 provides. This is particularly important for CSRs which might be
922 renamed over time. If GDB keeps track of the "latest" name, but a
923 particular target provides an older name then we don't want to force
924 users to see the newer name in register output.
926 The other case that reaches here are any registers that the target
927 provided that GDB is completely unaware of. For these we have no
928 choice but to accept the target description name.
930 Just accept whatever name TDESC_REGISTER_NAME returned. */
934 /* Implement gdbarch_pseudo_register_read. Read pseudo-register REGNUM
935 from REGCACHE and place the register value into BUF. BUF is sized
936 based on the type of register REGNUM, all of BUF should be written too,
937 the result should be sign or zero extended as appropriate. */
939 static enum register_status
940 riscv_pseudo_register_read (struct gdbarch
*gdbarch
,
941 readable_regcache
*regcache
,
942 int regnum
, gdb_byte
*buf
)
944 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
946 if (regnum
== tdep
->fflags_regnum
|| regnum
== tdep
->frm_regnum
)
949 memset (buf
, 0, register_size (gdbarch
, regnum
));
951 /* Read the first byte of the fcsr register, this contains both frm
953 enum register_status status
954 = regcache
->raw_read_part (RISCV_CSR_FCSR_REGNUM
, 0, 1, buf
);
956 if (status
!= REG_VALID
)
959 /* Extract the appropriate parts. */
960 if (regnum
== tdep
->fflags_regnum
)
962 else if (regnum
== tdep
->frm_regnum
)
963 buf
[0] = (buf
[0] >> 5) & 0x7;
971 /* Implement gdbarch_pseudo_register_write. Write the contents of BUF into
972 pseudo-register REGNUM in REGCACHE. BUF is sized based on the type of
976 riscv_pseudo_register_write (struct gdbarch
*gdbarch
,
977 struct regcache
*regcache
, int regnum
,
980 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
982 if (regnum
== tdep
->fflags_regnum
|| regnum
== tdep
->frm_regnum
)
984 int fcsr_regnum
= RISCV_CSR_FCSR_REGNUM
;
985 gdb_byte raw_buf
[register_size (gdbarch
, fcsr_regnum
)];
987 regcache
->raw_read (fcsr_regnum
, raw_buf
);
989 if (regnum
== tdep
->fflags_regnum
)
990 raw_buf
[0] = (raw_buf
[0] & ~0x1f) | (buf
[0] & 0x1f);
991 else if (regnum
== tdep
->frm_regnum
)
992 raw_buf
[0] = (raw_buf
[0] & ~(0x7 << 5)) | ((buf
[0] & 0x7) << 5);
994 regcache
->raw_write (fcsr_regnum
, raw_buf
);
997 gdb_assert_not_reached ("unknown pseudo register %d", regnum
);
1000 /* Implement the cannot_store_register gdbarch method. The zero register
1001 (x0) is read-only on RISC-V. */
1004 riscv_cannot_store_register (struct gdbarch
*gdbarch
, int regnum
)
1006 return regnum
== RISCV_ZERO_REGNUM
;
1009 /* Construct a type for 64-bit FP registers. */
1011 static struct type
*
1012 riscv_fpreg_d_type (struct gdbarch
*gdbarch
)
1014 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
1016 if (tdep
->riscv_fpreg_d_type
== nullptr)
1018 const struct builtin_type
*bt
= builtin_type (gdbarch
);
1020 /* The type we're building is this: */
1022 union __gdb_builtin_type_fpreg_d
1031 t
= arch_composite_type (gdbarch
,
1032 "__gdb_builtin_type_fpreg_d", TYPE_CODE_UNION
);
1033 append_composite_type_field (t
, "float", bt
->builtin_float
);
1034 append_composite_type_field (t
, "double", bt
->builtin_double
);
1035 t
->set_is_vector (true);
1036 t
->set_name ("builtin_type_fpreg_d");
1037 tdep
->riscv_fpreg_d_type
= t
;
1040 return tdep
->riscv_fpreg_d_type
;
1043 /* Implement the register_type gdbarch method. This is installed as an
1044 for the override setup by TDESC_USE_REGISTERS, for most registers we
1045 delegate the type choice to the target description, but for a few
1046 registers we try to improve the types if the target description has
1047 taken a simplistic approach. */
1049 static struct type
*
1050 riscv_register_type (struct gdbarch
*gdbarch
, int regnum
)
1052 struct type
*type
= tdesc_register_type (gdbarch
, regnum
);
1053 int xlen
= riscv_isa_xlen (gdbarch
);
1055 /* We want to perform some specific type "fixes" in cases where we feel
1056 that we really can do better than the target description. For all
1057 other cases we just return what the target description says. */
1058 if (riscv_is_fp_regno_p (regnum
))
1060 /* This spots the case for RV64 where the double is defined as
1061 either 'ieee_double' or 'float' (which is the generic name that
1062 converts to 'double' on 64-bit). In these cases its better to
1063 present the registers using a union type. */
1064 int flen
= riscv_isa_flen (gdbarch
);
1066 && type
->code () == TYPE_CODE_FLT
1067 && type
->length () == flen
1068 && (strcmp (type
->name (), "builtin_type_ieee_double") == 0
1069 || strcmp (type
->name (), "double") == 0))
1070 type
= riscv_fpreg_d_type (gdbarch
);
1073 if ((regnum
== gdbarch_pc_regnum (gdbarch
)
1074 || regnum
== RISCV_RA_REGNUM
1075 || regnum
== RISCV_FP_REGNUM
1076 || regnum
== RISCV_SP_REGNUM
1077 || regnum
== RISCV_GP_REGNUM
1078 || regnum
== RISCV_TP_REGNUM
)
1079 && type
->code () == TYPE_CODE_INT
1080 && type
->length () == xlen
)
1082 /* This spots the case where some interesting registers are defined
1083 as simple integers of the expected size, we force these registers
1084 to be pointers as we believe that is more useful. */
1085 if (regnum
== gdbarch_pc_regnum (gdbarch
)
1086 || regnum
== RISCV_RA_REGNUM
)
1087 type
= builtin_type (gdbarch
)->builtin_func_ptr
;
1088 else if (regnum
== RISCV_FP_REGNUM
1089 || regnum
== RISCV_SP_REGNUM
1090 || regnum
== RISCV_GP_REGNUM
1091 || regnum
== RISCV_TP_REGNUM
)
1092 type
= builtin_type (gdbarch
)->builtin_data_ptr
;
1098 /* Helper for riscv_print_registers_info, prints info for a single register
1102 riscv_print_one_register_info (struct gdbarch
*gdbarch
,
1103 struct ui_file
*file
,
1104 frame_info_ptr frame
,
1107 const char *name
= gdbarch_register_name (gdbarch
, regnum
);
1109 struct type
*regtype
;
1110 int print_raw_format
;
1111 enum tab_stops
{ value_column_1
= 15 };
1113 gdb_puts (name
, file
);
1114 print_spaces (value_column_1
- strlen (name
), file
);
1118 val
= value_of_register (regnum
, frame
);
1119 regtype
= val
->type ();
1121 catch (const gdb_exception_error
&ex
)
1123 /* Handle failure to read a register without interrupting the entire
1124 'info registers' flow. */
1125 gdb_printf (file
, "%s\n", ex
.what ());
1129 print_raw_format
= (value_entirely_available (val
)
1130 && !value_optimized_out (val
));
1132 if (regtype
->code () == TYPE_CODE_FLT
1133 || (regtype
->code () == TYPE_CODE_UNION
1134 && regtype
->num_fields () == 2
1135 && regtype
->field (0).type ()->code () == TYPE_CODE_FLT
1136 && regtype
->field (1).type ()->code () == TYPE_CODE_FLT
)
1137 || (regtype
->code () == TYPE_CODE_UNION
1138 && regtype
->num_fields () == 3
1139 && regtype
->field (0).type ()->code () == TYPE_CODE_FLT
1140 && regtype
->field (1).type ()->code () == TYPE_CODE_FLT
1141 && regtype
->field (2).type ()->code () == TYPE_CODE_FLT
))
1143 struct value_print_options opts
;
1144 const gdb_byte
*valaddr
= value_contents_for_printing (val
).data ();
1145 enum bfd_endian byte_order
= type_byte_order (regtype
);
1147 get_user_print_options (&opts
);
1148 opts
.deref_ref
= true;
1150 common_val_print (val
, file
, 0, &opts
, current_language
);
1152 if (print_raw_format
)
1154 gdb_printf (file
, "\t(raw ");
1155 print_hex_chars (file
, valaddr
, regtype
->length (), byte_order
,
1157 gdb_printf (file
, ")");
1162 struct value_print_options opts
;
1163 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
1165 /* Print the register in hex. */
1166 get_formatted_print_options (&opts
, 'x');
1167 opts
.deref_ref
= true;
1168 common_val_print (val
, file
, 0, &opts
, current_language
);
1170 if (print_raw_format
)
1172 if (regnum
== RISCV_CSR_MSTATUS_REGNUM
)
1175 int size
= register_size (gdbarch
, regnum
);
1178 /* The SD field is always in the upper bit of MSTATUS, regardless
1179 of the number of bits in MSTATUS. */
1180 d
= value_as_long (val
);
1183 "\tSD:%X VM:%02X MXR:%X PUM:%X MPRV:%X XS:%X "
1184 "FS:%X MPP:%x HPP:%X SPP:%X MPIE:%X HPIE:%X "
1185 "SPIE:%X UPIE:%X MIE:%X HIE:%X SIE:%X UIE:%X",
1186 (int) ((d
>> (xlen
- 1)) & 0x1),
1187 (int) ((d
>> 24) & 0x1f),
1188 (int) ((d
>> 19) & 0x1),
1189 (int) ((d
>> 18) & 0x1),
1190 (int) ((d
>> 17) & 0x1),
1191 (int) ((d
>> 15) & 0x3),
1192 (int) ((d
>> 13) & 0x3),
1193 (int) ((d
>> 11) & 0x3),
1194 (int) ((d
>> 9) & 0x3),
1195 (int) ((d
>> 8) & 0x1),
1196 (int) ((d
>> 7) & 0x1),
1197 (int) ((d
>> 6) & 0x1),
1198 (int) ((d
>> 5) & 0x1),
1199 (int) ((d
>> 4) & 0x1),
1200 (int) ((d
>> 3) & 0x1),
1201 (int) ((d
>> 2) & 0x1),
1202 (int) ((d
>> 1) & 0x1),
1203 (int) ((d
>> 0) & 0x1));
1205 else if (regnum
== RISCV_CSR_MISA_REGNUM
)
1210 int size
= register_size (gdbarch
, regnum
);
1212 /* The MXL field is always in the upper two bits of MISA,
1213 regardless of the number of bits in MISA. Mask out other
1214 bits to ensure we have a positive value. */
1215 d
= value_as_long (val
);
1216 base
= (d
>> ((size
* 8) - 2)) & 0x3;
1219 for (; base
> 0; base
--)
1221 gdb_printf (file
, "\tRV%d", xlen
);
1223 for (i
= 0; i
< 26; i
++)
1226 gdb_printf (file
, "%c", 'A' + i
);
1229 else if (regnum
== RISCV_CSR_FCSR_REGNUM
1230 || regnum
== tdep
->fflags_regnum
1231 || regnum
== tdep
->frm_regnum
)
1233 LONGEST d
= value_as_long (val
);
1235 gdb_printf (file
, "\t");
1236 if (regnum
!= tdep
->frm_regnum
)
1238 "NV:%d DZ:%d OF:%d UF:%d NX:%d",
1239 (int) ((d
>> 4) & 0x1),
1240 (int) ((d
>> 3) & 0x1),
1241 (int) ((d
>> 2) & 0x1),
1242 (int) ((d
>> 1) & 0x1),
1243 (int) ((d
>> 0) & 0x1));
1245 if (regnum
!= tdep
->fflags_regnum
)
1247 static const char * const sfrm
[] =
1249 _("RNE (round to nearest; ties to even)"),
1250 _("RTZ (Round towards zero)"),
1251 _("RDN (Round down towards -INF)"),
1252 _("RUP (Round up towards +INF)"),
1253 _("RMM (Round to nearest; ties to max magnitude)"),
1256 /* A value of 0x7 indicates dynamic rounding mode when
1257 used within an instructions rounding-mode field, but
1258 is invalid within the FRM register. */
1259 _("INVALID[7] (Dynamic rounding mode)"),
1261 int frm
= ((regnum
== RISCV_CSR_FCSR_REGNUM
)
1262 ? (d
>> 5) : d
) & 0x7;
1264 gdb_printf (file
, "%sFRM:%i [%s]",
1265 (regnum
== RISCV_CSR_FCSR_REGNUM
1270 else if (regnum
== RISCV_PRIV_REGNUM
)
1275 d
= value_as_long (val
);
1280 static const char * const sprv
[] =
1287 gdb_printf (file
, "\tprv:%d [%s]",
1291 gdb_printf (file
, "\tprv:%d [INVALID]", priv
);
1295 /* If not a vector register, print it also according to its
1297 if (regtype
->is_vector () == 0)
1299 get_user_print_options (&opts
);
1300 opts
.deref_ref
= true;
1301 gdb_printf (file
, "\t");
1302 common_val_print (val
, file
, 0, &opts
, current_language
);
1307 gdb_printf (file
, "\n");
1310 /* Return true if REGNUM is a valid CSR register. The CSR register space
1311 is sparsely populated, so not every number is a named CSR. */
1314 riscv_is_regnum_a_named_csr (int regnum
)
1316 gdb_assert (regnum
>= RISCV_FIRST_CSR_REGNUM
1317 && regnum
<= RISCV_LAST_CSR_REGNUM
);
1321 #define DECLARE_CSR(name, num, class, define_ver, abort_ver) case RISCV_ ## num ## _REGNUM:
1322 #include "opcode/riscv-opc.h"
1331 /* Return true if REGNUM is an unknown CSR identified in
1332 riscv_tdesc_unknown_reg for GDBARCH. */
1335 riscv_is_unknown_csr (struct gdbarch
*gdbarch
, int regnum
)
1337 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
1338 return (regnum
>= tdep
->unknown_csrs_first_regnum
1339 && regnum
< (tdep
->unknown_csrs_first_regnum
1340 + tdep
->unknown_csrs_count
));
1343 /* Implement the register_reggroup_p gdbarch method. Is REGNUM a member
1347 riscv_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
1348 const struct reggroup
*reggroup
)
1350 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
1352 /* Used by 'info registers' and 'info registers <groupname>'. */
1354 if (gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
1357 if (regnum
> RISCV_LAST_REGNUM
&& regnum
< gdbarch_num_regs (gdbarch
))
1359 /* Any extra registers from the CSR tdesc_feature (identified in
1360 riscv_tdesc_unknown_reg) are removed from the save/restore groups
1361 as some targets (QEMU) report CSRs which then can't be read and
1362 having unreadable registers in the save/restore group breaks
1363 things like inferior calls.
1365 The unknown CSRs are also removed from the general group, and
1366 added into both the csr and system group. This is inline with the
1367 known CSRs (see below). */
1368 if (riscv_is_unknown_csr (gdbarch
, regnum
))
1370 if (reggroup
== restore_reggroup
|| reggroup
== save_reggroup
1371 || reggroup
== general_reggroup
)
1373 else if (reggroup
== system_reggroup
|| reggroup
== csr_reggroup
)
1377 /* This is some other unknown register from the target description.
1378 In this case we trust whatever the target description says about
1379 which groups this register should be in. */
1380 int ret
= tdesc_register_in_reggroup_p (gdbarch
, regnum
, reggroup
);
1384 return default_register_reggroup_p (gdbarch
, regnum
, reggroup
);
1387 if (reggroup
== all_reggroup
)
1389 if (regnum
< RISCV_FIRST_CSR_REGNUM
|| regnum
>= RISCV_PRIV_REGNUM
)
1391 if (riscv_is_regnum_a_named_csr (regnum
))
1395 else if (reggroup
== float_reggroup
)
1396 return (riscv_is_fp_regno_p (regnum
)
1397 || regnum
== RISCV_CSR_FCSR_REGNUM
1398 || regnum
== tdep
->fflags_regnum
1399 || regnum
== tdep
->frm_regnum
);
1400 else if (reggroup
== general_reggroup
)
1401 return regnum
< RISCV_FIRST_FP_REGNUM
;
1402 else if (reggroup
== restore_reggroup
|| reggroup
== save_reggroup
)
1404 if (riscv_has_fp_regs (gdbarch
))
1405 return (regnum
<= RISCV_LAST_FP_REGNUM
1406 || regnum
== RISCV_CSR_FCSR_REGNUM
1407 || regnum
== tdep
->fflags_regnum
1408 || regnum
== tdep
->frm_regnum
);
1410 return regnum
< RISCV_FIRST_FP_REGNUM
;
1412 else if (reggroup
== system_reggroup
|| reggroup
== csr_reggroup
)
1414 if (regnum
== RISCV_PRIV_REGNUM
)
1416 if (regnum
< RISCV_FIRST_CSR_REGNUM
|| regnum
> RISCV_LAST_CSR_REGNUM
)
1418 if (riscv_is_regnum_a_named_csr (regnum
))
1422 else if (reggroup
== vector_reggroup
)
1423 return (regnum
>= RISCV_V0_REGNUM
&& regnum
<= RISCV_V31_REGNUM
);
1428 /* Return the name for pseudo-register REGNUM for GDBARCH. */
1431 riscv_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
1433 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
1435 if (regnum
== tdep
->fflags_regnum
)
1437 else if (regnum
== tdep
->frm_regnum
)
1440 gdb_assert_not_reached ("unknown pseudo register number %d", regnum
);
1443 /* Return the type for pseudo-register REGNUM for GDBARCH. */
1445 static struct type
*
1446 riscv_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
1448 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
1450 if (regnum
== tdep
->fflags_regnum
|| regnum
== tdep
->frm_regnum
)
1451 return builtin_type (gdbarch
)->builtin_int32
;
1453 gdb_assert_not_reached ("unknown pseudo register number %d", regnum
);
1456 /* Return true (non-zero) if pseudo-register REGNUM from GDBARCH is a
1457 member of REGGROUP, otherwise return false (zero). */
1460 riscv_pseudo_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
1461 const struct reggroup
*reggroup
)
1463 /* The standard function will also work for pseudo-registers. */
1464 return riscv_register_reggroup_p (gdbarch
, regnum
, reggroup
);
1467 /* Implement the print_registers_info gdbarch method. This is used by
1468 'info registers' and 'info all-registers'. */
1471 riscv_print_registers_info (struct gdbarch
*gdbarch
,
1472 struct ui_file
*file
,
1473 frame_info_ptr frame
,
1474 int regnum
, int print_all
)
1478 /* Print one specified register. */
1479 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
1480 error (_("Not a valid register for the current processor type"));
1481 riscv_print_one_register_info (gdbarch
, file
, frame
, regnum
);
1485 const struct reggroup
*reggroup
;
1488 reggroup
= all_reggroup
;
1490 reggroup
= general_reggroup
;
1492 for (regnum
= 0; regnum
< gdbarch_num_cooked_regs (gdbarch
); ++regnum
)
1494 /* Zero never changes, so might as well hide by default. */
1495 if (regnum
== RISCV_ZERO_REGNUM
&& !print_all
)
1498 /* Registers with no name are not valid on this ISA. */
1499 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
1502 /* Is the register in the group we're interested in? */
1503 if (!gdbarch_register_reggroup_p (gdbarch
, regnum
, reggroup
))
1506 riscv_print_one_register_info (gdbarch
, file
, frame
, regnum
);
1511 /* Class that handles one decoded RiscV instruction. */
1517 /* Enum of all the opcodes that GDB cares about during the prologue scan. */
1520 /* Unknown value is used at initialisation time. */
1523 /* These instructions are all the ones we are interested in during the
1536 /* These are needed for software breakpoint support. */
1545 /* These are needed for stepping over atomic sequences. */
1548 /* This instruction is used to do a syscall. */
1551 /* Other instructions are not interesting during the prologue scan, and
1566 void decode (struct gdbarch
*gdbarch
, CORE_ADDR pc
);
1568 /* Get the length of the instruction in bytes. */
1570 { return m_length
; }
1572 /* Get the opcode for this instruction. */
1573 enum opcode
opcode () const
1574 { return m_opcode
; }
1576 /* Get destination register field for this instruction. This is only
1577 valid if the OPCODE implies there is such a field for this
1582 /* Get the RS1 register field for this instruction. This is only valid
1583 if the OPCODE implies there is such a field for this instruction. */
1587 /* Get the RS2 register field for this instruction. This is only valid
1588 if the OPCODE implies there is such a field for this instruction. */
1592 /* Get the immediate for this instruction in signed form. This is only
1593 valid if the OPCODE implies there is such a field for this
1595 int imm_signed () const
1600 /* Extract 5 bit register field at OFFSET from instruction OPCODE. */
1601 int decode_register_index (unsigned long opcode
, int offset
)
1603 return (opcode
>> offset
) & 0x1F;
1606 /* Extract 5 bit register field at OFFSET from instruction OPCODE. */
1607 int decode_register_index_short (unsigned long opcode
, int offset
)
1609 return ((opcode
>> offset
) & 0x7) + 8;
1612 /* Helper for DECODE, decode 32-bit R-type instruction. */
1613 void decode_r_type_insn (enum opcode opcode
, ULONGEST ival
)
1616 m_rd
= decode_register_index (ival
, OP_SH_RD
);
1617 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
1618 m_rs2
= decode_register_index (ival
, OP_SH_RS2
);
1621 /* Helper for DECODE, decode 16-bit compressed R-type instruction. */
1622 void decode_cr_type_insn (enum opcode opcode
, ULONGEST ival
)
1625 m_rd
= m_rs1
= decode_register_index (ival
, OP_SH_CRS1S
);
1626 m_rs2
= decode_register_index (ival
, OP_SH_CRS2
);
1629 /* Helper for DECODE, decode 32-bit I-type instruction. */
1630 void decode_i_type_insn (enum opcode opcode
, ULONGEST ival
)
1633 m_rd
= decode_register_index (ival
, OP_SH_RD
);
1634 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
1635 m_imm
.s
= EXTRACT_ITYPE_IMM (ival
);
1638 /* Helper for DECODE, decode 16-bit compressed I-type instruction. */
1639 void decode_ci_type_insn (enum opcode opcode
, ULONGEST ival
)
1642 m_rd
= m_rs1
= decode_register_index (ival
, OP_SH_CRS1S
);
1643 m_imm
.s
= EXTRACT_CITYPE_IMM (ival
);
1646 /* Helper for DECODE, decode 16-bit compressed CL-type instruction. */
1647 void decode_cl_type_insn (enum opcode opcode
, ULONGEST ival
)
1650 m_rd
= decode_register_index_short (ival
, OP_SH_CRS2S
);
1651 m_rs1
= decode_register_index_short (ival
, OP_SH_CRS1S
);
1652 m_imm
.s
= EXTRACT_CLTYPE_IMM (ival
);
1655 /* Helper for DECODE, decode 32-bit S-type instruction. */
1656 void decode_s_type_insn (enum opcode opcode
, ULONGEST ival
)
1659 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
1660 m_rs2
= decode_register_index (ival
, OP_SH_RS2
);
1661 m_imm
.s
= EXTRACT_STYPE_IMM (ival
);
1664 /* Helper for DECODE, decode 16-bit CS-type instruction. The immediate
1665 encoding is different for each CS format instruction, so extracting
1666 the immediate is left up to the caller, who should pass the extracted
1667 immediate value through in IMM. */
1668 void decode_cs_type_insn (enum opcode opcode
, ULONGEST ival
, int imm
)
1672 m_rs1
= decode_register_index_short (ival
, OP_SH_CRS1S
);
1673 m_rs2
= decode_register_index_short (ival
, OP_SH_CRS2S
);
1676 /* Helper for DECODE, decode 16-bit CSS-type instruction. The immediate
1677 encoding is different for each CSS format instruction, so extracting
1678 the immediate is left up to the caller, who should pass the extracted
1679 immediate value through in IMM. */
1680 void decode_css_type_insn (enum opcode opcode
, ULONGEST ival
, int imm
)
1684 m_rs1
= RISCV_SP_REGNUM
;
1685 /* Not a compressed register number in this case. */
1686 m_rs2
= decode_register_index (ival
, OP_SH_CRS2
);
1689 /* Helper for DECODE, decode 32-bit U-type instruction. */
1690 void decode_u_type_insn (enum opcode opcode
, ULONGEST ival
)
1693 m_rd
= decode_register_index (ival
, OP_SH_RD
);
1694 m_imm
.s
= EXTRACT_UTYPE_IMM (ival
);
1697 /* Helper for DECODE, decode 32-bit J-type instruction. */
1698 void decode_j_type_insn (enum opcode opcode
, ULONGEST ival
)
1701 m_rd
= decode_register_index (ival
, OP_SH_RD
);
1702 m_imm
.s
= EXTRACT_JTYPE_IMM (ival
);
1705 /* Helper for DECODE, decode 32-bit J-type instruction. */
1706 void decode_cj_type_insn (enum opcode opcode
, ULONGEST ival
)
1709 m_imm
.s
= EXTRACT_CJTYPE_IMM (ival
);
1712 void decode_b_type_insn (enum opcode opcode
, ULONGEST ival
)
1715 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
1716 m_rs2
= decode_register_index (ival
, OP_SH_RS2
);
1717 m_imm
.s
= EXTRACT_BTYPE_IMM (ival
);
1720 void decode_cb_type_insn (enum opcode opcode
, ULONGEST ival
)
1723 m_rs1
= decode_register_index_short (ival
, OP_SH_CRS1S
);
1724 m_imm
.s
= EXTRACT_CBTYPE_IMM (ival
);
1727 /* Fetch instruction from target memory at ADDR, return the content of
1728 the instruction, and update LEN with the instruction length. */
1729 static ULONGEST
fetch_instruction (struct gdbarch
*gdbarch
,
1730 CORE_ADDR addr
, int *len
);
1732 /* The length of the instruction in bytes. Should be 2 or 4. */
1735 /* The instruction opcode. */
1736 enum opcode m_opcode
;
1738 /* The three possible registers an instruction might reference. Not
1739 every instruction fills in all of these registers. Which fields are
1740 valid depends on the opcode. The naming of these fields matches the
1741 naming in the riscv isa manual. */
1746 /* Possible instruction immediate. This is only valid if the instruction
1747 format contains an immediate, not all instruction, whether this is
1748 valid depends on the opcode. Despite only having one format for now
1749 the immediate is packed into a union, later instructions might require
1750 an unsigned formatted immediate, having the union in place now will
1751 reduce the need for code churn later. */
1752 union riscv_insn_immediate
1754 riscv_insn_immediate ()
1764 /* Fetch instruction from target memory at ADDR, return the content of the
1765 instruction, and update LEN with the instruction length. */
1768 riscv_insn::fetch_instruction (struct gdbarch
*gdbarch
,
1769 CORE_ADDR addr
, int *len
)
1771 enum bfd_endian byte_order
= gdbarch_byte_order_for_code (gdbarch
);
1772 gdb_byte buf
[RISCV_MAX_INSN_LEN
];
1773 int instlen
, status
;
1775 /* All insns are at least 16 bits. */
1776 status
= target_read_memory (addr
, buf
, 2);
1778 memory_error (TARGET_XFER_E_IO
, addr
);
1780 /* If we need more, grab it now. */
1781 instlen
= riscv_insn_length (buf
[0]);
1782 gdb_assert (instlen
<= sizeof (buf
));
1787 status
= target_read_memory (addr
+ 2, buf
+ 2, instlen
- 2);
1789 memory_error (TARGET_XFER_E_IO
, addr
+ 2);
1792 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1795 /* Fetch from target memory an instruction at PC and decode it. This can
1796 throw an error if the memory access fails, callers are responsible for
1797 handling this error if that is appropriate. */
1800 riscv_insn::decode (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1804 /* Fetch the instruction, and the instructions length. */
1805 ival
= fetch_instruction (gdbarch
, pc
, &m_length
);
1809 if (is_add_insn (ival
))
1810 decode_r_type_insn (ADD
, ival
);
1811 else if (is_addw_insn (ival
))
1812 decode_r_type_insn (ADDW
, ival
);
1813 else if (is_addi_insn (ival
))
1814 decode_i_type_insn (ADDI
, ival
);
1815 else if (is_addiw_insn (ival
))
1816 decode_i_type_insn (ADDIW
, ival
);
1817 else if (is_auipc_insn (ival
))
1818 decode_u_type_insn (AUIPC
, ival
);
1819 else if (is_lui_insn (ival
))
1820 decode_u_type_insn (LUI
, ival
);
1821 else if (is_sd_insn (ival
))
1822 decode_s_type_insn (SD
, ival
);
1823 else if (is_sw_insn (ival
))
1824 decode_s_type_insn (SW
, ival
);
1825 else if (is_jal_insn (ival
))
1826 decode_j_type_insn (JAL
, ival
);
1827 else if (is_jalr_insn (ival
))
1828 decode_i_type_insn (JALR
, ival
);
1829 else if (is_beq_insn (ival
))
1830 decode_b_type_insn (BEQ
, ival
);
1831 else if (is_bne_insn (ival
))
1832 decode_b_type_insn (BNE
, ival
);
1833 else if (is_blt_insn (ival
))
1834 decode_b_type_insn (BLT
, ival
);
1835 else if (is_bge_insn (ival
))
1836 decode_b_type_insn (BGE
, ival
);
1837 else if (is_bltu_insn (ival
))
1838 decode_b_type_insn (BLTU
, ival
);
1839 else if (is_bgeu_insn (ival
))
1840 decode_b_type_insn (BGEU
, ival
);
1841 else if (is_lr_w_insn (ival
))
1842 decode_r_type_insn (LR
, ival
);
1843 else if (is_lr_d_insn (ival
))
1844 decode_r_type_insn (LR
, ival
);
1845 else if (is_sc_w_insn (ival
))
1846 decode_r_type_insn (SC
, ival
);
1847 else if (is_sc_d_insn (ival
))
1848 decode_r_type_insn (SC
, ival
);
1849 else if (is_ecall_insn (ival
))
1850 decode_i_type_insn (ECALL
, ival
);
1851 else if (is_ld_insn (ival
))
1852 decode_i_type_insn (LD
, ival
);
1853 else if (is_lw_insn (ival
))
1854 decode_i_type_insn (LW
, ival
);
1856 /* None of the other fields are valid in this case. */
1859 else if (m_length
== 2)
1861 int xlen
= riscv_isa_xlen (gdbarch
);
1863 /* C_ADD and C_JALR have the same opcode. If RS2 is 0, then this is a
1864 C_JALR. So must try to match C_JALR first as it has more bits in
1866 if (is_c_jalr_insn (ival
))
1867 decode_cr_type_insn (JALR
, ival
);
1868 else if (is_c_add_insn (ival
))
1869 decode_cr_type_insn (ADD
, ival
);
1870 /* C_ADDW is RV64 and RV128 only. */
1871 else if (xlen
!= 4 && is_c_addw_insn (ival
))
1872 decode_cr_type_insn (ADDW
, ival
);
1873 else if (is_c_addi_insn (ival
))
1874 decode_ci_type_insn (ADDI
, ival
);
1875 /* C_ADDIW and C_JAL have the same opcode. C_ADDIW is RV64 and RV128
1876 only and C_JAL is RV32 only. */
1877 else if (xlen
!= 4 && is_c_addiw_insn (ival
))
1878 decode_ci_type_insn (ADDIW
, ival
);
1879 else if (xlen
== 4 && is_c_jal_insn (ival
))
1880 decode_cj_type_insn (JAL
, ival
);
1881 /* C_ADDI16SP and C_LUI have the same opcode. If RD is 2, then this is a
1882 C_ADDI16SP. So must try to match C_ADDI16SP first as it has more bits
1884 else if (is_c_addi16sp_insn (ival
))
1887 m_rd
= m_rs1
= decode_register_index (ival
, OP_SH_RD
);
1888 m_imm
.s
= EXTRACT_CITYPE_ADDI16SP_IMM (ival
);
1890 else if (is_c_addi4spn_insn (ival
))
1893 m_rd
= decode_register_index_short (ival
, OP_SH_CRS2S
);
1894 m_rs1
= RISCV_SP_REGNUM
;
1895 m_imm
.s
= EXTRACT_CIWTYPE_ADDI4SPN_IMM (ival
);
1897 else if (is_c_lui_insn (ival
))
1900 m_rd
= decode_register_index (ival
, OP_SH_CRS1S
);
1901 m_imm
.s
= EXTRACT_CITYPE_LUI_IMM (ival
);
1903 /* C_SD and C_FSW have the same opcode. C_SD is RV64 and RV128 only,
1904 and C_FSW is RV32 only. */
1905 else if (xlen
!= 4 && is_c_sd_insn (ival
))
1906 decode_cs_type_insn (SD
, ival
, EXTRACT_CLTYPE_LD_IMM (ival
));
1907 else if (is_c_sw_insn (ival
))
1908 decode_cs_type_insn (SW
, ival
, EXTRACT_CLTYPE_LW_IMM (ival
));
1909 else if (is_c_swsp_insn (ival
))
1910 decode_css_type_insn (SW
, ival
, EXTRACT_CSSTYPE_SWSP_IMM (ival
));
1911 else if (xlen
!= 4 && is_c_sdsp_insn (ival
))
1912 decode_css_type_insn (SD
, ival
, EXTRACT_CSSTYPE_SDSP_IMM (ival
));
1913 /* C_JR and C_MV have the same opcode. If RS2 is 0, then this is a C_JR.
1914 So must try to match C_JR first as it has more bits in mask. */
1915 else if (is_c_jr_insn (ival
))
1916 decode_cr_type_insn (JALR
, ival
);
1917 else if (is_c_mv_insn (ival
))
1918 decode_cr_type_insn (MV
, ival
);
1919 else if (is_c_j_insn (ival
))
1920 decode_cj_type_insn (JAL
, ival
);
1921 else if (is_c_beqz_insn (ival
))
1922 decode_cb_type_insn (BEQ
, ival
);
1923 else if (is_c_bnez_insn (ival
))
1924 decode_cb_type_insn (BNE
, ival
);
1925 else if (is_c_ld_insn (ival
))
1926 decode_cl_type_insn (LD
, ival
);
1927 else if (is_c_lw_insn (ival
))
1928 decode_cl_type_insn (LW
, ival
);
1930 /* None of the other fields of INSN are valid in this case. */
1935 /* 6 bytes or more. If the instruction is longer than 8 bytes, we don't
1936 have full instruction bits in ival. At least, such long instructions
1937 are not defined yet, so just ignore it. */
1938 gdb_assert (m_length
> 0 && m_length
% 2 == 0);
1943 /* The prologue scanner. This is currently only used for skipping the
1944 prologue of a function when the DWARF information is not sufficient.
1945 However, it is written with filling of the frame cache in mind, which
1946 is why different groups of stack setup instructions are split apart
1947 during the core of the inner loop. In the future, the intention is to
1948 extend this function to fully support building up a frame cache that
1949 can unwind register values when there is no DWARF information. */
1952 riscv_scan_prologue (struct gdbarch
*gdbarch
,
1953 CORE_ADDR start_pc
, CORE_ADDR end_pc
,
1954 struct riscv_unwind_cache
*cache
)
1956 CORE_ADDR cur_pc
, next_pc
, after_prologue_pc
;
1957 CORE_ADDR end_prologue_addr
= 0;
1959 /* Find an upper limit on the function prologue using the debug
1960 information. If the debug information could not be used to provide
1961 that bound, then use an arbitrary large number as the upper bound. */
1962 after_prologue_pc
= skip_prologue_using_sal (gdbarch
, start_pc
);
1963 if (after_prologue_pc
== 0)
1964 after_prologue_pc
= start_pc
+ 100; /* Arbitrary large number. */
1965 if (after_prologue_pc
< end_pc
)
1966 end_pc
= after_prologue_pc
;
1968 pv_t regs
[RISCV_NUM_INTEGER_REGS
]; /* Number of GPR. */
1969 for (int regno
= 0; regno
< RISCV_NUM_INTEGER_REGS
; regno
++)
1970 regs
[regno
] = pv_register (regno
, 0);
1971 pv_area
stack (RISCV_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
1973 if (riscv_debug_unwinder
)
1976 "Prologue scan for function starting at %s (limit %s)\n",
1977 core_addr_to_string (start_pc
),
1978 core_addr_to_string (end_pc
));
1980 for (next_pc
= cur_pc
= start_pc
; cur_pc
< end_pc
; cur_pc
= next_pc
)
1982 struct riscv_insn insn
;
1984 /* Decode the current instruction, and decide where the next
1985 instruction lives based on the size of this instruction. */
1986 insn
.decode (gdbarch
, cur_pc
);
1987 gdb_assert (insn
.length () > 0);
1988 next_pc
= cur_pc
+ insn
.length ();
1990 /* Look for common stack adjustment insns. */
1991 if ((insn
.opcode () == riscv_insn::ADDI
1992 || insn
.opcode () == riscv_insn::ADDIW
)
1993 && insn
.rd () == RISCV_SP_REGNUM
1994 && insn
.rs1 () == RISCV_SP_REGNUM
)
1996 /* Handle: addi sp, sp, -i
1997 or: addiw sp, sp, -i */
1998 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
1999 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
2001 = pv_add_constant (regs
[insn
.rs1 ()], insn
.imm_signed ());
2003 else if ((insn
.opcode () == riscv_insn::SW
2004 || insn
.opcode () == riscv_insn::SD
)
2005 && (insn
.rs1 () == RISCV_SP_REGNUM
2006 || insn
.rs1 () == RISCV_FP_REGNUM
))
2008 /* Handle: sw reg, offset(sp)
2009 or: sd reg, offset(sp)
2010 or: sw reg, offset(s0)
2011 or: sd reg, offset(s0) */
2012 /* Instruction storing a register onto the stack. */
2013 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
2014 gdb_assert (insn
.rs2 () < RISCV_NUM_INTEGER_REGS
);
2015 stack
.store (pv_add_constant (regs
[insn
.rs1 ()], insn
.imm_signed ()),
2016 (insn
.opcode () == riscv_insn::SW
? 4 : 8),
2019 else if (insn
.opcode () == riscv_insn::ADDI
2020 && insn
.rd () == RISCV_FP_REGNUM
2021 && insn
.rs1 () == RISCV_SP_REGNUM
)
2023 /* Handle: addi s0, sp, size */
2024 /* Instructions setting up the frame pointer. */
2025 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
2026 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
2028 = pv_add_constant (regs
[insn
.rs1 ()], insn
.imm_signed ());
2030 else if ((insn
.opcode () == riscv_insn::ADD
2031 || insn
.opcode () == riscv_insn::ADDW
)
2032 && insn
.rd () == RISCV_FP_REGNUM
2033 && insn
.rs1 () == RISCV_SP_REGNUM
2034 && insn
.rs2 () == RISCV_ZERO_REGNUM
)
2036 /* Handle: add s0, sp, 0
2037 or: addw s0, sp, 0 */
2038 /* Instructions setting up the frame pointer. */
2039 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
2040 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
2041 regs
[insn
.rd ()] = pv_add_constant (regs
[insn
.rs1 ()], 0);
2043 else if ((insn
.opcode () == riscv_insn::ADDI
2044 && insn
.rd () == RISCV_ZERO_REGNUM
2045 && insn
.rs1 () == RISCV_ZERO_REGNUM
2046 && insn
.imm_signed () == 0))
2048 /* Handle: add x0, x0, 0 (NOP) */
2050 else if (insn
.opcode () == riscv_insn::AUIPC
)
2052 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
2053 regs
[insn
.rd ()] = pv_constant (cur_pc
+ insn
.imm_signed ());
2055 else if (insn
.opcode () == riscv_insn::LUI
)
2057 /* Handle: lui REG, n
2058 Where REG is not gp register. */
2059 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
2060 regs
[insn
.rd ()] = pv_constant (insn
.imm_signed ());
2062 else if (insn
.opcode () == riscv_insn::ADDI
)
2064 /* Handle: addi REG1, REG2, IMM */
2065 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
2066 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
2068 = pv_add_constant (regs
[insn
.rs1 ()], insn
.imm_signed ());
2070 else if (insn
.opcode () == riscv_insn::ADD
)
2072 /* Handle: add REG1, REG2, REG3 */
2073 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
2074 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
2075 gdb_assert (insn
.rs2 () < RISCV_NUM_INTEGER_REGS
);
2076 regs
[insn
.rd ()] = pv_add (regs
[insn
.rs1 ()], regs
[insn
.rs2 ()]);
2078 else if (insn
.opcode () == riscv_insn::LD
2079 || insn
.opcode () == riscv_insn::LW
)
2081 /* Handle: ld reg, offset(rs1)
2082 or: c.ld reg, offset(rs1)
2083 or: lw reg, offset(rs1)
2084 or: c.lw reg, offset(rs1) */
2085 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
2086 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
2088 = stack
.fetch (pv_add_constant (regs
[insn
.rs1 ()],
2089 insn
.imm_signed ()),
2090 (insn
.opcode () == riscv_insn::LW
? 4 : 8));
2092 else if (insn
.opcode () == riscv_insn::MV
)
2094 /* Handle: c.mv RD, RS2 */
2095 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
2096 gdb_assert (insn
.rs2 () < RISCV_NUM_INTEGER_REGS
);
2097 gdb_assert (insn
.rs2 () > 0);
2098 regs
[insn
.rd ()] = regs
[insn
.rs2 ()];
2102 end_prologue_addr
= cur_pc
;
2107 if (end_prologue_addr
== 0)
2108 end_prologue_addr
= cur_pc
;
2110 if (riscv_debug_unwinder
)
2111 gdb_printf (gdb_stdlog
, "End of prologue at %s\n",
2112 core_addr_to_string (end_prologue_addr
));
2116 /* Figure out if it is a frame pointer or just a stack pointer. Also
2117 the offset held in the pv_t is from the original register value to
2118 the current value, which for a grows down stack means a negative
2119 value. The FRAME_BASE_OFFSET is the negation of this, how to get
2120 from the current value to the original value. */
2121 if (pv_is_register (regs
[RISCV_FP_REGNUM
], RISCV_SP_REGNUM
))
2123 cache
->frame_base_reg
= RISCV_FP_REGNUM
;
2124 cache
->frame_base_offset
= -regs
[RISCV_FP_REGNUM
].k
;
2128 cache
->frame_base_reg
= RISCV_SP_REGNUM
;
2129 cache
->frame_base_offset
= -regs
[RISCV_SP_REGNUM
].k
;
2132 /* Assign offset from old SP to all saved registers. As we don't
2133 have the previous value for the frame base register at this
2134 point, we store the offset as the address in the trad_frame, and
2135 then convert this to an actual address later. */
2136 for (int i
= 0; i
<= RISCV_NUM_INTEGER_REGS
; i
++)
2139 if (stack
.find_reg (gdbarch
, i
, &offset
))
2141 if (riscv_debug_unwinder
)
2143 /* Display OFFSET as a signed value, the offsets are from
2144 the frame base address to the registers location on
2145 the stack, with a descending stack this means the
2146 offsets are always negative. */
2147 gdb_printf (gdb_stdlog
,
2148 "Register $%s at stack offset %s\n",
2149 gdbarch_register_name (gdbarch
, i
),
2150 plongest ((LONGEST
) offset
));
2152 cache
->regs
[i
].set_addr (offset
);
2157 return end_prologue_addr
;
2160 /* Implement the riscv_skip_prologue gdbarch method. */
2163 riscv_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2165 CORE_ADDR func_addr
;
2167 /* See if we can determine the end of the prologue via the symbol
2168 table. If so, then return either PC, or the PC after the
2169 prologue, whichever is greater. */
2170 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
2172 CORE_ADDR post_prologue_pc
2173 = skip_prologue_using_sal (gdbarch
, func_addr
);
2175 if (post_prologue_pc
!= 0)
2176 return std::max (pc
, post_prologue_pc
);
2179 /* Can't determine prologue from the symbol table, need to examine
2180 instructions. Pass -1 for the end address to indicate the prologue
2181 scanner can scan as far as it needs to find the end of the prologue. */
2182 return riscv_scan_prologue (gdbarch
, pc
, ((CORE_ADDR
) -1), NULL
);
2185 /* Implement the gdbarch push dummy code callback. */
2188 riscv_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
2189 CORE_ADDR funaddr
, struct value
**args
, int nargs
,
2190 struct type
*value_type
, CORE_ADDR
*real_pc
,
2191 CORE_ADDR
*bp_addr
, struct regcache
*regcache
)
2193 /* A nop instruction is 'add x0, x0, 0'. */
2194 static const gdb_byte nop_insn
[] = { 0x13, 0x00, 0x00, 0x00 };
2196 /* Allocate space for a breakpoint, and keep the stack correctly
2197 aligned. The space allocated here must be at least big enough to
2198 accommodate the NOP_INSN defined above. */
2203 /* When we insert a breakpoint we select whether to use a compressed
2204 breakpoint or not based on the existing contents of the memory.
2206 If the breakpoint is being placed onto the stack as part of setting up
2207 for an inferior call from GDB, then the existing stack contents may
2208 randomly appear to be a compressed instruction, causing GDB to insert
2209 a compressed breakpoint. If this happens on a target that does not
2210 support compressed instructions then this could cause problems.
2212 To prevent this issue we write an uncompressed nop onto the stack at
2213 the location where the breakpoint will be inserted. In this way we
2214 ensure that we always use an uncompressed breakpoint, which should
2215 work on all targets.
2217 We call TARGET_WRITE_MEMORY here so that if the write fails we don't
2218 throw an exception. Instead we ignore the error and move on. The
2219 assumption is that either GDB will error later when actually trying to
2220 insert a software breakpoint, or GDB will use hardware breakpoints and
2221 there will be no need to write to memory later. */
2222 int status
= target_write_memory (*bp_addr
, nop_insn
, sizeof (nop_insn
));
2224 if (riscv_debug_breakpoints
|| riscv_debug_infcall
)
2225 gdb_printf (gdb_stdlog
,
2226 "Writing %s-byte nop instruction to %s: %s\n",
2227 plongest (sizeof (nop_insn
)),
2228 paddress (gdbarch
, *bp_addr
),
2229 (status
== 0 ? "success" : "failed"));
2234 /* Implement the gdbarch type alignment method, overrides the generic
2235 alignment algorithm for anything that is RISC-V specific. */
2238 riscv_type_align (gdbarch
*gdbarch
, type
*type
)
2240 type
= check_typedef (type
);
2241 if (type
->code () == TYPE_CODE_ARRAY
&& type
->is_vector ())
2242 return std::min (type
->length (), (ULONGEST
) BIGGEST_ALIGNMENT
);
2244 /* Anything else will be aligned by the generic code. */
2248 /* Holds information about a single argument either being passed to an
2249 inferior function, or returned from an inferior function. This includes
2250 information about the size, type, etc of the argument, and also
2251 information about how the argument will be passed (or returned). */
2253 struct riscv_arg_info
2255 /* Contents of the argument. */
2256 const gdb_byte
*contents
;
2258 /* Length of argument. */
2261 /* Alignment required for an argument of this type. */
2264 /* The type for this argument. */
2267 /* Each argument can have either 1 or 2 locations assigned to it. Each
2268 location describes where part of the argument will be placed. The
2269 second location is valid based on the LOC_TYPE and C_LENGTH fields
2270 of the first location (which is always valid). */
2273 /* What type of location this is. */
2276 /* Argument passed in a register. */
2279 /* Argument passed as an on stack argument. */
2282 /* Argument passed by reference. The second location is always
2283 valid for a BY_REF argument, and describes where the address
2284 of the BY_REF argument should be placed. */
2288 /* Information that depends on the location type. */
2291 /* Which register number to use. */
2294 /* The offset into the stack region. */
2298 /* The length of contents covered by this location. If this is less
2299 than the total length of the argument, then the second location
2300 will be valid, and will describe where the rest of the argument
2304 /* The offset within CONTENTS for this part of the argument. This can
2305 be non-zero even for the first part (the first field of a struct can
2306 have a non-zero offset due to padding). For the second part of the
2307 argument, this might be the C_LENGTH value of the first part,
2308 however, if we are passing a structure in two registers, and there's
2309 is padding between the first and second field, then this offset
2310 might be greater than the length of the first argument part. When
2311 the second argument location is not holding part of the argument
2312 value, but is instead holding the address of a reference argument,
2313 then this offset will be set to 0. */
2317 /* TRUE if this is an unnamed argument. */
2321 /* Information about a set of registers being used for passing arguments as
2322 part of a function call. The register set must be numerically
2323 sequential from NEXT_REGNUM to LAST_REGNUM. The register set can be
2324 disabled from use by setting NEXT_REGNUM greater than LAST_REGNUM. */
2326 struct riscv_arg_reg
2328 riscv_arg_reg (int first
, int last
)
2329 : next_regnum (first
),
2335 /* The GDB register number to use in this set. */
2338 /* The last GDB register number to use in this set. */
2342 /* Arguments can be passed as on stack arguments, or by reference. The
2343 on stack arguments must be in a continuous region starting from $sp,
2344 while the by reference arguments can be anywhere, but we'll put them
2345 on the stack after (at higher address) the on stack arguments.
2347 This might not be the right approach to take. The ABI is clear that
2348 an argument passed by reference can be modified by the callee, which
2349 us placing the argument (temporarily) onto the stack will not achieve
2350 (changes will be lost). There's also the possibility that very large
2351 arguments could overflow the stack.
2353 This struct is used to track offset into these two areas for where
2354 arguments are to be placed. */
2355 struct riscv_memory_offsets
2357 riscv_memory_offsets ()
2364 /* Offset into on stack argument area. */
2367 /* Offset into the pass by reference area. */
2371 /* Holds information about where arguments to a call will be placed. This
2372 is updated as arguments are added onto the call, and can be used to
2373 figure out where the next argument should be placed. */
2375 struct riscv_call_info
2377 riscv_call_info (struct gdbarch
*gdbarch
)
2378 : int_regs (RISCV_A0_REGNUM
, RISCV_A0_REGNUM
+ 7),
2379 float_regs (RISCV_FA0_REGNUM
, RISCV_FA0_REGNUM
+ 7)
2381 xlen
= riscv_abi_xlen (gdbarch
);
2382 flen
= riscv_abi_flen (gdbarch
);
2384 /* Reduce the number of integer argument registers when using the
2385 embedded abi (i.e. rv32e). */
2386 if (riscv_abi_embedded (gdbarch
))
2387 int_regs
.last_regnum
= RISCV_A0_REGNUM
+ 5;
2389 /* Disable use of floating point registers if needed. */
2390 if (!riscv_has_fp_abi (gdbarch
))
2391 float_regs
.next_regnum
= float_regs
.last_regnum
+ 1;
2394 /* Track the memory areas used for holding in-memory arguments to a
2396 struct riscv_memory_offsets memory
;
2398 /* Holds information about the next integer register to use for passing
2400 struct riscv_arg_reg int_regs
;
2402 /* Holds information about the next floating point register to use for
2403 passing an argument. */
2404 struct riscv_arg_reg float_regs
;
2406 /* The XLEN and FLEN are copied in to this structure for convenience, and
2407 are just the results of calling RISCV_ABI_XLEN and RISCV_ABI_FLEN. */
2412 /* Return the number of registers available for use as parameters in the
2413 register set REG. Returned value can be 0 or more. */
2416 riscv_arg_regs_available (struct riscv_arg_reg
*reg
)
2418 if (reg
->next_regnum
> reg
->last_regnum
)
2421 return (reg
->last_regnum
- reg
->next_regnum
+ 1);
2424 /* If there is at least one register available in the register set REG then
2425 the next register from REG is assigned to LOC and the length field of
2426 LOC is updated to LENGTH. The register set REG is updated to indicate
2427 that the assigned register is no longer available and the function
2430 If there are no registers available in REG then the function returns
2431 false, and LOC and REG are unchanged. */
2434 riscv_assign_reg_location (struct riscv_arg_info::location
*loc
,
2435 struct riscv_arg_reg
*reg
,
2436 int length
, int offset
)
2438 if (reg
->next_regnum
<= reg
->last_regnum
)
2440 loc
->loc_type
= riscv_arg_info::location::in_reg
;
2441 loc
->loc_data
.regno
= reg
->next_regnum
;
2443 loc
->c_length
= length
;
2444 loc
->c_offset
= offset
;
2451 /* Assign LOC a location as the next stack parameter, and update MEMORY to
2452 record that an area of stack has been used to hold the parameter
2455 The length field of LOC is updated to LENGTH, the length of the
2456 parameter being stored, and ALIGN is the alignment required by the
2457 parameter, which will affect how memory is allocated out of MEMORY. */
2460 riscv_assign_stack_location (struct riscv_arg_info::location
*loc
,
2461 struct riscv_memory_offsets
*memory
,
2462 int length
, int align
)
2464 loc
->loc_type
= riscv_arg_info::location::on_stack
;
2466 = align_up (memory
->arg_offset
, align
);
2467 loc
->loc_data
.offset
= memory
->arg_offset
;
2468 memory
->arg_offset
+= length
;
2469 loc
->c_length
= length
;
2471 /* Offset is always 0, either we're the first location part, in which
2472 case we're reading content from the start of the argument, or we're
2473 passing the address of a reference argument, so 0. */
2477 /* Update AINFO, which describes an argument that should be passed or
2478 returned using the integer ABI. The argloc fields within AINFO are
2479 updated to describe the location in which the argument will be passed to
2480 a function, or returned from a function.
2482 The CINFO structure contains the ongoing call information, the holds
2483 information such as which argument registers are remaining to be
2484 assigned to parameter, and how much memory has been used by parameters
2487 By examining the state of CINFO a suitable location can be selected,
2488 and assigned to AINFO. */
2491 riscv_call_arg_scalar_int (struct riscv_arg_info
*ainfo
,
2492 struct riscv_call_info
*cinfo
)
2494 if (TYPE_HAS_DYNAMIC_LENGTH (ainfo
->type
)
2495 || ainfo
->length
> (2 * cinfo
->xlen
))
2497 /* Argument is going to be passed by reference. */
2498 ainfo
->argloc
[0].loc_type
2499 = riscv_arg_info::location::by_ref
;
2500 cinfo
->memory
.ref_offset
2501 = align_up (cinfo
->memory
.ref_offset
, ainfo
->align
);
2502 ainfo
->argloc
[0].loc_data
.offset
= cinfo
->memory
.ref_offset
;
2503 cinfo
->memory
.ref_offset
+= ainfo
->length
;
2504 ainfo
->argloc
[0].c_length
= ainfo
->length
;
2506 /* The second location for this argument is given over to holding the
2507 address of the by-reference data. Pass 0 for the offset as this
2508 is not part of the actual argument value. */
2509 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
2512 riscv_assign_stack_location (&ainfo
->argloc
[1],
2513 &cinfo
->memory
, cinfo
->xlen
,
2518 int len
= std::min (ainfo
->length
, cinfo
->xlen
);
2519 int align
= std::max (ainfo
->align
, cinfo
->xlen
);
2521 /* Unnamed arguments in registers that require 2*XLEN alignment are
2522 passed in an aligned register pair. */
2523 if (ainfo
->is_unnamed
&& (align
== cinfo
->xlen
* 2)
2524 && cinfo
->int_regs
.next_regnum
& 1)
2525 cinfo
->int_regs
.next_regnum
++;
2527 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
2528 &cinfo
->int_regs
, len
, 0))
2529 riscv_assign_stack_location (&ainfo
->argloc
[0],
2530 &cinfo
->memory
, len
, align
);
2532 if (len
< ainfo
->length
)
2534 len
= ainfo
->length
- len
;
2535 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
2536 &cinfo
->int_regs
, len
,
2538 riscv_assign_stack_location (&ainfo
->argloc
[1],
2539 &cinfo
->memory
, len
, cinfo
->xlen
);
2544 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
2545 is being passed with the floating point ABI. */
2548 riscv_call_arg_scalar_float (struct riscv_arg_info
*ainfo
,
2549 struct riscv_call_info
*cinfo
)
2551 if (ainfo
->length
> cinfo
->flen
|| ainfo
->is_unnamed
)
2552 return riscv_call_arg_scalar_int (ainfo
, cinfo
);
2555 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
2558 return riscv_call_arg_scalar_int (ainfo
, cinfo
);
2562 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
2563 is a complex floating point argument, and is therefore handled
2564 differently to other argument types. */
2567 riscv_call_arg_complex_float (struct riscv_arg_info
*ainfo
,
2568 struct riscv_call_info
*cinfo
)
2570 if (ainfo
->length
<= (2 * cinfo
->flen
)
2571 && riscv_arg_regs_available (&cinfo
->float_regs
) >= 2
2572 && !ainfo
->is_unnamed
)
2575 int len
= ainfo
->length
/ 2;
2577 result
= riscv_assign_reg_location (&ainfo
->argloc
[0],
2578 &cinfo
->float_regs
, len
, 0);
2579 gdb_assert (result
);
2581 result
= riscv_assign_reg_location (&ainfo
->argloc
[1],
2582 &cinfo
->float_regs
, len
, len
);
2583 gdb_assert (result
);
2586 return riscv_call_arg_scalar_int (ainfo
, cinfo
);
2589 /* A structure used for holding information about a structure type within
2590 the inferior program. The RiscV ABI has special rules for handling some
2591 structures with a single field or with two fields. The counting of
2592 fields here is done after flattening out all nested structures. */
2594 class riscv_struct_info
2597 riscv_struct_info ()
2598 : m_number_of_fields (0),
2599 m_types
{ nullptr, nullptr },
2605 /* Analyse TYPE descending into nested structures, count the number of
2606 scalar fields and record the types of the first two fields found. */
2607 void analyse (struct type
*type
)
2609 analyse_inner (type
, 0);
2612 /* The number of scalar fields found in the analysed type. This is
2613 currently only accurate if the value returned is 0, 1, or 2 as the
2614 analysis stops counting when the number of fields is 3. This is
2615 because the RiscV ABI only has special cases for 1 or 2 fields,
2616 anything else we just don't care about. */
2617 int number_of_fields () const
2618 { return m_number_of_fields
; }
2620 /* Return the type for scalar field INDEX within the analysed type. Will
2621 return nullptr if there is no field at that index. Only INDEX values
2622 0 and 1 can be requested as the RiscV ABI only has special cases for
2623 structures with 1 or 2 fields. */
2624 struct type
*field_type (int index
) const
2626 gdb_assert (index
< (sizeof (m_types
) / sizeof (m_types
[0])));
2627 return m_types
[index
];
2630 /* Return the offset of scalar field INDEX within the analysed type. Will
2631 return 0 if there is no field at that index. Only INDEX values 0 and
2632 1 can be requested as the RiscV ABI only has special cases for
2633 structures with 1 or 2 fields. */
2634 int field_offset (int index
) const
2636 gdb_assert (index
< (sizeof (m_offsets
) / sizeof (m_offsets
[0])));
2637 return m_offsets
[index
];
2641 /* The number of scalar fields found within the structure after recursing
2642 into nested structures. */
2643 int m_number_of_fields
;
2645 /* The types of the first two scalar fields found within the structure
2646 after recursing into nested structures. */
2647 struct type
*m_types
[2];
2649 /* The offsets of the first two scalar fields found within the structure
2650 after recursing into nested structures. */
2653 /* Recursive core for ANALYSE, the OFFSET parameter tracks the byte
2654 offset from the start of the top level structure being analysed. */
2655 void analyse_inner (struct type
*type
, int offset
);
2658 /* See description in class declaration. */
2661 riscv_struct_info::analyse_inner (struct type
*type
, int offset
)
2663 unsigned int count
= type
->num_fields ();
2666 for (i
= 0; i
< count
; ++i
)
2668 if (type
->field (i
).loc_kind () != FIELD_LOC_KIND_BITPOS
)
2671 struct type
*field_type
= type
->field (i
).type ();
2672 field_type
= check_typedef (field_type
);
2674 = offset
+ type
->field (i
).loc_bitpos () / TARGET_CHAR_BIT
;
2676 switch (field_type
->code ())
2678 case TYPE_CODE_STRUCT
:
2679 analyse_inner (field_type
, field_offset
);
2683 /* RiscV only flattens out structures. Anything else does not
2684 need to be flattened, we just record the type, and when we
2685 look at the analysis results we'll realise this is not a
2686 structure we can special case, and pass the structure in
2688 if (m_number_of_fields
< 2)
2690 m_types
[m_number_of_fields
] = field_type
;
2691 m_offsets
[m_number_of_fields
] = field_offset
;
2693 m_number_of_fields
++;
2697 /* RiscV only has special handling for structures with 1 or 2 scalar
2698 fields, any more than that and the structure is just passed in
2699 memory. We can safely drop out early when we find 3 or more
2702 if (m_number_of_fields
> 2)
2707 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
2708 is a structure. Small structures on RiscV have some special case
2709 handling in order that the structure might be passed in register.
2710 Larger structures are passed in memory. After assigning location
2711 information to AINFO, CINFO will have been updated. */
2714 riscv_call_arg_struct (struct riscv_arg_info
*ainfo
,
2715 struct riscv_call_info
*cinfo
)
2717 if (riscv_arg_regs_available (&cinfo
->float_regs
) >= 1)
2719 struct riscv_struct_info sinfo
;
2721 sinfo
.analyse (ainfo
->type
);
2722 if (sinfo
.number_of_fields () == 1
2723 && sinfo
.field_type(0)->code () == TYPE_CODE_COMPLEX
)
2725 /* The following is similar to RISCV_CALL_ARG_COMPLEX_FLOAT,
2726 except we use the type of the complex field instead of the
2727 type from AINFO, and the first location might be at a non-zero
2729 if (sinfo
.field_type (0)->length () <= (2 * cinfo
->flen
)
2730 && riscv_arg_regs_available (&cinfo
->float_regs
) >= 2
2731 && !ainfo
->is_unnamed
)
2734 int len
= sinfo
.field_type (0)->length () / 2;
2735 int offset
= sinfo
.field_offset (0);
2737 result
= riscv_assign_reg_location (&ainfo
->argloc
[0],
2738 &cinfo
->float_regs
, len
,
2740 gdb_assert (result
);
2742 result
= riscv_assign_reg_location (&ainfo
->argloc
[1],
2743 &cinfo
->float_regs
, len
,
2745 gdb_assert (result
);
2748 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2752 if (sinfo
.number_of_fields () == 1
2753 && sinfo
.field_type(0)->code () == TYPE_CODE_FLT
)
2755 /* The following is similar to RISCV_CALL_ARG_SCALAR_FLOAT,
2756 except we use the type of the first scalar field instead of
2757 the type from AINFO. Also the location might be at a non-zero
2759 if (sinfo
.field_type (0)->length () > cinfo
->flen
2760 || ainfo
->is_unnamed
)
2761 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2764 int offset
= sinfo
.field_offset (0);
2765 int len
= sinfo
.field_type (0)->length ();
2767 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
2770 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2775 if (sinfo
.number_of_fields () == 2
2776 && sinfo
.field_type(0)->code () == TYPE_CODE_FLT
2777 && sinfo
.field_type (0)->length () <= cinfo
->flen
2778 && sinfo
.field_type(1)->code () == TYPE_CODE_FLT
2779 && sinfo
.field_type (1)->length () <= cinfo
->flen
2780 && riscv_arg_regs_available (&cinfo
->float_regs
) >= 2)
2782 int len0
= sinfo
.field_type (0)->length ();
2783 int offset
= sinfo
.field_offset (0);
2784 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
2785 &cinfo
->float_regs
, len0
, offset
))
2786 error (_("failed during argument setup"));
2788 int len1
= sinfo
.field_type (1)->length ();
2789 offset
= sinfo
.field_offset (1);
2790 gdb_assert (len1
<= (ainfo
->type
->length ()
2791 - sinfo
.field_type (0)->length ()));
2793 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
2796 error (_("failed during argument setup"));
2800 if (sinfo
.number_of_fields () == 2
2801 && riscv_arg_regs_available (&cinfo
->int_regs
) >= 1
2802 && (sinfo
.field_type(0)->code () == TYPE_CODE_FLT
2803 && sinfo
.field_type (0)->length () <= cinfo
->flen
2804 && is_integral_type (sinfo
.field_type (1))
2805 && sinfo
.field_type (1)->length () <= cinfo
->xlen
))
2807 int len0
= sinfo
.field_type (0)->length ();
2808 int offset
= sinfo
.field_offset (0);
2809 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
2810 &cinfo
->float_regs
, len0
, offset
))
2811 error (_("failed during argument setup"));
2813 int len1
= sinfo
.field_type (1)->length ();
2814 offset
= sinfo
.field_offset (1);
2815 gdb_assert (len1
<= cinfo
->xlen
);
2816 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
2817 &cinfo
->int_regs
, len1
, offset
))
2818 error (_("failed during argument setup"));
2822 if (sinfo
.number_of_fields () == 2
2823 && riscv_arg_regs_available (&cinfo
->int_regs
) >= 1
2824 && (is_integral_type (sinfo
.field_type (0))
2825 && sinfo
.field_type (0)->length () <= cinfo
->xlen
2826 && sinfo
.field_type(1)->code () == TYPE_CODE_FLT
2827 && sinfo
.field_type (1)->length () <= cinfo
->flen
))
2829 int len0
= sinfo
.field_type (0)->length ();
2830 int len1
= sinfo
.field_type (1)->length ();
2832 gdb_assert (len0
<= cinfo
->xlen
);
2833 gdb_assert (len1
<= cinfo
->flen
);
2835 int offset
= sinfo
.field_offset (0);
2836 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
2837 &cinfo
->int_regs
, len0
, offset
))
2838 error (_("failed during argument setup"));
2840 offset
= sinfo
.field_offset (1);
2841 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
2844 error (_("failed during argument setup"));
2850 /* Non of the structure flattening cases apply, so we just pass using
2852 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2855 /* Assign a location to call (or return) argument AINFO, the location is
2856 selected from CINFO which holds information about what call argument
2857 locations are available for use next. The TYPE is the type of the
2858 argument being passed, this information is recorded into AINFO (along
2859 with some additional information derived from the type). IS_UNNAMED
2860 is true if this is an unnamed (stdarg) argument, this info is also
2861 recorded into AINFO.
2863 After assigning a location to AINFO, CINFO will have been updated. */
2866 riscv_arg_location (struct gdbarch
*gdbarch
,
2867 struct riscv_arg_info
*ainfo
,
2868 struct riscv_call_info
*cinfo
,
2869 struct type
*type
, bool is_unnamed
)
2872 ainfo
->length
= ainfo
->type
->length ();
2873 ainfo
->align
= type_align (ainfo
->type
);
2874 ainfo
->is_unnamed
= is_unnamed
;
2875 ainfo
->contents
= nullptr;
2876 ainfo
->argloc
[0].c_length
= 0;
2877 ainfo
->argloc
[1].c_length
= 0;
2879 switch (ainfo
->type
->code ())
2882 case TYPE_CODE_BOOL
:
2883 case TYPE_CODE_CHAR
:
2884 case TYPE_CODE_RANGE
:
2885 case TYPE_CODE_ENUM
:
2887 case TYPE_CODE_FIXED_POINT
:
2888 if (ainfo
->length
<= cinfo
->xlen
)
2890 ainfo
->type
= builtin_type (gdbarch
)->builtin_long
;
2891 ainfo
->length
= cinfo
->xlen
;
2893 else if (ainfo
->length
<= (2 * cinfo
->xlen
))
2895 ainfo
->type
= builtin_type (gdbarch
)->builtin_long_long
;
2896 ainfo
->length
= 2 * cinfo
->xlen
;
2899 /* Recalculate the alignment requirement. */
2900 ainfo
->align
= type_align (ainfo
->type
);
2901 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2905 riscv_call_arg_scalar_float (ainfo
, cinfo
);
2908 case TYPE_CODE_COMPLEX
:
2909 riscv_call_arg_complex_float (ainfo
, cinfo
);
2912 case TYPE_CODE_STRUCT
:
2913 if (!TYPE_HAS_DYNAMIC_LENGTH (ainfo
->type
))
2915 riscv_call_arg_struct (ainfo
, cinfo
);
2921 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2926 /* Used for printing debug information about the call argument location in
2927 INFO to STREAM. The addresses in SP_REFS and SP_ARGS are the base
2928 addresses for the location of pass-by-reference and
2929 arguments-on-the-stack memory areas. */
2932 riscv_print_arg_location (ui_file
*stream
, struct gdbarch
*gdbarch
,
2933 struct riscv_arg_info
*info
,
2934 CORE_ADDR sp_refs
, CORE_ADDR sp_args
)
2936 gdb_printf (stream
, "type: '%s', length: 0x%x, alignment: 0x%x",
2937 TYPE_SAFE_NAME (info
->type
), info
->length
, info
->align
);
2938 switch (info
->argloc
[0].loc_type
)
2940 case riscv_arg_info::location::in_reg
:
2942 (stream
, ", register %s",
2943 gdbarch_register_name (gdbarch
, info
->argloc
[0].loc_data
.regno
));
2944 if (info
->argloc
[0].c_length
< info
->length
)
2946 switch (info
->argloc
[1].loc_type
)
2948 case riscv_arg_info::location::in_reg
:
2950 (stream
, ", register %s",
2951 gdbarch_register_name (gdbarch
,
2952 info
->argloc
[1].loc_data
.regno
));
2955 case riscv_arg_info::location::on_stack
:
2956 gdb_printf (stream
, ", on stack at offset 0x%x",
2957 info
->argloc
[1].loc_data
.offset
);
2960 case riscv_arg_info::location::by_ref
:
2962 /* The second location should never be a reference, any
2963 argument being passed by reference just places its address
2964 in the first location and is done. */
2965 error (_("invalid argument location"));
2969 if (info
->argloc
[1].c_offset
> info
->argloc
[0].c_length
)
2970 gdb_printf (stream
, " (offset 0x%x)",
2971 info
->argloc
[1].c_offset
);
2975 case riscv_arg_info::location::on_stack
:
2976 gdb_printf (stream
, ", on stack at offset 0x%x",
2977 info
->argloc
[0].loc_data
.offset
);
2980 case riscv_arg_info::location::by_ref
:
2982 (stream
, ", by reference, data at offset 0x%x (%s)",
2983 info
->argloc
[0].loc_data
.offset
,
2984 core_addr_to_string (sp_refs
+ info
->argloc
[0].loc_data
.offset
));
2985 if (info
->argloc
[1].loc_type
2986 == riscv_arg_info::location::in_reg
)
2988 (stream
, ", address in register %s",
2989 gdbarch_register_name (gdbarch
, info
->argloc
[1].loc_data
.regno
));
2992 gdb_assert (info
->argloc
[1].loc_type
2993 == riscv_arg_info::location::on_stack
);
2995 (stream
, ", address on stack at offset 0x%x (%s)",
2996 info
->argloc
[1].loc_data
.offset
,
2997 core_addr_to_string (sp_args
+ info
->argloc
[1].loc_data
.offset
));
3002 gdb_assert_not_reached ("unknown argument location type");
3006 /* Wrapper around REGCACHE->cooked_write. Places the LEN bytes of DATA
3007 into a buffer that is at least as big as the register REGNUM, padding
3008 out the DATA with either 0x00, or 0xff. For floating point registers
3009 0xff is used, for everyone else 0x00 is used. */
3012 riscv_regcache_cooked_write (int regnum
, const gdb_byte
*data
, int len
,
3013 struct regcache
*regcache
, int flen
)
3015 gdb_byte tmp
[sizeof (ULONGEST
)];
3017 /* FP values in FP registers must be NaN-boxed. */
3018 if (riscv_is_fp_regno_p (regnum
) && len
< flen
)
3019 memset (tmp
, -1, sizeof (tmp
));
3021 memset (tmp
, 0, sizeof (tmp
));
3022 memcpy (tmp
, data
, len
);
3023 regcache
->cooked_write (regnum
, tmp
);
3026 /* Implement the push dummy call gdbarch callback. */
3029 riscv_push_dummy_call (struct gdbarch
*gdbarch
,
3030 struct value
*function
,
3031 struct regcache
*regcache
,
3034 struct value
**args
,
3036 function_call_return_method return_method
,
3037 CORE_ADDR struct_addr
)
3040 CORE_ADDR sp_args
, sp_refs
;
3041 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3043 struct riscv_arg_info
*arg_info
=
3044 (struct riscv_arg_info
*) alloca (nargs
* sizeof (struct riscv_arg_info
));
3046 struct riscv_call_info
call_info (gdbarch
);
3050 struct type
*ftype
= check_typedef (function
->type ());
3052 if (ftype
->code () == TYPE_CODE_PTR
)
3053 ftype
= check_typedef (ftype
->target_type ());
3055 /* We'll use register $a0 if we're returning a struct. */
3056 if (return_method
== return_method_struct
)
3057 ++call_info
.int_regs
.next_regnum
;
3059 for (i
= 0; i
< nargs
; ++i
)
3061 struct value
*arg_value
;
3062 struct type
*arg_type
;
3063 struct riscv_arg_info
*info
= &arg_info
[i
];
3065 arg_value
= args
[i
];
3066 arg_type
= check_typedef (arg_value
->type ());
3068 riscv_arg_location (gdbarch
, info
, &call_info
, arg_type
,
3069 ftype
->has_varargs () && i
>= ftype
->num_fields ());
3071 if (info
->type
!= arg_type
)
3072 arg_value
= value_cast (info
->type
, arg_value
);
3073 info
->contents
= value_contents (arg_value
).data ();
3076 /* Adjust the stack pointer and align it. */
3077 sp
= sp_refs
= align_down (sp
- call_info
.memory
.ref_offset
, SP_ALIGNMENT
);
3078 sp
= sp_args
= align_down (sp
- call_info
.memory
.arg_offset
, SP_ALIGNMENT
);
3080 if (riscv_debug_infcall
> 0)
3082 gdb_printf (gdb_stdlog
, "dummy call args:\n");
3083 gdb_printf (gdb_stdlog
, ": floating point ABI %s in use\n",
3084 (riscv_has_fp_abi (gdbarch
) ? "is" : "is not"));
3085 gdb_printf (gdb_stdlog
, ": xlen: %d\n: flen: %d\n",
3086 call_info
.xlen
, call_info
.flen
);
3087 if (return_method
== return_method_struct
)
3088 gdb_printf (gdb_stdlog
,
3089 "[*] struct return pointer in register $A0\n");
3090 for (i
= 0; i
< nargs
; ++i
)
3092 struct riscv_arg_info
*info
= &arg_info
[i
];
3094 gdb_printf (gdb_stdlog
, "[%2d] ", i
);
3095 riscv_print_arg_location (gdb_stdlog
, gdbarch
, info
, sp_refs
, sp_args
);
3096 gdb_printf (gdb_stdlog
, "\n");
3098 if (call_info
.memory
.arg_offset
> 0
3099 || call_info
.memory
.ref_offset
> 0)
3101 gdb_printf (gdb_stdlog
, " Original sp: %s\n",
3102 core_addr_to_string (osp
));
3103 gdb_printf (gdb_stdlog
, "Stack required (for args): 0x%x\n",
3104 call_info
.memory
.arg_offset
);
3105 gdb_printf (gdb_stdlog
, "Stack required (for refs): 0x%x\n",
3106 call_info
.memory
.ref_offset
);
3107 gdb_printf (gdb_stdlog
, " Stack allocated: %s\n",
3108 core_addr_to_string_nz (osp
- sp
));
3112 /* Now load the argument into registers, or onto the stack. */
3114 if (return_method
== return_method_struct
)
3116 gdb_byte buf
[sizeof (LONGEST
)];
3118 store_unsigned_integer (buf
, call_info
.xlen
, byte_order
, struct_addr
);
3119 regcache
->cooked_write (RISCV_A0_REGNUM
, buf
);
3122 for (i
= 0; i
< nargs
; ++i
)
3125 int second_arg_length
= 0;
3126 const gdb_byte
*second_arg_data
;
3127 struct riscv_arg_info
*info
= &arg_info
[i
];
3129 gdb_assert (info
->length
> 0);
3131 switch (info
->argloc
[0].loc_type
)
3133 case riscv_arg_info::location::in_reg
:
3135 gdb_assert (info
->argloc
[0].c_length
<= info
->length
);
3137 riscv_regcache_cooked_write (info
->argloc
[0].loc_data
.regno
,
3139 + info
->argloc
[0].c_offset
),
3140 info
->argloc
[0].c_length
,
3141 regcache
, call_info
.flen
);
3143 (((info
->argloc
[0].c_length
+ info
->argloc
[0].c_offset
) < info
->length
)
3144 ? info
->argloc
[1].c_length
: 0);
3145 second_arg_data
= info
->contents
+ info
->argloc
[1].c_offset
;
3149 case riscv_arg_info::location::on_stack
:
3150 dst
= sp_args
+ info
->argloc
[0].loc_data
.offset
;
3151 write_memory (dst
, info
->contents
, info
->length
);
3152 second_arg_length
= 0;
3155 case riscv_arg_info::location::by_ref
:
3156 dst
= sp_refs
+ info
->argloc
[0].loc_data
.offset
;
3157 write_memory (dst
, info
->contents
, info
->length
);
3159 second_arg_length
= call_info
.xlen
;
3160 second_arg_data
= (gdb_byte
*) &dst
;
3164 gdb_assert_not_reached ("unknown argument location type");
3167 if (second_arg_length
> 0)
3169 switch (info
->argloc
[1].loc_type
)
3171 case riscv_arg_info::location::in_reg
:
3173 gdb_assert ((riscv_is_fp_regno_p (info
->argloc
[1].loc_data
.regno
)
3174 && second_arg_length
<= call_info
.flen
)
3175 || second_arg_length
<= call_info
.xlen
);
3176 riscv_regcache_cooked_write (info
->argloc
[1].loc_data
.regno
,
3179 regcache
, call_info
.flen
);
3183 case riscv_arg_info::location::on_stack
:
3187 arg_addr
= sp_args
+ info
->argloc
[1].loc_data
.offset
;
3188 write_memory (arg_addr
, second_arg_data
, second_arg_length
);
3192 case riscv_arg_info::location::by_ref
:
3194 /* The second location should never be a reference, any
3195 argument being passed by reference just places its address
3196 in the first location and is done. */
3197 error (_("invalid argument location"));
3203 /* Set the dummy return value to bp_addr.
3204 A dummy breakpoint will be setup to execute the call. */
3206 if (riscv_debug_infcall
> 0)
3207 gdb_printf (gdb_stdlog
, ": writing $ra = %s\n",
3208 core_addr_to_string (bp_addr
));
3209 regcache_cooked_write_unsigned (regcache
, RISCV_RA_REGNUM
, bp_addr
);
3211 /* Finally, update the stack pointer. */
3213 if (riscv_debug_infcall
> 0)
3214 gdb_printf (gdb_stdlog
, ": writing $sp = %s\n",
3215 core_addr_to_string (sp
));
3216 regcache_cooked_write_unsigned (regcache
, RISCV_SP_REGNUM
, sp
);
3221 /* Implement the return_value gdbarch method. */
3223 static enum return_value_convention
3224 riscv_return_value (struct gdbarch
*gdbarch
,
3225 struct value
*function
,
3227 struct regcache
*regcache
,
3228 struct value
**read_value
,
3229 const gdb_byte
*writebuf
)
3231 struct riscv_call_info
call_info (gdbarch
);
3232 struct riscv_arg_info info
;
3233 struct type
*arg_type
;
3235 arg_type
= check_typedef (type
);
3236 riscv_arg_location (gdbarch
, &info
, &call_info
, arg_type
, false);
3238 if (riscv_debug_infcall
> 0)
3240 gdb_printf (gdb_stdlog
, "riscv return value:\n");
3241 gdb_printf (gdb_stdlog
, "[R] ");
3242 riscv_print_arg_location (gdb_stdlog
, gdbarch
, &info
, 0, 0);
3243 gdb_printf (gdb_stdlog
, "\n");
3246 if (read_value
!= nullptr || writebuf
!= nullptr)
3248 unsigned int arg_len
;
3249 struct value
*abi_val
;
3250 gdb_byte
*readbuf
= nullptr;
3253 /* We only do one thing at a time. */
3254 gdb_assert (read_value
== nullptr || writebuf
== nullptr);
3256 /* In some cases the argument is not returned as the declared type,
3257 and we need to cast to or from the ABI type in order to
3258 correctly access the argument. When writing to the machine we
3259 do the cast here, when reading from the machine the cast occurs
3260 later, after extracting the value. As the ABI type can be
3261 larger than the declared type, then the read or write buffers
3262 passed in might be too small. Here we ensure that we are using
3263 buffers of sufficient size. */
3264 if (writebuf
!= nullptr)
3266 struct value
*arg_val
;
3268 if (is_fixed_point_type (arg_type
))
3270 /* Convert the argument to the type used to pass
3271 the return value, but being careful to preserve
3272 the fact that the value needs to be returned
3276 unscaled
.read (gdb::make_array_view (writebuf
,
3277 arg_type
->length ()),
3278 type_byte_order (arg_type
),
3279 arg_type
->is_unsigned ());
3280 abi_val
= value::allocate (info
.type
);
3281 unscaled
.write (abi_val
->contents_raw (),
3282 type_byte_order (info
.type
),
3283 info
.type
->is_unsigned ());
3287 arg_val
= value_from_contents (arg_type
, writebuf
);
3288 abi_val
= value_cast (info
.type
, arg_val
);
3290 writebuf
= abi_val
->contents_raw ().data ();
3294 abi_val
= value::allocate (info
.type
);
3295 readbuf
= abi_val
->contents_raw ().data ();
3297 arg_len
= info
.type
->length ();
3299 switch (info
.argloc
[0].loc_type
)
3301 /* Return value in register(s). */
3302 case riscv_arg_info::location::in_reg
:
3304 regnum
= info
.argloc
[0].loc_data
.regno
;
3305 gdb_assert (info
.argloc
[0].c_length
<= arg_len
);
3306 gdb_assert (info
.argloc
[0].c_length
3307 <= register_size (gdbarch
, regnum
));
3311 gdb_byte
*ptr
= readbuf
+ info
.argloc
[0].c_offset
;
3312 regcache
->cooked_read_part (regnum
, 0,
3313 info
.argloc
[0].c_length
,
3319 const gdb_byte
*ptr
= writebuf
+ info
.argloc
[0].c_offset
;
3320 riscv_regcache_cooked_write (regnum
, ptr
,
3321 info
.argloc
[0].c_length
,
3322 regcache
, call_info
.flen
);
3325 /* A return value in register can have a second part in a
3327 if (info
.argloc
[1].c_length
> 0)
3329 switch (info
.argloc
[1].loc_type
)
3331 case riscv_arg_info::location::in_reg
:
3332 regnum
= info
.argloc
[1].loc_data
.regno
;
3334 gdb_assert ((info
.argloc
[0].c_length
3335 + info
.argloc
[1].c_length
) <= arg_len
);
3336 gdb_assert (info
.argloc
[1].c_length
3337 <= register_size (gdbarch
, regnum
));
3341 readbuf
+= info
.argloc
[1].c_offset
;
3342 regcache
->cooked_read_part (regnum
, 0,
3343 info
.argloc
[1].c_length
,
3350 = writebuf
+ info
.argloc
[1].c_offset
;
3351 riscv_regcache_cooked_write
3352 (regnum
, ptr
, info
.argloc
[1].c_length
,
3353 regcache
, call_info
.flen
);
3357 case riscv_arg_info::location::by_ref
:
3358 case riscv_arg_info::location::on_stack
:
3360 error (_("invalid argument location"));
3367 /* Return value by reference will have its address in A0. */
3368 case riscv_arg_info::location::by_ref
:
3372 regcache_cooked_read_unsigned (regcache
, RISCV_A0_REGNUM
,
3374 if (read_value
!= nullptr)
3376 abi_val
= value_at_non_lval (type
, addr
);
3377 /* Also reset the expected type, so that the cast
3378 later on is a no-op. If the cast is not a no-op,
3379 and if the return type is variably-sized, then the
3380 type of ABI_VAL will differ from ARG_TYPE due to
3381 dynamic type resolution, and so will most likely
3383 arg_type
= abi_val
->type ();
3385 if (writebuf
!= nullptr)
3386 write_memory (addr
, writebuf
, info
.length
);
3390 case riscv_arg_info::location::on_stack
:
3392 error (_("invalid argument location"));
3396 /* This completes the cast from abi type back to the declared type
3397 in the case that we are reading from the machine. See the
3398 comment at the head of this block for more details. */
3399 if (read_value
!= nullptr)
3401 if (is_fixed_point_type (arg_type
))
3403 /* Convert abi_val to the actual return type, but
3404 being careful to preserve the fact that abi_val
3408 unscaled
.read (value_contents (abi_val
),
3409 type_byte_order (info
.type
),
3410 info
.type
->is_unsigned ());
3411 *read_value
= value::allocate (arg_type
);
3412 unscaled
.write ((*read_value
)->contents_raw (),
3413 type_byte_order (arg_type
),
3414 arg_type
->is_unsigned ());
3417 *read_value
= value_cast (arg_type
, abi_val
);
3421 switch (info
.argloc
[0].loc_type
)
3423 case riscv_arg_info::location::in_reg
:
3424 return RETURN_VALUE_REGISTER_CONVENTION
;
3425 case riscv_arg_info::location::by_ref
:
3426 return RETURN_VALUE_ABI_PRESERVES_ADDRESS
;
3427 case riscv_arg_info::location::on_stack
:
3429 error (_("invalid argument location"));
3433 /* Implement the frame_align gdbarch method. */
3436 riscv_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
3438 return align_down (addr
, 16);
3441 /* Generate, or return the cached frame cache for the RiscV frame
3444 static struct riscv_unwind_cache
*
3445 riscv_frame_cache (frame_info_ptr this_frame
, void **this_cache
)
3447 CORE_ADDR pc
, start_addr
;
3448 struct riscv_unwind_cache
*cache
;
3449 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3452 if ((*this_cache
) != NULL
)
3453 return (struct riscv_unwind_cache
*) *this_cache
;
3455 cache
= FRAME_OBSTACK_ZALLOC (struct riscv_unwind_cache
);
3456 cache
->regs
= trad_frame_alloc_saved_regs (this_frame
);
3457 (*this_cache
) = cache
;
3459 /* Scan the prologue, filling in the cache. */
3460 start_addr
= get_frame_func (this_frame
);
3461 pc
= get_frame_pc (this_frame
);
3462 riscv_scan_prologue (gdbarch
, start_addr
, pc
, cache
);
3464 /* We can now calculate the frame base address. */
3466 = (get_frame_register_unsigned (this_frame
, cache
->frame_base_reg
)
3467 + cache
->frame_base_offset
);
3468 if (riscv_debug_unwinder
)
3469 gdb_printf (gdb_stdlog
, "Frame base is %s ($%s + 0x%x)\n",
3470 core_addr_to_string (cache
->frame_base
),
3471 gdbarch_register_name (gdbarch
,
3472 cache
->frame_base_reg
),
3473 cache
->frame_base_offset
);
3475 /* The prologue scanner sets the address of registers stored to the stack
3476 as the offset of that register from the frame base. The prologue
3477 scanner doesn't know the actual frame base value, and so is unable to
3478 compute the exact address. We do now know the frame base value, so
3479 update the address of registers stored to the stack. */
3480 numregs
= gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
3481 for (regno
= 0; regno
< numregs
; ++regno
)
3483 if (cache
->regs
[regno
].is_addr ())
3484 cache
->regs
[regno
].set_addr (cache
->regs
[regno
].addr ()
3485 + cache
->frame_base
);
3488 /* The previous $pc can be found wherever the $ra value can be found.
3489 The previous $ra value is gone, this would have been stored be the
3490 previous frame if required. */
3491 cache
->regs
[gdbarch_pc_regnum (gdbarch
)] = cache
->regs
[RISCV_RA_REGNUM
];
3492 cache
->regs
[RISCV_RA_REGNUM
].set_unknown ();
3494 /* Build the frame id. */
3495 cache
->this_id
= frame_id_build (cache
->frame_base
, start_addr
);
3497 /* The previous $sp value is the frame base value. */
3498 cache
->regs
[gdbarch_sp_regnum (gdbarch
)].set_value (cache
->frame_base
);
3503 /* Implement the this_id callback for RiscV frame unwinder. */
3506 riscv_frame_this_id (frame_info_ptr this_frame
,
3507 void **prologue_cache
,
3508 struct frame_id
*this_id
)
3510 struct riscv_unwind_cache
*cache
;
3514 cache
= riscv_frame_cache (this_frame
, prologue_cache
);
3515 *this_id
= cache
->this_id
;
3517 catch (const gdb_exception_error
&ex
)
3519 /* Ignore errors, this leaves the frame id as the predefined outer
3520 frame id which terminates the backtrace at this point. */
3524 /* Implement the prev_register callback for RiscV frame unwinder. */
3526 static struct value
*
3527 riscv_frame_prev_register (frame_info_ptr this_frame
,
3528 void **prologue_cache
,
3531 struct riscv_unwind_cache
*cache
;
3533 cache
= riscv_frame_cache (this_frame
, prologue_cache
);
3534 return trad_frame_get_prev_register (this_frame
, cache
->regs
, regnum
);
3537 /* Structure defining the RiscV normal frame unwind functions. Since we
3538 are the fallback unwinder (DWARF unwinder is used first), we use the
3539 default frame sniffer, which always accepts the frame. */
3541 static const struct frame_unwind riscv_frame_unwind
=
3543 /*.name =*/ "riscv prologue",
3544 /*.type =*/ NORMAL_FRAME
,
3545 /*.stop_reason =*/ default_frame_unwind_stop_reason
,
3546 /*.this_id =*/ riscv_frame_this_id
,
3547 /*.prev_register =*/ riscv_frame_prev_register
,
3548 /*.unwind_data =*/ NULL
,
3549 /*.sniffer =*/ default_frame_sniffer
,
3550 /*.dealloc_cache =*/ NULL
,
3551 /*.prev_arch =*/ NULL
,
3554 /* Extract a set of required target features out of ABFD. If ABFD is
3555 nullptr then a RISCV_GDBARCH_FEATURES is returned in its default state. */
3557 static struct riscv_gdbarch_features
3558 riscv_features_from_bfd (const bfd
*abfd
)
3560 struct riscv_gdbarch_features features
;
3562 /* Now try to improve on the defaults by looking at the binary we are
3563 going to execute. We assume the user knows what they are doing and
3564 that the target will match the binary. Remember, this code path is
3565 only used at all if the target hasn't given us a description, so this
3566 is really a last ditched effort to do something sane before giving
3568 if (abfd
!= nullptr && bfd_get_flavour (abfd
) == bfd_target_elf_flavour
)
3570 unsigned char eclass
= elf_elfheader (abfd
)->e_ident
[EI_CLASS
];
3571 int e_flags
= elf_elfheader (abfd
)->e_flags
;
3573 if (eclass
== ELFCLASS32
)
3575 else if (eclass
== ELFCLASS64
)
3578 internal_error (_("unknown ELF header class %d"), eclass
);
3580 if (e_flags
& EF_RISCV_FLOAT_ABI_DOUBLE
)
3582 else if (e_flags
& EF_RISCV_FLOAT_ABI_SINGLE
)
3585 if (e_flags
& EF_RISCV_RVE
)
3587 if (features
.xlen
== 8)
3589 warning (_("64-bit ELF with RV32E flag set! Assuming 32-bit"));
3592 features
.embedded
= true;
3599 /* Find a suitable default target description. Use the contents of INFO,
3600 specifically the bfd object being executed, to guide the selection of a
3601 suitable default target description. */
3603 static const struct target_desc
*
3604 riscv_find_default_target_description (const struct gdbarch_info info
)
3606 /* Extract desired feature set from INFO. */
3607 struct riscv_gdbarch_features features
3608 = riscv_features_from_bfd (info
.abfd
);
3610 /* If the XLEN field is still 0 then we got nothing useful from INFO.BFD,
3611 maybe there was no bfd object. In this case we fall back to a minimal
3612 useful target with no floating point, the x-register size is selected
3613 based on the architecture from INFO. */
3614 if (features
.xlen
== 0)
3615 features
.xlen
= info
.bfd_arch_info
->bits_per_word
== 32 ? 4 : 8;
3617 /* Now build a target description based on the feature set. */
3618 return riscv_lookup_target_description (features
);
3621 /* Add all the RISC-V specific register groups into GDBARCH. */
3624 riscv_add_reggroups (struct gdbarch
*gdbarch
)
3626 reggroup_add (gdbarch
, csr_reggroup
);
3629 /* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
3632 riscv_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
3634 if (reg
<= RISCV_DWARF_REGNUM_X31
)
3635 return RISCV_ZERO_REGNUM
+ (reg
- RISCV_DWARF_REGNUM_X0
);
3637 else if (reg
<= RISCV_DWARF_REGNUM_F31
)
3638 return RISCV_FIRST_FP_REGNUM
+ (reg
- RISCV_DWARF_REGNUM_F0
);
3640 else if (reg
>= RISCV_DWARF_FIRST_CSR
&& reg
<= RISCV_DWARF_LAST_CSR
)
3641 return RISCV_FIRST_CSR_REGNUM
+ (reg
- RISCV_DWARF_FIRST_CSR
);
3643 else if (reg
>= RISCV_DWARF_REGNUM_V0
&& reg
<= RISCV_DWARF_REGNUM_V31
)
3644 return RISCV_V0_REGNUM
+ (reg
- RISCV_DWARF_REGNUM_V0
);
3649 /* Implement the gcc_target_options method. We have to select the arch and abi
3650 from the feature info. We have enough feature info to select the abi, but
3651 not enough info for the arch given all of the possible architecture
3652 extensions. So choose reasonable defaults for now. */
3655 riscv_gcc_target_options (struct gdbarch
*gdbarch
)
3657 int isa_xlen
= riscv_isa_xlen (gdbarch
);
3658 int isa_flen
= riscv_isa_flen (gdbarch
);
3659 int abi_xlen
= riscv_abi_xlen (gdbarch
);
3660 int abi_flen
= riscv_abi_flen (gdbarch
);
3661 std::string target_options
;
3663 target_options
= "-march=rv";
3665 target_options
+= "64";
3667 target_options
+= "32";
3669 target_options
+= "gc";
3670 else if (isa_flen
== 4)
3671 target_options
+= "imafc";
3673 target_options
+= "imac";
3675 target_options
+= " -mabi=";
3677 target_options
+= "lp64";
3679 target_options
+= "ilp32";
3681 target_options
+= "d";
3682 else if (abi_flen
== 4)
3683 target_options
+= "f";
3685 /* The gdb loader doesn't handle link-time relaxation relocations. */
3686 target_options
+= " -mno-relax";
3688 return target_options
;
3691 /* Call back from tdesc_use_registers, called for each unknown register
3692 found in the target description.
3694 See target-description.h (typedef tdesc_unknown_register_ftype) for a
3695 discussion of the arguments and return values. */
3698 riscv_tdesc_unknown_reg (struct gdbarch
*gdbarch
, tdesc_feature
*feature
,
3699 const char *reg_name
, int possible_regnum
)
3701 /* At one point in time GDB had an incorrect default target description
3702 that duplicated the fflags, frm, and fcsr registers in both the FPU
3703 and CSR register sets.
3705 Some targets (QEMU) copied these target descriptions into their source
3706 tree, and so we're now stuck working with some versions of QEMU that
3707 declare the same registers twice.
3709 To make matters worse, if GDB tries to read or write to these
3710 registers using the register number assigned in the FPU feature set,
3711 then QEMU will fail to read the register, so we must use the register
3712 number declared in the CSR feature set.
3714 Luckily, GDB scans the FPU feature first, and then the CSR feature,
3715 which means that the CSR feature will be the one we end up using, the
3716 versions of these registers in the FPU feature will appear as unknown
3717 registers and will be passed through to this code.
3719 To prevent these duplicate registers showing up in any of the register
3720 lists, and to prevent GDB every trying to access the FPU feature copies,
3721 we spot the three problematic registers here, and record the register
3722 number that GDB has assigned them. Then in riscv_register_name we will
3723 return no name for the three duplicates, this hides the duplicates from
3725 if (strcmp (tdesc_feature_name (feature
), riscv_freg_feature
.name ()) == 0)
3727 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
3728 int *regnum_ptr
= nullptr;
3730 if (strcmp (reg_name
, "fflags") == 0)
3731 regnum_ptr
= &tdep
->duplicate_fflags_regnum
;
3732 else if (strcmp (reg_name
, "frm") == 0)
3733 regnum_ptr
= &tdep
->duplicate_frm_regnum
;
3734 else if (strcmp (reg_name
, "fcsr") == 0)
3735 regnum_ptr
= &tdep
->duplicate_fcsr_regnum
;
3737 if (regnum_ptr
!= nullptr)
3739 /* This means the register appears more than twice in the target
3740 description. Just let GDB add this as another register.
3741 We'll have duplicates in the register name list, but there's
3742 not much more we can do. */
3743 if (*regnum_ptr
!= -1)
3746 /* Record the number assigned to this register, then return the
3747 number (so it actually gets assigned to this register). */
3748 *regnum_ptr
= possible_regnum
;
3749 return possible_regnum
;
3753 /* Any unknown registers in the CSR feature are recorded within a single
3754 block so we can easily identify these registers when making choices
3755 about register groups in riscv_register_reggroup_p. */
3756 if (strcmp (tdesc_feature_name (feature
), riscv_csr_feature
.name ()) == 0)
3758 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
3759 if (tdep
->unknown_csrs_first_regnum
== -1)
3760 tdep
->unknown_csrs_first_regnum
= possible_regnum
;
3761 gdb_assert (tdep
->unknown_csrs_first_regnum
3762 + tdep
->unknown_csrs_count
== possible_regnum
);
3763 tdep
->unknown_csrs_count
++;
3764 return possible_regnum
;
3767 /* Some other unknown register. Don't assign this a number now, it will
3768 be assigned a number automatically later by the target description
3773 /* Implement the gnu_triplet_regexp method. A single compiler supports both
3774 32-bit and 64-bit code, and may be named riscv32 or riscv64 or (not
3775 recommended) riscv. */
3778 riscv_gnu_triplet_regexp (struct gdbarch
*gdbarch
)
3780 return "riscv(32|64)?";
3783 /* Initialize the current architecture based on INFO. If possible,
3784 re-use an architecture from ARCHES, which is a list of
3785 architectures already created during this debugging session.
3787 Called e.g. at program startup, when reading a core file, and when
3788 reading a binary file. */
3790 static struct gdbarch
*
3791 riscv_gdbarch_init (struct gdbarch_info info
,
3792 struct gdbarch_list
*arches
)
3794 struct riscv_gdbarch_features features
;
3795 const struct target_desc
*tdesc
= info
.target_desc
;
3797 /* Ensure we always have a target description. */
3798 if (!tdesc_has_registers (tdesc
))
3799 tdesc
= riscv_find_default_target_description (info
);
3800 gdb_assert (tdesc
!= nullptr);
3802 if (riscv_debug_gdbarch
)
3803 gdb_printf (gdb_stdlog
, "Have got a target description\n");
3805 tdesc_arch_data_up tdesc_data
= tdesc_data_alloc ();
3806 std::vector
<riscv_pending_register_alias
> pending_aliases
;
3808 bool valid_p
= (riscv_xreg_feature
.check (tdesc
, tdesc_data
.get (),
3809 &pending_aliases
, &features
)
3810 && riscv_freg_feature
.check (tdesc
, tdesc_data
.get (),
3811 &pending_aliases
, &features
)
3812 && riscv_virtual_feature
.check (tdesc
, tdesc_data
.get (),
3813 &pending_aliases
, &features
)
3814 && riscv_csr_feature
.check (tdesc
, tdesc_data
.get (),
3815 &pending_aliases
, &features
)
3816 && riscv_vector_feature
.check (tdesc
, tdesc_data
.get (),
3817 &pending_aliases
, &features
));
3820 if (riscv_debug_gdbarch
)
3821 gdb_printf (gdb_stdlog
, "Target description is not valid\n");
3825 if (tdesc_found_register (tdesc_data
.get (), RISCV_CSR_FFLAGS_REGNUM
))
3826 features
.has_fflags_reg
= true;
3827 if (tdesc_found_register (tdesc_data
.get (), RISCV_CSR_FRM_REGNUM
))
3828 features
.has_frm_reg
= true;
3829 if (tdesc_found_register (tdesc_data
.get (), RISCV_CSR_FCSR_REGNUM
))
3830 features
.has_fcsr_reg
= true;
3832 /* Have a look at what the supplied (if any) bfd object requires of the
3833 target, then check that this matches with what the target is
3835 struct riscv_gdbarch_features abi_features
3836 = riscv_features_from_bfd (info
.abfd
);
3838 /* If the ABI_FEATURES xlen is 0 then this indicates we got no useful abi
3839 features from the INFO object. In this case we just treat the
3840 hardware features as defining the abi. */
3841 if (abi_features
.xlen
== 0)
3842 abi_features
= features
;
3844 /* In theory a binary compiled for RV32 could run on an RV64 target,
3845 however, this has not been tested in GDB yet, so for now we require
3846 that the requested xlen match the targets xlen. */
3847 if (abi_features
.xlen
!= features
.xlen
)
3848 error (_("bfd requires xlen %d, but target has xlen %d"),
3849 abi_features
.xlen
, features
.xlen
);
3850 /* We do support running binaries compiled for 32-bit float on targets
3851 with 64-bit float, so we only complain if the binary requires more
3852 than the target has available. */
3853 if (abi_features
.flen
> features
.flen
)
3854 error (_("bfd requires flen %d, but target has flen %d"),
3855 abi_features
.flen
, features
.flen
);
3857 /* Find a candidate among the list of pre-declared architectures. */
3858 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
3860 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
3862 /* Check that the feature set of the ARCHES matches the feature set
3863 we are looking for. If it doesn't then we can't reuse this
3865 riscv_gdbarch_tdep
*other_tdep
3866 = gdbarch_tdep
<riscv_gdbarch_tdep
> (arches
->gdbarch
);
3868 if (other_tdep
->isa_features
!= features
3869 || other_tdep
->abi_features
!= abi_features
)
3876 return arches
->gdbarch
;
3878 /* None found, so create a new architecture from the information provided. */
3880 = gdbarch_alloc (&info
, gdbarch_tdep_up (new riscv_gdbarch_tdep
));
3881 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
3883 tdep
->isa_features
= features
;
3884 tdep
->abi_features
= abi_features
;
3886 /* Target data types. */
3887 set_gdbarch_short_bit (gdbarch
, 16);
3888 set_gdbarch_int_bit (gdbarch
, 32);
3889 set_gdbarch_long_bit (gdbarch
, riscv_isa_xlen (gdbarch
) * 8);
3890 set_gdbarch_long_long_bit (gdbarch
, 64);
3891 set_gdbarch_float_bit (gdbarch
, 32);
3892 set_gdbarch_double_bit (gdbarch
, 64);
3893 set_gdbarch_long_double_bit (gdbarch
, 128);
3894 set_gdbarch_long_double_format (gdbarch
, floatformats_ieee_quad
);
3895 set_gdbarch_ptr_bit (gdbarch
, riscv_isa_xlen (gdbarch
) * 8);
3896 set_gdbarch_char_signed (gdbarch
, 0);
3897 set_gdbarch_type_align (gdbarch
, riscv_type_align
);
3899 /* Information about the target architecture. */
3900 set_gdbarch_return_value_as_value (gdbarch
, riscv_return_value
);
3901 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, riscv_breakpoint_kind_from_pc
);
3902 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, riscv_sw_breakpoint_from_kind
);
3903 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
3905 /* Functions to analyze frames. */
3906 set_gdbarch_skip_prologue (gdbarch
, riscv_skip_prologue
);
3907 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
3908 set_gdbarch_frame_align (gdbarch
, riscv_frame_align
);
3910 /* Functions handling dummy frames. */
3911 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
3912 set_gdbarch_push_dummy_code (gdbarch
, riscv_push_dummy_code
);
3913 set_gdbarch_push_dummy_call (gdbarch
, riscv_push_dummy_call
);
3915 /* Frame unwinders. Use DWARF debug info if available, otherwise use our own
3917 dwarf2_append_unwinders (gdbarch
);
3918 frame_unwind_append_unwinder (gdbarch
, &riscv_frame_unwind
);
3920 /* Register architecture. */
3921 riscv_add_reggroups (gdbarch
);
3923 /* Internal <-> external register number maps. */
3924 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, riscv_dwarf_reg_to_regnum
);
3926 /* We reserve all possible register numbers for the known registers.
3927 This means the target description mechanism will add any target
3928 specific registers after this number. This helps make debugging GDB
3929 just a little easier. */
3930 set_gdbarch_num_regs (gdbarch
, RISCV_LAST_REGNUM
+ 1);
3932 /* Some specific register numbers GDB likes to know about. */
3933 set_gdbarch_sp_regnum (gdbarch
, RISCV_SP_REGNUM
);
3934 set_gdbarch_pc_regnum (gdbarch
, RISCV_PC_REGNUM
);
3936 set_gdbarch_print_registers_info (gdbarch
, riscv_print_registers_info
);
3938 set_tdesc_pseudo_register_name (gdbarch
, riscv_pseudo_register_name
);
3939 set_tdesc_pseudo_register_type (gdbarch
, riscv_pseudo_register_type
);
3940 set_tdesc_pseudo_register_reggroup_p (gdbarch
,
3941 riscv_pseudo_register_reggroup_p
);
3942 set_gdbarch_pseudo_register_read (gdbarch
, riscv_pseudo_register_read
);
3943 set_gdbarch_pseudo_register_write (gdbarch
, riscv_pseudo_register_write
);
3945 /* Finalise the target description registers. */
3946 tdesc_use_registers (gdbarch
, tdesc
, std::move (tdesc_data
),
3947 riscv_tdesc_unknown_reg
);
3949 /* Calculate the number of pseudo registers we need. The fflags and frm
3950 registers are sub-fields of the fcsr CSR register (csr3). However,
3951 these registers can also be accessed directly as separate CSR
3952 registers (fflags is csr1, and frm is csr2). And so, some targets
3953 might choose to offer direct access to all three registers in the
3954 target description, while other targets might choose to only offer
3957 As we scan the target description we spot which of fcsr, fflags, and
3958 frm are available. If fcsr is available but either of fflags and/or
3959 frm are not available, then we add pseudo-registers to provide the
3960 missing functionality.
3962 This has to be done after the call to tdesc_use_registers as we don't
3963 know the final register number until after that call, and the pseudo
3964 register numbers need to be after the physical registers. */
3965 int num_pseudo_regs
= 0;
3966 int next_pseudo_regnum
= gdbarch_num_regs (gdbarch
);
3968 if (features
.has_fflags_reg
)
3969 tdep
->fflags_regnum
= RISCV_CSR_FFLAGS_REGNUM
;
3970 else if (features
.has_fcsr_reg
)
3972 tdep
->fflags_regnum
= next_pseudo_regnum
;
3973 pending_aliases
.emplace_back ("csr1", (void *) &tdep
->fflags_regnum
);
3974 next_pseudo_regnum
++;
3978 if (features
.has_frm_reg
)
3979 tdep
->frm_regnum
= RISCV_CSR_FRM_REGNUM
;
3980 else if (features
.has_fcsr_reg
)
3982 tdep
->frm_regnum
= next_pseudo_regnum
;
3983 pending_aliases
.emplace_back ("csr2", (void *) &tdep
->frm_regnum
);
3984 next_pseudo_regnum
++;
3988 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudo_regs
);
3990 /* Override the register type callback setup by the target description
3991 mechanism. This allows us to provide special type for floating point
3993 set_gdbarch_register_type (gdbarch
, riscv_register_type
);
3995 /* Override the register name callback setup by the target description
3996 mechanism. This allows us to force our preferred names for the
3997 registers, no matter what the target description called them. */
3998 set_gdbarch_register_name (gdbarch
, riscv_register_name
);
4000 /* Tell GDB which RISC-V registers are read-only. */
4001 set_gdbarch_cannot_store_register (gdbarch
, riscv_cannot_store_register
);
4003 /* Override the register group callback setup by the target description
4004 mechanism. This allows us to force registers into the groups we
4005 want, ignoring what the target tells us. */
4006 set_gdbarch_register_reggroup_p (gdbarch
, riscv_register_reggroup_p
);
4008 /* Create register aliases for alternative register names. We only
4009 create aliases for registers which were mentioned in the target
4011 for (const auto &alias
: pending_aliases
)
4012 alias
.create (gdbarch
);
4014 /* Compile command hooks. */
4015 set_gdbarch_gcc_target_options (gdbarch
, riscv_gcc_target_options
);
4016 set_gdbarch_gnu_triplet_regexp (gdbarch
, riscv_gnu_triplet_regexp
);
4018 /* Disassembler options support. */
4019 set_gdbarch_valid_disassembler_options (gdbarch
,
4020 disassembler_options_riscv ());
4021 set_gdbarch_disassembler_options (gdbarch
, &riscv_disassembler_options
);
4023 /* Hook in OS ABI-specific overrides, if they have been registered. */
4024 gdbarch_init_osabi (info
, gdbarch
);
4026 register_riscv_ravenscar_ops (gdbarch
);
4031 /* This decodes the current instruction and determines the address of the
4032 next instruction. */
4035 riscv_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
4037 struct gdbarch
*gdbarch
= regcache
->arch ();
4038 const riscv_gdbarch_tdep
*tdep
4039 = gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
4040 struct riscv_insn insn
;
4043 insn
.decode (gdbarch
, pc
);
4044 next_pc
= pc
+ insn
.length ();
4046 if (insn
.opcode () == riscv_insn::JAL
)
4047 next_pc
= pc
+ insn
.imm_signed ();
4048 else if (insn
.opcode () == riscv_insn::JALR
)
4051 regcache
->cooked_read (insn
.rs1 (), &source
);
4052 next_pc
= (source
+ insn
.imm_signed ()) & ~(CORE_ADDR
) 0x1;
4054 else if (insn
.opcode () == riscv_insn::BEQ
)
4057 regcache
->cooked_read (insn
.rs1 (), &src1
);
4058 regcache
->cooked_read (insn
.rs2 (), &src2
);
4060 next_pc
= pc
+ insn
.imm_signed ();
4062 else if (insn
.opcode () == riscv_insn::BNE
)
4065 regcache
->cooked_read (insn
.rs1 (), &src1
);
4066 regcache
->cooked_read (insn
.rs2 (), &src2
);
4068 next_pc
= pc
+ insn
.imm_signed ();
4070 else if (insn
.opcode () == riscv_insn::BLT
)
4073 regcache
->cooked_read (insn
.rs1 (), &src1
);
4074 regcache
->cooked_read (insn
.rs2 (), &src2
);
4076 next_pc
= pc
+ insn
.imm_signed ();
4078 else if (insn
.opcode () == riscv_insn::BGE
)
4081 regcache
->cooked_read (insn
.rs1 (), &src1
);
4082 regcache
->cooked_read (insn
.rs2 (), &src2
);
4084 next_pc
= pc
+ insn
.imm_signed ();
4086 else if (insn
.opcode () == riscv_insn::BLTU
)
4088 ULONGEST src1
, src2
;
4089 regcache
->cooked_read (insn
.rs1 (), &src1
);
4090 regcache
->cooked_read (insn
.rs2 (), &src2
);
4092 next_pc
= pc
+ insn
.imm_signed ();
4094 else if (insn
.opcode () == riscv_insn::BGEU
)
4096 ULONGEST src1
, src2
;
4097 regcache
->cooked_read (insn
.rs1 (), &src1
);
4098 regcache
->cooked_read (insn
.rs2 (), &src2
);
4100 next_pc
= pc
+ insn
.imm_signed ();
4102 else if (insn
.opcode () == riscv_insn::ECALL
)
4104 if (tdep
->syscall_next_pc
!= nullptr)
4105 next_pc
= tdep
->syscall_next_pc (get_current_frame ());
4111 /* We can't put a breakpoint in the middle of a lr/sc atomic sequence, so look
4112 for the end of the sequence and put the breakpoint there. */
4115 riscv_next_pc_atomic_sequence (struct regcache
*regcache
, CORE_ADDR pc
,
4118 struct gdbarch
*gdbarch
= regcache
->arch ();
4119 struct riscv_insn insn
;
4120 CORE_ADDR cur_step_pc
= pc
;
4121 CORE_ADDR last_addr
= 0;
4123 /* First instruction has to be a load reserved. */
4124 insn
.decode (gdbarch
, cur_step_pc
);
4125 if (insn
.opcode () != riscv_insn::LR
)
4127 cur_step_pc
= cur_step_pc
+ insn
.length ();
4129 /* Next instruction should be branch to exit. */
4130 insn
.decode (gdbarch
, cur_step_pc
);
4131 if (insn
.opcode () != riscv_insn::BNE
)
4133 last_addr
= cur_step_pc
+ insn
.imm_signed ();
4134 cur_step_pc
= cur_step_pc
+ insn
.length ();
4136 /* Next instruction should be store conditional. */
4137 insn
.decode (gdbarch
, cur_step_pc
);
4138 if (insn
.opcode () != riscv_insn::SC
)
4140 cur_step_pc
= cur_step_pc
+ insn
.length ();
4142 /* Next instruction should be branch to start. */
4143 insn
.decode (gdbarch
, cur_step_pc
);
4144 if (insn
.opcode () != riscv_insn::BNE
)
4146 if (pc
!= (cur_step_pc
+ insn
.imm_signed ()))
4148 cur_step_pc
= cur_step_pc
+ insn
.length ();
4150 /* We should now be at the end of the sequence. */
4151 if (cur_step_pc
!= last_addr
)
4154 *next_pc
= cur_step_pc
;
4158 /* This is called just before we want to resume the inferior, if we want to
4159 single-step it but there is no hardware or kernel single-step support. We
4160 find the target of the coming instruction and breakpoint it. */
4162 std::vector
<CORE_ADDR
>
4163 riscv_software_single_step (struct regcache
*regcache
)
4165 CORE_ADDR pc
, next_pc
;
4167 pc
= regcache_read_pc (regcache
);
4169 if (riscv_next_pc_atomic_sequence (regcache
, pc
, &next_pc
))
4172 next_pc
= riscv_next_pc (regcache
, pc
);
4177 /* Create RISC-V specific reggroups. */
4180 riscv_init_reggroups ()
4182 csr_reggroup
= reggroup_new ("csr", USER_REGGROUP
);
4185 /* See riscv-tdep.h. */
4188 riscv_supply_regset (const struct regset
*regset
,
4189 struct regcache
*regcache
, int regnum
,
4190 const void *regs
, size_t len
)
4192 regcache
->supply_regset (regset
, regnum
, regs
, len
);
4194 if (regnum
== -1 || regnum
== RISCV_ZERO_REGNUM
)
4195 regcache
->raw_supply_zeroed (RISCV_ZERO_REGNUM
);
4197 struct gdbarch
*gdbarch
= regcache
->arch ();
4198 riscv_gdbarch_tdep
*tdep
= gdbarch_tdep
<riscv_gdbarch_tdep
> (gdbarch
);
4201 || regnum
== tdep
->fflags_regnum
4202 || regnum
== tdep
->frm_regnum
)
4204 int fcsr_regnum
= RISCV_CSR_FCSR_REGNUM
;
4206 /* Ensure that FCSR has been read into REGCACHE. */
4208 regcache
->supply_regset (regset
, fcsr_regnum
, regs
, len
);
4210 /* Grab the FCSR value if it is now in the regcache. We must check
4211 the status first as, if the register was not supplied by REGSET,
4212 this call will trigger a recursive attempt to fetch the
4214 if (regcache
->get_register_status (fcsr_regnum
) == REG_VALID
)
4216 /* If we have an fcsr register then we should have fflags and frm
4217 too, either provided by the target, or provided as a pseudo
4219 gdb_assert (tdep
->fflags_regnum
>= 0);
4220 gdb_assert (tdep
->frm_regnum
>= 0);
4223 regcache
->raw_read (fcsr_regnum
, &fcsr_val
);
4225 /* Extract the fflags and frm values. */
4226 ULONGEST fflags_val
= fcsr_val
& 0x1f;
4227 ULONGEST frm_val
= (fcsr_val
>> 5) & 0x7;
4229 /* And supply these if needed. We can only supply real
4230 registers, so don't try to supply fflags or frm if they are
4231 implemented as pseudo-registers. */
4232 if ((regnum
== -1 || regnum
== tdep
->fflags_regnum
)
4233 && tdep
->fflags_regnum
< gdbarch_num_regs (gdbarch
))
4234 regcache
->raw_supply_integer (tdep
->fflags_regnum
,
4235 (gdb_byte
*) &fflags_val
,
4236 sizeof (fflags_val
),
4237 /* is_signed */ false);
4239 if ((regnum
== -1 || regnum
== tdep
->frm_regnum
)
4240 && tdep
->frm_regnum
< gdbarch_num_regs (gdbarch
))
4241 regcache
->raw_supply_integer (tdep
->frm_regnum
,
4242 (gdb_byte
*)&frm_val
,
4243 sizeof (fflags_val
),
4244 /* is_signed */ false);
4249 void _initialize_riscv_tdep ();
4251 _initialize_riscv_tdep ()
4253 riscv_init_reggroups ();
4255 gdbarch_register (bfd_arch_riscv
, riscv_gdbarch_init
, NULL
);
4257 /* Add root prefix command for all "set debug riscv" and "show debug
4259 add_setshow_prefix_cmd ("riscv", no_class
,
4260 _("RISC-V specific debug commands."),
4261 _("RISC-V specific debug commands."),
4262 &setdebugriscvcmdlist
, &showdebugriscvcmdlist
,
4263 &setdebuglist
, &showdebuglist
);
4265 add_setshow_zuinteger_cmd ("breakpoints", class_maintenance
,
4266 &riscv_debug_breakpoints
, _("\
4267 Set riscv breakpoint debugging."), _("\
4268 Show riscv breakpoint debugging."), _("\
4269 When non-zero, print debugging information for the riscv specific parts\n\
4270 of the breakpoint mechanism."),
4272 show_riscv_debug_variable
,
4273 &setdebugriscvcmdlist
, &showdebugriscvcmdlist
);
4275 add_setshow_zuinteger_cmd ("infcall", class_maintenance
,
4276 &riscv_debug_infcall
, _("\
4277 Set riscv inferior call debugging."), _("\
4278 Show riscv inferior call debugging."), _("\
4279 When non-zero, print debugging information for the riscv specific parts\n\
4280 of the inferior call mechanism."),
4282 show_riscv_debug_variable
,
4283 &setdebugriscvcmdlist
, &showdebugriscvcmdlist
);
4285 add_setshow_zuinteger_cmd ("unwinder", class_maintenance
,
4286 &riscv_debug_unwinder
, _("\
4287 Set riscv stack unwinding debugging."), _("\
4288 Show riscv stack unwinding debugging."), _("\
4289 When non-zero, print debugging information for the riscv specific parts\n\
4290 of the stack unwinding mechanism."),
4292 show_riscv_debug_variable
,
4293 &setdebugriscvcmdlist
, &showdebugriscvcmdlist
);
4295 add_setshow_zuinteger_cmd ("gdbarch", class_maintenance
,
4296 &riscv_debug_gdbarch
, _("\
4297 Set riscv gdbarch initialisation debugging."), _("\
4298 Show riscv gdbarch initialisation debugging."), _("\
4299 When non-zero, print debugging information for the riscv gdbarch\n\
4300 initialisation process."),
4302 show_riscv_debug_variable
,
4303 &setdebugriscvcmdlist
, &showdebugriscvcmdlist
);
4305 /* Add root prefix command for all "set riscv" and "show riscv" commands. */
4306 add_setshow_prefix_cmd ("riscv", no_class
,
4307 _("RISC-V specific commands."),
4308 _("RISC-V specific commands."),
4309 &setriscvcmdlist
, &showriscvcmdlist
,
4310 &setlist
, &showlist
);
4313 use_compressed_breakpoints
= AUTO_BOOLEAN_AUTO
;
4314 add_setshow_auto_boolean_cmd ("use-compressed-breakpoints", no_class
,
4315 &use_compressed_breakpoints
,
4317 Set debugger's use of compressed breakpoints."), _(" \
4318 Show debugger's use of compressed breakpoints."), _("\
4319 Debugging compressed code requires compressed breakpoints to be used. If\n\
4320 left to 'auto' then gdb will use them if the existing instruction is a\n\
4321 compressed instruction. If that doesn't give the correct behavior, then\n\
4322 this option can be used."),
4324 show_use_compressed_breakpoints
,