1 /* Target-dependent code for GDB, the GNU debugger.
3 Copyright (C) 1986-2021 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
29 #include "arch-utils.h"
32 #include "target-float.h"
34 #include "parser-defs.h"
37 #include "sim-regno.h"
38 #include "gdb/sim-ppc.h"
39 #include "reggroups.h"
40 #include "dwarf2/frame.h"
41 #include "target-descriptions.h"
42 #include "user-regs.h"
43 #include "record-full.h"
46 #include "coff/internal.h" /* for libcoff.h */
47 #include "libcoff.h" /* for xcoff_data */
48 #include "coff/xcoff.h"
53 #include "elf/ppc64.h"
55 #include "solib-svr4.h"
57 #include "ppc-ravenscar-thread.h"
61 #include "trad-frame.h"
62 #include "frame-unwind.h"
63 #include "frame-base.h"
69 #include "features/rs6000/powerpc-32.c"
70 #include "features/rs6000/powerpc-altivec32.c"
71 #include "features/rs6000/powerpc-vsx32.c"
72 #include "features/rs6000/powerpc-403.c"
73 #include "features/rs6000/powerpc-403gc.c"
74 #include "features/rs6000/powerpc-405.c"
75 #include "features/rs6000/powerpc-505.c"
76 #include "features/rs6000/powerpc-601.c"
77 #include "features/rs6000/powerpc-602.c"
78 #include "features/rs6000/powerpc-603.c"
79 #include "features/rs6000/powerpc-604.c"
80 #include "features/rs6000/powerpc-64.c"
81 #include "features/rs6000/powerpc-altivec64.c"
82 #include "features/rs6000/powerpc-vsx64.c"
83 #include "features/rs6000/powerpc-7400.c"
84 #include "features/rs6000/powerpc-750.c"
85 #include "features/rs6000/powerpc-860.c"
86 #include "features/rs6000/powerpc-e500.c"
87 #include "features/rs6000/rs6000.c"
89 /* Determine if regnum is an SPE pseudo-register. */
90 #define IS_SPE_PSEUDOREG(tdep, regnum) ((tdep)->ppc_ev0_regnum >= 0 \
91 && (regnum) >= (tdep)->ppc_ev0_regnum \
92 && (regnum) < (tdep)->ppc_ev0_regnum + 32)
94 /* Determine if regnum is a decimal float pseudo-register. */
95 #define IS_DFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_dl0_regnum >= 0 \
96 && (regnum) >= (tdep)->ppc_dl0_regnum \
97 && (regnum) < (tdep)->ppc_dl0_regnum + 16)
99 /* Determine if regnum is a "vX" alias for the raw "vrX" vector
101 #define IS_V_ALIAS_PSEUDOREG(tdep, regnum) (\
102 (tdep)->ppc_v0_alias_regnum >= 0 \
103 && (regnum) >= (tdep)->ppc_v0_alias_regnum \
104 && (regnum) < (tdep)->ppc_v0_alias_regnum + ppc_num_vrs)
106 /* Determine if regnum is a POWER7 VSX register. */
107 #define IS_VSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_vsr0_regnum >= 0 \
108 && (regnum) >= (tdep)->ppc_vsr0_regnum \
109 && (regnum) < (tdep)->ppc_vsr0_regnum + ppc_num_vsrs)
111 /* Determine if regnum is a POWER7 Extended FP register. */
112 #define IS_EFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_efpr0_regnum >= 0 \
113 && (regnum) >= (tdep)->ppc_efpr0_regnum \
114 && (regnum) < (tdep)->ppc_efpr0_regnum + ppc_num_efprs)
116 /* Determine if regnum is a checkpointed decimal float
118 #define IS_CDFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_cdl0_regnum >= 0 \
119 && (regnum) >= (tdep)->ppc_cdl0_regnum \
120 && (regnum) < (tdep)->ppc_cdl0_regnum + 16)
122 /* Determine if regnum is a Checkpointed POWER7 VSX register. */
123 #define IS_CVSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_cvsr0_regnum >= 0 \
124 && (regnum) >= (tdep)->ppc_cvsr0_regnum \
125 && (regnum) < (tdep)->ppc_cvsr0_regnum + ppc_num_vsrs)
127 /* Determine if regnum is a Checkpointed POWER7 Extended FP register. */
128 #define IS_CEFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_cefpr0_regnum >= 0 \
129 && (regnum) >= (tdep)->ppc_cefpr0_regnum \
130 && (regnum) < (tdep)->ppc_cefpr0_regnum + ppc_num_efprs)
132 /* Holds the current set of options to be passed to the disassembler. */
133 static char *powerpc_disassembler_options
;
135 /* The list of available "set powerpc ..." and "show powerpc ..."
137 static struct cmd_list_element
*setpowerpccmdlist
= NULL
;
138 static struct cmd_list_element
*showpowerpccmdlist
= NULL
;
140 static enum auto_boolean powerpc_soft_float_global
= AUTO_BOOLEAN_AUTO
;
142 /* The vector ABI to use. Keep this in sync with powerpc_vector_abi. */
143 static const char *const powerpc_vector_strings
[] =
152 /* A variable that can be configured by the user. */
153 static enum powerpc_vector_abi powerpc_vector_abi_global
= POWERPC_VEC_AUTO
;
154 static const char *powerpc_vector_abi_string
= "auto";
156 /* PowerPC-related per-inferior data. */
158 struct ppc_inferior_data
160 /* This is an optional in case we add more fields to ppc_inferior_data, we
161 don't want it instantiated as soon as we get the ppc_inferior_data for an
163 gdb::optional
<displaced_step_buffers
> disp_step_buf
;
166 static inferior_key
<ppc_inferior_data
> ppc_inferior_data_key
;
168 /* Get the per-inferior PowerPC data for INF. */
170 static ppc_inferior_data
*
171 get_ppc_per_inferior (inferior
*inf
)
173 ppc_inferior_data
*per_inf
= ppc_inferior_data_key
.get (inf
);
175 if (per_inf
== nullptr)
176 per_inf
= ppc_inferior_data_key
.emplace (inf
);
181 /* To be used by skip_prologue. */
183 struct rs6000_framedata
185 int offset
; /* total size of frame --- the distance
186 by which we decrement sp to allocate
188 int saved_gpr
; /* smallest # of saved gpr */
189 unsigned int gpr_mask
; /* Each bit is an individual saved GPR. */
190 int saved_fpr
; /* smallest # of saved fpr */
191 int saved_vr
; /* smallest # of saved vr */
192 int saved_ev
; /* smallest # of saved ev */
193 int alloca_reg
; /* alloca register number (frame ptr) */
194 char frameless
; /* true if frameless functions. */
195 char nosavedpc
; /* true if pc not saved. */
196 char used_bl
; /* true if link register clobbered */
197 int gpr_offset
; /* offset of saved gprs from prev sp */
198 int fpr_offset
; /* offset of saved fprs from prev sp */
199 int vr_offset
; /* offset of saved vrs from prev sp */
200 int ev_offset
; /* offset of saved evs from prev sp */
201 int lr_offset
; /* offset of saved lr */
202 int lr_register
; /* register of saved lr, if trustworthy */
203 int cr_offset
; /* offset of saved cr */
204 int vrsave_offset
; /* offset of saved vrsave register */
208 /* Is REGNO a VSX register? Return 1 if so, 0 otherwise. */
210 vsx_register_p (struct gdbarch
*gdbarch
, int regno
)
212 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
213 if (tdep
->ppc_vsr0_regnum
< 0)
216 return (regno
>= tdep
->ppc_vsr0_upper_regnum
&& regno
217 <= tdep
->ppc_vsr0_upper_regnum
+ 31);
220 /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
222 altivec_register_p (struct gdbarch
*gdbarch
, int regno
)
224 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
225 if (tdep
->ppc_vr0_regnum
< 0 || tdep
->ppc_vrsave_regnum
< 0)
228 return (regno
>= tdep
->ppc_vr0_regnum
&& regno
<= tdep
->ppc_vrsave_regnum
);
232 /* Return true if REGNO is an SPE register, false otherwise. */
234 spe_register_p (struct gdbarch
*gdbarch
, int regno
)
236 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
238 /* Is it a reference to EV0 -- EV31, and do we have those? */
239 if (IS_SPE_PSEUDOREG (tdep
, regno
))
242 /* Is it a reference to one of the raw upper GPR halves? */
243 if (tdep
->ppc_ev0_upper_regnum
>= 0
244 && tdep
->ppc_ev0_upper_regnum
<= regno
245 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
248 /* Is it a reference to the 64-bit accumulator, and do we have that? */
249 if (tdep
->ppc_acc_regnum
>= 0
250 && tdep
->ppc_acc_regnum
== regno
)
253 /* Is it a reference to the SPE floating-point status and control register,
254 and do we have that? */
255 if (tdep
->ppc_spefscr_regnum
>= 0
256 && tdep
->ppc_spefscr_regnum
== regno
)
263 /* Return non-zero if the architecture described by GDBARCH has
264 floating-point registers (f0 --- f31 and fpscr). */
266 ppc_floating_point_unit_p (struct gdbarch
*gdbarch
)
268 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
270 return (tdep
->ppc_fp0_regnum
>= 0
271 && tdep
->ppc_fpscr_regnum
>= 0);
274 /* Return non-zero if the architecture described by GDBARCH has
275 Altivec registers (vr0 --- vr31, vrsave and vscr). */
277 ppc_altivec_support_p (struct gdbarch
*gdbarch
)
279 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
281 return (tdep
->ppc_vr0_regnum
>= 0
282 && tdep
->ppc_vrsave_regnum
>= 0);
285 /* Check that TABLE[GDB_REGNO] is not already initialized, and then
288 This is a helper function for init_sim_regno_table, constructing
289 the table mapping GDB register numbers to sim register numbers; we
290 initialize every element in that table to -1 before we start
293 set_sim_regno (int *table
, int gdb_regno
, int sim_regno
)
295 /* Make sure we don't try to assign any given GDB register a sim
296 register number more than once. */
297 gdb_assert (table
[gdb_regno
] == -1);
298 table
[gdb_regno
] = sim_regno
;
302 /* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
303 numbers to simulator register numbers, based on the values placed
304 in the ARCH->tdep->ppc_foo_regnum members. */
306 init_sim_regno_table (struct gdbarch
*arch
)
308 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
309 int total_regs
= gdbarch_num_regs (arch
);
310 int *sim_regno
= GDBARCH_OBSTACK_CALLOC (arch
, total_regs
, int);
312 static const char *const segment_regs
[] = {
313 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
314 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
317 /* Presume that all registers not explicitly mentioned below are
318 unavailable from the sim. */
319 for (i
= 0; i
< total_regs
; i
++)
322 /* General-purpose registers. */
323 for (i
= 0; i
< ppc_num_gprs
; i
++)
324 set_sim_regno (sim_regno
, tdep
->ppc_gp0_regnum
+ i
, sim_ppc_r0_regnum
+ i
);
326 /* Floating-point registers. */
327 if (tdep
->ppc_fp0_regnum
>= 0)
328 for (i
= 0; i
< ppc_num_fprs
; i
++)
329 set_sim_regno (sim_regno
,
330 tdep
->ppc_fp0_regnum
+ i
,
331 sim_ppc_f0_regnum
+ i
);
332 if (tdep
->ppc_fpscr_regnum
>= 0)
333 set_sim_regno (sim_regno
, tdep
->ppc_fpscr_regnum
, sim_ppc_fpscr_regnum
);
335 set_sim_regno (sim_regno
, gdbarch_pc_regnum (arch
), sim_ppc_pc_regnum
);
336 set_sim_regno (sim_regno
, tdep
->ppc_ps_regnum
, sim_ppc_ps_regnum
);
337 set_sim_regno (sim_regno
, tdep
->ppc_cr_regnum
, sim_ppc_cr_regnum
);
339 /* Segment registers. */
340 for (i
= 0; i
< ppc_num_srs
; i
++)
344 gdb_regno
= user_reg_map_name_to_regnum (arch
, segment_regs
[i
], -1);
346 set_sim_regno (sim_regno
, gdb_regno
, sim_ppc_sr0_regnum
+ i
);
349 /* Altivec registers. */
350 if (tdep
->ppc_vr0_regnum
>= 0)
352 for (i
= 0; i
< ppc_num_vrs
; i
++)
353 set_sim_regno (sim_regno
,
354 tdep
->ppc_vr0_regnum
+ i
,
355 sim_ppc_vr0_regnum
+ i
);
357 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
358 we can treat this more like the other cases. */
359 set_sim_regno (sim_regno
,
360 tdep
->ppc_vr0_regnum
+ ppc_num_vrs
,
361 sim_ppc_vscr_regnum
);
363 /* vsave is a special-purpose register, so the code below handles it. */
365 /* SPE APU (E500) registers. */
366 if (tdep
->ppc_ev0_upper_regnum
>= 0)
367 for (i
= 0; i
< ppc_num_gprs
; i
++)
368 set_sim_regno (sim_regno
,
369 tdep
->ppc_ev0_upper_regnum
+ i
,
370 sim_ppc_rh0_regnum
+ i
);
371 if (tdep
->ppc_acc_regnum
>= 0)
372 set_sim_regno (sim_regno
, tdep
->ppc_acc_regnum
, sim_ppc_acc_regnum
);
373 /* spefscr is a special-purpose register, so the code below handles it. */
376 /* Now handle all special-purpose registers. Verify that they
377 haven't mistakenly been assigned numbers by any of the above
379 for (i
= 0; i
< sim_ppc_num_sprs
; i
++)
381 const char *spr_name
= sim_spr_register_name (i
);
384 if (spr_name
!= NULL
)
385 gdb_regno
= user_reg_map_name_to_regnum (arch
, spr_name
, -1);
388 set_sim_regno (sim_regno
, gdb_regno
, sim_ppc_spr0_regnum
+ i
);
392 /* Drop the initialized array into place. */
393 tdep
->sim_regno
= sim_regno
;
397 /* Given a GDB register number REG, return the corresponding SIM
400 rs6000_register_sim_regno (struct gdbarch
*gdbarch
, int reg
)
402 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
405 if (tdep
->sim_regno
== NULL
)
406 init_sim_regno_table (gdbarch
);
408 gdb_assert (0 <= reg
&& reg
<= gdbarch_num_cooked_regs (gdbarch
));
409 sim_regno
= tdep
->sim_regno
[reg
];
414 return LEGACY_SIM_REGNO_IGNORE
;
419 /* Register set support functions. */
421 /* REGS + OFFSET contains register REGNUM in a field REGSIZE wide.
422 Write the register to REGCACHE. */
425 ppc_supply_reg (struct regcache
*regcache
, int regnum
,
426 const gdb_byte
*regs
, size_t offset
, int regsize
)
428 if (regnum
!= -1 && offset
!= -1)
432 struct gdbarch
*gdbarch
= regcache
->arch ();
433 int gdb_regsize
= register_size (gdbarch
, regnum
);
434 if (gdb_regsize
< regsize
435 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
436 offset
+= regsize
- gdb_regsize
;
438 regcache
->raw_supply (regnum
, regs
+ offset
);
442 /* Read register REGNUM from REGCACHE and store to REGS + OFFSET
443 in a field REGSIZE wide. Zero pad as necessary. */
446 ppc_collect_reg (const struct regcache
*regcache
, int regnum
,
447 gdb_byte
*regs
, size_t offset
, int regsize
)
449 if (regnum
!= -1 && offset
!= -1)
453 struct gdbarch
*gdbarch
= regcache
->arch ();
454 int gdb_regsize
= register_size (gdbarch
, regnum
);
455 if (gdb_regsize
< regsize
)
457 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
459 memset (regs
+ offset
, 0, regsize
- gdb_regsize
);
460 offset
+= regsize
- gdb_regsize
;
463 memset (regs
+ offset
+ regsize
- gdb_regsize
, 0,
464 regsize
- gdb_regsize
);
467 regcache
->raw_collect (regnum
, regs
+ offset
);
472 ppc_greg_offset (struct gdbarch
*gdbarch
,
473 struct gdbarch_tdep
*tdep
,
474 const struct ppc_reg_offsets
*offsets
,
478 *regsize
= offsets
->gpr_size
;
479 if (regnum
>= tdep
->ppc_gp0_regnum
480 && regnum
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
)
481 return (offsets
->r0_offset
482 + (regnum
- tdep
->ppc_gp0_regnum
) * offsets
->gpr_size
);
484 if (regnum
== gdbarch_pc_regnum (gdbarch
))
485 return offsets
->pc_offset
;
487 if (regnum
== tdep
->ppc_ps_regnum
)
488 return offsets
->ps_offset
;
490 if (regnum
== tdep
->ppc_lr_regnum
)
491 return offsets
->lr_offset
;
493 if (regnum
== tdep
->ppc_ctr_regnum
)
494 return offsets
->ctr_offset
;
496 *regsize
= offsets
->xr_size
;
497 if (regnum
== tdep
->ppc_cr_regnum
)
498 return offsets
->cr_offset
;
500 if (regnum
== tdep
->ppc_xer_regnum
)
501 return offsets
->xer_offset
;
503 if (regnum
== tdep
->ppc_mq_regnum
)
504 return offsets
->mq_offset
;
510 ppc_fpreg_offset (struct gdbarch_tdep
*tdep
,
511 const struct ppc_reg_offsets
*offsets
,
514 if (regnum
>= tdep
->ppc_fp0_regnum
515 && regnum
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
)
516 return offsets
->f0_offset
+ (regnum
- tdep
->ppc_fp0_regnum
) * 8;
518 if (regnum
== tdep
->ppc_fpscr_regnum
)
519 return offsets
->fpscr_offset
;
524 /* Supply register REGNUM in the general-purpose register set REGSET
525 from the buffer specified by GREGS and LEN to register cache
526 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
529 ppc_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
530 int regnum
, const void *gregs
, size_t len
)
532 struct gdbarch
*gdbarch
= regcache
->arch ();
533 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
534 const struct ppc_reg_offsets
*offsets
535 = (const struct ppc_reg_offsets
*) regset
->regmap
;
542 int gpr_size
= offsets
->gpr_size
;
544 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
545 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
546 i
++, offset
+= gpr_size
)
547 ppc_supply_reg (regcache
, i
, (const gdb_byte
*) gregs
, offset
,
550 ppc_supply_reg (regcache
, gdbarch_pc_regnum (gdbarch
),
551 (const gdb_byte
*) gregs
, offsets
->pc_offset
, gpr_size
);
552 ppc_supply_reg (regcache
, tdep
->ppc_ps_regnum
,
553 (const gdb_byte
*) gregs
, offsets
->ps_offset
, gpr_size
);
554 ppc_supply_reg (regcache
, tdep
->ppc_lr_regnum
,
555 (const gdb_byte
*) gregs
, offsets
->lr_offset
, gpr_size
);
556 ppc_supply_reg (regcache
, tdep
->ppc_ctr_regnum
,
557 (const gdb_byte
*) gregs
, offsets
->ctr_offset
, gpr_size
);
558 ppc_supply_reg (regcache
, tdep
->ppc_cr_regnum
,
559 (const gdb_byte
*) gregs
, offsets
->cr_offset
,
561 ppc_supply_reg (regcache
, tdep
->ppc_xer_regnum
,
562 (const gdb_byte
*) gregs
, offsets
->xer_offset
,
564 ppc_supply_reg (regcache
, tdep
->ppc_mq_regnum
,
565 (const gdb_byte
*) gregs
, offsets
->mq_offset
,
570 offset
= ppc_greg_offset (gdbarch
, tdep
, offsets
, regnum
, ®size
);
571 ppc_supply_reg (regcache
, regnum
, (const gdb_byte
*) gregs
, offset
, regsize
);
574 /* Supply register REGNUM in the floating-point register set REGSET
575 from the buffer specified by FPREGS and LEN to register cache
576 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
579 ppc_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
580 int regnum
, const void *fpregs
, size_t len
)
582 struct gdbarch
*gdbarch
= regcache
->arch ();
583 struct gdbarch_tdep
*tdep
;
584 const struct ppc_reg_offsets
*offsets
;
587 if (!ppc_floating_point_unit_p (gdbarch
))
590 tdep
= gdbarch_tdep (gdbarch
);
591 offsets
= (const struct ppc_reg_offsets
*) regset
->regmap
;
596 for (i
= tdep
->ppc_fp0_regnum
, offset
= offsets
->f0_offset
;
597 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
599 ppc_supply_reg (regcache
, i
, (const gdb_byte
*) fpregs
, offset
, 8);
601 ppc_supply_reg (regcache
, tdep
->ppc_fpscr_regnum
,
602 (const gdb_byte
*) fpregs
, offsets
->fpscr_offset
,
603 offsets
->fpscr_size
);
607 offset
= ppc_fpreg_offset (tdep
, offsets
, regnum
);
608 ppc_supply_reg (regcache
, regnum
, (const gdb_byte
*) fpregs
, offset
,
609 regnum
== tdep
->ppc_fpscr_regnum
? offsets
->fpscr_size
: 8);
612 /* Collect register REGNUM in the general-purpose register set
613 REGSET from register cache REGCACHE into the buffer specified by
614 GREGS and LEN. If REGNUM is -1, do this for all registers in
618 ppc_collect_gregset (const struct regset
*regset
,
619 const struct regcache
*regcache
,
620 int regnum
, void *gregs
, size_t len
)
622 struct gdbarch
*gdbarch
= regcache
->arch ();
623 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
624 const struct ppc_reg_offsets
*offsets
625 = (const struct ppc_reg_offsets
*) regset
->regmap
;
632 int gpr_size
= offsets
->gpr_size
;
634 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
635 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
636 i
++, offset
+= gpr_size
)
637 ppc_collect_reg (regcache
, i
, (gdb_byte
*) gregs
, offset
, gpr_size
);
639 ppc_collect_reg (regcache
, gdbarch_pc_regnum (gdbarch
),
640 (gdb_byte
*) gregs
, offsets
->pc_offset
, gpr_size
);
641 ppc_collect_reg (regcache
, tdep
->ppc_ps_regnum
,
642 (gdb_byte
*) gregs
, offsets
->ps_offset
, gpr_size
);
643 ppc_collect_reg (regcache
, tdep
->ppc_lr_regnum
,
644 (gdb_byte
*) gregs
, offsets
->lr_offset
, gpr_size
);
645 ppc_collect_reg (regcache
, tdep
->ppc_ctr_regnum
,
646 (gdb_byte
*) gregs
, offsets
->ctr_offset
, gpr_size
);
647 ppc_collect_reg (regcache
, tdep
->ppc_cr_regnum
,
648 (gdb_byte
*) gregs
, offsets
->cr_offset
,
650 ppc_collect_reg (regcache
, tdep
->ppc_xer_regnum
,
651 (gdb_byte
*) gregs
, offsets
->xer_offset
,
653 ppc_collect_reg (regcache
, tdep
->ppc_mq_regnum
,
654 (gdb_byte
*) gregs
, offsets
->mq_offset
,
659 offset
= ppc_greg_offset (gdbarch
, tdep
, offsets
, regnum
, ®size
);
660 ppc_collect_reg (regcache
, regnum
, (gdb_byte
*) gregs
, offset
, regsize
);
663 /* Collect register REGNUM in the floating-point register set
664 REGSET from register cache REGCACHE into the buffer specified by
665 FPREGS and LEN. If REGNUM is -1, do this for all registers in
669 ppc_collect_fpregset (const struct regset
*regset
,
670 const struct regcache
*regcache
,
671 int regnum
, void *fpregs
, size_t len
)
673 struct gdbarch
*gdbarch
= regcache
->arch ();
674 struct gdbarch_tdep
*tdep
;
675 const struct ppc_reg_offsets
*offsets
;
678 if (!ppc_floating_point_unit_p (gdbarch
))
681 tdep
= gdbarch_tdep (gdbarch
);
682 offsets
= (const struct ppc_reg_offsets
*) regset
->regmap
;
687 for (i
= tdep
->ppc_fp0_regnum
, offset
= offsets
->f0_offset
;
688 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
690 ppc_collect_reg (regcache
, i
, (gdb_byte
*) fpregs
, offset
, 8);
692 ppc_collect_reg (regcache
, tdep
->ppc_fpscr_regnum
,
693 (gdb_byte
*) fpregs
, offsets
->fpscr_offset
,
694 offsets
->fpscr_size
);
698 offset
= ppc_fpreg_offset (tdep
, offsets
, regnum
);
699 ppc_collect_reg (regcache
, regnum
, (gdb_byte
*) fpregs
, offset
,
700 regnum
== tdep
->ppc_fpscr_regnum
? offsets
->fpscr_size
: 8);
704 insn_changes_sp_or_jumps (unsigned long insn
)
706 int opcode
= (insn
>> 26) & 0x03f;
707 int sd
= (insn
>> 21) & 0x01f;
708 int a
= (insn
>> 16) & 0x01f;
709 int subcode
= (insn
>> 1) & 0x3ff;
711 /* Changes the stack pointer. */
713 /* NOTE: There are many ways to change the value of a given register.
714 The ways below are those used when the register is R1, the SP,
715 in a funtion's epilogue. */
717 if (opcode
== 31 && subcode
== 444 && a
== 1)
718 return 1; /* mr R1,Rn */
719 if (opcode
== 14 && sd
== 1)
720 return 1; /* addi R1,Rn,simm */
721 if (opcode
== 58 && sd
== 1)
722 return 1; /* ld R1,ds(Rn) */
724 /* Transfers control. */
730 if (opcode
== 19 && subcode
== 16)
732 if (opcode
== 19 && subcode
== 528)
733 return 1; /* bcctr */
738 /* Return true if we are in the function's epilogue, i.e. after the
739 instruction that destroyed the function's stack frame.
741 1) scan forward from the point of execution:
742 a) If you find an instruction that modifies the stack pointer
743 or transfers control (except a return), execution is not in
745 b) Stop scanning if you find a return instruction or reach the
746 end of the function or reach the hard limit for the size of
748 2) scan backward from the point of execution:
749 a) If you find an instruction that modifies the stack pointer,
750 execution *is* in an epilogue, return.
751 b) Stop scanning if you reach an instruction that transfers
752 control or the beginning of the function or reach the hard
753 limit for the size of an epilogue. */
756 rs6000_in_function_epilogue_frame_p (struct frame_info
*curfrm
,
757 struct gdbarch
*gdbarch
, CORE_ADDR pc
)
759 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
760 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
761 bfd_byte insn_buf
[PPC_INSN_SIZE
];
762 CORE_ADDR scan_pc
, func_start
, func_end
, epilogue_start
, epilogue_end
;
765 /* Find the search limits based on function boundaries and hard limit. */
767 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
770 epilogue_start
= pc
- PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
771 if (epilogue_start
< func_start
) epilogue_start
= func_start
;
773 epilogue_end
= pc
+ PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
774 if (epilogue_end
> func_end
) epilogue_end
= func_end
;
776 /* Scan forward until next 'blr'. */
778 for (scan_pc
= pc
; scan_pc
< epilogue_end
; scan_pc
+= PPC_INSN_SIZE
)
780 if (!safe_frame_unwind_memory (curfrm
, scan_pc
, insn_buf
, PPC_INSN_SIZE
))
782 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
, byte_order
);
783 if (insn
== 0x4e800020)
785 /* Assume a bctr is a tail call unless it points strictly within
787 if (insn
== 0x4e800420)
789 CORE_ADDR ctr
= get_frame_register_unsigned (curfrm
,
790 tdep
->ppc_ctr_regnum
);
791 if (ctr
> func_start
&& ctr
< func_end
)
796 if (insn_changes_sp_or_jumps (insn
))
800 /* Scan backward until adjustment to stack pointer (R1). */
802 for (scan_pc
= pc
- PPC_INSN_SIZE
;
803 scan_pc
>= epilogue_start
;
804 scan_pc
-= PPC_INSN_SIZE
)
806 if (!safe_frame_unwind_memory (curfrm
, scan_pc
, insn_buf
, PPC_INSN_SIZE
))
808 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
, byte_order
);
809 if (insn_changes_sp_or_jumps (insn
))
816 /* Implement the stack_frame_destroyed_p gdbarch method. */
819 rs6000_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
821 return rs6000_in_function_epilogue_frame_p (get_current_frame (),
825 /* Get the ith function argument for the current function. */
827 rs6000_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
830 return get_frame_register_unsigned (frame
, 3 + argi
);
833 /* Sequence of bytes for breakpoint instruction. */
835 constexpr gdb_byte big_breakpoint
[] = { 0x7d, 0x82, 0x10, 0x08 };
836 constexpr gdb_byte little_breakpoint
[] = { 0x08, 0x10, 0x82, 0x7d };
838 typedef BP_MANIPULATION_ENDIAN (little_breakpoint
, big_breakpoint
)
841 /* Instruction masks for displaced stepping. */
842 #define BRANCH_MASK 0xfc000000
843 #define BP_MASK 0xFC0007FE
844 #define B_INSN 0x48000000
845 #define BC_INSN 0x40000000
846 #define BXL_INSN 0x4c000000
847 #define BP_INSN 0x7C000008
849 /* Instruction masks used during single-stepping of atomic
851 #define LOAD_AND_RESERVE_MASK 0xfc0007fe
852 #define LWARX_INSTRUCTION 0x7c000028
853 #define LDARX_INSTRUCTION 0x7c0000A8
854 #define LBARX_INSTRUCTION 0x7c000068
855 #define LHARX_INSTRUCTION 0x7c0000e8
856 #define LQARX_INSTRUCTION 0x7c000228
857 #define STORE_CONDITIONAL_MASK 0xfc0007ff
858 #define STWCX_INSTRUCTION 0x7c00012d
859 #define STDCX_INSTRUCTION 0x7c0001ad
860 #define STBCX_INSTRUCTION 0x7c00056d
861 #define STHCX_INSTRUCTION 0x7c0005ad
862 #define STQCX_INSTRUCTION 0x7c00016d
864 /* Check if insn is one of the Load And Reserve instructions used for atomic
866 #define IS_LOAD_AND_RESERVE_INSN(insn) ((insn & LOAD_AND_RESERVE_MASK) == LWARX_INSTRUCTION \
867 || (insn & LOAD_AND_RESERVE_MASK) == LDARX_INSTRUCTION \
868 || (insn & LOAD_AND_RESERVE_MASK) == LBARX_INSTRUCTION \
869 || (insn & LOAD_AND_RESERVE_MASK) == LHARX_INSTRUCTION \
870 || (insn & LOAD_AND_RESERVE_MASK) == LQARX_INSTRUCTION)
871 /* Check if insn is one of the Store Conditional instructions used for atomic
873 #define IS_STORE_CONDITIONAL_INSN(insn) ((insn & STORE_CONDITIONAL_MASK) == STWCX_INSTRUCTION \
874 || (insn & STORE_CONDITIONAL_MASK) == STDCX_INSTRUCTION \
875 || (insn & STORE_CONDITIONAL_MASK) == STBCX_INSTRUCTION \
876 || (insn & STORE_CONDITIONAL_MASK) == STHCX_INSTRUCTION \
877 || (insn & STORE_CONDITIONAL_MASK) == STQCX_INSTRUCTION)
879 typedef buf_displaced_step_copy_insn_closure
880 ppc_displaced_step_copy_insn_closure
;
882 /* We can't displaced step atomic sequences. */
884 static displaced_step_copy_insn_closure_up
885 ppc_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
886 CORE_ADDR from
, CORE_ADDR to
,
887 struct regcache
*regs
)
889 size_t len
= gdbarch_max_insn_length (gdbarch
);
890 std::unique_ptr
<ppc_displaced_step_copy_insn_closure
> closure
891 (new ppc_displaced_step_copy_insn_closure (len
));
892 gdb_byte
*buf
= closure
->buf
.data ();
893 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
896 read_memory (from
, buf
, len
);
898 insn
= extract_signed_integer (buf
, PPC_INSN_SIZE
, byte_order
);
900 /* Assume all atomic sequences start with a Load and Reserve instruction. */
901 if (IS_LOAD_AND_RESERVE_INSN (insn
))
903 displaced_debug_printf ("can't displaced step atomic sequence at %s",
904 paddress (gdbarch
, from
));
909 write_memory (to
, buf
, len
);
911 displaced_debug_printf ("copy %s->%s: %s",
912 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
913 displaced_step_dump_bytes (buf
, len
).c_str ());;
915 /* This is a work around for a problem with g++ 4.8. */
916 return displaced_step_copy_insn_closure_up (closure
.release ());
919 /* Fix up the state of registers and memory after having single-stepped
920 a displaced instruction. */
922 ppc_displaced_step_fixup (struct gdbarch
*gdbarch
,
923 struct displaced_step_copy_insn_closure
*closure_
,
924 CORE_ADDR from
, CORE_ADDR to
,
925 struct regcache
*regs
)
927 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
928 /* Our closure is a copy of the instruction. */
929 ppc_displaced_step_copy_insn_closure
*closure
930 = (ppc_displaced_step_copy_insn_closure
*) closure_
;
931 ULONGEST insn
= extract_unsigned_integer (closure
->buf
.data (),
932 PPC_INSN_SIZE
, byte_order
);
934 /* Offset for non PC-relative instructions. */
935 LONGEST offset
= PPC_INSN_SIZE
;
937 opcode
= insn
& BRANCH_MASK
;
939 displaced_debug_printf ("(ppc) fixup (%s, %s)",
940 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
942 /* Handle PC-relative branch instructions. */
943 if (opcode
== B_INSN
|| opcode
== BC_INSN
|| opcode
== BXL_INSN
)
947 /* Read the current PC value after the instruction has been executed
948 in a displaced location. Calculate the offset to be applied to the
949 original PC value before the displaced stepping. */
950 regcache_cooked_read_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
952 offset
= current_pc
- to
;
954 if (opcode
!= BXL_INSN
)
956 /* Check for AA bit indicating whether this is an absolute
957 addressing or PC-relative (1: absolute, 0: relative). */
960 /* PC-relative addressing is being used in the branch. */
961 displaced_debug_printf ("(ppc) branch instruction: %s",
962 paddress (gdbarch
, insn
));
963 displaced_debug_printf ("(ppc) adjusted PC from %s to %s",
964 paddress (gdbarch
, current_pc
),
965 paddress (gdbarch
, from
+ offset
));
967 regcache_cooked_write_unsigned (regs
,
968 gdbarch_pc_regnum (gdbarch
),
974 /* If we're here, it means we have a branch to LR or CTR. If the
975 branch was taken, the offset is probably greater than 4 (the next
976 instruction), so it's safe to assume that an offset of 4 means we
977 did not take the branch. */
978 if (offset
== PPC_INSN_SIZE
)
979 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
980 from
+ PPC_INSN_SIZE
);
983 /* Check for LK bit indicating whether we should set the link
984 register to point to the next instruction
985 (1: Set, 0: Don't set). */
988 /* Link register needs to be set to the next instruction's PC. */
989 regcache_cooked_write_unsigned (regs
,
990 gdbarch_tdep (gdbarch
)->ppc_lr_regnum
,
991 from
+ PPC_INSN_SIZE
);
992 displaced_debug_printf ("(ppc) adjusted LR to %s",
993 paddress (gdbarch
, from
+ PPC_INSN_SIZE
));
997 /* Check for breakpoints in the inferior. If we've found one, place the PC
998 right at the breakpoint instruction. */
999 else if ((insn
& BP_MASK
) == BP_INSN
)
1000 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
), from
);
1002 /* Handle any other instructions that do not fit in the categories above. */
1003 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
1007 /* Implementation of gdbarch_displaced_step_prepare. */
1009 static displaced_step_prepare_status
1010 ppc_displaced_step_prepare (gdbarch
*arch
, thread_info
*thread
,
1011 CORE_ADDR
&displaced_pc
)
1013 ppc_inferior_data
*per_inferior
= get_ppc_per_inferior (thread
->inf
);
1015 if (!per_inferior
->disp_step_buf
.has_value ())
1017 /* Figure out where the displaced step buffer is. */
1018 CORE_ADDR disp_step_buf_addr
1019 = displaced_step_at_entry_point (thread
->inf
->gdbarch
);
1021 per_inferior
->disp_step_buf
.emplace (disp_step_buf_addr
);
1024 return per_inferior
->disp_step_buf
->prepare (thread
, displaced_pc
);
1027 /* Implementation of gdbarch_displaced_step_finish. */
1029 static displaced_step_finish_status
1030 ppc_displaced_step_finish (gdbarch
*arch
, thread_info
*thread
,
1033 ppc_inferior_data
*per_inferior
= get_ppc_per_inferior (thread
->inf
);
1035 gdb_assert (per_inferior
->disp_step_buf
.has_value ());
1037 return per_inferior
->disp_step_buf
->finish (arch
, thread
, sig
);
1040 /* Implementation of gdbarch_displaced_step_restore_all_in_ptid. */
1043 ppc_displaced_step_restore_all_in_ptid (inferior
*parent_inf
, ptid_t ptid
)
1045 ppc_inferior_data
*per_inferior
= ppc_inferior_data_key
.get (parent_inf
);
1047 if (per_inferior
== nullptr
1048 || !per_inferior
->disp_step_buf
.has_value ())
1051 per_inferior
->disp_step_buf
->restore_in_ptid (ptid
);
1054 /* Always use hardware single-stepping to execute the
1055 displaced instruction. */
1057 ppc_displaced_step_hw_singlestep (struct gdbarch
*gdbarch
)
1062 /* Checks for an atomic sequence of instructions beginning with a
1063 Load And Reserve instruction and ending with a Store Conditional
1064 instruction. If such a sequence is found, attempt to step through it.
1065 A breakpoint is placed at the end of the sequence. */
1066 std::vector
<CORE_ADDR
>
1067 ppc_deal_with_atomic_sequence (struct regcache
*regcache
)
1069 struct gdbarch
*gdbarch
= regcache
->arch ();
1070 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1071 CORE_ADDR pc
= regcache_read_pc (regcache
);
1072 CORE_ADDR breaks
[2] = {CORE_ADDR_MAX
, CORE_ADDR_MAX
};
1074 CORE_ADDR closing_insn
; /* Instruction that closes the atomic sequence. */
1075 int insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
1078 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
1079 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
1080 int bc_insn_count
= 0; /* Conditional branch instruction count. */
1082 /* Assume all atomic sequences start with a Load And Reserve instruction. */
1083 if (!IS_LOAD_AND_RESERVE_INSN (insn
))
1086 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
1088 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
1090 loc
+= PPC_INSN_SIZE
;
1091 insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
1093 /* Assume that there is at most one conditional branch in the atomic
1094 sequence. If a conditional branch is found, put a breakpoint in
1095 its destination address. */
1096 if ((insn
& BRANCH_MASK
) == BC_INSN
)
1098 int immediate
= ((insn
& 0xfffc) ^ 0x8000) - 0x8000;
1099 int absolute
= insn
& 2;
1101 if (bc_insn_count
>= 1)
1102 return {}; /* More than one conditional branch found, fallback
1103 to the standard single-step code. */
1106 breaks
[1] = immediate
;
1108 breaks
[1] = loc
+ immediate
;
1114 if (IS_STORE_CONDITIONAL_INSN (insn
))
1118 /* Assume that the atomic sequence ends with a Store Conditional
1120 if (!IS_STORE_CONDITIONAL_INSN (insn
))
1124 loc
+= PPC_INSN_SIZE
;
1126 /* Insert a breakpoint right after the end of the atomic sequence. */
1129 /* Check for duplicated breakpoints. Check also for a breakpoint
1130 placed (branch instruction's destination) anywhere in sequence. */
1132 && (breaks
[1] == breaks
[0]
1133 || (breaks
[1] >= pc
&& breaks
[1] <= closing_insn
)))
1134 last_breakpoint
= 0;
1136 std::vector
<CORE_ADDR
> next_pcs
;
1138 for (index
= 0; index
<= last_breakpoint
; index
++)
1139 next_pcs
.push_back (breaks
[index
]);
1145 #define SIGNED_SHORT(x) \
1146 ((sizeof (short) == 2) \
1147 ? ((int)(short)(x)) \
1148 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
1150 #define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
1152 /* Limit the number of skipped non-prologue instructions, as the examining
1153 of the prologue is expensive. */
1154 static int max_skip_non_prologue_insns
= 10;
1156 /* Return nonzero if the given instruction OP can be part of the prologue
1157 of a function and saves a parameter on the stack. FRAMEP should be
1158 set if one of the previous instructions in the function has set the
1162 store_param_on_stack_p (unsigned long op
, int framep
, int *r0_contains_arg
)
1164 /* Move parameters from argument registers to temporary register. */
1165 if ((op
& 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
1167 /* Rx must be scratch register r0. */
1168 const int rx_regno
= (op
>> 16) & 31;
1169 /* Ry: Only r3 - r10 are used for parameter passing. */
1170 const int ry_regno
= GET_SRC_REG (op
);
1172 if (rx_regno
== 0 && ry_regno
>= 3 && ry_regno
<= 10)
1174 *r0_contains_arg
= 1;
1181 /* Save a General Purpose Register on stack. */
1183 if ((op
& 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
1184 (op
& 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
1186 /* Rx: Only r3 - r10 are used for parameter passing. */
1187 const int rx_regno
= GET_SRC_REG (op
);
1189 return (rx_regno
>= 3 && rx_regno
<= 10);
1192 /* Save a General Purpose Register on stack via the Frame Pointer. */
1195 ((op
& 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
1196 (op
& 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
1197 (op
& 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
1199 /* Rx: Usually, only r3 - r10 are used for parameter passing.
1200 However, the compiler sometimes uses r0 to hold an argument. */
1201 const int rx_regno
= GET_SRC_REG (op
);
1203 return ((rx_regno
>= 3 && rx_regno
<= 10)
1204 || (rx_regno
== 0 && *r0_contains_arg
));
1207 if ((op
& 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
1209 /* Only f2 - f8 are used for parameter passing. */
1210 const int src_regno
= GET_SRC_REG (op
);
1212 return (src_regno
>= 2 && src_regno
<= 8);
1215 if (framep
&& ((op
& 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
1217 /* Only f2 - f8 are used for parameter passing. */
1218 const int src_regno
= GET_SRC_REG (op
);
1220 return (src_regno
>= 2 && src_regno
<= 8);
1223 /* Not an insn that saves a parameter on stack. */
1227 /* Assuming that INSN is a "bl" instruction located at PC, return
1228 nonzero if the destination of the branch is a "blrl" instruction.
1230 This sequence is sometimes found in certain function prologues.
1231 It allows the function to load the LR register with a value that
1232 they can use to access PIC data using PC-relative offsets. */
1235 bl_to_blrl_insn_p (CORE_ADDR pc
, int insn
, enum bfd_endian byte_order
)
1242 absolute
= (int) ((insn
>> 1) & 1);
1243 immediate
= ((insn
& ~3) << 6) >> 6;
1247 dest
= pc
+ immediate
;
1249 dest_insn
= read_memory_integer (dest
, 4, byte_order
);
1250 if ((dest_insn
& 0xfc00ffff) == 0x4c000021) /* blrl */
1256 /* Return true if OP is a stw or std instruction with
1257 register operands RS and RA and any immediate offset.
1259 If WITH_UPDATE is true, also return true if OP is
1260 a stwu or stdu instruction with the same operands.
1262 Return false otherwise.
1265 store_insn_p (unsigned long op
, unsigned long rs
,
1266 unsigned long ra
, bool with_update
)
1271 if (/* std RS, SIMM(RA) */
1272 ((op
& 0xffff0003) == (rs
| ra
| 0xf8000000)) ||
1273 /* stw RS, SIMM(RA) */
1274 ((op
& 0xffff0000) == (rs
| ra
| 0x90000000)))
1279 if (/* stdu RS, SIMM(RA) */
1280 ((op
& 0xffff0003) == (rs
| ra
| 0xf8000001)) ||
1281 /* stwu RS, SIMM(RA) */
1282 ((op
& 0xffff0000) == (rs
| ra
| 0x94000000)))
1289 /* Masks for decoding a branch-and-link (bl) instruction.
1291 BL_MASK and BL_INSTRUCTION are used in combination with each other.
1292 The former is anded with the opcode in question; if the result of
1293 this masking operation is equal to BL_INSTRUCTION, then the opcode in
1294 question is a ``bl'' instruction.
1296 BL_DISPLACEMENT_MASK is anded with the opcode in order to extract
1297 the branch displacement. */
1299 #define BL_MASK 0xfc000001
1300 #define BL_INSTRUCTION 0x48000001
1301 #define BL_DISPLACEMENT_MASK 0x03fffffc
1303 static unsigned long
1304 rs6000_fetch_instruction (struct gdbarch
*gdbarch
, const CORE_ADDR pc
)
1306 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1310 /* Fetch the instruction and convert it to an integer. */
1311 if (target_read_memory (pc
, buf
, 4))
1313 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1318 /* GCC generates several well-known sequences of instructions at the begining
1319 of each function prologue when compiling with -fstack-check. If one of
1320 such sequences starts at START_PC, then return the address of the
1321 instruction immediately past this sequence. Otherwise, return START_PC. */
1324 rs6000_skip_stack_check (struct gdbarch
*gdbarch
, const CORE_ADDR start_pc
)
1326 CORE_ADDR pc
= start_pc
;
1327 unsigned long op
= rs6000_fetch_instruction (gdbarch
, pc
);
1329 /* First possible sequence: A small number of probes.
1330 stw 0, -<some immediate>(1)
1331 [repeat this instruction any (small) number of times]. */
1333 if ((op
& 0xffff0000) == 0x90010000)
1335 while ((op
& 0xffff0000) == 0x90010000)
1338 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1343 /* Second sequence: A probing loop.
1344 addi 12,1,-<some immediate>
1345 lis 0,-<some immediate>
1346 [possibly ori 0,0,<some immediate>]
1350 addi 12,12,-<some immediate>
1353 [possibly one last probe: stw 0,<some immediate>(12)]. */
1357 /* addi 12,1,-<some immediate> */
1358 if ((op
& 0xffff0000) != 0x39810000)
1361 /* lis 0,-<some immediate> */
1363 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1364 if ((op
& 0xffff0000) != 0x3c000000)
1368 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1369 /* [possibly ori 0,0,<some immediate>] */
1370 if ((op
& 0xffff0000) == 0x60000000)
1373 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1376 if (op
!= 0x7c0c0214)
1381 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1382 if (op
!= 0x7c0c0000)
1387 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1388 if ((op
& 0xff9f0001) != 0x41820000)
1391 /* addi 12,12,-<some immediate> */
1393 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1394 if ((op
& 0xffff0000) != 0x398c0000)
1399 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1400 if (op
!= 0x900c0000)
1405 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1406 if ((op
& 0xfc000001) != 0x48000000)
1409 /* [possibly one last probe: stw 0,<some immediate>(12)]. */
1411 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1412 if ((op
& 0xffff0000) == 0x900c0000)
1415 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1418 /* We found a valid stack-check sequence, return the new PC. */
1422 /* Third sequence: No probe; instead, a comparison between the stack size
1423 limit (saved in a run-time global variable) and the current stack
1426 addi 0,1,-<some immediate>
1427 lis 12,__gnat_stack_limit@ha
1428 lwz 12,__gnat_stack_limit@l(12)
1431 or, with a small variant in the case of a bigger stack frame:
1432 addis 0,1,<some immediate>
1433 addic 0,0,-<some immediate>
1434 lis 12,__gnat_stack_limit@ha
1435 lwz 12,__gnat_stack_limit@l(12)
1440 /* addi 0,1,-<some immediate> */
1441 if ((op
& 0xffff0000) != 0x38010000)
1443 /* small stack frame variant not recognized; try the
1444 big stack frame variant: */
1446 /* addis 0,1,<some immediate> */
1447 if ((op
& 0xffff0000) != 0x3c010000)
1450 /* addic 0,0,-<some immediate> */
1452 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1453 if ((op
& 0xffff0000) != 0x30000000)
1457 /* lis 12,<some immediate> */
1459 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1460 if ((op
& 0xffff0000) != 0x3d800000)
1463 /* lwz 12,<some immediate>(12) */
1465 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1466 if ((op
& 0xffff0000) != 0x818c0000)
1471 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1472 if ((op
& 0xfffffffe) != 0x7c406008)
1475 /* We found a valid stack-check sequence, return the new PC. */
1479 /* No stack check code in our prologue, return the start_pc. */
1483 /* return pc value after skipping a function prologue and also return
1484 information about a function frame.
1486 in struct rs6000_framedata fdata:
1487 - frameless is TRUE, if function does not have a frame.
1488 - nosavedpc is TRUE, if function does not save %pc value in its frame.
1489 - offset is the initial size of this stack frame --- the amount by
1490 which we decrement the sp to allocate the frame.
1491 - saved_gpr is the number of the first saved gpr.
1492 - saved_fpr is the number of the first saved fpr.
1493 - saved_vr is the number of the first saved vr.
1494 - saved_ev is the number of the first saved ev.
1495 - alloca_reg is the number of the register used for alloca() handling.
1497 - gpr_offset is the offset of the first saved gpr from the previous frame.
1498 - fpr_offset is the offset of the first saved fpr from the previous frame.
1499 - vr_offset is the offset of the first saved vr from the previous frame.
1500 - ev_offset is the offset of the first saved ev from the previous frame.
1501 - lr_offset is the offset of the saved lr
1502 - cr_offset is the offset of the saved cr
1503 - vrsave_offset is the offset of the saved vrsave register. */
1506 skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
, CORE_ADDR lim_pc
,
1507 struct rs6000_framedata
*fdata
)
1509 CORE_ADDR orig_pc
= pc
;
1510 CORE_ADDR last_prologue_pc
= pc
;
1511 CORE_ADDR li_found_pc
= 0;
1515 long alloca_reg_offset
= 0;
1516 long vr_saved_offset
= 0;
1522 int vrsave_reg
= -1;
1525 int minimal_toc_loaded
= 0;
1526 int prev_insn_was_prologue_insn
= 1;
1527 int num_skip_non_prologue_insns
= 0;
1528 int r0_contains_arg
= 0;
1529 const struct bfd_arch_info
*arch_info
= gdbarch_bfd_arch_info (gdbarch
);
1530 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1531 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1533 memset (fdata
, 0, sizeof (struct rs6000_framedata
));
1534 fdata
->saved_gpr
= -1;
1535 fdata
->saved_fpr
= -1;
1536 fdata
->saved_vr
= -1;
1537 fdata
->saved_ev
= -1;
1538 fdata
->alloca_reg
= -1;
1539 fdata
->frameless
= 1;
1540 fdata
->nosavedpc
= 1;
1541 fdata
->lr_register
= -1;
1543 pc
= rs6000_skip_stack_check (gdbarch
, pc
);
1549 /* Sometimes it isn't clear if an instruction is a prologue
1550 instruction or not. When we encounter one of these ambiguous
1551 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
1552 Otherwise, we'll assume that it really is a prologue instruction. */
1553 if (prev_insn_was_prologue_insn
)
1554 last_prologue_pc
= pc
;
1556 /* Stop scanning if we've hit the limit. */
1560 prev_insn_was_prologue_insn
= 1;
1562 /* Fetch the instruction and convert it to an integer. */
1563 if (target_read_memory (pc
, buf
, 4))
1565 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1567 if ((op
& 0xfc1fffff) == 0x7c0802a6)
1569 /* Since shared library / PIC code, which needs to get its
1570 address at runtime, can appear to save more than one link
1584 remember just the first one, but skip over additional
1587 lr_reg
= (op
& 0x03e00000) >> 21;
1589 r0_contains_arg
= 0;
1592 else if ((op
& 0xfc1fffff) == 0x7c000026)
1594 cr_reg
= (op
& 0x03e00000) >> 21;
1596 r0_contains_arg
= 0;
1600 else if ((op
& 0xfc1f0000) == 0xd8010000)
1601 { /* stfd Rx,NUM(r1) */
1602 reg
= GET_SRC_REG (op
);
1603 if (fdata
->saved_fpr
== -1 || fdata
->saved_fpr
> reg
)
1605 fdata
->saved_fpr
= reg
;
1606 fdata
->fpr_offset
= SIGNED_SHORT (op
) + offset
;
1611 else if (((op
& 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
1612 (((op
& 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
1613 (op
& 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
1614 (op
& 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
1617 reg
= GET_SRC_REG (op
);
1618 if ((op
& 0xfc1f0000) == 0xbc010000)
1619 fdata
->gpr_mask
|= ~((1U << reg
) - 1);
1621 fdata
->gpr_mask
|= 1U << reg
;
1622 if (fdata
->saved_gpr
== -1 || fdata
->saved_gpr
> reg
)
1624 fdata
->saved_gpr
= reg
;
1625 if ((op
& 0xfc1f0003) == 0xf8010000)
1627 fdata
->gpr_offset
= SIGNED_SHORT (op
) + offset
;
1632 else if ((op
& 0xffff0000) == 0x3c4c0000
1633 || (op
& 0xffff0000) == 0x3c400000
1634 || (op
& 0xffff0000) == 0x38420000)
1636 /* . 0: addis 2,12,.TOC.-0b@ha
1637 . addi 2,2,.TOC.-0b@l
1641 used by ELFv2 global entry points to set up r2. */
1644 else if (op
== 0x60000000)
1647 /* Allow nops in the prologue, but do not consider them to
1648 be part of the prologue unless followed by other prologue
1650 prev_insn_was_prologue_insn
= 0;
1654 else if ((op
& 0xffff0000) == 0x3c000000)
1655 { /* addis 0,0,NUM, used for >= 32k frames */
1656 fdata
->offset
= (op
& 0x0000ffff) << 16;
1657 fdata
->frameless
= 0;
1658 r0_contains_arg
= 0;
1662 else if ((op
& 0xffff0000) == 0x60000000)
1663 { /* ori 0,0,NUM, 2nd half of >= 32k frames */
1664 fdata
->offset
|= (op
& 0x0000ffff);
1665 fdata
->frameless
= 0;
1666 r0_contains_arg
= 0;
1670 else if (lr_reg
>= 0 &&
1671 ((store_insn_p (op
, lr_reg
, 1, true)) ||
1673 (store_insn_p (op
, lr_reg
,
1674 fdata
->alloca_reg
- tdep
->ppc_gp0_regnum
,
1677 if (store_insn_p (op
, lr_reg
, 1, true))
1678 fdata
->lr_offset
= offset
;
1679 else /* LR save through frame pointer. */
1680 fdata
->lr_offset
= alloca_reg_offset
;
1682 fdata
->nosavedpc
= 0;
1683 /* Invalidate lr_reg, but don't set it to -1.
1684 That would mean that it had never been set. */
1686 if ((op
& 0xfc000003) == 0xf8000000 || /* std */
1687 (op
& 0xfc000000) == 0x90000000) /* stw */
1689 /* Does not update r1, so add displacement to lr_offset. */
1690 fdata
->lr_offset
+= SIGNED_SHORT (op
);
1695 else if (cr_reg
>= 0 &&
1696 (store_insn_p (op
, cr_reg
, 1, true)))
1698 fdata
->cr_offset
= offset
;
1699 /* Invalidate cr_reg, but don't set it to -1.
1700 That would mean that it had never been set. */
1702 if ((op
& 0xfc000003) == 0xf8000000 ||
1703 (op
& 0xfc000000) == 0x90000000)
1705 /* Does not update r1, so add displacement to cr_offset. */
1706 fdata
->cr_offset
+= SIGNED_SHORT (op
);
1711 else if ((op
& 0xfe80ffff) == 0x42800005 && lr_reg
!= -1)
1713 /* bcl 20,xx,.+4 is used to get the current PC, with or without
1714 prediction bits. If the LR has already been saved, we can
1718 else if (op
== 0x48000005)
1725 else if (op
== 0x48000004)
1730 else if ((op
& 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
1731 in V.4 -mminimal-toc */
1732 (op
& 0xffff0000) == 0x3bde0000)
1733 { /* addi 30,30,foo@l */
1737 else if ((op
& 0xfc000001) == 0x48000001)
1741 fdata
->frameless
= 0;
1743 /* If the return address has already been saved, we can skip
1744 calls to blrl (for PIC). */
1745 if (lr_reg
!= -1 && bl_to_blrl_insn_p (pc
, op
, byte_order
))
1751 /* Don't skip over the subroutine call if it is not within
1752 the first three instructions of the prologue and either
1753 we have no line table information or the line info tells
1754 us that the subroutine call is not part of the line
1755 associated with the prologue. */
1756 if ((pc
- orig_pc
) > 8)
1758 struct symtab_and_line prologue_sal
= find_pc_line (orig_pc
, 0);
1759 struct symtab_and_line this_sal
= find_pc_line (pc
, 0);
1761 if ((prologue_sal
.line
== 0)
1762 || (prologue_sal
.line
!= this_sal
.line
))
1766 op
= read_memory_integer (pc
+ 4, 4, byte_order
);
1768 /* At this point, make sure this is not a trampoline
1769 function (a function that simply calls another functions,
1770 and nothing else). If the next is not a nop, this branch
1771 was part of the function prologue. */
1773 if (op
== 0x4def7b82 || op
== 0) /* crorc 15, 15, 15 */
1774 break; /* Don't skip over
1780 /* update stack pointer */
1781 else if ((op
& 0xfc1f0000) == 0x94010000)
1782 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
1783 fdata
->frameless
= 0;
1784 fdata
->offset
= SIGNED_SHORT (op
);
1785 offset
= fdata
->offset
;
1788 else if ((op
& 0xfc1f07fa) == 0x7c01016a)
1789 { /* stwux rX,r1,rY || stdux rX,r1,rY */
1790 /* No way to figure out what r1 is going to be. */
1791 fdata
->frameless
= 0;
1792 offset
= fdata
->offset
;
1795 else if ((op
& 0xfc1f0003) == 0xf8010001)
1796 { /* stdu rX,NUM(r1) */
1797 fdata
->frameless
= 0;
1798 fdata
->offset
= SIGNED_SHORT (op
& ~3UL);
1799 offset
= fdata
->offset
;
1802 else if ((op
& 0xffff0000) == 0x38210000)
1803 { /* addi r1,r1,SIMM */
1804 fdata
->frameless
= 0;
1805 fdata
->offset
+= SIGNED_SHORT (op
);
1806 offset
= fdata
->offset
;
1809 /* Load up minimal toc pointer. Do not treat an epilogue restore
1810 of r31 as a minimal TOC load. */
1811 else if (((op
>> 22) == 0x20f || /* l r31,... or l r30,... */
1812 (op
>> 22) == 0x3af) /* ld r31,... or ld r30,... */
1814 && !minimal_toc_loaded
)
1816 minimal_toc_loaded
= 1;
1819 /* move parameters from argument registers to local variable
1822 else if ((op
& 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
1823 (((op
>> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
1824 (((op
>> 21) & 31) <= 10) &&
1825 ((long) ((op
>> 16) & 31)
1826 >= fdata
->saved_gpr
)) /* Rx: local var reg */
1830 /* store parameters in stack */
1832 /* Move parameters from argument registers to temporary register. */
1833 else if (store_param_on_stack_p (op
, framep
, &r0_contains_arg
))
1837 /* Set up frame pointer */
1839 else if (op
== 0x603d0000) /* oril r29, r1, 0x0 */
1841 fdata
->frameless
= 0;
1843 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
+ 29);
1844 alloca_reg_offset
= offset
;
1847 /* Another way to set up the frame pointer. */
1849 else if (op
== 0x603f0000 /* oril r31, r1, 0x0 */
1850 || op
== 0x7c3f0b78)
1852 fdata
->frameless
= 0;
1854 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
+ 31);
1855 alloca_reg_offset
= offset
;
1858 /* Another way to set up the frame pointer. */
1860 else if ((op
& 0xfc1fffff) == 0x38010000)
1861 { /* addi rX, r1, 0x0 */
1862 fdata
->frameless
= 0;
1864 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
1865 + ((op
& ~0x38010000) >> 21));
1866 alloca_reg_offset
= offset
;
1869 /* AltiVec related instructions. */
1870 /* Store the vrsave register (spr 256) in another register for
1871 later manipulation, or load a register into the vrsave
1872 register. 2 instructions are used: mfvrsave and
1873 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1874 and mtspr SPR256, Rn. */
1875 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1876 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1877 else if ((op
& 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1879 vrsave_reg
= GET_SRC_REG (op
);
1882 else if ((op
& 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1886 /* Store the register where vrsave was saved to onto the stack:
1887 rS is the register where vrsave was stored in a previous
1889 /* 100100 sssss 00001 dddddddd dddddddd */
1890 else if ((op
& 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1892 if (vrsave_reg
== GET_SRC_REG (op
))
1894 fdata
->vrsave_offset
= SIGNED_SHORT (op
) + offset
;
1899 /* Compute the new value of vrsave, by modifying the register
1900 where vrsave was saved to. */
1901 else if (((op
& 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1902 || ((op
& 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1906 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1907 in a pair of insns to save the vector registers on the
1909 /* 001110 00000 00000 iiii iiii iiii iiii */
1910 /* 001110 01110 00000 iiii iiii iiii iiii */
1911 else if ((op
& 0xffff0000) == 0x38000000 /* li r0, SIMM */
1912 || (op
& 0xffff0000) == 0x39c00000) /* li r14, SIMM */
1914 if ((op
& 0xffff0000) == 0x38000000)
1915 r0_contains_arg
= 0;
1917 vr_saved_offset
= SIGNED_SHORT (op
);
1919 /* This insn by itself is not part of the prologue, unless
1920 if part of the pair of insns mentioned above. So do not
1921 record this insn as part of the prologue yet. */
1922 prev_insn_was_prologue_insn
= 0;
1924 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
1925 /* 011111 sssss 11111 00000 00111001110 */
1926 else if ((op
& 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
1928 if (pc
== (li_found_pc
+ 4))
1930 vr_reg
= GET_SRC_REG (op
);
1931 /* If this is the first vector reg to be saved, or if
1932 it has a lower number than others previously seen,
1933 reupdate the frame info. */
1934 if (fdata
->saved_vr
== -1 || fdata
->saved_vr
> vr_reg
)
1936 fdata
->saved_vr
= vr_reg
;
1937 fdata
->vr_offset
= vr_saved_offset
+ offset
;
1939 vr_saved_offset
= -1;
1944 /* End AltiVec related instructions. */
1946 /* Start BookE related instructions. */
1947 /* Store gen register S at (r31+uimm).
1948 Any register less than r13 is volatile, so we don't care. */
1949 /* 000100 sssss 11111 iiiii 01100100001 */
1950 else if (arch_info
->mach
== bfd_mach_ppc_e500
1951 && (op
& 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
1953 if ((op
& 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
1956 ev_reg
= GET_SRC_REG (op
);
1957 imm
= (op
>> 11) & 0x1f;
1958 ev_offset
= imm
* 8;
1959 /* If this is the first vector reg to be saved, or if
1960 it has a lower number than others previously seen,
1961 reupdate the frame info. */
1962 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1964 fdata
->saved_ev
= ev_reg
;
1965 fdata
->ev_offset
= ev_offset
+ offset
;
1970 /* Store gen register rS at (r1+rB). */
1971 /* 000100 sssss 00001 bbbbb 01100100000 */
1972 else if (arch_info
->mach
== bfd_mach_ppc_e500
1973 && (op
& 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
1975 if (pc
== (li_found_pc
+ 4))
1977 ev_reg
= GET_SRC_REG (op
);
1978 /* If this is the first vector reg to be saved, or if
1979 it has a lower number than others previously seen,
1980 reupdate the frame info. */
1981 /* We know the contents of rB from the previous instruction. */
1982 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1984 fdata
->saved_ev
= ev_reg
;
1985 fdata
->ev_offset
= vr_saved_offset
+ offset
;
1987 vr_saved_offset
= -1;
1993 /* Store gen register r31 at (rA+uimm). */
1994 /* 000100 11111 aaaaa iiiii 01100100001 */
1995 else if (arch_info
->mach
== bfd_mach_ppc_e500
1996 && (op
& 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
1998 /* Wwe know that the source register is 31 already, but
1999 it can't hurt to compute it. */
2000 ev_reg
= GET_SRC_REG (op
);
2001 ev_offset
= ((op
>> 11) & 0x1f) * 8;
2002 /* If this is the first vector reg to be saved, or if
2003 it has a lower number than others previously seen,
2004 reupdate the frame info. */
2005 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2007 fdata
->saved_ev
= ev_reg
;
2008 fdata
->ev_offset
= ev_offset
+ offset
;
2013 /* Store gen register S at (r31+r0).
2014 Store param on stack when offset from SP bigger than 4 bytes. */
2015 /* 000100 sssss 11111 00000 01100100000 */
2016 else if (arch_info
->mach
== bfd_mach_ppc_e500
2017 && (op
& 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
2019 if (pc
== (li_found_pc
+ 4))
2021 if ((op
& 0x03e00000) >= 0x01a00000)
2023 ev_reg
= GET_SRC_REG (op
);
2024 /* If this is the first vector reg to be saved, or if
2025 it has a lower number than others previously seen,
2026 reupdate the frame info. */
2027 /* We know the contents of r0 from the previous
2029 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2031 fdata
->saved_ev
= ev_reg
;
2032 fdata
->ev_offset
= vr_saved_offset
+ offset
;
2036 vr_saved_offset
= -1;
2041 /* End BookE related instructions. */
2045 /* Not a recognized prologue instruction.
2046 Handle optimizer code motions into the prologue by continuing
2047 the search if we have no valid frame yet or if the return
2048 address is not yet saved in the frame. Also skip instructions
2049 if some of the GPRs expected to be saved are not yet saved. */
2050 if (fdata
->frameless
== 0 && fdata
->nosavedpc
== 0
2051 && fdata
->saved_gpr
!= -1)
2053 unsigned int all_mask
= ~((1U << fdata
->saved_gpr
) - 1);
2055 if ((fdata
->gpr_mask
& all_mask
) == all_mask
)
2059 if (op
== 0x4e800020 /* blr */
2060 || op
== 0x4e800420) /* bctr */
2061 /* Do not scan past epilogue in frameless functions or
2064 if ((op
& 0xf4000000) == 0x40000000) /* bxx */
2065 /* Never skip branches. */
2068 if (num_skip_non_prologue_insns
++ > max_skip_non_prologue_insns
)
2069 /* Do not scan too many insns, scanning insns is expensive with
2073 /* Continue scanning. */
2074 prev_insn_was_prologue_insn
= 0;
2080 /* I have problems with skipping over __main() that I need to address
2081 * sometime. Previously, I used to use misc_function_vector which
2082 * didn't work as well as I wanted to be. -MGO */
2084 /* If the first thing after skipping a prolog is a branch to a function,
2085 this might be a call to an initializer in main(), introduced by gcc2.
2086 We'd like to skip over it as well. Fortunately, xlc does some extra
2087 work before calling a function right after a prologue, thus we can
2088 single out such gcc2 behaviour. */
2091 if ((op
& 0xfc000001) == 0x48000001)
2092 { /* bl foo, an initializer function? */
2093 op
= read_memory_integer (pc
+ 4, 4, byte_order
);
2095 if (op
== 0x4def7b82)
2096 { /* cror 0xf, 0xf, 0xf (nop) */
2098 /* Check and see if we are in main. If so, skip over this
2099 initializer function as well. */
2101 tmp
= find_pc_misc_function (pc
);
2103 && strcmp (misc_function_vector
[tmp
].name
, main_name ()) == 0)
2109 if (pc
== lim_pc
&& lr_reg
>= 0)
2110 fdata
->lr_register
= lr_reg
;
2112 fdata
->offset
= -fdata
->offset
;
2113 return last_prologue_pc
;
2117 rs6000_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2119 struct rs6000_framedata frame
;
2120 CORE_ADDR limit_pc
, func_addr
, func_end_addr
= 0;
2122 /* See if we can determine the end of the prologue via the symbol table.
2123 If so, then return either PC, or the PC after the prologue, whichever
2125 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end_addr
))
2127 CORE_ADDR post_prologue_pc
2128 = skip_prologue_using_sal (gdbarch
, func_addr
);
2129 if (post_prologue_pc
!= 0)
2130 return std::max (pc
, post_prologue_pc
);
2133 /* Can't determine prologue from the symbol table, need to examine
2136 /* Find an upper limit on the function prologue using the debug
2137 information. If the debug information could not be used to provide
2138 that bound, then use an arbitrary large number as the upper bound. */
2139 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
2141 limit_pc
= pc
+ 100; /* Magic. */
2143 /* Do not allow limit_pc to be past the function end, if we know
2144 where that end is... */
2145 if (func_end_addr
&& limit_pc
> func_end_addr
)
2146 limit_pc
= func_end_addr
;
2148 pc
= skip_prologue (gdbarch
, pc
, limit_pc
, &frame
);
2152 /* When compiling for EABI, some versions of GCC emit a call to __eabi
2153 in the prologue of main().
2155 The function below examines the code pointed at by PC and checks to
2156 see if it corresponds to a call to __eabi. If so, it returns the
2157 address of the instruction following that call. Otherwise, it simply
2161 rs6000_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2163 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2167 if (target_read_memory (pc
, buf
, 4))
2169 op
= extract_unsigned_integer (buf
, 4, byte_order
);
2171 if ((op
& BL_MASK
) == BL_INSTRUCTION
)
2173 CORE_ADDR displ
= op
& BL_DISPLACEMENT_MASK
;
2174 CORE_ADDR call_dest
= pc
+ 4 + displ
;
2175 struct bound_minimal_symbol s
= lookup_minimal_symbol_by_pc (call_dest
);
2177 /* We check for ___eabi (three leading underscores) in addition
2178 to __eabi in case the GCC option "-fleading-underscore" was
2179 used to compile the program. */
2180 if (s
.minsym
!= NULL
2181 && s
.minsym
->linkage_name () != NULL
2182 && (strcmp (s
.minsym
->linkage_name (), "__eabi") == 0
2183 || strcmp (s
.minsym
->linkage_name (), "___eabi") == 0))
2189 /* All the ABI's require 16 byte alignment. */
2191 rs6000_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2193 return (addr
& -16);
2196 /* Return whether handle_inferior_event() should proceed through code
2197 starting at PC in function NAME when stepping.
2199 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
2200 handle memory references that are too distant to fit in instructions
2201 generated by the compiler. For example, if 'foo' in the following
2206 is greater than 32767, the linker might replace the lwz with a branch to
2207 somewhere in @FIX1 that does the load in 2 instructions and then branches
2208 back to where execution should continue.
2210 GDB should silently step over @FIX code, just like AIX dbx does.
2211 Unfortunately, the linker uses the "b" instruction for the
2212 branches, meaning that the link register doesn't get set.
2213 Therefore, GDB's usual step_over_function () mechanism won't work.
2215 Instead, use the gdbarch_skip_trampoline_code and
2216 gdbarch_skip_trampoline_code hooks in handle_inferior_event() to skip past
2220 rs6000_in_solib_return_trampoline (struct gdbarch
*gdbarch
,
2221 CORE_ADDR pc
, const char *name
)
2223 return name
&& startswith (name
, "@FIX");
2226 /* Skip code that the user doesn't want to see when stepping:
2228 1. Indirect function calls use a piece of trampoline code to do context
2229 switching, i.e. to set the new TOC table. Skip such code if we are on
2230 its first instruction (as when we have single-stepped to here).
2232 2. Skip shared library trampoline code (which is different from
2233 indirect function call trampolines).
2235 3. Skip bigtoc fixup code.
2237 Result is desired PC to step until, or NULL if we are not in
2238 code that should be skipped. */
2241 rs6000_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
2243 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2244 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2245 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2246 unsigned int ii
, op
;
2248 CORE_ADDR solib_target_pc
;
2249 struct bound_minimal_symbol msymbol
;
2251 static unsigned trampoline_code
[] =
2253 0x800b0000, /* l r0,0x0(r11) */
2254 0x90410014, /* st r2,0x14(r1) */
2255 0x7c0903a6, /* mtctr r0 */
2256 0x804b0004, /* l r2,0x4(r11) */
2257 0x816b0008, /* l r11,0x8(r11) */
2258 0x4e800420, /* bctr */
2259 0x4e800020, /* br */
2263 /* Check for bigtoc fixup code. */
2264 msymbol
= lookup_minimal_symbol_by_pc (pc
);
2266 && rs6000_in_solib_return_trampoline (gdbarch
, pc
,
2267 msymbol
.minsym
->linkage_name ()))
2269 /* Double-check that the third instruction from PC is relative "b". */
2270 op
= read_memory_integer (pc
+ 8, 4, byte_order
);
2271 if ((op
& 0xfc000003) == 0x48000000)
2273 /* Extract bits 6-29 as a signed 24-bit relative word address and
2274 add it to the containing PC. */
2275 rel
= ((int)(op
<< 6) >> 6);
2276 return pc
+ 8 + rel
;
2280 /* If pc is in a shared library trampoline, return its target. */
2281 solib_target_pc
= find_solib_trampoline_target (frame
, pc
);
2282 if (solib_target_pc
)
2283 return solib_target_pc
;
2285 for (ii
= 0; trampoline_code
[ii
]; ++ii
)
2287 op
= read_memory_integer (pc
+ (ii
* 4), 4, byte_order
);
2288 if (op
!= trampoline_code
[ii
])
2291 ii
= get_frame_register_unsigned (frame
, 11); /* r11 holds destination
2293 pc
= read_memory_unsigned_integer (ii
, tdep
->wordsize
, byte_order
);
2297 /* ISA-specific vector types. */
2299 static struct type
*
2300 rs6000_builtin_type_vec64 (struct gdbarch
*gdbarch
)
2302 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2304 if (!tdep
->ppc_builtin_type_vec64
)
2306 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2308 /* The type we're building is this: */
2310 union __gdb_builtin_type_vec64
2314 int32_t v2_int32
[2];
2315 int16_t v4_int16
[4];
2322 t
= arch_composite_type (gdbarch
,
2323 "__ppc_builtin_type_vec64", TYPE_CODE_UNION
);
2324 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
2325 append_composite_type_field (t
, "v2_float",
2326 init_vector_type (bt
->builtin_float
, 2));
2327 append_composite_type_field (t
, "v2_int32",
2328 init_vector_type (bt
->builtin_int32
, 2));
2329 append_composite_type_field (t
, "v4_int16",
2330 init_vector_type (bt
->builtin_int16
, 4));
2331 append_composite_type_field (t
, "v8_int8",
2332 init_vector_type (bt
->builtin_int8
, 8));
2334 t
->set_is_vector (true);
2335 t
->set_name ("ppc_builtin_type_vec64");
2336 tdep
->ppc_builtin_type_vec64
= t
;
2339 return tdep
->ppc_builtin_type_vec64
;
2342 /* Vector 128 type. */
2344 static struct type
*
2345 rs6000_builtin_type_vec128 (struct gdbarch
*gdbarch
)
2347 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2349 if (!tdep
->ppc_builtin_type_vec128
)
2351 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2353 /* The type we're building is this
2355 type = union __ppc_builtin_type_vec128 {
2357 double v2_double[2];
2359 int32_t v4_int32[4];
2360 int16_t v8_int16[8];
2361 int8_t v16_int8[16];
2367 t
= arch_composite_type (gdbarch
,
2368 "__ppc_builtin_type_vec128", TYPE_CODE_UNION
);
2369 append_composite_type_field (t
, "uint128", bt
->builtin_uint128
);
2370 append_composite_type_field (t
, "v2_double",
2371 init_vector_type (bt
->builtin_double
, 2));
2372 append_composite_type_field (t
, "v4_float",
2373 init_vector_type (bt
->builtin_float
, 4));
2374 append_composite_type_field (t
, "v4_int32",
2375 init_vector_type (bt
->builtin_int32
, 4));
2376 append_composite_type_field (t
, "v8_int16",
2377 init_vector_type (bt
->builtin_int16
, 8));
2378 append_composite_type_field (t
, "v16_int8",
2379 init_vector_type (bt
->builtin_int8
, 16));
2381 t
->set_is_vector (true);
2382 t
->set_name ("ppc_builtin_type_vec128");
2383 tdep
->ppc_builtin_type_vec128
= t
;
2386 return tdep
->ppc_builtin_type_vec128
;
2389 /* Return the name of register number REGNO, or the empty string if it
2390 is an anonymous register. */
2393 rs6000_register_name (struct gdbarch
*gdbarch
, int regno
)
2395 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2397 /* The upper half "registers" have names in the XML description,
2398 but we present only the low GPRs and the full 64-bit registers
2400 if (tdep
->ppc_ev0_upper_regnum
>= 0
2401 && tdep
->ppc_ev0_upper_regnum
<= regno
2402 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
2405 /* Hide the upper halves of the vs0~vs31 registers. */
2406 if (tdep
->ppc_vsr0_regnum
>= 0
2407 && tdep
->ppc_vsr0_upper_regnum
<= regno
2408 && regno
< tdep
->ppc_vsr0_upper_regnum
+ ppc_num_gprs
)
2411 /* Hide the upper halves of the cvs0~cvs31 registers. */
2412 if (PPC_CVSR0_UPPER_REGNUM
<= regno
2413 && regno
< PPC_CVSR0_UPPER_REGNUM
+ ppc_num_gprs
)
2416 /* Check if the SPE pseudo registers are available. */
2417 if (IS_SPE_PSEUDOREG (tdep
, regno
))
2419 static const char *const spe_regnames
[] = {
2420 "ev0", "ev1", "ev2", "ev3", "ev4", "ev5", "ev6", "ev7",
2421 "ev8", "ev9", "ev10", "ev11", "ev12", "ev13", "ev14", "ev15",
2422 "ev16", "ev17", "ev18", "ev19", "ev20", "ev21", "ev22", "ev23",
2423 "ev24", "ev25", "ev26", "ev27", "ev28", "ev29", "ev30", "ev31",
2425 return spe_regnames
[regno
- tdep
->ppc_ev0_regnum
];
2428 /* Check if the decimal128 pseudo-registers are available. */
2429 if (IS_DFP_PSEUDOREG (tdep
, regno
))
2431 static const char *const dfp128_regnames
[] = {
2432 "dl0", "dl1", "dl2", "dl3",
2433 "dl4", "dl5", "dl6", "dl7",
2434 "dl8", "dl9", "dl10", "dl11",
2435 "dl12", "dl13", "dl14", "dl15"
2437 return dfp128_regnames
[regno
- tdep
->ppc_dl0_regnum
];
2440 /* Check if this is a vX alias for a raw vrX vector register. */
2441 if (IS_V_ALIAS_PSEUDOREG (tdep
, regno
))
2443 static const char *const vector_alias_regnames
[] = {
2444 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
2445 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
2446 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
2447 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
2449 return vector_alias_regnames
[regno
- tdep
->ppc_v0_alias_regnum
];
2452 /* Check if this is a VSX pseudo-register. */
2453 if (IS_VSX_PSEUDOREG (tdep
, regno
))
2455 static const char *const vsx_regnames
[] = {
2456 "vs0", "vs1", "vs2", "vs3", "vs4", "vs5", "vs6", "vs7",
2457 "vs8", "vs9", "vs10", "vs11", "vs12", "vs13", "vs14",
2458 "vs15", "vs16", "vs17", "vs18", "vs19", "vs20", "vs21",
2459 "vs22", "vs23", "vs24", "vs25", "vs26", "vs27", "vs28",
2460 "vs29", "vs30", "vs31", "vs32", "vs33", "vs34", "vs35",
2461 "vs36", "vs37", "vs38", "vs39", "vs40", "vs41", "vs42",
2462 "vs43", "vs44", "vs45", "vs46", "vs47", "vs48", "vs49",
2463 "vs50", "vs51", "vs52", "vs53", "vs54", "vs55", "vs56",
2464 "vs57", "vs58", "vs59", "vs60", "vs61", "vs62", "vs63"
2466 return vsx_regnames
[regno
- tdep
->ppc_vsr0_regnum
];
2469 /* Check if the this is a Extended FP pseudo-register. */
2470 if (IS_EFP_PSEUDOREG (tdep
, regno
))
2472 static const char *const efpr_regnames
[] = {
2473 "f32", "f33", "f34", "f35", "f36", "f37", "f38",
2474 "f39", "f40", "f41", "f42", "f43", "f44", "f45",
2475 "f46", "f47", "f48", "f49", "f50", "f51",
2476 "f52", "f53", "f54", "f55", "f56", "f57",
2477 "f58", "f59", "f60", "f61", "f62", "f63"
2479 return efpr_regnames
[regno
- tdep
->ppc_efpr0_regnum
];
2482 /* Check if this is a Checkpointed DFP pseudo-register. */
2483 if (IS_CDFP_PSEUDOREG (tdep
, regno
))
2485 static const char *const cdfp128_regnames
[] = {
2486 "cdl0", "cdl1", "cdl2", "cdl3",
2487 "cdl4", "cdl5", "cdl6", "cdl7",
2488 "cdl8", "cdl9", "cdl10", "cdl11",
2489 "cdl12", "cdl13", "cdl14", "cdl15"
2491 return cdfp128_regnames
[regno
- tdep
->ppc_cdl0_regnum
];
2494 /* Check if this is a Checkpointed VSX pseudo-register. */
2495 if (IS_CVSX_PSEUDOREG (tdep
, regno
))
2497 static const char *const cvsx_regnames
[] = {
2498 "cvs0", "cvs1", "cvs2", "cvs3", "cvs4", "cvs5", "cvs6", "cvs7",
2499 "cvs8", "cvs9", "cvs10", "cvs11", "cvs12", "cvs13", "cvs14",
2500 "cvs15", "cvs16", "cvs17", "cvs18", "cvs19", "cvs20", "cvs21",
2501 "cvs22", "cvs23", "cvs24", "cvs25", "cvs26", "cvs27", "cvs28",
2502 "cvs29", "cvs30", "cvs31", "cvs32", "cvs33", "cvs34", "cvs35",
2503 "cvs36", "cvs37", "cvs38", "cvs39", "cvs40", "cvs41", "cvs42",
2504 "cvs43", "cvs44", "cvs45", "cvs46", "cvs47", "cvs48", "cvs49",
2505 "cvs50", "cvs51", "cvs52", "cvs53", "cvs54", "cvs55", "cvs56",
2506 "cvs57", "cvs58", "cvs59", "cvs60", "cvs61", "cvs62", "cvs63"
2508 return cvsx_regnames
[regno
- tdep
->ppc_cvsr0_regnum
];
2511 /* Check if the this is a Checkpointed Extended FP pseudo-register. */
2512 if (IS_CEFP_PSEUDOREG (tdep
, regno
))
2514 static const char *const cefpr_regnames
[] = {
2515 "cf32", "cf33", "cf34", "cf35", "cf36", "cf37", "cf38",
2516 "cf39", "cf40", "cf41", "cf42", "cf43", "cf44", "cf45",
2517 "cf46", "cf47", "cf48", "cf49", "cf50", "cf51",
2518 "cf52", "cf53", "cf54", "cf55", "cf56", "cf57",
2519 "cf58", "cf59", "cf60", "cf61", "cf62", "cf63"
2521 return cefpr_regnames
[regno
- tdep
->ppc_cefpr0_regnum
];
2524 return tdesc_register_name (gdbarch
, regno
);
2527 /* Return the GDB type object for the "standard" data type of data in
2530 static struct type
*
2531 rs6000_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2533 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2535 /* These are the e500 pseudo-registers. */
2536 if (IS_SPE_PSEUDOREG (tdep
, regnum
))
2537 return rs6000_builtin_type_vec64 (gdbarch
);
2538 else if (IS_DFP_PSEUDOREG (tdep
, regnum
)
2539 || IS_CDFP_PSEUDOREG (tdep
, regnum
))
2540 /* PPC decimal128 pseudo-registers. */
2541 return builtin_type (gdbarch
)->builtin_declong
;
2542 else if (IS_V_ALIAS_PSEUDOREG (tdep
, regnum
))
2543 return gdbarch_register_type (gdbarch
,
2544 tdep
->ppc_vr0_regnum
2546 - tdep
->ppc_v0_alias_regnum
));
2547 else if (IS_VSX_PSEUDOREG (tdep
, regnum
)
2548 || IS_CVSX_PSEUDOREG (tdep
, regnum
))
2549 /* POWER7 VSX pseudo-registers. */
2550 return rs6000_builtin_type_vec128 (gdbarch
);
2551 else if (IS_EFP_PSEUDOREG (tdep
, regnum
)
2552 || IS_CEFP_PSEUDOREG (tdep
, regnum
))
2553 /* POWER7 Extended FP pseudo-registers. */
2554 return builtin_type (gdbarch
)->builtin_double
;
2556 internal_error (__FILE__
, __LINE__
,
2557 _("rs6000_pseudo_register_type: "
2558 "called on unexpected register '%s' (%d)"),
2559 gdbarch_register_name (gdbarch
, regnum
), regnum
);
2562 /* Check if REGNUM is a member of REGGROUP. We only need to handle
2563 the vX aliases for the vector registers by always returning false
2564 to avoid duplicated information in "info register vector/all",
2565 since the raw vrX registers will already show in these cases. For
2566 other pseudo-registers we use the default membership function. */
2569 rs6000_pseudo_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
2570 struct reggroup
*group
)
2572 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2574 if (IS_V_ALIAS_PSEUDOREG (tdep
, regnum
))
2577 return default_register_reggroup_p (gdbarch
, regnum
, group
);
2580 /* The register format for RS/6000 floating point registers is always
2581 double, we need a conversion if the memory format is float. */
2584 rs6000_convert_register_p (struct gdbarch
*gdbarch
, int regnum
,
2587 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2589 return (tdep
->ppc_fp0_regnum
>= 0
2590 && regnum
>= tdep
->ppc_fp0_regnum
2591 && regnum
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
2592 && type
->code () == TYPE_CODE_FLT
2593 && TYPE_LENGTH (type
)
2594 != TYPE_LENGTH (builtin_type (gdbarch
)->builtin_double
));
2598 rs6000_register_to_value (struct frame_info
*frame
,
2602 int *optimizedp
, int *unavailablep
)
2604 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2605 gdb_byte from
[PPC_MAX_REGISTER_SIZE
];
2607 gdb_assert (type
->code () == TYPE_CODE_FLT
);
2609 if (!get_frame_register_bytes (frame
, regnum
, 0,
2610 register_size (gdbarch
, regnum
),
2611 from
, optimizedp
, unavailablep
))
2614 target_float_convert (from
, builtin_type (gdbarch
)->builtin_double
,
2616 *optimizedp
= *unavailablep
= 0;
2621 rs6000_value_to_register (struct frame_info
*frame
,
2624 const gdb_byte
*from
)
2626 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2627 gdb_byte to
[PPC_MAX_REGISTER_SIZE
];
2629 gdb_assert (type
->code () == TYPE_CODE_FLT
);
2631 target_float_convert (from
, type
,
2632 to
, builtin_type (gdbarch
)->builtin_double
);
2633 put_frame_register (frame
, regnum
, to
);
2636 /* The type of a function that moves the value of REG between CACHE
2637 or BUF --- in either direction. */
2638 typedef enum register_status (*move_ev_register_func
) (struct regcache
*,
2641 /* Move SPE vector register values between a 64-bit buffer and the two
2642 32-bit raw register halves in a regcache. This function handles
2643 both splitting a 64-bit value into two 32-bit halves, and joining
2644 two halves into a whole 64-bit value, depending on the function
2645 passed as the MOVE argument.
2647 EV_REG must be the number of an SPE evN vector register --- a
2648 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a
2651 Call MOVE once for each 32-bit half of that register, passing
2652 REGCACHE, the number of the raw register corresponding to that
2653 half, and the address of the appropriate half of BUFFER.
2655 For example, passing 'regcache_raw_read' as the MOVE function will
2656 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing
2657 'regcache_raw_supply' will supply the contents of BUFFER to the
2658 appropriate pair of raw registers in REGCACHE.
2660 You may need to cast away some 'const' qualifiers when passing
2661 MOVE, since this function can't tell at compile-time which of
2662 REGCACHE or BUFFER is acting as the source of the data. If C had
2663 co-variant type qualifiers, ... */
2665 static enum register_status
2666 e500_move_ev_register (move_ev_register_func move
,
2667 struct regcache
*regcache
, int ev_reg
, void *buffer
)
2669 struct gdbarch
*arch
= regcache
->arch ();
2670 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
2672 gdb_byte
*byte_buffer
= (gdb_byte
*) buffer
;
2673 enum register_status status
;
2675 gdb_assert (IS_SPE_PSEUDOREG (tdep
, ev_reg
));
2677 reg_index
= ev_reg
- tdep
->ppc_ev0_regnum
;
2679 if (gdbarch_byte_order (arch
) == BFD_ENDIAN_BIG
)
2681 status
= move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2683 if (status
== REG_VALID
)
2684 status
= move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
,
2689 status
= move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
, byte_buffer
);
2690 if (status
== REG_VALID
)
2691 status
= move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2698 static enum register_status
2699 do_regcache_raw_write (struct regcache
*regcache
, int regnum
, void *buffer
)
2701 regcache
->raw_write (regnum
, (const gdb_byte
*) buffer
);
2706 static enum register_status
2707 e500_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2708 int ev_reg
, gdb_byte
*buffer
)
2710 struct gdbarch
*arch
= regcache
->arch ();
2711 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
2713 enum register_status status
;
2715 gdb_assert (IS_SPE_PSEUDOREG (tdep
, ev_reg
));
2717 reg_index
= ev_reg
- tdep
->ppc_ev0_regnum
;
2719 if (gdbarch_byte_order (arch
) == BFD_ENDIAN_BIG
)
2721 status
= regcache
->raw_read (tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2723 if (status
== REG_VALID
)
2724 status
= regcache
->raw_read (tdep
->ppc_gp0_regnum
+ reg_index
,
2729 status
= regcache
->raw_read (tdep
->ppc_gp0_regnum
+ reg_index
, buffer
);
2730 if (status
== REG_VALID
)
2731 status
= regcache
->raw_read (tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2740 e500_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2741 int reg_nr
, const gdb_byte
*buffer
)
2743 e500_move_ev_register (do_regcache_raw_write
, regcache
,
2744 reg_nr
, (void *) buffer
);
2747 /* Read method for DFP pseudo-registers. */
2748 static enum register_status
2749 dfp_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2750 int reg_nr
, gdb_byte
*buffer
)
2752 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2754 enum register_status status
;
2756 if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2758 reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2759 fp0
= PPC_F0_REGNUM
;
2763 gdb_assert (IS_CDFP_PSEUDOREG (tdep
, reg_nr
));
2765 reg_index
= reg_nr
- tdep
->ppc_cdl0_regnum
;
2766 fp0
= PPC_CF0_REGNUM
;
2769 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2771 /* Read two FP registers to form a whole dl register. */
2772 status
= regcache
->raw_read (fp0
+ 2 * reg_index
, buffer
);
2773 if (status
== REG_VALID
)
2774 status
= regcache
->raw_read (fp0
+ 2 * reg_index
+ 1,
2779 status
= regcache
->raw_read (fp0
+ 2 * reg_index
+ 1, buffer
);
2780 if (status
== REG_VALID
)
2781 status
= regcache
->raw_read (fp0
+ 2 * reg_index
, buffer
+ 8);
2787 /* Write method for DFP pseudo-registers. */
2789 dfp_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2790 int reg_nr
, const gdb_byte
*buffer
)
2792 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2795 if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2797 reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2798 fp0
= PPC_F0_REGNUM
;
2802 gdb_assert (IS_CDFP_PSEUDOREG (tdep
, reg_nr
));
2804 reg_index
= reg_nr
- tdep
->ppc_cdl0_regnum
;
2805 fp0
= PPC_CF0_REGNUM
;
2808 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2810 /* Write each half of the dl register into a separate
2812 regcache
->raw_write (fp0
+ 2 * reg_index
, buffer
);
2813 regcache
->raw_write (fp0
+ 2 * reg_index
+ 1, buffer
+ 8);
2817 regcache
->raw_write (fp0
+ 2 * reg_index
+ 1, buffer
);
2818 regcache
->raw_write (fp0
+ 2 * reg_index
, buffer
+ 8);
2822 /* Read method for the vX aliases for the raw vrX registers. */
2824 static enum register_status
2825 v_alias_pseudo_register_read (struct gdbarch
*gdbarch
,
2826 readable_regcache
*regcache
, int reg_nr
,
2829 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2830 gdb_assert (IS_V_ALIAS_PSEUDOREG (tdep
, reg_nr
));
2832 return regcache
->raw_read (tdep
->ppc_vr0_regnum
2833 + (reg_nr
- tdep
->ppc_v0_alias_regnum
),
2837 /* Write method for the vX aliases for the raw vrX registers. */
2840 v_alias_pseudo_register_write (struct gdbarch
*gdbarch
,
2841 struct regcache
*regcache
,
2842 int reg_nr
, const gdb_byte
*buffer
)
2844 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2845 gdb_assert (IS_V_ALIAS_PSEUDOREG (tdep
, reg_nr
));
2847 regcache
->raw_write (tdep
->ppc_vr0_regnum
2848 + (reg_nr
- tdep
->ppc_v0_alias_regnum
), buffer
);
2851 /* Read method for POWER7 VSX pseudo-registers. */
2852 static enum register_status
2853 vsx_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2854 int reg_nr
, gdb_byte
*buffer
)
2856 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2857 int reg_index
, vr0
, fp0
, vsr0_upper
;
2858 enum register_status status
;
2860 if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
2862 reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
2863 vr0
= PPC_VR0_REGNUM
;
2864 fp0
= PPC_F0_REGNUM
;
2865 vsr0_upper
= PPC_VSR0_UPPER_REGNUM
;
2869 gdb_assert (IS_CVSX_PSEUDOREG (tdep
, reg_nr
));
2871 reg_index
= reg_nr
- tdep
->ppc_cvsr0_regnum
;
2872 vr0
= PPC_CVR0_REGNUM
;
2873 fp0
= PPC_CF0_REGNUM
;
2874 vsr0_upper
= PPC_CVSR0_UPPER_REGNUM
;
2877 /* Read the portion that overlaps the VMX registers. */
2879 status
= regcache
->raw_read (vr0
+ reg_index
- 32, buffer
);
2881 /* Read the portion that overlaps the FPR registers. */
2882 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2884 status
= regcache
->raw_read (fp0
+ reg_index
, buffer
);
2885 if (status
== REG_VALID
)
2886 status
= regcache
->raw_read (vsr0_upper
+ reg_index
,
2891 status
= regcache
->raw_read (fp0
+ reg_index
, buffer
+ 8);
2892 if (status
== REG_VALID
)
2893 status
= regcache
->raw_read (vsr0_upper
+ reg_index
, buffer
);
2899 /* Write method for POWER7 VSX pseudo-registers. */
2901 vsx_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2902 int reg_nr
, const gdb_byte
*buffer
)
2904 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2905 int reg_index
, vr0
, fp0
, vsr0_upper
;
2907 if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
2909 reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
2910 vr0
= PPC_VR0_REGNUM
;
2911 fp0
= PPC_F0_REGNUM
;
2912 vsr0_upper
= PPC_VSR0_UPPER_REGNUM
;
2916 gdb_assert (IS_CVSX_PSEUDOREG (tdep
, reg_nr
));
2918 reg_index
= reg_nr
- tdep
->ppc_cvsr0_regnum
;
2919 vr0
= PPC_CVR0_REGNUM
;
2920 fp0
= PPC_CF0_REGNUM
;
2921 vsr0_upper
= PPC_CVSR0_UPPER_REGNUM
;
2924 /* Write the portion that overlaps the VMX registers. */
2926 regcache
->raw_write (vr0
+ reg_index
- 32, buffer
);
2928 /* Write the portion that overlaps the FPR registers. */
2929 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2931 regcache
->raw_write (fp0
+ reg_index
, buffer
);
2932 regcache
->raw_write (vsr0_upper
+ reg_index
, buffer
+ 8);
2936 regcache
->raw_write (fp0
+ reg_index
, buffer
+ 8);
2937 regcache
->raw_write (vsr0_upper
+ reg_index
, buffer
);
2941 /* Read method for POWER7 Extended FP pseudo-registers. */
2942 static enum register_status
2943 efp_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2944 int reg_nr
, gdb_byte
*buffer
)
2946 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2949 if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
2951 reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
2952 vr0
= PPC_VR0_REGNUM
;
2956 gdb_assert (IS_CEFP_PSEUDOREG (tdep
, reg_nr
));
2958 reg_index
= reg_nr
- tdep
->ppc_cefpr0_regnum
;
2959 vr0
= PPC_CVR0_REGNUM
;
2962 int offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 0 : 8;
2964 /* Read the portion that overlaps the VMX register. */
2965 return regcache
->raw_read_part (vr0
+ reg_index
, offset
,
2966 register_size (gdbarch
, reg_nr
),
2970 /* Write method for POWER7 Extended FP pseudo-registers. */
2972 efp_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2973 int reg_nr
, const gdb_byte
*buffer
)
2975 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2977 int offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 0 : 8;
2979 if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
2981 reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
2982 vr0
= PPC_VR0_REGNUM
;
2986 gdb_assert (IS_CEFP_PSEUDOREG (tdep
, reg_nr
));
2988 reg_index
= reg_nr
- tdep
->ppc_cefpr0_regnum
;
2989 vr0
= PPC_CVR0_REGNUM
;
2991 /* The call to raw_write_part fails silently if the initial read
2992 of the read-update-write sequence returns an invalid status,
2993 so we check this manually and throw an error if needed. */
2994 regcache
->raw_update (vr0
+ reg_index
);
2995 if (regcache
->get_register_status (vr0
+ reg_index
) != REG_VALID
)
2996 error (_("Cannot write to the checkpointed EFP register, "
2997 "the corresponding vector register is unavailable."));
3000 /* Write the portion that overlaps the VMX register. */
3001 regcache
->raw_write_part (vr0
+ reg_index
, offset
,
3002 register_size (gdbarch
, reg_nr
), buffer
);
3005 static enum register_status
3006 rs6000_pseudo_register_read (struct gdbarch
*gdbarch
,
3007 readable_regcache
*regcache
,
3008 int reg_nr
, gdb_byte
*buffer
)
3010 struct gdbarch
*regcache_arch
= regcache
->arch ();
3011 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3013 gdb_assert (regcache_arch
== gdbarch
);
3015 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
3016 return e500_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
3017 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
)
3018 || IS_CDFP_PSEUDOREG (tdep
, reg_nr
))
3019 return dfp_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
3020 else if (IS_V_ALIAS_PSEUDOREG (tdep
, reg_nr
))
3021 return v_alias_pseudo_register_read (gdbarch
, regcache
, reg_nr
,
3023 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
)
3024 || IS_CVSX_PSEUDOREG (tdep
, reg_nr
))
3025 return vsx_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
3026 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
)
3027 || IS_CEFP_PSEUDOREG (tdep
, reg_nr
))
3028 return efp_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
3030 internal_error (__FILE__
, __LINE__
,
3031 _("rs6000_pseudo_register_read: "
3032 "called on unexpected register '%s' (%d)"),
3033 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
3037 rs6000_pseudo_register_write (struct gdbarch
*gdbarch
,
3038 struct regcache
*regcache
,
3039 int reg_nr
, const gdb_byte
*buffer
)
3041 struct gdbarch
*regcache_arch
= regcache
->arch ();
3042 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3044 gdb_assert (regcache_arch
== gdbarch
);
3046 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
3047 e500_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
3048 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
)
3049 || IS_CDFP_PSEUDOREG (tdep
, reg_nr
))
3050 dfp_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
3051 else if (IS_V_ALIAS_PSEUDOREG (tdep
, reg_nr
))
3052 v_alias_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
3053 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
)
3054 || IS_CVSX_PSEUDOREG (tdep
, reg_nr
))
3055 vsx_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
3056 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
)
3057 || IS_CEFP_PSEUDOREG (tdep
, reg_nr
))
3058 efp_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
3060 internal_error (__FILE__
, __LINE__
,
3061 _("rs6000_pseudo_register_write: "
3062 "called on unexpected register '%s' (%d)"),
3063 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
3066 /* Set the register mask in AX with the registers that form the DFP or
3067 checkpointed DFP pseudo-register REG_NR. */
3070 dfp_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
3071 struct agent_expr
*ax
, int reg_nr
)
3073 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3076 if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
3078 reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
3079 fp0
= PPC_F0_REGNUM
;
3083 gdb_assert (IS_CDFP_PSEUDOREG (tdep
, reg_nr
));
3085 reg_index
= reg_nr
- tdep
->ppc_cdl0_regnum
;
3086 fp0
= PPC_CF0_REGNUM
;
3089 ax_reg_mask (ax
, fp0
+ 2 * reg_index
);
3090 ax_reg_mask (ax
, fp0
+ 2 * reg_index
+ 1);
3093 /* Set the register mask in AX with the raw vector register that
3094 corresponds to its REG_NR alias. */
3097 v_alias_pseudo_register_collect (struct gdbarch
*gdbarch
,
3098 struct agent_expr
*ax
, int reg_nr
)
3100 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3101 gdb_assert (IS_V_ALIAS_PSEUDOREG (tdep
, reg_nr
));
3103 ax_reg_mask (ax
, tdep
->ppc_vr0_regnum
3104 + (reg_nr
- tdep
->ppc_v0_alias_regnum
));
3107 /* Set the register mask in AX with the registers that form the VSX or
3108 checkpointed VSX pseudo-register REG_NR. */
3111 vsx_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
3112 struct agent_expr
*ax
, int reg_nr
)
3114 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3115 int reg_index
, vr0
, fp0
, vsr0_upper
;
3117 if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
3119 reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
3120 vr0
= PPC_VR0_REGNUM
;
3121 fp0
= PPC_F0_REGNUM
;
3122 vsr0_upper
= PPC_VSR0_UPPER_REGNUM
;
3126 gdb_assert (IS_CVSX_PSEUDOREG (tdep
, reg_nr
));
3128 reg_index
= reg_nr
- tdep
->ppc_cvsr0_regnum
;
3129 vr0
= PPC_CVR0_REGNUM
;
3130 fp0
= PPC_CF0_REGNUM
;
3131 vsr0_upper
= PPC_CVSR0_UPPER_REGNUM
;
3136 ax_reg_mask (ax
, vr0
+ reg_index
- 32);
3140 ax_reg_mask (ax
, fp0
+ reg_index
);
3141 ax_reg_mask (ax
, vsr0_upper
+ reg_index
);
3145 /* Set the register mask in AX with the register that corresponds to
3146 the EFP or checkpointed EFP pseudo-register REG_NR. */
3149 efp_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
3150 struct agent_expr
*ax
, int reg_nr
)
3152 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3155 if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
3157 reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
3158 vr0
= PPC_VR0_REGNUM
;
3162 gdb_assert (IS_CEFP_PSEUDOREG (tdep
, reg_nr
));
3164 reg_index
= reg_nr
- tdep
->ppc_cefpr0_regnum
;
3165 vr0
= PPC_CVR0_REGNUM
;
3168 ax_reg_mask (ax
, vr0
+ reg_index
);
3172 rs6000_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
3173 struct agent_expr
*ax
, int reg_nr
)
3175 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3176 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
3178 int reg_index
= reg_nr
- tdep
->ppc_ev0_regnum
;
3179 ax_reg_mask (ax
, tdep
->ppc_gp0_regnum
+ reg_index
);
3180 ax_reg_mask (ax
, tdep
->ppc_ev0_upper_regnum
+ reg_index
);
3182 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
)
3183 || IS_CDFP_PSEUDOREG (tdep
, reg_nr
))
3185 dfp_ax_pseudo_register_collect (gdbarch
, ax
, reg_nr
);
3187 else if (IS_V_ALIAS_PSEUDOREG (tdep
, reg_nr
))
3189 v_alias_pseudo_register_collect (gdbarch
, ax
, reg_nr
);
3191 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
)
3192 || IS_CVSX_PSEUDOREG (tdep
, reg_nr
))
3194 vsx_ax_pseudo_register_collect (gdbarch
, ax
, reg_nr
);
3196 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
)
3197 || IS_CEFP_PSEUDOREG (tdep
, reg_nr
))
3199 efp_ax_pseudo_register_collect (gdbarch
, ax
, reg_nr
);
3202 internal_error (__FILE__
, __LINE__
,
3203 _("rs6000_pseudo_register_collect: "
3204 "called on unexpected register '%s' (%d)"),
3205 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
3211 rs6000_gen_return_address (struct gdbarch
*gdbarch
,
3212 struct agent_expr
*ax
, struct axs_value
*value
,
3215 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3216 value
->type
= register_type (gdbarch
, tdep
->ppc_lr_regnum
);
3217 value
->kind
= axs_lvalue_register
;
3218 value
->u
.reg
= tdep
->ppc_lr_regnum
;
3222 /* Convert a DBX STABS register number to a GDB register number. */
3224 rs6000_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
3226 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3228 if (0 <= num
&& num
<= 31)
3229 return tdep
->ppc_gp0_regnum
+ num
;
3230 else if (32 <= num
&& num
<= 63)
3231 /* FIXME: jimb/2004-05-05: What should we do when the debug info
3232 specifies registers the architecture doesn't have? Our
3233 callers don't check the value we return. */
3234 return tdep
->ppc_fp0_regnum
+ (num
- 32);
3235 else if (77 <= num
&& num
<= 108)
3236 return tdep
->ppc_vr0_regnum
+ (num
- 77);
3237 else if (1200 <= num
&& num
< 1200 + 32)
3238 return tdep
->ppc_ev0_upper_regnum
+ (num
- 1200);
3243 return tdep
->ppc_mq_regnum
;
3245 return tdep
->ppc_lr_regnum
;
3247 return tdep
->ppc_ctr_regnum
;
3249 return tdep
->ppc_xer_regnum
;
3251 return tdep
->ppc_vrsave_regnum
;
3253 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
3255 return tdep
->ppc_acc_regnum
;
3257 return tdep
->ppc_spefscr_regnum
;
3264 /* Convert a Dwarf 2 register number to a GDB register number. */
3266 rs6000_dwarf2_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
3268 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3270 if (0 <= num
&& num
<= 31)
3271 return tdep
->ppc_gp0_regnum
+ num
;
3272 else if (32 <= num
&& num
<= 63)
3273 /* FIXME: jimb/2004-05-05: What should we do when the debug info
3274 specifies registers the architecture doesn't have? Our
3275 callers don't check the value we return. */
3276 return tdep
->ppc_fp0_regnum
+ (num
- 32);
3277 else if (1124 <= num
&& num
< 1124 + 32)
3278 return tdep
->ppc_vr0_regnum
+ (num
- 1124);
3279 else if (1200 <= num
&& num
< 1200 + 32)
3280 return tdep
->ppc_ev0_upper_regnum
+ (num
- 1200);
3285 return tdep
->ppc_cr_regnum
;
3287 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
3289 return tdep
->ppc_acc_regnum
;
3291 return tdep
->ppc_mq_regnum
;
3293 return tdep
->ppc_xer_regnum
;
3295 return tdep
->ppc_lr_regnum
;
3297 return tdep
->ppc_ctr_regnum
;
3299 return tdep
->ppc_vrsave_regnum
;
3301 return tdep
->ppc_spefscr_regnum
;
3304 /* Unknown DWARF register number. */
3308 /* Translate a .eh_frame register to DWARF register, or adjust a
3309 .debug_frame register. */
3312 rs6000_adjust_frame_regnum (struct gdbarch
*gdbarch
, int num
, int eh_frame_p
)
3314 /* GCC releases before 3.4 use GCC internal register numbering in
3315 .debug_frame (and .debug_info, et cetera). The numbering is
3316 different from the standard SysV numbering for everything except
3317 for GPRs and FPRs. We can not detect this problem in most cases
3318 - to get accurate debug info for variables living in lr, ctr, v0,
3319 et cetera, use a newer version of GCC. But we must detect
3320 one important case - lr is in column 65 in .debug_frame output,
3323 GCC 3.4, and the "hammer" branch, have a related problem. They
3324 record lr register saves in .debug_frame as 108, but still record
3325 the return column as 65. We fix that up too.
3327 We can do this because 65 is assigned to fpsr, and GCC never
3328 generates debug info referring to it. To add support for
3329 handwritten debug info that restores fpsr, we would need to add a
3330 producer version check to this. */
3339 /* .eh_frame is GCC specific. For binary compatibility, it uses GCC
3340 internal register numbering; translate that to the standard DWARF2
3341 register numbering. */
3342 if (0 <= num
&& num
<= 63) /* r0-r31,fp0-fp31 */
3344 else if (68 <= num
&& num
<= 75) /* cr0-cr8 */
3345 return num
- 68 + 86;
3346 else if (77 <= num
&& num
<= 108) /* vr0-vr31 */
3347 return num
- 77 + 1124;
3359 case 109: /* vrsave */
3361 case 110: /* vscr */
3363 case 111: /* spe_acc */
3365 case 112: /* spefscr */
3373 /* Handling the various POWER/PowerPC variants. */
3375 /* Information about a particular processor variant. */
3379 /* Name of this variant. */
3382 /* English description of the variant. */
3383 const char *description
;
3385 /* bfd_arch_info.arch corresponding to variant. */
3386 enum bfd_architecture arch
;
3388 /* bfd_arch_info.mach corresponding to variant. */
3391 /* Target description for this variant. */
3392 struct target_desc
**tdesc
;
3395 static struct ppc_variant variants
[] =
3397 {"powerpc", "PowerPC user-level", bfd_arch_powerpc
,
3398 bfd_mach_ppc
, &tdesc_powerpc_altivec32
},
3399 {"power", "POWER user-level", bfd_arch_rs6000
,
3400 bfd_mach_rs6k
, &tdesc_rs6000
},
3401 {"403", "IBM PowerPC 403", bfd_arch_powerpc
,
3402 bfd_mach_ppc_403
, &tdesc_powerpc_403
},
3403 {"405", "IBM PowerPC 405", bfd_arch_powerpc
,
3404 bfd_mach_ppc_405
, &tdesc_powerpc_405
},
3405 {"601", "Motorola PowerPC 601", bfd_arch_powerpc
,
3406 bfd_mach_ppc_601
, &tdesc_powerpc_601
},
3407 {"602", "Motorola PowerPC 602", bfd_arch_powerpc
,
3408 bfd_mach_ppc_602
, &tdesc_powerpc_602
},
3409 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc
,
3410 bfd_mach_ppc_603
, &tdesc_powerpc_603
},
3411 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc
,
3412 604, &tdesc_powerpc_604
},
3413 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc
,
3414 bfd_mach_ppc_403gc
, &tdesc_powerpc_403gc
},
3415 {"505", "Motorola PowerPC 505", bfd_arch_powerpc
,
3416 bfd_mach_ppc_505
, &tdesc_powerpc_505
},
3417 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc
,
3418 bfd_mach_ppc_860
, &tdesc_powerpc_860
},
3419 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc
,
3420 bfd_mach_ppc_750
, &tdesc_powerpc_750
},
3421 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc
,
3422 bfd_mach_ppc_7400
, &tdesc_powerpc_7400
},
3423 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc
,
3424 bfd_mach_ppc_e500
, &tdesc_powerpc_e500
},
3427 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc
,
3428 bfd_mach_ppc64
, &tdesc_powerpc_altivec64
},
3429 {"620", "Motorola PowerPC 620", bfd_arch_powerpc
,
3430 bfd_mach_ppc_620
, &tdesc_powerpc_64
},
3431 {"630", "Motorola PowerPC 630", bfd_arch_powerpc
,
3432 bfd_mach_ppc_630
, &tdesc_powerpc_64
},
3433 {"a35", "PowerPC A35", bfd_arch_powerpc
,
3434 bfd_mach_ppc_a35
, &tdesc_powerpc_64
},
3435 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc
,
3436 bfd_mach_ppc_rs64ii
, &tdesc_powerpc_64
},
3437 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc
,
3438 bfd_mach_ppc_rs64iii
, &tdesc_powerpc_64
},
3440 /* FIXME: I haven't checked the register sets of the following. */
3441 {"rs1", "IBM POWER RS1", bfd_arch_rs6000
,
3442 bfd_mach_rs6k_rs1
, &tdesc_rs6000
},
3443 {"rsc", "IBM POWER RSC", bfd_arch_rs6000
,
3444 bfd_mach_rs6k_rsc
, &tdesc_rs6000
},
3445 {"rs2", "IBM POWER RS2", bfd_arch_rs6000
,
3446 bfd_mach_rs6k_rs2
, &tdesc_rs6000
},
3448 {0, 0, (enum bfd_architecture
) 0, 0, 0}
3451 /* Return the variant corresponding to architecture ARCH and machine number
3452 MACH. If no such variant exists, return null. */
3454 static const struct ppc_variant
*
3455 find_variant_by_arch (enum bfd_architecture arch
, unsigned long mach
)
3457 const struct ppc_variant
*v
;
3459 for (v
= variants
; v
->name
; v
++)
3460 if (arch
== v
->arch
&& mach
== v
->mach
)
3468 struct rs6000_frame_cache
3471 CORE_ADDR initial_sp
;
3472 trad_frame_saved_reg
*saved_regs
;
3474 /* Set BASE_P to true if this frame cache is properly initialized.
3475 Otherwise set to false because some registers or memory cannot
3478 /* Cache PC for building unavailable frame. */
3482 static struct rs6000_frame_cache
*
3483 rs6000_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3485 struct rs6000_frame_cache
*cache
;
3486 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3487 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3488 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3489 struct rs6000_framedata fdata
;
3490 int wordsize
= tdep
->wordsize
;
3491 CORE_ADDR func
= 0, pc
= 0;
3493 if ((*this_cache
) != NULL
)
3494 return (struct rs6000_frame_cache
*) (*this_cache
);
3495 cache
= FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache
);
3496 (*this_cache
) = cache
;
3498 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3502 func
= get_frame_func (this_frame
);
3504 pc
= get_frame_pc (this_frame
);
3505 skip_prologue (gdbarch
, func
, pc
, &fdata
);
3507 /* Figure out the parent's stack pointer. */
3509 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
3510 address of the current frame. Things might be easier if the
3511 ->frame pointed to the outer-most address of the frame. In
3512 the mean time, the address of the prev frame is used as the
3513 base address of this frame. */
3514 cache
->base
= get_frame_register_unsigned
3515 (this_frame
, gdbarch_sp_regnum (gdbarch
));
3517 catch (const gdb_exception_error
&ex
)
3519 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
3521 return (struct rs6000_frame_cache
*) (*this_cache
);
3524 /* If the function appears to be frameless, check a couple of likely
3525 indicators that we have simply failed to find the frame setup.
3526 Two common cases of this are missing symbols (i.e.
3527 get_frame_func returns the wrong address or 0), and assembly
3528 stubs which have a fast exit path but set up a frame on the slow
3531 If the LR appears to return to this function, then presume that
3532 we have an ABI compliant frame that we failed to find. */
3533 if (fdata
.frameless
&& fdata
.lr_offset
== 0)
3538 saved_lr
= get_frame_register_unsigned (this_frame
, tdep
->ppc_lr_regnum
);
3539 if (func
== 0 && saved_lr
== pc
)
3543 CORE_ADDR saved_func
= get_pc_function_start (saved_lr
);
3544 if (func
== saved_func
)
3550 fdata
.frameless
= 0;
3551 fdata
.lr_offset
= tdep
->lr_frame_offset
;
3555 if (!fdata
.frameless
)
3557 /* Frameless really means stackless. */
3560 if (safe_read_memory_unsigned_integer (cache
->base
, wordsize
,
3561 byte_order
, &backchain
))
3562 cache
->base
= (CORE_ADDR
) backchain
;
3565 trad_frame_set_value (cache
->saved_regs
,
3566 gdbarch_sp_regnum (gdbarch
), cache
->base
);
3568 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
3569 All fpr's from saved_fpr to fp31 are saved. */
3571 if (fdata
.saved_fpr
>= 0)
3574 CORE_ADDR fpr_addr
= cache
->base
+ fdata
.fpr_offset
;
3576 /* If skip_prologue says floating-point registers were saved,
3577 but the current architecture has no floating-point registers,
3578 then that's strange. But we have no indices to even record
3579 the addresses under, so we just ignore it. */
3580 if (ppc_floating_point_unit_p (gdbarch
))
3581 for (i
= fdata
.saved_fpr
; i
< ppc_num_fprs
; i
++)
3583 cache
->saved_regs
[tdep
->ppc_fp0_regnum
+ i
].set_addr (fpr_addr
);
3588 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
3589 All gpr's from saved_gpr to gpr31 are saved (except during the
3592 if (fdata
.saved_gpr
>= 0)
3595 CORE_ADDR gpr_addr
= cache
->base
+ fdata
.gpr_offset
;
3596 for (i
= fdata
.saved_gpr
; i
< ppc_num_gprs
; i
++)
3598 if (fdata
.gpr_mask
& (1U << i
))
3599 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].set_addr (gpr_addr
);
3600 gpr_addr
+= wordsize
;
3604 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
3605 All vr's from saved_vr to vr31 are saved. */
3606 if (tdep
->ppc_vr0_regnum
!= -1 && tdep
->ppc_vrsave_regnum
!= -1)
3608 if (fdata
.saved_vr
>= 0)
3611 CORE_ADDR vr_addr
= cache
->base
+ fdata
.vr_offset
;
3612 for (i
= fdata
.saved_vr
; i
< 32; i
++)
3614 cache
->saved_regs
[tdep
->ppc_vr0_regnum
+ i
].set_addr (vr_addr
);
3615 vr_addr
+= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
3620 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
3621 All vr's from saved_ev to ev31 are saved. ????? */
3622 if (tdep
->ppc_ev0_regnum
!= -1)
3624 if (fdata
.saved_ev
>= 0)
3627 CORE_ADDR ev_addr
= cache
->base
+ fdata
.ev_offset
;
3628 CORE_ADDR off
= (byte_order
== BFD_ENDIAN_BIG
? 4 : 0);
3630 for (i
= fdata
.saved_ev
; i
< ppc_num_gprs
; i
++)
3632 cache
->saved_regs
[tdep
->ppc_ev0_regnum
+ i
].set_addr (ev_addr
);
3633 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].set_addr (ev_addr
3635 ev_addr
+= register_size (gdbarch
, tdep
->ppc_ev0_regnum
);
3640 /* If != 0, fdata.cr_offset is the offset from the frame that
3642 if (fdata
.cr_offset
!= 0)
3643 cache
->saved_regs
[tdep
->ppc_cr_regnum
].set_addr (cache
->base
3646 /* If != 0, fdata.lr_offset is the offset from the frame that
3648 if (fdata
.lr_offset
!= 0)
3649 cache
->saved_regs
[tdep
->ppc_lr_regnum
].set_addr (cache
->base
3651 else if (fdata
.lr_register
!= -1)
3652 cache
->saved_regs
[tdep
->ppc_lr_regnum
].set_realreg (fdata
.lr_register
);
3653 /* The PC is found in the link register. */
3654 cache
->saved_regs
[gdbarch_pc_regnum (gdbarch
)] =
3655 cache
->saved_regs
[tdep
->ppc_lr_regnum
];
3657 /* If != 0, fdata.vrsave_offset is the offset from the frame that
3658 holds the VRSAVE. */
3659 if (fdata
.vrsave_offset
!= 0)
3660 cache
->saved_regs
[tdep
->ppc_vrsave_regnum
].set_addr (cache
->base
3661 + fdata
.vrsave_offset
);
3663 if (fdata
.alloca_reg
< 0)
3664 /* If no alloca register used, then fi->frame is the value of the
3665 %sp for this frame, and it is good enough. */
3667 = get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
3670 = get_frame_register_unsigned (this_frame
, fdata
.alloca_reg
);
3677 rs6000_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3678 struct frame_id
*this_id
)
3680 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3685 (*this_id
) = frame_id_build_unavailable_stack (info
->pc
);
3689 /* This marks the outermost frame. */
3690 if (info
->base
== 0)
3693 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3696 static struct value
*
3697 rs6000_frame_prev_register (struct frame_info
*this_frame
,
3698 void **this_cache
, int regnum
)
3700 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3702 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3705 static const struct frame_unwind rs6000_frame_unwind
=
3708 default_frame_unwind_stop_reason
,
3709 rs6000_frame_this_id
,
3710 rs6000_frame_prev_register
,
3712 default_frame_sniffer
3715 /* Allocate and initialize a frame cache for an epilogue frame.
3716 SP is restored and prev-PC is stored in LR. */
3718 static struct rs6000_frame_cache
*
3719 rs6000_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3721 struct rs6000_frame_cache
*cache
;
3722 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3723 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3726 return (struct rs6000_frame_cache
*) *this_cache
;
3728 cache
= FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache
);
3729 (*this_cache
) = cache
;
3730 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3734 /* At this point the stack looks as if we just entered the
3735 function, and the return address is stored in LR. */
3738 sp
= get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
3739 lr
= get_frame_register_unsigned (this_frame
, tdep
->ppc_lr_regnum
);
3742 cache
->initial_sp
= sp
;
3744 trad_frame_set_value (cache
->saved_regs
,
3745 gdbarch_pc_regnum (gdbarch
), lr
);
3747 catch (const gdb_exception_error
&ex
)
3749 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
3756 /* Implementation of frame_unwind.this_id, as defined in frame_unwind.h.
3757 Return the frame ID of an epilogue frame. */
3760 rs6000_epilogue_frame_this_id (struct frame_info
*this_frame
,
3761 void **this_cache
, struct frame_id
*this_id
)
3764 struct rs6000_frame_cache
*info
=
3765 rs6000_epilogue_frame_cache (this_frame
, this_cache
);
3767 pc
= get_frame_func (this_frame
);
3768 if (info
->base
== 0)
3769 (*this_id
) = frame_id_build_unavailable_stack (pc
);
3771 (*this_id
) = frame_id_build (info
->base
, pc
);
3774 /* Implementation of frame_unwind.prev_register, as defined in frame_unwind.h.
3775 Return the register value of REGNUM in previous frame. */
3777 static struct value
*
3778 rs6000_epilogue_frame_prev_register (struct frame_info
*this_frame
,
3779 void **this_cache
, int regnum
)
3781 struct rs6000_frame_cache
*info
=
3782 rs6000_epilogue_frame_cache (this_frame
, this_cache
);
3783 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3786 /* Implementation of frame_unwind.sniffer, as defined in frame_unwind.h.
3787 Check whether this an epilogue frame. */
3790 rs6000_epilogue_frame_sniffer (const struct frame_unwind
*self
,
3791 struct frame_info
*this_frame
,
3792 void **this_prologue_cache
)
3794 if (frame_relative_level (this_frame
) == 0)
3795 return rs6000_in_function_epilogue_frame_p (this_frame
,
3796 get_frame_arch (this_frame
),
3797 get_frame_pc (this_frame
));
3802 /* Frame unwinder for epilogue frame. This is required for reverse step-over
3803 a function without debug information. */
3805 static const struct frame_unwind rs6000_epilogue_frame_unwind
=
3808 default_frame_unwind_stop_reason
,
3809 rs6000_epilogue_frame_this_id
, rs6000_epilogue_frame_prev_register
,
3811 rs6000_epilogue_frame_sniffer
3816 rs6000_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
3818 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3820 return info
->initial_sp
;
3823 static const struct frame_base rs6000_frame_base
= {
3824 &rs6000_frame_unwind
,
3825 rs6000_frame_base_address
,
3826 rs6000_frame_base_address
,
3827 rs6000_frame_base_address
3830 static const struct frame_base
*
3831 rs6000_frame_base_sniffer (struct frame_info
*this_frame
)
3833 return &rs6000_frame_base
;
3836 /* DWARF-2 frame support. Used to handle the detection of
3837 clobbered registers during function calls. */
3840 ppc_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
3841 struct dwarf2_frame_state_reg
*reg
,
3842 struct frame_info
*this_frame
)
3844 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3846 /* PPC32 and PPC64 ABI's are the same regarding volatile and
3847 non-volatile registers. We will use the same code for both. */
3849 /* Call-saved GP registers. */
3850 if ((regnum
>= tdep
->ppc_gp0_regnum
+ 14
3851 && regnum
<= tdep
->ppc_gp0_regnum
+ 31)
3852 || (regnum
== tdep
->ppc_gp0_regnum
+ 1))
3853 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3855 /* Call-clobbered GP registers. */
3856 if ((regnum
>= tdep
->ppc_gp0_regnum
+ 3
3857 && regnum
<= tdep
->ppc_gp0_regnum
+ 12)
3858 || (regnum
== tdep
->ppc_gp0_regnum
))
3859 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3861 /* Deal with FP registers, if supported. */
3862 if (tdep
->ppc_fp0_regnum
>= 0)
3864 /* Call-saved FP registers. */
3865 if ((regnum
>= tdep
->ppc_fp0_regnum
+ 14
3866 && regnum
<= tdep
->ppc_fp0_regnum
+ 31))
3867 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3869 /* Call-clobbered FP registers. */
3870 if ((regnum
>= tdep
->ppc_fp0_regnum
3871 && regnum
<= tdep
->ppc_fp0_regnum
+ 13))
3872 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3875 /* Deal with ALTIVEC registers, if supported. */
3876 if (tdep
->ppc_vr0_regnum
> 0 && tdep
->ppc_vrsave_regnum
> 0)
3878 /* Call-saved Altivec registers. */
3879 if ((regnum
>= tdep
->ppc_vr0_regnum
+ 20
3880 && regnum
<= tdep
->ppc_vr0_regnum
+ 31)
3881 || regnum
== tdep
->ppc_vrsave_regnum
)
3882 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3884 /* Call-clobbered Altivec registers. */
3885 if ((regnum
>= tdep
->ppc_vr0_regnum
3886 && regnum
<= tdep
->ppc_vr0_regnum
+ 19))
3887 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3890 /* Handle PC register and Stack Pointer correctly. */
3891 if (regnum
== gdbarch_pc_regnum (gdbarch
))
3892 reg
->how
= DWARF2_FRAME_REG_RA
;
3893 else if (regnum
== gdbarch_sp_regnum (gdbarch
))
3894 reg
->how
= DWARF2_FRAME_REG_CFA
;
3898 /* Return true if a .gnu_attributes section exists in BFD and it
3899 indicates we are using SPE extensions OR if a .PPC.EMB.apuinfo
3900 section exists in BFD and it indicates that SPE extensions are in
3901 use. Check the .gnu.attributes section first, as the binary might be
3902 compiled for SPE, but not actually using SPE instructions. */
3905 bfd_uses_spe_extensions (bfd
*abfd
)
3908 gdb_byte
*contents
= NULL
;
3917 /* Using Tag_GNU_Power_ABI_Vector here is a bit of a hack, as the user
3918 could be using the SPE vector abi without actually using any spe
3919 bits whatsoever. But it's close enough for now. */
3920 int vector_abi
= bfd_elf_get_obj_attr_int (abfd
, OBJ_ATTR_GNU
,
3921 Tag_GNU_Power_ABI_Vector
);
3922 if (vector_abi
== 3)
3926 sect
= bfd_get_section_by_name (abfd
, ".PPC.EMB.apuinfo");
3930 size
= bfd_section_size (sect
);
3931 contents
= (gdb_byte
*) xmalloc (size
);
3932 if (!bfd_get_section_contents (abfd
, sect
, contents
, 0, size
))
3938 /* Parse the .PPC.EMB.apuinfo section. The layout is as follows:
3944 char name[name_len rounded up to 4-byte alignment];
3945 char data[data_len];
3948 Technically, there's only supposed to be one such structure in a
3949 given apuinfo section, but the linker is not always vigilant about
3950 merging apuinfo sections from input files. Just go ahead and parse
3951 them all, exiting early when we discover the binary uses SPE
3954 It's not specified in what endianness the information in this
3955 section is stored. Assume that it's the endianness of the BFD. */
3959 unsigned int name_len
;
3960 unsigned int data_len
;
3963 /* If we can't read the first three fields, we're done. */
3967 name_len
= bfd_get_32 (abfd
, ptr
);
3968 name_len
= (name_len
+ 3) & ~3U; /* Round to 4 bytes. */
3969 data_len
= bfd_get_32 (abfd
, ptr
+ 4);
3970 type
= bfd_get_32 (abfd
, ptr
+ 8);
3973 /* The name must be "APUinfo\0". */
3975 && strcmp ((const char *) ptr
, "APUinfo") != 0)
3979 /* The type must be 2. */
3983 /* The data is stored as a series of uint32. The upper half of
3984 each uint32 indicates the particular APU used and the lower
3985 half indicates the revision of that APU. We just care about
3988 /* Not 4-byte quantities. */
3994 unsigned int apuinfo
= bfd_get_32 (abfd
, ptr
);
3995 unsigned int apu
= apuinfo
>> 16;
3999 /* The SPE APU is 0x100; the SPEFP APU is 0x101. Accept
4001 if (apu
== 0x100 || apu
== 0x101)
4016 /* These are macros for parsing instruction fields (I.1.6.28) */
4018 #define PPC_FIELD(value, from, len) \
4019 (((value) >> (32 - (from) - (len))) & ((1 << (len)) - 1))
4020 #define PPC_SEXT(v, bs) \
4021 ((((CORE_ADDR) (v) & (((CORE_ADDR) 1 << (bs)) - 1)) \
4022 ^ ((CORE_ADDR) 1 << ((bs) - 1))) \
4023 - ((CORE_ADDR) 1 << ((bs) - 1)))
4024 #define PPC_OP6(insn) PPC_FIELD (insn, 0, 6)
4025 #define PPC_EXTOP(insn) PPC_FIELD (insn, 21, 10)
4026 #define PPC_RT(insn) PPC_FIELD (insn, 6, 5)
4027 #define PPC_RS(insn) PPC_FIELD (insn, 6, 5)
4028 #define PPC_RA(insn) PPC_FIELD (insn, 11, 5)
4029 #define PPC_RB(insn) PPC_FIELD (insn, 16, 5)
4030 #define PPC_NB(insn) PPC_FIELD (insn, 16, 5)
4031 #define PPC_VRT(insn) PPC_FIELD (insn, 6, 5)
4032 #define PPC_FRT(insn) PPC_FIELD (insn, 6, 5)
4033 #define PPC_SPR(insn) (PPC_FIELD (insn, 11, 5) \
4034 | (PPC_FIELD (insn, 16, 5) << 5))
4035 #define PPC_BO(insn) PPC_FIELD (insn, 6, 5)
4036 #define PPC_T(insn) PPC_FIELD (insn, 6, 5)
4037 #define PPC_D(insn) PPC_SEXT (PPC_FIELD (insn, 16, 16), 16)
4038 #define PPC_DS(insn) PPC_SEXT (PPC_FIELD (insn, 16, 14), 14)
4039 #define PPC_DQ(insn) PPC_SEXT (PPC_FIELD (insn, 16, 12), 12)
4040 #define PPC_BIT(insn,n) ((insn & (1 << (31 - (n)))) ? 1 : 0)
4041 #define PPC_OE(insn) PPC_BIT (insn, 21)
4042 #define PPC_RC(insn) PPC_BIT (insn, 31)
4043 #define PPC_Rc(insn) PPC_BIT (insn, 21)
4044 #define PPC_LK(insn) PPC_BIT (insn, 31)
4045 #define PPC_TX(insn) PPC_BIT (insn, 31)
4046 #define PPC_LEV(insn) PPC_FIELD (insn, 20, 7)
4048 #define PPC_XT(insn) ((PPC_TX (insn) << 5) | PPC_T (insn))
4049 #define PPC_XER_NB(xer) (xer & 0x7f)
4051 /* Record Vector-Scalar Registers.
4052 For VSR less than 32, it's represented by an FPR and an VSR-upper register.
4053 Otherwise, it's just a VR register. Record them accordingly. */
4056 ppc_record_vsr (struct regcache
*regcache
, struct gdbarch_tdep
*tdep
, int vsr
)
4058 if (vsr
< 0 || vsr
>= 64)
4063 if (tdep
->ppc_vr0_regnum
>= 0)
4064 record_full_arch_list_add_reg (regcache
, tdep
->ppc_vr0_regnum
+ vsr
- 32);
4068 if (tdep
->ppc_fp0_regnum
>= 0)
4069 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fp0_regnum
+ vsr
);
4070 if (tdep
->ppc_vsr0_upper_regnum
>= 0)
4071 record_full_arch_list_add_reg (regcache
,
4072 tdep
->ppc_vsr0_upper_regnum
+ vsr
);
4078 /* Parse and record instructions primary opcode-4 at ADDR.
4079 Return 0 if successful. */
4082 ppc_process_record_op4 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4083 CORE_ADDR addr
, uint32_t insn
)
4085 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4086 int ext
= PPC_FIELD (insn
, 21, 11);
4087 int vra
= PPC_FIELD (insn
, 11, 5);
4091 case 32: /* Vector Multiply-High-Add Signed Halfword Saturate */
4092 case 33: /* Vector Multiply-High-Round-Add Signed Halfword Saturate */
4093 case 39: /* Vector Multiply-Sum Unsigned Halfword Saturate */
4094 case 41: /* Vector Multiply-Sum Signed Halfword Saturate */
4095 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
4097 case 42: /* Vector Select */
4098 case 43: /* Vector Permute */
4099 case 59: /* Vector Permute Right-indexed */
4100 case 44: /* Vector Shift Left Double by Octet Immediate */
4101 case 45: /* Vector Permute and Exclusive-OR */
4102 case 60: /* Vector Add Extended Unsigned Quadword Modulo */
4103 case 61: /* Vector Add Extended & write Carry Unsigned Quadword */
4104 case 62: /* Vector Subtract Extended Unsigned Quadword Modulo */
4105 case 63: /* Vector Subtract Extended & write Carry Unsigned Quadword */
4106 case 34: /* Vector Multiply-Low-Add Unsigned Halfword Modulo */
4107 case 35: /* Vector Multiply-Sum Unsigned Doubleword Modulo */
4108 case 36: /* Vector Multiply-Sum Unsigned Byte Modulo */
4109 case 37: /* Vector Multiply-Sum Mixed Byte Modulo */
4110 case 38: /* Vector Multiply-Sum Unsigned Halfword Modulo */
4111 case 40: /* Vector Multiply-Sum Signed Halfword Modulo */
4112 case 46: /* Vector Multiply-Add Single-Precision */
4113 case 47: /* Vector Negative Multiply-Subtract Single-Precision */
4114 record_full_arch_list_add_reg (regcache
,
4115 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4118 case 48: /* Multiply-Add High Doubleword */
4119 case 49: /* Multiply-Add High Doubleword Unsigned */
4120 case 51: /* Multiply-Add Low Doubleword */
4121 record_full_arch_list_add_reg (regcache
,
4122 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4126 switch ((ext
& 0x1ff))
4129 if (vra
!= 0 /* Decimal Convert To Signed Quadword */
4130 && vra
!= 2 /* Decimal Convert From Signed Quadword */
4131 && vra
!= 4 /* Decimal Convert To Zoned */
4132 && vra
!= 5 /* Decimal Convert To National */
4133 && vra
!= 6 /* Decimal Convert From Zoned */
4134 && vra
!= 7 /* Decimal Convert From National */
4135 && vra
!= 31) /* Decimal Set Sign */
4138 /* 5.16 Decimal Integer Arithmetic Instructions */
4139 case 1: /* Decimal Add Modulo */
4140 case 65: /* Decimal Subtract Modulo */
4142 case 193: /* Decimal Shift */
4143 case 129: /* Decimal Unsigned Shift */
4144 case 449: /* Decimal Shift and Round */
4146 case 257: /* Decimal Truncate */
4147 case 321: /* Decimal Unsigned Truncate */
4149 /* Bit-21 should be set. */
4150 if (!PPC_BIT (insn
, 21))
4153 record_full_arch_list_add_reg (regcache
,
4154 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4155 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4159 /* Bit-21 is used for RC */
4160 switch (ext
& 0x3ff)
4162 case 6: /* Vector Compare Equal To Unsigned Byte */
4163 case 70: /* Vector Compare Equal To Unsigned Halfword */
4164 case 134: /* Vector Compare Equal To Unsigned Word */
4165 case 199: /* Vector Compare Equal To Unsigned Doubleword */
4166 case 774: /* Vector Compare Greater Than Signed Byte */
4167 case 838: /* Vector Compare Greater Than Signed Halfword */
4168 case 902: /* Vector Compare Greater Than Signed Word */
4169 case 967: /* Vector Compare Greater Than Signed Doubleword */
4170 case 518: /* Vector Compare Greater Than Unsigned Byte */
4171 case 646: /* Vector Compare Greater Than Unsigned Word */
4172 case 582: /* Vector Compare Greater Than Unsigned Halfword */
4173 case 711: /* Vector Compare Greater Than Unsigned Doubleword */
4174 case 966: /* Vector Compare Bounds Single-Precision */
4175 case 198: /* Vector Compare Equal To Single-Precision */
4176 case 454: /* Vector Compare Greater Than or Equal To Single-Precision */
4177 case 710: /* Vector Compare Greater Than Single-Precision */
4178 case 7: /* Vector Compare Not Equal Byte */
4179 case 71: /* Vector Compare Not Equal Halfword */
4180 case 135: /* Vector Compare Not Equal Word */
4181 case 263: /* Vector Compare Not Equal or Zero Byte */
4182 case 327: /* Vector Compare Not Equal or Zero Halfword */
4183 case 391: /* Vector Compare Not Equal or Zero Word */
4185 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4186 record_full_arch_list_add_reg (regcache
,
4187 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4195 case 0: /* Vector Count Leading Zero Least-Significant Bits
4197 case 1: /* Vector Count Trailing Zero Least-Significant Bits
4199 record_full_arch_list_add_reg (regcache
,
4200 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4203 case 6: /* Vector Negate Word */
4204 case 7: /* Vector Negate Doubleword */
4205 case 8: /* Vector Parity Byte Word */
4206 case 9: /* Vector Parity Byte Doubleword */
4207 case 10: /* Vector Parity Byte Quadword */
4208 case 16: /* Vector Extend Sign Byte To Word */
4209 case 17: /* Vector Extend Sign Halfword To Word */
4210 case 24: /* Vector Extend Sign Byte To Doubleword */
4211 case 25: /* Vector Extend Sign Halfword To Doubleword */
4212 case 26: /* Vector Extend Sign Word To Doubleword */
4213 case 28: /* Vector Count Trailing Zeros Byte */
4214 case 29: /* Vector Count Trailing Zeros Halfword */
4215 case 30: /* Vector Count Trailing Zeros Word */
4216 case 31: /* Vector Count Trailing Zeros Doubleword */
4217 record_full_arch_list_add_reg (regcache
,
4218 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4225 case 142: /* Vector Pack Unsigned Halfword Unsigned Saturate */
4226 case 206: /* Vector Pack Unsigned Word Unsigned Saturate */
4227 case 270: /* Vector Pack Signed Halfword Unsigned Saturate */
4228 case 334: /* Vector Pack Signed Word Unsigned Saturate */
4229 case 398: /* Vector Pack Signed Halfword Signed Saturate */
4230 case 462: /* Vector Pack Signed Word Signed Saturate */
4231 case 1230: /* Vector Pack Unsigned Doubleword Unsigned Saturate */
4232 case 1358: /* Vector Pack Signed Doubleword Unsigned Saturate */
4233 case 1486: /* Vector Pack Signed Doubleword Signed Saturate */
4234 case 512: /* Vector Add Unsigned Byte Saturate */
4235 case 576: /* Vector Add Unsigned Halfword Saturate */
4236 case 640: /* Vector Add Unsigned Word Saturate */
4237 case 768: /* Vector Add Signed Byte Saturate */
4238 case 832: /* Vector Add Signed Halfword Saturate */
4239 case 896: /* Vector Add Signed Word Saturate */
4240 case 1536: /* Vector Subtract Unsigned Byte Saturate */
4241 case 1600: /* Vector Subtract Unsigned Halfword Saturate */
4242 case 1664: /* Vector Subtract Unsigned Word Saturate */
4243 case 1792: /* Vector Subtract Signed Byte Saturate */
4244 case 1856: /* Vector Subtract Signed Halfword Saturate */
4245 case 1920: /* Vector Subtract Signed Word Saturate */
4247 case 1544: /* Vector Sum across Quarter Unsigned Byte Saturate */
4248 case 1800: /* Vector Sum across Quarter Signed Byte Saturate */
4249 case 1608: /* Vector Sum across Quarter Signed Halfword Saturate */
4250 case 1672: /* Vector Sum across Half Signed Word Saturate */
4251 case 1928: /* Vector Sum across Signed Word Saturate */
4252 case 970: /* Vector Convert To Signed Fixed-Point Word Saturate */
4253 case 906: /* Vector Convert To Unsigned Fixed-Point Word Saturate */
4254 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
4256 case 12: /* Vector Merge High Byte */
4257 case 14: /* Vector Pack Unsigned Halfword Unsigned Modulo */
4258 case 76: /* Vector Merge High Halfword */
4259 case 78: /* Vector Pack Unsigned Word Unsigned Modulo */
4260 case 140: /* Vector Merge High Word */
4261 case 268: /* Vector Merge Low Byte */
4262 case 332: /* Vector Merge Low Halfword */
4263 case 396: /* Vector Merge Low Word */
4264 case 526: /* Vector Unpack High Signed Byte */
4265 case 590: /* Vector Unpack High Signed Halfword */
4266 case 654: /* Vector Unpack Low Signed Byte */
4267 case 718: /* Vector Unpack Low Signed Halfword */
4268 case 782: /* Vector Pack Pixel */
4269 case 846: /* Vector Unpack High Pixel */
4270 case 974: /* Vector Unpack Low Pixel */
4271 case 1102: /* Vector Pack Unsigned Doubleword Unsigned Modulo */
4272 case 1614: /* Vector Unpack High Signed Word */
4273 case 1676: /* Vector Merge Odd Word */
4274 case 1742: /* Vector Unpack Low Signed Word */
4275 case 1932: /* Vector Merge Even Word */
4276 case 524: /* Vector Splat Byte */
4277 case 588: /* Vector Splat Halfword */
4278 case 652: /* Vector Splat Word */
4279 case 780: /* Vector Splat Immediate Signed Byte */
4280 case 844: /* Vector Splat Immediate Signed Halfword */
4281 case 908: /* Vector Splat Immediate Signed Word */
4282 case 452: /* Vector Shift Left */
4283 case 708: /* Vector Shift Right */
4284 case 1036: /* Vector Shift Left by Octet */
4285 case 1100: /* Vector Shift Right by Octet */
4286 case 0: /* Vector Add Unsigned Byte Modulo */
4287 case 64: /* Vector Add Unsigned Halfword Modulo */
4288 case 128: /* Vector Add Unsigned Word Modulo */
4289 case 192: /* Vector Add Unsigned Doubleword Modulo */
4290 case 256: /* Vector Add Unsigned Quadword Modulo */
4291 case 320: /* Vector Add & write Carry Unsigned Quadword */
4292 case 384: /* Vector Add and Write Carry-Out Unsigned Word */
4293 case 8: /* Vector Multiply Odd Unsigned Byte */
4294 case 72: /* Vector Multiply Odd Unsigned Halfword */
4295 case 136: /* Vector Multiply Odd Unsigned Word */
4296 case 264: /* Vector Multiply Odd Signed Byte */
4297 case 328: /* Vector Multiply Odd Signed Halfword */
4298 case 392: /* Vector Multiply Odd Signed Word */
4299 case 520: /* Vector Multiply Even Unsigned Byte */
4300 case 584: /* Vector Multiply Even Unsigned Halfword */
4301 case 648: /* Vector Multiply Even Unsigned Word */
4302 case 776: /* Vector Multiply Even Signed Byte */
4303 case 840: /* Vector Multiply Even Signed Halfword */
4304 case 904: /* Vector Multiply Even Signed Word */
4305 case 137: /* Vector Multiply Unsigned Word Modulo */
4306 case 1024: /* Vector Subtract Unsigned Byte Modulo */
4307 case 1088: /* Vector Subtract Unsigned Halfword Modulo */
4308 case 1152: /* Vector Subtract Unsigned Word Modulo */
4309 case 1216: /* Vector Subtract Unsigned Doubleword Modulo */
4310 case 1280: /* Vector Subtract Unsigned Quadword Modulo */
4311 case 1344: /* Vector Subtract & write Carry Unsigned Quadword */
4312 case 1408: /* Vector Subtract and Write Carry-Out Unsigned Word */
4313 case 1282: /* Vector Average Signed Byte */
4314 case 1346: /* Vector Average Signed Halfword */
4315 case 1410: /* Vector Average Signed Word */
4316 case 1026: /* Vector Average Unsigned Byte */
4317 case 1090: /* Vector Average Unsigned Halfword */
4318 case 1154: /* Vector Average Unsigned Word */
4319 case 258: /* Vector Maximum Signed Byte */
4320 case 322: /* Vector Maximum Signed Halfword */
4321 case 386: /* Vector Maximum Signed Word */
4322 case 450: /* Vector Maximum Signed Doubleword */
4323 case 2: /* Vector Maximum Unsigned Byte */
4324 case 66: /* Vector Maximum Unsigned Halfword */
4325 case 130: /* Vector Maximum Unsigned Word */
4326 case 194: /* Vector Maximum Unsigned Doubleword */
4327 case 770: /* Vector Minimum Signed Byte */
4328 case 834: /* Vector Minimum Signed Halfword */
4329 case 898: /* Vector Minimum Signed Word */
4330 case 962: /* Vector Minimum Signed Doubleword */
4331 case 514: /* Vector Minimum Unsigned Byte */
4332 case 578: /* Vector Minimum Unsigned Halfword */
4333 case 642: /* Vector Minimum Unsigned Word */
4334 case 706: /* Vector Minimum Unsigned Doubleword */
4335 case 1028: /* Vector Logical AND */
4336 case 1668: /* Vector Logical Equivalent */
4337 case 1092: /* Vector Logical AND with Complement */
4338 case 1412: /* Vector Logical NAND */
4339 case 1348: /* Vector Logical OR with Complement */
4340 case 1156: /* Vector Logical OR */
4341 case 1284: /* Vector Logical NOR */
4342 case 1220: /* Vector Logical XOR */
4343 case 4: /* Vector Rotate Left Byte */
4344 case 132: /* Vector Rotate Left Word VX-form */
4345 case 68: /* Vector Rotate Left Halfword */
4346 case 196: /* Vector Rotate Left Doubleword */
4347 case 260: /* Vector Shift Left Byte */
4348 case 388: /* Vector Shift Left Word */
4349 case 324: /* Vector Shift Left Halfword */
4350 case 1476: /* Vector Shift Left Doubleword */
4351 case 516: /* Vector Shift Right Byte */
4352 case 644: /* Vector Shift Right Word */
4353 case 580: /* Vector Shift Right Halfword */
4354 case 1732: /* Vector Shift Right Doubleword */
4355 case 772: /* Vector Shift Right Algebraic Byte */
4356 case 900: /* Vector Shift Right Algebraic Word */
4357 case 836: /* Vector Shift Right Algebraic Halfword */
4358 case 964: /* Vector Shift Right Algebraic Doubleword */
4359 case 10: /* Vector Add Single-Precision */
4360 case 74: /* Vector Subtract Single-Precision */
4361 case 1034: /* Vector Maximum Single-Precision */
4362 case 1098: /* Vector Minimum Single-Precision */
4363 case 842: /* Vector Convert From Signed Fixed-Point Word */
4364 case 778: /* Vector Convert From Unsigned Fixed-Point Word */
4365 case 714: /* Vector Round to Single-Precision Integer toward -Infinity */
4366 case 522: /* Vector Round to Single-Precision Integer Nearest */
4367 case 650: /* Vector Round to Single-Precision Integer toward +Infinity */
4368 case 586: /* Vector Round to Single-Precision Integer toward Zero */
4369 case 394: /* Vector 2 Raised to the Exponent Estimate Floating-Point */
4370 case 458: /* Vector Log Base 2 Estimate Floating-Point */
4371 case 266: /* Vector Reciprocal Estimate Single-Precision */
4372 case 330: /* Vector Reciprocal Square Root Estimate Single-Precision */
4373 case 1288: /* Vector AES Cipher */
4374 case 1289: /* Vector AES Cipher Last */
4375 case 1352: /* Vector AES Inverse Cipher */
4376 case 1353: /* Vector AES Inverse Cipher Last */
4377 case 1480: /* Vector AES SubBytes */
4378 case 1730: /* Vector SHA-512 Sigma Doubleword */
4379 case 1666: /* Vector SHA-256 Sigma Word */
4380 case 1032: /* Vector Polynomial Multiply-Sum Byte */
4381 case 1160: /* Vector Polynomial Multiply-Sum Word */
4382 case 1096: /* Vector Polynomial Multiply-Sum Halfword */
4383 case 1224: /* Vector Polynomial Multiply-Sum Doubleword */
4384 case 1292: /* Vector Gather Bits by Bytes by Doubleword */
4385 case 1794: /* Vector Count Leading Zeros Byte */
4386 case 1858: /* Vector Count Leading Zeros Halfword */
4387 case 1922: /* Vector Count Leading Zeros Word */
4388 case 1986: /* Vector Count Leading Zeros Doubleword */
4389 case 1795: /* Vector Population Count Byte */
4390 case 1859: /* Vector Population Count Halfword */
4391 case 1923: /* Vector Population Count Word */
4392 case 1987: /* Vector Population Count Doubleword */
4393 case 1356: /* Vector Bit Permute Quadword */
4394 case 1484: /* Vector Bit Permute Doubleword */
4395 case 513: /* Vector Multiply-by-10 Unsigned Quadword */
4396 case 1: /* Vector Multiply-by-10 & write Carry Unsigned
4398 case 577: /* Vector Multiply-by-10 Extended Unsigned Quadword */
4399 case 65: /* Vector Multiply-by-10 Extended & write Carry
4400 Unsigned Quadword */
4401 case 1027: /* Vector Absolute Difference Unsigned Byte */
4402 case 1091: /* Vector Absolute Difference Unsigned Halfword */
4403 case 1155: /* Vector Absolute Difference Unsigned Word */
4404 case 1796: /* Vector Shift Right Variable */
4405 case 1860: /* Vector Shift Left Variable */
4406 case 133: /* Vector Rotate Left Word then Mask Insert */
4407 case 197: /* Vector Rotate Left Doubleword then Mask Insert */
4408 case 389: /* Vector Rotate Left Word then AND with Mask */
4409 case 453: /* Vector Rotate Left Doubleword then AND with Mask */
4410 case 525: /* Vector Extract Unsigned Byte */
4411 case 589: /* Vector Extract Unsigned Halfword */
4412 case 653: /* Vector Extract Unsigned Word */
4413 case 717: /* Vector Extract Doubleword */
4414 case 781: /* Vector Insert Byte */
4415 case 845: /* Vector Insert Halfword */
4416 case 909: /* Vector Insert Word */
4417 case 973: /* Vector Insert Doubleword */
4418 record_full_arch_list_add_reg (regcache
,
4419 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4422 case 1549: /* Vector Extract Unsigned Byte Left-Indexed */
4423 case 1613: /* Vector Extract Unsigned Halfword Left-Indexed */
4424 case 1677: /* Vector Extract Unsigned Word Left-Indexed */
4425 case 1805: /* Vector Extract Unsigned Byte Right-Indexed */
4426 case 1869: /* Vector Extract Unsigned Halfword Right-Indexed */
4427 case 1933: /* Vector Extract Unsigned Word Right-Indexed */
4428 record_full_arch_list_add_reg (regcache
,
4429 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4432 case 1604: /* Move To Vector Status and Control Register */
4433 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
4435 case 1540: /* Move From Vector Status and Control Register */
4436 record_full_arch_list_add_reg (regcache
,
4437 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4439 case 833: /* Decimal Copy Sign */
4440 record_full_arch_list_add_reg (regcache
,
4441 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4442 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4446 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4447 "at %s, 4-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4451 /* Parse and record instructions of primary opcode-19 at ADDR.
4452 Return 0 if successful. */
4455 ppc_process_record_op19 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4456 CORE_ADDR addr
, uint32_t insn
)
4458 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4459 int ext
= PPC_EXTOP (insn
);
4461 switch (ext
& 0x01f)
4463 case 2: /* Add PC Immediate Shifted */
4464 record_full_arch_list_add_reg (regcache
,
4465 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4471 case 0: /* Move Condition Register Field */
4472 case 33: /* Condition Register NOR */
4473 case 129: /* Condition Register AND with Complement */
4474 case 193: /* Condition Register XOR */
4475 case 225: /* Condition Register NAND */
4476 case 257: /* Condition Register AND */
4477 case 289: /* Condition Register Equivalent */
4478 case 417: /* Condition Register OR with Complement */
4479 case 449: /* Condition Register OR */
4480 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4483 case 16: /* Branch Conditional */
4484 case 560: /* Branch Conditional to Branch Target Address Register */
4485 if ((PPC_BO (insn
) & 0x4) == 0)
4486 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
4488 case 528: /* Branch Conditional to Count Register */
4490 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
4493 case 150: /* Instruction Synchronize */
4498 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4499 "at %s, 19-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4503 /* Parse and record instructions of primary opcode-31 at ADDR.
4504 Return 0 if successful. */
4507 ppc_process_record_op31 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4508 CORE_ADDR addr
, uint32_t insn
)
4510 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4511 int ext
= PPC_EXTOP (insn
);
4513 CORE_ADDR at_dcsz
, ea
= 0;
4514 ULONGEST rb
, ra
, xer
;
4517 /* These instructions have OE bit. */
4518 switch (ext
& 0x1ff)
4520 /* These write RT and XER. Update CR if RC is set. */
4521 case 8: /* Subtract from carrying */
4522 case 10: /* Add carrying */
4523 case 136: /* Subtract from extended */
4524 case 138: /* Add extended */
4525 case 200: /* Subtract from zero extended */
4526 case 202: /* Add to zero extended */
4527 case 232: /* Subtract from minus one extended */
4528 case 234: /* Add to minus one extended */
4529 /* CA is always altered, but SO/OV are only altered when OE=1.
4530 In any case, XER is always altered. */
4531 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4533 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4534 record_full_arch_list_add_reg (regcache
,
4535 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4538 /* These write RT. Update CR if RC is set and update XER if OE is set. */
4539 case 40: /* Subtract from */
4540 case 104: /* Negate */
4541 case 233: /* Multiply low doubleword */
4542 case 235: /* Multiply low word */
4544 case 393: /* Divide Doubleword Extended Unsigned */
4545 case 395: /* Divide Word Extended Unsigned */
4546 case 425: /* Divide Doubleword Extended */
4547 case 427: /* Divide Word Extended */
4548 case 457: /* Divide Doubleword Unsigned */
4549 case 459: /* Divide Word Unsigned */
4550 case 489: /* Divide Doubleword */
4551 case 491: /* Divide Word */
4553 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4555 case 9: /* Multiply High Doubleword Unsigned */
4556 case 11: /* Multiply High Word Unsigned */
4557 case 73: /* Multiply High Doubleword */
4558 case 75: /* Multiply High Word */
4560 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4561 record_full_arch_list_add_reg (regcache
,
4562 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4566 if ((ext
& 0x1f) == 15)
4568 /* Integer Select. bit[16:20] is used for BC. */
4569 record_full_arch_list_add_reg (regcache
,
4570 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4574 if ((ext
& 0xff) == 170)
4576 /* Add Extended using alternate carry bits */
4577 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4578 record_full_arch_list_add_reg (regcache
,
4579 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4585 case 78: /* Determine Leftmost Zero Byte */
4587 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4588 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4589 record_full_arch_list_add_reg (regcache
,
4590 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4593 /* These only write RT. */
4594 case 19: /* Move from condition register */
4595 /* Move From One Condition Register Field */
4596 case 74: /* Add and Generate Sixes */
4597 case 74 | 0x200: /* Add and Generate Sixes (bit-21 dont-care) */
4598 case 302: /* Move From Branch History Rolling Buffer */
4599 case 339: /* Move From Special Purpose Register */
4600 case 371: /* Move From Time Base [Phased-Out] */
4601 case 309: /* Load Doubleword Monitored Indexed */
4602 case 128: /* Set Boolean */
4603 case 755: /* Deliver A Random Number */
4604 record_full_arch_list_add_reg (regcache
,
4605 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4608 /* These only write to RA. */
4609 case 51: /* Move From VSR Doubleword */
4610 case 115: /* Move From VSR Word and Zero */
4611 case 122: /* Population count bytes */
4612 case 378: /* Population count words */
4613 case 506: /* Population count doublewords */
4614 case 154: /* Parity Word */
4615 case 186: /* Parity Doubleword */
4616 case 252: /* Bit Permute Doubleword */
4617 case 282: /* Convert Declets To Binary Coded Decimal */
4618 case 314: /* Convert Binary Coded Decimal To Declets */
4619 case 508: /* Compare bytes */
4620 case 307: /* Move From VSR Lower Doubleword */
4621 record_full_arch_list_add_reg (regcache
,
4622 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4625 /* These write CR and optional RA. */
4626 case 792: /* Shift Right Algebraic Word */
4627 case 794: /* Shift Right Algebraic Doubleword */
4628 case 824: /* Shift Right Algebraic Word Immediate */
4629 case 826: /* Shift Right Algebraic Doubleword Immediate (413) */
4630 case 826 | 1: /* Shift Right Algebraic Doubleword Immediate (413) */
4631 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4632 record_full_arch_list_add_reg (regcache
,
4633 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4635 case 0: /* Compare */
4636 case 32: /* Compare logical */
4637 case 144: /* Move To Condition Register Fields */
4638 /* Move To One Condition Register Field */
4639 case 192: /* Compare Ranged Byte */
4640 case 224: /* Compare Equal Byte */
4641 case 576: /* Move XER to CR Extended */
4642 case 902: /* Paste (should always fail due to single-stepping and
4643 the memory location might not be accessible, so
4645 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4648 /* These write to RT. Update RA if 'update indexed.' */
4649 case 53: /* Load Doubleword with Update Indexed */
4650 case 119: /* Load Byte and Zero with Update Indexed */
4651 case 311: /* Load Halfword and Zero with Update Indexed */
4652 case 55: /* Load Word and Zero with Update Indexed */
4653 case 375: /* Load Halfword Algebraic with Update Indexed */
4654 case 373: /* Load Word Algebraic with Update Indexed */
4655 record_full_arch_list_add_reg (regcache
,
4656 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4658 case 21: /* Load Doubleword Indexed */
4659 case 52: /* Load Byte And Reserve Indexed */
4660 case 116: /* Load Halfword And Reserve Indexed */
4661 case 20: /* Load Word And Reserve Indexed */
4662 case 84: /* Load Doubleword And Reserve Indexed */
4663 case 87: /* Load Byte and Zero Indexed */
4664 case 279: /* Load Halfword and Zero Indexed */
4665 case 23: /* Load Word and Zero Indexed */
4666 case 343: /* Load Halfword Algebraic Indexed */
4667 case 341: /* Load Word Algebraic Indexed */
4668 case 790: /* Load Halfword Byte-Reverse Indexed */
4669 case 534: /* Load Word Byte-Reverse Indexed */
4670 case 532: /* Load Doubleword Byte-Reverse Indexed */
4671 case 582: /* Load Word Atomic */
4672 case 614: /* Load Doubleword Atomic */
4673 case 265: /* Modulo Unsigned Doubleword */
4674 case 777: /* Modulo Signed Doubleword */
4675 case 267: /* Modulo Unsigned Word */
4676 case 779: /* Modulo Signed Word */
4677 record_full_arch_list_add_reg (regcache
,
4678 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4681 case 597: /* Load String Word Immediate */
4682 case 533: /* Load String Word Indexed */
4691 regcache_raw_read_unsigned (regcache
, tdep
->ppc_xer_regnum
, &xer
);
4692 nr
= PPC_XER_NB (xer
);
4697 /* If n=0, the contents of register RT are undefined. */
4701 for (i
= 0; i
< nr
; i
++)
4702 record_full_arch_list_add_reg (regcache
,
4703 tdep
->ppc_gp0_regnum
4704 + ((PPC_RT (insn
) + i
) & 0x1f));
4707 case 276: /* Load Quadword And Reserve Indexed */
4708 tmp
= tdep
->ppc_gp0_regnum
+ (PPC_RT (insn
) & ~1);
4709 record_full_arch_list_add_reg (regcache
, tmp
);
4710 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
4713 /* These write VRT. */
4714 case 6: /* Load Vector for Shift Left Indexed */
4715 case 38: /* Load Vector for Shift Right Indexed */
4716 case 7: /* Load Vector Element Byte Indexed */
4717 case 39: /* Load Vector Element Halfword Indexed */
4718 case 71: /* Load Vector Element Word Indexed */
4719 case 103: /* Load Vector Indexed */
4720 case 359: /* Load Vector Indexed LRU */
4721 record_full_arch_list_add_reg (regcache
,
4722 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4725 /* These write FRT. Update RA if 'update indexed.' */
4726 case 567: /* Load Floating-Point Single with Update Indexed */
4727 case 631: /* Load Floating-Point Double with Update Indexed */
4728 record_full_arch_list_add_reg (regcache
,
4729 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4731 case 535: /* Load Floating-Point Single Indexed */
4732 case 599: /* Load Floating-Point Double Indexed */
4733 case 855: /* Load Floating-Point as Integer Word Algebraic Indexed */
4734 case 887: /* Load Floating-Point as Integer Word and Zero Indexed */
4735 record_full_arch_list_add_reg (regcache
,
4736 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4739 case 791: /* Load Floating-Point Double Pair Indexed */
4740 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
4741 record_full_arch_list_add_reg (regcache
, tmp
);
4742 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
4745 case 179: /* Move To VSR Doubleword */
4746 case 211: /* Move To VSR Word Algebraic */
4747 case 243: /* Move To VSR Word and Zero */
4748 case 588: /* Load VSX Scalar Doubleword Indexed */
4749 case 524: /* Load VSX Scalar Single-Precision Indexed */
4750 case 76: /* Load VSX Scalar as Integer Word Algebraic Indexed */
4751 case 12: /* Load VSX Scalar as Integer Word and Zero Indexed */
4752 case 844: /* Load VSX Vector Doubleword*2 Indexed */
4753 case 332: /* Load VSX Vector Doubleword & Splat Indexed */
4754 case 780: /* Load VSX Vector Word*4 Indexed */
4755 case 268: /* Load VSX Vector Indexed */
4756 case 364: /* Load VSX Vector Word & Splat Indexed */
4757 case 812: /* Load VSX Vector Halfword*8 Indexed */
4758 case 876: /* Load VSX Vector Byte*16 Indexed */
4759 case 269: /* Load VSX Vector with Length */
4760 case 301: /* Load VSX Vector Left-justified with Length */
4761 case 781: /* Load VSX Scalar as Integer Byte & Zero Indexed */
4762 case 813: /* Load VSX Scalar as Integer Halfword & Zero Indexed */
4763 case 403: /* Move To VSR Word & Splat */
4764 case 435: /* Move To VSR Double Doubleword */
4765 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
4768 /* These write RA. Update CR if RC is set. */
4769 case 24: /* Shift Left Word */
4770 case 26: /* Count Leading Zeros Word */
4771 case 27: /* Shift Left Doubleword */
4773 case 58: /* Count Leading Zeros Doubleword */
4774 case 60: /* AND with Complement */
4776 case 284: /* Equivalent */
4778 case 476: /* NAND */
4779 case 412: /* OR with Complement */
4781 case 536: /* Shift Right Word */
4782 case 539: /* Shift Right Doubleword */
4783 case 922: /* Extend Sign Halfword */
4784 case 954: /* Extend Sign Byte */
4785 case 986: /* Extend Sign Word */
4786 case 538: /* Count Trailing Zeros Word */
4787 case 570: /* Count Trailing Zeros Doubleword */
4788 case 890: /* Extend-Sign Word and Shift Left Immediate (445) */
4789 case 890 | 1: /* Extend-Sign Word and Shift Left Immediate (445) */
4791 if (ext
== 444 && tdep
->ppc_ppr_regnum
>= 0
4792 && (PPC_RS (insn
) == PPC_RA (insn
))
4793 && (PPC_RA (insn
) == PPC_RB (insn
))
4796 /* or Rx,Rx,Rx alters PRI in PPR. */
4797 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ppr_regnum
);
4802 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4803 record_full_arch_list_add_reg (regcache
,
4804 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4808 case 181: /* Store Doubleword with Update Indexed */
4809 case 183: /* Store Word with Update Indexed */
4810 case 247: /* Store Byte with Update Indexed */
4811 case 439: /* Store Half Word with Update Indexed */
4812 case 695: /* Store Floating-Point Single with Update Indexed */
4813 case 759: /* Store Floating-Point Double with Update Indexed */
4814 record_full_arch_list_add_reg (regcache
,
4815 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4817 case 135: /* Store Vector Element Byte Indexed */
4818 case 167: /* Store Vector Element Halfword Indexed */
4819 case 199: /* Store Vector Element Word Indexed */
4820 case 231: /* Store Vector Indexed */
4821 case 487: /* Store Vector Indexed LRU */
4822 case 716: /* Store VSX Scalar Doubleword Indexed */
4823 case 140: /* Store VSX Scalar as Integer Word Indexed */
4824 case 652: /* Store VSX Scalar Single-Precision Indexed */
4825 case 972: /* Store VSX Vector Doubleword*2 Indexed */
4826 case 908: /* Store VSX Vector Word*4 Indexed */
4827 case 149: /* Store Doubleword Indexed */
4828 case 151: /* Store Word Indexed */
4829 case 215: /* Store Byte Indexed */
4830 case 407: /* Store Half Word Indexed */
4831 case 694: /* Store Byte Conditional Indexed */
4832 case 726: /* Store Halfword Conditional Indexed */
4833 case 150: /* Store Word Conditional Indexed */
4834 case 214: /* Store Doubleword Conditional Indexed */
4835 case 182: /* Store Quadword Conditional Indexed */
4836 case 662: /* Store Word Byte-Reverse Indexed */
4837 case 918: /* Store Halfword Byte-Reverse Indexed */
4838 case 660: /* Store Doubleword Byte-Reverse Indexed */
4839 case 663: /* Store Floating-Point Single Indexed */
4840 case 727: /* Store Floating-Point Double Indexed */
4841 case 919: /* Store Floating-Point Double Pair Indexed */
4842 case 983: /* Store Floating-Point as Integer Word Indexed */
4843 case 396: /* Store VSX Vector Indexed */
4844 case 940: /* Store VSX Vector Halfword*8 Indexed */
4845 case 1004: /* Store VSX Vector Byte*16 Indexed */
4846 case 909: /* Store VSX Scalar as Integer Byte Indexed */
4847 case 941: /* Store VSX Scalar as Integer Halfword Indexed */
4848 if (ext
== 694 || ext
== 726 || ext
== 150 || ext
== 214 || ext
== 182)
4849 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4852 if (PPC_RA (insn
) != 0)
4853 regcache_raw_read_unsigned (regcache
,
4854 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4855 regcache_raw_read_unsigned (regcache
,
4856 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
4861 case 183: /* Store Word with Update Indexed */
4862 case 199: /* Store Vector Element Word Indexed */
4863 case 140: /* Store VSX Scalar as Integer Word Indexed */
4864 case 652: /* Store VSX Scalar Single-Precision Indexed */
4865 case 151: /* Store Word Indexed */
4866 case 150: /* Store Word Conditional Indexed */
4867 case 662: /* Store Word Byte-Reverse Indexed */
4868 case 663: /* Store Floating-Point Single Indexed */
4869 case 695: /* Store Floating-Point Single with Update Indexed */
4870 case 983: /* Store Floating-Point as Integer Word Indexed */
4873 case 247: /* Store Byte with Update Indexed */
4874 case 135: /* Store Vector Element Byte Indexed */
4875 case 215: /* Store Byte Indexed */
4876 case 694: /* Store Byte Conditional Indexed */
4877 case 909: /* Store VSX Scalar as Integer Byte Indexed */
4880 case 439: /* Store Halfword with Update Indexed */
4881 case 167: /* Store Vector Element Halfword Indexed */
4882 case 407: /* Store Halfword Indexed */
4883 case 726: /* Store Halfword Conditional Indexed */
4884 case 918: /* Store Halfword Byte-Reverse Indexed */
4885 case 941: /* Store VSX Scalar as Integer Halfword Indexed */
4888 case 181: /* Store Doubleword with Update Indexed */
4889 case 716: /* Store VSX Scalar Doubleword Indexed */
4890 case 149: /* Store Doubleword Indexed */
4891 case 214: /* Store Doubleword Conditional Indexed */
4892 case 660: /* Store Doubleword Byte-Reverse Indexed */
4893 case 727: /* Store Floating-Point Double Indexed */
4894 case 759: /* Store Floating-Point Double with Update Indexed */
4897 case 972: /* Store VSX Vector Doubleword*2 Indexed */
4898 case 908: /* Store VSX Vector Word*4 Indexed */
4899 case 182: /* Store Quadword Conditional Indexed */
4900 case 231: /* Store Vector Indexed */
4901 case 487: /* Store Vector Indexed LRU */
4902 case 919: /* Store Floating-Point Double Pair Indexed */
4903 case 396: /* Store VSX Vector Indexed */
4904 case 940: /* Store VSX Vector Halfword*8 Indexed */
4905 case 1004: /* Store VSX Vector Byte*16 Indexed */
4912 /* Align address for Store Vector instructions. */
4915 case 167: /* Store Vector Element Halfword Indexed */
4916 addr
= addr
& ~0x1ULL
;
4919 case 199: /* Store Vector Element Word Indexed */
4920 addr
= addr
& ~0x3ULL
;
4923 case 231: /* Store Vector Indexed */
4924 case 487: /* Store Vector Indexed LRU */
4925 addr
= addr
& ~0xfULL
;
4929 record_full_arch_list_add_mem (addr
, size
);
4932 case 397: /* Store VSX Vector with Length */
4933 case 429: /* Store VSX Vector Left-justified with Length */
4935 if (PPC_RA (insn
) != 0)
4936 regcache_raw_read_unsigned (regcache
,
4937 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4939 regcache_raw_read_unsigned (regcache
,
4940 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
4941 /* Store up to 16 bytes. */
4942 nb
= (rb
& 0xff) > 16 ? 16 : (rb
& 0xff);
4944 record_full_arch_list_add_mem (ea
, nb
);
4947 case 710: /* Store Word Atomic */
4948 case 742: /* Store Doubleword Atomic */
4950 if (PPC_RA (insn
) != 0)
4951 regcache_raw_read_unsigned (regcache
,
4952 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4956 case 710: /* Store Word Atomic */
4959 case 742: /* Store Doubleword Atomic */
4965 record_full_arch_list_add_mem (ea
, size
);
4968 case 725: /* Store String Word Immediate */
4970 if (PPC_RA (insn
) != 0)
4971 regcache_raw_read_unsigned (regcache
,
4972 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4979 record_full_arch_list_add_mem (ea
, nb
);
4983 case 661: /* Store String Word Indexed */
4985 if (PPC_RA (insn
) != 0)
4986 regcache_raw_read_unsigned (regcache
,
4987 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4990 regcache_raw_read_unsigned (regcache
, tdep
->ppc_xer_regnum
, &xer
);
4991 nb
= PPC_XER_NB (xer
);
4995 regcache_raw_read_unsigned (regcache
,
4996 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
),
4999 record_full_arch_list_add_mem (ea
, nb
);
5004 case 467: /* Move To Special Purpose Register */
5005 switch (PPC_SPR (insn
))
5008 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
5011 if (tdep
->ppc_dscr_regnum
>= 0)
5012 record_full_arch_list_add_reg (regcache
, tdep
->ppc_dscr_regnum
);
5015 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
5018 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
5020 case 256: /* VRSAVE */
5021 record_full_arch_list_add_reg (regcache
, tdep
->ppc_vrsave_regnum
);
5024 if (tdep
->ppc_tar_regnum
>= 0)
5025 record_full_arch_list_add_reg (regcache
, tdep
->ppc_tar_regnum
);
5029 if (tdep
->ppc_ppr_regnum
>= 0)
5030 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ppr_regnum
);
5036 case 147: /* Move To Split Little Endian */
5037 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ps_regnum
);
5040 case 512: /* Move to Condition Register from XER */
5041 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5042 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
5045 case 4: /* Trap Word */
5046 case 68: /* Trap Doubleword */
5047 case 430: /* Clear BHRB */
5048 case 598: /* Synchronize */
5049 case 62: /* Wait for Interrupt */
5051 case 22: /* Instruction Cache Block Touch */
5052 case 854: /* Enforce In-order Execution of I/O */
5053 case 246: /* Data Cache Block Touch for Store */
5054 case 54: /* Data Cache Block Store */
5055 case 86: /* Data Cache Block Flush */
5056 case 278: /* Data Cache Block Touch */
5057 case 758: /* Data Cache Block Allocate */
5058 case 982: /* Instruction Cache Block Invalidate */
5059 case 774: /* Copy */
5060 case 838: /* CP_Abort */
5063 case 654: /* Transaction Begin */
5064 case 686: /* Transaction End */
5065 case 750: /* Transaction Suspend or Resume */
5066 case 782: /* Transaction Abort Word Conditional */
5067 case 814: /* Transaction Abort Doubleword Conditional */
5068 case 846: /* Transaction Abort Word Conditional Immediate */
5069 case 878: /* Transaction Abort Doubleword Conditional Immediate */
5070 case 910: /* Transaction Abort */
5071 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ps_regnum
);
5073 case 718: /* Transaction Check */
5074 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5077 case 1014: /* Data Cache Block set to Zero */
5078 if (target_auxv_search (current_top_target (), AT_DCACHEBSIZE
, &at_dcsz
) <= 0
5080 at_dcsz
= 128; /* Assume 128-byte cache line size (POWER8) */
5083 if (PPC_RA (insn
) != 0)
5084 regcache_raw_read_unsigned (regcache
,
5085 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
5086 regcache_raw_read_unsigned (regcache
,
5087 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
5088 ea
= (ra
+ rb
) & ~((ULONGEST
) (at_dcsz
- 1));
5089 record_full_arch_list_add_mem (ea
, at_dcsz
);
5094 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5095 "at %s, 31-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
5099 /* Parse and record instructions of primary opcode-59 at ADDR.
5100 Return 0 if successful. */
5103 ppc_process_record_op59 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5104 CORE_ADDR addr
, uint32_t insn
)
5106 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5107 int ext
= PPC_EXTOP (insn
);
5111 case 18: /* Floating Divide */
5112 case 20: /* Floating Subtract */
5113 case 21: /* Floating Add */
5114 case 22: /* Floating Square Root */
5115 case 24: /* Floating Reciprocal Estimate */
5116 case 25: /* Floating Multiply */
5117 case 26: /* Floating Reciprocal Square Root Estimate */
5118 case 28: /* Floating Multiply-Subtract */
5119 case 29: /* Floating Multiply-Add */
5120 case 30: /* Floating Negative Multiply-Subtract */
5121 case 31: /* Floating Negative Multiply-Add */
5122 record_full_arch_list_add_reg (regcache
,
5123 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5125 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5126 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5133 case 2: /* DFP Add */
5134 case 3: /* DFP Quantize */
5135 case 34: /* DFP Multiply */
5136 case 35: /* DFP Reround */
5137 case 67: /* DFP Quantize Immediate */
5138 case 99: /* DFP Round To FP Integer With Inexact */
5139 case 227: /* DFP Round To FP Integer Without Inexact */
5140 case 258: /* DFP Convert To DFP Long! */
5141 case 290: /* DFP Convert To Fixed */
5142 case 514: /* DFP Subtract */
5143 case 546: /* DFP Divide */
5144 case 770: /* DFP Round To DFP Short! */
5145 case 802: /* DFP Convert From Fixed */
5146 case 834: /* DFP Encode BCD To DPD */
5148 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5149 record_full_arch_list_add_reg (regcache
,
5150 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5151 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5154 case 130: /* DFP Compare Ordered */
5155 case 162: /* DFP Test Exponent */
5156 case 194: /* DFP Test Data Class */
5157 case 226: /* DFP Test Data Group */
5158 case 642: /* DFP Compare Unordered */
5159 case 674: /* DFP Test Significance */
5160 case 675: /* DFP Test Significance Immediate */
5161 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5162 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5165 case 66: /* DFP Shift Significand Left Immediate */
5166 case 98: /* DFP Shift Significand Right Immediate */
5167 case 322: /* DFP Decode DPD To BCD */
5168 case 354: /* DFP Extract Biased Exponent */
5169 case 866: /* DFP Insert Biased Exponent */
5170 record_full_arch_list_add_reg (regcache
,
5171 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5173 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5176 case 846: /* Floating Convert From Integer Doubleword Single */
5177 case 974: /* Floating Convert From Integer Doubleword Unsigned
5179 record_full_arch_list_add_reg (regcache
,
5180 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5182 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5183 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5188 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5189 "at %s, 59-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
5193 /* Parse and record instructions of primary opcode-60 at ADDR.
5194 Return 0 if successful. */
5197 ppc_process_record_op60 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5198 CORE_ADDR addr
, uint32_t insn
)
5200 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5201 int ext
= PPC_EXTOP (insn
);
5205 case 0: /* VSX Scalar Add Single-Precision */
5206 case 32: /* VSX Scalar Add Double-Precision */
5207 case 24: /* VSX Scalar Divide Single-Precision */
5208 case 56: /* VSX Scalar Divide Double-Precision */
5209 case 176: /* VSX Scalar Copy Sign Double-Precision */
5210 case 33: /* VSX Scalar Multiply-Add Double-Precision */
5211 case 41: /* ditto */
5212 case 1: /* VSX Scalar Multiply-Add Single-Precision */
5214 case 160: /* VSX Scalar Maximum Double-Precision */
5215 case 168: /* VSX Scalar Minimum Double-Precision */
5216 case 49: /* VSX Scalar Multiply-Subtract Double-Precision */
5217 case 57: /* ditto */
5218 case 17: /* VSX Scalar Multiply-Subtract Single-Precision */
5219 case 25: /* ditto */
5220 case 48: /* VSX Scalar Multiply Double-Precision */
5221 case 16: /* VSX Scalar Multiply Single-Precision */
5222 case 161: /* VSX Scalar Negative Multiply-Add Double-Precision */
5223 case 169: /* ditto */
5224 case 129: /* VSX Scalar Negative Multiply-Add Single-Precision */
5225 case 137: /* ditto */
5226 case 177: /* VSX Scalar Negative Multiply-Subtract Double-Precision */
5227 case 185: /* ditto */
5228 case 145: /* VSX Scalar Negative Multiply-Subtract Single-Precision */
5229 case 153: /* ditto */
5230 case 40: /* VSX Scalar Subtract Double-Precision */
5231 case 8: /* VSX Scalar Subtract Single-Precision */
5232 case 96: /* VSX Vector Add Double-Precision */
5233 case 64: /* VSX Vector Add Single-Precision */
5234 case 120: /* VSX Vector Divide Double-Precision */
5235 case 88: /* VSX Vector Divide Single-Precision */
5236 case 97: /* VSX Vector Multiply-Add Double-Precision */
5237 case 105: /* ditto */
5238 case 65: /* VSX Vector Multiply-Add Single-Precision */
5239 case 73: /* ditto */
5240 case 224: /* VSX Vector Maximum Double-Precision */
5241 case 192: /* VSX Vector Maximum Single-Precision */
5242 case 232: /* VSX Vector Minimum Double-Precision */
5243 case 200: /* VSX Vector Minimum Single-Precision */
5244 case 113: /* VSX Vector Multiply-Subtract Double-Precision */
5245 case 121: /* ditto */
5246 case 81: /* VSX Vector Multiply-Subtract Single-Precision */
5247 case 89: /* ditto */
5248 case 112: /* VSX Vector Multiply Double-Precision */
5249 case 80: /* VSX Vector Multiply Single-Precision */
5250 case 225: /* VSX Vector Negative Multiply-Add Double-Precision */
5251 case 233: /* ditto */
5252 case 193: /* VSX Vector Negative Multiply-Add Single-Precision */
5253 case 201: /* ditto */
5254 case 241: /* VSX Vector Negative Multiply-Subtract Double-Precision */
5255 case 249: /* ditto */
5256 case 209: /* VSX Vector Negative Multiply-Subtract Single-Precision */
5257 case 217: /* ditto */
5258 case 104: /* VSX Vector Subtract Double-Precision */
5259 case 72: /* VSX Vector Subtract Single-Precision */
5260 case 128: /* VSX Scalar Maximum Type-C Double-Precision */
5261 case 136: /* VSX Scalar Minimum Type-C Double-Precision */
5262 case 144: /* VSX Scalar Maximum Type-J Double-Precision */
5263 case 152: /* VSX Scalar Minimum Type-J Double-Precision */
5264 case 3: /* VSX Scalar Compare Equal Double-Precision */
5265 case 11: /* VSX Scalar Compare Greater Than Double-Precision */
5266 case 19: /* VSX Scalar Compare Greater Than or Equal
5268 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5270 case 240: /* VSX Vector Copy Sign Double-Precision */
5271 case 208: /* VSX Vector Copy Sign Single-Precision */
5272 case 130: /* VSX Logical AND */
5273 case 138: /* VSX Logical AND with Complement */
5274 case 186: /* VSX Logical Equivalence */
5275 case 178: /* VSX Logical NAND */
5276 case 170: /* VSX Logical OR with Complement */
5277 case 162: /* VSX Logical NOR */
5278 case 146: /* VSX Logical OR */
5279 case 154: /* VSX Logical XOR */
5280 case 18: /* VSX Merge High Word */
5281 case 50: /* VSX Merge Low Word */
5282 case 10: /* VSX Permute Doubleword Immediate (DM=0) */
5283 case 10 | 0x20: /* VSX Permute Doubleword Immediate (DM=1) */
5284 case 10 | 0x40: /* VSX Permute Doubleword Immediate (DM=2) */
5285 case 10 | 0x60: /* VSX Permute Doubleword Immediate (DM=3) */
5286 case 2: /* VSX Shift Left Double by Word Immediate (SHW=0) */
5287 case 2 | 0x20: /* VSX Shift Left Double by Word Immediate (SHW=1) */
5288 case 2 | 0x40: /* VSX Shift Left Double by Word Immediate (SHW=2) */
5289 case 2 | 0x60: /* VSX Shift Left Double by Word Immediate (SHW=3) */
5290 case 216: /* VSX Vector Insert Exponent Single-Precision */
5291 case 248: /* VSX Vector Insert Exponent Double-Precision */
5292 case 26: /* VSX Vector Permute */
5293 case 58: /* VSX Vector Permute Right-indexed */
5294 case 213: /* VSX Vector Test Data Class Single-Precision (DC=0) */
5295 case 213 | 0x8: /* VSX Vector Test Data Class Single-Precision (DC=1) */
5296 case 245: /* VSX Vector Test Data Class Double-Precision (DC=0) */
5297 case 245 | 0x8: /* VSX Vector Test Data Class Double-Precision (DC=1) */
5298 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5301 case 61: /* VSX Scalar Test for software Divide Double-Precision */
5302 case 125: /* VSX Vector Test for software Divide Double-Precision */
5303 case 93: /* VSX Vector Test for software Divide Single-Precision */
5304 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5307 case 35: /* VSX Scalar Compare Unordered Double-Precision */
5308 case 43: /* VSX Scalar Compare Ordered Double-Precision */
5309 case 59: /* VSX Scalar Compare Exponents Double-Precision */
5310 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5311 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5315 switch ((ext
>> 2) & 0x7f) /* Mask out Rc-bit. */
5317 case 99: /* VSX Vector Compare Equal To Double-Precision */
5318 case 67: /* VSX Vector Compare Equal To Single-Precision */
5319 case 115: /* VSX Vector Compare Greater Than or
5320 Equal To Double-Precision */
5321 case 83: /* VSX Vector Compare Greater Than or
5322 Equal To Single-Precision */
5323 case 107: /* VSX Vector Compare Greater Than Double-Precision */
5324 case 75: /* VSX Vector Compare Greater Than Single-Precision */
5326 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5327 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5328 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5334 case 265: /* VSX Scalar round Double-Precision to
5335 Single-Precision and Convert to
5336 Single-Precision format */
5337 case 344: /* VSX Scalar truncate Double-Precision to
5338 Integer and Convert to Signed Integer
5339 Doubleword format with Saturate */
5340 case 88: /* VSX Scalar truncate Double-Precision to
5341 Integer and Convert to Signed Integer Word
5342 Format with Saturate */
5343 case 328: /* VSX Scalar truncate Double-Precision integer
5344 and Convert to Unsigned Integer Doubleword
5345 Format with Saturate */
5346 case 72: /* VSX Scalar truncate Double-Precision to
5347 Integer and Convert to Unsigned Integer Word
5348 Format with Saturate */
5349 case 329: /* VSX Scalar Convert Single-Precision to
5350 Double-Precision format */
5351 case 376: /* VSX Scalar Convert Signed Integer
5352 Doubleword to floating-point format and
5353 Round to Double-Precision format */
5354 case 312: /* VSX Scalar Convert Signed Integer
5355 Doubleword to floating-point format and
5356 round to Single-Precision */
5357 case 360: /* VSX Scalar Convert Unsigned Integer
5358 Doubleword to floating-point format and
5359 Round to Double-Precision format */
5360 case 296: /* VSX Scalar Convert Unsigned Integer
5361 Doubleword to floating-point format and
5362 Round to Single-Precision */
5363 case 73: /* VSX Scalar Round to Double-Precision Integer
5364 Using Round to Nearest Away */
5365 case 107: /* VSX Scalar Round to Double-Precision Integer
5366 Exact using Current rounding mode */
5367 case 121: /* VSX Scalar Round to Double-Precision Integer
5368 Using Round toward -Infinity */
5369 case 105: /* VSX Scalar Round to Double-Precision Integer
5370 Using Round toward +Infinity */
5371 case 89: /* VSX Scalar Round to Double-Precision Integer
5372 Using Round toward Zero */
5373 case 90: /* VSX Scalar Reciprocal Estimate Double-Precision */
5374 case 26: /* VSX Scalar Reciprocal Estimate Single-Precision */
5375 case 281: /* VSX Scalar Round to Single-Precision */
5376 case 74: /* VSX Scalar Reciprocal Square Root Estimate
5378 case 10: /* VSX Scalar Reciprocal Square Root Estimate
5380 case 75: /* VSX Scalar Square Root Double-Precision */
5381 case 11: /* VSX Scalar Square Root Single-Precision */
5382 case 393: /* VSX Vector round Double-Precision to
5383 Single-Precision and Convert to
5384 Single-Precision format */
5385 case 472: /* VSX Vector truncate Double-Precision to
5386 Integer and Convert to Signed Integer
5387 Doubleword format with Saturate */
5388 case 216: /* VSX Vector truncate Double-Precision to
5389 Integer and Convert to Signed Integer Word
5390 Format with Saturate */
5391 case 456: /* VSX Vector truncate Double-Precision to
5392 Integer and Convert to Unsigned Integer
5393 Doubleword format with Saturate */
5394 case 200: /* VSX Vector truncate Double-Precision to
5395 Integer and Convert to Unsigned Integer Word
5396 Format with Saturate */
5397 case 457: /* VSX Vector Convert Single-Precision to
5398 Double-Precision format */
5399 case 408: /* VSX Vector truncate Single-Precision to
5400 Integer and Convert to Signed Integer
5401 Doubleword format with Saturate */
5402 case 152: /* VSX Vector truncate Single-Precision to
5403 Integer and Convert to Signed Integer Word
5404 Format with Saturate */
5405 case 392: /* VSX Vector truncate Single-Precision to
5406 Integer and Convert to Unsigned Integer
5407 Doubleword format with Saturate */
5408 case 136: /* VSX Vector truncate Single-Precision to
5409 Integer and Convert to Unsigned Integer Word
5410 Format with Saturate */
5411 case 504: /* VSX Vector Convert and round Signed Integer
5412 Doubleword to Double-Precision format */
5413 case 440: /* VSX Vector Convert and round Signed Integer
5414 Doubleword to Single-Precision format */
5415 case 248: /* VSX Vector Convert Signed Integer Word to
5416 Double-Precision format */
5417 case 184: /* VSX Vector Convert and round Signed Integer
5418 Word to Single-Precision format */
5419 case 488: /* VSX Vector Convert and round Unsigned
5420 Integer Doubleword to Double-Precision format */
5421 case 424: /* VSX Vector Convert and round Unsigned
5422 Integer Doubleword to Single-Precision format */
5423 case 232: /* VSX Vector Convert and round Unsigned
5424 Integer Word to Double-Precision format */
5425 case 168: /* VSX Vector Convert and round Unsigned
5426 Integer Word to Single-Precision format */
5427 case 201: /* VSX Vector Round to Double-Precision
5428 Integer using round to Nearest Away */
5429 case 235: /* VSX Vector Round to Double-Precision
5430 Integer Exact using Current rounding mode */
5431 case 249: /* VSX Vector Round to Double-Precision
5432 Integer using round toward -Infinity */
5433 case 233: /* VSX Vector Round to Double-Precision
5434 Integer using round toward +Infinity */
5435 case 217: /* VSX Vector Round to Double-Precision
5436 Integer using round toward Zero */
5437 case 218: /* VSX Vector Reciprocal Estimate Double-Precision */
5438 case 154: /* VSX Vector Reciprocal Estimate Single-Precision */
5439 case 137: /* VSX Vector Round to Single-Precision Integer
5440 Using Round to Nearest Away */
5441 case 171: /* VSX Vector Round to Single-Precision Integer
5442 Exact Using Current rounding mode */
5443 case 185: /* VSX Vector Round to Single-Precision Integer
5444 Using Round toward -Infinity */
5445 case 169: /* VSX Vector Round to Single-Precision Integer
5446 Using Round toward +Infinity */
5447 case 153: /* VSX Vector Round to Single-Precision Integer
5448 Using round toward Zero */
5449 case 202: /* VSX Vector Reciprocal Square Root Estimate
5451 case 138: /* VSX Vector Reciprocal Square Root Estimate
5453 case 203: /* VSX Vector Square Root Double-Precision */
5454 case 139: /* VSX Vector Square Root Single-Precision */
5455 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5457 case 345: /* VSX Scalar Absolute Value Double-Precision */
5458 case 267: /* VSX Scalar Convert Scalar Single-Precision to
5459 Vector Single-Precision format Non-signalling */
5460 case 331: /* VSX Scalar Convert Single-Precision to
5461 Double-Precision format Non-signalling */
5462 case 361: /* VSX Scalar Negative Absolute Value Double-Precision */
5463 case 377: /* VSX Scalar Negate Double-Precision */
5464 case 473: /* VSX Vector Absolute Value Double-Precision */
5465 case 409: /* VSX Vector Absolute Value Single-Precision */
5466 case 489: /* VSX Vector Negative Absolute Value Double-Precision */
5467 case 425: /* VSX Vector Negative Absolute Value Single-Precision */
5468 case 505: /* VSX Vector Negate Double-Precision */
5469 case 441: /* VSX Vector Negate Single-Precision */
5470 case 164: /* VSX Splat Word */
5471 case 165: /* VSX Vector Extract Unsigned Word */
5472 case 181: /* VSX Vector Insert Word */
5473 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5476 case 298: /* VSX Scalar Test Data Class Single-Precision */
5477 case 362: /* VSX Scalar Test Data Class Double-Precision */
5478 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5480 case 106: /* VSX Scalar Test for software Square Root
5482 case 234: /* VSX Vector Test for software Square Root
5484 case 170: /* VSX Vector Test for software Square Root
5486 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5490 switch (PPC_FIELD (insn
, 11, 5))
5492 case 0: /* VSX Scalar Extract Exponent Double-Precision */
5493 case 1: /* VSX Scalar Extract Significand Double-Precision */
5494 record_full_arch_list_add_reg (regcache
,
5495 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5497 case 16: /* VSX Scalar Convert Half-Precision format to
5498 Double-Precision format */
5499 case 17: /* VSX Scalar round & Convert Double-Precision format
5500 to Half-Precision format */
5501 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5502 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5508 switch (PPC_FIELD (insn
, 11, 5))
5510 case 24: /* VSX Vector Convert Half-Precision format to
5511 Single-Precision format */
5512 case 25: /* VSX Vector round and Convert Single-Precision format
5513 to Half-Precision format */
5514 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5516 case 0: /* VSX Vector Extract Exponent Double-Precision */
5517 case 1: /* VSX Vector Extract Significand Double-Precision */
5518 case 7: /* VSX Vector Byte-Reverse Halfword */
5519 case 8: /* VSX Vector Extract Exponent Single-Precision */
5520 case 9: /* VSX Vector Extract Significand Single-Precision */
5521 case 15: /* VSX Vector Byte-Reverse Word */
5522 case 23: /* VSX Vector Byte-Reverse Doubleword */
5523 case 31: /* VSX Vector Byte-Reverse Quadword */
5524 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5532 case 360: /* VSX Vector Splat Immediate Byte */
5533 if (PPC_FIELD (insn
, 11, 2) == 0)
5535 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5539 case 918: /* VSX Scalar Insert Exponent Double-Precision */
5540 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5544 if (((ext
>> 3) & 0x3) == 3) /* VSX Select */
5546 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5550 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5551 "at %s, 60-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
5555 /* Parse and record instructions of primary opcode-61 at ADDR.
5556 Return 0 if successful. */
5559 ppc_process_record_op61 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5560 CORE_ADDR addr
, uint32_t insn
)
5562 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5568 case 0: /* Store Floating-Point Double Pair */
5569 case 2: /* Store VSX Scalar Doubleword */
5570 case 3: /* Store VSX Scalar Single */
5571 if (PPC_RA (insn
) != 0)
5572 regcache_raw_read_unsigned (regcache
,
5573 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5575 ea
+= PPC_DS (insn
) << 2;
5578 case 0: /* Store Floating-Point Double Pair */
5581 case 2: /* Store VSX Scalar Doubleword */
5584 case 3: /* Store VSX Scalar Single */
5590 record_full_arch_list_add_mem (ea
, size
);
5596 case 1: /* Load VSX Vector */
5597 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5599 case 5: /* Store VSX Vector */
5600 if (PPC_RA (insn
) != 0)
5601 regcache_raw_read_unsigned (regcache
,
5602 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5604 ea
+= PPC_DQ (insn
) << 4;
5605 record_full_arch_list_add_mem (ea
, 16);
5609 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5610 "at %s.\n", insn
, paddress (gdbarch
, addr
));
5614 /* Parse and record instructions of primary opcode-63 at ADDR.
5615 Return 0 if successful. */
5618 ppc_process_record_op63 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5619 CORE_ADDR addr
, uint32_t insn
)
5621 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5622 int ext
= PPC_EXTOP (insn
);
5627 case 18: /* Floating Divide */
5628 case 20: /* Floating Subtract */
5629 case 21: /* Floating Add */
5630 case 22: /* Floating Square Root */
5631 case 24: /* Floating Reciprocal Estimate */
5632 case 25: /* Floating Multiply */
5633 case 26: /* Floating Reciprocal Square Root Estimate */
5634 case 28: /* Floating Multiply-Subtract */
5635 case 29: /* Floating Multiply-Add */
5636 case 30: /* Floating Negative Multiply-Subtract */
5637 case 31: /* Floating Negative Multiply-Add */
5638 record_full_arch_list_add_reg (regcache
,
5639 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5641 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5642 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5645 case 23: /* Floating Select */
5646 record_full_arch_list_add_reg (regcache
,
5647 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5649 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5655 case 5: /* VSX Scalar Round to Quad-Precision Integer */
5656 case 37: /* VSX Scalar Round Quad-Precision to Double-Extended
5658 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5659 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5665 case 2: /* DFP Add Quad */
5666 case 3: /* DFP Quantize Quad */
5667 case 34: /* DFP Multiply Quad */
5668 case 35: /* DFP Reround Quad */
5669 case 67: /* DFP Quantize Immediate Quad */
5670 case 99: /* DFP Round To FP Integer With Inexact Quad */
5671 case 227: /* DFP Round To FP Integer Without Inexact Quad */
5672 case 258: /* DFP Convert To DFP Extended Quad */
5673 case 514: /* DFP Subtract Quad */
5674 case 546: /* DFP Divide Quad */
5675 case 770: /* DFP Round To DFP Long Quad */
5676 case 802: /* DFP Convert From Fixed Quad */
5677 case 834: /* DFP Encode BCD To DPD Quad */
5679 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5680 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
5681 record_full_arch_list_add_reg (regcache
, tmp
);
5682 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5683 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5686 case 130: /* DFP Compare Ordered Quad */
5687 case 162: /* DFP Test Exponent Quad */
5688 case 194: /* DFP Test Data Class Quad */
5689 case 226: /* DFP Test Data Group Quad */
5690 case 642: /* DFP Compare Unordered Quad */
5691 case 674: /* DFP Test Significance Quad */
5692 case 675: /* DFP Test Significance Immediate Quad */
5693 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5694 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5697 case 66: /* DFP Shift Significand Left Immediate Quad */
5698 case 98: /* DFP Shift Significand Right Immediate Quad */
5699 case 322: /* DFP Decode DPD To BCD Quad */
5700 case 866: /* DFP Insert Biased Exponent Quad */
5701 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
5702 record_full_arch_list_add_reg (regcache
, tmp
);
5703 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5705 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5708 case 290: /* DFP Convert To Fixed Quad */
5709 record_full_arch_list_add_reg (regcache
,
5710 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5712 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5713 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5716 case 354: /* DFP Extract Biased Exponent Quad */
5717 record_full_arch_list_add_reg (regcache
,
5718 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5720 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5723 case 12: /* Floating Round to Single-Precision */
5724 case 14: /* Floating Convert To Integer Word */
5725 case 15: /* Floating Convert To Integer Word
5726 with round toward Zero */
5727 case 142: /* Floating Convert To Integer Word Unsigned */
5728 case 143: /* Floating Convert To Integer Word Unsigned
5729 with round toward Zero */
5730 case 392: /* Floating Round to Integer Nearest */
5731 case 424: /* Floating Round to Integer Toward Zero */
5732 case 456: /* Floating Round to Integer Plus */
5733 case 488: /* Floating Round to Integer Minus */
5734 case 814: /* Floating Convert To Integer Doubleword */
5735 case 815: /* Floating Convert To Integer Doubleword
5736 with round toward Zero */
5737 case 846: /* Floating Convert From Integer Doubleword */
5738 case 942: /* Floating Convert To Integer Doubleword Unsigned */
5739 case 943: /* Floating Convert To Integer Doubleword Unsigned
5740 with round toward Zero */
5741 case 974: /* Floating Convert From Integer Doubleword Unsigned */
5742 record_full_arch_list_add_reg (regcache
,
5743 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5745 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5746 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5750 switch (PPC_FIELD (insn
, 11, 5))
5752 case 1: /* Move From FPSCR & Clear Enables */
5753 case 20: /* Move From FPSCR Control & set DRN */
5754 case 21: /* Move From FPSCR Control & set DRN Immediate */
5755 case 22: /* Move From FPSCR Control & set RN */
5756 case 23: /* Move From FPSCR Control & set RN Immediate */
5757 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5759 case 0: /* Move From FPSCR */
5760 case 24: /* Move From FPSCR Lightweight */
5761 if (PPC_FIELD (insn
, 11, 5) == 0 && PPC_RC (insn
))
5762 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5763 record_full_arch_list_add_reg (regcache
,
5764 tdep
->ppc_fp0_regnum
5770 case 8: /* Floating Copy Sign */
5771 case 40: /* Floating Negate */
5772 case 72: /* Floating Move Register */
5773 case 136: /* Floating Negative Absolute Value */
5774 case 264: /* Floating Absolute Value */
5775 record_full_arch_list_add_reg (regcache
,
5776 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5778 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5781 case 838: /* Floating Merge Odd Word */
5782 case 966: /* Floating Merge Even Word */
5783 record_full_arch_list_add_reg (regcache
,
5784 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5787 case 38: /* Move To FPSCR Bit 1 */
5788 case 70: /* Move To FPSCR Bit 0 */
5789 case 134: /* Move To FPSCR Field Immediate */
5790 case 711: /* Move To FPSCR Fields */
5792 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5793 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5796 case 0: /* Floating Compare Unordered */
5797 case 32: /* Floating Compare Ordered */
5798 case 64: /* Move to Condition Register from FPSCR */
5799 case 132: /* VSX Scalar Compare Ordered Quad-Precision */
5800 case 164: /* VSX Scalar Compare Exponents Quad-Precision */
5801 case 644: /* VSX Scalar Compare Unordered Quad-Precision */
5802 case 708: /* VSX Scalar Test Data Class Quad-Precision */
5803 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5805 case 128: /* Floating Test for software Divide */
5806 case 160: /* Floating Test for software Square Root */
5807 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5810 case 4: /* VSX Scalar Add Quad-Precision */
5811 case 36: /* VSX Scalar Multiply Quad-Precision */
5812 case 388: /* VSX Scalar Multiply-Add Quad-Precision */
5813 case 420: /* VSX Scalar Multiply-Subtract Quad-Precision */
5814 case 452: /* VSX Scalar Negative Multiply-Add Quad-Precision */
5815 case 484: /* VSX Scalar Negative Multiply-Subtract
5817 case 516: /* VSX Scalar Subtract Quad-Precision */
5818 case 548: /* VSX Scalar Divide Quad-Precision */
5819 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5821 case 100: /* VSX Scalar Copy Sign Quad-Precision */
5822 case 868: /* VSX Scalar Insert Exponent Quad-Precision */
5823 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5827 switch (PPC_FIELD (insn
, 11, 5))
5829 case 27: /* VSX Scalar Square Root Quad-Precision */
5830 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5832 case 0: /* VSX Scalar Absolute Quad-Precision */
5833 case 2: /* VSX Scalar Extract Exponent Quad-Precision */
5834 case 8: /* VSX Scalar Negative Absolute Quad-Precision */
5835 case 16: /* VSX Scalar Negate Quad-Precision */
5836 case 18: /* VSX Scalar Extract Significand Quad-Precision */
5837 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5843 switch (PPC_FIELD (insn
, 11, 5))
5845 case 1: /* VSX Scalar truncate & Convert Quad-Precision format
5846 to Unsigned Word format */
5847 case 2: /* VSX Scalar Convert Unsigned Doubleword format to
5848 Quad-Precision format */
5849 case 9: /* VSX Scalar truncate & Convert Quad-Precision format
5850 to Signed Word format */
5851 case 10: /* VSX Scalar Convert Signed Doubleword format to
5852 Quad-Precision format */
5853 case 17: /* VSX Scalar truncate & Convert Quad-Precision format
5854 to Unsigned Doubleword format */
5855 case 20: /* VSX Scalar round & Convert Quad-Precision format to
5856 Double-Precision format */
5857 case 22: /* VSX Scalar Convert Double-Precision format to
5858 Quad-Precision format */
5859 case 25: /* VSX Scalar truncate & Convert Quad-Precision format
5860 to Signed Doubleword format */
5861 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5862 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5867 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5868 "at %s, 63-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
5872 /* Parse the current instruction and record the values of the registers and
5873 memory that will be changed in current instruction to "record_arch_list".
5874 Return -1 if something wrong. */
5877 ppc_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5880 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5881 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5885 insn
= read_memory_unsigned_integer (addr
, 4, byte_order
);
5886 op6
= PPC_OP6 (insn
);
5890 case 2: /* Trap Doubleword Immediate */
5891 case 3: /* Trap Word Immediate */
5896 if (ppc_process_record_op4 (gdbarch
, regcache
, addr
, insn
) != 0)
5900 case 17: /* System call */
5901 if (PPC_LEV (insn
) != 0)
5904 if (tdep
->ppc_syscall_record
!= NULL
)
5906 if (tdep
->ppc_syscall_record (regcache
) != 0)
5911 printf_unfiltered (_("no syscall record support\n"));
5916 case 7: /* Multiply Low Immediate */
5917 record_full_arch_list_add_reg (regcache
,
5918 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5921 case 8: /* Subtract From Immediate Carrying */
5922 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
5923 record_full_arch_list_add_reg (regcache
,
5924 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5927 case 10: /* Compare Logical Immediate */
5928 case 11: /* Compare Immediate */
5929 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5932 case 13: /* Add Immediate Carrying and Record */
5933 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5935 case 12: /* Add Immediate Carrying */
5936 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
5938 case 14: /* Add Immediate */
5939 case 15: /* Add Immediate Shifted */
5940 record_full_arch_list_add_reg (regcache
,
5941 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5944 case 16: /* Branch Conditional */
5945 if ((PPC_BO (insn
) & 0x4) == 0)
5946 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
5948 case 18: /* Branch */
5950 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
5954 if (ppc_process_record_op19 (gdbarch
, regcache
, addr
, insn
) != 0)
5958 case 20: /* Rotate Left Word Immediate then Mask Insert */
5959 case 21: /* Rotate Left Word Immediate then AND with Mask */
5960 case 23: /* Rotate Left Word then AND with Mask */
5961 case 30: /* Rotate Left Doubleword Immediate then Clear Left */
5962 /* Rotate Left Doubleword Immediate then Clear Right */
5963 /* Rotate Left Doubleword Immediate then Clear */
5964 /* Rotate Left Doubleword then Clear Left */
5965 /* Rotate Left Doubleword then Clear Right */
5966 /* Rotate Left Doubleword Immediate then Mask Insert */
5968 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5969 record_full_arch_list_add_reg (regcache
,
5970 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5973 case 28: /* AND Immediate */
5974 case 29: /* AND Immediate Shifted */
5975 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5977 case 24: /* OR Immediate */
5978 case 25: /* OR Immediate Shifted */
5979 case 26: /* XOR Immediate */
5980 case 27: /* XOR Immediate Shifted */
5981 record_full_arch_list_add_reg (regcache
,
5982 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5986 if (ppc_process_record_op31 (gdbarch
, regcache
, addr
, insn
) != 0)
5990 case 33: /* Load Word and Zero with Update */
5991 case 35: /* Load Byte and Zero with Update */
5992 case 41: /* Load Halfword and Zero with Update */
5993 case 43: /* Load Halfword Algebraic with Update */
5994 record_full_arch_list_add_reg (regcache
,
5995 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5997 case 32: /* Load Word and Zero */
5998 case 34: /* Load Byte and Zero */
5999 case 40: /* Load Halfword and Zero */
6000 case 42: /* Load Halfword Algebraic */
6001 record_full_arch_list_add_reg (regcache
,
6002 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
6005 case 46: /* Load Multiple Word */
6006 for (i
= PPC_RT (insn
); i
< 32; i
++)
6007 record_full_arch_list_add_reg (regcache
, tdep
->ppc_gp0_regnum
+ i
);
6010 case 56: /* Load Quadword */
6011 tmp
= tdep
->ppc_gp0_regnum
+ (PPC_RT (insn
) & ~1);
6012 record_full_arch_list_add_reg (regcache
, tmp
);
6013 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
6016 case 49: /* Load Floating-Point Single with Update */
6017 case 51: /* Load Floating-Point Double with Update */
6018 record_full_arch_list_add_reg (regcache
,
6019 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
6021 case 48: /* Load Floating-Point Single */
6022 case 50: /* Load Floating-Point Double */
6023 record_full_arch_list_add_reg (regcache
,
6024 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
6027 case 47: /* Store Multiple Word */
6031 if (PPC_RA (insn
) != 0)
6032 regcache_raw_read_unsigned (regcache
,
6033 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
6036 iaddr
+= PPC_D (insn
);
6037 record_full_arch_list_add_mem (iaddr
, 4 * (32 - PPC_RS (insn
)));
6041 case 37: /* Store Word with Update */
6042 case 39: /* Store Byte with Update */
6043 case 45: /* Store Halfword with Update */
6044 case 53: /* Store Floating-Point Single with Update */
6045 case 55: /* Store Floating-Point Double with Update */
6046 record_full_arch_list_add_reg (regcache
,
6047 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
6049 case 36: /* Store Word */
6050 case 38: /* Store Byte */
6051 case 44: /* Store Halfword */
6052 case 52: /* Store Floating-Point Single */
6053 case 54: /* Store Floating-Point Double */
6058 if (PPC_RA (insn
) != 0)
6059 regcache_raw_read_unsigned (regcache
,
6060 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
6062 iaddr
+= PPC_D (insn
);
6064 if (op6
== 36 || op6
== 37 || op6
== 52 || op6
== 53)
6066 else if (op6
== 54 || op6
== 55)
6068 else if (op6
== 44 || op6
== 45)
6070 else if (op6
== 38 || op6
== 39)
6075 record_full_arch_list_add_mem (iaddr
, size
);
6082 case 0: /* Load Floating-Point Double Pair */
6083 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_RT (insn
) & ~1);
6084 record_full_arch_list_add_reg (regcache
, tmp
);
6085 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
6087 case 2: /* Load VSX Scalar Doubleword */
6088 case 3: /* Load VSX Scalar Single */
6089 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
6096 case 58: /* Load Doubleword */
6097 /* Load Doubleword with Update */
6098 /* Load Word Algebraic */
6099 if (PPC_FIELD (insn
, 30, 2) > 2)
6102 record_full_arch_list_add_reg (regcache
,
6103 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
6104 if (PPC_BIT (insn
, 31))
6105 record_full_arch_list_add_reg (regcache
,
6106 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
6110 if (ppc_process_record_op59 (gdbarch
, regcache
, addr
, insn
) != 0)
6115 if (ppc_process_record_op60 (gdbarch
, regcache
, addr
, insn
) != 0)
6120 if (ppc_process_record_op61 (gdbarch
, regcache
, addr
, insn
) != 0)
6124 case 62: /* Store Doubleword */
6125 /* Store Doubleword with Update */
6126 /* Store Quadword with Update */
6130 int sub2
= PPC_FIELD (insn
, 30, 2);
6135 if (PPC_RA (insn
) != 0)
6136 regcache_raw_read_unsigned (regcache
,
6137 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
6140 size
= (sub2
== 2) ? 16 : 8;
6142 iaddr
+= PPC_DS (insn
) << 2;
6143 record_full_arch_list_add_mem (iaddr
, size
);
6145 if (op6
== 62 && sub2
== 1)
6146 record_full_arch_list_add_reg (regcache
,
6147 tdep
->ppc_gp0_regnum
+
6154 if (ppc_process_record_op63 (gdbarch
, regcache
, addr
, insn
) != 0)
6160 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
6161 "at %s, %d.\n", insn
, paddress (gdbarch
, addr
), op6
);
6165 if (record_full_arch_list_add_reg (regcache
, PPC_PC_REGNUM
))
6167 if (record_full_arch_list_add_end ())
6172 /* Initialize the current architecture based on INFO. If possible, re-use an
6173 architecture from ARCHES, which is a list of architectures already created
6174 during this debugging session.
6176 Called e.g. at program startup, when reading a core file, and when reading
6179 static struct gdbarch
*
6180 rs6000_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
6182 struct gdbarch
*gdbarch
;
6183 struct gdbarch_tdep
*tdep
;
6184 int wordsize
, from_xcoff_exec
, from_elf_exec
;
6185 enum bfd_architecture arch
;
6188 enum auto_boolean soft_float_flag
= powerpc_soft_float_global
;
6190 enum powerpc_long_double_abi long_double_abi
= POWERPC_LONG_DOUBLE_AUTO
;
6191 enum powerpc_vector_abi vector_abi
= powerpc_vector_abi_global
;
6192 enum powerpc_elf_abi elf_abi
= POWERPC_ELF_AUTO
;
6193 int have_fpu
= 0, have_spe
= 0, have_mq
= 0, have_altivec
= 0;
6194 int have_dfp
= 0, have_vsx
= 0, have_ppr
= 0, have_dscr
= 0;
6195 int have_tar
= 0, have_ebb
= 0, have_pmu
= 0, have_htm_spr
= 0;
6196 int have_htm_core
= 0, have_htm_fpu
= 0, have_htm_altivec
= 0;
6197 int have_htm_vsx
= 0, have_htm_ppr
= 0, have_htm_dscr
= 0;
6198 int have_htm_tar
= 0;
6199 int tdesc_wordsize
= -1;
6200 const struct target_desc
*tdesc
= info
.target_desc
;
6201 tdesc_arch_data_up tdesc_data
;
6202 int num_pseudoregs
= 0;
6205 from_xcoff_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
6206 bfd_get_flavour (info
.abfd
) == bfd_target_xcoff_flavour
;
6208 from_elf_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
6209 bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
;
6211 /* Check word size. If INFO is from a binary file, infer it from
6212 that, else choose a likely default. */
6213 if (from_xcoff_exec
)
6215 if (bfd_xcoff_is_xcoff64 (info
.abfd
))
6220 else if (from_elf_exec
)
6222 if (elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
6227 else if (tdesc_has_registers (tdesc
))
6231 if (info
.bfd_arch_info
!= NULL
&& info
.bfd_arch_info
->bits_per_word
!= 0)
6232 wordsize
= (info
.bfd_arch_info
->bits_per_word
6233 / info
.bfd_arch_info
->bits_per_byte
);
6238 /* Get the architecture and machine from the BFD. */
6239 arch
= info
.bfd_arch_info
->arch
;
6240 mach
= info
.bfd_arch_info
->mach
;
6242 /* For e500 executables, the apuinfo section is of help here. Such
6243 section contains the identifier and revision number of each
6244 Application-specific Processing Unit that is present on the
6245 chip. The content of the section is determined by the assembler
6246 which looks at each instruction and determines which unit (and
6247 which version of it) can execute it. Grovel through the section
6248 looking for relevant e500 APUs. */
6250 if (bfd_uses_spe_extensions (info
.abfd
))
6252 arch
= info
.bfd_arch_info
->arch
;
6253 mach
= bfd_mach_ppc_e500
;
6254 bfd_default_set_arch_mach (&abfd
, arch
, mach
);
6255 info
.bfd_arch_info
= bfd_get_arch_info (&abfd
);
6258 /* Find a default target description which describes our register
6259 layout, if we do not already have one. */
6260 if (! tdesc_has_registers (tdesc
))
6262 const struct ppc_variant
*v
;
6264 /* Choose variant. */
6265 v
= find_variant_by_arch (arch
, mach
);
6272 gdb_assert (tdesc_has_registers (tdesc
));
6274 /* Check any target description for validity. */
6275 if (tdesc_has_registers (tdesc
))
6277 static const char *const gprs
[] = {
6278 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6279 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
6280 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
6281 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
6283 const struct tdesc_feature
*feature
;
6285 static const char *const msr_names
[] = { "msr", "ps" };
6286 static const char *const cr_names
[] = { "cr", "cnd" };
6287 static const char *const ctr_names
[] = { "ctr", "cnt" };
6289 feature
= tdesc_find_feature (tdesc
,
6290 "org.gnu.gdb.power.core");
6291 if (feature
== NULL
)
6294 tdesc_data
= tdesc_data_alloc ();
6297 for (i
= 0; i
< ppc_num_gprs
; i
++)
6298 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6300 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6301 PPC_PC_REGNUM
, "pc");
6302 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6303 PPC_LR_REGNUM
, "lr");
6304 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6305 PPC_XER_REGNUM
, "xer");
6307 /* Allow alternate names for these registers, to accomodate GDB's
6309 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
.get (),
6310 PPC_MSR_REGNUM
, msr_names
);
6311 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
.get (),
6312 PPC_CR_REGNUM
, cr_names
);
6313 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
.get (),
6314 PPC_CTR_REGNUM
, ctr_names
);
6319 have_mq
= tdesc_numbered_register (feature
, tdesc_data
.get (),
6320 PPC_MQ_REGNUM
, "mq");
6322 tdesc_wordsize
= tdesc_register_bitsize (feature
, "pc") / 8;
6324 wordsize
= tdesc_wordsize
;
6326 feature
= tdesc_find_feature (tdesc
,
6327 "org.gnu.gdb.power.fpu");
6328 if (feature
!= NULL
)
6330 static const char *const fprs
[] = {
6331 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
6332 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
6333 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
6334 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
6337 for (i
= 0; i
< ppc_num_fprs
; i
++)
6338 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6339 PPC_F0_REGNUM
+ i
, fprs
[i
]);
6340 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6341 PPC_FPSCR_REGNUM
, "fpscr");
6347 /* The fpscr register was expanded in isa 2.05 to 64 bits
6348 along with the addition of the decimal floating point
6350 if (tdesc_register_bitsize (feature
, "fpscr") > 32)
6356 feature
= tdesc_find_feature (tdesc
,
6357 "org.gnu.gdb.power.altivec");
6358 if (feature
!= NULL
)
6360 static const char *const vector_regs
[] = {
6361 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7",
6362 "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15",
6363 "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23",
6364 "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31"
6368 for (i
= 0; i
< ppc_num_gprs
; i
++)
6369 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6372 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6373 PPC_VSCR_REGNUM
, "vscr");
6374 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6375 PPC_VRSAVE_REGNUM
, "vrsave");
6377 if (have_spe
|| !valid_p
)
6384 /* Check for POWER7 VSX registers support. */
6385 feature
= tdesc_find_feature (tdesc
,
6386 "org.gnu.gdb.power.vsx");
6388 if (feature
!= NULL
)
6390 static const char *const vsx_regs
[] = {
6391 "vs0h", "vs1h", "vs2h", "vs3h", "vs4h", "vs5h",
6392 "vs6h", "vs7h", "vs8h", "vs9h", "vs10h", "vs11h",
6393 "vs12h", "vs13h", "vs14h", "vs15h", "vs16h", "vs17h",
6394 "vs18h", "vs19h", "vs20h", "vs21h", "vs22h", "vs23h",
6395 "vs24h", "vs25h", "vs26h", "vs27h", "vs28h", "vs29h",
6401 for (i
= 0; i
< ppc_num_vshrs
; i
++)
6402 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6403 PPC_VSR0_UPPER_REGNUM
+ i
,
6406 if (!valid_p
|| !have_fpu
|| !have_altivec
)
6414 /* On machines supporting the SPE APU, the general-purpose registers
6415 are 64 bits long. There are SIMD vector instructions to treat them
6416 as pairs of floats, but the rest of the instruction set treats them
6417 as 32-bit registers, and only operates on their lower halves.
6419 In the GDB regcache, we treat their high and low halves as separate
6420 registers. The low halves we present as the general-purpose
6421 registers, and then we have pseudo-registers that stitch together
6422 the upper and lower halves and present them as pseudo-registers.
6424 Thus, the target description is expected to supply the upper
6425 halves separately. */
6427 feature
= tdesc_find_feature (tdesc
,
6428 "org.gnu.gdb.power.spe");
6429 if (feature
!= NULL
)
6431 static const char *const upper_spe
[] = {
6432 "ev0h", "ev1h", "ev2h", "ev3h",
6433 "ev4h", "ev5h", "ev6h", "ev7h",
6434 "ev8h", "ev9h", "ev10h", "ev11h",
6435 "ev12h", "ev13h", "ev14h", "ev15h",
6436 "ev16h", "ev17h", "ev18h", "ev19h",
6437 "ev20h", "ev21h", "ev22h", "ev23h",
6438 "ev24h", "ev25h", "ev26h", "ev27h",
6439 "ev28h", "ev29h", "ev30h", "ev31h"
6443 for (i
= 0; i
< ppc_num_gprs
; i
++)
6444 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6445 PPC_SPE_UPPER_GP0_REGNUM
+ i
,
6447 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6448 PPC_SPE_ACC_REGNUM
, "acc");
6449 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6450 PPC_SPE_FSCR_REGNUM
, "spefscr");
6452 if (have_mq
|| have_fpu
|| !valid_p
)
6459 /* Program Priority Register. */
6460 feature
= tdesc_find_feature (tdesc
,
6461 "org.gnu.gdb.power.ppr");
6462 if (feature
!= NULL
)
6465 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6466 PPC_PPR_REGNUM
, "ppr");
6475 /* Data Stream Control Register. */
6476 feature
= tdesc_find_feature (tdesc
,
6477 "org.gnu.gdb.power.dscr");
6478 if (feature
!= NULL
)
6481 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6482 PPC_DSCR_REGNUM
, "dscr");
6491 /* Target Address Register. */
6492 feature
= tdesc_find_feature (tdesc
,
6493 "org.gnu.gdb.power.tar");
6494 if (feature
!= NULL
)
6497 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6498 PPC_TAR_REGNUM
, "tar");
6507 /* Event-based Branching Registers. */
6508 feature
= tdesc_find_feature (tdesc
,
6509 "org.gnu.gdb.power.ebb");
6510 if (feature
!= NULL
)
6512 static const char *const ebb_regs
[] = {
6513 "bescr", "ebbhr", "ebbrr"
6517 for (i
= 0; i
< ARRAY_SIZE (ebb_regs
); i
++)
6518 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6519 PPC_BESCR_REGNUM
+ i
,
6528 /* Subset of the ISA 2.07 Performance Monitor Registers provided
6530 feature
= tdesc_find_feature (tdesc
,
6531 "org.gnu.gdb.power.linux.pmu");
6532 if (feature
!= NULL
)
6536 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6539 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6542 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6545 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6548 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6559 /* Hardware Transactional Memory Registers. */
6560 feature
= tdesc_find_feature (tdesc
,
6561 "org.gnu.gdb.power.htm.spr");
6562 if (feature
!= NULL
)
6564 static const char *const tm_spr_regs
[] = {
6565 "tfhar", "texasr", "tfiar"
6569 for (i
= 0; i
< ARRAY_SIZE (tm_spr_regs
); i
++)
6570 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6571 PPC_TFHAR_REGNUM
+ i
,
6581 feature
= tdesc_find_feature (tdesc
,
6582 "org.gnu.gdb.power.htm.core");
6583 if (feature
!= NULL
)
6585 static const char *const cgprs
[] = {
6586 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
6587 "cr8", "cr9", "cr10", "cr11", "cr12", "cr13", "cr14",
6588 "cr15", "cr16", "cr17", "cr18", "cr19", "cr20", "cr21",
6589 "cr22", "cr23", "cr24", "cr25", "cr26", "cr27", "cr28",
6590 "cr29", "cr30", "cr31", "ccr", "cxer", "clr", "cctr"
6595 for (i
= 0; i
< ARRAY_SIZE (cgprs
); i
++)
6596 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6607 feature
= tdesc_find_feature (tdesc
,
6608 "org.gnu.gdb.power.htm.fpu");
6609 if (feature
!= NULL
)
6613 static const char *const cfprs
[] = {
6614 "cf0", "cf1", "cf2", "cf3", "cf4", "cf5", "cf6", "cf7",
6615 "cf8", "cf9", "cf10", "cf11", "cf12", "cf13", "cf14", "cf15",
6616 "cf16", "cf17", "cf18", "cf19", "cf20", "cf21", "cf22",
6617 "cf23", "cf24", "cf25", "cf26", "cf27", "cf28", "cf29",
6618 "cf30", "cf31", "cfpscr"
6621 for (i
= 0; i
< ARRAY_SIZE (cfprs
); i
++)
6622 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6633 feature
= tdesc_find_feature (tdesc
,
6634 "org.gnu.gdb.power.htm.altivec");
6635 if (feature
!= NULL
)
6639 static const char *const cvmx
[] = {
6640 "cvr0", "cvr1", "cvr2", "cvr3", "cvr4", "cvr5", "cvr6",
6641 "cvr7", "cvr8", "cvr9", "cvr10", "cvr11", "cvr12", "cvr13",
6642 "cvr14", "cvr15","cvr16", "cvr17", "cvr18", "cvr19", "cvr20",
6643 "cvr21", "cvr22", "cvr23", "cvr24", "cvr25", "cvr26",
6644 "cvr27", "cvr28", "cvr29", "cvr30", "cvr31", "cvscr",
6648 for (i
= 0; i
< ARRAY_SIZE (cvmx
); i
++)
6649 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6650 PPC_CVR0_REGNUM
+ i
,
6655 have_htm_altivec
= 1;
6658 have_htm_altivec
= 0;
6660 feature
= tdesc_find_feature (tdesc
,
6661 "org.gnu.gdb.power.htm.vsx");
6662 if (feature
!= NULL
)
6666 static const char *const cvsx
[] = {
6667 "cvs0h", "cvs1h", "cvs2h", "cvs3h", "cvs4h", "cvs5h",
6668 "cvs6h", "cvs7h", "cvs8h", "cvs9h", "cvs10h", "cvs11h",
6669 "cvs12h", "cvs13h", "cvs14h", "cvs15h", "cvs16h", "cvs17h",
6670 "cvs18h", "cvs19h", "cvs20h", "cvs21h", "cvs22h", "cvs23h",
6671 "cvs24h", "cvs25h", "cvs26h", "cvs27h", "cvs28h", "cvs29h",
6675 for (i
= 0; i
< ARRAY_SIZE (cvsx
); i
++)
6676 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6677 (PPC_CVSR0_UPPER_REGNUM
6681 if (!valid_p
|| !have_htm_fpu
|| !have_htm_altivec
)
6688 feature
= tdesc_find_feature (tdesc
,
6689 "org.gnu.gdb.power.htm.ppr");
6690 if (feature
!= NULL
)
6692 valid_p
= tdesc_numbered_register (feature
, tdesc_data
.get (),
6693 PPC_CPPR_REGNUM
, "cppr");
6702 feature
= tdesc_find_feature (tdesc
,
6703 "org.gnu.gdb.power.htm.dscr");
6704 if (feature
!= NULL
)
6706 valid_p
= tdesc_numbered_register (feature
, tdesc_data
.get (),
6707 PPC_CDSCR_REGNUM
, "cdscr");
6716 feature
= tdesc_find_feature (tdesc
,
6717 "org.gnu.gdb.power.htm.tar");
6718 if (feature
!= NULL
)
6720 valid_p
= tdesc_numbered_register (feature
, tdesc_data
.get (),
6721 PPC_CTAR_REGNUM
, "ctar");
6731 /* If we have a 64-bit binary on a 32-bit target, complain. Also
6732 complain for a 32-bit binary on a 64-bit target; we do not yet
6733 support that. For instance, the 32-bit ABI routines expect
6736 As long as there isn't an explicit target description, we'll
6737 choose one based on the BFD architecture and get a word size
6738 matching the binary (probably powerpc:common or
6739 powerpc:common64). So there is only trouble if a 64-bit target
6740 supplies a 64-bit description while debugging a 32-bit
6742 if (tdesc_wordsize
!= -1 && tdesc_wordsize
!= wordsize
)
6748 switch (elf_elfheader (info
.abfd
)->e_flags
& EF_PPC64_ABI
)
6751 elf_abi
= POWERPC_ELF_V1
;
6754 elf_abi
= POWERPC_ELF_V2
;
6761 if (soft_float_flag
== AUTO_BOOLEAN_AUTO
&& from_elf_exec
)
6763 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
6764 Tag_GNU_Power_ABI_FP
) & 3)
6767 soft_float_flag
= AUTO_BOOLEAN_FALSE
;
6770 soft_float_flag
= AUTO_BOOLEAN_TRUE
;
6777 if (long_double_abi
== POWERPC_LONG_DOUBLE_AUTO
&& from_elf_exec
)
6779 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
6780 Tag_GNU_Power_ABI_FP
) >> 2)
6783 long_double_abi
= POWERPC_LONG_DOUBLE_IBM128
;
6786 long_double_abi
= POWERPC_LONG_DOUBLE_IEEE128
;
6793 if (vector_abi
== POWERPC_VEC_AUTO
&& from_elf_exec
)
6795 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
6796 Tag_GNU_Power_ABI_Vector
))
6799 vector_abi
= POWERPC_VEC_GENERIC
;
6802 vector_abi
= POWERPC_VEC_ALTIVEC
;
6805 vector_abi
= POWERPC_VEC_SPE
;
6813 /* At this point, the only supported ELF-based 64-bit little-endian
6814 operating system is GNU/Linux, and this uses the ELFv2 ABI by
6815 default. All other supported ELF-based operating systems use the
6816 ELFv1 ABI by default. Therefore, if the ABI marker is missing,
6817 e.g. because we run a legacy binary, or have attached to a process
6818 and have not found any associated binary file, set the default
6819 according to this heuristic. */
6820 if (elf_abi
== POWERPC_ELF_AUTO
)
6822 if (wordsize
== 8 && info
.byte_order
== BFD_ENDIAN_LITTLE
)
6823 elf_abi
= POWERPC_ELF_V2
;
6825 elf_abi
= POWERPC_ELF_V1
;
6828 if (soft_float_flag
== AUTO_BOOLEAN_TRUE
)
6830 else if (soft_float_flag
== AUTO_BOOLEAN_FALSE
)
6833 soft_float
= !have_fpu
;
6835 /* If we have a hard float binary or setting but no floating point
6836 registers, downgrade to soft float anyway. We're still somewhat
6837 useful in this scenario. */
6838 if (!soft_float
&& !have_fpu
)
6841 /* Similarly for vector registers. */
6842 if (vector_abi
== POWERPC_VEC_ALTIVEC
&& !have_altivec
)
6843 vector_abi
= POWERPC_VEC_GENERIC
;
6845 if (vector_abi
== POWERPC_VEC_SPE
&& !have_spe
)
6846 vector_abi
= POWERPC_VEC_GENERIC
;
6848 if (vector_abi
== POWERPC_VEC_AUTO
)
6851 vector_abi
= POWERPC_VEC_ALTIVEC
;
6853 vector_abi
= POWERPC_VEC_SPE
;
6855 vector_abi
= POWERPC_VEC_GENERIC
;
6858 /* Do not limit the vector ABI based on available hardware, since we
6859 do not yet know what hardware we'll decide we have. Yuck! FIXME! */
6861 /* Find a candidate among extant architectures. */
6862 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
6864 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
6866 /* Word size in the various PowerPC bfd_arch_info structs isn't
6867 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
6868 separate word size check. */
6869 tdep
= gdbarch_tdep (arches
->gdbarch
);
6870 if (tdep
&& tdep
->elf_abi
!= elf_abi
)
6872 if (tdep
&& tdep
->soft_float
!= soft_float
)
6874 if (tdep
&& tdep
->long_double_abi
!= long_double_abi
)
6876 if (tdep
&& tdep
->vector_abi
!= vector_abi
)
6878 if (tdep
&& tdep
->wordsize
== wordsize
)
6879 return arches
->gdbarch
;
6882 /* None found, create a new architecture from INFO, whose bfd_arch_info
6883 validity depends on the source:
6884 - executable useless
6885 - rs6000_host_arch() good
6887 - "set arch" trust blindly
6888 - GDB startup useless but harmless */
6890 tdep
= XCNEW (struct gdbarch_tdep
);
6891 tdep
->wordsize
= wordsize
;
6892 tdep
->elf_abi
= elf_abi
;
6893 tdep
->soft_float
= soft_float
;
6894 tdep
->long_double_abi
= long_double_abi
;
6895 tdep
->vector_abi
= vector_abi
;
6897 gdbarch
= gdbarch_alloc (&info
, tdep
);
6899 tdep
->ppc_gp0_regnum
= PPC_R0_REGNUM
;
6900 tdep
->ppc_toc_regnum
= PPC_R0_REGNUM
+ 2;
6901 tdep
->ppc_ps_regnum
= PPC_MSR_REGNUM
;
6902 tdep
->ppc_cr_regnum
= PPC_CR_REGNUM
;
6903 tdep
->ppc_lr_regnum
= PPC_LR_REGNUM
;
6904 tdep
->ppc_ctr_regnum
= PPC_CTR_REGNUM
;
6905 tdep
->ppc_xer_regnum
= PPC_XER_REGNUM
;
6906 tdep
->ppc_mq_regnum
= have_mq
? PPC_MQ_REGNUM
: -1;
6908 tdep
->ppc_fp0_regnum
= have_fpu
? PPC_F0_REGNUM
: -1;
6909 tdep
->ppc_fpscr_regnum
= have_fpu
? PPC_FPSCR_REGNUM
: -1;
6910 tdep
->ppc_vsr0_upper_regnum
= have_vsx
? PPC_VSR0_UPPER_REGNUM
: -1;
6911 tdep
->ppc_vr0_regnum
= have_altivec
? PPC_VR0_REGNUM
: -1;
6912 tdep
->ppc_vrsave_regnum
= have_altivec
? PPC_VRSAVE_REGNUM
: -1;
6913 tdep
->ppc_ev0_upper_regnum
= have_spe
? PPC_SPE_UPPER_GP0_REGNUM
: -1;
6914 tdep
->ppc_acc_regnum
= have_spe
? PPC_SPE_ACC_REGNUM
: -1;
6915 tdep
->ppc_spefscr_regnum
= have_spe
? PPC_SPE_FSCR_REGNUM
: -1;
6916 tdep
->ppc_ppr_regnum
= have_ppr
? PPC_PPR_REGNUM
: -1;
6917 tdep
->ppc_dscr_regnum
= have_dscr
? PPC_DSCR_REGNUM
: -1;
6918 tdep
->ppc_tar_regnum
= have_tar
? PPC_TAR_REGNUM
: -1;
6919 tdep
->have_ebb
= have_ebb
;
6921 /* If additional pmu registers are added, care must be taken when
6922 setting new fields in the tdep below, to maintain compatibility
6923 with features that only provide some of the registers. Currently
6924 gdb access to the pmu registers is only supported in linux, and
6925 linux only provides a subset of the pmu registers defined in the
6928 tdep
->ppc_mmcr0_regnum
= have_pmu
? PPC_MMCR0_REGNUM
: -1;
6929 tdep
->ppc_mmcr2_regnum
= have_pmu
? PPC_MMCR2_REGNUM
: -1;
6930 tdep
->ppc_siar_regnum
= have_pmu
? PPC_SIAR_REGNUM
: -1;
6931 tdep
->ppc_sdar_regnum
= have_pmu
? PPC_SDAR_REGNUM
: -1;
6932 tdep
->ppc_sier_regnum
= have_pmu
? PPC_SIER_REGNUM
: -1;
6934 tdep
->have_htm_spr
= have_htm_spr
;
6935 tdep
->have_htm_core
= have_htm_core
;
6936 tdep
->have_htm_fpu
= have_htm_fpu
;
6937 tdep
->have_htm_altivec
= have_htm_altivec
;
6938 tdep
->have_htm_vsx
= have_htm_vsx
;
6939 tdep
->ppc_cppr_regnum
= have_htm_ppr
? PPC_CPPR_REGNUM
: -1;
6940 tdep
->ppc_cdscr_regnum
= have_htm_dscr
? PPC_CDSCR_REGNUM
: -1;
6941 tdep
->ppc_ctar_regnum
= have_htm_tar
? PPC_CTAR_REGNUM
: -1;
6943 set_gdbarch_pc_regnum (gdbarch
, PPC_PC_REGNUM
);
6944 set_gdbarch_sp_regnum (gdbarch
, PPC_R0_REGNUM
+ 1);
6945 set_gdbarch_fp0_regnum (gdbarch
, tdep
->ppc_fp0_regnum
);
6946 set_gdbarch_register_sim_regno (gdbarch
, rs6000_register_sim_regno
);
6948 /* The XML specification for PowerPC sensibly calls the MSR "msr".
6949 GDB traditionally called it "ps", though, so let GDB add an
6951 set_gdbarch_ps_regnum (gdbarch
, tdep
->ppc_ps_regnum
);
6954 set_gdbarch_return_value (gdbarch
, ppc64_sysv_abi_return_value
);
6956 set_gdbarch_return_value (gdbarch
, ppc_sysv_abi_return_value
);
6958 /* Set lr_frame_offset. */
6960 tdep
->lr_frame_offset
= 16;
6962 tdep
->lr_frame_offset
= 4;
6964 if (have_spe
|| have_dfp
|| have_altivec
6965 || have_vsx
|| have_htm_fpu
|| have_htm_vsx
)
6967 set_gdbarch_pseudo_register_read (gdbarch
, rs6000_pseudo_register_read
);
6968 set_gdbarch_pseudo_register_write (gdbarch
,
6969 rs6000_pseudo_register_write
);
6970 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
6971 rs6000_ax_pseudo_register_collect
);
6974 set_gdbarch_gen_return_address (gdbarch
, rs6000_gen_return_address
);
6976 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
6978 set_gdbarch_num_regs (gdbarch
, PPC_NUM_REGS
);
6981 num_pseudoregs
+= 32;
6983 num_pseudoregs
+= 16;
6985 num_pseudoregs
+= 32;
6987 /* Include both VSX and Extended FP registers. */
6988 num_pseudoregs
+= 96;
6990 num_pseudoregs
+= 16;
6991 /* Include both checkpointed VSX and EFP registers. */
6993 num_pseudoregs
+= 64 + 32;
6995 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudoregs
);
6997 set_gdbarch_ptr_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
6998 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
6999 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
7000 set_gdbarch_long_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
7001 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
7002 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
7003 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
7004 set_gdbarch_long_double_bit (gdbarch
, 16 * TARGET_CHAR_BIT
);
7005 set_gdbarch_char_signed (gdbarch
, 0);
7007 set_gdbarch_frame_align (gdbarch
, rs6000_frame_align
);
7010 set_gdbarch_frame_red_zone_size (gdbarch
, 288);
7012 set_gdbarch_convert_register_p (gdbarch
, rs6000_convert_register_p
);
7013 set_gdbarch_register_to_value (gdbarch
, rs6000_register_to_value
);
7014 set_gdbarch_value_to_register (gdbarch
, rs6000_value_to_register
);
7016 set_gdbarch_stab_reg_to_regnum (gdbarch
, rs6000_stab_reg_to_regnum
);
7017 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, rs6000_dwarf2_reg_to_regnum
);
7020 set_gdbarch_push_dummy_call (gdbarch
, ppc_sysv_abi_push_dummy_call
);
7021 else if (wordsize
== 8)
7022 set_gdbarch_push_dummy_call (gdbarch
, ppc64_sysv_abi_push_dummy_call
);
7024 set_gdbarch_skip_prologue (gdbarch
, rs6000_skip_prologue
);
7025 set_gdbarch_stack_frame_destroyed_p (gdbarch
, rs6000_stack_frame_destroyed_p
);
7026 set_gdbarch_skip_main_prologue (gdbarch
, rs6000_skip_main_prologue
);
7028 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
7030 set_gdbarch_breakpoint_kind_from_pc (gdbarch
,
7031 rs6000_breakpoint::kind_from_pc
);
7032 set_gdbarch_sw_breakpoint_from_kind (gdbarch
,
7033 rs6000_breakpoint::bp_from_kind
);
7035 /* The value of symbols of type N_SO and N_FUN maybe null when
7037 set_gdbarch_sofun_address_maybe_missing (gdbarch
, 1);
7039 /* Handles single stepping of atomic sequences. */
7040 set_gdbarch_software_single_step (gdbarch
, ppc_deal_with_atomic_sequence
);
7042 /* Not sure on this. FIXMEmgo */
7043 set_gdbarch_frame_args_skip (gdbarch
, 8);
7045 /* Helpers for function argument information. */
7046 set_gdbarch_fetch_pointer_argument (gdbarch
, rs6000_fetch_pointer_argument
);
7049 set_gdbarch_in_solib_return_trampoline
7050 (gdbarch
, rs6000_in_solib_return_trampoline
);
7051 set_gdbarch_skip_trampoline_code (gdbarch
, rs6000_skip_trampoline_code
);
7053 /* Hook in the DWARF CFI frame unwinder. */
7054 dwarf2_append_unwinders (gdbarch
);
7055 dwarf2_frame_set_adjust_regnum (gdbarch
, rs6000_adjust_frame_regnum
);
7057 /* Frame handling. */
7058 dwarf2_frame_set_init_reg (gdbarch
, ppc_dwarf2_frame_init_reg
);
7060 /* Setup displaced stepping. */
7061 set_gdbarch_displaced_step_copy_insn (gdbarch
,
7062 ppc_displaced_step_copy_insn
);
7063 set_gdbarch_displaced_step_hw_singlestep (gdbarch
,
7064 ppc_displaced_step_hw_singlestep
);
7065 set_gdbarch_displaced_step_fixup (gdbarch
, ppc_displaced_step_fixup
);
7066 set_gdbarch_displaced_step_prepare (gdbarch
, ppc_displaced_step_prepare
);
7067 set_gdbarch_displaced_step_finish (gdbarch
, ppc_displaced_step_finish
);
7068 set_gdbarch_displaced_step_restore_all_in_ptid
7069 (gdbarch
, ppc_displaced_step_restore_all_in_ptid
);
7071 set_gdbarch_max_insn_length (gdbarch
, PPC_INSN_SIZE
);
7073 /* Hook in ABI-specific overrides, if they have been registered. */
7074 info
.target_desc
= tdesc
;
7075 info
.tdesc_data
= tdesc_data
.get ();
7076 gdbarch_init_osabi (info
, gdbarch
);
7080 case GDB_OSABI_LINUX
:
7081 case GDB_OSABI_NETBSD
:
7082 case GDB_OSABI_UNKNOWN
:
7083 frame_unwind_append_unwinder (gdbarch
, &rs6000_epilogue_frame_unwind
);
7084 frame_unwind_append_unwinder (gdbarch
, &rs6000_frame_unwind
);
7085 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
7088 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
7090 frame_unwind_append_unwinder (gdbarch
, &rs6000_epilogue_frame_unwind
);
7091 frame_unwind_append_unwinder (gdbarch
, &rs6000_frame_unwind
);
7092 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
7095 set_tdesc_pseudo_register_type (gdbarch
, rs6000_pseudo_register_type
);
7096 set_tdesc_pseudo_register_reggroup_p (gdbarch
,
7097 rs6000_pseudo_register_reggroup_p
);
7098 tdesc_use_registers (gdbarch
, tdesc
, std::move (tdesc_data
));
7100 /* Override the normal target description method to make the SPE upper
7101 halves anonymous. */
7102 set_gdbarch_register_name (gdbarch
, rs6000_register_name
);
7104 /* Choose register numbers for all supported pseudo-registers. */
7105 tdep
->ppc_ev0_regnum
= -1;
7106 tdep
->ppc_dl0_regnum
= -1;
7107 tdep
->ppc_v0_alias_regnum
= -1;
7108 tdep
->ppc_vsr0_regnum
= -1;
7109 tdep
->ppc_efpr0_regnum
= -1;
7110 tdep
->ppc_cdl0_regnum
= -1;
7111 tdep
->ppc_cvsr0_regnum
= -1;
7112 tdep
->ppc_cefpr0_regnum
= -1;
7114 cur_reg
= gdbarch_num_regs (gdbarch
);
7118 tdep
->ppc_ev0_regnum
= cur_reg
;
7123 tdep
->ppc_dl0_regnum
= cur_reg
;
7128 tdep
->ppc_v0_alias_regnum
= cur_reg
;
7133 tdep
->ppc_vsr0_regnum
= cur_reg
;
7135 tdep
->ppc_efpr0_regnum
= cur_reg
;
7140 tdep
->ppc_cdl0_regnum
= cur_reg
;
7145 tdep
->ppc_cvsr0_regnum
= cur_reg
;
7147 tdep
->ppc_cefpr0_regnum
= cur_reg
;
7151 gdb_assert (gdbarch_num_cooked_regs (gdbarch
) == cur_reg
);
7153 /* Register the ravenscar_arch_ops. */
7154 if (mach
== bfd_mach_ppc_e500
)
7155 register_e500_ravenscar_ops (gdbarch
);
7157 register_ppc_ravenscar_ops (gdbarch
);
7159 set_gdbarch_disassembler_options (gdbarch
, &powerpc_disassembler_options
);
7160 set_gdbarch_valid_disassembler_options (gdbarch
,
7161 disassembler_options_powerpc ());
7167 rs6000_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
7169 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
7174 /* FIXME: Dump gdbarch_tdep. */
7178 powerpc_set_soft_float (const char *args
, int from_tty
,
7179 struct cmd_list_element
*c
)
7181 struct gdbarch_info info
;
7183 /* Update the architecture. */
7184 gdbarch_info_init (&info
);
7185 if (!gdbarch_update_p (info
))
7186 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
7190 powerpc_set_vector_abi (const char *args
, int from_tty
,
7191 struct cmd_list_element
*c
)
7193 struct gdbarch_info info
;
7196 for (vector_abi
= POWERPC_VEC_AUTO
;
7197 vector_abi
!= POWERPC_VEC_LAST
;
7199 if (strcmp (powerpc_vector_abi_string
,
7200 powerpc_vector_strings
[vector_abi
]) == 0)
7202 powerpc_vector_abi_global
= (enum powerpc_vector_abi
) vector_abi
;
7206 if (vector_abi
== POWERPC_VEC_LAST
)
7207 internal_error (__FILE__
, __LINE__
, _("Invalid vector ABI accepted: %s."),
7208 powerpc_vector_abi_string
);
7210 /* Update the architecture. */
7211 gdbarch_info_init (&info
);
7212 if (!gdbarch_update_p (info
))
7213 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
7216 /* Show the current setting of the exact watchpoints flag. */
7219 show_powerpc_exact_watchpoints (struct ui_file
*file
, int from_tty
,
7220 struct cmd_list_element
*c
,
7223 fprintf_filtered (file
, _("Use of exact watchpoints is %s.\n"), value
);
7226 /* Read a PPC instruction from memory. */
7229 read_insn (struct frame_info
*frame
, CORE_ADDR pc
)
7231 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7232 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7234 return read_memory_unsigned_integer (pc
, 4, byte_order
);
7237 /* Return non-zero if the instructions at PC match the series
7238 described in PATTERN, or zero otherwise. PATTERN is an array of
7239 'struct ppc_insn_pattern' objects, terminated by an entry whose
7242 When the match is successful, fill INSNS[i] with what PATTERN[i]
7243 matched. If PATTERN[i] is optional, and the instruction wasn't
7244 present, set INSNS[i] to 0 (which is not a valid PPC instruction).
7245 INSNS should have as many elements as PATTERN, minus the terminator.
7246 Note that, if PATTERN contains optional instructions which aren't
7247 present in memory, then INSNS will have holes, so INSNS[i] isn't
7248 necessarily the i'th instruction in memory. */
7251 ppc_insns_match_pattern (struct frame_info
*frame
, CORE_ADDR pc
,
7252 const struct ppc_insn_pattern
*pattern
,
7253 unsigned int *insns
)
7258 for (i
= 0, insn
= 0; pattern
[i
].mask
; i
++)
7261 insn
= read_insn (frame
, pc
);
7263 if ((insn
& pattern
[i
].mask
) == pattern
[i
].data
)
7269 else if (!pattern
[i
].optional
)
7276 /* Return the 'd' field of the d-form instruction INSN, properly
7280 ppc_insn_d_field (unsigned int insn
)
7282 return ((((CORE_ADDR
) insn
& 0xffff) ^ 0x8000) - 0x8000);
7285 /* Return the 'ds' field of the ds-form instruction INSN, with the two
7286 zero bits concatenated at the right, and properly
7290 ppc_insn_ds_field (unsigned int insn
)
7292 return ((((CORE_ADDR
) insn
& 0xfffc) ^ 0x8000) - 0x8000);
7295 /* Initialization code. */
7297 void _initialize_rs6000_tdep ();
7299 _initialize_rs6000_tdep ()
7301 gdbarch_register (bfd_arch_rs6000
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
7302 gdbarch_register (bfd_arch_powerpc
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
7304 /* Initialize the standard target descriptions. */
7305 initialize_tdesc_powerpc_32 ();
7306 initialize_tdesc_powerpc_altivec32 ();
7307 initialize_tdesc_powerpc_vsx32 ();
7308 initialize_tdesc_powerpc_403 ();
7309 initialize_tdesc_powerpc_403gc ();
7310 initialize_tdesc_powerpc_405 ();
7311 initialize_tdesc_powerpc_505 ();
7312 initialize_tdesc_powerpc_601 ();
7313 initialize_tdesc_powerpc_602 ();
7314 initialize_tdesc_powerpc_603 ();
7315 initialize_tdesc_powerpc_604 ();
7316 initialize_tdesc_powerpc_64 ();
7317 initialize_tdesc_powerpc_altivec64 ();
7318 initialize_tdesc_powerpc_vsx64 ();
7319 initialize_tdesc_powerpc_7400 ();
7320 initialize_tdesc_powerpc_750 ();
7321 initialize_tdesc_powerpc_860 ();
7322 initialize_tdesc_powerpc_e500 ();
7323 initialize_tdesc_rs6000 ();
7325 /* Add root prefix command for all "set powerpc"/"show powerpc"
7327 add_basic_prefix_cmd ("powerpc", no_class
,
7328 _("Various PowerPC-specific commands."),
7329 &setpowerpccmdlist
, "set powerpc ", 0, &setlist
);
7331 add_show_prefix_cmd ("powerpc", no_class
,
7332 _("Various PowerPC-specific commands."),
7333 &showpowerpccmdlist
, "show powerpc ", 0, &showlist
);
7335 /* Add a command to allow the user to force the ABI. */
7336 add_setshow_auto_boolean_cmd ("soft-float", class_support
,
7337 &powerpc_soft_float_global
,
7338 _("Set whether to use a soft-float ABI."),
7339 _("Show whether to use a soft-float ABI."),
7341 powerpc_set_soft_float
, NULL
,
7342 &setpowerpccmdlist
, &showpowerpccmdlist
);
7344 add_setshow_enum_cmd ("vector-abi", class_support
, powerpc_vector_strings
,
7345 &powerpc_vector_abi_string
,
7346 _("Set the vector ABI."),
7347 _("Show the vector ABI."),
7348 NULL
, powerpc_set_vector_abi
, NULL
,
7349 &setpowerpccmdlist
, &showpowerpccmdlist
);
7351 add_setshow_boolean_cmd ("exact-watchpoints", class_support
,
7352 &target_exact_watchpoints
,
7354 Set whether to use just one debug register for watchpoints on scalars."),
7356 Show whether to use just one debug register for watchpoints on scalars."),
7358 If true, GDB will use only one debug register when watching a variable of\n\
7359 scalar type, thus assuming that the variable is accessed through the address\n\
7360 of its first byte."),
7361 NULL
, show_powerpc_exact_watchpoints
,
7362 &setpowerpccmdlist
, &showpowerpccmdlist
);