1 /* Target-dependent code for GDB, the GNU debugger.
3 Copyright (C) 1986-2021 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
29 #include "arch-utils.h"
32 #include "target-float.h"
34 #include "parser-defs.h"
37 #include "sim-regno.h"
38 #include "gdb/sim-ppc.h"
39 #include "reggroups.h"
40 #include "dwarf2/frame.h"
41 #include "target-descriptions.h"
42 #include "user-regs.h"
43 #include "record-full.h"
46 #include "coff/internal.h" /* for libcoff.h */
47 #include "libcoff.h" /* for xcoff_data */
48 #include "coff/xcoff.h"
53 #include "elf/ppc64.h"
55 #include "solib-svr4.h"
57 #include "ppc-ravenscar-thread.h"
61 #include "trad-frame.h"
62 #include "frame-unwind.h"
63 #include "frame-base.h"
69 #include "features/rs6000/powerpc-32.c"
70 #include "features/rs6000/powerpc-altivec32.c"
71 #include "features/rs6000/powerpc-vsx32.c"
72 #include "features/rs6000/powerpc-403.c"
73 #include "features/rs6000/powerpc-403gc.c"
74 #include "features/rs6000/powerpc-405.c"
75 #include "features/rs6000/powerpc-505.c"
76 #include "features/rs6000/powerpc-601.c"
77 #include "features/rs6000/powerpc-602.c"
78 #include "features/rs6000/powerpc-603.c"
79 #include "features/rs6000/powerpc-604.c"
80 #include "features/rs6000/powerpc-64.c"
81 #include "features/rs6000/powerpc-altivec64.c"
82 #include "features/rs6000/powerpc-vsx64.c"
83 #include "features/rs6000/powerpc-7400.c"
84 #include "features/rs6000/powerpc-750.c"
85 #include "features/rs6000/powerpc-860.c"
86 #include "features/rs6000/powerpc-e500.c"
87 #include "features/rs6000/rs6000.c"
89 /* Determine if regnum is an SPE pseudo-register. */
90 #define IS_SPE_PSEUDOREG(tdep, regnum) ((tdep)->ppc_ev0_regnum >= 0 \
91 && (regnum) >= (tdep)->ppc_ev0_regnum \
92 && (regnum) < (tdep)->ppc_ev0_regnum + 32)
94 /* Determine if regnum is a decimal float pseudo-register. */
95 #define IS_DFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_dl0_regnum >= 0 \
96 && (regnum) >= (tdep)->ppc_dl0_regnum \
97 && (regnum) < (tdep)->ppc_dl0_regnum + 16)
99 /* Determine if regnum is a "vX" alias for the raw "vrX" vector
101 #define IS_V_ALIAS_PSEUDOREG(tdep, regnum) (\
102 (tdep)->ppc_v0_alias_regnum >= 0 \
103 && (regnum) >= (tdep)->ppc_v0_alias_regnum \
104 && (regnum) < (tdep)->ppc_v0_alias_regnum + ppc_num_vrs)
106 /* Determine if regnum is a POWER7 VSX register. */
107 #define IS_VSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_vsr0_regnum >= 0 \
108 && (regnum) >= (tdep)->ppc_vsr0_regnum \
109 && (regnum) < (tdep)->ppc_vsr0_regnum + ppc_num_vsrs)
111 /* Determine if regnum is a POWER7 Extended FP register. */
112 #define IS_EFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_efpr0_regnum >= 0 \
113 && (regnum) >= (tdep)->ppc_efpr0_regnum \
114 && (regnum) < (tdep)->ppc_efpr0_regnum + ppc_num_efprs)
116 /* Determine if regnum is a checkpointed decimal float
118 #define IS_CDFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_cdl0_regnum >= 0 \
119 && (regnum) >= (tdep)->ppc_cdl0_regnum \
120 && (regnum) < (tdep)->ppc_cdl0_regnum + 16)
122 /* Determine if regnum is a Checkpointed POWER7 VSX register. */
123 #define IS_CVSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_cvsr0_regnum >= 0 \
124 && (regnum) >= (tdep)->ppc_cvsr0_regnum \
125 && (regnum) < (tdep)->ppc_cvsr0_regnum + ppc_num_vsrs)
127 /* Determine if regnum is a Checkpointed POWER7 Extended FP register. */
128 #define IS_CEFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_cefpr0_regnum >= 0 \
129 && (regnum) >= (tdep)->ppc_cefpr0_regnum \
130 && (regnum) < (tdep)->ppc_cefpr0_regnum + ppc_num_efprs)
132 /* Holds the current set of options to be passed to the disassembler. */
133 static char *powerpc_disassembler_options
;
135 /* The list of available "set powerpc ..." and "show powerpc ..."
137 static struct cmd_list_element
*setpowerpccmdlist
= NULL
;
138 static struct cmd_list_element
*showpowerpccmdlist
= NULL
;
140 static enum auto_boolean powerpc_soft_float_global
= AUTO_BOOLEAN_AUTO
;
142 /* The vector ABI to use. Keep this in sync with powerpc_vector_abi. */
143 static const char *const powerpc_vector_strings
[] =
152 /* A variable that can be configured by the user. */
153 static enum powerpc_vector_abi powerpc_vector_abi_global
= POWERPC_VEC_AUTO
;
154 static const char *powerpc_vector_abi_string
= "auto";
156 /* PowerPC-related per-inferior data. */
158 static inferior_key
<ppc_inferior_data
> ppc_inferior_data_key
;
160 /* Get the per-inferior PowerPC data for INF. */
163 get_ppc_per_inferior (inferior
*inf
)
165 ppc_inferior_data
*per_inf
= ppc_inferior_data_key
.get (inf
);
167 if (per_inf
== nullptr)
168 per_inf
= ppc_inferior_data_key
.emplace (inf
);
173 /* To be used by skip_prologue. */
175 struct rs6000_framedata
177 int offset
; /* total size of frame --- the distance
178 by which we decrement sp to allocate
180 int saved_gpr
; /* smallest # of saved gpr */
181 unsigned int gpr_mask
; /* Each bit is an individual saved GPR. */
182 int saved_fpr
; /* smallest # of saved fpr */
183 int saved_vr
; /* smallest # of saved vr */
184 int saved_ev
; /* smallest # of saved ev */
185 int alloca_reg
; /* alloca register number (frame ptr) */
186 char frameless
; /* true if frameless functions. */
187 char nosavedpc
; /* true if pc not saved. */
188 char used_bl
; /* true if link register clobbered */
189 int gpr_offset
; /* offset of saved gprs from prev sp */
190 int fpr_offset
; /* offset of saved fprs from prev sp */
191 int vr_offset
; /* offset of saved vrs from prev sp */
192 int ev_offset
; /* offset of saved evs from prev sp */
193 int lr_offset
; /* offset of saved lr */
194 int lr_register
; /* register of saved lr, if trustworthy */
195 int cr_offset
; /* offset of saved cr */
196 int vrsave_offset
; /* offset of saved vrsave register */
200 /* Is REGNO a VSX register? Return 1 if so, 0 otherwise. */
202 vsx_register_p (struct gdbarch
*gdbarch
, int regno
)
204 ppc_gdbarch_tdep
*tdep
= (ppc_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
205 if (tdep
->ppc_vsr0_regnum
< 0)
208 return (regno
>= tdep
->ppc_vsr0_upper_regnum
&& regno
209 <= tdep
->ppc_vsr0_upper_regnum
+ 31);
212 /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
214 altivec_register_p (struct gdbarch
*gdbarch
, int regno
)
216 ppc_gdbarch_tdep
*tdep
= (ppc_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
217 if (tdep
->ppc_vr0_regnum
< 0 || tdep
->ppc_vrsave_regnum
< 0)
220 return (regno
>= tdep
->ppc_vr0_regnum
&& regno
<= tdep
->ppc_vrsave_regnum
);
224 /* Return true if REGNO is an SPE register, false otherwise. */
226 spe_register_p (struct gdbarch
*gdbarch
, int regno
)
228 ppc_gdbarch_tdep
*tdep
= (ppc_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
230 /* Is it a reference to EV0 -- EV31, and do we have those? */
231 if (IS_SPE_PSEUDOREG (tdep
, regno
))
234 /* Is it a reference to one of the raw upper GPR halves? */
235 if (tdep
->ppc_ev0_upper_regnum
>= 0
236 && tdep
->ppc_ev0_upper_regnum
<= regno
237 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
240 /* Is it a reference to the 64-bit accumulator, and do we have that? */
241 if (tdep
->ppc_acc_regnum
>= 0
242 && tdep
->ppc_acc_regnum
== regno
)
245 /* Is it a reference to the SPE floating-point status and control register,
246 and do we have that? */
247 if (tdep
->ppc_spefscr_regnum
>= 0
248 && tdep
->ppc_spefscr_regnum
== regno
)
255 /* Return non-zero if the architecture described by GDBARCH has
256 floating-point registers (f0 --- f31 and fpscr). */
258 ppc_floating_point_unit_p (struct gdbarch
*gdbarch
)
260 ppc_gdbarch_tdep
*tdep
= (ppc_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
262 return (tdep
->ppc_fp0_regnum
>= 0
263 && tdep
->ppc_fpscr_regnum
>= 0);
266 /* Return non-zero if the architecture described by GDBARCH has
267 Altivec registers (vr0 --- vr31, vrsave and vscr). */
269 ppc_altivec_support_p (struct gdbarch
*gdbarch
)
271 ppc_gdbarch_tdep
*tdep
= (ppc_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
273 return (tdep
->ppc_vr0_regnum
>= 0
274 && tdep
->ppc_vrsave_regnum
>= 0);
277 /* Check that TABLE[GDB_REGNO] is not already initialized, and then
280 This is a helper function for init_sim_regno_table, constructing
281 the table mapping GDB register numbers to sim register numbers; we
282 initialize every element in that table to -1 before we start
285 set_sim_regno (int *table
, int gdb_regno
, int sim_regno
)
287 /* Make sure we don't try to assign any given GDB register a sim
288 register number more than once. */
289 gdb_assert (table
[gdb_regno
] == -1);
290 table
[gdb_regno
] = sim_regno
;
294 /* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
295 numbers to simulator register numbers, based on the values placed
296 in the ARCH->tdep->ppc_foo_regnum members. */
298 init_sim_regno_table (struct gdbarch
*arch
)
300 ppc_gdbarch_tdep
*tdep
= (ppc_gdbarch_tdep
*) gdbarch_tdep (arch
);
301 int total_regs
= gdbarch_num_regs (arch
);
302 int *sim_regno
= GDBARCH_OBSTACK_CALLOC (arch
, total_regs
, int);
304 static const char *const segment_regs
[] = {
305 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
306 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
309 /* Presume that all registers not explicitly mentioned below are
310 unavailable from the sim. */
311 for (i
= 0; i
< total_regs
; i
++)
314 /* General-purpose registers. */
315 for (i
= 0; i
< ppc_num_gprs
; i
++)
316 set_sim_regno (sim_regno
, tdep
->ppc_gp0_regnum
+ i
, sim_ppc_r0_regnum
+ i
);
318 /* Floating-point registers. */
319 if (tdep
->ppc_fp0_regnum
>= 0)
320 for (i
= 0; i
< ppc_num_fprs
; i
++)
321 set_sim_regno (sim_regno
,
322 tdep
->ppc_fp0_regnum
+ i
,
323 sim_ppc_f0_regnum
+ i
);
324 if (tdep
->ppc_fpscr_regnum
>= 0)
325 set_sim_regno (sim_regno
, tdep
->ppc_fpscr_regnum
, sim_ppc_fpscr_regnum
);
327 set_sim_regno (sim_regno
, gdbarch_pc_regnum (arch
), sim_ppc_pc_regnum
);
328 set_sim_regno (sim_regno
, tdep
->ppc_ps_regnum
, sim_ppc_ps_regnum
);
329 set_sim_regno (sim_regno
, tdep
->ppc_cr_regnum
, sim_ppc_cr_regnum
);
331 /* Segment registers. */
332 for (i
= 0; i
< ppc_num_srs
; i
++)
336 gdb_regno
= user_reg_map_name_to_regnum (arch
, segment_regs
[i
], -1);
338 set_sim_regno (sim_regno
, gdb_regno
, sim_ppc_sr0_regnum
+ i
);
341 /* Altivec registers. */
342 if (tdep
->ppc_vr0_regnum
>= 0)
344 for (i
= 0; i
< ppc_num_vrs
; i
++)
345 set_sim_regno (sim_regno
,
346 tdep
->ppc_vr0_regnum
+ i
,
347 sim_ppc_vr0_regnum
+ i
);
349 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
350 we can treat this more like the other cases. */
351 set_sim_regno (sim_regno
,
352 tdep
->ppc_vr0_regnum
+ ppc_num_vrs
,
353 sim_ppc_vscr_regnum
);
355 /* vsave is a special-purpose register, so the code below handles it. */
357 /* SPE APU (E500) registers. */
358 if (tdep
->ppc_ev0_upper_regnum
>= 0)
359 for (i
= 0; i
< ppc_num_gprs
; i
++)
360 set_sim_regno (sim_regno
,
361 tdep
->ppc_ev0_upper_regnum
+ i
,
362 sim_ppc_rh0_regnum
+ i
);
363 if (tdep
->ppc_acc_regnum
>= 0)
364 set_sim_regno (sim_regno
, tdep
->ppc_acc_regnum
, sim_ppc_acc_regnum
);
365 /* spefscr is a special-purpose register, so the code below handles it. */
368 /* Now handle all special-purpose registers. Verify that they
369 haven't mistakenly been assigned numbers by any of the above
371 for (i
= 0; i
< sim_ppc_num_sprs
; i
++)
373 const char *spr_name
= sim_spr_register_name (i
);
376 if (spr_name
!= NULL
)
377 gdb_regno
= user_reg_map_name_to_regnum (arch
, spr_name
, -1);
380 set_sim_regno (sim_regno
, gdb_regno
, sim_ppc_spr0_regnum
+ i
);
384 /* Drop the initialized array into place. */
385 tdep
->sim_regno
= sim_regno
;
389 /* Given a GDB register number REG, return the corresponding SIM
392 rs6000_register_sim_regno (struct gdbarch
*gdbarch
, int reg
)
394 ppc_gdbarch_tdep
*tdep
= (ppc_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
397 if (tdep
->sim_regno
== NULL
)
398 init_sim_regno_table (gdbarch
);
400 gdb_assert (0 <= reg
&& reg
<= gdbarch_num_cooked_regs (gdbarch
));
401 sim_regno
= tdep
->sim_regno
[reg
];
406 return LEGACY_SIM_REGNO_IGNORE
;
411 /* Register set support functions. */
413 /* REGS + OFFSET contains register REGNUM in a field REGSIZE wide.
414 Write the register to REGCACHE. */
417 ppc_supply_reg (struct regcache
*regcache
, int regnum
,
418 const gdb_byte
*regs
, size_t offset
, int regsize
)
420 if (regnum
!= -1 && offset
!= -1)
424 struct gdbarch
*gdbarch
= regcache
->arch ();
425 int gdb_regsize
= register_size (gdbarch
, regnum
);
426 if (gdb_regsize
< regsize
427 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
428 offset
+= regsize
- gdb_regsize
;
430 regcache
->raw_supply (regnum
, regs
+ offset
);
434 /* Read register REGNUM from REGCACHE and store to REGS + OFFSET
435 in a field REGSIZE wide. Zero pad as necessary. */
438 ppc_collect_reg (const struct regcache
*regcache
, int regnum
,
439 gdb_byte
*regs
, size_t offset
, int regsize
)
441 if (regnum
!= -1 && offset
!= -1)
445 struct gdbarch
*gdbarch
= regcache
->arch ();
446 int gdb_regsize
= register_size (gdbarch
, regnum
);
447 if (gdb_regsize
< regsize
)
449 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
451 memset (regs
+ offset
, 0, regsize
- gdb_regsize
);
452 offset
+= regsize
- gdb_regsize
;
455 memset (regs
+ offset
+ regsize
- gdb_regsize
, 0,
456 regsize
- gdb_regsize
);
459 regcache
->raw_collect (regnum
, regs
+ offset
);
464 ppc_greg_offset (struct gdbarch
*gdbarch
,
465 ppc_gdbarch_tdep
*tdep
,
466 const struct ppc_reg_offsets
*offsets
,
470 *regsize
= offsets
->gpr_size
;
471 if (regnum
>= tdep
->ppc_gp0_regnum
472 && regnum
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
)
473 return (offsets
->r0_offset
474 + (regnum
- tdep
->ppc_gp0_regnum
) * offsets
->gpr_size
);
476 if (regnum
== gdbarch_pc_regnum (gdbarch
))
477 return offsets
->pc_offset
;
479 if (regnum
== tdep
->ppc_ps_regnum
)
480 return offsets
->ps_offset
;
482 if (regnum
== tdep
->ppc_lr_regnum
)
483 return offsets
->lr_offset
;
485 if (regnum
== tdep
->ppc_ctr_regnum
)
486 return offsets
->ctr_offset
;
488 *regsize
= offsets
->xr_size
;
489 if (regnum
== tdep
->ppc_cr_regnum
)
490 return offsets
->cr_offset
;
492 if (regnum
== tdep
->ppc_xer_regnum
)
493 return offsets
->xer_offset
;
495 if (regnum
== tdep
->ppc_mq_regnum
)
496 return offsets
->mq_offset
;
502 ppc_fpreg_offset (ppc_gdbarch_tdep
*tdep
,
503 const struct ppc_reg_offsets
*offsets
,
506 if (regnum
>= tdep
->ppc_fp0_regnum
507 && regnum
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
)
508 return offsets
->f0_offset
+ (regnum
- tdep
->ppc_fp0_regnum
) * 8;
510 if (regnum
== tdep
->ppc_fpscr_regnum
)
511 return offsets
->fpscr_offset
;
516 /* Supply register REGNUM in the general-purpose register set REGSET
517 from the buffer specified by GREGS and LEN to register cache
518 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
521 ppc_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
522 int regnum
, const void *gregs
, size_t len
)
524 struct gdbarch
*gdbarch
= regcache
->arch ();
525 ppc_gdbarch_tdep
*tdep
= (ppc_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
526 const struct ppc_reg_offsets
*offsets
527 = (const struct ppc_reg_offsets
*) regset
->regmap
;
534 int gpr_size
= offsets
->gpr_size
;
536 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
537 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
538 i
++, offset
+= gpr_size
)
539 ppc_supply_reg (regcache
, i
, (const gdb_byte
*) gregs
, offset
,
542 ppc_supply_reg (regcache
, gdbarch_pc_regnum (gdbarch
),
543 (const gdb_byte
*) gregs
, offsets
->pc_offset
, gpr_size
);
544 ppc_supply_reg (regcache
, tdep
->ppc_ps_regnum
,
545 (const gdb_byte
*) gregs
, offsets
->ps_offset
, gpr_size
);
546 ppc_supply_reg (regcache
, tdep
->ppc_lr_regnum
,
547 (const gdb_byte
*) gregs
, offsets
->lr_offset
, gpr_size
);
548 ppc_supply_reg (regcache
, tdep
->ppc_ctr_regnum
,
549 (const gdb_byte
*) gregs
, offsets
->ctr_offset
, gpr_size
);
550 ppc_supply_reg (regcache
, tdep
->ppc_cr_regnum
,
551 (const gdb_byte
*) gregs
, offsets
->cr_offset
,
553 ppc_supply_reg (regcache
, tdep
->ppc_xer_regnum
,
554 (const gdb_byte
*) gregs
, offsets
->xer_offset
,
556 ppc_supply_reg (regcache
, tdep
->ppc_mq_regnum
,
557 (const gdb_byte
*) gregs
, offsets
->mq_offset
,
562 offset
= ppc_greg_offset (gdbarch
, tdep
, offsets
, regnum
, ®size
);
563 ppc_supply_reg (regcache
, regnum
, (const gdb_byte
*) gregs
, offset
, regsize
);
566 /* Supply register REGNUM in the floating-point register set REGSET
567 from the buffer specified by FPREGS and LEN to register cache
568 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
571 ppc_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
572 int regnum
, const void *fpregs
, size_t len
)
574 struct gdbarch
*gdbarch
= regcache
->arch ();
575 const struct ppc_reg_offsets
*offsets
;
578 if (!ppc_floating_point_unit_p (gdbarch
))
581 ppc_gdbarch_tdep
*tdep
= (ppc_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
582 offsets
= (const struct ppc_reg_offsets
*) regset
->regmap
;
587 for (i
= tdep
->ppc_fp0_regnum
, offset
= offsets
->f0_offset
;
588 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
590 ppc_supply_reg (regcache
, i
, (const gdb_byte
*) fpregs
, offset
, 8);
592 ppc_supply_reg (regcache
, tdep
->ppc_fpscr_regnum
,
593 (const gdb_byte
*) fpregs
, offsets
->fpscr_offset
,
594 offsets
->fpscr_size
);
598 offset
= ppc_fpreg_offset (tdep
, offsets
, regnum
);
599 ppc_supply_reg (regcache
, regnum
, (const gdb_byte
*) fpregs
, offset
,
600 regnum
== tdep
->ppc_fpscr_regnum
? offsets
->fpscr_size
: 8);
603 /* Collect register REGNUM in the general-purpose register set
604 REGSET from register cache REGCACHE into the buffer specified by
605 GREGS and LEN. If REGNUM is -1, do this for all registers in
609 ppc_collect_gregset (const struct regset
*regset
,
610 const struct regcache
*regcache
,
611 int regnum
, void *gregs
, size_t len
)
613 struct gdbarch
*gdbarch
= regcache
->arch ();
614 ppc_gdbarch_tdep
*tdep
= (ppc_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
615 const struct ppc_reg_offsets
*offsets
616 = (const struct ppc_reg_offsets
*) regset
->regmap
;
623 int gpr_size
= offsets
->gpr_size
;
625 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
626 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
627 i
++, offset
+= gpr_size
)
628 ppc_collect_reg (regcache
, i
, (gdb_byte
*) gregs
, offset
, gpr_size
);
630 ppc_collect_reg (regcache
, gdbarch_pc_regnum (gdbarch
),
631 (gdb_byte
*) gregs
, offsets
->pc_offset
, gpr_size
);
632 ppc_collect_reg (regcache
, tdep
->ppc_ps_regnum
,
633 (gdb_byte
*) gregs
, offsets
->ps_offset
, gpr_size
);
634 ppc_collect_reg (regcache
, tdep
->ppc_lr_regnum
,
635 (gdb_byte
*) gregs
, offsets
->lr_offset
, gpr_size
);
636 ppc_collect_reg (regcache
, tdep
->ppc_ctr_regnum
,
637 (gdb_byte
*) gregs
, offsets
->ctr_offset
, gpr_size
);
638 ppc_collect_reg (regcache
, tdep
->ppc_cr_regnum
,
639 (gdb_byte
*) gregs
, offsets
->cr_offset
,
641 ppc_collect_reg (regcache
, tdep
->ppc_xer_regnum
,
642 (gdb_byte
*) gregs
, offsets
->xer_offset
,
644 ppc_collect_reg (regcache
, tdep
->ppc_mq_regnum
,
645 (gdb_byte
*) gregs
, offsets
->mq_offset
,
650 offset
= ppc_greg_offset (gdbarch
, tdep
, offsets
, regnum
, ®size
);
651 ppc_collect_reg (regcache
, regnum
, (gdb_byte
*) gregs
, offset
, regsize
);
654 /* Collect register REGNUM in the floating-point register set
655 REGSET from register cache REGCACHE into the buffer specified by
656 FPREGS and LEN. If REGNUM is -1, do this for all registers in
660 ppc_collect_fpregset (const struct regset
*regset
,
661 const struct regcache
*regcache
,
662 int regnum
, void *fpregs
, size_t len
)
664 struct gdbarch
*gdbarch
= regcache
->arch ();
665 const struct ppc_reg_offsets
*offsets
;
668 if (!ppc_floating_point_unit_p (gdbarch
))
671 ppc_gdbarch_tdep
*tdep
= (ppc_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
672 offsets
= (const struct ppc_reg_offsets
*) regset
->regmap
;
677 for (i
= tdep
->ppc_fp0_regnum
, offset
= offsets
->f0_offset
;
678 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
680 ppc_collect_reg (regcache
, i
, (gdb_byte
*) fpregs
, offset
, 8);
682 ppc_collect_reg (regcache
, tdep
->ppc_fpscr_regnum
,
683 (gdb_byte
*) fpregs
, offsets
->fpscr_offset
,
684 offsets
->fpscr_size
);
688 offset
= ppc_fpreg_offset (tdep
, offsets
, regnum
);
689 ppc_collect_reg (regcache
, regnum
, (gdb_byte
*) fpregs
, offset
,
690 regnum
== tdep
->ppc_fpscr_regnum
? offsets
->fpscr_size
: 8);
694 insn_changes_sp_or_jumps (unsigned long insn
)
696 int opcode
= (insn
>> 26) & 0x03f;
697 int sd
= (insn
>> 21) & 0x01f;
698 int a
= (insn
>> 16) & 0x01f;
699 int subcode
= (insn
>> 1) & 0x3ff;
701 /* Changes the stack pointer. */
703 /* NOTE: There are many ways to change the value of a given register.
704 The ways below are those used when the register is R1, the SP,
705 in a funtion's epilogue. */
707 if (opcode
== 31 && subcode
== 444 && a
== 1)
708 return 1; /* mr R1,Rn */
709 if (opcode
== 14 && sd
== 1)
710 return 1; /* addi R1,Rn,simm */
711 if (opcode
== 58 && sd
== 1)
712 return 1; /* ld R1,ds(Rn) */
714 /* Transfers control. */
720 if (opcode
== 19 && subcode
== 16)
722 if (opcode
== 19 && subcode
== 528)
723 return 1; /* bcctr */
728 /* Return true if we are in the function's epilogue, i.e. after the
729 instruction that destroyed the function's stack frame.
731 1) scan forward from the point of execution:
732 a) If you find an instruction that modifies the stack pointer
733 or transfers control (except a return), execution is not in
735 b) Stop scanning if you find a return instruction or reach the
736 end of the function or reach the hard limit for the size of
738 2) scan backward from the point of execution:
739 a) If you find an instruction that modifies the stack pointer,
740 execution *is* in an epilogue, return.
741 b) Stop scanning if you reach an instruction that transfers
742 control or the beginning of the function or reach the hard
743 limit for the size of an epilogue. */
746 rs6000_in_function_epilogue_frame_p (struct frame_info
*curfrm
,
747 struct gdbarch
*gdbarch
, CORE_ADDR pc
)
749 ppc_gdbarch_tdep
*tdep
= (ppc_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
750 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
751 bfd_byte insn_buf
[PPC_INSN_SIZE
];
752 CORE_ADDR scan_pc
, func_start
, func_end
, epilogue_start
, epilogue_end
;
755 /* Find the search limits based on function boundaries and hard limit. */
757 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
760 epilogue_start
= pc
- PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
761 if (epilogue_start
< func_start
) epilogue_start
= func_start
;
763 epilogue_end
= pc
+ PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
764 if (epilogue_end
> func_end
) epilogue_end
= func_end
;
766 /* Scan forward until next 'blr'. */
768 for (scan_pc
= pc
; scan_pc
< epilogue_end
; scan_pc
+= PPC_INSN_SIZE
)
770 if (!safe_frame_unwind_memory (curfrm
, scan_pc
,
771 {insn_buf
, PPC_INSN_SIZE
}))
773 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
, byte_order
);
774 if (insn
== 0x4e800020)
776 /* Assume a bctr is a tail call unless it points strictly within
778 if (insn
== 0x4e800420)
780 CORE_ADDR ctr
= get_frame_register_unsigned (curfrm
,
781 tdep
->ppc_ctr_regnum
);
782 if (ctr
> func_start
&& ctr
< func_end
)
787 if (insn_changes_sp_or_jumps (insn
))
791 /* Scan backward until adjustment to stack pointer (R1). */
793 for (scan_pc
= pc
- PPC_INSN_SIZE
;
794 scan_pc
>= epilogue_start
;
795 scan_pc
-= PPC_INSN_SIZE
)
797 if (!safe_frame_unwind_memory (curfrm
, scan_pc
,
798 {insn_buf
, PPC_INSN_SIZE
}))
800 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
, byte_order
);
801 if (insn_changes_sp_or_jumps (insn
))
808 /* Implement the stack_frame_destroyed_p gdbarch method. */
811 rs6000_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
813 return rs6000_in_function_epilogue_frame_p (get_current_frame (),
817 /* Get the ith function argument for the current function. */
819 rs6000_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
822 return get_frame_register_unsigned (frame
, 3 + argi
);
825 /* Sequence of bytes for breakpoint instruction. */
827 constexpr gdb_byte big_breakpoint
[] = { 0x7f, 0xe0, 0x00, 0x08 };
828 constexpr gdb_byte little_breakpoint
[] = { 0x08, 0x00, 0xe0, 0x7f };
830 typedef BP_MANIPULATION_ENDIAN (little_breakpoint
, big_breakpoint
)
833 /* Instruction masks for displaced stepping. */
834 #define OP_MASK 0xfc000000
835 #define BP_MASK 0xFC0007FE
836 #define B_INSN 0x48000000
837 #define BC_INSN 0x40000000
838 #define BXL_INSN 0x4c000000
839 #define BP_INSN 0x7C000008
841 /* Instruction masks used during single-stepping of atomic
843 #define LOAD_AND_RESERVE_MASK 0xfc0007fe
844 #define LWARX_INSTRUCTION 0x7c000028
845 #define LDARX_INSTRUCTION 0x7c0000A8
846 #define LBARX_INSTRUCTION 0x7c000068
847 #define LHARX_INSTRUCTION 0x7c0000e8
848 #define LQARX_INSTRUCTION 0x7c000228
849 #define STORE_CONDITIONAL_MASK 0xfc0007ff
850 #define STWCX_INSTRUCTION 0x7c00012d
851 #define STDCX_INSTRUCTION 0x7c0001ad
852 #define STBCX_INSTRUCTION 0x7c00056d
853 #define STHCX_INSTRUCTION 0x7c0005ad
854 #define STQCX_INSTRUCTION 0x7c00016d
856 /* Instruction masks for single-stepping of addpcis/lnia. */
857 #define ADDPCIS_INSN 0x4c000004
858 #define ADDPCIS_INSN_MASK 0xfc00003e
859 #define ADDPCIS_TARGET_REGISTER 0x03F00000
860 #define ADDPCIS_INSN_REGSHIFT 21
862 #define PNOP_MASK 0xfff3ffff
863 #define PNOP_INSN 0x07000000
864 #define R_MASK 0x00100000
865 #define R_ZERO 0x00000000
867 /* Check if insn is one of the Load And Reserve instructions used for atomic
869 #define IS_LOAD_AND_RESERVE_INSN(insn) ((insn & LOAD_AND_RESERVE_MASK) == LWARX_INSTRUCTION \
870 || (insn & LOAD_AND_RESERVE_MASK) == LDARX_INSTRUCTION \
871 || (insn & LOAD_AND_RESERVE_MASK) == LBARX_INSTRUCTION \
872 || (insn & LOAD_AND_RESERVE_MASK) == LHARX_INSTRUCTION \
873 || (insn & LOAD_AND_RESERVE_MASK) == LQARX_INSTRUCTION)
874 /* Check if insn is one of the Store Conditional instructions used for atomic
876 #define IS_STORE_CONDITIONAL_INSN(insn) ((insn & STORE_CONDITIONAL_MASK) == STWCX_INSTRUCTION \
877 || (insn & STORE_CONDITIONAL_MASK) == STDCX_INSTRUCTION \
878 || (insn & STORE_CONDITIONAL_MASK) == STBCX_INSTRUCTION \
879 || (insn & STORE_CONDITIONAL_MASK) == STHCX_INSTRUCTION \
880 || (insn & STORE_CONDITIONAL_MASK) == STQCX_INSTRUCTION)
882 typedef buf_displaced_step_copy_insn_closure
883 ppc_displaced_step_copy_insn_closure
;
885 /* We can't displaced step atomic sequences. */
887 static displaced_step_copy_insn_closure_up
888 ppc_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
889 CORE_ADDR from
, CORE_ADDR to
,
890 struct regcache
*regs
)
892 size_t len
= gdbarch_max_insn_length (gdbarch
);
893 std::unique_ptr
<ppc_displaced_step_copy_insn_closure
> closure
894 (new ppc_displaced_step_copy_insn_closure (len
));
895 gdb_byte
*buf
= closure
->buf
.data ();
896 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
899 len
= target_read (current_inferior()->top_target(), TARGET_OBJECT_MEMORY
, NULL
,
901 if ((ssize_t
) len
< PPC_INSN_SIZE
)
902 memory_error (TARGET_XFER_E_IO
, from
);
904 insn
= extract_signed_integer (buf
, PPC_INSN_SIZE
, byte_order
);
906 /* Check for PNOP and for prefixed instructions with R=0. Those
907 instructions are safe to displace. Prefixed instructions with R=1
908 will read/write data to/from locations relative to the current PC.
909 We would not be able to fixup after an instruction has written data
910 into a displaced location, so decline to displace those instructions. */
911 if ((insn
& OP_MASK
) == 1 << 26)
913 if (((insn
& PNOP_MASK
) != PNOP_INSN
)
914 && ((insn
& R_MASK
) != R_ZERO
))
916 displaced_debug_printf ("Not displacing prefixed instruction %08x at %s",
917 insn
, paddress (gdbarch
, from
));
922 /* Non-prefixed instructions.. */
924 /* Set the instruction length to 4 to match the actual instruction
929 /* Assume all atomic sequences start with a Load and Reserve instruction. */
930 if (IS_LOAD_AND_RESERVE_INSN (insn
))
932 displaced_debug_printf ("can't displaced step atomic sequence at %s",
933 paddress (gdbarch
, from
));
938 write_memory (to
, buf
, len
);
940 displaced_debug_printf ("copy %s->%s: %s",
941 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
942 displaced_step_dump_bytes (buf
, len
).c_str ());
944 /* This is a work around for a problem with g++ 4.8. */
945 return displaced_step_copy_insn_closure_up (closure
.release ());
948 /* Fix up the state of registers and memory after having single-stepped
949 a displaced instruction. */
951 ppc_displaced_step_fixup (struct gdbarch
*gdbarch
,
952 struct displaced_step_copy_insn_closure
*closure_
,
953 CORE_ADDR from
, CORE_ADDR to
,
954 struct regcache
*regs
)
956 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
957 /* Our closure is a copy of the instruction. */
958 ppc_displaced_step_copy_insn_closure
*closure
959 = (ppc_displaced_step_copy_insn_closure
*) closure_
;
960 ULONGEST insn
= extract_unsigned_integer (closure
->buf
.data (),
961 PPC_INSN_SIZE
, byte_order
);
963 /* Offset for non PC-relative instructions. */
966 opcode
= insn
& OP_MASK
;
968 /* Set offset to 8 if this is an 8-byte (prefixed) instruction. */
969 if ((opcode
) == 1 << 26)
970 offset
= 2 * PPC_INSN_SIZE
;
972 offset
= PPC_INSN_SIZE
;
974 displaced_debug_printf ("(ppc) fixup (%s, %s)",
975 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
977 /* Handle the addpcis/lnia instruction. */
978 if ((insn
& ADDPCIS_INSN_MASK
) == ADDPCIS_INSN
)
980 LONGEST displaced_offset
;
981 ULONGEST current_val
;
982 /* Measure the displacement. */
983 displaced_offset
= from
- to
;
984 /* Identify the target register that was updated by the instruction. */
985 int regnum
= (insn
& ADDPCIS_TARGET_REGISTER
) >> ADDPCIS_INSN_REGSHIFT
;
986 /* Read and update the target value. */
987 regcache_cooked_read_unsigned (regs
, regnum
, ¤t_val
);
988 displaced_debug_printf ("addpcis target regnum %d was %s now %s",
989 regnum
, paddress (gdbarch
, current_val
),
990 paddress (gdbarch
, current_val
991 + displaced_offset
));
992 regcache_cooked_write_unsigned (regs
, regnum
,
993 current_val
+ displaced_offset
);
994 /* point the PC back at the non-displaced instruction. */
995 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
998 /* Handle PC-relative branch instructions. */
999 else if (opcode
== B_INSN
|| opcode
== BC_INSN
|| opcode
== BXL_INSN
)
1001 ULONGEST current_pc
;
1003 /* Read the current PC value after the instruction has been executed
1004 in a displaced location. Calculate the offset to be applied to the
1005 original PC value before the displaced stepping. */
1006 regcache_cooked_read_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
1008 offset
= current_pc
- to
;
1010 if (opcode
!= BXL_INSN
)
1012 /* Check for AA bit indicating whether this is an absolute
1013 addressing or PC-relative (1: absolute, 0: relative). */
1016 /* PC-relative addressing is being used in the branch. */
1017 displaced_debug_printf ("(ppc) branch instruction: %s",
1018 paddress (gdbarch
, insn
));
1019 displaced_debug_printf ("(ppc) adjusted PC from %s to %s",
1020 paddress (gdbarch
, current_pc
),
1021 paddress (gdbarch
, from
+ offset
));
1023 regcache_cooked_write_unsigned (regs
,
1024 gdbarch_pc_regnum (gdbarch
),
1030 /* If we're here, it means we have a branch to LR or CTR. If the
1031 branch was taken, the offset is probably greater than 4 (the next
1032 instruction), so it's safe to assume that an offset of 4 means we
1033 did not take the branch. */
1034 if (offset
== PPC_INSN_SIZE
)
1035 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
1036 from
+ PPC_INSN_SIZE
);
1039 /* Check for LK bit indicating whether we should set the link
1040 register to point to the next instruction
1041 (1: Set, 0: Don't set). */
1044 /* Link register needs to be set to the next instruction's PC. */
1045 ppc_gdbarch_tdep
*tdep
= (ppc_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
1046 regcache_cooked_write_unsigned (regs
,
1047 tdep
->ppc_lr_regnum
,
1048 from
+ PPC_INSN_SIZE
);
1049 displaced_debug_printf ("(ppc) adjusted LR to %s",
1050 paddress (gdbarch
, from
+ PPC_INSN_SIZE
));
1054 /* Check for breakpoints in the inferior. If we've found one, place the PC
1055 right at the breakpoint instruction. */
1056 else if ((insn
& BP_MASK
) == BP_INSN
)
1057 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
), from
);
1060 /* Handle any other instructions that do not fit in the categories
1062 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
1067 /* Implementation of gdbarch_displaced_step_prepare. */
1069 static displaced_step_prepare_status
1070 ppc_displaced_step_prepare (gdbarch
*arch
, thread_info
*thread
,
1071 CORE_ADDR
&displaced_pc
)
1073 ppc_inferior_data
*per_inferior
= get_ppc_per_inferior (thread
->inf
);
1075 if (!per_inferior
->disp_step_buf
.has_value ())
1077 /* Figure out where the displaced step buffer is. */
1078 CORE_ADDR disp_step_buf_addr
1079 = displaced_step_at_entry_point (thread
->inf
->gdbarch
);
1081 per_inferior
->disp_step_buf
.emplace (disp_step_buf_addr
);
1084 return per_inferior
->disp_step_buf
->prepare (thread
, displaced_pc
);
1087 /* Implementation of gdbarch_displaced_step_finish. */
1089 static displaced_step_finish_status
1090 ppc_displaced_step_finish (gdbarch
*arch
, thread_info
*thread
,
1093 ppc_inferior_data
*per_inferior
= get_ppc_per_inferior (thread
->inf
);
1095 gdb_assert (per_inferior
->disp_step_buf
.has_value ());
1097 return per_inferior
->disp_step_buf
->finish (arch
, thread
, sig
);
1100 /* Implementation of gdbarch_displaced_step_restore_all_in_ptid. */
1103 ppc_displaced_step_restore_all_in_ptid (inferior
*parent_inf
, ptid_t ptid
)
1105 ppc_inferior_data
*per_inferior
= ppc_inferior_data_key
.get (parent_inf
);
1107 if (per_inferior
== nullptr
1108 || !per_inferior
->disp_step_buf
.has_value ())
1111 per_inferior
->disp_step_buf
->restore_in_ptid (ptid
);
1114 /* Always use hardware single-stepping to execute the
1115 displaced instruction. */
1117 ppc_displaced_step_hw_singlestep (struct gdbarch
*gdbarch
)
1122 /* Checks for an atomic sequence of instructions beginning with a
1123 Load And Reserve instruction and ending with a Store Conditional
1124 instruction. If such a sequence is found, attempt to step through it.
1125 A breakpoint is placed at the end of the sequence. */
1126 std::vector
<CORE_ADDR
>
1127 ppc_deal_with_atomic_sequence (struct regcache
*regcache
)
1129 struct gdbarch
*gdbarch
= regcache
->arch ();
1130 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1131 CORE_ADDR pc
= regcache_read_pc (regcache
);
1132 CORE_ADDR breaks
[2] = {CORE_ADDR_MAX
, CORE_ADDR_MAX
};
1134 CORE_ADDR closing_insn
; /* Instruction that closes the atomic sequence. */
1135 int insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
1138 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
1139 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
1140 int bc_insn_count
= 0; /* Conditional branch instruction count. */
1142 /* Assume all atomic sequences start with a Load And Reserve instruction. */
1143 if (!IS_LOAD_AND_RESERVE_INSN (insn
))
1146 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
1148 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
1150 if ((insn
& OP_MASK
) == 1 << 26)
1151 loc
+= 2 * PPC_INSN_SIZE
;
1153 loc
+= PPC_INSN_SIZE
;
1154 insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
1156 /* Assume that there is at most one conditional branch in the atomic
1157 sequence. If a conditional branch is found, put a breakpoint in
1158 its destination address. */
1159 if ((insn
& OP_MASK
) == BC_INSN
)
1161 int immediate
= ((insn
& 0xfffc) ^ 0x8000) - 0x8000;
1162 int absolute
= insn
& 2;
1164 if (bc_insn_count
>= 1)
1165 return {}; /* More than one conditional branch found, fallback
1166 to the standard single-step code. */
1169 breaks
[1] = immediate
;
1171 breaks
[1] = loc
+ immediate
;
1177 if (IS_STORE_CONDITIONAL_INSN (insn
))
1181 /* Assume that the atomic sequence ends with a Store Conditional
1183 if (!IS_STORE_CONDITIONAL_INSN (insn
))
1187 loc
+= PPC_INSN_SIZE
;
1189 /* Insert a breakpoint right after the end of the atomic sequence. */
1192 /* Check for duplicated breakpoints. Check also for a breakpoint
1193 placed (branch instruction's destination) anywhere in sequence. */
1195 && (breaks
[1] == breaks
[0]
1196 || (breaks
[1] >= pc
&& breaks
[1] <= closing_insn
)))
1197 last_breakpoint
= 0;
1199 std::vector
<CORE_ADDR
> next_pcs
;
1201 for (index
= 0; index
<= last_breakpoint
; index
++)
1202 next_pcs
.push_back (breaks
[index
]);
1208 #define SIGNED_SHORT(x) \
1209 ((sizeof (short) == 2) \
1210 ? ((int)(short)(x)) \
1211 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
1213 #define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
1215 /* Limit the number of skipped non-prologue instructions, as the examining
1216 of the prologue is expensive. */
1217 static int max_skip_non_prologue_insns
= 10;
1219 /* Return nonzero if the given instruction OP can be part of the prologue
1220 of a function and saves a parameter on the stack. FRAMEP should be
1221 set if one of the previous instructions in the function has set the
1225 store_param_on_stack_p (unsigned long op
, int framep
, int *r0_contains_arg
)
1227 /* Move parameters from argument registers to temporary register. */
1228 if ((op
& 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
1230 /* Rx must be scratch register r0. */
1231 const int rx_regno
= (op
>> 16) & 31;
1232 /* Ry: Only r3 - r10 are used for parameter passing. */
1233 const int ry_regno
= GET_SRC_REG (op
);
1235 if (rx_regno
== 0 && ry_regno
>= 3 && ry_regno
<= 10)
1237 *r0_contains_arg
= 1;
1244 /* Save a General Purpose Register on stack. */
1246 if ((op
& 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
1247 (op
& 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
1249 /* Rx: Only r3 - r10 are used for parameter passing. */
1250 const int rx_regno
= GET_SRC_REG (op
);
1252 return (rx_regno
>= 3 && rx_regno
<= 10);
1255 /* Save a General Purpose Register on stack via the Frame Pointer. */
1258 ((op
& 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
1259 (op
& 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
1260 (op
& 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
1262 /* Rx: Usually, only r3 - r10 are used for parameter passing.
1263 However, the compiler sometimes uses r0 to hold an argument. */
1264 const int rx_regno
= GET_SRC_REG (op
);
1266 return ((rx_regno
>= 3 && rx_regno
<= 10)
1267 || (rx_regno
== 0 && *r0_contains_arg
));
1270 if ((op
& 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
1272 /* Only f2 - f8 are used for parameter passing. */
1273 const int src_regno
= GET_SRC_REG (op
);
1275 return (src_regno
>= 2 && src_regno
<= 8);
1278 if (framep
&& ((op
& 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
1280 /* Only f2 - f8 are used for parameter passing. */
1281 const int src_regno
= GET_SRC_REG (op
);
1283 return (src_regno
>= 2 && src_regno
<= 8);
1286 /* Not an insn that saves a parameter on stack. */
1290 /* Assuming that INSN is a "bl" instruction located at PC, return
1291 nonzero if the destination of the branch is a "blrl" instruction.
1293 This sequence is sometimes found in certain function prologues.
1294 It allows the function to load the LR register with a value that
1295 they can use to access PIC data using PC-relative offsets. */
1298 bl_to_blrl_insn_p (CORE_ADDR pc
, int insn
, enum bfd_endian byte_order
)
1305 absolute
= (int) ((insn
>> 1) & 1);
1306 immediate
= ((insn
& ~3) << 6) >> 6;
1310 dest
= pc
+ immediate
;
1312 dest_insn
= read_memory_integer (dest
, 4, byte_order
);
1313 if ((dest_insn
& 0xfc00ffff) == 0x4c000021) /* blrl */
1319 /* Return true if OP is a stw or std instruction with
1320 register operands RS and RA and any immediate offset.
1322 If WITH_UPDATE is true, also return true if OP is
1323 a stwu or stdu instruction with the same operands.
1325 Return false otherwise.
1328 store_insn_p (unsigned long op
, unsigned long rs
,
1329 unsigned long ra
, bool with_update
)
1334 if (/* std RS, SIMM(RA) */
1335 ((op
& 0xffff0003) == (rs
| ra
| 0xf8000000)) ||
1336 /* stw RS, SIMM(RA) */
1337 ((op
& 0xffff0000) == (rs
| ra
| 0x90000000)))
1342 if (/* stdu RS, SIMM(RA) */
1343 ((op
& 0xffff0003) == (rs
| ra
| 0xf8000001)) ||
1344 /* stwu RS, SIMM(RA) */
1345 ((op
& 0xffff0000) == (rs
| ra
| 0x94000000)))
1352 /* Masks for decoding a branch-and-link (bl) instruction.
1354 BL_MASK and BL_INSTRUCTION are used in combination with each other.
1355 The former is anded with the opcode in question; if the result of
1356 this masking operation is equal to BL_INSTRUCTION, then the opcode in
1357 question is a ``bl'' instruction.
1359 BL_DISPLACEMENT_MASK is anded with the opcode in order to extract
1360 the branch displacement. */
1362 #define BL_MASK 0xfc000001
1363 #define BL_INSTRUCTION 0x48000001
1364 #define BL_DISPLACEMENT_MASK 0x03fffffc
1366 static unsigned long
1367 rs6000_fetch_instruction (struct gdbarch
*gdbarch
, const CORE_ADDR pc
)
1369 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1373 /* Fetch the instruction and convert it to an integer. */
1374 if (target_read_memory (pc
, buf
, 4))
1376 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1381 /* GCC generates several well-known sequences of instructions at the begining
1382 of each function prologue when compiling with -fstack-check. If one of
1383 such sequences starts at START_PC, then return the address of the
1384 instruction immediately past this sequence. Otherwise, return START_PC. */
1387 rs6000_skip_stack_check (struct gdbarch
*gdbarch
, const CORE_ADDR start_pc
)
1389 CORE_ADDR pc
= start_pc
;
1390 unsigned long op
= rs6000_fetch_instruction (gdbarch
, pc
);
1392 /* First possible sequence: A small number of probes.
1393 stw 0, -<some immediate>(1)
1394 [repeat this instruction any (small) number of times]. */
1396 if ((op
& 0xffff0000) == 0x90010000)
1398 while ((op
& 0xffff0000) == 0x90010000)
1401 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1406 /* Second sequence: A probing loop.
1407 addi 12,1,-<some immediate>
1408 lis 0,-<some immediate>
1409 [possibly ori 0,0,<some immediate>]
1413 addi 12,12,-<some immediate>
1416 [possibly one last probe: stw 0,<some immediate>(12)]. */
1420 /* addi 12,1,-<some immediate> */
1421 if ((op
& 0xffff0000) != 0x39810000)
1424 /* lis 0,-<some immediate> */
1426 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1427 if ((op
& 0xffff0000) != 0x3c000000)
1431 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1432 /* [possibly ori 0,0,<some immediate>] */
1433 if ((op
& 0xffff0000) == 0x60000000)
1436 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1439 if (op
!= 0x7c0c0214)
1444 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1445 if (op
!= 0x7c0c0000)
1450 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1451 if ((op
& 0xff9f0001) != 0x41820000)
1454 /* addi 12,12,-<some immediate> */
1456 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1457 if ((op
& 0xffff0000) != 0x398c0000)
1462 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1463 if (op
!= 0x900c0000)
1468 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1469 if ((op
& 0xfc000001) != 0x48000000)
1472 /* [possibly one last probe: stw 0,<some immediate>(12)]. */
1474 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1475 if ((op
& 0xffff0000) == 0x900c0000)
1478 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1481 /* We found a valid stack-check sequence, return the new PC. */
1485 /* Third sequence: No probe; instead, a comparison between the stack size
1486 limit (saved in a run-time global variable) and the current stack
1489 addi 0,1,-<some immediate>
1490 lis 12,__gnat_stack_limit@ha
1491 lwz 12,__gnat_stack_limit@l(12)
1494 or, with a small variant in the case of a bigger stack frame:
1495 addis 0,1,<some immediate>
1496 addic 0,0,-<some immediate>
1497 lis 12,__gnat_stack_limit@ha
1498 lwz 12,__gnat_stack_limit@l(12)
1503 /* addi 0,1,-<some immediate> */
1504 if ((op
& 0xffff0000) != 0x38010000)
1506 /* small stack frame variant not recognized; try the
1507 big stack frame variant: */
1509 /* addis 0,1,<some immediate> */
1510 if ((op
& 0xffff0000) != 0x3c010000)
1513 /* addic 0,0,-<some immediate> */
1515 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1516 if ((op
& 0xffff0000) != 0x30000000)
1520 /* lis 12,<some immediate> */
1522 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1523 if ((op
& 0xffff0000) != 0x3d800000)
1526 /* lwz 12,<some immediate>(12) */
1528 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1529 if ((op
& 0xffff0000) != 0x818c0000)
1534 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1535 if ((op
& 0xfffffffe) != 0x7c406008)
1538 /* We found a valid stack-check sequence, return the new PC. */
1542 /* No stack check code in our prologue, return the start_pc. */
1546 /* return pc value after skipping a function prologue and also return
1547 information about a function frame.
1549 in struct rs6000_framedata fdata:
1550 - frameless is TRUE, if function does not have a frame.
1551 - nosavedpc is TRUE, if function does not save %pc value in its frame.
1552 - offset is the initial size of this stack frame --- the amount by
1553 which we decrement the sp to allocate the frame.
1554 - saved_gpr is the number of the first saved gpr.
1555 - saved_fpr is the number of the first saved fpr.
1556 - saved_vr is the number of the first saved vr.
1557 - saved_ev is the number of the first saved ev.
1558 - alloca_reg is the number of the register used for alloca() handling.
1560 - gpr_offset is the offset of the first saved gpr from the previous frame.
1561 - fpr_offset is the offset of the first saved fpr from the previous frame.
1562 - vr_offset is the offset of the first saved vr from the previous frame.
1563 - ev_offset is the offset of the first saved ev from the previous frame.
1564 - lr_offset is the offset of the saved lr
1565 - cr_offset is the offset of the saved cr
1566 - vrsave_offset is the offset of the saved vrsave register. */
1569 skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
, CORE_ADDR lim_pc
,
1570 struct rs6000_framedata
*fdata
)
1572 CORE_ADDR orig_pc
= pc
;
1573 CORE_ADDR last_prologue_pc
= pc
;
1574 CORE_ADDR li_found_pc
= 0;
1578 long alloca_reg_offset
= 0;
1579 long vr_saved_offset
= 0;
1585 int vrsave_reg
= -1;
1588 int minimal_toc_loaded
= 0;
1589 int prev_insn_was_prologue_insn
= 1;
1590 int num_skip_non_prologue_insns
= 0;
1591 int r0_contains_arg
= 0;
1592 const struct bfd_arch_info
*arch_info
= gdbarch_bfd_arch_info (gdbarch
);
1593 ppc_gdbarch_tdep
*tdep
= (ppc_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
1594 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1596 memset (fdata
, 0, sizeof (struct rs6000_framedata
));
1597 fdata
->saved_gpr
= -1;
1598 fdata
->saved_fpr
= -1;
1599 fdata
->saved_vr
= -1;
1600 fdata
->saved_ev
= -1;
1601 fdata
->alloca_reg
= -1;
1602 fdata
->frameless
= 1;
1603 fdata
->nosavedpc
= 1;
1604 fdata
->lr_register
= -1;
1606 pc
= rs6000_skip_stack_check (gdbarch
, pc
);
1612 /* Sometimes it isn't clear if an instruction is a prologue
1613 instruction or not. When we encounter one of these ambiguous
1614 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
1615 Otherwise, we'll assume that it really is a prologue instruction. */
1616 if (prev_insn_was_prologue_insn
)
1617 last_prologue_pc
= pc
;
1619 /* Stop scanning if we've hit the limit. */
1623 prev_insn_was_prologue_insn
= 1;
1625 /* Fetch the instruction and convert it to an integer. */
1626 if (target_read_memory (pc
, buf
, 4))
1628 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1630 if ((op
& 0xfc1fffff) == 0x7c0802a6)
1632 /* Since shared library / PIC code, which needs to get its
1633 address at runtime, can appear to save more than one link
1647 remember just the first one, but skip over additional
1650 lr_reg
= (op
& 0x03e00000) >> 21;
1652 r0_contains_arg
= 0;
1655 else if ((op
& 0xfc1fffff) == 0x7c000026)
1657 cr_reg
= (op
& 0x03e00000) >> 21;
1659 r0_contains_arg
= 0;
1663 else if ((op
& 0xfc1f0000) == 0xd8010000)
1664 { /* stfd Rx,NUM(r1) */
1665 reg
= GET_SRC_REG (op
);
1666 if (fdata
->saved_fpr
== -1 || fdata
->saved_fpr
> reg
)
1668 fdata
->saved_fpr
= reg
;
1669 fdata
->fpr_offset
= SIGNED_SHORT (op
) + offset
;
1674 else if (((op
& 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
1675 (((op
& 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
1676 (op
& 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
1677 (op
& 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
1680 reg
= GET_SRC_REG (op
);
1681 if ((op
& 0xfc1f0000) == 0xbc010000)
1682 fdata
->gpr_mask
|= ~((1U << reg
) - 1);
1684 fdata
->gpr_mask
|= 1U << reg
;
1685 if (fdata
->saved_gpr
== -1 || fdata
->saved_gpr
> reg
)
1687 fdata
->saved_gpr
= reg
;
1688 if ((op
& 0xfc1f0003) == 0xf8010000)
1690 fdata
->gpr_offset
= SIGNED_SHORT (op
) + offset
;
1695 else if ((op
& 0xffff0000) == 0x3c4c0000
1696 || (op
& 0xffff0000) == 0x3c400000
1697 || (op
& 0xffff0000) == 0x38420000)
1699 /* . 0: addis 2,12,.TOC.-0b@ha
1700 . addi 2,2,.TOC.-0b@l
1704 used by ELFv2 global entry points to set up r2. */
1707 else if (op
== 0x60000000)
1710 /* Allow nops in the prologue, but do not consider them to
1711 be part of the prologue unless followed by other prologue
1713 prev_insn_was_prologue_insn
= 0;
1717 else if ((op
& 0xffff0000) == 0x3c000000)
1718 { /* addis 0,0,NUM, used for >= 32k frames */
1719 fdata
->offset
= (op
& 0x0000ffff) << 16;
1720 fdata
->frameless
= 0;
1721 r0_contains_arg
= 0;
1725 else if ((op
& 0xffff0000) == 0x60000000)
1726 { /* ori 0,0,NUM, 2nd half of >= 32k frames */
1727 fdata
->offset
|= (op
& 0x0000ffff);
1728 fdata
->frameless
= 0;
1729 r0_contains_arg
= 0;
1733 else if (lr_reg
>= 0 &&
1734 ((store_insn_p (op
, lr_reg
, 1, true)) ||
1736 (store_insn_p (op
, lr_reg
,
1737 fdata
->alloca_reg
- tdep
->ppc_gp0_regnum
,
1740 if (store_insn_p (op
, lr_reg
, 1, true))
1741 fdata
->lr_offset
= offset
;
1742 else /* LR save through frame pointer. */
1743 fdata
->lr_offset
= alloca_reg_offset
;
1745 fdata
->nosavedpc
= 0;
1746 /* Invalidate lr_reg, but don't set it to -1.
1747 That would mean that it had never been set. */
1749 if ((op
& 0xfc000003) == 0xf8000000 || /* std */
1750 (op
& 0xfc000000) == 0x90000000) /* stw */
1752 /* Does not update r1, so add displacement to lr_offset. */
1753 fdata
->lr_offset
+= SIGNED_SHORT (op
);
1758 else if (cr_reg
>= 0 &&
1759 (store_insn_p (op
, cr_reg
, 1, true)))
1761 fdata
->cr_offset
= offset
;
1762 /* Invalidate cr_reg, but don't set it to -1.
1763 That would mean that it had never been set. */
1765 if ((op
& 0xfc000003) == 0xf8000000 ||
1766 (op
& 0xfc000000) == 0x90000000)
1768 /* Does not update r1, so add displacement to cr_offset. */
1769 fdata
->cr_offset
+= SIGNED_SHORT (op
);
1774 else if ((op
& 0xfe80ffff) == 0x42800005 && lr_reg
!= -1)
1776 /* bcl 20,xx,.+4 is used to get the current PC, with or without
1777 prediction bits. If the LR has already been saved, we can
1781 else if (op
== 0x48000005)
1788 else if (op
== 0x48000004)
1793 else if ((op
& 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
1794 in V.4 -mminimal-toc */
1795 (op
& 0xffff0000) == 0x3bde0000)
1796 { /* addi 30,30,foo@l */
1800 else if ((op
& 0xfc000001) == 0x48000001)
1804 fdata
->frameless
= 0;
1806 /* If the return address has already been saved, we can skip
1807 calls to blrl (for PIC). */
1808 if (lr_reg
!= -1 && bl_to_blrl_insn_p (pc
, op
, byte_order
))
1814 /* Don't skip over the subroutine call if it is not within
1815 the first three instructions of the prologue and either
1816 we have no line table information or the line info tells
1817 us that the subroutine call is not part of the line
1818 associated with the prologue. */
1819 if ((pc
- orig_pc
) > 8)
1821 struct symtab_and_line prologue_sal
= find_pc_line (orig_pc
, 0);
1822 struct symtab_and_line this_sal
= find_pc_line (pc
, 0);
1824 if ((prologue_sal
.line
== 0)
1825 || (prologue_sal
.line
!= this_sal
.line
))
1829 op
= read_memory_integer (pc
+ 4, 4, byte_order
);
1831 /* At this point, make sure this is not a trampoline
1832 function (a function that simply calls another functions,
1833 and nothing else). If the next is not a nop, this branch
1834 was part of the function prologue. */
1836 if (op
== 0x4def7b82 || op
== 0) /* crorc 15, 15, 15 */
1837 break; /* Don't skip over
1843 /* update stack pointer */
1844 else if ((op
& 0xfc1f0000) == 0x94010000)
1845 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
1846 fdata
->frameless
= 0;
1847 fdata
->offset
= SIGNED_SHORT (op
);
1848 offset
= fdata
->offset
;
1851 else if ((op
& 0xfc1f07fa) == 0x7c01016a)
1852 { /* stwux rX,r1,rY || stdux rX,r1,rY */
1853 /* No way to figure out what r1 is going to be. */
1854 fdata
->frameless
= 0;
1855 offset
= fdata
->offset
;
1858 else if ((op
& 0xfc1f0003) == 0xf8010001)
1859 { /* stdu rX,NUM(r1) */
1860 fdata
->frameless
= 0;
1861 fdata
->offset
= SIGNED_SHORT (op
& ~3UL);
1862 offset
= fdata
->offset
;
1865 else if ((op
& 0xffff0000) == 0x38210000)
1866 { /* addi r1,r1,SIMM */
1867 fdata
->frameless
= 0;
1868 fdata
->offset
+= SIGNED_SHORT (op
);
1869 offset
= fdata
->offset
;
1872 /* Load up minimal toc pointer. Do not treat an epilogue restore
1873 of r31 as a minimal TOC load. */
1874 else if (((op
>> 22) == 0x20f || /* l r31,... or l r30,... */
1875 (op
>> 22) == 0x3af) /* ld r31,... or ld r30,... */
1877 && !minimal_toc_loaded
)
1879 minimal_toc_loaded
= 1;
1882 /* move parameters from argument registers to local variable
1885 else if ((op
& 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
1886 (((op
>> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
1887 (((op
>> 21) & 31) <= 10) &&
1888 ((long) ((op
>> 16) & 31)
1889 >= fdata
->saved_gpr
)) /* Rx: local var reg */
1893 /* store parameters in stack */
1895 /* Move parameters from argument registers to temporary register. */
1896 else if (store_param_on_stack_p (op
, framep
, &r0_contains_arg
))
1900 /* Set up frame pointer */
1902 else if (op
== 0x603d0000) /* oril r29, r1, 0x0 */
1904 fdata
->frameless
= 0;
1906 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
+ 29);
1907 alloca_reg_offset
= offset
;
1910 /* Another way to set up the frame pointer. */
1912 else if (op
== 0x603f0000 /* oril r31, r1, 0x0 */
1913 || op
== 0x7c3f0b78)
1915 fdata
->frameless
= 0;
1917 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
+ 31);
1918 alloca_reg_offset
= offset
;
1921 /* Another way to set up the frame pointer. */
1923 else if ((op
& 0xfc1fffff) == 0x38010000)
1924 { /* addi rX, r1, 0x0 */
1925 fdata
->frameless
= 0;
1927 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
1928 + ((op
& ~0x38010000) >> 21));
1929 alloca_reg_offset
= offset
;
1932 /* AltiVec related instructions. */
1933 /* Store the vrsave register (spr 256) in another register for
1934 later manipulation, or load a register into the vrsave
1935 register. 2 instructions are used: mfvrsave and
1936 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1937 and mtspr SPR256, Rn. */
1938 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1939 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1940 else if ((op
& 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1942 vrsave_reg
= GET_SRC_REG (op
);
1945 else if ((op
& 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1949 /* Store the register where vrsave was saved to onto the stack:
1950 rS is the register where vrsave was stored in a previous
1952 /* 100100 sssss 00001 dddddddd dddddddd */
1953 else if ((op
& 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1955 if (vrsave_reg
== GET_SRC_REG (op
))
1957 fdata
->vrsave_offset
= SIGNED_SHORT (op
) + offset
;
1962 /* Compute the new value of vrsave, by modifying the register
1963 where vrsave was saved to. */
1964 else if (((op
& 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1965 || ((op
& 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1969 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1970 in a pair of insns to save the vector registers on the
1972 /* 001110 00000 00000 iiii iiii iiii iiii */
1973 /* 001110 01110 00000 iiii iiii iiii iiii */
1974 else if ((op
& 0xffff0000) == 0x38000000 /* li r0, SIMM */
1975 || (op
& 0xffff0000) == 0x39c00000) /* li r14, SIMM */
1977 if ((op
& 0xffff0000) == 0x38000000)
1978 r0_contains_arg
= 0;
1980 vr_saved_offset
= SIGNED_SHORT (op
);
1982 /* This insn by itself is not part of the prologue, unless
1983 if part of the pair of insns mentioned above. So do not
1984 record this insn as part of the prologue yet. */
1985 prev_insn_was_prologue_insn
= 0;
1987 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
1988 /* 011111 sssss 11111 00000 00111001110 */
1989 else if ((op
& 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
1991 if (pc
== (li_found_pc
+ 4))
1993 vr_reg
= GET_SRC_REG (op
);
1994 /* If this is the first vector reg to be saved, or if
1995 it has a lower number than others previously seen,
1996 reupdate the frame info. */
1997 if (fdata
->saved_vr
== -1 || fdata
->saved_vr
> vr_reg
)
1999 fdata
->saved_vr
= vr_reg
;
2000 fdata
->vr_offset
= vr_saved_offset
+ offset
;
2002 vr_saved_offset
= -1;
2007 /* End AltiVec related instructions. */
2009 /* Start BookE related instructions. */
2010 /* Store gen register S at (r31+uimm).
2011 Any register less than r13 is volatile, so we don't care. */
2012 /* 000100 sssss 11111 iiiii 01100100001 */
2013 else if (arch_info
->mach
== bfd_mach_ppc_e500
2014 && (op
& 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
2016 if ((op
& 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
2019 ev_reg
= GET_SRC_REG (op
);
2020 imm
= (op
>> 11) & 0x1f;
2021 ev_offset
= imm
* 8;
2022 /* If this is the first vector reg to be saved, or if
2023 it has a lower number than others previously seen,
2024 reupdate the frame info. */
2025 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2027 fdata
->saved_ev
= ev_reg
;
2028 fdata
->ev_offset
= ev_offset
+ offset
;
2033 /* Store gen register rS at (r1+rB). */
2034 /* 000100 sssss 00001 bbbbb 01100100000 */
2035 else if (arch_info
->mach
== bfd_mach_ppc_e500
2036 && (op
& 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
2038 if (pc
== (li_found_pc
+ 4))
2040 ev_reg
= GET_SRC_REG (op
);
2041 /* If this is the first vector reg to be saved, or if
2042 it has a lower number than others previously seen,
2043 reupdate the frame info. */
2044 /* We know the contents of rB from the previous instruction. */
2045 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2047 fdata
->saved_ev
= ev_reg
;
2048 fdata
->ev_offset
= vr_saved_offset
+ offset
;
2050 vr_saved_offset
= -1;
2056 /* Store gen register r31 at (rA+uimm). */
2057 /* 000100 11111 aaaaa iiiii 01100100001 */
2058 else if (arch_info
->mach
== bfd_mach_ppc_e500
2059 && (op
& 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
2061 /* Wwe know that the source register is 31 already, but
2062 it can't hurt to compute it. */
2063 ev_reg
= GET_SRC_REG (op
);
2064 ev_offset
= ((op
>> 11) & 0x1f) * 8;
2065 /* If this is the first vector reg to be saved, or if
2066 it has a lower number than others previously seen,
2067 reupdate the frame info. */
2068 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2070 fdata
->saved_ev
= ev_reg
;
2071 fdata
->ev_offset
= ev_offset
+ offset
;
2076 /* Store gen register S at (r31+r0).
2077 Store param on stack when offset from SP bigger than 4 bytes. */
2078 /* 000100 sssss 11111 00000 01100100000 */
2079 else if (arch_info
->mach
== bfd_mach_ppc_e500
2080 && (op
& 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
2082 if (pc
== (li_found_pc
+ 4))
2084 if ((op
& 0x03e00000) >= 0x01a00000)
2086 ev_reg
= GET_SRC_REG (op
);
2087 /* If this is the first vector reg to be saved, or if
2088 it has a lower number than others previously seen,
2089 reupdate the frame info. */
2090 /* We know the contents of r0 from the previous
2092 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2094 fdata
->saved_ev
= ev_reg
;
2095 fdata
->ev_offset
= vr_saved_offset
+ offset
;
2099 vr_saved_offset
= -1;
2104 /* End BookE related instructions. */
2108 /* Not a recognized prologue instruction.
2109 Handle optimizer code motions into the prologue by continuing
2110 the search if we have no valid frame yet or if the return
2111 address is not yet saved in the frame. Also skip instructions
2112 if some of the GPRs expected to be saved are not yet saved. */
2113 if (fdata
->frameless
== 0 && fdata
->nosavedpc
== 0
2114 && fdata
->saved_gpr
!= -1)
2116 unsigned int all_mask
= ~((1U << fdata
->saved_gpr
) - 1);
2118 if ((fdata
->gpr_mask
& all_mask
) == all_mask
)
2122 if (op
== 0x4e800020 /* blr */
2123 || op
== 0x4e800420) /* bctr */
2124 /* Do not scan past epilogue in frameless functions or
2127 if ((op
& 0xf4000000) == 0x40000000) /* bxx */
2128 /* Never skip branches. */
2131 /* Test based on opcode and mask values of
2132 powerpc_opcodes[svc..svcla] in opcodes/ppc-opc.c. */
2133 if ((op
& 0xffff0000) == 0x44000000)
2134 /* Never skip system calls. */
2137 if (num_skip_non_prologue_insns
++ > max_skip_non_prologue_insns
)
2138 /* Do not scan too many insns, scanning insns is expensive with
2142 /* Continue scanning. */
2143 prev_insn_was_prologue_insn
= 0;
2149 /* I have problems with skipping over __main() that I need to address
2150 * sometime. Previously, I used to use misc_function_vector which
2151 * didn't work as well as I wanted to be. -MGO */
2153 /* If the first thing after skipping a prolog is a branch to a function,
2154 this might be a call to an initializer in main(), introduced by gcc2.
2155 We'd like to skip over it as well. Fortunately, xlc does some extra
2156 work before calling a function right after a prologue, thus we can
2157 single out such gcc2 behaviour. */
2160 if ((op
& 0xfc000001) == 0x48000001)
2161 { /* bl foo, an initializer function? */
2162 op
= read_memory_integer (pc
+ 4, 4, byte_order
);
2164 if (op
== 0x4def7b82)
2165 { /* cror 0xf, 0xf, 0xf (nop) */
2167 /* Check and see if we are in main. If so, skip over this
2168 initializer function as well. */
2170 tmp
= find_pc_misc_function (pc
);
2172 && strcmp (misc_function_vector
[tmp
].name
, main_name ()) == 0)
2178 if (pc
== lim_pc
&& lr_reg
>= 0)
2179 fdata
->lr_register
= lr_reg
;
2181 fdata
->offset
= -fdata
->offset
;
2182 return last_prologue_pc
;
2186 rs6000_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2188 struct rs6000_framedata frame
;
2189 CORE_ADDR limit_pc
, func_addr
, func_end_addr
= 0;
2191 /* See if we can determine the end of the prologue via the symbol table.
2192 If so, then return either PC, or the PC after the prologue, whichever
2194 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end_addr
))
2196 CORE_ADDR post_prologue_pc
2197 = skip_prologue_using_sal (gdbarch
, func_addr
);
2198 if (post_prologue_pc
!= 0)
2199 return std::max (pc
, post_prologue_pc
);
2202 /* Can't determine prologue from the symbol table, need to examine
2205 /* Find an upper limit on the function prologue using the debug
2206 information. If the debug information could not be used to provide
2207 that bound, then use an arbitrary large number as the upper bound. */
2208 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
2210 limit_pc
= pc
+ 100; /* Magic. */
2212 /* Do not allow limit_pc to be past the function end, if we know
2213 where that end is... */
2214 if (func_end_addr
&& limit_pc
> func_end_addr
)
2215 limit_pc
= func_end_addr
;
2217 pc
= skip_prologue (gdbarch
, pc
, limit_pc
, &frame
);
2221 /* When compiling for EABI, some versions of GCC emit a call to __eabi
2222 in the prologue of main().
2224 The function below examines the code pointed at by PC and checks to
2225 see if it corresponds to a call to __eabi. If so, it returns the
2226 address of the instruction following that call. Otherwise, it simply
2230 rs6000_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2232 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2236 if (target_read_memory (pc
, buf
, 4))
2238 op
= extract_unsigned_integer (buf
, 4, byte_order
);
2240 if ((op
& BL_MASK
) == BL_INSTRUCTION
)
2242 CORE_ADDR displ
= op
& BL_DISPLACEMENT_MASK
;
2243 CORE_ADDR call_dest
= pc
+ 4 + displ
;
2244 struct bound_minimal_symbol s
= lookup_minimal_symbol_by_pc (call_dest
);
2246 /* We check for ___eabi (three leading underscores) in addition
2247 to __eabi in case the GCC option "-fleading-underscore" was
2248 used to compile the program. */
2249 if (s
.minsym
!= NULL
2250 && s
.minsym
->linkage_name () != NULL
2251 && (strcmp (s
.minsym
->linkage_name (), "__eabi") == 0
2252 || strcmp (s
.minsym
->linkage_name (), "___eabi") == 0))
2258 /* All the ABI's require 16 byte alignment. */
2260 rs6000_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2262 return (addr
& -16);
2265 /* Return whether handle_inferior_event() should proceed through code
2266 starting at PC in function NAME when stepping.
2268 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
2269 handle memory references that are too distant to fit in instructions
2270 generated by the compiler. For example, if 'foo' in the following
2275 is greater than 32767, the linker might replace the lwz with a branch to
2276 somewhere in @FIX1 that does the load in 2 instructions and then branches
2277 back to where execution should continue.
2279 GDB should silently step over @FIX code, just like AIX dbx does.
2280 Unfortunately, the linker uses the "b" instruction for the
2281 branches, meaning that the link register doesn't get set.
2282 Therefore, GDB's usual step_over_function () mechanism won't work.
2284 Instead, use the gdbarch_skip_trampoline_code and
2285 gdbarch_skip_trampoline_code hooks in handle_inferior_event() to skip past
2289 rs6000_in_solib_return_trampoline (struct gdbarch
*gdbarch
,
2290 CORE_ADDR pc
, const char *name
)
2292 return name
&& startswith (name
, "@FIX");
2295 /* Skip code that the user doesn't want to see when stepping:
2297 1. Indirect function calls use a piece of trampoline code to do context
2298 switching, i.e. to set the new TOC table. Skip such code if we are on
2299 its first instruction (as when we have single-stepped to here).
2301 2. Skip shared library trampoline code (which is different from
2302 indirect function call trampolines).
2304 3. Skip bigtoc fixup code.
2306 Result is desired PC to step until, or NULL if we are not in
2307 code that should be skipped. */
2310 rs6000_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
2312 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2313 ppc_gdbarch_tdep
*tdep
= (ppc_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
2314 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2315 unsigned int ii
, op
;
2317 CORE_ADDR solib_target_pc
;
2318 struct bound_minimal_symbol msymbol
;
2320 static unsigned trampoline_code
[] =
2322 0x800b0000, /* l r0,0x0(r11) */
2323 0x90410014, /* st r2,0x14(r1) */
2324 0x7c0903a6, /* mtctr r0 */
2325 0x804b0004, /* l r2,0x4(r11) */
2326 0x816b0008, /* l r11,0x8(r11) */
2327 0x4e800420, /* bctr */
2328 0x4e800020, /* br */
2332 /* Check for bigtoc fixup code. */
2333 msymbol
= lookup_minimal_symbol_by_pc (pc
);
2335 && rs6000_in_solib_return_trampoline (gdbarch
, pc
,
2336 msymbol
.minsym
->linkage_name ()))
2338 /* Double-check that the third instruction from PC is relative "b". */
2339 op
= read_memory_integer (pc
+ 8, 4, byte_order
);
2340 if ((op
& 0xfc000003) == 0x48000000)
2342 /* Extract bits 6-29 as a signed 24-bit relative word address and
2343 add it to the containing PC. */
2344 rel
= ((int)(op
<< 6) >> 6);
2345 return pc
+ 8 + rel
;
2349 /* If pc is in a shared library trampoline, return its target. */
2350 solib_target_pc
= find_solib_trampoline_target (frame
, pc
);
2351 if (solib_target_pc
)
2352 return solib_target_pc
;
2354 for (ii
= 0; trampoline_code
[ii
]; ++ii
)
2356 op
= read_memory_integer (pc
+ (ii
* 4), 4, byte_order
);
2357 if (op
!= trampoline_code
[ii
])
2360 ii
= get_frame_register_unsigned (frame
, 11); /* r11 holds destination
2362 pc
= read_memory_unsigned_integer (ii
, tdep
->wordsize
, byte_order
);
2366 /* ISA-specific vector types. */
2368 static struct type
*
2369 rs6000_builtin_type_vec64 (struct gdbarch
*gdbarch
)
2371 ppc_gdbarch_tdep
*tdep
= (ppc_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
2373 if (!tdep
->ppc_builtin_type_vec64
)
2375 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2377 /* The type we're building is this: */
2379 union __gdb_builtin_type_vec64
2383 int32_t v2_int32
[2];
2384 int16_t v4_int16
[4];
2391 t
= arch_composite_type (gdbarch
,
2392 "__ppc_builtin_type_vec64", TYPE_CODE_UNION
);
2393 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
2394 append_composite_type_field (t
, "v2_float",
2395 init_vector_type (bt
->builtin_float
, 2));
2396 append_composite_type_field (t
, "v2_int32",
2397 init_vector_type (bt
->builtin_int32
, 2));
2398 append_composite_type_field (t
, "v4_int16",
2399 init_vector_type (bt
->builtin_int16
, 4));
2400 append_composite_type_field (t
, "v8_int8",
2401 init_vector_type (bt
->builtin_int8
, 8));
2403 t
->set_is_vector (true);
2404 t
->set_name ("ppc_builtin_type_vec64");
2405 tdep
->ppc_builtin_type_vec64
= t
;
2408 return tdep
->ppc_builtin_type_vec64
;
2411 /* Vector 128 type. */
2413 static struct type
*
2414 rs6000_builtin_type_vec128 (struct gdbarch
*gdbarch
)
2416 ppc_gdbarch_tdep
*tdep
= (ppc_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
2418 if (!tdep
->ppc_builtin_type_vec128
)
2420 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2422 /* The type we're building is this
2424 type = union __ppc_builtin_type_vec128 {
2425 float128_t float128;
2427 double v2_double[2];
2429 int32_t v4_int32[4];
2430 int16_t v8_int16[8];
2431 int8_t v16_int8[16];
2435 /* PPC specific type for IEEE 128-bit float field */
2436 struct type
*t_float128
2437 = arch_float_type (gdbarch
, 128, "float128_t", floatformats_ia64_quad
);
2441 t
= arch_composite_type (gdbarch
,
2442 "__ppc_builtin_type_vec128", TYPE_CODE_UNION
);
2443 append_composite_type_field (t
, "float128", t_float128
);
2444 append_composite_type_field (t
, "uint128", bt
->builtin_uint128
);
2445 append_composite_type_field (t
, "v2_double",
2446 init_vector_type (bt
->builtin_double
, 2));
2447 append_composite_type_field (t
, "v4_float",
2448 init_vector_type (bt
->builtin_float
, 4));
2449 append_composite_type_field (t
, "v4_int32",
2450 init_vector_type (bt
->builtin_int32
, 4));
2451 append_composite_type_field (t
, "v8_int16",
2452 init_vector_type (bt
->builtin_int16
, 8));
2453 append_composite_type_field (t
, "v16_int8",
2454 init_vector_type (bt
->builtin_int8
, 16));
2456 t
->set_is_vector (true);
2457 t
->set_name ("ppc_builtin_type_vec128");
2458 tdep
->ppc_builtin_type_vec128
= t
;
2461 return tdep
->ppc_builtin_type_vec128
;
2464 /* Return the name of register number REGNO, or the empty string if it
2465 is an anonymous register. */
2468 rs6000_register_name (struct gdbarch
*gdbarch
, int regno
)
2470 ppc_gdbarch_tdep
*tdep
= (ppc_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
2472 /* The upper half "registers" have names in the XML description,
2473 but we present only the low GPRs and the full 64-bit registers
2475 if (tdep
->ppc_ev0_upper_regnum
>= 0
2476 && tdep
->ppc_ev0_upper_regnum
<= regno
2477 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
2480 /* Hide the upper halves of the vs0~vs31 registers. */
2481 if (tdep
->ppc_vsr0_regnum
>= 0
2482 && tdep
->ppc_vsr0_upper_regnum
<= regno
2483 && regno
< tdep
->ppc_vsr0_upper_regnum
+ ppc_num_gprs
)
2486 /* Hide the upper halves of the cvs0~cvs31 registers. */
2487 if (PPC_CVSR0_UPPER_REGNUM
<= regno
2488 && regno
< PPC_CVSR0_UPPER_REGNUM
+ ppc_num_gprs
)
2491 /* Check if the SPE pseudo registers are available. */
2492 if (IS_SPE_PSEUDOREG (tdep
, regno
))
2494 static const char *const spe_regnames
[] = {
2495 "ev0", "ev1", "ev2", "ev3", "ev4", "ev5", "ev6", "ev7",
2496 "ev8", "ev9", "ev10", "ev11", "ev12", "ev13", "ev14", "ev15",
2497 "ev16", "ev17", "ev18", "ev19", "ev20", "ev21", "ev22", "ev23",
2498 "ev24", "ev25", "ev26", "ev27", "ev28", "ev29", "ev30", "ev31",
2500 return spe_regnames
[regno
- tdep
->ppc_ev0_regnum
];
2503 /* Check if the decimal128 pseudo-registers are available. */
2504 if (IS_DFP_PSEUDOREG (tdep
, regno
))
2506 static const char *const dfp128_regnames
[] = {
2507 "dl0", "dl1", "dl2", "dl3",
2508 "dl4", "dl5", "dl6", "dl7",
2509 "dl8", "dl9", "dl10", "dl11",
2510 "dl12", "dl13", "dl14", "dl15"
2512 return dfp128_regnames
[regno
- tdep
->ppc_dl0_regnum
];
2515 /* Check if this is a vX alias for a raw vrX vector register. */
2516 if (IS_V_ALIAS_PSEUDOREG (tdep
, regno
))
2518 static const char *const vector_alias_regnames
[] = {
2519 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
2520 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
2521 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
2522 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
2524 return vector_alias_regnames
[regno
- tdep
->ppc_v0_alias_regnum
];
2527 /* Check if this is a VSX pseudo-register. */
2528 if (IS_VSX_PSEUDOREG (tdep
, regno
))
2530 static const char *const vsx_regnames
[] = {
2531 "vs0", "vs1", "vs2", "vs3", "vs4", "vs5", "vs6", "vs7",
2532 "vs8", "vs9", "vs10", "vs11", "vs12", "vs13", "vs14",
2533 "vs15", "vs16", "vs17", "vs18", "vs19", "vs20", "vs21",
2534 "vs22", "vs23", "vs24", "vs25", "vs26", "vs27", "vs28",
2535 "vs29", "vs30", "vs31", "vs32", "vs33", "vs34", "vs35",
2536 "vs36", "vs37", "vs38", "vs39", "vs40", "vs41", "vs42",
2537 "vs43", "vs44", "vs45", "vs46", "vs47", "vs48", "vs49",
2538 "vs50", "vs51", "vs52", "vs53", "vs54", "vs55", "vs56",
2539 "vs57", "vs58", "vs59", "vs60", "vs61", "vs62", "vs63"
2541 return vsx_regnames
[regno
- tdep
->ppc_vsr0_regnum
];
2544 /* Check if the this is a Extended FP pseudo-register. */
2545 if (IS_EFP_PSEUDOREG (tdep
, regno
))
2547 static const char *const efpr_regnames
[] = {
2548 "f32", "f33", "f34", "f35", "f36", "f37", "f38",
2549 "f39", "f40", "f41", "f42", "f43", "f44", "f45",
2550 "f46", "f47", "f48", "f49", "f50", "f51",
2551 "f52", "f53", "f54", "f55", "f56", "f57",
2552 "f58", "f59", "f60", "f61", "f62", "f63"
2554 return efpr_regnames
[regno
- tdep
->ppc_efpr0_regnum
];
2557 /* Check if this is a Checkpointed DFP pseudo-register. */
2558 if (IS_CDFP_PSEUDOREG (tdep
, regno
))
2560 static const char *const cdfp128_regnames
[] = {
2561 "cdl0", "cdl1", "cdl2", "cdl3",
2562 "cdl4", "cdl5", "cdl6", "cdl7",
2563 "cdl8", "cdl9", "cdl10", "cdl11",
2564 "cdl12", "cdl13", "cdl14", "cdl15"
2566 return cdfp128_regnames
[regno
- tdep
->ppc_cdl0_regnum
];
2569 /* Check if this is a Checkpointed VSX pseudo-register. */
2570 if (IS_CVSX_PSEUDOREG (tdep
, regno
))
2572 static const char *const cvsx_regnames
[] = {
2573 "cvs0", "cvs1", "cvs2", "cvs3", "cvs4", "cvs5", "cvs6", "cvs7",
2574 "cvs8", "cvs9", "cvs10", "cvs11", "cvs12", "cvs13", "cvs14",
2575 "cvs15", "cvs16", "cvs17", "cvs18", "cvs19", "cvs20", "cvs21",
2576 "cvs22", "cvs23", "cvs24", "cvs25", "cvs26", "cvs27", "cvs28",
2577 "cvs29", "cvs30", "cvs31", "cvs32", "cvs33", "cvs34", "cvs35",
2578 "cvs36", "cvs37", "cvs38", "cvs39", "cvs40", "cvs41", "cvs42",
2579 "cvs43", "cvs44", "cvs45", "cvs46", "cvs47", "cvs48", "cvs49",
2580 "cvs50", "cvs51", "cvs52", "cvs53", "cvs54", "cvs55", "cvs56",
2581 "cvs57", "cvs58", "cvs59", "cvs60", "cvs61", "cvs62", "cvs63"
2583 return cvsx_regnames
[regno
- tdep
->ppc_cvsr0_regnum
];
2586 /* Check if the this is a Checkpointed Extended FP pseudo-register. */
2587 if (IS_CEFP_PSEUDOREG (tdep
, regno
))
2589 static const char *const cefpr_regnames
[] = {
2590 "cf32", "cf33", "cf34", "cf35", "cf36", "cf37", "cf38",
2591 "cf39", "cf40", "cf41", "cf42", "cf43", "cf44", "cf45",
2592 "cf46", "cf47", "cf48", "cf49", "cf50", "cf51",
2593 "cf52", "cf53", "cf54", "cf55", "cf56", "cf57",
2594 "cf58", "cf59", "cf60", "cf61", "cf62", "cf63"
2596 return cefpr_regnames
[regno
- tdep
->ppc_cefpr0_regnum
];
2599 return tdesc_register_name (gdbarch
, regno
);
2602 /* Return the GDB type object for the "standard" data type of data in
2605 static struct type
*
2606 rs6000_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2608 ppc_gdbarch_tdep
*tdep
= (ppc_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
2610 /* These are the e500 pseudo-registers. */
2611 if (IS_SPE_PSEUDOREG (tdep
, regnum
))
2612 return rs6000_builtin_type_vec64 (gdbarch
);
2613 else if (IS_DFP_PSEUDOREG (tdep
, regnum
)
2614 || IS_CDFP_PSEUDOREG (tdep
, regnum
))
2615 /* PPC decimal128 pseudo-registers. */
2616 return builtin_type (gdbarch
)->builtin_declong
;
2617 else if (IS_V_ALIAS_PSEUDOREG (tdep
, regnum
))
2618 return gdbarch_register_type (gdbarch
,
2619 tdep
->ppc_vr0_regnum
2621 - tdep
->ppc_v0_alias_regnum
));
2622 else if (IS_VSX_PSEUDOREG (tdep
, regnum
)
2623 || IS_CVSX_PSEUDOREG (tdep
, regnum
))
2624 /* POWER7 VSX pseudo-registers. */
2625 return rs6000_builtin_type_vec128 (gdbarch
);
2626 else if (IS_EFP_PSEUDOREG (tdep
, regnum
)
2627 || IS_CEFP_PSEUDOREG (tdep
, regnum
))
2628 /* POWER7 Extended FP pseudo-registers. */
2629 return builtin_type (gdbarch
)->builtin_double
;
2631 internal_error (__FILE__
, __LINE__
,
2632 _("rs6000_pseudo_register_type: "
2633 "called on unexpected register '%s' (%d)"),
2634 gdbarch_register_name (gdbarch
, regnum
), regnum
);
2637 /* Check if REGNUM is a member of REGGROUP. We only need to handle
2638 the vX aliases for the vector registers by always returning false
2639 to avoid duplicated information in "info register vector/all",
2640 since the raw vrX registers will already show in these cases. For
2641 other pseudo-registers we use the default membership function. */
2644 rs6000_pseudo_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
2645 struct reggroup
*group
)
2647 ppc_gdbarch_tdep
*tdep
= (ppc_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
2649 if (IS_V_ALIAS_PSEUDOREG (tdep
, regnum
))
2652 return default_register_reggroup_p (gdbarch
, regnum
, group
);
2655 /* The register format for RS/6000 floating point registers is always
2656 double, we need a conversion if the memory format is float. */
2659 rs6000_convert_register_p (struct gdbarch
*gdbarch
, int regnum
,
2662 ppc_gdbarch_tdep
*tdep
= (ppc_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
2664 return (tdep
->ppc_fp0_regnum
>= 0
2665 && regnum
>= tdep
->ppc_fp0_regnum
2666 && regnum
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
2667 && type
->code () == TYPE_CODE_FLT
2668 && TYPE_LENGTH (type
)
2669 != TYPE_LENGTH (builtin_type (gdbarch
)->builtin_double
));
2673 rs6000_register_to_value (struct frame_info
*frame
,
2677 int *optimizedp
, int *unavailablep
)
2679 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2680 gdb_byte from
[PPC_MAX_REGISTER_SIZE
];
2682 gdb_assert (type
->code () == TYPE_CODE_FLT
);
2684 if (!get_frame_register_bytes (frame
, regnum
, 0,
2685 gdb::make_array_view (from
,
2686 register_size (gdbarch
,
2688 optimizedp
, unavailablep
))
2691 target_float_convert (from
, builtin_type (gdbarch
)->builtin_double
,
2693 *optimizedp
= *unavailablep
= 0;
2698 rs6000_value_to_register (struct frame_info
*frame
,
2701 const gdb_byte
*from
)
2703 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2704 gdb_byte to
[PPC_MAX_REGISTER_SIZE
];
2706 gdb_assert (type
->code () == TYPE_CODE_FLT
);
2708 target_float_convert (from
, type
,
2709 to
, builtin_type (gdbarch
)->builtin_double
);
2710 put_frame_register (frame
, regnum
, to
);
2713 /* The type of a function that moves the value of REG between CACHE
2714 or BUF --- in either direction. */
2715 typedef enum register_status (*move_ev_register_func
) (struct regcache
*,
2718 /* Move SPE vector register values between a 64-bit buffer and the two
2719 32-bit raw register halves in a regcache. This function handles
2720 both splitting a 64-bit value into two 32-bit halves, and joining
2721 two halves into a whole 64-bit value, depending on the function
2722 passed as the MOVE argument.
2724 EV_REG must be the number of an SPE evN vector register --- a
2725 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a
2728 Call MOVE once for each 32-bit half of that register, passing
2729 REGCACHE, the number of the raw register corresponding to that
2730 half, and the address of the appropriate half of BUFFER.
2732 For example, passing 'regcache_raw_read' as the MOVE function will
2733 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing
2734 'regcache_raw_supply' will supply the contents of BUFFER to the
2735 appropriate pair of raw registers in REGCACHE.
2737 You may need to cast away some 'const' qualifiers when passing
2738 MOVE, since this function can't tell at compile-time which of
2739 REGCACHE or BUFFER is acting as the source of the data. If C had
2740 co-variant type qualifiers, ... */
2742 static enum register_status
2743 e500_move_ev_register (move_ev_register_func move
,
2744 struct regcache
*regcache
, int ev_reg
, void *buffer
)
2746 struct gdbarch
*arch
= regcache
->arch ();
2747 ppc_gdbarch_tdep
*tdep
= (ppc_gdbarch_tdep
*) gdbarch_tdep (arch
);
2749 gdb_byte
*byte_buffer
= (gdb_byte
*) buffer
;
2750 enum register_status status
;
2752 gdb_assert (IS_SPE_PSEUDOREG (tdep
, ev_reg
));
2754 reg_index
= ev_reg
- tdep
->ppc_ev0_regnum
;
2756 if (gdbarch_byte_order (arch
) == BFD_ENDIAN_BIG
)
2758 status
= move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2760 if (status
== REG_VALID
)
2761 status
= move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
,
2766 status
= move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
, byte_buffer
);
2767 if (status
== REG_VALID
)
2768 status
= move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2775 static enum register_status
2776 do_regcache_raw_write (struct regcache
*regcache
, int regnum
, void *buffer
)
2778 regcache
->raw_write (regnum
, (const gdb_byte
*) buffer
);
2783 static enum register_status
2784 e500_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2785 int ev_reg
, gdb_byte
*buffer
)
2787 struct gdbarch
*arch
= regcache
->arch ();
2788 ppc_gdbarch_tdep
*tdep
= (ppc_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
2790 enum register_status status
;
2792 gdb_assert (IS_SPE_PSEUDOREG (tdep
, ev_reg
));
2794 reg_index
= ev_reg
- tdep
->ppc_ev0_regnum
;
2796 if (gdbarch_byte_order (arch
) == BFD_ENDIAN_BIG
)
2798 status
= regcache
->raw_read (tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2800 if (status
== REG_VALID
)
2801 status
= regcache
->raw_read (tdep
->ppc_gp0_regnum
+ reg_index
,
2806 status
= regcache
->raw_read (tdep
->ppc_gp0_regnum
+ reg_index
, buffer
);
2807 if (status
== REG_VALID
)
2808 status
= regcache
->raw_read (tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2817 e500_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2818 int reg_nr
, const gdb_byte
*buffer
)
2820 e500_move_ev_register (do_regcache_raw_write
, regcache
,
2821 reg_nr
, (void *) buffer
);
2824 /* Read method for DFP pseudo-registers. */
2825 static enum register_status
2826 dfp_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2827 int reg_nr
, gdb_byte
*buffer
)
2829 ppc_gdbarch_tdep
*tdep
= (ppc_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
2831 enum register_status status
;
2833 if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2835 reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2836 fp0
= PPC_F0_REGNUM
;
2840 gdb_assert (IS_CDFP_PSEUDOREG (tdep
, reg_nr
));
2842 reg_index
= reg_nr
- tdep
->ppc_cdl0_regnum
;
2843 fp0
= PPC_CF0_REGNUM
;
2846 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2848 /* Read two FP registers to form a whole dl register. */
2849 status
= regcache
->raw_read (fp0
+ 2 * reg_index
, buffer
);
2850 if (status
== REG_VALID
)
2851 status
= regcache
->raw_read (fp0
+ 2 * reg_index
+ 1,
2856 status
= regcache
->raw_read (fp0
+ 2 * reg_index
+ 1, buffer
);
2857 if (status
== REG_VALID
)
2858 status
= regcache
->raw_read (fp0
+ 2 * reg_index
, buffer
+ 8);
2864 /* Write method for DFP pseudo-registers. */
2866 dfp_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2867 int reg_nr
, const gdb_byte
*buffer
)
2869 ppc_gdbarch_tdep
*tdep
= (ppc_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
2872 if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2874 reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2875 fp0
= PPC_F0_REGNUM
;
2879 gdb_assert (IS_CDFP_PSEUDOREG (tdep
, reg_nr
));
2881 reg_index
= reg_nr
- tdep
->ppc_cdl0_regnum
;
2882 fp0
= PPC_CF0_REGNUM
;
2885 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2887 /* Write each half of the dl register into a separate
2889 regcache
->raw_write (fp0
+ 2 * reg_index
, buffer
);
2890 regcache
->raw_write (fp0
+ 2 * reg_index
+ 1, buffer
+ 8);
2894 regcache
->raw_write (fp0
+ 2 * reg_index
+ 1, buffer
);
2895 regcache
->raw_write (fp0
+ 2 * reg_index
, buffer
+ 8);
2899 /* Read method for the vX aliases for the raw vrX registers. */
2901 static enum register_status
2902 v_alias_pseudo_register_read (struct gdbarch
*gdbarch
,
2903 readable_regcache
*regcache
, int reg_nr
,
2906 ppc_gdbarch_tdep
*tdep
= (ppc_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
2907 gdb_assert (IS_V_ALIAS_PSEUDOREG (tdep
, reg_nr
));
2909 return regcache
->raw_read (tdep
->ppc_vr0_regnum
2910 + (reg_nr
- tdep
->ppc_v0_alias_regnum
),
2914 /* Write method for the vX aliases for the raw vrX registers. */
2917 v_alias_pseudo_register_write (struct gdbarch
*gdbarch
,
2918 struct regcache
*regcache
,
2919 int reg_nr
, const gdb_byte
*buffer
)
2921 ppc_gdbarch_tdep
*tdep
= (ppc_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
2922 gdb_assert (IS_V_ALIAS_PSEUDOREG (tdep
, reg_nr
));
2924 regcache
->raw_write (tdep
->ppc_vr0_regnum
2925 + (reg_nr
- tdep
->ppc_v0_alias_regnum
), buffer
);
2928 /* Read method for POWER7 VSX pseudo-registers. */
2929 static enum register_status
2930 vsx_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2931 int reg_nr
, gdb_byte
*buffer
)
2933 ppc_gdbarch_tdep
*tdep
= (ppc_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
2934 int reg_index
, vr0
, fp0
, vsr0_upper
;
2935 enum register_status status
;
2937 if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
2939 reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
2940 vr0
= PPC_VR0_REGNUM
;
2941 fp0
= PPC_F0_REGNUM
;
2942 vsr0_upper
= PPC_VSR0_UPPER_REGNUM
;
2946 gdb_assert (IS_CVSX_PSEUDOREG (tdep
, reg_nr
));
2948 reg_index
= reg_nr
- tdep
->ppc_cvsr0_regnum
;
2949 vr0
= PPC_CVR0_REGNUM
;
2950 fp0
= PPC_CF0_REGNUM
;
2951 vsr0_upper
= PPC_CVSR0_UPPER_REGNUM
;
2954 /* Read the portion that overlaps the VMX registers. */
2956 status
= regcache
->raw_read (vr0
+ reg_index
- 32, buffer
);
2958 /* Read the portion that overlaps the FPR registers. */
2959 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2961 status
= regcache
->raw_read (fp0
+ reg_index
, buffer
);
2962 if (status
== REG_VALID
)
2963 status
= regcache
->raw_read (vsr0_upper
+ reg_index
,
2968 status
= regcache
->raw_read (fp0
+ reg_index
, buffer
+ 8);
2969 if (status
== REG_VALID
)
2970 status
= regcache
->raw_read (vsr0_upper
+ reg_index
, buffer
);
2976 /* Write method for POWER7 VSX pseudo-registers. */
2978 vsx_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2979 int reg_nr
, const gdb_byte
*buffer
)
2981 ppc_gdbarch_tdep
*tdep
= (ppc_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
2982 int reg_index
, vr0
, fp0
, vsr0_upper
;
2984 if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
2986 reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
2987 vr0
= PPC_VR0_REGNUM
;
2988 fp0
= PPC_F0_REGNUM
;
2989 vsr0_upper
= PPC_VSR0_UPPER_REGNUM
;
2993 gdb_assert (IS_CVSX_PSEUDOREG (tdep
, reg_nr
));
2995 reg_index
= reg_nr
- tdep
->ppc_cvsr0_regnum
;
2996 vr0
= PPC_CVR0_REGNUM
;
2997 fp0
= PPC_CF0_REGNUM
;
2998 vsr0_upper
= PPC_CVSR0_UPPER_REGNUM
;
3001 /* Write the portion that overlaps the VMX registers. */
3003 regcache
->raw_write (vr0
+ reg_index
- 32, buffer
);
3005 /* Write the portion that overlaps the FPR registers. */
3006 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
3008 regcache
->raw_write (fp0
+ reg_index
, buffer
);
3009 regcache
->raw_write (vsr0_upper
+ reg_index
, buffer
+ 8);
3013 regcache
->raw_write (fp0
+ reg_index
, buffer
+ 8);
3014 regcache
->raw_write (vsr0_upper
+ reg_index
, buffer
);
3018 /* Read method for POWER7 Extended FP pseudo-registers. */
3019 static enum register_status
3020 efp_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
3021 int reg_nr
, gdb_byte
*buffer
)
3023 ppc_gdbarch_tdep
*tdep
= (ppc_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
3026 if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
3028 reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
3029 vr0
= PPC_VR0_REGNUM
;
3033 gdb_assert (IS_CEFP_PSEUDOREG (tdep
, reg_nr
));
3035 reg_index
= reg_nr
- tdep
->ppc_cefpr0_regnum
;
3036 vr0
= PPC_CVR0_REGNUM
;
3039 int offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 0 : 8;
3041 /* Read the portion that overlaps the VMX register. */
3042 return regcache
->raw_read_part (vr0
+ reg_index
, offset
,
3043 register_size (gdbarch
, reg_nr
),
3047 /* Write method for POWER7 Extended FP pseudo-registers. */
3049 efp_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
3050 int reg_nr
, const gdb_byte
*buffer
)
3052 ppc_gdbarch_tdep
*tdep
= (ppc_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
3054 int offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 0 : 8;
3056 if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
3058 reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
3059 vr0
= PPC_VR0_REGNUM
;
3063 gdb_assert (IS_CEFP_PSEUDOREG (tdep
, reg_nr
));
3065 reg_index
= reg_nr
- tdep
->ppc_cefpr0_regnum
;
3066 vr0
= PPC_CVR0_REGNUM
;
3068 /* The call to raw_write_part fails silently if the initial read
3069 of the read-update-write sequence returns an invalid status,
3070 so we check this manually and throw an error if needed. */
3071 regcache
->raw_update (vr0
+ reg_index
);
3072 if (regcache
->get_register_status (vr0
+ reg_index
) != REG_VALID
)
3073 error (_("Cannot write to the checkpointed EFP register, "
3074 "the corresponding vector register is unavailable."));
3077 /* Write the portion that overlaps the VMX register. */
3078 regcache
->raw_write_part (vr0
+ reg_index
, offset
,
3079 register_size (gdbarch
, reg_nr
), buffer
);
3082 static enum register_status
3083 rs6000_pseudo_register_read (struct gdbarch
*gdbarch
,
3084 readable_regcache
*regcache
,
3085 int reg_nr
, gdb_byte
*buffer
)
3087 struct gdbarch
*regcache_arch
= regcache
->arch ();
3088 ppc_gdbarch_tdep
*tdep
= (ppc_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
3090 gdb_assert (regcache_arch
== gdbarch
);
3092 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
3093 return e500_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
3094 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
)
3095 || IS_CDFP_PSEUDOREG (tdep
, reg_nr
))
3096 return dfp_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
3097 else if (IS_V_ALIAS_PSEUDOREG (tdep
, reg_nr
))
3098 return v_alias_pseudo_register_read (gdbarch
, regcache
, reg_nr
,
3100 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
)
3101 || IS_CVSX_PSEUDOREG (tdep
, reg_nr
))
3102 return vsx_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
3103 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
)
3104 || IS_CEFP_PSEUDOREG (tdep
, reg_nr
))
3105 return efp_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
3107 internal_error (__FILE__
, __LINE__
,
3108 _("rs6000_pseudo_register_read: "
3109 "called on unexpected register '%s' (%d)"),
3110 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
3114 rs6000_pseudo_register_write (struct gdbarch
*gdbarch
,
3115 struct regcache
*regcache
,
3116 int reg_nr
, const gdb_byte
*buffer
)
3118 struct gdbarch
*regcache_arch
= regcache
->arch ();
3119 ppc_gdbarch_tdep
*tdep
= (ppc_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
3121 gdb_assert (regcache_arch
== gdbarch
);
3123 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
3124 e500_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
3125 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
)
3126 || IS_CDFP_PSEUDOREG (tdep
, reg_nr
))
3127 dfp_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
3128 else if (IS_V_ALIAS_PSEUDOREG (tdep
, reg_nr
))
3129 v_alias_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
3130 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
)
3131 || IS_CVSX_PSEUDOREG (tdep
, reg_nr
))
3132 vsx_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
3133 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
)
3134 || IS_CEFP_PSEUDOREG (tdep
, reg_nr
))
3135 efp_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
3137 internal_error (__FILE__
, __LINE__
,
3138 _("rs6000_pseudo_register_write: "
3139 "called on unexpected register '%s' (%d)"),
3140 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
3143 /* Set the register mask in AX with the registers that form the DFP or
3144 checkpointed DFP pseudo-register REG_NR. */
3147 dfp_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
3148 struct agent_expr
*ax
, int reg_nr
)
3150 ppc_gdbarch_tdep
*tdep
= (ppc_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
3153 if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
3155 reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
3156 fp0
= PPC_F0_REGNUM
;
3160 gdb_assert (IS_CDFP_PSEUDOREG (tdep
, reg_nr
));
3162 reg_index
= reg_nr
- tdep
->ppc_cdl0_regnum
;
3163 fp0
= PPC_CF0_REGNUM
;
3166 ax_reg_mask (ax
, fp0
+ 2 * reg_index
);
3167 ax_reg_mask (ax
, fp0
+ 2 * reg_index
+ 1);
3170 /* Set the register mask in AX with the raw vector register that
3171 corresponds to its REG_NR alias. */
3174 v_alias_pseudo_register_collect (struct gdbarch
*gdbarch
,
3175 struct agent_expr
*ax
, int reg_nr
)
3177 ppc_gdbarch_tdep
*tdep
= (ppc_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
3178 gdb_assert (IS_V_ALIAS_PSEUDOREG (tdep
, reg_nr
));
3180 ax_reg_mask (ax
, tdep
->ppc_vr0_regnum
3181 + (reg_nr
- tdep
->ppc_v0_alias_regnum
));
3184 /* Set the register mask in AX with the registers that form the VSX or
3185 checkpointed VSX pseudo-register REG_NR. */
3188 vsx_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
3189 struct agent_expr
*ax
, int reg_nr
)
3191 ppc_gdbarch_tdep
*tdep
= (ppc_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
3192 int reg_index
, vr0
, fp0
, vsr0_upper
;
3194 if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
3196 reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
3197 vr0
= PPC_VR0_REGNUM
;
3198 fp0
= PPC_F0_REGNUM
;
3199 vsr0_upper
= PPC_VSR0_UPPER_REGNUM
;
3203 gdb_assert (IS_CVSX_PSEUDOREG (tdep
, reg_nr
));
3205 reg_index
= reg_nr
- tdep
->ppc_cvsr0_regnum
;
3206 vr0
= PPC_CVR0_REGNUM
;
3207 fp0
= PPC_CF0_REGNUM
;
3208 vsr0_upper
= PPC_CVSR0_UPPER_REGNUM
;
3213 ax_reg_mask (ax
, vr0
+ reg_index
- 32);
3217 ax_reg_mask (ax
, fp0
+ reg_index
);
3218 ax_reg_mask (ax
, vsr0_upper
+ reg_index
);
3222 /* Set the register mask in AX with the register that corresponds to
3223 the EFP or checkpointed EFP pseudo-register REG_NR. */
3226 efp_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
3227 struct agent_expr
*ax
, int reg_nr
)
3229 ppc_gdbarch_tdep
*tdep
= (ppc_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
3232 if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
3234 reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
3235 vr0
= PPC_VR0_REGNUM
;
3239 gdb_assert (IS_CEFP_PSEUDOREG (tdep
, reg_nr
));
3241 reg_index
= reg_nr
- tdep
->ppc_cefpr0_regnum
;
3242 vr0
= PPC_CVR0_REGNUM
;
3245 ax_reg_mask (ax
, vr0
+ reg_index
);
3249 rs6000_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
3250 struct agent_expr
*ax
, int reg_nr
)
3252 ppc_gdbarch_tdep
*tdep
= (ppc_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
3253 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
3255 int reg_index
= reg_nr
- tdep
->ppc_ev0_regnum
;
3256 ax_reg_mask (ax
, tdep
->ppc_gp0_regnum
+ reg_index
);
3257 ax_reg_mask (ax
, tdep
->ppc_ev0_upper_regnum
+ reg_index
);
3259 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
)
3260 || IS_CDFP_PSEUDOREG (tdep
, reg_nr
))
3262 dfp_ax_pseudo_register_collect (gdbarch
, ax
, reg_nr
);
3264 else if (IS_V_ALIAS_PSEUDOREG (tdep
, reg_nr
))
3266 v_alias_pseudo_register_collect (gdbarch
, ax
, reg_nr
);
3268 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
)
3269 || IS_CVSX_PSEUDOREG (tdep
, reg_nr
))
3271 vsx_ax_pseudo_register_collect (gdbarch
, ax
, reg_nr
);
3273 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
)
3274 || IS_CEFP_PSEUDOREG (tdep
, reg_nr
))
3276 efp_ax_pseudo_register_collect (gdbarch
, ax
, reg_nr
);
3279 internal_error (__FILE__
, __LINE__
,
3280 _("rs6000_pseudo_register_collect: "
3281 "called on unexpected register '%s' (%d)"),
3282 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
3288 rs6000_gen_return_address (struct gdbarch
*gdbarch
,
3289 struct agent_expr
*ax
, struct axs_value
*value
,
3292 ppc_gdbarch_tdep
*tdep
= (ppc_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
3293 value
->type
= register_type (gdbarch
, tdep
->ppc_lr_regnum
);
3294 value
->kind
= axs_lvalue_register
;
3295 value
->u
.reg
= tdep
->ppc_lr_regnum
;
3299 /* Convert a DBX STABS register number to a GDB register number. */
3301 rs6000_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
3303 ppc_gdbarch_tdep
*tdep
= (ppc_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
3305 if (0 <= num
&& num
<= 31)
3306 return tdep
->ppc_gp0_regnum
+ num
;
3307 else if (32 <= num
&& num
<= 63)
3308 /* FIXME: jimb/2004-05-05: What should we do when the debug info
3309 specifies registers the architecture doesn't have? Our
3310 callers don't check the value we return. */
3311 return tdep
->ppc_fp0_regnum
+ (num
- 32);
3312 else if (77 <= num
&& num
<= 108)
3313 return tdep
->ppc_vr0_regnum
+ (num
- 77);
3314 else if (1200 <= num
&& num
< 1200 + 32)
3315 return tdep
->ppc_ev0_upper_regnum
+ (num
- 1200);
3320 return tdep
->ppc_mq_regnum
;
3322 return tdep
->ppc_lr_regnum
;
3324 return tdep
->ppc_ctr_regnum
;
3326 return tdep
->ppc_xer_regnum
;
3328 return tdep
->ppc_vrsave_regnum
;
3330 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
3332 return tdep
->ppc_acc_regnum
;
3334 return tdep
->ppc_spefscr_regnum
;
3341 /* Convert a Dwarf 2 register number to a GDB register number. */
3343 rs6000_dwarf2_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
3345 ppc_gdbarch_tdep
*tdep
= (ppc_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
3347 if (0 <= num
&& num
<= 31)
3348 return tdep
->ppc_gp0_regnum
+ num
;
3349 else if (32 <= num
&& num
<= 63)
3350 /* FIXME: jimb/2004-05-05: What should we do when the debug info
3351 specifies registers the architecture doesn't have? Our
3352 callers don't check the value we return. */
3353 return tdep
->ppc_fp0_regnum
+ (num
- 32);
3354 else if (1124 <= num
&& num
< 1124 + 32)
3355 return tdep
->ppc_vr0_regnum
+ (num
- 1124);
3356 else if (1200 <= num
&& num
< 1200 + 32)
3357 return tdep
->ppc_ev0_upper_regnum
+ (num
- 1200);
3362 return tdep
->ppc_cr_regnum
;
3364 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
3366 return tdep
->ppc_acc_regnum
;
3368 return tdep
->ppc_mq_regnum
;
3370 return tdep
->ppc_xer_regnum
;
3372 return tdep
->ppc_lr_regnum
;
3374 return tdep
->ppc_ctr_regnum
;
3376 return tdep
->ppc_vrsave_regnum
;
3378 return tdep
->ppc_spefscr_regnum
;
3381 /* Unknown DWARF register number. */
3385 /* Translate a .eh_frame register to DWARF register, or adjust a
3386 .debug_frame register. */
3389 rs6000_adjust_frame_regnum (struct gdbarch
*gdbarch
, int num
, int eh_frame_p
)
3391 /* GCC releases before 3.4 use GCC internal register numbering in
3392 .debug_frame (and .debug_info, et cetera). The numbering is
3393 different from the standard SysV numbering for everything except
3394 for GPRs and FPRs. We can not detect this problem in most cases
3395 - to get accurate debug info for variables living in lr, ctr, v0,
3396 et cetera, use a newer version of GCC. But we must detect
3397 one important case - lr is in column 65 in .debug_frame output,
3400 GCC 3.4, and the "hammer" branch, have a related problem. They
3401 record lr register saves in .debug_frame as 108, but still record
3402 the return column as 65. We fix that up too.
3404 We can do this because 65 is assigned to fpsr, and GCC never
3405 generates debug info referring to it. To add support for
3406 handwritten debug info that restores fpsr, we would need to add a
3407 producer version check to this. */
3416 /* .eh_frame is GCC specific. For binary compatibility, it uses GCC
3417 internal register numbering; translate that to the standard DWARF2
3418 register numbering. */
3419 if (0 <= num
&& num
<= 63) /* r0-r31,fp0-fp31 */
3421 else if (68 <= num
&& num
<= 75) /* cr0-cr8 */
3422 return num
- 68 + 86;
3423 else if (77 <= num
&& num
<= 108) /* vr0-vr31 */
3424 return num
- 77 + 1124;
3436 case 109: /* vrsave */
3438 case 110: /* vscr */
3440 case 111: /* spe_acc */
3442 case 112: /* spefscr */
3450 /* Handling the various POWER/PowerPC variants. */
3452 /* Information about a particular processor variant. */
3456 /* Name of this variant. */
3459 /* English description of the variant. */
3460 const char *description
;
3462 /* bfd_arch_info.arch corresponding to variant. */
3463 enum bfd_architecture arch
;
3465 /* bfd_arch_info.mach corresponding to variant. */
3468 /* Target description for this variant. */
3469 struct target_desc
**tdesc
;
3472 static struct ppc_variant variants
[] =
3474 {"powerpc", "PowerPC user-level", bfd_arch_powerpc
,
3475 bfd_mach_ppc
, &tdesc_powerpc_altivec32
},
3476 {"power", "POWER user-level", bfd_arch_rs6000
,
3477 bfd_mach_rs6k
, &tdesc_rs6000
},
3478 {"403", "IBM PowerPC 403", bfd_arch_powerpc
,
3479 bfd_mach_ppc_403
, &tdesc_powerpc_403
},
3480 {"405", "IBM PowerPC 405", bfd_arch_powerpc
,
3481 bfd_mach_ppc_405
, &tdesc_powerpc_405
},
3482 {"601", "Motorola PowerPC 601", bfd_arch_powerpc
,
3483 bfd_mach_ppc_601
, &tdesc_powerpc_601
},
3484 {"602", "Motorola PowerPC 602", bfd_arch_powerpc
,
3485 bfd_mach_ppc_602
, &tdesc_powerpc_602
},
3486 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc
,
3487 bfd_mach_ppc_603
, &tdesc_powerpc_603
},
3488 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc
,
3489 604, &tdesc_powerpc_604
},
3490 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc
,
3491 bfd_mach_ppc_403gc
, &tdesc_powerpc_403gc
},
3492 {"505", "Motorola PowerPC 505", bfd_arch_powerpc
,
3493 bfd_mach_ppc_505
, &tdesc_powerpc_505
},
3494 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc
,
3495 bfd_mach_ppc_860
, &tdesc_powerpc_860
},
3496 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc
,
3497 bfd_mach_ppc_750
, &tdesc_powerpc_750
},
3498 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc
,
3499 bfd_mach_ppc_7400
, &tdesc_powerpc_7400
},
3500 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc
,
3501 bfd_mach_ppc_e500
, &tdesc_powerpc_e500
},
3504 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc
,
3505 bfd_mach_ppc64
, &tdesc_powerpc_altivec64
},
3506 {"620", "Motorola PowerPC 620", bfd_arch_powerpc
,
3507 bfd_mach_ppc_620
, &tdesc_powerpc_64
},
3508 {"630", "Motorola PowerPC 630", bfd_arch_powerpc
,
3509 bfd_mach_ppc_630
, &tdesc_powerpc_64
},
3510 {"a35", "PowerPC A35", bfd_arch_powerpc
,
3511 bfd_mach_ppc_a35
, &tdesc_powerpc_64
},
3512 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc
,
3513 bfd_mach_ppc_rs64ii
, &tdesc_powerpc_64
},
3514 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc
,
3515 bfd_mach_ppc_rs64iii
, &tdesc_powerpc_64
},
3517 /* FIXME: I haven't checked the register sets of the following. */
3518 {"rs1", "IBM POWER RS1", bfd_arch_rs6000
,
3519 bfd_mach_rs6k_rs1
, &tdesc_rs6000
},
3520 {"rsc", "IBM POWER RSC", bfd_arch_rs6000
,
3521 bfd_mach_rs6k_rsc
, &tdesc_rs6000
},
3522 {"rs2", "IBM POWER RS2", bfd_arch_rs6000
,
3523 bfd_mach_rs6k_rs2
, &tdesc_rs6000
},
3525 {0, 0, (enum bfd_architecture
) 0, 0, 0}
3528 /* Return the variant corresponding to architecture ARCH and machine number
3529 MACH. If no such variant exists, return null. */
3531 static const struct ppc_variant
*
3532 find_variant_by_arch (enum bfd_architecture arch
, unsigned long mach
)
3534 const struct ppc_variant
*v
;
3536 for (v
= variants
; v
->name
; v
++)
3537 if (arch
== v
->arch
&& mach
== v
->mach
)
3545 struct rs6000_frame_cache
3548 CORE_ADDR initial_sp
;
3549 trad_frame_saved_reg
*saved_regs
;
3551 /* Set BASE_P to true if this frame cache is properly initialized.
3552 Otherwise set to false because some registers or memory cannot
3555 /* Cache PC for building unavailable frame. */
3559 static struct rs6000_frame_cache
*
3560 rs6000_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3562 struct rs6000_frame_cache
*cache
;
3563 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3564 ppc_gdbarch_tdep
*tdep
= (ppc_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
3565 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3566 struct rs6000_framedata fdata
;
3567 int wordsize
= tdep
->wordsize
;
3568 CORE_ADDR func
= 0, pc
= 0;
3570 if ((*this_cache
) != NULL
)
3571 return (struct rs6000_frame_cache
*) (*this_cache
);
3572 cache
= FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache
);
3573 (*this_cache
) = cache
;
3575 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3579 func
= get_frame_func (this_frame
);
3581 pc
= get_frame_pc (this_frame
);
3582 skip_prologue (gdbarch
, func
, pc
, &fdata
);
3584 /* Figure out the parent's stack pointer. */
3586 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
3587 address of the current frame. Things might be easier if the
3588 ->frame pointed to the outer-most address of the frame. In
3589 the mean time, the address of the prev frame is used as the
3590 base address of this frame. */
3591 cache
->base
= get_frame_register_unsigned
3592 (this_frame
, gdbarch_sp_regnum (gdbarch
));
3594 catch (const gdb_exception_error
&ex
)
3596 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
3598 return (struct rs6000_frame_cache
*) (*this_cache
);
3601 /* If the function appears to be frameless, check a couple of likely
3602 indicators that we have simply failed to find the frame setup.
3603 Two common cases of this are missing symbols (i.e.
3604 get_frame_func returns the wrong address or 0), and assembly
3605 stubs which have a fast exit path but set up a frame on the slow
3608 If the LR appears to return to this function, then presume that
3609 we have an ABI compliant frame that we failed to find. */
3610 if (fdata
.frameless
&& fdata
.lr_offset
== 0)
3615 saved_lr
= get_frame_register_unsigned (this_frame
, tdep
->ppc_lr_regnum
);
3616 if (func
== 0 && saved_lr
== pc
)
3620 CORE_ADDR saved_func
= get_pc_function_start (saved_lr
);
3621 if (func
== saved_func
)
3627 fdata
.frameless
= 0;
3628 fdata
.lr_offset
= tdep
->lr_frame_offset
;
3632 if (!fdata
.frameless
)
3634 /* Frameless really means stackless. */
3637 if (safe_read_memory_unsigned_integer (cache
->base
, wordsize
,
3638 byte_order
, &backchain
))
3639 cache
->base
= (CORE_ADDR
) backchain
;
3642 cache
->saved_regs
[gdbarch_sp_regnum (gdbarch
)].set_value (cache
->base
);
3644 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
3645 All fpr's from saved_fpr to fp31 are saved. */
3647 if (fdata
.saved_fpr
>= 0)
3650 CORE_ADDR fpr_addr
= cache
->base
+ fdata
.fpr_offset
;
3652 /* If skip_prologue says floating-point registers were saved,
3653 but the current architecture has no floating-point registers,
3654 then that's strange. But we have no indices to even record
3655 the addresses under, so we just ignore it. */
3656 if (ppc_floating_point_unit_p (gdbarch
))
3657 for (i
= fdata
.saved_fpr
; i
< ppc_num_fprs
; i
++)
3659 cache
->saved_regs
[tdep
->ppc_fp0_regnum
+ i
].set_addr (fpr_addr
);
3664 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
3665 All gpr's from saved_gpr to gpr31 are saved (except during the
3668 if (fdata
.saved_gpr
>= 0)
3671 CORE_ADDR gpr_addr
= cache
->base
+ fdata
.gpr_offset
;
3672 for (i
= fdata
.saved_gpr
; i
< ppc_num_gprs
; i
++)
3674 if (fdata
.gpr_mask
& (1U << i
))
3675 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].set_addr (gpr_addr
);
3676 gpr_addr
+= wordsize
;
3680 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
3681 All vr's from saved_vr to vr31 are saved. */
3682 if (tdep
->ppc_vr0_regnum
!= -1 && tdep
->ppc_vrsave_regnum
!= -1)
3684 if (fdata
.saved_vr
>= 0)
3687 CORE_ADDR vr_addr
= cache
->base
+ fdata
.vr_offset
;
3688 for (i
= fdata
.saved_vr
; i
< 32; i
++)
3690 cache
->saved_regs
[tdep
->ppc_vr0_regnum
+ i
].set_addr (vr_addr
);
3691 vr_addr
+= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
3696 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
3697 All vr's from saved_ev to ev31 are saved. ????? */
3698 if (tdep
->ppc_ev0_regnum
!= -1)
3700 if (fdata
.saved_ev
>= 0)
3703 CORE_ADDR ev_addr
= cache
->base
+ fdata
.ev_offset
;
3704 CORE_ADDR off
= (byte_order
== BFD_ENDIAN_BIG
? 4 : 0);
3706 for (i
= fdata
.saved_ev
; i
< ppc_num_gprs
; i
++)
3708 cache
->saved_regs
[tdep
->ppc_ev0_regnum
+ i
].set_addr (ev_addr
);
3709 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].set_addr (ev_addr
3711 ev_addr
+= register_size (gdbarch
, tdep
->ppc_ev0_regnum
);
3716 /* If != 0, fdata.cr_offset is the offset from the frame that
3718 if (fdata
.cr_offset
!= 0)
3719 cache
->saved_regs
[tdep
->ppc_cr_regnum
].set_addr (cache
->base
3722 /* If != 0, fdata.lr_offset is the offset from the frame that
3724 if (fdata
.lr_offset
!= 0)
3725 cache
->saved_regs
[tdep
->ppc_lr_regnum
].set_addr (cache
->base
3727 else if (fdata
.lr_register
!= -1)
3728 cache
->saved_regs
[tdep
->ppc_lr_regnum
].set_realreg (fdata
.lr_register
);
3729 /* The PC is found in the link register. */
3730 cache
->saved_regs
[gdbarch_pc_regnum (gdbarch
)] =
3731 cache
->saved_regs
[tdep
->ppc_lr_regnum
];
3733 /* If != 0, fdata.vrsave_offset is the offset from the frame that
3734 holds the VRSAVE. */
3735 if (fdata
.vrsave_offset
!= 0)
3736 cache
->saved_regs
[tdep
->ppc_vrsave_regnum
].set_addr (cache
->base
3737 + fdata
.vrsave_offset
);
3739 if (fdata
.alloca_reg
< 0)
3740 /* If no alloca register used, then fi->frame is the value of the
3741 %sp for this frame, and it is good enough. */
3743 = get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
3746 = get_frame_register_unsigned (this_frame
, fdata
.alloca_reg
);
3753 rs6000_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3754 struct frame_id
*this_id
)
3756 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3761 (*this_id
) = frame_id_build_unavailable_stack (info
->pc
);
3765 /* This marks the outermost frame. */
3766 if (info
->base
== 0)
3769 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3772 static struct value
*
3773 rs6000_frame_prev_register (struct frame_info
*this_frame
,
3774 void **this_cache
, int regnum
)
3776 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3778 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3781 static const struct frame_unwind rs6000_frame_unwind
=
3785 default_frame_unwind_stop_reason
,
3786 rs6000_frame_this_id
,
3787 rs6000_frame_prev_register
,
3789 default_frame_sniffer
3792 /* Allocate and initialize a frame cache for an epilogue frame.
3793 SP is restored and prev-PC is stored in LR. */
3795 static struct rs6000_frame_cache
*
3796 rs6000_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3798 struct rs6000_frame_cache
*cache
;
3799 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3800 ppc_gdbarch_tdep
*tdep
= (ppc_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
3803 return (struct rs6000_frame_cache
*) *this_cache
;
3805 cache
= FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache
);
3806 (*this_cache
) = cache
;
3807 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3811 /* At this point the stack looks as if we just entered the
3812 function, and the return address is stored in LR. */
3815 sp
= get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
3816 lr
= get_frame_register_unsigned (this_frame
, tdep
->ppc_lr_regnum
);
3819 cache
->initial_sp
= sp
;
3821 cache
->saved_regs
[gdbarch_pc_regnum (gdbarch
)].set_value (lr
);
3823 catch (const gdb_exception_error
&ex
)
3825 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
3832 /* Implementation of frame_unwind.this_id, as defined in frame_unwind.h.
3833 Return the frame ID of an epilogue frame. */
3836 rs6000_epilogue_frame_this_id (struct frame_info
*this_frame
,
3837 void **this_cache
, struct frame_id
*this_id
)
3840 struct rs6000_frame_cache
*info
=
3841 rs6000_epilogue_frame_cache (this_frame
, this_cache
);
3843 pc
= get_frame_func (this_frame
);
3844 if (info
->base
== 0)
3845 (*this_id
) = frame_id_build_unavailable_stack (pc
);
3847 (*this_id
) = frame_id_build (info
->base
, pc
);
3850 /* Implementation of frame_unwind.prev_register, as defined in frame_unwind.h.
3851 Return the register value of REGNUM in previous frame. */
3853 static struct value
*
3854 rs6000_epilogue_frame_prev_register (struct frame_info
*this_frame
,
3855 void **this_cache
, int regnum
)
3857 struct rs6000_frame_cache
*info
=
3858 rs6000_epilogue_frame_cache (this_frame
, this_cache
);
3859 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3862 /* Implementation of frame_unwind.sniffer, as defined in frame_unwind.h.
3863 Check whether this an epilogue frame. */
3866 rs6000_epilogue_frame_sniffer (const struct frame_unwind
*self
,
3867 struct frame_info
*this_frame
,
3868 void **this_prologue_cache
)
3870 if (frame_relative_level (this_frame
) == 0)
3871 return rs6000_in_function_epilogue_frame_p (this_frame
,
3872 get_frame_arch (this_frame
),
3873 get_frame_pc (this_frame
));
3878 /* Frame unwinder for epilogue frame. This is required for reverse step-over
3879 a function without debug information. */
3881 static const struct frame_unwind rs6000_epilogue_frame_unwind
=
3885 default_frame_unwind_stop_reason
,
3886 rs6000_epilogue_frame_this_id
, rs6000_epilogue_frame_prev_register
,
3888 rs6000_epilogue_frame_sniffer
3893 rs6000_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
3895 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3897 return info
->initial_sp
;
3900 static const struct frame_base rs6000_frame_base
= {
3901 &rs6000_frame_unwind
,
3902 rs6000_frame_base_address
,
3903 rs6000_frame_base_address
,
3904 rs6000_frame_base_address
3907 static const struct frame_base
*
3908 rs6000_frame_base_sniffer (struct frame_info
*this_frame
)
3910 return &rs6000_frame_base
;
3913 /* DWARF-2 frame support. Used to handle the detection of
3914 clobbered registers during function calls. */
3917 ppc_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
3918 struct dwarf2_frame_state_reg
*reg
,
3919 struct frame_info
*this_frame
)
3921 ppc_gdbarch_tdep
*tdep
= (ppc_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
3923 /* PPC32 and PPC64 ABI's are the same regarding volatile and
3924 non-volatile registers. We will use the same code for both. */
3926 /* Call-saved GP registers. */
3927 if ((regnum
>= tdep
->ppc_gp0_regnum
+ 14
3928 && regnum
<= tdep
->ppc_gp0_regnum
+ 31)
3929 || (regnum
== tdep
->ppc_gp0_regnum
+ 1))
3930 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3932 /* Call-clobbered GP registers. */
3933 if ((regnum
>= tdep
->ppc_gp0_regnum
+ 3
3934 && regnum
<= tdep
->ppc_gp0_regnum
+ 12)
3935 || (regnum
== tdep
->ppc_gp0_regnum
))
3936 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3938 /* Deal with FP registers, if supported. */
3939 if (tdep
->ppc_fp0_regnum
>= 0)
3941 /* Call-saved FP registers. */
3942 if ((regnum
>= tdep
->ppc_fp0_regnum
+ 14
3943 && regnum
<= tdep
->ppc_fp0_regnum
+ 31))
3944 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3946 /* Call-clobbered FP registers. */
3947 if ((regnum
>= tdep
->ppc_fp0_regnum
3948 && regnum
<= tdep
->ppc_fp0_regnum
+ 13))
3949 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3952 /* Deal with ALTIVEC registers, if supported. */
3953 if (tdep
->ppc_vr0_regnum
> 0 && tdep
->ppc_vrsave_regnum
> 0)
3955 /* Call-saved Altivec registers. */
3956 if ((regnum
>= tdep
->ppc_vr0_regnum
+ 20
3957 && regnum
<= tdep
->ppc_vr0_regnum
+ 31)
3958 || regnum
== tdep
->ppc_vrsave_regnum
)
3959 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3961 /* Call-clobbered Altivec registers. */
3962 if ((regnum
>= tdep
->ppc_vr0_regnum
3963 && regnum
<= tdep
->ppc_vr0_regnum
+ 19))
3964 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3967 /* Handle PC register and Stack Pointer correctly. */
3968 if (regnum
== gdbarch_pc_regnum (gdbarch
))
3969 reg
->how
= DWARF2_FRAME_REG_RA
;
3970 else if (regnum
== gdbarch_sp_regnum (gdbarch
))
3971 reg
->how
= DWARF2_FRAME_REG_CFA
;
3975 /* Return true if a .gnu_attributes section exists in BFD and it
3976 indicates we are using SPE extensions OR if a .PPC.EMB.apuinfo
3977 section exists in BFD and it indicates that SPE extensions are in
3978 use. Check the .gnu.attributes section first, as the binary might be
3979 compiled for SPE, but not actually using SPE instructions. */
3982 bfd_uses_spe_extensions (bfd
*abfd
)
3985 gdb_byte
*contents
= NULL
;
3994 /* Using Tag_GNU_Power_ABI_Vector here is a bit of a hack, as the user
3995 could be using the SPE vector abi without actually using any spe
3996 bits whatsoever. But it's close enough for now. */
3997 int vector_abi
= bfd_elf_get_obj_attr_int (abfd
, OBJ_ATTR_GNU
,
3998 Tag_GNU_Power_ABI_Vector
);
3999 if (vector_abi
== 3)
4003 sect
= bfd_get_section_by_name (abfd
, ".PPC.EMB.apuinfo");
4007 size
= bfd_section_size (sect
);
4008 contents
= (gdb_byte
*) xmalloc (size
);
4009 if (!bfd_get_section_contents (abfd
, sect
, contents
, 0, size
))
4015 /* Parse the .PPC.EMB.apuinfo section. The layout is as follows:
4021 char name[name_len rounded up to 4-byte alignment];
4022 char data[data_len];
4025 Technically, there's only supposed to be one such structure in a
4026 given apuinfo section, but the linker is not always vigilant about
4027 merging apuinfo sections from input files. Just go ahead and parse
4028 them all, exiting early when we discover the binary uses SPE
4031 It's not specified in what endianness the information in this
4032 section is stored. Assume that it's the endianness of the BFD. */
4036 unsigned int name_len
;
4037 unsigned int data_len
;
4040 /* If we can't read the first three fields, we're done. */
4044 name_len
= bfd_get_32 (abfd
, ptr
);
4045 name_len
= (name_len
+ 3) & ~3U; /* Round to 4 bytes. */
4046 data_len
= bfd_get_32 (abfd
, ptr
+ 4);
4047 type
= bfd_get_32 (abfd
, ptr
+ 8);
4050 /* The name must be "APUinfo\0". */
4052 && strcmp ((const char *) ptr
, "APUinfo") != 0)
4056 /* The type must be 2. */
4060 /* The data is stored as a series of uint32. The upper half of
4061 each uint32 indicates the particular APU used and the lower
4062 half indicates the revision of that APU. We just care about
4065 /* Not 4-byte quantities. */
4071 unsigned int apuinfo
= bfd_get_32 (abfd
, ptr
);
4072 unsigned int apu
= apuinfo
>> 16;
4076 /* The SPE APU is 0x100; the SPEFP APU is 0x101. Accept
4078 if (apu
== 0x100 || apu
== 0x101)
4093 /* These are macros for parsing instruction fields (I.1.6.28) */
4095 #define PPC_FIELD(value, from, len) \
4096 (((value) >> (32 - (from) - (len))) & ((1 << (len)) - 1))
4097 #define PPC_SEXT(v, bs) \
4098 ((((CORE_ADDR) (v) & (((CORE_ADDR) 1 << (bs)) - 1)) \
4099 ^ ((CORE_ADDR) 1 << ((bs) - 1))) \
4100 - ((CORE_ADDR) 1 << ((bs) - 1)))
4101 #define PPC_OP6(insn) PPC_FIELD (insn, 0, 6)
4102 #define PPC_EXTOP(insn) PPC_FIELD (insn, 21, 10)
4103 #define PPC_RT(insn) PPC_FIELD (insn, 6, 5)
4104 #define PPC_RS(insn) PPC_FIELD (insn, 6, 5)
4105 #define PPC_RA(insn) PPC_FIELD (insn, 11, 5)
4106 #define PPC_RB(insn) PPC_FIELD (insn, 16, 5)
4107 #define PPC_NB(insn) PPC_FIELD (insn, 16, 5)
4108 #define PPC_VRT(insn) PPC_FIELD (insn, 6, 5)
4109 #define PPC_FRT(insn) PPC_FIELD (insn, 6, 5)
4110 #define PPC_SPR(insn) (PPC_FIELD (insn, 11, 5) \
4111 | (PPC_FIELD (insn, 16, 5) << 5))
4112 #define PPC_BO(insn) PPC_FIELD (insn, 6, 5)
4113 #define PPC_T(insn) PPC_FIELD (insn, 6, 5)
4114 #define PPC_D(insn) PPC_SEXT (PPC_FIELD (insn, 16, 16), 16)
4115 #define PPC_DS(insn) PPC_SEXT (PPC_FIELD (insn, 16, 14), 14)
4116 #define PPC_DQ(insn) PPC_SEXT (PPC_FIELD (insn, 16, 12), 12)
4117 #define PPC_BIT(insn,n) ((insn & (1 << (31 - (n)))) ? 1 : 0)
4118 #define PPC_OE(insn) PPC_BIT (insn, 21)
4119 #define PPC_RC(insn) PPC_BIT (insn, 31)
4120 #define PPC_Rc(insn) PPC_BIT (insn, 21)
4121 #define PPC_LK(insn) PPC_BIT (insn, 31)
4122 #define PPC_TX(insn) PPC_BIT (insn, 31)
4123 #define PPC_LEV(insn) PPC_FIELD (insn, 20, 7)
4125 #define PPC_XT(insn) ((PPC_TX (insn) << 5) | PPC_T (insn))
4126 #define PPC_XER_NB(xer) (xer & 0x7f)
4128 /* Record Vector-Scalar Registers.
4129 For VSR less than 32, it's represented by an FPR and an VSR-upper register.
4130 Otherwise, it's just a VR register. Record them accordingly. */
4133 ppc_record_vsr (struct regcache
*regcache
, ppc_gdbarch_tdep
*tdep
, int vsr
)
4135 if (vsr
< 0 || vsr
>= 64)
4140 if (tdep
->ppc_vr0_regnum
>= 0)
4141 record_full_arch_list_add_reg (regcache
, tdep
->ppc_vr0_regnum
+ vsr
- 32);
4145 if (tdep
->ppc_fp0_regnum
>= 0)
4146 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fp0_regnum
+ vsr
);
4147 if (tdep
->ppc_vsr0_upper_regnum
>= 0)
4148 record_full_arch_list_add_reg (regcache
,
4149 tdep
->ppc_vsr0_upper_regnum
+ vsr
);
4155 /* Parse and record instructions primary opcode-4 at ADDR.
4156 Return 0 if successful. */
4159 ppc_process_record_op4 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4160 CORE_ADDR addr
, uint32_t insn
)
4162 ppc_gdbarch_tdep
*tdep
= (ppc_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
4163 int ext
= PPC_FIELD (insn
, 21, 11);
4164 int vra
= PPC_FIELD (insn
, 11, 5);
4168 case 32: /* Vector Multiply-High-Add Signed Halfword Saturate */
4169 case 33: /* Vector Multiply-High-Round-Add Signed Halfword Saturate */
4170 case 39: /* Vector Multiply-Sum Unsigned Halfword Saturate */
4171 case 41: /* Vector Multiply-Sum Signed Halfword Saturate */
4172 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
4174 case 42: /* Vector Select */
4175 case 43: /* Vector Permute */
4176 case 59: /* Vector Permute Right-indexed */
4177 case 44: /* Vector Shift Left Double by Octet Immediate */
4178 case 45: /* Vector Permute and Exclusive-OR */
4179 case 60: /* Vector Add Extended Unsigned Quadword Modulo */
4180 case 61: /* Vector Add Extended & write Carry Unsigned Quadword */
4181 case 62: /* Vector Subtract Extended Unsigned Quadword Modulo */
4182 case 63: /* Vector Subtract Extended & write Carry Unsigned Quadword */
4183 case 34: /* Vector Multiply-Low-Add Unsigned Halfword Modulo */
4184 case 35: /* Vector Multiply-Sum Unsigned Doubleword Modulo */
4185 case 36: /* Vector Multiply-Sum Unsigned Byte Modulo */
4186 case 37: /* Vector Multiply-Sum Mixed Byte Modulo */
4187 case 38: /* Vector Multiply-Sum Unsigned Halfword Modulo */
4188 case 40: /* Vector Multiply-Sum Signed Halfword Modulo */
4189 case 46: /* Vector Multiply-Add Single-Precision */
4190 case 47: /* Vector Negative Multiply-Subtract Single-Precision */
4191 record_full_arch_list_add_reg (regcache
,
4192 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4195 case 48: /* Multiply-Add High Doubleword */
4196 case 49: /* Multiply-Add High Doubleword Unsigned */
4197 case 51: /* Multiply-Add Low Doubleword */
4198 record_full_arch_list_add_reg (regcache
,
4199 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4203 switch ((ext
& 0x1ff))
4206 if (vra
!= 0 /* Decimal Convert To Signed Quadword */
4207 && vra
!= 2 /* Decimal Convert From Signed Quadword */
4208 && vra
!= 4 /* Decimal Convert To Zoned */
4209 && vra
!= 5 /* Decimal Convert To National */
4210 && vra
!= 6 /* Decimal Convert From Zoned */
4211 && vra
!= 7 /* Decimal Convert From National */
4212 && vra
!= 31) /* Decimal Set Sign */
4215 /* 5.16 Decimal Integer Arithmetic Instructions */
4216 case 1: /* Decimal Add Modulo */
4217 case 65: /* Decimal Subtract Modulo */
4219 case 193: /* Decimal Shift */
4220 case 129: /* Decimal Unsigned Shift */
4221 case 449: /* Decimal Shift and Round */
4223 case 257: /* Decimal Truncate */
4224 case 321: /* Decimal Unsigned Truncate */
4226 /* Bit-21 should be set. */
4227 if (!PPC_BIT (insn
, 21))
4230 record_full_arch_list_add_reg (regcache
,
4231 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4232 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4236 /* Bit-21 is used for RC */
4237 switch (ext
& 0x3ff)
4239 case 6: /* Vector Compare Equal To Unsigned Byte */
4240 case 70: /* Vector Compare Equal To Unsigned Halfword */
4241 case 134: /* Vector Compare Equal To Unsigned Word */
4242 case 199: /* Vector Compare Equal To Unsigned Doubleword */
4243 case 774: /* Vector Compare Greater Than Signed Byte */
4244 case 838: /* Vector Compare Greater Than Signed Halfword */
4245 case 902: /* Vector Compare Greater Than Signed Word */
4246 case 967: /* Vector Compare Greater Than Signed Doubleword */
4247 case 518: /* Vector Compare Greater Than Unsigned Byte */
4248 case 646: /* Vector Compare Greater Than Unsigned Word */
4249 case 582: /* Vector Compare Greater Than Unsigned Halfword */
4250 case 711: /* Vector Compare Greater Than Unsigned Doubleword */
4251 case 966: /* Vector Compare Bounds Single-Precision */
4252 case 198: /* Vector Compare Equal To Single-Precision */
4253 case 454: /* Vector Compare Greater Than or Equal To Single-Precision */
4254 case 710: /* Vector Compare Greater Than Single-Precision */
4255 case 7: /* Vector Compare Not Equal Byte */
4256 case 71: /* Vector Compare Not Equal Halfword */
4257 case 135: /* Vector Compare Not Equal Word */
4258 case 263: /* Vector Compare Not Equal or Zero Byte */
4259 case 327: /* Vector Compare Not Equal or Zero Halfword */
4260 case 391: /* Vector Compare Not Equal or Zero Word */
4262 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4263 record_full_arch_list_add_reg (regcache
,
4264 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4272 case 0: /* Vector Count Leading Zero Least-Significant Bits
4274 case 1: /* Vector Count Trailing Zero Least-Significant Bits
4276 record_full_arch_list_add_reg (regcache
,
4277 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4280 case 6: /* Vector Negate Word */
4281 case 7: /* Vector Negate Doubleword */
4282 case 8: /* Vector Parity Byte Word */
4283 case 9: /* Vector Parity Byte Doubleword */
4284 case 10: /* Vector Parity Byte Quadword */
4285 case 16: /* Vector Extend Sign Byte To Word */
4286 case 17: /* Vector Extend Sign Halfword To Word */
4287 case 24: /* Vector Extend Sign Byte To Doubleword */
4288 case 25: /* Vector Extend Sign Halfword To Doubleword */
4289 case 26: /* Vector Extend Sign Word To Doubleword */
4290 case 28: /* Vector Count Trailing Zeros Byte */
4291 case 29: /* Vector Count Trailing Zeros Halfword */
4292 case 30: /* Vector Count Trailing Zeros Word */
4293 case 31: /* Vector Count Trailing Zeros Doubleword */
4294 record_full_arch_list_add_reg (regcache
,
4295 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4302 case 142: /* Vector Pack Unsigned Halfword Unsigned Saturate */
4303 case 206: /* Vector Pack Unsigned Word Unsigned Saturate */
4304 case 270: /* Vector Pack Signed Halfword Unsigned Saturate */
4305 case 334: /* Vector Pack Signed Word Unsigned Saturate */
4306 case 398: /* Vector Pack Signed Halfword Signed Saturate */
4307 case 462: /* Vector Pack Signed Word Signed Saturate */
4308 case 1230: /* Vector Pack Unsigned Doubleword Unsigned Saturate */
4309 case 1358: /* Vector Pack Signed Doubleword Unsigned Saturate */
4310 case 1486: /* Vector Pack Signed Doubleword Signed Saturate */
4311 case 512: /* Vector Add Unsigned Byte Saturate */
4312 case 576: /* Vector Add Unsigned Halfword Saturate */
4313 case 640: /* Vector Add Unsigned Word Saturate */
4314 case 768: /* Vector Add Signed Byte Saturate */
4315 case 832: /* Vector Add Signed Halfword Saturate */
4316 case 896: /* Vector Add Signed Word Saturate */
4317 case 1536: /* Vector Subtract Unsigned Byte Saturate */
4318 case 1600: /* Vector Subtract Unsigned Halfword Saturate */
4319 case 1664: /* Vector Subtract Unsigned Word Saturate */
4320 case 1792: /* Vector Subtract Signed Byte Saturate */
4321 case 1856: /* Vector Subtract Signed Halfword Saturate */
4322 case 1920: /* Vector Subtract Signed Word Saturate */
4324 case 1544: /* Vector Sum across Quarter Unsigned Byte Saturate */
4325 case 1800: /* Vector Sum across Quarter Signed Byte Saturate */
4326 case 1608: /* Vector Sum across Quarter Signed Halfword Saturate */
4327 case 1672: /* Vector Sum across Half Signed Word Saturate */
4328 case 1928: /* Vector Sum across Signed Word Saturate */
4329 case 970: /* Vector Convert To Signed Fixed-Point Word Saturate */
4330 case 906: /* Vector Convert To Unsigned Fixed-Point Word Saturate */
4331 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
4333 case 12: /* Vector Merge High Byte */
4334 case 14: /* Vector Pack Unsigned Halfword Unsigned Modulo */
4335 case 76: /* Vector Merge High Halfword */
4336 case 78: /* Vector Pack Unsigned Word Unsigned Modulo */
4337 case 140: /* Vector Merge High Word */
4338 case 268: /* Vector Merge Low Byte */
4339 case 332: /* Vector Merge Low Halfword */
4340 case 396: /* Vector Merge Low Word */
4341 case 526: /* Vector Unpack High Signed Byte */
4342 case 590: /* Vector Unpack High Signed Halfword */
4343 case 654: /* Vector Unpack Low Signed Byte */
4344 case 718: /* Vector Unpack Low Signed Halfword */
4345 case 782: /* Vector Pack Pixel */
4346 case 846: /* Vector Unpack High Pixel */
4347 case 974: /* Vector Unpack Low Pixel */
4348 case 1102: /* Vector Pack Unsigned Doubleword Unsigned Modulo */
4349 case 1614: /* Vector Unpack High Signed Word */
4350 case 1676: /* Vector Merge Odd Word */
4351 case 1742: /* Vector Unpack Low Signed Word */
4352 case 1932: /* Vector Merge Even Word */
4353 case 524: /* Vector Splat Byte */
4354 case 588: /* Vector Splat Halfword */
4355 case 652: /* Vector Splat Word */
4356 case 780: /* Vector Splat Immediate Signed Byte */
4357 case 844: /* Vector Splat Immediate Signed Halfword */
4358 case 908: /* Vector Splat Immediate Signed Word */
4359 case 452: /* Vector Shift Left */
4360 case 708: /* Vector Shift Right */
4361 case 1036: /* Vector Shift Left by Octet */
4362 case 1100: /* Vector Shift Right by Octet */
4363 case 0: /* Vector Add Unsigned Byte Modulo */
4364 case 64: /* Vector Add Unsigned Halfword Modulo */
4365 case 128: /* Vector Add Unsigned Word Modulo */
4366 case 192: /* Vector Add Unsigned Doubleword Modulo */
4367 case 256: /* Vector Add Unsigned Quadword Modulo */
4368 case 320: /* Vector Add & write Carry Unsigned Quadword */
4369 case 384: /* Vector Add and Write Carry-Out Unsigned Word */
4370 case 8: /* Vector Multiply Odd Unsigned Byte */
4371 case 72: /* Vector Multiply Odd Unsigned Halfword */
4372 case 136: /* Vector Multiply Odd Unsigned Word */
4373 case 264: /* Vector Multiply Odd Signed Byte */
4374 case 328: /* Vector Multiply Odd Signed Halfword */
4375 case 392: /* Vector Multiply Odd Signed Word */
4376 case 520: /* Vector Multiply Even Unsigned Byte */
4377 case 584: /* Vector Multiply Even Unsigned Halfword */
4378 case 648: /* Vector Multiply Even Unsigned Word */
4379 case 776: /* Vector Multiply Even Signed Byte */
4380 case 840: /* Vector Multiply Even Signed Halfword */
4381 case 904: /* Vector Multiply Even Signed Word */
4382 case 137: /* Vector Multiply Unsigned Word Modulo */
4383 case 1024: /* Vector Subtract Unsigned Byte Modulo */
4384 case 1088: /* Vector Subtract Unsigned Halfword Modulo */
4385 case 1152: /* Vector Subtract Unsigned Word Modulo */
4386 case 1216: /* Vector Subtract Unsigned Doubleword Modulo */
4387 case 1280: /* Vector Subtract Unsigned Quadword Modulo */
4388 case 1344: /* Vector Subtract & write Carry Unsigned Quadword */
4389 case 1408: /* Vector Subtract and Write Carry-Out Unsigned Word */
4390 case 1282: /* Vector Average Signed Byte */
4391 case 1346: /* Vector Average Signed Halfword */
4392 case 1410: /* Vector Average Signed Word */
4393 case 1026: /* Vector Average Unsigned Byte */
4394 case 1090: /* Vector Average Unsigned Halfword */
4395 case 1154: /* Vector Average Unsigned Word */
4396 case 258: /* Vector Maximum Signed Byte */
4397 case 322: /* Vector Maximum Signed Halfword */
4398 case 386: /* Vector Maximum Signed Word */
4399 case 450: /* Vector Maximum Signed Doubleword */
4400 case 2: /* Vector Maximum Unsigned Byte */
4401 case 66: /* Vector Maximum Unsigned Halfword */
4402 case 130: /* Vector Maximum Unsigned Word */
4403 case 194: /* Vector Maximum Unsigned Doubleword */
4404 case 770: /* Vector Minimum Signed Byte */
4405 case 834: /* Vector Minimum Signed Halfword */
4406 case 898: /* Vector Minimum Signed Word */
4407 case 962: /* Vector Minimum Signed Doubleword */
4408 case 514: /* Vector Minimum Unsigned Byte */
4409 case 578: /* Vector Minimum Unsigned Halfword */
4410 case 642: /* Vector Minimum Unsigned Word */
4411 case 706: /* Vector Minimum Unsigned Doubleword */
4412 case 1028: /* Vector Logical AND */
4413 case 1668: /* Vector Logical Equivalent */
4414 case 1092: /* Vector Logical AND with Complement */
4415 case 1412: /* Vector Logical NAND */
4416 case 1348: /* Vector Logical OR with Complement */
4417 case 1156: /* Vector Logical OR */
4418 case 1284: /* Vector Logical NOR */
4419 case 1220: /* Vector Logical XOR */
4420 case 4: /* Vector Rotate Left Byte */
4421 case 132: /* Vector Rotate Left Word VX-form */
4422 case 68: /* Vector Rotate Left Halfword */
4423 case 196: /* Vector Rotate Left Doubleword */
4424 case 260: /* Vector Shift Left Byte */
4425 case 388: /* Vector Shift Left Word */
4426 case 324: /* Vector Shift Left Halfword */
4427 case 1476: /* Vector Shift Left Doubleword */
4428 case 516: /* Vector Shift Right Byte */
4429 case 644: /* Vector Shift Right Word */
4430 case 580: /* Vector Shift Right Halfword */
4431 case 1732: /* Vector Shift Right Doubleword */
4432 case 772: /* Vector Shift Right Algebraic Byte */
4433 case 900: /* Vector Shift Right Algebraic Word */
4434 case 836: /* Vector Shift Right Algebraic Halfword */
4435 case 964: /* Vector Shift Right Algebraic Doubleword */
4436 case 10: /* Vector Add Single-Precision */
4437 case 74: /* Vector Subtract Single-Precision */
4438 case 1034: /* Vector Maximum Single-Precision */
4439 case 1098: /* Vector Minimum Single-Precision */
4440 case 842: /* Vector Convert From Signed Fixed-Point Word */
4441 case 778: /* Vector Convert From Unsigned Fixed-Point Word */
4442 case 714: /* Vector Round to Single-Precision Integer toward -Infinity */
4443 case 522: /* Vector Round to Single-Precision Integer Nearest */
4444 case 650: /* Vector Round to Single-Precision Integer toward +Infinity */
4445 case 586: /* Vector Round to Single-Precision Integer toward Zero */
4446 case 394: /* Vector 2 Raised to the Exponent Estimate Floating-Point */
4447 case 458: /* Vector Log Base 2 Estimate Floating-Point */
4448 case 266: /* Vector Reciprocal Estimate Single-Precision */
4449 case 330: /* Vector Reciprocal Square Root Estimate Single-Precision */
4450 case 1288: /* Vector AES Cipher */
4451 case 1289: /* Vector AES Cipher Last */
4452 case 1352: /* Vector AES Inverse Cipher */
4453 case 1353: /* Vector AES Inverse Cipher Last */
4454 case 1480: /* Vector AES SubBytes */
4455 case 1730: /* Vector SHA-512 Sigma Doubleword */
4456 case 1666: /* Vector SHA-256 Sigma Word */
4457 case 1032: /* Vector Polynomial Multiply-Sum Byte */
4458 case 1160: /* Vector Polynomial Multiply-Sum Word */
4459 case 1096: /* Vector Polynomial Multiply-Sum Halfword */
4460 case 1224: /* Vector Polynomial Multiply-Sum Doubleword */
4461 case 1292: /* Vector Gather Bits by Bytes by Doubleword */
4462 case 1794: /* Vector Count Leading Zeros Byte */
4463 case 1858: /* Vector Count Leading Zeros Halfword */
4464 case 1922: /* Vector Count Leading Zeros Word */
4465 case 1986: /* Vector Count Leading Zeros Doubleword */
4466 case 1795: /* Vector Population Count Byte */
4467 case 1859: /* Vector Population Count Halfword */
4468 case 1923: /* Vector Population Count Word */
4469 case 1987: /* Vector Population Count Doubleword */
4470 case 1356: /* Vector Bit Permute Quadword */
4471 case 1484: /* Vector Bit Permute Doubleword */
4472 case 513: /* Vector Multiply-by-10 Unsigned Quadword */
4473 case 1: /* Vector Multiply-by-10 & write Carry Unsigned
4475 case 577: /* Vector Multiply-by-10 Extended Unsigned Quadword */
4476 case 65: /* Vector Multiply-by-10 Extended & write Carry
4477 Unsigned Quadword */
4478 case 1027: /* Vector Absolute Difference Unsigned Byte */
4479 case 1091: /* Vector Absolute Difference Unsigned Halfword */
4480 case 1155: /* Vector Absolute Difference Unsigned Word */
4481 case 1796: /* Vector Shift Right Variable */
4482 case 1860: /* Vector Shift Left Variable */
4483 case 133: /* Vector Rotate Left Word then Mask Insert */
4484 case 197: /* Vector Rotate Left Doubleword then Mask Insert */
4485 case 389: /* Vector Rotate Left Word then AND with Mask */
4486 case 453: /* Vector Rotate Left Doubleword then AND with Mask */
4487 case 525: /* Vector Extract Unsigned Byte */
4488 case 589: /* Vector Extract Unsigned Halfword */
4489 case 653: /* Vector Extract Unsigned Word */
4490 case 717: /* Vector Extract Doubleword */
4491 case 781: /* Vector Insert Byte */
4492 case 845: /* Vector Insert Halfword */
4493 case 909: /* Vector Insert Word */
4494 case 973: /* Vector Insert Doubleword */
4495 record_full_arch_list_add_reg (regcache
,
4496 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4499 case 1549: /* Vector Extract Unsigned Byte Left-Indexed */
4500 case 1613: /* Vector Extract Unsigned Halfword Left-Indexed */
4501 case 1677: /* Vector Extract Unsigned Word Left-Indexed */
4502 case 1805: /* Vector Extract Unsigned Byte Right-Indexed */
4503 case 1869: /* Vector Extract Unsigned Halfword Right-Indexed */
4504 case 1933: /* Vector Extract Unsigned Word Right-Indexed */
4505 record_full_arch_list_add_reg (regcache
,
4506 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4509 case 1604: /* Move To Vector Status and Control Register */
4510 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
4512 case 1540: /* Move From Vector Status and Control Register */
4513 record_full_arch_list_add_reg (regcache
,
4514 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4516 case 833: /* Decimal Copy Sign */
4517 record_full_arch_list_add_reg (regcache
,
4518 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4519 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4523 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4524 "at %s, 4-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4528 /* Parse and record instructions of primary opcode-19 at ADDR.
4529 Return 0 if successful. */
4532 ppc_process_record_op19 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4533 CORE_ADDR addr
, uint32_t insn
)
4535 ppc_gdbarch_tdep
*tdep
= (ppc_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
4536 int ext
= PPC_EXTOP (insn
);
4538 switch (ext
& 0x01f)
4540 case 2: /* Add PC Immediate Shifted */
4541 record_full_arch_list_add_reg (regcache
,
4542 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4548 case 0: /* Move Condition Register Field */
4549 case 33: /* Condition Register NOR */
4550 case 129: /* Condition Register AND with Complement */
4551 case 193: /* Condition Register XOR */
4552 case 225: /* Condition Register NAND */
4553 case 257: /* Condition Register AND */
4554 case 289: /* Condition Register Equivalent */
4555 case 417: /* Condition Register OR with Complement */
4556 case 449: /* Condition Register OR */
4557 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4560 case 16: /* Branch Conditional */
4561 case 560: /* Branch Conditional to Branch Target Address Register */
4562 if ((PPC_BO (insn
) & 0x4) == 0)
4563 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
4565 case 528: /* Branch Conditional to Count Register */
4567 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
4570 case 150: /* Instruction Synchronize */
4575 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4576 "at %s, 19-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4580 /* Parse and record instructions of primary opcode-31 at ADDR.
4581 Return 0 if successful. */
4584 ppc_process_record_op31 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4585 CORE_ADDR addr
, uint32_t insn
)
4587 ppc_gdbarch_tdep
*tdep
= (ppc_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
4588 int ext
= PPC_EXTOP (insn
);
4590 CORE_ADDR at_dcsz
, ea
= 0;
4591 ULONGEST rb
, ra
, xer
;
4594 /* These instructions have OE bit. */
4595 switch (ext
& 0x1ff)
4597 /* These write RT and XER. Update CR if RC is set. */
4598 case 8: /* Subtract from carrying */
4599 case 10: /* Add carrying */
4600 case 136: /* Subtract from extended */
4601 case 138: /* Add extended */
4602 case 200: /* Subtract from zero extended */
4603 case 202: /* Add to zero extended */
4604 case 232: /* Subtract from minus one extended */
4605 case 234: /* Add to minus one extended */
4606 /* CA is always altered, but SO/OV are only altered when OE=1.
4607 In any case, XER is always altered. */
4608 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4610 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4611 record_full_arch_list_add_reg (regcache
,
4612 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4615 /* These write RT. Update CR if RC is set and update XER if OE is set. */
4616 case 40: /* Subtract from */
4617 case 104: /* Negate */
4618 case 233: /* Multiply low doubleword */
4619 case 235: /* Multiply low word */
4621 case 393: /* Divide Doubleword Extended Unsigned */
4622 case 395: /* Divide Word Extended Unsigned */
4623 case 425: /* Divide Doubleword Extended */
4624 case 427: /* Divide Word Extended */
4625 case 457: /* Divide Doubleword Unsigned */
4626 case 459: /* Divide Word Unsigned */
4627 case 489: /* Divide Doubleword */
4628 case 491: /* Divide Word */
4630 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4632 case 9: /* Multiply High Doubleword Unsigned */
4633 case 11: /* Multiply High Word Unsigned */
4634 case 73: /* Multiply High Doubleword */
4635 case 75: /* Multiply High Word */
4637 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4638 record_full_arch_list_add_reg (regcache
,
4639 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4643 if ((ext
& 0x1f) == 15)
4645 /* Integer Select. bit[16:20] is used for BC. */
4646 record_full_arch_list_add_reg (regcache
,
4647 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4651 if ((ext
& 0xff) == 170)
4653 /* Add Extended using alternate carry bits */
4654 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4655 record_full_arch_list_add_reg (regcache
,
4656 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4662 case 78: /* Determine Leftmost Zero Byte */
4664 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4665 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4666 record_full_arch_list_add_reg (regcache
,
4667 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4670 /* These only write RT. */
4671 case 19: /* Move from condition register */
4672 /* Move From One Condition Register Field */
4673 case 74: /* Add and Generate Sixes */
4674 case 74 | 0x200: /* Add and Generate Sixes (bit-21 dont-care) */
4675 case 302: /* Move From Branch History Rolling Buffer */
4676 case 339: /* Move From Special Purpose Register */
4677 case 371: /* Move From Time Base [Phased-Out] */
4678 case 309: /* Load Doubleword Monitored Indexed */
4679 case 128: /* Set Boolean */
4680 case 755: /* Deliver A Random Number */
4681 record_full_arch_list_add_reg (regcache
,
4682 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4685 /* These only write to RA. */
4686 case 51: /* Move From VSR Doubleword */
4687 case 115: /* Move From VSR Word and Zero */
4688 case 122: /* Population count bytes */
4689 case 378: /* Population count words */
4690 case 506: /* Population count doublewords */
4691 case 154: /* Parity Word */
4692 case 186: /* Parity Doubleword */
4693 case 252: /* Bit Permute Doubleword */
4694 case 282: /* Convert Declets To Binary Coded Decimal */
4695 case 314: /* Convert Binary Coded Decimal To Declets */
4696 case 508: /* Compare bytes */
4697 case 307: /* Move From VSR Lower Doubleword */
4698 record_full_arch_list_add_reg (regcache
,
4699 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4702 /* These write CR and optional RA. */
4703 case 792: /* Shift Right Algebraic Word */
4704 case 794: /* Shift Right Algebraic Doubleword */
4705 case 824: /* Shift Right Algebraic Word Immediate */
4706 case 826: /* Shift Right Algebraic Doubleword Immediate (413) */
4707 case 826 | 1: /* Shift Right Algebraic Doubleword Immediate (413) */
4708 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4709 record_full_arch_list_add_reg (regcache
,
4710 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4712 case 0: /* Compare */
4713 case 32: /* Compare logical */
4714 case 144: /* Move To Condition Register Fields */
4715 /* Move To One Condition Register Field */
4716 case 192: /* Compare Ranged Byte */
4717 case 224: /* Compare Equal Byte */
4718 case 576: /* Move XER to CR Extended */
4719 case 902: /* Paste (should always fail due to single-stepping and
4720 the memory location might not be accessible, so
4722 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4725 /* These write to RT. Update RA if 'update indexed.' */
4726 case 53: /* Load Doubleword with Update Indexed */
4727 case 119: /* Load Byte and Zero with Update Indexed */
4728 case 311: /* Load Halfword and Zero with Update Indexed */
4729 case 55: /* Load Word and Zero with Update Indexed */
4730 case 375: /* Load Halfword Algebraic with Update Indexed */
4731 case 373: /* Load Word Algebraic with Update Indexed */
4732 record_full_arch_list_add_reg (regcache
,
4733 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4735 case 21: /* Load Doubleword Indexed */
4736 case 52: /* Load Byte And Reserve Indexed */
4737 case 116: /* Load Halfword And Reserve Indexed */
4738 case 20: /* Load Word And Reserve Indexed */
4739 case 84: /* Load Doubleword And Reserve Indexed */
4740 case 87: /* Load Byte and Zero Indexed */
4741 case 279: /* Load Halfword and Zero Indexed */
4742 case 23: /* Load Word and Zero Indexed */
4743 case 343: /* Load Halfword Algebraic Indexed */
4744 case 341: /* Load Word Algebraic Indexed */
4745 case 790: /* Load Halfword Byte-Reverse Indexed */
4746 case 534: /* Load Word Byte-Reverse Indexed */
4747 case 532: /* Load Doubleword Byte-Reverse Indexed */
4748 case 582: /* Load Word Atomic */
4749 case 614: /* Load Doubleword Atomic */
4750 case 265: /* Modulo Unsigned Doubleword */
4751 case 777: /* Modulo Signed Doubleword */
4752 case 267: /* Modulo Unsigned Word */
4753 case 779: /* Modulo Signed Word */
4754 record_full_arch_list_add_reg (regcache
,
4755 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4758 case 597: /* Load String Word Immediate */
4759 case 533: /* Load String Word Indexed */
4768 regcache_raw_read_unsigned (regcache
, tdep
->ppc_xer_regnum
, &xer
);
4769 nr
= PPC_XER_NB (xer
);
4774 /* If n=0, the contents of register RT are undefined. */
4778 for (i
= 0; i
< nr
; i
++)
4779 record_full_arch_list_add_reg (regcache
,
4780 tdep
->ppc_gp0_regnum
4781 + ((PPC_RT (insn
) + i
) & 0x1f));
4784 case 276: /* Load Quadword And Reserve Indexed */
4785 tmp
= tdep
->ppc_gp0_regnum
+ (PPC_RT (insn
) & ~1);
4786 record_full_arch_list_add_reg (regcache
, tmp
);
4787 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
4790 /* These write VRT. */
4791 case 6: /* Load Vector for Shift Left Indexed */
4792 case 38: /* Load Vector for Shift Right Indexed */
4793 case 7: /* Load Vector Element Byte Indexed */
4794 case 39: /* Load Vector Element Halfword Indexed */
4795 case 71: /* Load Vector Element Word Indexed */
4796 case 103: /* Load Vector Indexed */
4797 case 359: /* Load Vector Indexed LRU */
4798 record_full_arch_list_add_reg (regcache
,
4799 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4802 /* These write FRT. Update RA if 'update indexed.' */
4803 case 567: /* Load Floating-Point Single with Update Indexed */
4804 case 631: /* Load Floating-Point Double with Update Indexed */
4805 record_full_arch_list_add_reg (regcache
,
4806 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4808 case 535: /* Load Floating-Point Single Indexed */
4809 case 599: /* Load Floating-Point Double Indexed */
4810 case 855: /* Load Floating-Point as Integer Word Algebraic Indexed */
4811 case 887: /* Load Floating-Point as Integer Word and Zero Indexed */
4812 record_full_arch_list_add_reg (regcache
,
4813 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4816 case 791: /* Load Floating-Point Double Pair Indexed */
4817 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
4818 record_full_arch_list_add_reg (regcache
, tmp
);
4819 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
4822 case 179: /* Move To VSR Doubleword */
4823 case 211: /* Move To VSR Word Algebraic */
4824 case 243: /* Move To VSR Word and Zero */
4825 case 588: /* Load VSX Scalar Doubleword Indexed */
4826 case 524: /* Load VSX Scalar Single-Precision Indexed */
4827 case 76: /* Load VSX Scalar as Integer Word Algebraic Indexed */
4828 case 12: /* Load VSX Scalar as Integer Word and Zero Indexed */
4829 case 844: /* Load VSX Vector Doubleword*2 Indexed */
4830 case 332: /* Load VSX Vector Doubleword & Splat Indexed */
4831 case 780: /* Load VSX Vector Word*4 Indexed */
4832 case 268: /* Load VSX Vector Indexed */
4833 case 364: /* Load VSX Vector Word & Splat Indexed */
4834 case 812: /* Load VSX Vector Halfword*8 Indexed */
4835 case 876: /* Load VSX Vector Byte*16 Indexed */
4836 case 269: /* Load VSX Vector with Length */
4837 case 301: /* Load VSX Vector Left-justified with Length */
4838 case 781: /* Load VSX Scalar as Integer Byte & Zero Indexed */
4839 case 813: /* Load VSX Scalar as Integer Halfword & Zero Indexed */
4840 case 403: /* Move To VSR Word & Splat */
4841 case 435: /* Move To VSR Double Doubleword */
4842 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
4845 /* These write RA. Update CR if RC is set. */
4846 case 24: /* Shift Left Word */
4847 case 26: /* Count Leading Zeros Word */
4848 case 27: /* Shift Left Doubleword */
4850 case 58: /* Count Leading Zeros Doubleword */
4851 case 60: /* AND with Complement */
4853 case 284: /* Equivalent */
4855 case 476: /* NAND */
4856 case 412: /* OR with Complement */
4858 case 536: /* Shift Right Word */
4859 case 539: /* Shift Right Doubleword */
4860 case 922: /* Extend Sign Halfword */
4861 case 954: /* Extend Sign Byte */
4862 case 986: /* Extend Sign Word */
4863 case 538: /* Count Trailing Zeros Word */
4864 case 570: /* Count Trailing Zeros Doubleword */
4865 case 890: /* Extend-Sign Word and Shift Left Immediate (445) */
4866 case 890 | 1: /* Extend-Sign Word and Shift Left Immediate (445) */
4868 if (ext
== 444 && tdep
->ppc_ppr_regnum
>= 0
4869 && (PPC_RS (insn
) == PPC_RA (insn
))
4870 && (PPC_RA (insn
) == PPC_RB (insn
))
4873 /* or Rx,Rx,Rx alters PRI in PPR. */
4874 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ppr_regnum
);
4879 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4880 record_full_arch_list_add_reg (regcache
,
4881 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4885 case 181: /* Store Doubleword with Update Indexed */
4886 case 183: /* Store Word with Update Indexed */
4887 case 247: /* Store Byte with Update Indexed */
4888 case 439: /* Store Half Word with Update Indexed */
4889 case 695: /* Store Floating-Point Single with Update Indexed */
4890 case 759: /* Store Floating-Point Double with Update Indexed */
4891 record_full_arch_list_add_reg (regcache
,
4892 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4894 case 135: /* Store Vector Element Byte Indexed */
4895 case 167: /* Store Vector Element Halfword Indexed */
4896 case 199: /* Store Vector Element Word Indexed */
4897 case 231: /* Store Vector Indexed */
4898 case 487: /* Store Vector Indexed LRU */
4899 case 716: /* Store VSX Scalar Doubleword Indexed */
4900 case 140: /* Store VSX Scalar as Integer Word Indexed */
4901 case 652: /* Store VSX Scalar Single-Precision Indexed */
4902 case 972: /* Store VSX Vector Doubleword*2 Indexed */
4903 case 908: /* Store VSX Vector Word*4 Indexed */
4904 case 149: /* Store Doubleword Indexed */
4905 case 151: /* Store Word Indexed */
4906 case 215: /* Store Byte Indexed */
4907 case 407: /* Store Half Word Indexed */
4908 case 694: /* Store Byte Conditional Indexed */
4909 case 726: /* Store Halfword Conditional Indexed */
4910 case 150: /* Store Word Conditional Indexed */
4911 case 214: /* Store Doubleword Conditional Indexed */
4912 case 182: /* Store Quadword Conditional Indexed */
4913 case 662: /* Store Word Byte-Reverse Indexed */
4914 case 918: /* Store Halfword Byte-Reverse Indexed */
4915 case 660: /* Store Doubleword Byte-Reverse Indexed */
4916 case 663: /* Store Floating-Point Single Indexed */
4917 case 727: /* Store Floating-Point Double Indexed */
4918 case 919: /* Store Floating-Point Double Pair Indexed */
4919 case 983: /* Store Floating-Point as Integer Word Indexed */
4920 case 396: /* Store VSX Vector Indexed */
4921 case 940: /* Store VSX Vector Halfword*8 Indexed */
4922 case 1004: /* Store VSX Vector Byte*16 Indexed */
4923 case 909: /* Store VSX Scalar as Integer Byte Indexed */
4924 case 941: /* Store VSX Scalar as Integer Halfword Indexed */
4925 if (ext
== 694 || ext
== 726 || ext
== 150 || ext
== 214 || ext
== 182)
4926 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4929 if (PPC_RA (insn
) != 0)
4930 regcache_raw_read_unsigned (regcache
,
4931 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4932 regcache_raw_read_unsigned (regcache
,
4933 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
4938 case 183: /* Store Word with Update Indexed */
4939 case 199: /* Store Vector Element Word Indexed */
4940 case 140: /* Store VSX Scalar as Integer Word Indexed */
4941 case 652: /* Store VSX Scalar Single-Precision Indexed */
4942 case 151: /* Store Word Indexed */
4943 case 150: /* Store Word Conditional Indexed */
4944 case 662: /* Store Word Byte-Reverse Indexed */
4945 case 663: /* Store Floating-Point Single Indexed */
4946 case 695: /* Store Floating-Point Single with Update Indexed */
4947 case 983: /* Store Floating-Point as Integer Word Indexed */
4950 case 247: /* Store Byte with Update Indexed */
4951 case 135: /* Store Vector Element Byte Indexed */
4952 case 215: /* Store Byte Indexed */
4953 case 694: /* Store Byte Conditional Indexed */
4954 case 909: /* Store VSX Scalar as Integer Byte Indexed */
4957 case 439: /* Store Halfword with Update Indexed */
4958 case 167: /* Store Vector Element Halfword Indexed */
4959 case 407: /* Store Halfword Indexed */
4960 case 726: /* Store Halfword Conditional Indexed */
4961 case 918: /* Store Halfword Byte-Reverse Indexed */
4962 case 941: /* Store VSX Scalar as Integer Halfword Indexed */
4965 case 181: /* Store Doubleword with Update Indexed */
4966 case 716: /* Store VSX Scalar Doubleword Indexed */
4967 case 149: /* Store Doubleword Indexed */
4968 case 214: /* Store Doubleword Conditional Indexed */
4969 case 660: /* Store Doubleword Byte-Reverse Indexed */
4970 case 727: /* Store Floating-Point Double Indexed */
4971 case 759: /* Store Floating-Point Double with Update Indexed */
4974 case 972: /* Store VSX Vector Doubleword*2 Indexed */
4975 case 908: /* Store VSX Vector Word*4 Indexed */
4976 case 182: /* Store Quadword Conditional Indexed */
4977 case 231: /* Store Vector Indexed */
4978 case 487: /* Store Vector Indexed LRU */
4979 case 919: /* Store Floating-Point Double Pair Indexed */
4980 case 396: /* Store VSX Vector Indexed */
4981 case 940: /* Store VSX Vector Halfword*8 Indexed */
4982 case 1004: /* Store VSX Vector Byte*16 Indexed */
4989 /* Align address for Store Vector instructions. */
4992 case 167: /* Store Vector Element Halfword Indexed */
4996 case 199: /* Store Vector Element Word Indexed */
5000 case 231: /* Store Vector Indexed */
5001 case 487: /* Store Vector Indexed LRU */
5006 record_full_arch_list_add_mem (ea
, size
);
5009 case 397: /* Store VSX Vector with Length */
5010 case 429: /* Store VSX Vector Left-justified with Length */
5012 if (PPC_RA (insn
) != 0)
5013 regcache_raw_read_unsigned (regcache
,
5014 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
5016 regcache_raw_read_unsigned (regcache
,
5017 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
5018 /* Store up to 16 bytes. */
5019 nb
= (rb
& 0xff) > 16 ? 16 : (rb
& 0xff);
5021 record_full_arch_list_add_mem (ea
, nb
);
5024 case 710: /* Store Word Atomic */
5025 case 742: /* Store Doubleword Atomic */
5027 if (PPC_RA (insn
) != 0)
5028 regcache_raw_read_unsigned (regcache
,
5029 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
5033 case 710: /* Store Word Atomic */
5036 case 742: /* Store Doubleword Atomic */
5042 record_full_arch_list_add_mem (ea
, size
);
5045 case 725: /* Store String Word Immediate */
5047 if (PPC_RA (insn
) != 0)
5048 regcache_raw_read_unsigned (regcache
,
5049 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
5056 record_full_arch_list_add_mem (ea
, nb
);
5060 case 661: /* Store String Word Indexed */
5062 if (PPC_RA (insn
) != 0)
5063 regcache_raw_read_unsigned (regcache
,
5064 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
5067 regcache_raw_read_unsigned (regcache
, tdep
->ppc_xer_regnum
, &xer
);
5068 nb
= PPC_XER_NB (xer
);
5072 regcache_raw_read_unsigned (regcache
,
5073 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
),
5076 record_full_arch_list_add_mem (ea
, nb
);
5081 case 467: /* Move To Special Purpose Register */
5082 switch (PPC_SPR (insn
))
5085 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
5088 if (tdep
->ppc_dscr_regnum
>= 0)
5089 record_full_arch_list_add_reg (regcache
, tdep
->ppc_dscr_regnum
);
5092 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
5095 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
5097 case 256: /* VRSAVE */
5098 record_full_arch_list_add_reg (regcache
, tdep
->ppc_vrsave_regnum
);
5101 if (tdep
->ppc_tar_regnum
>= 0)
5102 record_full_arch_list_add_reg (regcache
, tdep
->ppc_tar_regnum
);
5106 if (tdep
->ppc_ppr_regnum
>= 0)
5107 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ppr_regnum
);
5113 case 147: /* Move To Split Little Endian */
5114 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ps_regnum
);
5117 case 512: /* Move to Condition Register from XER */
5118 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5119 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
5122 case 4: /* Trap Word */
5123 case 68: /* Trap Doubleword */
5124 case 430: /* Clear BHRB */
5125 case 598: /* Synchronize */
5126 case 62: /* Wait for Interrupt */
5128 case 22: /* Instruction Cache Block Touch */
5129 case 854: /* Enforce In-order Execution of I/O */
5130 case 246: /* Data Cache Block Touch for Store */
5131 case 54: /* Data Cache Block Store */
5132 case 86: /* Data Cache Block Flush */
5133 case 278: /* Data Cache Block Touch */
5134 case 758: /* Data Cache Block Allocate */
5135 case 982: /* Instruction Cache Block Invalidate */
5136 case 774: /* Copy */
5137 case 838: /* CP_Abort */
5140 case 654: /* Transaction Begin */
5141 case 686: /* Transaction End */
5142 case 750: /* Transaction Suspend or Resume */
5143 case 782: /* Transaction Abort Word Conditional */
5144 case 814: /* Transaction Abort Doubleword Conditional */
5145 case 846: /* Transaction Abort Word Conditional Immediate */
5146 case 878: /* Transaction Abort Doubleword Conditional Immediate */
5147 case 910: /* Transaction Abort */
5148 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ps_regnum
);
5150 case 718: /* Transaction Check */
5151 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5154 case 1014: /* Data Cache Block set to Zero */
5155 if (target_auxv_search (current_inferior ()->top_target (),
5156 AT_DCACHEBSIZE
, &at_dcsz
) <= 0
5158 at_dcsz
= 128; /* Assume 128-byte cache line size (POWER8) */
5161 if (PPC_RA (insn
) != 0)
5162 regcache_raw_read_unsigned (regcache
,
5163 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
5164 regcache_raw_read_unsigned (regcache
,
5165 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
5166 ea
= (ra
+ rb
) & ~((ULONGEST
) (at_dcsz
- 1));
5167 record_full_arch_list_add_mem (ea
, at_dcsz
);
5172 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5173 "at %s, 31-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
5177 /* Parse and record instructions of primary opcode-59 at ADDR.
5178 Return 0 if successful. */
5181 ppc_process_record_op59 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5182 CORE_ADDR addr
, uint32_t insn
)
5184 ppc_gdbarch_tdep
*tdep
= (ppc_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
5185 int ext
= PPC_EXTOP (insn
);
5189 case 18: /* Floating Divide */
5190 case 20: /* Floating Subtract */
5191 case 21: /* Floating Add */
5192 case 22: /* Floating Square Root */
5193 case 24: /* Floating Reciprocal Estimate */
5194 case 25: /* Floating Multiply */
5195 case 26: /* Floating Reciprocal Square Root Estimate */
5196 case 28: /* Floating Multiply-Subtract */
5197 case 29: /* Floating Multiply-Add */
5198 case 30: /* Floating Negative Multiply-Subtract */
5199 case 31: /* Floating Negative Multiply-Add */
5200 record_full_arch_list_add_reg (regcache
,
5201 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5203 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5204 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5211 case 2: /* DFP Add */
5212 case 3: /* DFP Quantize */
5213 case 34: /* DFP Multiply */
5214 case 35: /* DFP Reround */
5215 case 67: /* DFP Quantize Immediate */
5216 case 99: /* DFP Round To FP Integer With Inexact */
5217 case 227: /* DFP Round To FP Integer Without Inexact */
5218 case 258: /* DFP Convert To DFP Long! */
5219 case 290: /* DFP Convert To Fixed */
5220 case 514: /* DFP Subtract */
5221 case 546: /* DFP Divide */
5222 case 770: /* DFP Round To DFP Short! */
5223 case 802: /* DFP Convert From Fixed */
5224 case 834: /* DFP Encode BCD To DPD */
5226 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5227 record_full_arch_list_add_reg (regcache
,
5228 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5229 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5232 case 130: /* DFP Compare Ordered */
5233 case 162: /* DFP Test Exponent */
5234 case 194: /* DFP Test Data Class */
5235 case 226: /* DFP Test Data Group */
5236 case 642: /* DFP Compare Unordered */
5237 case 674: /* DFP Test Significance */
5238 case 675: /* DFP Test Significance Immediate */
5239 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5240 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5243 case 66: /* DFP Shift Significand Left Immediate */
5244 case 98: /* DFP Shift Significand Right Immediate */
5245 case 322: /* DFP Decode DPD To BCD */
5246 case 354: /* DFP Extract Biased Exponent */
5247 case 866: /* DFP Insert Biased Exponent */
5248 record_full_arch_list_add_reg (regcache
,
5249 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5251 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5254 case 846: /* Floating Convert From Integer Doubleword Single */
5255 case 974: /* Floating Convert From Integer Doubleword Unsigned
5257 record_full_arch_list_add_reg (regcache
,
5258 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5260 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5261 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5266 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5267 "at %s, 59-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
5271 /* Parse and record instructions of primary opcode-60 at ADDR.
5272 Return 0 if successful. */
5275 ppc_process_record_op60 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5276 CORE_ADDR addr
, uint32_t insn
)
5278 ppc_gdbarch_tdep
*tdep
= (ppc_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
5279 int ext
= PPC_EXTOP (insn
);
5283 case 0: /* VSX Scalar Add Single-Precision */
5284 case 32: /* VSX Scalar Add Double-Precision */
5285 case 24: /* VSX Scalar Divide Single-Precision */
5286 case 56: /* VSX Scalar Divide Double-Precision */
5287 case 176: /* VSX Scalar Copy Sign Double-Precision */
5288 case 33: /* VSX Scalar Multiply-Add Double-Precision */
5289 case 41: /* ditto */
5290 case 1: /* VSX Scalar Multiply-Add Single-Precision */
5292 case 160: /* VSX Scalar Maximum Double-Precision */
5293 case 168: /* VSX Scalar Minimum Double-Precision */
5294 case 49: /* VSX Scalar Multiply-Subtract Double-Precision */
5295 case 57: /* ditto */
5296 case 17: /* VSX Scalar Multiply-Subtract Single-Precision */
5297 case 25: /* ditto */
5298 case 48: /* VSX Scalar Multiply Double-Precision */
5299 case 16: /* VSX Scalar Multiply Single-Precision */
5300 case 161: /* VSX Scalar Negative Multiply-Add Double-Precision */
5301 case 169: /* ditto */
5302 case 129: /* VSX Scalar Negative Multiply-Add Single-Precision */
5303 case 137: /* ditto */
5304 case 177: /* VSX Scalar Negative Multiply-Subtract Double-Precision */
5305 case 185: /* ditto */
5306 case 145: /* VSX Scalar Negative Multiply-Subtract Single-Precision */
5307 case 153: /* ditto */
5308 case 40: /* VSX Scalar Subtract Double-Precision */
5309 case 8: /* VSX Scalar Subtract Single-Precision */
5310 case 96: /* VSX Vector Add Double-Precision */
5311 case 64: /* VSX Vector Add Single-Precision */
5312 case 120: /* VSX Vector Divide Double-Precision */
5313 case 88: /* VSX Vector Divide Single-Precision */
5314 case 97: /* VSX Vector Multiply-Add Double-Precision */
5315 case 105: /* ditto */
5316 case 65: /* VSX Vector Multiply-Add Single-Precision */
5317 case 73: /* ditto */
5318 case 224: /* VSX Vector Maximum Double-Precision */
5319 case 192: /* VSX Vector Maximum Single-Precision */
5320 case 232: /* VSX Vector Minimum Double-Precision */
5321 case 200: /* VSX Vector Minimum Single-Precision */
5322 case 113: /* VSX Vector Multiply-Subtract Double-Precision */
5323 case 121: /* ditto */
5324 case 81: /* VSX Vector Multiply-Subtract Single-Precision */
5325 case 89: /* ditto */
5326 case 112: /* VSX Vector Multiply Double-Precision */
5327 case 80: /* VSX Vector Multiply Single-Precision */
5328 case 225: /* VSX Vector Negative Multiply-Add Double-Precision */
5329 case 233: /* ditto */
5330 case 193: /* VSX Vector Negative Multiply-Add Single-Precision */
5331 case 201: /* ditto */
5332 case 241: /* VSX Vector Negative Multiply-Subtract Double-Precision */
5333 case 249: /* ditto */
5334 case 209: /* VSX Vector Negative Multiply-Subtract Single-Precision */
5335 case 217: /* ditto */
5336 case 104: /* VSX Vector Subtract Double-Precision */
5337 case 72: /* VSX Vector Subtract Single-Precision */
5338 case 128: /* VSX Scalar Maximum Type-C Double-Precision */
5339 case 136: /* VSX Scalar Minimum Type-C Double-Precision */
5340 case 144: /* VSX Scalar Maximum Type-J Double-Precision */
5341 case 152: /* VSX Scalar Minimum Type-J Double-Precision */
5342 case 3: /* VSX Scalar Compare Equal Double-Precision */
5343 case 11: /* VSX Scalar Compare Greater Than Double-Precision */
5344 case 19: /* VSX Scalar Compare Greater Than or Equal
5346 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5348 case 240: /* VSX Vector Copy Sign Double-Precision */
5349 case 208: /* VSX Vector Copy Sign Single-Precision */
5350 case 130: /* VSX Logical AND */
5351 case 138: /* VSX Logical AND with Complement */
5352 case 186: /* VSX Logical Equivalence */
5353 case 178: /* VSX Logical NAND */
5354 case 170: /* VSX Logical OR with Complement */
5355 case 162: /* VSX Logical NOR */
5356 case 146: /* VSX Logical OR */
5357 case 154: /* VSX Logical XOR */
5358 case 18: /* VSX Merge High Word */
5359 case 50: /* VSX Merge Low Word */
5360 case 10: /* VSX Permute Doubleword Immediate (DM=0) */
5361 case 10 | 0x20: /* VSX Permute Doubleword Immediate (DM=1) */
5362 case 10 | 0x40: /* VSX Permute Doubleword Immediate (DM=2) */
5363 case 10 | 0x60: /* VSX Permute Doubleword Immediate (DM=3) */
5364 case 2: /* VSX Shift Left Double by Word Immediate (SHW=0) */
5365 case 2 | 0x20: /* VSX Shift Left Double by Word Immediate (SHW=1) */
5366 case 2 | 0x40: /* VSX Shift Left Double by Word Immediate (SHW=2) */
5367 case 2 | 0x60: /* VSX Shift Left Double by Word Immediate (SHW=3) */
5368 case 216: /* VSX Vector Insert Exponent Single-Precision */
5369 case 248: /* VSX Vector Insert Exponent Double-Precision */
5370 case 26: /* VSX Vector Permute */
5371 case 58: /* VSX Vector Permute Right-indexed */
5372 case 213: /* VSX Vector Test Data Class Single-Precision (DC=0) */
5373 case 213 | 0x8: /* VSX Vector Test Data Class Single-Precision (DC=1) */
5374 case 245: /* VSX Vector Test Data Class Double-Precision (DC=0) */
5375 case 245 | 0x8: /* VSX Vector Test Data Class Double-Precision (DC=1) */
5376 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5379 case 61: /* VSX Scalar Test for software Divide Double-Precision */
5380 case 125: /* VSX Vector Test for software Divide Double-Precision */
5381 case 93: /* VSX Vector Test for software Divide Single-Precision */
5382 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5385 case 35: /* VSX Scalar Compare Unordered Double-Precision */
5386 case 43: /* VSX Scalar Compare Ordered Double-Precision */
5387 case 59: /* VSX Scalar Compare Exponents Double-Precision */
5388 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5389 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5393 switch ((ext
>> 2) & 0x7f) /* Mask out Rc-bit. */
5395 case 99: /* VSX Vector Compare Equal To Double-Precision */
5396 case 67: /* VSX Vector Compare Equal To Single-Precision */
5397 case 115: /* VSX Vector Compare Greater Than or
5398 Equal To Double-Precision */
5399 case 83: /* VSX Vector Compare Greater Than or
5400 Equal To Single-Precision */
5401 case 107: /* VSX Vector Compare Greater Than Double-Precision */
5402 case 75: /* VSX Vector Compare Greater Than Single-Precision */
5404 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5405 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5406 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5412 case 265: /* VSX Scalar round Double-Precision to
5413 Single-Precision and Convert to
5414 Single-Precision format */
5415 case 344: /* VSX Scalar truncate Double-Precision to
5416 Integer and Convert to Signed Integer
5417 Doubleword format with Saturate */
5418 case 88: /* VSX Scalar truncate Double-Precision to
5419 Integer and Convert to Signed Integer Word
5420 Format with Saturate */
5421 case 328: /* VSX Scalar truncate Double-Precision integer
5422 and Convert to Unsigned Integer Doubleword
5423 Format with Saturate */
5424 case 72: /* VSX Scalar truncate Double-Precision to
5425 Integer and Convert to Unsigned Integer Word
5426 Format with Saturate */
5427 case 329: /* VSX Scalar Convert Single-Precision to
5428 Double-Precision format */
5429 case 376: /* VSX Scalar Convert Signed Integer
5430 Doubleword to floating-point format and
5431 Round to Double-Precision format */
5432 case 312: /* VSX Scalar Convert Signed Integer
5433 Doubleword to floating-point format and
5434 round to Single-Precision */
5435 case 360: /* VSX Scalar Convert Unsigned Integer
5436 Doubleword to floating-point format and
5437 Round to Double-Precision format */
5438 case 296: /* VSX Scalar Convert Unsigned Integer
5439 Doubleword to floating-point format and
5440 Round to Single-Precision */
5441 case 73: /* VSX Scalar Round to Double-Precision Integer
5442 Using Round to Nearest Away */
5443 case 107: /* VSX Scalar Round to Double-Precision Integer
5444 Exact using Current rounding mode */
5445 case 121: /* VSX Scalar Round to Double-Precision Integer
5446 Using Round toward -Infinity */
5447 case 105: /* VSX Scalar Round to Double-Precision Integer
5448 Using Round toward +Infinity */
5449 case 89: /* VSX Scalar Round to Double-Precision Integer
5450 Using Round toward Zero */
5451 case 90: /* VSX Scalar Reciprocal Estimate Double-Precision */
5452 case 26: /* VSX Scalar Reciprocal Estimate Single-Precision */
5453 case 281: /* VSX Scalar Round to Single-Precision */
5454 case 74: /* VSX Scalar Reciprocal Square Root Estimate
5456 case 10: /* VSX Scalar Reciprocal Square Root Estimate
5458 case 75: /* VSX Scalar Square Root Double-Precision */
5459 case 11: /* VSX Scalar Square Root Single-Precision */
5460 case 393: /* VSX Vector round Double-Precision to
5461 Single-Precision and Convert to
5462 Single-Precision format */
5463 case 472: /* VSX Vector truncate Double-Precision to
5464 Integer and Convert to Signed Integer
5465 Doubleword format with Saturate */
5466 case 216: /* VSX Vector truncate Double-Precision to
5467 Integer and Convert to Signed Integer Word
5468 Format with Saturate */
5469 case 456: /* VSX Vector truncate Double-Precision to
5470 Integer and Convert to Unsigned Integer
5471 Doubleword format with Saturate */
5472 case 200: /* VSX Vector truncate Double-Precision to
5473 Integer and Convert to Unsigned Integer Word
5474 Format with Saturate */
5475 case 457: /* VSX Vector Convert Single-Precision to
5476 Double-Precision format */
5477 case 408: /* VSX Vector truncate Single-Precision to
5478 Integer and Convert to Signed Integer
5479 Doubleword format with Saturate */
5480 case 152: /* VSX Vector truncate Single-Precision to
5481 Integer and Convert to Signed Integer Word
5482 Format with Saturate */
5483 case 392: /* VSX Vector truncate Single-Precision to
5484 Integer and Convert to Unsigned Integer
5485 Doubleword format with Saturate */
5486 case 136: /* VSX Vector truncate Single-Precision to
5487 Integer and Convert to Unsigned Integer Word
5488 Format with Saturate */
5489 case 504: /* VSX Vector Convert and round Signed Integer
5490 Doubleword to Double-Precision format */
5491 case 440: /* VSX Vector Convert and round Signed Integer
5492 Doubleword to Single-Precision format */
5493 case 248: /* VSX Vector Convert Signed Integer Word to
5494 Double-Precision format */
5495 case 184: /* VSX Vector Convert and round Signed Integer
5496 Word to Single-Precision format */
5497 case 488: /* VSX Vector Convert and round Unsigned
5498 Integer Doubleword to Double-Precision format */
5499 case 424: /* VSX Vector Convert and round Unsigned
5500 Integer Doubleword to Single-Precision format */
5501 case 232: /* VSX Vector Convert and round Unsigned
5502 Integer Word to Double-Precision format */
5503 case 168: /* VSX Vector Convert and round Unsigned
5504 Integer Word to Single-Precision format */
5505 case 201: /* VSX Vector Round to Double-Precision
5506 Integer using round to Nearest Away */
5507 case 235: /* VSX Vector Round to Double-Precision
5508 Integer Exact using Current rounding mode */
5509 case 249: /* VSX Vector Round to Double-Precision
5510 Integer using round toward -Infinity */
5511 case 233: /* VSX Vector Round to Double-Precision
5512 Integer using round toward +Infinity */
5513 case 217: /* VSX Vector Round to Double-Precision
5514 Integer using round toward Zero */
5515 case 218: /* VSX Vector Reciprocal Estimate Double-Precision */
5516 case 154: /* VSX Vector Reciprocal Estimate Single-Precision */
5517 case 137: /* VSX Vector Round to Single-Precision Integer
5518 Using Round to Nearest Away */
5519 case 171: /* VSX Vector Round to Single-Precision Integer
5520 Exact Using Current rounding mode */
5521 case 185: /* VSX Vector Round to Single-Precision Integer
5522 Using Round toward -Infinity */
5523 case 169: /* VSX Vector Round to Single-Precision Integer
5524 Using Round toward +Infinity */
5525 case 153: /* VSX Vector Round to Single-Precision Integer
5526 Using round toward Zero */
5527 case 202: /* VSX Vector Reciprocal Square Root Estimate
5529 case 138: /* VSX Vector Reciprocal Square Root Estimate
5531 case 203: /* VSX Vector Square Root Double-Precision */
5532 case 139: /* VSX Vector Square Root Single-Precision */
5533 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5535 case 345: /* VSX Scalar Absolute Value Double-Precision */
5536 case 267: /* VSX Scalar Convert Scalar Single-Precision to
5537 Vector Single-Precision format Non-signalling */
5538 case 331: /* VSX Scalar Convert Single-Precision to
5539 Double-Precision format Non-signalling */
5540 case 361: /* VSX Scalar Negative Absolute Value Double-Precision */
5541 case 377: /* VSX Scalar Negate Double-Precision */
5542 case 473: /* VSX Vector Absolute Value Double-Precision */
5543 case 409: /* VSX Vector Absolute Value Single-Precision */
5544 case 489: /* VSX Vector Negative Absolute Value Double-Precision */
5545 case 425: /* VSX Vector Negative Absolute Value Single-Precision */
5546 case 505: /* VSX Vector Negate Double-Precision */
5547 case 441: /* VSX Vector Negate Single-Precision */
5548 case 164: /* VSX Splat Word */
5549 case 165: /* VSX Vector Extract Unsigned Word */
5550 case 181: /* VSX Vector Insert Word */
5551 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5554 case 298: /* VSX Scalar Test Data Class Single-Precision */
5555 case 362: /* VSX Scalar Test Data Class Double-Precision */
5556 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5558 case 106: /* VSX Scalar Test for software Square Root
5560 case 234: /* VSX Vector Test for software Square Root
5562 case 170: /* VSX Vector Test for software Square Root
5564 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5568 switch (PPC_FIELD (insn
, 11, 5))
5570 case 0: /* VSX Scalar Extract Exponent Double-Precision */
5571 case 1: /* VSX Scalar Extract Significand Double-Precision */
5572 record_full_arch_list_add_reg (regcache
,
5573 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5575 case 16: /* VSX Scalar Convert Half-Precision format to
5576 Double-Precision format */
5577 case 17: /* VSX Scalar round & Convert Double-Precision format
5578 to Half-Precision format */
5579 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5580 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5586 switch (PPC_FIELD (insn
, 11, 5))
5588 case 24: /* VSX Vector Convert Half-Precision format to
5589 Single-Precision format */
5590 case 25: /* VSX Vector round and Convert Single-Precision format
5591 to Half-Precision format */
5592 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5594 case 0: /* VSX Vector Extract Exponent Double-Precision */
5595 case 1: /* VSX Vector Extract Significand Double-Precision */
5596 case 7: /* VSX Vector Byte-Reverse Halfword */
5597 case 8: /* VSX Vector Extract Exponent Single-Precision */
5598 case 9: /* VSX Vector Extract Significand Single-Precision */
5599 case 15: /* VSX Vector Byte-Reverse Word */
5600 case 23: /* VSX Vector Byte-Reverse Doubleword */
5601 case 31: /* VSX Vector Byte-Reverse Quadword */
5602 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5610 case 360: /* VSX Vector Splat Immediate Byte */
5611 if (PPC_FIELD (insn
, 11, 2) == 0)
5613 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5617 case 918: /* VSX Scalar Insert Exponent Double-Precision */
5618 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5622 if (((ext
>> 3) & 0x3) == 3) /* VSX Select */
5624 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5628 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5629 "at %s, 60-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
5633 /* Parse and record instructions of primary opcode-61 at ADDR.
5634 Return 0 if successful. */
5637 ppc_process_record_op61 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5638 CORE_ADDR addr
, uint32_t insn
)
5640 ppc_gdbarch_tdep
*tdep
= (ppc_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
5646 case 0: /* Store Floating-Point Double Pair */
5647 case 2: /* Store VSX Scalar Doubleword */
5648 case 3: /* Store VSX Scalar Single */
5649 if (PPC_RA (insn
) != 0)
5650 regcache_raw_read_unsigned (regcache
,
5651 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5653 ea
+= PPC_DS (insn
) << 2;
5656 case 0: /* Store Floating-Point Double Pair */
5659 case 2: /* Store VSX Scalar Doubleword */
5662 case 3: /* Store VSX Scalar Single */
5668 record_full_arch_list_add_mem (ea
, size
);
5674 case 1: /* Load VSX Vector */
5675 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5677 case 5: /* Store VSX Vector */
5678 if (PPC_RA (insn
) != 0)
5679 regcache_raw_read_unsigned (regcache
,
5680 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5682 ea
+= PPC_DQ (insn
) << 4;
5683 record_full_arch_list_add_mem (ea
, 16);
5687 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5688 "at %s.\n", insn
, paddress (gdbarch
, addr
));
5692 /* Parse and record instructions of primary opcode-63 at ADDR.
5693 Return 0 if successful. */
5696 ppc_process_record_op63 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5697 CORE_ADDR addr
, uint32_t insn
)
5699 ppc_gdbarch_tdep
*tdep
= (ppc_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
5700 int ext
= PPC_EXTOP (insn
);
5705 case 18: /* Floating Divide */
5706 case 20: /* Floating Subtract */
5707 case 21: /* Floating Add */
5708 case 22: /* Floating Square Root */
5709 case 24: /* Floating Reciprocal Estimate */
5710 case 25: /* Floating Multiply */
5711 case 26: /* Floating Reciprocal Square Root Estimate */
5712 case 28: /* Floating Multiply-Subtract */
5713 case 29: /* Floating Multiply-Add */
5714 case 30: /* Floating Negative Multiply-Subtract */
5715 case 31: /* Floating Negative Multiply-Add */
5716 record_full_arch_list_add_reg (regcache
,
5717 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5719 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5720 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5723 case 23: /* Floating Select */
5724 record_full_arch_list_add_reg (regcache
,
5725 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5727 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5733 case 5: /* VSX Scalar Round to Quad-Precision Integer */
5734 case 37: /* VSX Scalar Round Quad-Precision to Double-Extended
5736 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5737 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5743 case 2: /* DFP Add Quad */
5744 case 3: /* DFP Quantize Quad */
5745 case 34: /* DFP Multiply Quad */
5746 case 35: /* DFP Reround Quad */
5747 case 67: /* DFP Quantize Immediate Quad */
5748 case 99: /* DFP Round To FP Integer With Inexact Quad */
5749 case 227: /* DFP Round To FP Integer Without Inexact Quad */
5750 case 258: /* DFP Convert To DFP Extended Quad */
5751 case 514: /* DFP Subtract Quad */
5752 case 546: /* DFP Divide Quad */
5753 case 770: /* DFP Round To DFP Long Quad */
5754 case 802: /* DFP Convert From Fixed Quad */
5755 case 834: /* DFP Encode BCD To DPD Quad */
5757 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5758 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
5759 record_full_arch_list_add_reg (regcache
, tmp
);
5760 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5761 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5764 case 130: /* DFP Compare Ordered Quad */
5765 case 162: /* DFP Test Exponent Quad */
5766 case 194: /* DFP Test Data Class Quad */
5767 case 226: /* DFP Test Data Group Quad */
5768 case 642: /* DFP Compare Unordered Quad */
5769 case 674: /* DFP Test Significance Quad */
5770 case 675: /* DFP Test Significance Immediate Quad */
5771 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5772 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5775 case 66: /* DFP Shift Significand Left Immediate Quad */
5776 case 98: /* DFP Shift Significand Right Immediate Quad */
5777 case 322: /* DFP Decode DPD To BCD Quad */
5778 case 866: /* DFP Insert Biased Exponent Quad */
5779 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
5780 record_full_arch_list_add_reg (regcache
, tmp
);
5781 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5783 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5786 case 290: /* DFP Convert To Fixed Quad */
5787 record_full_arch_list_add_reg (regcache
,
5788 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5790 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5791 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5794 case 354: /* DFP Extract Biased Exponent Quad */
5795 record_full_arch_list_add_reg (regcache
,
5796 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5798 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5801 case 12: /* Floating Round to Single-Precision */
5802 case 14: /* Floating Convert To Integer Word */
5803 case 15: /* Floating Convert To Integer Word
5804 with round toward Zero */
5805 case 142: /* Floating Convert To Integer Word Unsigned */
5806 case 143: /* Floating Convert To Integer Word Unsigned
5807 with round toward Zero */
5808 case 392: /* Floating Round to Integer Nearest */
5809 case 424: /* Floating Round to Integer Toward Zero */
5810 case 456: /* Floating Round to Integer Plus */
5811 case 488: /* Floating Round to Integer Minus */
5812 case 814: /* Floating Convert To Integer Doubleword */
5813 case 815: /* Floating Convert To Integer Doubleword
5814 with round toward Zero */
5815 case 846: /* Floating Convert From Integer Doubleword */
5816 case 942: /* Floating Convert To Integer Doubleword Unsigned */
5817 case 943: /* Floating Convert To Integer Doubleword Unsigned
5818 with round toward Zero */
5819 case 974: /* Floating Convert From Integer Doubleword Unsigned */
5820 record_full_arch_list_add_reg (regcache
,
5821 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5823 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5824 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5828 switch (PPC_FIELD (insn
, 11, 5))
5830 case 1: /* Move From FPSCR & Clear Enables */
5831 case 20: /* Move From FPSCR Control & set DRN */
5832 case 21: /* Move From FPSCR Control & set DRN Immediate */
5833 case 22: /* Move From FPSCR Control & set RN */
5834 case 23: /* Move From FPSCR Control & set RN Immediate */
5835 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5837 case 0: /* Move From FPSCR */
5838 case 24: /* Move From FPSCR Lightweight */
5839 if (PPC_FIELD (insn
, 11, 5) == 0 && PPC_RC (insn
))
5840 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5841 record_full_arch_list_add_reg (regcache
,
5842 tdep
->ppc_fp0_regnum
5848 case 8: /* Floating Copy Sign */
5849 case 40: /* Floating Negate */
5850 case 72: /* Floating Move Register */
5851 case 136: /* Floating Negative Absolute Value */
5852 case 264: /* Floating Absolute Value */
5853 record_full_arch_list_add_reg (regcache
,
5854 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5856 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5859 case 838: /* Floating Merge Odd Word */
5860 case 966: /* Floating Merge Even Word */
5861 record_full_arch_list_add_reg (regcache
,
5862 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5865 case 38: /* Move To FPSCR Bit 1 */
5866 case 70: /* Move To FPSCR Bit 0 */
5867 case 134: /* Move To FPSCR Field Immediate */
5868 case 711: /* Move To FPSCR Fields */
5870 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5871 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5874 case 0: /* Floating Compare Unordered */
5875 case 32: /* Floating Compare Ordered */
5876 case 64: /* Move to Condition Register from FPSCR */
5877 case 132: /* VSX Scalar Compare Ordered Quad-Precision */
5878 case 164: /* VSX Scalar Compare Exponents Quad-Precision */
5879 case 644: /* VSX Scalar Compare Unordered Quad-Precision */
5880 case 708: /* VSX Scalar Test Data Class Quad-Precision */
5881 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5883 case 128: /* Floating Test for software Divide */
5884 case 160: /* Floating Test for software Square Root */
5885 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5888 case 4: /* VSX Scalar Add Quad-Precision */
5889 case 36: /* VSX Scalar Multiply Quad-Precision */
5890 case 388: /* VSX Scalar Multiply-Add Quad-Precision */
5891 case 420: /* VSX Scalar Multiply-Subtract Quad-Precision */
5892 case 452: /* VSX Scalar Negative Multiply-Add Quad-Precision */
5893 case 484: /* VSX Scalar Negative Multiply-Subtract
5895 case 516: /* VSX Scalar Subtract Quad-Precision */
5896 case 548: /* VSX Scalar Divide Quad-Precision */
5897 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5899 case 100: /* VSX Scalar Copy Sign Quad-Precision */
5900 case 868: /* VSX Scalar Insert Exponent Quad-Precision */
5901 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5905 switch (PPC_FIELD (insn
, 11, 5))
5907 case 27: /* VSX Scalar Square Root Quad-Precision */
5908 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5910 case 0: /* VSX Scalar Absolute Quad-Precision */
5911 case 2: /* VSX Scalar Extract Exponent Quad-Precision */
5912 case 8: /* VSX Scalar Negative Absolute Quad-Precision */
5913 case 16: /* VSX Scalar Negate Quad-Precision */
5914 case 18: /* VSX Scalar Extract Significand Quad-Precision */
5915 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5921 switch (PPC_FIELD (insn
, 11, 5))
5923 case 1: /* VSX Scalar truncate & Convert Quad-Precision format
5924 to Unsigned Word format */
5925 case 2: /* VSX Scalar Convert Unsigned Doubleword format to
5926 Quad-Precision format */
5927 case 9: /* VSX Scalar truncate & Convert Quad-Precision format
5928 to Signed Word format */
5929 case 10: /* VSX Scalar Convert Signed Doubleword format to
5930 Quad-Precision format */
5931 case 17: /* VSX Scalar truncate & Convert Quad-Precision format
5932 to Unsigned Doubleword format */
5933 case 20: /* VSX Scalar round & Convert Quad-Precision format to
5934 Double-Precision format */
5935 case 22: /* VSX Scalar Convert Double-Precision format to
5936 Quad-Precision format */
5937 case 25: /* VSX Scalar truncate & Convert Quad-Precision format
5938 to Signed Doubleword format */
5939 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5940 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5945 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5946 "at %s, 63-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
5950 /* Parse the current instruction and record the values of the registers and
5951 memory that will be changed in current instruction to "record_arch_list".
5952 Return -1 if something wrong. */
5955 ppc_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5958 ppc_gdbarch_tdep
*tdep
= (ppc_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
5959 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5963 insn
= read_memory_unsigned_integer (addr
, 4, byte_order
);
5964 op6
= PPC_OP6 (insn
);
5968 case 2: /* Trap Doubleword Immediate */
5969 case 3: /* Trap Word Immediate */
5974 if (ppc_process_record_op4 (gdbarch
, regcache
, addr
, insn
) != 0)
5978 case 17: /* System call */
5979 if (PPC_LEV (insn
) != 0)
5982 if (tdep
->ppc_syscall_record
!= NULL
)
5984 if (tdep
->ppc_syscall_record (regcache
) != 0)
5989 fprintf_unfiltered (gdb_stderr
, _("no syscall record support\n"));
5994 case 7: /* Multiply Low Immediate */
5995 record_full_arch_list_add_reg (regcache
,
5996 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5999 case 8: /* Subtract From Immediate Carrying */
6000 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
6001 record_full_arch_list_add_reg (regcache
,
6002 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
6005 case 10: /* Compare Logical Immediate */
6006 case 11: /* Compare Immediate */
6007 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
6010 case 13: /* Add Immediate Carrying and Record */
6011 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
6013 case 12: /* Add Immediate Carrying */
6014 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
6016 case 14: /* Add Immediate */
6017 case 15: /* Add Immediate Shifted */
6018 record_full_arch_list_add_reg (regcache
,
6019 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
6022 case 16: /* Branch Conditional */
6023 if ((PPC_BO (insn
) & 0x4) == 0)
6024 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
6026 case 18: /* Branch */
6028 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
6032 if (ppc_process_record_op19 (gdbarch
, regcache
, addr
, insn
) != 0)
6036 case 20: /* Rotate Left Word Immediate then Mask Insert */
6037 case 21: /* Rotate Left Word Immediate then AND with Mask */
6038 case 23: /* Rotate Left Word then AND with Mask */
6039 case 30: /* Rotate Left Doubleword Immediate then Clear Left */
6040 /* Rotate Left Doubleword Immediate then Clear Right */
6041 /* Rotate Left Doubleword Immediate then Clear */
6042 /* Rotate Left Doubleword then Clear Left */
6043 /* Rotate Left Doubleword then Clear Right */
6044 /* Rotate Left Doubleword Immediate then Mask Insert */
6046 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
6047 record_full_arch_list_add_reg (regcache
,
6048 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
6051 case 28: /* AND Immediate */
6052 case 29: /* AND Immediate Shifted */
6053 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
6055 case 24: /* OR Immediate */
6056 case 25: /* OR Immediate Shifted */
6057 case 26: /* XOR Immediate */
6058 case 27: /* XOR Immediate Shifted */
6059 record_full_arch_list_add_reg (regcache
,
6060 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
6064 if (ppc_process_record_op31 (gdbarch
, regcache
, addr
, insn
) != 0)
6068 case 33: /* Load Word and Zero with Update */
6069 case 35: /* Load Byte and Zero with Update */
6070 case 41: /* Load Halfword and Zero with Update */
6071 case 43: /* Load Halfword Algebraic with Update */
6072 record_full_arch_list_add_reg (regcache
,
6073 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
6075 case 32: /* Load Word and Zero */
6076 case 34: /* Load Byte and Zero */
6077 case 40: /* Load Halfword and Zero */
6078 case 42: /* Load Halfword Algebraic */
6079 record_full_arch_list_add_reg (regcache
,
6080 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
6083 case 46: /* Load Multiple Word */
6084 for (i
= PPC_RT (insn
); i
< 32; i
++)
6085 record_full_arch_list_add_reg (regcache
, tdep
->ppc_gp0_regnum
+ i
);
6088 case 56: /* Load Quadword */
6089 tmp
= tdep
->ppc_gp0_regnum
+ (PPC_RT (insn
) & ~1);
6090 record_full_arch_list_add_reg (regcache
, tmp
);
6091 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
6094 case 49: /* Load Floating-Point Single with Update */
6095 case 51: /* Load Floating-Point Double with Update */
6096 record_full_arch_list_add_reg (regcache
,
6097 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
6099 case 48: /* Load Floating-Point Single */
6100 case 50: /* Load Floating-Point Double */
6101 record_full_arch_list_add_reg (regcache
,
6102 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
6105 case 47: /* Store Multiple Word */
6109 if (PPC_RA (insn
) != 0)
6110 regcache_raw_read_unsigned (regcache
,
6111 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
6114 iaddr
+= PPC_D (insn
);
6115 record_full_arch_list_add_mem (iaddr
, 4 * (32 - PPC_RS (insn
)));
6119 case 37: /* Store Word with Update */
6120 case 39: /* Store Byte with Update */
6121 case 45: /* Store Halfword with Update */
6122 case 53: /* Store Floating-Point Single with Update */
6123 case 55: /* Store Floating-Point Double with Update */
6124 record_full_arch_list_add_reg (regcache
,
6125 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
6127 case 36: /* Store Word */
6128 case 38: /* Store Byte */
6129 case 44: /* Store Halfword */
6130 case 52: /* Store Floating-Point Single */
6131 case 54: /* Store Floating-Point Double */
6136 if (PPC_RA (insn
) != 0)
6137 regcache_raw_read_unsigned (regcache
,
6138 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
6140 iaddr
+= PPC_D (insn
);
6142 if (op6
== 36 || op6
== 37 || op6
== 52 || op6
== 53)
6144 else if (op6
== 54 || op6
== 55)
6146 else if (op6
== 44 || op6
== 45)
6148 else if (op6
== 38 || op6
== 39)
6153 record_full_arch_list_add_mem (iaddr
, size
);
6160 case 0: /* Load Floating-Point Double Pair */
6161 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_RT (insn
) & ~1);
6162 record_full_arch_list_add_reg (regcache
, tmp
);
6163 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
6165 case 2: /* Load VSX Scalar Doubleword */
6166 case 3: /* Load VSX Scalar Single */
6167 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
6174 case 58: /* Load Doubleword */
6175 /* Load Doubleword with Update */
6176 /* Load Word Algebraic */
6177 if (PPC_FIELD (insn
, 30, 2) > 2)
6180 record_full_arch_list_add_reg (regcache
,
6181 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
6182 if (PPC_BIT (insn
, 31))
6183 record_full_arch_list_add_reg (regcache
,
6184 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
6188 if (ppc_process_record_op59 (gdbarch
, regcache
, addr
, insn
) != 0)
6193 if (ppc_process_record_op60 (gdbarch
, regcache
, addr
, insn
) != 0)
6198 if (ppc_process_record_op61 (gdbarch
, regcache
, addr
, insn
) != 0)
6202 case 62: /* Store Doubleword */
6203 /* Store Doubleword with Update */
6204 /* Store Quadword with Update */
6208 int sub2
= PPC_FIELD (insn
, 30, 2);
6213 if (PPC_RA (insn
) != 0)
6214 regcache_raw_read_unsigned (regcache
,
6215 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
6218 size
= (sub2
== 2) ? 16 : 8;
6220 iaddr
+= PPC_DS (insn
) << 2;
6221 record_full_arch_list_add_mem (iaddr
, size
);
6223 if (op6
== 62 && sub2
== 1)
6224 record_full_arch_list_add_reg (regcache
,
6225 tdep
->ppc_gp0_regnum
+
6232 if (ppc_process_record_op63 (gdbarch
, regcache
, addr
, insn
) != 0)
6238 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
6239 "at %s, %d.\n", insn
, paddress (gdbarch
, addr
), op6
);
6243 if (record_full_arch_list_add_reg (regcache
, PPC_PC_REGNUM
))
6245 if (record_full_arch_list_add_end ())
6250 /* Used for matching tw, twi, td and tdi instructions for POWER. */
6252 static constexpr uint32_t TX_INSN_MASK
= 0xFC0007FF;
6253 static constexpr uint32_t TW_INSN
= 0x7C000008;
6254 static constexpr uint32_t TD_INSN
= 0x7C000088;
6256 static constexpr uint32_t TXI_INSN_MASK
= 0xFC000000;
6257 static constexpr uint32_t TWI_INSN
= 0x0C000000;
6258 static constexpr uint32_t TDI_INSN
= 0x08000000;
6261 is_tw_insn (uint32_t insn
)
6263 return (insn
& TX_INSN_MASK
) == TW_INSN
;
6267 is_twi_insn (uint32_t insn
)
6269 return (insn
& TXI_INSN_MASK
) == TWI_INSN
;
6273 is_td_insn (uint32_t insn
)
6275 return (insn
& TX_INSN_MASK
) == TD_INSN
;
6279 is_tdi_insn (uint32_t insn
)
6281 return (insn
& TXI_INSN_MASK
) == TDI_INSN
;
6284 /* Implementation of gdbarch_program_breakpoint_here_p for POWER. */
6287 rs6000_program_breakpoint_here_p (gdbarch
*gdbarch
, CORE_ADDR address
)
6289 gdb_byte target_mem
[PPC_INSN_SIZE
];
6291 /* Enable the automatic memory restoration from breakpoints while
6292 we read the memory. Otherwise we may find temporary breakpoints, ones
6293 inserted by GDB, and flag them as permanent breakpoints. */
6294 scoped_restore restore_memory
6295 = make_scoped_restore_show_memory_breakpoints (0);
6297 if (target_read_memory (address
, target_mem
, PPC_INSN_SIZE
) == 0)
6299 uint32_t insn
= (uint32_t) extract_unsigned_integer
6300 (target_mem
, PPC_INSN_SIZE
, gdbarch_byte_order_for_code (gdbarch
));
6302 /* Check if INSN is a TW, TWI, TD or TDI instruction. There
6303 are multiple choices of such instructions with different registers
6304 and / or immediate values but they all cause a break. */
6305 if (is_tw_insn (insn
) || is_twi_insn (insn
) || is_td_insn (insn
)
6306 || is_tdi_insn (insn
))
6313 /* Initialize the current architecture based on INFO. If possible, re-use an
6314 architecture from ARCHES, which is a list of architectures already created
6315 during this debugging session.
6317 Called e.g. at program startup, when reading a core file, and when reading
6320 static struct gdbarch
*
6321 rs6000_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
6323 struct gdbarch
*gdbarch
;
6324 int wordsize
, from_xcoff_exec
, from_elf_exec
;
6325 enum bfd_architecture arch
;
6328 enum auto_boolean soft_float_flag
= powerpc_soft_float_global
;
6330 enum powerpc_long_double_abi long_double_abi
= POWERPC_LONG_DOUBLE_AUTO
;
6331 enum powerpc_vector_abi vector_abi
= powerpc_vector_abi_global
;
6332 enum powerpc_elf_abi elf_abi
= POWERPC_ELF_AUTO
;
6333 int have_fpu
= 0, have_spe
= 0, have_mq
= 0, have_altivec
= 0;
6334 int have_dfp
= 0, have_vsx
= 0, have_ppr
= 0, have_dscr
= 0;
6335 int have_tar
= 0, have_ebb
= 0, have_pmu
= 0, have_htm_spr
= 0;
6336 int have_htm_core
= 0, have_htm_fpu
= 0, have_htm_altivec
= 0;
6337 int have_htm_vsx
= 0, have_htm_ppr
= 0, have_htm_dscr
= 0;
6338 int have_htm_tar
= 0;
6339 int tdesc_wordsize
= -1;
6340 const struct target_desc
*tdesc
= info
.target_desc
;
6341 tdesc_arch_data_up tdesc_data
;
6342 int num_pseudoregs
= 0;
6345 from_xcoff_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
6346 bfd_get_flavour (info
.abfd
) == bfd_target_xcoff_flavour
;
6348 from_elf_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
6349 bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
;
6351 /* Check word size. If INFO is from a binary file, infer it from
6352 that, else choose a likely default. */
6353 if (from_xcoff_exec
)
6355 if (bfd_xcoff_is_xcoff64 (info
.abfd
))
6360 else if (from_elf_exec
)
6362 if (elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
6367 else if (tdesc_has_registers (tdesc
))
6371 if (info
.bfd_arch_info
!= NULL
&& info
.bfd_arch_info
->bits_per_word
!= 0)
6372 wordsize
= (info
.bfd_arch_info
->bits_per_word
6373 / info
.bfd_arch_info
->bits_per_byte
);
6378 /* Get the architecture and machine from the BFD. */
6379 arch
= info
.bfd_arch_info
->arch
;
6380 mach
= info
.bfd_arch_info
->mach
;
6382 /* For e500 executables, the apuinfo section is of help here. Such
6383 section contains the identifier and revision number of each
6384 Application-specific Processing Unit that is present on the
6385 chip. The content of the section is determined by the assembler
6386 which looks at each instruction and determines which unit (and
6387 which version of it) can execute it. Grovel through the section
6388 looking for relevant e500 APUs. */
6390 if (bfd_uses_spe_extensions (info
.abfd
))
6392 arch
= info
.bfd_arch_info
->arch
;
6393 mach
= bfd_mach_ppc_e500
;
6394 bfd_default_set_arch_mach (&abfd
, arch
, mach
);
6395 info
.bfd_arch_info
= bfd_get_arch_info (&abfd
);
6398 /* Find a default target description which describes our register
6399 layout, if we do not already have one. */
6400 if (! tdesc_has_registers (tdesc
))
6402 const struct ppc_variant
*v
;
6404 /* Choose variant. */
6405 v
= find_variant_by_arch (arch
, mach
);
6412 gdb_assert (tdesc_has_registers (tdesc
));
6414 /* Check any target description for validity. */
6415 if (tdesc_has_registers (tdesc
))
6417 static const char *const gprs
[] = {
6418 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6419 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
6420 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
6421 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
6423 const struct tdesc_feature
*feature
;
6425 static const char *const msr_names
[] = { "msr", "ps" };
6426 static const char *const cr_names
[] = { "cr", "cnd" };
6427 static const char *const ctr_names
[] = { "ctr", "cnt" };
6429 feature
= tdesc_find_feature (tdesc
,
6430 "org.gnu.gdb.power.core");
6431 if (feature
== NULL
)
6434 tdesc_data
= tdesc_data_alloc ();
6437 for (i
= 0; i
< ppc_num_gprs
; i
++)
6438 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6440 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6441 PPC_PC_REGNUM
, "pc");
6442 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6443 PPC_LR_REGNUM
, "lr");
6444 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6445 PPC_XER_REGNUM
, "xer");
6447 /* Allow alternate names for these registers, to accomodate GDB's
6449 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
.get (),
6450 PPC_MSR_REGNUM
, msr_names
);
6451 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
.get (),
6452 PPC_CR_REGNUM
, cr_names
);
6453 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
.get (),
6454 PPC_CTR_REGNUM
, ctr_names
);
6459 have_mq
= tdesc_numbered_register (feature
, tdesc_data
.get (),
6460 PPC_MQ_REGNUM
, "mq");
6462 tdesc_wordsize
= tdesc_register_bitsize (feature
, "pc") / 8;
6464 wordsize
= tdesc_wordsize
;
6466 feature
= tdesc_find_feature (tdesc
,
6467 "org.gnu.gdb.power.fpu");
6468 if (feature
!= NULL
)
6470 static const char *const fprs
[] = {
6471 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
6472 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
6473 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
6474 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
6477 for (i
= 0; i
< ppc_num_fprs
; i
++)
6478 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6479 PPC_F0_REGNUM
+ i
, fprs
[i
]);
6480 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6481 PPC_FPSCR_REGNUM
, "fpscr");
6487 /* The fpscr register was expanded in isa 2.05 to 64 bits
6488 along with the addition of the decimal floating point
6490 if (tdesc_register_bitsize (feature
, "fpscr") > 32)
6496 feature
= tdesc_find_feature (tdesc
,
6497 "org.gnu.gdb.power.altivec");
6498 if (feature
!= NULL
)
6500 static const char *const vector_regs
[] = {
6501 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7",
6502 "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15",
6503 "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23",
6504 "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31"
6508 for (i
= 0; i
< ppc_num_gprs
; i
++)
6509 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6512 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6513 PPC_VSCR_REGNUM
, "vscr");
6514 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6515 PPC_VRSAVE_REGNUM
, "vrsave");
6517 if (have_spe
|| !valid_p
)
6524 /* Check for POWER7 VSX registers support. */
6525 feature
= tdesc_find_feature (tdesc
,
6526 "org.gnu.gdb.power.vsx");
6528 if (feature
!= NULL
)
6530 static const char *const vsx_regs
[] = {
6531 "vs0h", "vs1h", "vs2h", "vs3h", "vs4h", "vs5h",
6532 "vs6h", "vs7h", "vs8h", "vs9h", "vs10h", "vs11h",
6533 "vs12h", "vs13h", "vs14h", "vs15h", "vs16h", "vs17h",
6534 "vs18h", "vs19h", "vs20h", "vs21h", "vs22h", "vs23h",
6535 "vs24h", "vs25h", "vs26h", "vs27h", "vs28h", "vs29h",
6541 for (i
= 0; i
< ppc_num_vshrs
; i
++)
6542 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6543 PPC_VSR0_UPPER_REGNUM
+ i
,
6546 if (!valid_p
|| !have_fpu
|| !have_altivec
)
6554 /* On machines supporting the SPE APU, the general-purpose registers
6555 are 64 bits long. There are SIMD vector instructions to treat them
6556 as pairs of floats, but the rest of the instruction set treats them
6557 as 32-bit registers, and only operates on their lower halves.
6559 In the GDB regcache, we treat their high and low halves as separate
6560 registers. The low halves we present as the general-purpose
6561 registers, and then we have pseudo-registers that stitch together
6562 the upper and lower halves and present them as pseudo-registers.
6564 Thus, the target description is expected to supply the upper
6565 halves separately. */
6567 feature
= tdesc_find_feature (tdesc
,
6568 "org.gnu.gdb.power.spe");
6569 if (feature
!= NULL
)
6571 static const char *const upper_spe
[] = {
6572 "ev0h", "ev1h", "ev2h", "ev3h",
6573 "ev4h", "ev5h", "ev6h", "ev7h",
6574 "ev8h", "ev9h", "ev10h", "ev11h",
6575 "ev12h", "ev13h", "ev14h", "ev15h",
6576 "ev16h", "ev17h", "ev18h", "ev19h",
6577 "ev20h", "ev21h", "ev22h", "ev23h",
6578 "ev24h", "ev25h", "ev26h", "ev27h",
6579 "ev28h", "ev29h", "ev30h", "ev31h"
6583 for (i
= 0; i
< ppc_num_gprs
; i
++)
6584 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6585 PPC_SPE_UPPER_GP0_REGNUM
+ i
,
6587 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6588 PPC_SPE_ACC_REGNUM
, "acc");
6589 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6590 PPC_SPE_FSCR_REGNUM
, "spefscr");
6592 if (have_mq
|| have_fpu
|| !valid_p
)
6599 /* Program Priority Register. */
6600 feature
= tdesc_find_feature (tdesc
,
6601 "org.gnu.gdb.power.ppr");
6602 if (feature
!= NULL
)
6605 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6606 PPC_PPR_REGNUM
, "ppr");
6615 /* Data Stream Control Register. */
6616 feature
= tdesc_find_feature (tdesc
,
6617 "org.gnu.gdb.power.dscr");
6618 if (feature
!= NULL
)
6621 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6622 PPC_DSCR_REGNUM
, "dscr");
6631 /* Target Address Register. */
6632 feature
= tdesc_find_feature (tdesc
,
6633 "org.gnu.gdb.power.tar");
6634 if (feature
!= NULL
)
6637 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6638 PPC_TAR_REGNUM
, "tar");
6647 /* Event-based Branching Registers. */
6648 feature
= tdesc_find_feature (tdesc
,
6649 "org.gnu.gdb.power.ebb");
6650 if (feature
!= NULL
)
6652 static const char *const ebb_regs
[] = {
6653 "bescr", "ebbhr", "ebbrr"
6657 for (i
= 0; i
< ARRAY_SIZE (ebb_regs
); i
++)
6658 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6659 PPC_BESCR_REGNUM
+ i
,
6668 /* Subset of the ISA 2.07 Performance Monitor Registers provided
6670 feature
= tdesc_find_feature (tdesc
,
6671 "org.gnu.gdb.power.linux.pmu");
6672 if (feature
!= NULL
)
6676 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6679 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6682 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6685 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6688 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6699 /* Hardware Transactional Memory Registers. */
6700 feature
= tdesc_find_feature (tdesc
,
6701 "org.gnu.gdb.power.htm.spr");
6702 if (feature
!= NULL
)
6704 static const char *const tm_spr_regs
[] = {
6705 "tfhar", "texasr", "tfiar"
6709 for (i
= 0; i
< ARRAY_SIZE (tm_spr_regs
); i
++)
6710 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6711 PPC_TFHAR_REGNUM
+ i
,
6721 feature
= tdesc_find_feature (tdesc
,
6722 "org.gnu.gdb.power.htm.core");
6723 if (feature
!= NULL
)
6725 static const char *const cgprs
[] = {
6726 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
6727 "cr8", "cr9", "cr10", "cr11", "cr12", "cr13", "cr14",
6728 "cr15", "cr16", "cr17", "cr18", "cr19", "cr20", "cr21",
6729 "cr22", "cr23", "cr24", "cr25", "cr26", "cr27", "cr28",
6730 "cr29", "cr30", "cr31", "ccr", "cxer", "clr", "cctr"
6735 for (i
= 0; i
< ARRAY_SIZE (cgprs
); i
++)
6736 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6747 feature
= tdesc_find_feature (tdesc
,
6748 "org.gnu.gdb.power.htm.fpu");
6749 if (feature
!= NULL
)
6753 static const char *const cfprs
[] = {
6754 "cf0", "cf1", "cf2", "cf3", "cf4", "cf5", "cf6", "cf7",
6755 "cf8", "cf9", "cf10", "cf11", "cf12", "cf13", "cf14", "cf15",
6756 "cf16", "cf17", "cf18", "cf19", "cf20", "cf21", "cf22",
6757 "cf23", "cf24", "cf25", "cf26", "cf27", "cf28", "cf29",
6758 "cf30", "cf31", "cfpscr"
6761 for (i
= 0; i
< ARRAY_SIZE (cfprs
); i
++)
6762 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6773 feature
= tdesc_find_feature (tdesc
,
6774 "org.gnu.gdb.power.htm.altivec");
6775 if (feature
!= NULL
)
6779 static const char *const cvmx
[] = {
6780 "cvr0", "cvr1", "cvr2", "cvr3", "cvr4", "cvr5", "cvr6",
6781 "cvr7", "cvr8", "cvr9", "cvr10", "cvr11", "cvr12", "cvr13",
6782 "cvr14", "cvr15","cvr16", "cvr17", "cvr18", "cvr19", "cvr20",
6783 "cvr21", "cvr22", "cvr23", "cvr24", "cvr25", "cvr26",
6784 "cvr27", "cvr28", "cvr29", "cvr30", "cvr31", "cvscr",
6788 for (i
= 0; i
< ARRAY_SIZE (cvmx
); i
++)
6789 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6790 PPC_CVR0_REGNUM
+ i
,
6795 have_htm_altivec
= 1;
6798 have_htm_altivec
= 0;
6800 feature
= tdesc_find_feature (tdesc
,
6801 "org.gnu.gdb.power.htm.vsx");
6802 if (feature
!= NULL
)
6806 static const char *const cvsx
[] = {
6807 "cvs0h", "cvs1h", "cvs2h", "cvs3h", "cvs4h", "cvs5h",
6808 "cvs6h", "cvs7h", "cvs8h", "cvs9h", "cvs10h", "cvs11h",
6809 "cvs12h", "cvs13h", "cvs14h", "cvs15h", "cvs16h", "cvs17h",
6810 "cvs18h", "cvs19h", "cvs20h", "cvs21h", "cvs22h", "cvs23h",
6811 "cvs24h", "cvs25h", "cvs26h", "cvs27h", "cvs28h", "cvs29h",
6815 for (i
= 0; i
< ARRAY_SIZE (cvsx
); i
++)
6816 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6817 (PPC_CVSR0_UPPER_REGNUM
6821 if (!valid_p
|| !have_htm_fpu
|| !have_htm_altivec
)
6828 feature
= tdesc_find_feature (tdesc
,
6829 "org.gnu.gdb.power.htm.ppr");
6830 if (feature
!= NULL
)
6832 valid_p
= tdesc_numbered_register (feature
, tdesc_data
.get (),
6833 PPC_CPPR_REGNUM
, "cppr");
6842 feature
= tdesc_find_feature (tdesc
,
6843 "org.gnu.gdb.power.htm.dscr");
6844 if (feature
!= NULL
)
6846 valid_p
= tdesc_numbered_register (feature
, tdesc_data
.get (),
6847 PPC_CDSCR_REGNUM
, "cdscr");
6856 feature
= tdesc_find_feature (tdesc
,
6857 "org.gnu.gdb.power.htm.tar");
6858 if (feature
!= NULL
)
6860 valid_p
= tdesc_numbered_register (feature
, tdesc_data
.get (),
6861 PPC_CTAR_REGNUM
, "ctar");
6871 /* If we have a 64-bit binary on a 32-bit target, complain. Also
6872 complain for a 32-bit binary on a 64-bit target; we do not yet
6873 support that. For instance, the 32-bit ABI routines expect
6876 As long as there isn't an explicit target description, we'll
6877 choose one based on the BFD architecture and get a word size
6878 matching the binary (probably powerpc:common or
6879 powerpc:common64). So there is only trouble if a 64-bit target
6880 supplies a 64-bit description while debugging a 32-bit
6882 if (tdesc_wordsize
!= -1 && tdesc_wordsize
!= wordsize
)
6888 switch (elf_elfheader (info
.abfd
)->e_flags
& EF_PPC64_ABI
)
6891 elf_abi
= POWERPC_ELF_V1
;
6894 elf_abi
= POWERPC_ELF_V2
;
6901 if (soft_float_flag
== AUTO_BOOLEAN_AUTO
&& from_elf_exec
)
6903 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
6904 Tag_GNU_Power_ABI_FP
) & 3)
6907 soft_float_flag
= AUTO_BOOLEAN_FALSE
;
6910 soft_float_flag
= AUTO_BOOLEAN_TRUE
;
6917 if (long_double_abi
== POWERPC_LONG_DOUBLE_AUTO
&& from_elf_exec
)
6919 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
6920 Tag_GNU_Power_ABI_FP
) >> 2)
6923 long_double_abi
= POWERPC_LONG_DOUBLE_IBM128
;
6926 long_double_abi
= POWERPC_LONG_DOUBLE_IEEE128
;
6933 if (vector_abi
== POWERPC_VEC_AUTO
&& from_elf_exec
)
6935 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
6936 Tag_GNU_Power_ABI_Vector
))
6939 vector_abi
= POWERPC_VEC_GENERIC
;
6942 vector_abi
= POWERPC_VEC_ALTIVEC
;
6945 vector_abi
= POWERPC_VEC_SPE
;
6953 /* At this point, the only supported ELF-based 64-bit little-endian
6954 operating system is GNU/Linux, and this uses the ELFv2 ABI by
6955 default. All other supported ELF-based operating systems use the
6956 ELFv1 ABI by default. Therefore, if the ABI marker is missing,
6957 e.g. because we run a legacy binary, or have attached to a process
6958 and have not found any associated binary file, set the default
6959 according to this heuristic. */
6960 if (elf_abi
== POWERPC_ELF_AUTO
)
6962 if (wordsize
== 8 && info
.byte_order
== BFD_ENDIAN_LITTLE
)
6963 elf_abi
= POWERPC_ELF_V2
;
6965 elf_abi
= POWERPC_ELF_V1
;
6968 if (soft_float_flag
== AUTO_BOOLEAN_TRUE
)
6970 else if (soft_float_flag
== AUTO_BOOLEAN_FALSE
)
6973 soft_float
= !have_fpu
;
6975 /* If we have a hard float binary or setting but no floating point
6976 registers, downgrade to soft float anyway. We're still somewhat
6977 useful in this scenario. */
6978 if (!soft_float
&& !have_fpu
)
6981 /* Similarly for vector registers. */
6982 if (vector_abi
== POWERPC_VEC_ALTIVEC
&& !have_altivec
)
6983 vector_abi
= POWERPC_VEC_GENERIC
;
6985 if (vector_abi
== POWERPC_VEC_SPE
&& !have_spe
)
6986 vector_abi
= POWERPC_VEC_GENERIC
;
6988 if (vector_abi
== POWERPC_VEC_AUTO
)
6991 vector_abi
= POWERPC_VEC_ALTIVEC
;
6993 vector_abi
= POWERPC_VEC_SPE
;
6995 vector_abi
= POWERPC_VEC_GENERIC
;
6998 /* Do not limit the vector ABI based on available hardware, since we
6999 do not yet know what hardware we'll decide we have. Yuck! FIXME! */
7001 /* Find a candidate among extant architectures. */
7002 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
7004 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
7006 /* Word size in the various PowerPC bfd_arch_info structs isn't
7007 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
7008 separate word size check. */
7009 ppc_gdbarch_tdep
*tdep
7010 = (ppc_gdbarch_tdep
*) gdbarch_tdep (arches
->gdbarch
);
7011 if (tdep
&& tdep
->elf_abi
!= elf_abi
)
7013 if (tdep
&& tdep
->soft_float
!= soft_float
)
7015 if (tdep
&& tdep
->long_double_abi
!= long_double_abi
)
7017 if (tdep
&& tdep
->vector_abi
!= vector_abi
)
7019 if (tdep
&& tdep
->wordsize
== wordsize
)
7020 return arches
->gdbarch
;
7023 /* None found, create a new architecture from INFO, whose bfd_arch_info
7024 validity depends on the source:
7025 - executable useless
7026 - rs6000_host_arch() good
7028 - "set arch" trust blindly
7029 - GDB startup useless but harmless */
7031 ppc_gdbarch_tdep
*tdep
= new ppc_gdbarch_tdep
;
7032 tdep
->wordsize
= wordsize
;
7033 tdep
->elf_abi
= elf_abi
;
7034 tdep
->soft_float
= soft_float
;
7035 tdep
->long_double_abi
= long_double_abi
;
7036 tdep
->vector_abi
= vector_abi
;
7038 gdbarch
= gdbarch_alloc (&info
, tdep
);
7040 tdep
->ppc_gp0_regnum
= PPC_R0_REGNUM
;
7041 tdep
->ppc_toc_regnum
= PPC_R0_REGNUM
+ 2;
7042 tdep
->ppc_ps_regnum
= PPC_MSR_REGNUM
;
7043 tdep
->ppc_cr_regnum
= PPC_CR_REGNUM
;
7044 tdep
->ppc_lr_regnum
= PPC_LR_REGNUM
;
7045 tdep
->ppc_ctr_regnum
= PPC_CTR_REGNUM
;
7046 tdep
->ppc_xer_regnum
= PPC_XER_REGNUM
;
7047 tdep
->ppc_mq_regnum
= have_mq
? PPC_MQ_REGNUM
: -1;
7049 tdep
->ppc_fp0_regnum
= have_fpu
? PPC_F0_REGNUM
: -1;
7050 tdep
->ppc_fpscr_regnum
= have_fpu
? PPC_FPSCR_REGNUM
: -1;
7051 tdep
->ppc_vsr0_upper_regnum
= have_vsx
? PPC_VSR0_UPPER_REGNUM
: -1;
7052 tdep
->ppc_vr0_regnum
= have_altivec
? PPC_VR0_REGNUM
: -1;
7053 tdep
->ppc_vrsave_regnum
= have_altivec
? PPC_VRSAVE_REGNUM
: -1;
7054 tdep
->ppc_ev0_upper_regnum
= have_spe
? PPC_SPE_UPPER_GP0_REGNUM
: -1;
7055 tdep
->ppc_acc_regnum
= have_spe
? PPC_SPE_ACC_REGNUM
: -1;
7056 tdep
->ppc_spefscr_regnum
= have_spe
? PPC_SPE_FSCR_REGNUM
: -1;
7057 tdep
->ppc_ppr_regnum
= have_ppr
? PPC_PPR_REGNUM
: -1;
7058 tdep
->ppc_dscr_regnum
= have_dscr
? PPC_DSCR_REGNUM
: -1;
7059 tdep
->ppc_tar_regnum
= have_tar
? PPC_TAR_REGNUM
: -1;
7060 tdep
->have_ebb
= have_ebb
;
7062 /* If additional pmu registers are added, care must be taken when
7063 setting new fields in the tdep below, to maintain compatibility
7064 with features that only provide some of the registers. Currently
7065 gdb access to the pmu registers is only supported in linux, and
7066 linux only provides a subset of the pmu registers defined in the
7069 tdep
->ppc_mmcr0_regnum
= have_pmu
? PPC_MMCR0_REGNUM
: -1;
7070 tdep
->ppc_mmcr2_regnum
= have_pmu
? PPC_MMCR2_REGNUM
: -1;
7071 tdep
->ppc_siar_regnum
= have_pmu
? PPC_SIAR_REGNUM
: -1;
7072 tdep
->ppc_sdar_regnum
= have_pmu
? PPC_SDAR_REGNUM
: -1;
7073 tdep
->ppc_sier_regnum
= have_pmu
? PPC_SIER_REGNUM
: -1;
7075 tdep
->have_htm_spr
= have_htm_spr
;
7076 tdep
->have_htm_core
= have_htm_core
;
7077 tdep
->have_htm_fpu
= have_htm_fpu
;
7078 tdep
->have_htm_altivec
= have_htm_altivec
;
7079 tdep
->have_htm_vsx
= have_htm_vsx
;
7080 tdep
->ppc_cppr_regnum
= have_htm_ppr
? PPC_CPPR_REGNUM
: -1;
7081 tdep
->ppc_cdscr_regnum
= have_htm_dscr
? PPC_CDSCR_REGNUM
: -1;
7082 tdep
->ppc_ctar_regnum
= have_htm_tar
? PPC_CTAR_REGNUM
: -1;
7084 set_gdbarch_pc_regnum (gdbarch
, PPC_PC_REGNUM
);
7085 set_gdbarch_sp_regnum (gdbarch
, PPC_R0_REGNUM
+ 1);
7086 set_gdbarch_fp0_regnum (gdbarch
, tdep
->ppc_fp0_regnum
);
7087 set_gdbarch_register_sim_regno (gdbarch
, rs6000_register_sim_regno
);
7089 /* The XML specification for PowerPC sensibly calls the MSR "msr".
7090 GDB traditionally called it "ps", though, so let GDB add an
7092 set_gdbarch_ps_regnum (gdbarch
, tdep
->ppc_ps_regnum
);
7095 set_gdbarch_return_value (gdbarch
, ppc64_sysv_abi_return_value
);
7097 set_gdbarch_return_value (gdbarch
, ppc_sysv_abi_return_value
);
7099 /* Set lr_frame_offset. */
7101 tdep
->lr_frame_offset
= 16;
7103 tdep
->lr_frame_offset
= 4;
7105 if (have_spe
|| have_dfp
|| have_altivec
7106 || have_vsx
|| have_htm_fpu
|| have_htm_vsx
)
7108 set_gdbarch_pseudo_register_read (gdbarch
, rs6000_pseudo_register_read
);
7109 set_gdbarch_pseudo_register_write (gdbarch
,
7110 rs6000_pseudo_register_write
);
7111 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
7112 rs6000_ax_pseudo_register_collect
);
7115 set_gdbarch_gen_return_address (gdbarch
, rs6000_gen_return_address
);
7117 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
7119 set_gdbarch_num_regs (gdbarch
, PPC_NUM_REGS
);
7122 num_pseudoregs
+= 32;
7124 num_pseudoregs
+= 16;
7126 num_pseudoregs
+= 32;
7128 /* Include both VSX and Extended FP registers. */
7129 num_pseudoregs
+= 96;
7131 num_pseudoregs
+= 16;
7132 /* Include both checkpointed VSX and EFP registers. */
7134 num_pseudoregs
+= 64 + 32;
7136 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudoregs
);
7138 set_gdbarch_ptr_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
7139 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
7140 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
7141 set_gdbarch_long_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
7142 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
7143 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
7144 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
7145 set_gdbarch_long_double_bit (gdbarch
, 16 * TARGET_CHAR_BIT
);
7146 set_gdbarch_char_signed (gdbarch
, 0);
7148 set_gdbarch_frame_align (gdbarch
, rs6000_frame_align
);
7151 set_gdbarch_frame_red_zone_size (gdbarch
, 288);
7153 set_gdbarch_convert_register_p (gdbarch
, rs6000_convert_register_p
);
7154 set_gdbarch_register_to_value (gdbarch
, rs6000_register_to_value
);
7155 set_gdbarch_value_to_register (gdbarch
, rs6000_value_to_register
);
7157 set_gdbarch_stab_reg_to_regnum (gdbarch
, rs6000_stab_reg_to_regnum
);
7158 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, rs6000_dwarf2_reg_to_regnum
);
7161 set_gdbarch_push_dummy_call (gdbarch
, ppc_sysv_abi_push_dummy_call
);
7162 else if (wordsize
== 8)
7163 set_gdbarch_push_dummy_call (gdbarch
, ppc64_sysv_abi_push_dummy_call
);
7165 set_gdbarch_skip_prologue (gdbarch
, rs6000_skip_prologue
);
7166 set_gdbarch_stack_frame_destroyed_p (gdbarch
, rs6000_stack_frame_destroyed_p
);
7167 set_gdbarch_skip_main_prologue (gdbarch
, rs6000_skip_main_prologue
);
7169 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
7171 set_gdbarch_breakpoint_kind_from_pc (gdbarch
,
7172 rs6000_breakpoint::kind_from_pc
);
7173 set_gdbarch_sw_breakpoint_from_kind (gdbarch
,
7174 rs6000_breakpoint::bp_from_kind
);
7175 set_gdbarch_program_breakpoint_here_p (gdbarch
,
7176 rs6000_program_breakpoint_here_p
);
7178 /* The value of symbols of type N_SO and N_FUN maybe null when
7180 set_gdbarch_sofun_address_maybe_missing (gdbarch
, 1);
7182 /* Handles single stepping of atomic sequences. */
7183 set_gdbarch_software_single_step (gdbarch
, ppc_deal_with_atomic_sequence
);
7185 /* Not sure on this. FIXMEmgo */
7186 set_gdbarch_frame_args_skip (gdbarch
, 8);
7188 /* Helpers for function argument information. */
7189 set_gdbarch_fetch_pointer_argument (gdbarch
, rs6000_fetch_pointer_argument
);
7192 set_gdbarch_in_solib_return_trampoline
7193 (gdbarch
, rs6000_in_solib_return_trampoline
);
7194 set_gdbarch_skip_trampoline_code (gdbarch
, rs6000_skip_trampoline_code
);
7196 /* Hook in the DWARF CFI frame unwinder. */
7197 dwarf2_append_unwinders (gdbarch
);
7198 dwarf2_frame_set_adjust_regnum (gdbarch
, rs6000_adjust_frame_regnum
);
7200 /* Frame handling. */
7201 dwarf2_frame_set_init_reg (gdbarch
, ppc_dwarf2_frame_init_reg
);
7203 /* Setup displaced stepping. */
7204 set_gdbarch_displaced_step_copy_insn (gdbarch
,
7205 ppc_displaced_step_copy_insn
);
7206 set_gdbarch_displaced_step_hw_singlestep (gdbarch
,
7207 ppc_displaced_step_hw_singlestep
);
7208 set_gdbarch_displaced_step_fixup (gdbarch
, ppc_displaced_step_fixup
);
7209 set_gdbarch_displaced_step_prepare (gdbarch
, ppc_displaced_step_prepare
);
7210 set_gdbarch_displaced_step_finish (gdbarch
, ppc_displaced_step_finish
);
7211 set_gdbarch_displaced_step_restore_all_in_ptid
7212 (gdbarch
, ppc_displaced_step_restore_all_in_ptid
);
7214 set_gdbarch_max_insn_length (gdbarch
, 2 * PPC_INSN_SIZE
);
7216 /* Hook in ABI-specific overrides, if they have been registered. */
7217 info
.target_desc
= tdesc
;
7218 info
.tdesc_data
= tdesc_data
.get ();
7219 gdbarch_init_osabi (info
, gdbarch
);
7223 case GDB_OSABI_LINUX
:
7224 case GDB_OSABI_NETBSD
:
7225 case GDB_OSABI_UNKNOWN
:
7226 frame_unwind_append_unwinder (gdbarch
, &rs6000_epilogue_frame_unwind
);
7227 frame_unwind_append_unwinder (gdbarch
, &rs6000_frame_unwind
);
7228 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
7231 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
7233 frame_unwind_append_unwinder (gdbarch
, &rs6000_epilogue_frame_unwind
);
7234 frame_unwind_append_unwinder (gdbarch
, &rs6000_frame_unwind
);
7235 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
7238 set_tdesc_pseudo_register_type (gdbarch
, rs6000_pseudo_register_type
);
7239 set_tdesc_pseudo_register_reggroup_p (gdbarch
,
7240 rs6000_pseudo_register_reggroup_p
);
7241 tdesc_use_registers (gdbarch
, tdesc
, std::move (tdesc_data
));
7243 /* Override the normal target description method to make the SPE upper
7244 halves anonymous. */
7245 set_gdbarch_register_name (gdbarch
, rs6000_register_name
);
7247 /* Choose register numbers for all supported pseudo-registers. */
7248 tdep
->ppc_ev0_regnum
= -1;
7249 tdep
->ppc_dl0_regnum
= -1;
7250 tdep
->ppc_v0_alias_regnum
= -1;
7251 tdep
->ppc_vsr0_regnum
= -1;
7252 tdep
->ppc_efpr0_regnum
= -1;
7253 tdep
->ppc_cdl0_regnum
= -1;
7254 tdep
->ppc_cvsr0_regnum
= -1;
7255 tdep
->ppc_cefpr0_regnum
= -1;
7257 cur_reg
= gdbarch_num_regs (gdbarch
);
7261 tdep
->ppc_ev0_regnum
= cur_reg
;
7266 tdep
->ppc_dl0_regnum
= cur_reg
;
7271 tdep
->ppc_v0_alias_regnum
= cur_reg
;
7276 tdep
->ppc_vsr0_regnum
= cur_reg
;
7278 tdep
->ppc_efpr0_regnum
= cur_reg
;
7283 tdep
->ppc_cdl0_regnum
= cur_reg
;
7288 tdep
->ppc_cvsr0_regnum
= cur_reg
;
7290 tdep
->ppc_cefpr0_regnum
= cur_reg
;
7294 gdb_assert (gdbarch_num_cooked_regs (gdbarch
) == cur_reg
);
7296 /* Register the ravenscar_arch_ops. */
7297 if (mach
== bfd_mach_ppc_e500
)
7298 register_e500_ravenscar_ops (gdbarch
);
7300 register_ppc_ravenscar_ops (gdbarch
);
7302 set_gdbarch_disassembler_options (gdbarch
, &powerpc_disassembler_options
);
7303 set_gdbarch_valid_disassembler_options (gdbarch
,
7304 disassembler_options_powerpc ());
7310 rs6000_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
7312 ppc_gdbarch_tdep
*tdep
= (ppc_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
7317 /* FIXME: Dump gdbarch_tdep. */
7321 powerpc_set_soft_float (const char *args
, int from_tty
,
7322 struct cmd_list_element
*c
)
7324 struct gdbarch_info info
;
7326 /* Update the architecture. */
7327 if (!gdbarch_update_p (info
))
7328 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
7332 powerpc_set_vector_abi (const char *args
, int from_tty
,
7333 struct cmd_list_element
*c
)
7337 for (vector_abi
= POWERPC_VEC_AUTO
;
7338 vector_abi
!= POWERPC_VEC_LAST
;
7340 if (strcmp (powerpc_vector_abi_string
,
7341 powerpc_vector_strings
[vector_abi
]) == 0)
7343 powerpc_vector_abi_global
= (enum powerpc_vector_abi
) vector_abi
;
7347 if (vector_abi
== POWERPC_VEC_LAST
)
7348 internal_error (__FILE__
, __LINE__
, _("Invalid vector ABI accepted: %s."),
7349 powerpc_vector_abi_string
);
7351 /* Update the architecture. */
7353 if (!gdbarch_update_p (info
))
7354 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
7357 /* Show the current setting of the exact watchpoints flag. */
7360 show_powerpc_exact_watchpoints (struct ui_file
*file
, int from_tty
,
7361 struct cmd_list_element
*c
,
7364 fprintf_filtered (file
, _("Use of exact watchpoints is %s.\n"), value
);
7367 /* Read a PPC instruction from memory. */
7370 read_insn (struct frame_info
*frame
, CORE_ADDR pc
)
7372 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7373 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7375 return read_memory_unsigned_integer (pc
, 4, byte_order
);
7378 /* Return non-zero if the instructions at PC match the series
7379 described in PATTERN, or zero otherwise. PATTERN is an array of
7380 'struct ppc_insn_pattern' objects, terminated by an entry whose
7383 When the match is successful, fill INSNS[i] with what PATTERN[i]
7384 matched. If PATTERN[i] is optional, and the instruction wasn't
7385 present, set INSNS[i] to 0 (which is not a valid PPC instruction).
7386 INSNS should have as many elements as PATTERN, minus the terminator.
7387 Note that, if PATTERN contains optional instructions which aren't
7388 present in memory, then INSNS will have holes, so INSNS[i] isn't
7389 necessarily the i'th instruction in memory. */
7392 ppc_insns_match_pattern (struct frame_info
*frame
, CORE_ADDR pc
,
7393 const struct ppc_insn_pattern
*pattern
,
7394 unsigned int *insns
)
7399 for (i
= 0, insn
= 0; pattern
[i
].mask
; i
++)
7402 insn
= read_insn (frame
, pc
);
7404 if ((insn
& pattern
[i
].mask
) == pattern
[i
].data
)
7410 else if (!pattern
[i
].optional
)
7417 /* Return the 'd' field of the d-form instruction INSN, properly
7421 ppc_insn_d_field (unsigned int insn
)
7423 return ((((CORE_ADDR
) insn
& 0xffff) ^ 0x8000) - 0x8000);
7426 /* Return the 'ds' field of the ds-form instruction INSN, with the two
7427 zero bits concatenated at the right, and properly
7431 ppc_insn_ds_field (unsigned int insn
)
7433 return ((((CORE_ADDR
) insn
& 0xfffc) ^ 0x8000) - 0x8000);
7437 ppc_insn_prefix_dform (unsigned int insn1
, unsigned int insn2
)
7439 /* result is 34-bits */
7440 return (CORE_ADDR
) ((((insn1
& 0x3ffff) ^ 0x20000) - 0x20000) << 16)
7441 | (CORE_ADDR
)(insn2
& 0xffff);
7444 /* Initialization code. */
7446 void _initialize_rs6000_tdep ();
7448 _initialize_rs6000_tdep ()
7450 gdbarch_register (bfd_arch_rs6000
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
7451 gdbarch_register (bfd_arch_powerpc
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
7453 /* Initialize the standard target descriptions. */
7454 initialize_tdesc_powerpc_32 ();
7455 initialize_tdesc_powerpc_altivec32 ();
7456 initialize_tdesc_powerpc_vsx32 ();
7457 initialize_tdesc_powerpc_403 ();
7458 initialize_tdesc_powerpc_403gc ();
7459 initialize_tdesc_powerpc_405 ();
7460 initialize_tdesc_powerpc_505 ();
7461 initialize_tdesc_powerpc_601 ();
7462 initialize_tdesc_powerpc_602 ();
7463 initialize_tdesc_powerpc_603 ();
7464 initialize_tdesc_powerpc_604 ();
7465 initialize_tdesc_powerpc_64 ();
7466 initialize_tdesc_powerpc_altivec64 ();
7467 initialize_tdesc_powerpc_vsx64 ();
7468 initialize_tdesc_powerpc_7400 ();
7469 initialize_tdesc_powerpc_750 ();
7470 initialize_tdesc_powerpc_860 ();
7471 initialize_tdesc_powerpc_e500 ();
7472 initialize_tdesc_rs6000 ();
7474 /* Add root prefix command for all "set powerpc"/"show powerpc"
7476 add_setshow_prefix_cmd ("powerpc", no_class
,
7477 _("Various PowerPC-specific commands."),
7478 _("Various PowerPC-specific commands."),
7479 &setpowerpccmdlist
, &showpowerpccmdlist
,
7480 &setlist
, &showlist
);
7482 /* Add a command to allow the user to force the ABI. */
7483 add_setshow_auto_boolean_cmd ("soft-float", class_support
,
7484 &powerpc_soft_float_global
,
7485 _("Set whether to use a soft-float ABI."),
7486 _("Show whether to use a soft-float ABI."),
7488 powerpc_set_soft_float
, NULL
,
7489 &setpowerpccmdlist
, &showpowerpccmdlist
);
7491 add_setshow_enum_cmd ("vector-abi", class_support
, powerpc_vector_strings
,
7492 &powerpc_vector_abi_string
,
7493 _("Set the vector ABI."),
7494 _("Show the vector ABI."),
7495 NULL
, powerpc_set_vector_abi
, NULL
,
7496 &setpowerpccmdlist
, &showpowerpccmdlist
);
7498 add_setshow_boolean_cmd ("exact-watchpoints", class_support
,
7499 &target_exact_watchpoints
,
7501 Set whether to use just one debug register for watchpoints on scalars."),
7503 Show whether to use just one debug register for watchpoints on scalars."),
7505 If true, GDB will use only one debug register when watching a variable of\n\
7506 scalar type, thus assuming that the variable is accessed through the address\n\
7507 of its first byte."),
7508 NULL
, show_powerpc_exact_watchpoints
,
7509 &setpowerpccmdlist
, &showpowerpccmdlist
);