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2003-08-01 Michael Snyder <msnyder@redhat.com>
[binutils-gdb.git] / gdb / sh-tdep.c
1 /* Target-dependent code for Hitachi Super-H, for GDB.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
21
22 /*
23 Contributed by Steve Chamberlain
24 sac@cygnus.com
25 */
26
27 #include "defs.h"
28 #include "frame.h"
29 #include "symtab.h"
30 #include "symfile.h"
31 #include "gdbtypes.h"
32 #include "gdbcmd.h"
33 #include "gdbcore.h"
34 #include "value.h"
35 #include "dis-asm.h"
36 #include "inferior.h"
37 #include "gdb_string.h"
38 #include "arch-utils.h"
39 #include "floatformat.h"
40 #include "regcache.h"
41 #include "doublest.h"
42 #include "osabi.h"
43
44 #include "sh-tdep.h"
45
46 #include "elf-bfd.h"
47 #include "solib-svr4.h"
48
49 /* sh64 flags */
50 #include "elf/sh.h"
51 /* registers numbers shared with the simulator */
52 #include "gdb/sim-sh.h"
53
54 void (*sh_show_regs) (void);
55 CORE_ADDR (*skip_prologue_hard_way) (CORE_ADDR);
56
57 #define SH_DEFAULT_NUM_REGS 59
58
59 /* Define other aspects of the stack frame.
60 we keep a copy of the worked out return pc lying around, since it
61 is a useful bit of info */
62
63 struct frame_extra_info
64 {
65 CORE_ADDR return_pc;
66 int leaf_function;
67 int f_offset;
68 };
69
70 static const char *
71 sh_generic_register_name (int reg_nr)
72 {
73 static char *register_names[] =
74 {
75 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
76 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
77 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
78 "fpul", "fpscr",
79 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
80 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
81 "ssr", "spc",
82 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
83 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
84 };
85 if (reg_nr < 0)
86 return NULL;
87 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
88 return NULL;
89 return register_names[reg_nr];
90 }
91
92 static const char *
93 sh_sh_register_name (int reg_nr)
94 {
95 static char *register_names[] =
96 {
97 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
98 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
99 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
100 "", "",
101 "", "", "", "", "", "", "", "",
102 "", "", "", "", "", "", "", "",
103 "", "",
104 "", "", "", "", "", "", "", "",
105 "", "", "", "", "", "", "", "",
106 };
107 if (reg_nr < 0)
108 return NULL;
109 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
110 return NULL;
111 return register_names[reg_nr];
112 }
113
114 static const char *
115 sh_sh3_register_name (int reg_nr)
116 {
117 static char *register_names[] =
118 {
119 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
120 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
121 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
122 "", "",
123 "", "", "", "", "", "", "", "",
124 "", "", "", "", "", "", "", "",
125 "ssr", "spc",
126 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
127 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
128 };
129 if (reg_nr < 0)
130 return NULL;
131 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
132 return NULL;
133 return register_names[reg_nr];
134 }
135
136 static const char *
137 sh_sh3e_register_name (int reg_nr)
138 {
139 static char *register_names[] =
140 {
141 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
142 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
143 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
144 "fpul", "fpscr",
145 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
146 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
147 "ssr", "spc",
148 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
149 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
150 };
151 if (reg_nr < 0)
152 return NULL;
153 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
154 return NULL;
155 return register_names[reg_nr];
156 }
157
158 static const char *
159 sh_sh2e_register_name (int reg_nr)
160 {
161 static char *register_names[] =
162 {
163 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
164 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
165 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
166 "fpul", "fpscr",
167 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
168 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
169 "", "",
170 "", "", "", "", "", "", "", "",
171 "", "", "", "", "", "", "", "",
172 };
173 if (reg_nr < 0)
174 return NULL;
175 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
176 return NULL;
177 return register_names[reg_nr];
178 }
179
180 static const char *
181 sh_sh_dsp_register_name (int reg_nr)
182 {
183 static char *register_names[] =
184 {
185 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
186 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
187 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
188 "", "dsr",
189 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
190 "y0", "y1", "", "", "", "", "", "mod",
191 "", "",
192 "rs", "re", "", "", "", "", "", "",
193 "", "", "", "", "", "", "", "",
194 };
195 if (reg_nr < 0)
196 return NULL;
197 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
198 return NULL;
199 return register_names[reg_nr];
200 }
201
202 static const char *
203 sh_sh3_dsp_register_name (int reg_nr)
204 {
205 static char *register_names[] =
206 {
207 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
208 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
209 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
210 "", "dsr",
211 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
212 "y0", "y1", "", "", "", "", "", "mod",
213 "ssr", "spc",
214 "rs", "re", "", "", "", "", "", "",
215 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b"
216 "", "", "", "", "", "", "", "",
217 };
218 if (reg_nr < 0)
219 return NULL;
220 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
221 return NULL;
222 return register_names[reg_nr];
223 }
224
225 static const char *
226 sh_sh4_register_name (int reg_nr)
227 {
228 static char *register_names[] =
229 {
230 /* general registers 0-15 */
231 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
232 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
233 /* 16 - 22 */
234 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
235 /* 23, 24 */
236 "fpul", "fpscr",
237 /* floating point registers 25 - 40 */
238 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
239 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
240 /* 41, 42 */
241 "ssr", "spc",
242 /* bank 0 43 - 50 */
243 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
244 /* bank 1 51 - 58 */
245 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
246 /* double precision (pseudo) 59 - 66 */
247 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
248 /* vectors (pseudo) 67 - 70 */
249 "fv0", "fv4", "fv8", "fv12",
250 /* FIXME: missing XF 71 - 86 */
251 /* FIXME: missing XD 87 - 94 */
252 };
253 if (reg_nr < 0)
254 return NULL;
255 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
256 return NULL;
257 return register_names[reg_nr];
258 }
259
260 static const char *
261 sh_sh64_register_name (int reg_nr)
262 {
263 static char *register_names[] =
264 {
265 /* SH MEDIA MODE (ISA 32) */
266 /* general registers (64-bit) 0-63 */
267 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
268 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
269 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
270 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
271 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
272 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
273 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
274 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
275
276 /* pc (64-bit) 64 */
277 "pc",
278
279 /* status reg., saved status reg., saved pc reg. (64-bit) 65-67 */
280 "sr", "ssr", "spc",
281
282 /* target registers (64-bit) 68-75*/
283 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7",
284
285 /* floating point state control register (32-bit) 76 */
286 "fpscr",
287
288 /* single precision floating point registers (32-bit) 77-140*/
289 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
290 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
291 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23",
292 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31",
293 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39",
294 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47",
295 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55",
296 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63",
297
298 /* double precision registers (pseudo) 141-172 */
299 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
300 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30",
301 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46",
302 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62",
303
304 /* floating point pairs (pseudo) 173-204*/
305 "fp0", "fp2", "fp4", "fp6", "fp8", "fp10", "fp12", "fp14",
306 "fp16", "fp18", "fp20", "fp22", "fp24", "fp26", "fp28", "fp30",
307 "fp32", "fp34", "fp36", "fp38", "fp40", "fp42", "fp44", "fp46",
308 "fp48", "fp50", "fp52", "fp54", "fp56", "fp58", "fp60", "fp62",
309
310 /* floating point vectors (4 floating point regs) (pseudo) 205-220*/
311 "fv0", "fv4", "fv8", "fv12", "fv16", "fv20", "fv24", "fv28",
312 "fv32", "fv36", "fv40", "fv44", "fv48", "fv52", "fv56", "fv60",
313
314 /* SH COMPACT MODE (ISA 16) (all pseudo) 221-272*/
315 "r0_c", "r1_c", "r2_c", "r3_c", "r4_c", "r5_c", "r6_c", "r7_c",
316 "r8_c", "r9_c", "r10_c", "r11_c", "r12_c", "r13_c", "r14_c", "r15_c",
317 "pc_c",
318 "gbr_c", "mach_c", "macl_c", "pr_c", "t_c",
319 "fpscr_c", "fpul_c",
320 "fr0_c", "fr1_c", "fr2_c", "fr3_c", "fr4_c", "fr5_c", "fr6_c", "fr7_c",
321 "fr8_c", "fr9_c", "fr10_c", "fr11_c", "fr12_c", "fr13_c", "fr14_c", "fr15_c",
322 "dr0_c", "dr2_c", "dr4_c", "dr6_c", "dr8_c", "dr10_c", "dr12_c", "dr14_c",
323 "fv0_c", "fv4_c", "fv8_c", "fv12_c",
324 /* FIXME!!!! XF0 XF15, XD0 XD14 ?????*/
325 };
326
327 if (reg_nr < 0)
328 return NULL;
329 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
330 return NULL;
331 return register_names[reg_nr];
332 }
333
334 #define NUM_PSEUDO_REGS_SH_MEDIA 80
335 #define NUM_PSEUDO_REGS_SH_COMPACT 51
336
337 static const unsigned char *
338 sh_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
339 {
340 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */
341 static unsigned char breakpoint[] = {0xc3, 0xc3};
342
343 *lenptr = sizeof (breakpoint);
344 return breakpoint;
345 }
346
347 static CORE_ADDR
348 sh_push_dummy_code (struct gdbarch *gdbarch,
349 CORE_ADDR sp, CORE_ADDR funaddr, int using_gcc,
350 struct value **args, int nargs,
351 struct type *value_type,
352 CORE_ADDR *real_pc, CORE_ADDR *bp_addr)
353 {
354 /* Allocate space sufficient for a breakpoint. */
355 sp = (sp - 2) & ~1;
356 /* Store the address of that breakpoint */
357 *bp_addr = sp;
358 /* sh always starts the call at the callee's entry point. */
359 *real_pc = funaddr;
360 return sp;
361 }
362
363 /* Macros and functions for setting and testing a bit in a minimal
364 symbol that marks it as 32-bit function. The MSB of the minimal
365 symbol's "info" field is used for this purpose. This field is
366 already being used to store the symbol size, so the assumption is
367 that the symbol size cannot exceed 2^31.
368
369 ELF_MAKE_MSYMBOL_SPECIAL
370 tests whether an ELF symbol is "special", i.e. refers
371 to a 32-bit function, and sets a "special" bit in a
372 minimal symbol to mark it as a 32-bit function
373 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol
374 MSYMBOL_SIZE returns the size of the minimal symbol, i.e.
375 the "info" field with the "special" bit masked out */
376
377 #define MSYMBOL_IS_SPECIAL(msym) \
378 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
379
380 static void
381 sh64_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym)
382 {
383 if (msym == NULL)
384 return;
385
386 if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_SH5_ISA32)
387 {
388 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) | 0x80000000);
389 SYMBOL_VALUE_ADDRESS (msym) |= 1;
390 }
391 }
392
393 /* ISA32 (shmedia) function addresses are odd (bit 0 is set). Here
394 are some macros to test, set, or clear bit 0 of addresses. */
395 #define IS_ISA32_ADDR(addr) ((addr) & 1)
396 #define MAKE_ISA32_ADDR(addr) ((addr) | 1)
397 #define UNMAKE_ISA32_ADDR(addr) ((addr) & ~1)
398
399 static int
400 pc_is_isa32 (bfd_vma memaddr)
401 {
402 struct minimal_symbol *sym;
403
404 /* If bit 0 of the address is set, assume this is a
405 ISA32 (shmedia) address. */
406 if (IS_ISA32_ADDR (memaddr))
407 return 1;
408
409 /* A flag indicating that this is a ISA32 function is stored by elfread.c in
410 the high bit of the info field. Use this to decide if the function is
411 ISA16 or ISA32. */
412 sym = lookup_minimal_symbol_by_pc (memaddr);
413 if (sym)
414 return MSYMBOL_IS_SPECIAL (sym);
415 else
416 return 0;
417 }
418
419 static const unsigned char *
420 sh_sh64_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
421 {
422 /* The BRK instruction for shmedia is
423 01101111 11110101 11111111 11110000
424 which translates in big endian mode to 0x6f, 0xf5, 0xff, 0xf0
425 and in little endian mode to 0xf0, 0xff, 0xf5, 0x6f */
426
427 /* The BRK instruction for shcompact is
428 00000000 00111011
429 which translates in big endian mode to 0x0, 0x3b
430 and in little endian mode to 0x3b, 0x0*/
431
432 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
433 {
434 if (pc_is_isa32 (*pcptr))
435 {
436 static unsigned char big_breakpoint_media[] = {0x6f, 0xf5, 0xff, 0xf0};
437 *pcptr = UNMAKE_ISA32_ADDR (*pcptr);
438 *lenptr = sizeof (big_breakpoint_media);
439 return big_breakpoint_media;
440 }
441 else
442 {
443 static unsigned char big_breakpoint_compact[] = {0x0, 0x3b};
444 *lenptr = sizeof (big_breakpoint_compact);
445 return big_breakpoint_compact;
446 }
447 }
448 else
449 {
450 if (pc_is_isa32 (*pcptr))
451 {
452 static unsigned char little_breakpoint_media[] = {0xf0, 0xff, 0xf5, 0x6f};
453 *pcptr = UNMAKE_ISA32_ADDR (*pcptr);
454 *lenptr = sizeof (little_breakpoint_media);
455 return little_breakpoint_media;
456 }
457 else
458 {
459 static unsigned char little_breakpoint_compact[] = {0x3b, 0x0};
460 *lenptr = sizeof (little_breakpoint_compact);
461 return little_breakpoint_compact;
462 }
463 }
464 }
465
466 /* Prologue looks like
467 [mov.l <regs>,@-r15]...
468 [sts.l pr,@-r15]
469 [mov.l r14,@-r15]
470 [mov r15,r14]
471
472 Actually it can be more complicated than this. For instance, with
473 newer gcc's:
474
475 mov.l r14,@-r15
476 add #-12,r15
477 mov r15,r14
478 mov r4,r1
479 mov r5,r2
480 mov.l r6,@(4,r14)
481 mov.l r7,@(8,r14)
482 mov.b r1,@r14
483 mov r14,r1
484 mov r14,r1
485 add #2,r1
486 mov.w r2,@r1
487
488 */
489
490 /* PTABS/L Rn, TRa 0110101111110001nnnnnnl00aaa0000
491 with l=1 and n = 18 0110101111110001010010100aaa0000 */
492 #define IS_PTABSL_R18(x) (((x) & 0xffffff8f) == 0x6bf14a00)
493
494 /* STS.L PR,@-r0 0100000000100010
495 r0-4-->r0, PR-->(r0) */
496 #define IS_STS_R0(x) ((x) == 0x4022)
497
498 /* STS PR, Rm 0000mmmm00101010
499 PR-->Rm */
500 #define IS_STS_PR(x) (((x) & 0xf0ff) == 0x2a)
501
502 /* MOV.L Rm,@(disp,r15) 00011111mmmmdddd
503 Rm-->(dispx4+r15) */
504 #define IS_MOV_TO_R15(x) (((x) & 0xff00) == 0x1f00)
505
506 /* MOV.L R14,@(disp,r15) 000111111110dddd
507 R14-->(dispx4+r15) */
508 #define IS_MOV_R14(x) (((x) & 0xfff0) == 0x1fe0)
509
510 /* ST.Q R14, disp, R18 101011001110dddddddddd0100100000
511 R18-->(dispx8+R14) */
512 #define IS_STQ_R18_R14(x) (((x) & 0xfff003ff) == 0xace00120)
513
514 /* ST.Q R15, disp, R18 101011001111dddddddddd0100100000
515 R18-->(dispx8+R15) */
516 #define IS_STQ_R18_R15(x) (((x) & 0xfff003ff) == 0xacf00120)
517
518 /* ST.L R15, disp, R18 101010001111dddddddddd0100100000
519 R18-->(dispx4+R15) */
520 #define IS_STL_R18_R15(x) (((x) & 0xfff003ff) == 0xa8f00120)
521
522 /* ST.Q R15, disp, R14 1010 1100 1111 dddd dddd dd00 1110 0000
523 R14-->(dispx8+R15) */
524 #define IS_STQ_R14_R15(x) (((x) & 0xfff003ff) == 0xacf000e0)
525
526 /* ST.L R15, disp, R14 1010 1000 1111 dddd dddd dd00 1110 0000
527 R14-->(dispx4+R15) */
528 #define IS_STL_R14_R15(x) (((x) & 0xfff003ff) == 0xa8f000e0)
529
530 /* ADDI.L R15,imm,R15 1101 0100 1111 ssss ssss ss00 1111 0000
531 R15 + imm --> R15 */
532 #define IS_ADDIL_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd4f000f0)
533
534 /* ADDI R15,imm,R15 1101 0000 1111 ssss ssss ss00 1111 0000
535 R15 + imm --> R15 */
536 #define IS_ADDI_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd0f000f0)
537
538 /* ADD.L R15,R63,R14 0000 0000 1111 1000 1111 1100 1110 0000
539 R15 + R63 --> R14 */
540 #define IS_ADDL_SP_FP_MEDIA(x) ((x) == 0x00f8fce0)
541
542 /* ADD R15,R63,R14 0000 0000 1111 1001 1111 1100 1110 0000
543 R15 + R63 --> R14 */
544 #define IS_ADD_SP_FP_MEDIA(x) ((x) == 0x00f9fce0)
545
546 #define IS_MOV_SP_FP_MEDIA(x) (IS_ADDL_SP_FP_MEDIA(x) || IS_ADD_SP_FP_MEDIA(x))
547
548 /* MOV #imm, R0 1110 0000 ssss ssss
549 #imm-->R0 */
550 #define IS_MOV_R0(x) (((x) & 0xff00) == 0xe000)
551
552 /* MOV.L @(disp,PC), R0 1101 0000 iiii iiii */
553 #define IS_MOVL_R0(x) (((x) & 0xff00) == 0xd000)
554
555 /* ADD r15,r0 0011 0000 1111 1100
556 r15+r0-->r0 */
557 #define IS_ADD_SP_R0(x) ((x) == 0x30fc)
558
559 /* MOV.L R14 @-R0 0010 0000 1110 0110
560 R14-->(R0-4), R0-4-->R0 */
561 #define IS_MOV_R14_R0(x) ((x) == 0x20e6)
562
563 /* ADD Rm,R63,Rn Rm+R63-->Rn 0000 00mm mmmm 1001 1111 11nn nnnn 0000
564 where Rm is one of r2-r9 which are the argument registers. */
565 /* FIXME: Recognize the float and double register moves too! */
566 #define IS_MEDIA_IND_ARG_MOV(x) \
567 ((((x) & 0xfc0ffc0f) == 0x0009fc00) && (((x) & 0x03f00000) >= 0x00200000 && ((x) & 0x03f00000) <= 0x00900000))
568
569 /* ST.Q Rn,0,Rm Rm-->Rn+0 1010 11nn nnnn 0000 0000 00mm mmmm 0000
570 or ST.L Rn,0,Rm Rm-->Rn+0 1010 10nn nnnn 0000 0000 00mm mmmm 0000
571 where Rm is one of r2-r9 which are the argument registers. */
572 #define IS_MEDIA_ARG_MOV(x) \
573 (((((x) & 0xfc0ffc0f) == 0xac000000) || (((x) & 0xfc0ffc0f) == 0xa8000000)) \
574 && (((x) & 0x000003f0) >= 0x00000020 && ((x) & 0x000003f0) <= 0x00000090))
575
576 /* ST.B R14,0,Rn Rn-->(R14+0) 1010 0000 1110 0000 0000 00nn nnnn 0000*/
577 /* ST.W R14,0,Rn Rn-->(R14+0) 1010 0100 1110 0000 0000 00nn nnnn 0000*/
578 /* ST.L R14,0,Rn Rn-->(R14+0) 1010 1000 1110 0000 0000 00nn nnnn 0000*/
579 /* FST.S R14,0,FRn Rn-->(R14+0) 1011 0100 1110 0000 0000 00nn nnnn 0000*/
580 /* FST.D R14,0,DRn Rn-->(R14+0) 1011 1100 1110 0000 0000 00nn nnnn 0000*/
581 #define IS_MEDIA_MOV_TO_R14(x) \
582 ((((x) & 0xfffffc0f) == 0xa0e00000) \
583 || (((x) & 0xfffffc0f) == 0xa4e00000) \
584 || (((x) & 0xfffffc0f) == 0xa8e00000) \
585 || (((x) & 0xfffffc0f) == 0xb4e00000) \
586 || (((x) & 0xfffffc0f) == 0xbce00000))
587
588 /* MOV Rm, Rn Rm-->Rn 0110 nnnn mmmm 0011
589 where Rm is r2-r9 */
590 #define IS_COMPACT_IND_ARG_MOV(x) \
591 ((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0020) && (((x) & 0x00f0) <= 0x0090))
592
593 /* compact direct arg move!
594 MOV.L Rn, @r14 0010 1110 mmmm 0010 */
595 #define IS_COMPACT_ARG_MOV(x) \
596 (((((x) & 0xff0f) == 0x2e02) && (((x) & 0x00f0) >= 0x0020) && ((x) & 0x00f0) <= 0x0090))
597
598 /* MOV.B Rm, @R14 0010 1110 mmmm 0000
599 MOV.W Rm, @R14 0010 1110 mmmm 0001 */
600 #define IS_COMPACT_MOV_TO_R14(x) \
601 ((((x) & 0xff0f) == 0x2e00) || (((x) & 0xff0f) == 0x2e01))
602
603 #define IS_JSR_R0(x) ((x) == 0x400b)
604 #define IS_NOP(x) ((x) == 0x0009)
605
606
607 /* STS.L PR,@-r15 0100111100100010
608 r15-4-->r15, PR-->(r15) */
609 #define IS_STS(x) ((x) == 0x4f22)
610
611 /* MOV.L Rm,@-r15 00101111mmmm0110
612 r15-4-->r15, Rm-->(R15) */
613 #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
614
615 #define GET_PUSHED_REG(x) (((x) >> 4) & 0xf)
616
617 /* MOV r15,r14 0110111011110011
618 r15-->r14 */
619 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
620
621 /* ADD #imm,r15 01111111iiiiiiii
622 r15+imm-->r15 */
623 #define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00)
624
625 #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
626 #define IS_SHLL_R3(x) ((x) == 0x4300)
627
628 /* ADD r3,r15 0011111100111100
629 r15+r3-->r15 */
630 #define IS_ADD_R3SP(x) ((x) == 0x3f3c)
631
632 /* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
633 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
634 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
635 #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b)
636
637 /* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011
638 MOV.L Rm,@(disp,Rn) Rm-->(dispx4+Rn) 0001nnnnmmmmdddd
639 MOV.L Rm,@Rn Rm-->(Rn) 0010nnnnmmmm0010
640 where Rm is one of r4,r5,r6,r7 which are the argument registers. */
641 #define IS_ARG_MOV(x) \
642 (((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) \
643 || ((((x) & 0xf000) == 0x1000) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) \
644 || ((((x) & 0xf00f) == 0x2002) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)))
645
646 /* MOV.L Rm,@(disp,r14) 00011110mmmmdddd
647 Rm-->(dispx4+r14) where Rm is one of r4,r5,r6,r7 */
648 #define IS_MOV_TO_R14(x) \
649 ((((x) & 0xff00) == 0x1e) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070))
650
651 #define FPSCR_SZ (1 << 20)
652
653 /* Skip any prologue before the guts of a function */
654
655 /* Skip the prologue using the debug information. If this fails we'll
656 fall back on the 'guess' method below. */
657 static CORE_ADDR
658 after_prologue (CORE_ADDR pc)
659 {
660 struct symtab_and_line sal;
661 CORE_ADDR func_addr, func_end;
662
663 /* If we can not find the symbol in the partial symbol table, then
664 there is no hope we can determine the function's start address
665 with this code. */
666 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
667 return 0;
668
669 /* Get the line associated with FUNC_ADDR. */
670 sal = find_pc_line (func_addr, 0);
671
672 /* There are only two cases to consider. First, the end of the source line
673 is within the function bounds. In that case we return the end of the
674 source line. Second is the end of the source line extends beyond the
675 bounds of the current function. We need to use the slow code to
676 examine instructions in that case. */
677 if (sal.end < func_end)
678 return sal.end;
679 else
680 return 0;
681 }
682
683 /* Here we look at each instruction in the function, and try to guess
684 where the prologue ends. Unfortunately this is not always
685 accurate. */
686 static CORE_ADDR
687 sh_skip_prologue_hard_way (CORE_ADDR start_pc)
688 {
689 CORE_ADDR here, end;
690 int updated_fp = 0;
691
692 if (!start_pc)
693 return 0;
694
695 for (here = start_pc, end = start_pc + (2 * 28); here < end;)
696 {
697 int w = read_memory_integer (here, 2);
698 here += 2;
699 if (IS_FMOV (w) || IS_PUSH (w) || IS_STS (w) || IS_MOV_R3 (w)
700 || IS_ADD_R3SP (w) || IS_ADD_SP (w) || IS_SHLL_R3 (w)
701 || IS_ARG_MOV (w) || IS_MOV_TO_R14 (w))
702 {
703 start_pc = here;
704 }
705 else if (IS_MOV_SP_FP (w))
706 {
707 start_pc = here;
708 updated_fp = 1;
709 }
710 else
711 /* Don't bail out yet, if we are before the copy of sp. */
712 if (updated_fp)
713 break;
714 }
715
716 return start_pc;
717 }
718
719 static CORE_ADDR
720 look_for_args_moves (CORE_ADDR start_pc, int media_mode)
721 {
722 CORE_ADDR here, end;
723 int w;
724 int insn_size = (media_mode ? 4 : 2);
725
726 for (here = start_pc, end = start_pc + (insn_size * 28); here < end;)
727 {
728 if (media_mode)
729 {
730 w = read_memory_integer (UNMAKE_ISA32_ADDR (here), insn_size);
731 here += insn_size;
732 if (IS_MEDIA_IND_ARG_MOV (w))
733 {
734 /* This must be followed by a store to r14, so the argument
735 is where the debug info says it is. This can happen after
736 the SP has been saved, unfortunately. */
737
738 int next_insn = read_memory_integer (UNMAKE_ISA32_ADDR (here),
739 insn_size);
740 here += insn_size;
741 if (IS_MEDIA_MOV_TO_R14 (next_insn))
742 start_pc = here;
743 }
744 else if (IS_MEDIA_ARG_MOV (w))
745 {
746 /* These instructions store directly the argument in r14. */
747 start_pc = here;
748 }
749 else
750 break;
751 }
752 else
753 {
754 w = read_memory_integer (here, insn_size);
755 w = w & 0xffff;
756 here += insn_size;
757 if (IS_COMPACT_IND_ARG_MOV (w))
758 {
759 /* This must be followed by a store to r14, so the argument
760 is where the debug info says it is. This can happen after
761 the SP has been saved, unfortunately. */
762
763 int next_insn = 0xffff & read_memory_integer (here, insn_size);
764 here += insn_size;
765 if (IS_COMPACT_MOV_TO_R14 (next_insn))
766 start_pc = here;
767 }
768 else if (IS_COMPACT_ARG_MOV (w))
769 {
770 /* These instructions store directly the argument in r14. */
771 start_pc = here;
772 }
773 else if (IS_MOVL_R0 (w))
774 {
775 /* There is a function that gcc calls to get the arguments
776 passed correctly to the function. Only after this
777 function call the arguments will be found at the place
778 where they are supposed to be. This happens in case the
779 argument has to be stored into a 64-bit register (for
780 instance doubles, long longs). SHcompact doesn't have
781 access to the full 64-bits, so we store the register in
782 stack slot and store the address of the stack slot in
783 the register, then do a call through a wrapper that
784 loads the memory value into the register. A SHcompact
785 callee calls an argument decoder
786 (GCC_shcompact_incoming_args) that stores the 64-bit
787 value in a stack slot and stores the address of the
788 stack slot in the register. GCC thinks the argument is
789 just passed by transparent reference, but this is only
790 true after the argument decoder is called. Such a call
791 needs to be considered part of the prologue. */
792
793 /* This must be followed by a JSR @r0 instruction and by
794 a NOP instruction. After these, the prologue is over! */
795
796 int next_insn = 0xffff & read_memory_integer (here, insn_size);
797 here += insn_size;
798 if (IS_JSR_R0 (next_insn))
799 {
800 next_insn = 0xffff & read_memory_integer (here, insn_size);
801 here += insn_size;
802
803 if (IS_NOP (next_insn))
804 start_pc = here;
805 }
806 }
807 else
808 break;
809 }
810 }
811
812 return start_pc;
813 }
814
815 static CORE_ADDR
816 sh64_skip_prologue_hard_way (CORE_ADDR start_pc)
817 {
818 CORE_ADDR here, end;
819 int updated_fp = 0;
820 int insn_size = 4;
821 int media_mode = 1;
822
823 if (!start_pc)
824 return 0;
825
826 if (pc_is_isa32 (start_pc) == 0)
827 {
828 insn_size = 2;
829 media_mode = 0;
830 }
831
832 for (here = start_pc, end = start_pc + (insn_size * 28); here < end;)
833 {
834
835 if (media_mode)
836 {
837 int w = read_memory_integer (UNMAKE_ISA32_ADDR (here), insn_size);
838 here += insn_size;
839 if (IS_STQ_R18_R14 (w) || IS_STQ_R18_R15 (w) || IS_STQ_R14_R15 (w)
840 || IS_STL_R14_R15 (w) || IS_STL_R18_R15 (w)
841 || IS_ADDIL_SP_MEDIA (w) || IS_ADDI_SP_MEDIA (w) || IS_PTABSL_R18 (w))
842 {
843 start_pc = here;
844 }
845 else if (IS_MOV_SP_FP (w) || IS_MOV_SP_FP_MEDIA(w))
846 {
847 start_pc = here;
848 updated_fp = 1;
849 }
850 else
851 if (updated_fp)
852 {
853 /* Don't bail out yet, we may have arguments stored in
854 registers here, according to the debug info, so that
855 gdb can print the frames correctly. */
856 start_pc = look_for_args_moves (here - insn_size, media_mode);
857 break;
858 }
859 }
860 else
861 {
862 int w = 0xffff & read_memory_integer (here, insn_size);
863 here += insn_size;
864
865 if (IS_STS_R0 (w) || IS_STS_PR (w)
866 || IS_MOV_TO_R15 (w) || IS_MOV_R14 (w)
867 || IS_MOV_R0 (w) || IS_ADD_SP_R0 (w) || IS_MOV_R14_R0 (w))
868 {
869 start_pc = here;
870 }
871 else if (IS_MOV_SP_FP (w))
872 {
873 start_pc = here;
874 updated_fp = 1;
875 }
876 else
877 if (updated_fp)
878 {
879 /* Don't bail out yet, we may have arguments stored in
880 registers here, according to the debug info, so that
881 gdb can print the frames correctly. */
882 start_pc = look_for_args_moves (here - insn_size, media_mode);
883 break;
884 }
885 }
886 }
887
888 return start_pc;
889 }
890
891 static CORE_ADDR
892 sh_skip_prologue (CORE_ADDR pc)
893 {
894 CORE_ADDR post_prologue_pc;
895
896 /* See if we can determine the end of the prologue via the symbol table.
897 If so, then return either PC, or the PC after the prologue, whichever
898 is greater. */
899 post_prologue_pc = after_prologue (pc);
900
901 /* If after_prologue returned a useful address, then use it. Else
902 fall back on the instruction skipping code. */
903 if (post_prologue_pc != 0)
904 return max (pc, post_prologue_pc);
905 else
906 return (skip_prologue_hard_way (pc));
907 }
908
909 /* Immediately after a function call, return the saved pc.
910 Can't always go through the frames for this because on some machines
911 the new frame is not set up until the new function executes
912 some instructions.
913
914 The return address is the value saved in the PR register + 4 */
915 static CORE_ADDR
916 sh_saved_pc_after_call (struct frame_info *frame)
917 {
918 return (ADDR_BITS_REMOVE (read_register (gdbarch_tdep (current_gdbarch)->PR_REGNUM)));
919 }
920
921 /* Should call_function allocate stack space for a struct return? */
922 static int
923 sh_use_struct_convention (int gcc_p, struct type *type)
924 {
925 #if 0
926 return (TYPE_LENGTH (type) > 1);
927 #else
928 int len = TYPE_LENGTH (type);
929 int nelem = TYPE_NFIELDS (type);
930 return ((len != 1 && len != 2 && len != 4 && len != 8) || nelem != 1) &&
931 (len != 8 || TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) != 4);
932 #endif
933 }
934
935 static int
936 sh64_use_struct_convention (int gcc_p, struct type *type)
937 {
938 return (TYPE_LENGTH (type) > 8);
939 }
940
941 /* Store the address of the place in which to copy the structure the
942 subroutine will return. This is called from call_function.
943
944 We store structs through a pointer passed in R2 */
945 static void
946 sh64_store_struct_return (CORE_ADDR addr, CORE_ADDR sp)
947 {
948 write_register (STRUCT_RETURN_REGNUM, (addr));
949 }
950
951 /* Disassemble an instruction. */
952 static int
953 gdb_print_insn_sh (bfd_vma memaddr, disassemble_info *info)
954 {
955 info->endian = TARGET_BYTE_ORDER;
956 return print_insn_sh (memaddr, info);
957 }
958
959 /* Given a GDB frame, determine the address of the calling function's
960 frame. This will be used to create a new GDB frame struct, and
961 then DEPRECATED_INIT_EXTRA_FRAME_INFO and DEPRECATED_INIT_FRAME_PC
962 will be called for the new frame.
963
964 For us, the frame address is its stack pointer value, so we look up
965 the function prologue to determine the caller's sp value, and return it. */
966 static CORE_ADDR
967 sh_frame_chain (struct frame_info *frame)
968 {
969 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame),
970 get_frame_base (frame),
971 get_frame_base (frame)))
972 return get_frame_base (frame); /* dummy frame same as caller's frame */
973 if (get_frame_pc (frame) && !inside_entry_file (get_frame_pc (frame)))
974 return read_memory_integer (get_frame_base (frame)
975 + get_frame_extra_info (frame)->f_offset, 4);
976 else
977 return 0;
978 }
979
980 /* Given a register number RN as it appears in an assembly
981 instruction, find the corresponding register number in the GDB
982 scheme. */
983 static int
984 translate_insn_rn (int rn, int media_mode)
985 {
986 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
987
988 /* FIXME: this assumes that the number rn is for a not pseudo
989 register only. */
990 if (media_mode)
991 return rn;
992 else
993 {
994 /* These registers don't have a corresponding compact one. */
995 /* FIXME: This is probably not enough. */
996 #if 0
997 if ((rn >= 16 && rn <= 63) || (rn >= 93 && rn <= 140))
998 return rn;
999 #endif
1000 if (rn >= 0 && rn <= tdep->R0_C_REGNUM)
1001 return tdep->R0_C_REGNUM + rn;
1002 else
1003 return rn;
1004 }
1005 }
1006
1007 static CORE_ADDR
1008 sh64_frame_chain (struct frame_info *frame)
1009 {
1010 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame),
1011 get_frame_base (frame),
1012 get_frame_base (frame)))
1013 return get_frame_base (frame); /* dummy frame same as caller's frame */
1014 if (get_frame_pc (frame) && !inside_entry_file (get_frame_pc (frame)))
1015 {
1016 int media_mode = pc_is_isa32 (get_frame_pc (frame));
1017 int size;
1018 if (gdbarch_tdep (current_gdbarch)->sh_abi == SH_ABI_32)
1019 size = 4;
1020 else
1021 size = REGISTER_RAW_SIZE (translate_insn_rn (DEPRECATED_FP_REGNUM, media_mode));
1022 return read_memory_integer (get_frame_base (frame)
1023 + get_frame_extra_info (frame)->f_offset,
1024 size);
1025 }
1026 else
1027 return 0;
1028 }
1029
1030 /* Find REGNUM on the stack. Otherwise, it's in an active register. One thing
1031 we might want to do here is to check REGNUM against the clobber mask, and
1032 somehow flag it as invalid if it isn't saved on the stack somewhere. This
1033 would provide a graceful failure mode when trying to get the value of
1034 caller-saves registers for an inner frame. */
1035 static CORE_ADDR
1036 sh_find_callers_reg (struct frame_info *fi, int regnum)
1037 {
1038 for (; fi; fi = get_next_frame (fi))
1039 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), get_frame_base (fi),
1040 get_frame_base (fi)))
1041 /* When the caller requests PR from the dummy frame, we return PC because
1042 that's where the previous routine appears to have done a call from. */
1043 return deprecated_read_register_dummy (get_frame_pc (fi),
1044 get_frame_base (fi), regnum);
1045 else
1046 {
1047 DEPRECATED_FRAME_INIT_SAVED_REGS (fi);
1048 if (!get_frame_pc (fi))
1049 return 0;
1050 if (get_frame_saved_regs (fi)[regnum] != 0)
1051 return read_memory_integer (get_frame_saved_regs (fi)[regnum],
1052 register_size (current_gdbarch, regnum));
1053 }
1054 return read_register (regnum);
1055 }
1056
1057 static CORE_ADDR
1058 sh64_get_saved_pr (struct frame_info *fi, int pr_regnum)
1059 {
1060 int media_mode = 0;
1061
1062 for (; fi; fi = get_next_frame (fi))
1063 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), get_frame_base (fi),
1064 get_frame_base (fi)))
1065 /* When the caller requests PR from the dummy frame, we return PC because
1066 that's where the previous routine appears to have done a call from. */
1067 return deprecated_read_register_dummy (get_frame_pc (fi),
1068 get_frame_base (fi), pr_regnum);
1069 else
1070 {
1071 DEPRECATED_FRAME_INIT_SAVED_REGS (fi);
1072 if (!get_frame_pc (fi))
1073 return 0;
1074
1075 media_mode = pc_is_isa32 (get_frame_pc (fi));
1076
1077 if (get_frame_saved_regs (fi)[pr_regnum] != 0)
1078 {
1079 int gdb_reg_num = translate_insn_rn (pr_regnum, media_mode);
1080 int size = ((gdbarch_tdep (current_gdbarch)->sh_abi == SH_ABI_32)
1081 ? 4
1082 : REGISTER_RAW_SIZE (gdb_reg_num));
1083 return read_memory_integer (get_frame_saved_regs (fi)[pr_regnum], size);
1084 }
1085 }
1086 return read_register (pr_regnum);
1087 }
1088
1089 /* Put here the code to store, into a struct frame_saved_regs, the
1090 addresses of the saved registers of frame described by FRAME_INFO.
1091 This includes special registers such as pc and fp saved in special
1092 ways in the stack frame. sp is even more special: the address we
1093 return for it IS the sp for the next frame. */
1094 static void
1095 sh_nofp_frame_init_saved_regs (struct frame_info *fi)
1096 {
1097 int *where = (int *) alloca ((NUM_REGS + NUM_PSEUDO_REGS) * sizeof(int));
1098 int rn;
1099 int have_fp = 0;
1100 int depth;
1101 int pc;
1102 int opc;
1103 int insn;
1104 int r3_val = 0;
1105 char *dummy_regs = deprecated_generic_find_dummy_frame (get_frame_pc (fi),
1106 get_frame_base (fi));
1107
1108 if (get_frame_saved_regs (fi) == NULL)
1109 frame_saved_regs_zalloc (fi);
1110 else
1111 memset (get_frame_saved_regs (fi), 0, SIZEOF_FRAME_SAVED_REGS);
1112
1113 if (dummy_regs)
1114 {
1115 /* DANGER! This is ONLY going to work if the char buffer format of
1116 the saved registers is byte-for-byte identical to the
1117 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
1118 memcpy (get_frame_saved_regs (fi), dummy_regs, SIZEOF_FRAME_SAVED_REGS);
1119 return;
1120 }
1121
1122 get_frame_extra_info (fi)->leaf_function = 1;
1123 get_frame_extra_info (fi)->f_offset = 0;
1124
1125 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
1126 where[rn] = -1;
1127
1128 depth = 0;
1129
1130 /* Loop around examining the prologue insns until we find something
1131 that does not appear to be part of the prologue. But give up
1132 after 20 of them, since we're getting silly then. */
1133
1134 pc = get_frame_func (fi);
1135 if (!pc)
1136 {
1137 deprecated_update_frame_pc_hack (fi, 0);
1138 return;
1139 }
1140
1141 for (opc = pc + (2 * 28); pc < opc; pc += 2)
1142 {
1143 insn = read_memory_integer (pc, 2);
1144 /* See where the registers will be saved to */
1145 if (IS_PUSH (insn))
1146 {
1147 rn = GET_PUSHED_REG (insn);
1148 where[rn] = depth;
1149 depth += 4;
1150 }
1151 else if (IS_STS (insn))
1152 {
1153 where[gdbarch_tdep (current_gdbarch)->PR_REGNUM] = depth;
1154 /* If we're storing the pr then this isn't a leaf */
1155 get_frame_extra_info (fi)->leaf_function = 0;
1156 depth += 4;
1157 }
1158 else if (IS_MOV_R3 (insn))
1159 {
1160 r3_val = ((insn & 0xff) ^ 0x80) - 0x80;
1161 }
1162 else if (IS_SHLL_R3 (insn))
1163 {
1164 r3_val <<= 1;
1165 }
1166 else if (IS_ADD_R3SP (insn))
1167 {
1168 depth += -r3_val;
1169 }
1170 else if (IS_ADD_SP (insn))
1171 {
1172 depth -= ((insn & 0xff) ^ 0x80) - 0x80;
1173 }
1174 else if (IS_MOV_SP_FP (insn))
1175 break;
1176 #if 0 /* This used to just stop when it found an instruction that
1177 was not considered part of the prologue. Now, we just
1178 keep going looking for likely instructions. */
1179 else
1180 break;
1181 #endif
1182 }
1183
1184 /* Now we know how deep things are, we can work out their addresses */
1185
1186 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
1187 {
1188 if (where[rn] >= 0)
1189 {
1190 if (rn == DEPRECATED_FP_REGNUM)
1191 have_fp = 1;
1192
1193 get_frame_saved_regs (fi)[rn] = get_frame_base (fi) - where[rn] + depth - 4;
1194 }
1195 else
1196 {
1197 get_frame_saved_regs (fi)[rn] = 0;
1198 }
1199 }
1200
1201 if (have_fp)
1202 {
1203 get_frame_saved_regs (fi)[SP_REGNUM] = read_memory_integer (get_frame_saved_regs (fi)[DEPRECATED_FP_REGNUM], 4);
1204 }
1205 else
1206 {
1207 get_frame_saved_regs (fi)[SP_REGNUM] = get_frame_base (fi) - 4;
1208 }
1209
1210 get_frame_extra_info (fi)->f_offset = depth - where[DEPRECATED_FP_REGNUM] - 4;
1211 /* Work out the return pc - either from the saved pr or the pr
1212 value */
1213 }
1214
1215 /* For vectors of 4 floating point registers. */
1216 static int
1217 fv_reg_base_num (int fv_regnum)
1218 {
1219 int fp_regnum;
1220
1221 fp_regnum = FP0_REGNUM +
1222 (fv_regnum - gdbarch_tdep (current_gdbarch)->FV0_REGNUM) * 4;
1223 return fp_regnum;
1224 }
1225
1226 /* For double precision floating point registers, i.e 2 fp regs.*/
1227 static int
1228 dr_reg_base_num (int dr_regnum)
1229 {
1230 int fp_regnum;
1231
1232 fp_regnum = FP0_REGNUM +
1233 (dr_regnum - gdbarch_tdep (current_gdbarch)->DR0_REGNUM) * 2;
1234 return fp_regnum;
1235 }
1236
1237 /* For pairs of floating point registers */
1238 static int
1239 fpp_reg_base_num (int fpp_regnum)
1240 {
1241 int fp_regnum;
1242
1243 fp_regnum = FP0_REGNUM +
1244 (fpp_regnum - gdbarch_tdep (current_gdbarch)->FPP0_REGNUM) * 2;
1245 return fp_regnum;
1246 }
1247
1248 static int
1249 is_media_pseudo (int rn)
1250 {
1251 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1252
1253 return (rn >= tdep->DR0_REGNUM
1254 && rn <= tdep->FV_LAST_REGNUM);
1255 }
1256
1257 static int
1258 sh64_get_gdb_regnum (int gcc_regnum, CORE_ADDR pc)
1259 {
1260 return translate_insn_rn (gcc_regnum, pc_is_isa32 (pc));
1261 }
1262
1263 static int
1264 sh64_media_reg_base_num (int reg_nr)
1265 {
1266 int base_regnum = -1;
1267 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1268
1269 if (reg_nr >= tdep->DR0_REGNUM
1270 && reg_nr <= tdep->DR_LAST_REGNUM)
1271 base_regnum = dr_reg_base_num (reg_nr);
1272
1273 else if (reg_nr >= tdep->FPP0_REGNUM
1274 && reg_nr <= tdep->FPP_LAST_REGNUM)
1275 base_regnum = fpp_reg_base_num (reg_nr);
1276
1277 else if (reg_nr >= tdep->FV0_REGNUM
1278 && reg_nr <= tdep->FV_LAST_REGNUM)
1279 base_regnum = fv_reg_base_num (reg_nr);
1280
1281 return base_regnum;
1282 }
1283
1284 /* *INDENT-OFF* */
1285 /*
1286 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
1287 GDB_REGNUM BASE_REGNUM
1288 r0_c 221 0
1289 r1_c 222 1
1290 r2_c 223 2
1291 r3_c 224 3
1292 r4_c 225 4
1293 r5_c 226 5
1294 r6_c 227 6
1295 r7_c 228 7
1296 r8_c 229 8
1297 r9_c 230 9
1298 r10_c 231 10
1299 r11_c 232 11
1300 r12_c 233 12
1301 r13_c 234 13
1302 r14_c 235 14
1303 r15_c 236 15
1304
1305 pc_c 237 64
1306 gbr_c 238 16
1307 mach_c 239 17
1308 macl_c 240 17
1309 pr_c 241 18
1310 t_c 242 19
1311 fpscr_c 243 76
1312 fpul_c 244 109
1313
1314 fr0_c 245 77
1315 fr1_c 246 78
1316 fr2_c 247 79
1317 fr3_c 248 80
1318 fr4_c 249 81
1319 fr5_c 250 82
1320 fr6_c 251 83
1321 fr7_c 252 84
1322 fr8_c 253 85
1323 fr9_c 254 86
1324 fr10_c 255 87
1325 fr11_c 256 88
1326 fr12_c 257 89
1327 fr13_c 258 90
1328 fr14_c 259 91
1329 fr15_c 260 92
1330
1331 dr0_c 261 77
1332 dr2_c 262 79
1333 dr4_c 263 81
1334 dr6_c 264 83
1335 dr8_c 265 85
1336 dr10_c 266 87
1337 dr12_c 267 89
1338 dr14_c 268 91
1339
1340 fv0_c 269 77
1341 fv4_c 270 81
1342 fv8_c 271 85
1343 fv12_c 272 91
1344 */
1345 /* *INDENT-ON* */
1346 static int
1347 sh64_compact_reg_base_num (int reg_nr)
1348 {
1349 int base_regnum = -1;
1350 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1351
1352 /* general register N maps to general register N */
1353 if (reg_nr >= tdep->R0_C_REGNUM
1354 && reg_nr <= tdep->R_LAST_C_REGNUM)
1355 base_regnum = reg_nr - tdep->R0_C_REGNUM;
1356
1357 /* floating point register N maps to floating point register N */
1358 else if (reg_nr >= tdep->FP0_C_REGNUM
1359 && reg_nr <= tdep->FP_LAST_C_REGNUM)
1360 base_regnum = reg_nr - tdep->FP0_C_REGNUM + FP0_REGNUM;
1361
1362 /* double prec register N maps to base regnum for double prec register N */
1363 else if (reg_nr >= tdep->DR0_C_REGNUM
1364 && reg_nr <= tdep->DR_LAST_C_REGNUM)
1365 base_regnum = dr_reg_base_num (tdep->DR0_REGNUM
1366 + reg_nr - tdep->DR0_C_REGNUM);
1367
1368 /* vector N maps to base regnum for vector register N */
1369 else if (reg_nr >= tdep->FV0_C_REGNUM
1370 && reg_nr <= tdep->FV_LAST_C_REGNUM)
1371 base_regnum = fv_reg_base_num (tdep->FV0_REGNUM
1372 + reg_nr - tdep->FV0_C_REGNUM);
1373
1374 else if (reg_nr == tdep->PC_C_REGNUM)
1375 base_regnum = PC_REGNUM;
1376
1377 else if (reg_nr == tdep->GBR_C_REGNUM)
1378 base_regnum = 16;
1379
1380 else if (reg_nr == tdep->MACH_C_REGNUM
1381 || reg_nr == tdep->MACL_C_REGNUM)
1382 base_regnum = 17;
1383
1384 else if (reg_nr == tdep->PR_C_REGNUM)
1385 base_regnum = 18;
1386
1387 else if (reg_nr == tdep->T_C_REGNUM)
1388 base_regnum = 19;
1389
1390 else if (reg_nr == tdep->FPSCR_C_REGNUM)
1391 base_regnum = tdep->FPSCR_REGNUM; /*???? this register is a mess. */
1392
1393 else if (reg_nr == tdep->FPUL_C_REGNUM)
1394 base_regnum = FP0_REGNUM + 32;
1395
1396 return base_regnum;
1397 }
1398
1399 /* Given a register number RN (according to the gdb scheme) , return
1400 its corresponding architectural register. In media mode, only a
1401 subset of the registers is pseudo registers. For compact mode, all
1402 the registers are pseudo. */
1403 static int
1404 translate_rn_to_arch_reg_num (int rn, int media_mode)
1405 {
1406
1407 if (media_mode)
1408 {
1409 if (!is_media_pseudo (rn))
1410 return rn;
1411 else
1412 return sh64_media_reg_base_num (rn);
1413 }
1414 else
1415 /* All compact registers are pseudo. */
1416 return sh64_compact_reg_base_num (rn);
1417 }
1418
1419 static int
1420 sign_extend (int value, int bits)
1421 {
1422 value = value & ((1 << bits) - 1);
1423 return (value & (1 << (bits - 1))
1424 ? value | (~((1 << bits) - 1))
1425 : value);
1426 }
1427
1428 static void
1429 sh64_nofp_frame_init_saved_regs (struct frame_info *fi)
1430 {
1431 int *where = (int *) alloca ((NUM_REGS + NUM_PSEUDO_REGS) * sizeof (int));
1432 int rn;
1433 int have_fp = 0;
1434 int fp_regnum;
1435 int sp_regnum;
1436 int depth;
1437 int pc;
1438 int opc;
1439 int insn;
1440 int r0_val = 0;
1441 int media_mode = 0;
1442 int insn_size;
1443 int gdb_register_number;
1444 int register_number;
1445 char *dummy_regs = deprecated_generic_find_dummy_frame (get_frame_pc (fi), get_frame_base (fi));
1446 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1447
1448 if (get_frame_saved_regs (fi) == NULL)
1449 frame_saved_regs_zalloc (fi);
1450 else
1451 memset (get_frame_saved_regs (fi), 0, SIZEOF_FRAME_SAVED_REGS);
1452
1453 if (dummy_regs)
1454 {
1455 /* DANGER! This is ONLY going to work if the char buffer format of
1456 the saved registers is byte-for-byte identical to the
1457 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
1458 memcpy (get_frame_saved_regs (fi), dummy_regs, SIZEOF_FRAME_SAVED_REGS);
1459 return;
1460 }
1461
1462 get_frame_extra_info (fi)->leaf_function = 1;
1463 get_frame_extra_info (fi)->f_offset = 0;
1464
1465 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
1466 where[rn] = -1;
1467
1468 depth = 0;
1469
1470 /* Loop around examining the prologue insns until we find something
1471 that does not appear to be part of the prologue. But give up
1472 after 20 of them, since we're getting silly then. */
1473
1474 pc = get_frame_func (fi);
1475 if (!pc)
1476 {
1477 deprecated_update_frame_pc_hack (fi, 0);
1478 return;
1479 }
1480
1481 if (pc_is_isa32 (pc))
1482 {
1483 media_mode = 1;
1484 insn_size = 4;
1485 }
1486 else
1487 {
1488 media_mode = 0;
1489 insn_size = 2;
1490 }
1491
1492 /* The frame pointer register is general register 14 in shmedia and
1493 shcompact modes. In sh compact it is a pseudo register. Same goes
1494 for the stack pointer register, which is register 15. */
1495 fp_regnum = translate_insn_rn (DEPRECATED_FP_REGNUM, media_mode);
1496 sp_regnum = translate_insn_rn (SP_REGNUM, media_mode);
1497
1498 for (opc = pc + (insn_size * 28); pc < opc; pc += insn_size)
1499 {
1500 insn = read_memory_integer (media_mode ? UNMAKE_ISA32_ADDR (pc) : pc,
1501 insn_size);
1502
1503 if (media_mode == 0)
1504 {
1505 if (IS_STS_PR (insn))
1506 {
1507 int next_insn = read_memory_integer (pc + insn_size, insn_size);
1508 if (IS_MOV_TO_R15 (next_insn))
1509 {
1510 int reg_nr = tdep->PR_C_REGNUM;
1511
1512 where[reg_nr] = depth - ((((next_insn & 0xf) ^ 0x8) - 0x8) << 2);
1513 get_frame_extra_info (fi)->leaf_function = 0;
1514 pc += insn_size;
1515 }
1516 }
1517 else if (IS_MOV_R14 (insn))
1518 {
1519 where[fp_regnum] = depth - ((((insn & 0xf) ^ 0x8) - 0x8) << 2);
1520 }
1521
1522 else if (IS_MOV_R0 (insn))
1523 {
1524 /* Put in R0 the offset from SP at which to store some
1525 registers. We are interested in this value, because it
1526 will tell us where the given registers are stored within
1527 the frame. */
1528 r0_val = ((insn & 0xff) ^ 0x80) - 0x80;
1529 }
1530 else if (IS_ADD_SP_R0 (insn))
1531 {
1532 /* This instruction still prepares r0, but we don't care.
1533 We already have the offset in r0_val. */
1534 }
1535 else if (IS_STS_R0 (insn))
1536 {
1537 /* Store PR at r0_val-4 from SP. Decrement r0 by 4*/
1538 int reg_nr = tdep->PR_C_REGNUM;
1539 where[reg_nr] = depth - (r0_val - 4);
1540 r0_val -= 4;
1541 get_frame_extra_info (fi)->leaf_function = 0;
1542 }
1543 else if (IS_MOV_R14_R0 (insn))
1544 {
1545 /* Store R14 at r0_val-4 from SP. Decrement r0 by 4 */
1546 where[fp_regnum] = depth - (r0_val - 4);
1547 r0_val -= 4;
1548 }
1549
1550 else if (IS_ADD_SP (insn))
1551 {
1552 depth -= ((insn & 0xff) ^ 0x80) - 0x80;
1553 }
1554 else if (IS_MOV_SP_FP (insn))
1555 break;
1556 }
1557 else
1558 {
1559 if (IS_ADDIL_SP_MEDIA (insn)
1560 || IS_ADDI_SP_MEDIA (insn))
1561 {
1562 depth -= sign_extend ((((insn & 0xffc00) ^ 0x80000) - 0x80000) >> 10, 9);
1563 }
1564
1565 else if (IS_STQ_R18_R15 (insn))
1566 {
1567 where[tdep->PR_REGNUM] =
1568 depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 3);
1569 get_frame_extra_info (fi)->leaf_function = 0;
1570 }
1571
1572 else if (IS_STL_R18_R15 (insn))
1573 {
1574 where[tdep->PR_REGNUM] =
1575 depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 2);
1576 get_frame_extra_info (fi)->leaf_function = 0;
1577 }
1578
1579 else if (IS_STQ_R14_R15 (insn))
1580 {
1581 where[fp_regnum] = depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 3);
1582 }
1583
1584 else if (IS_STL_R14_R15 (insn))
1585 {
1586 where[fp_regnum] = depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 2);
1587 }
1588
1589 else if (IS_MOV_SP_FP_MEDIA (insn))
1590 break;
1591 }
1592 }
1593
1594 /* Now we know how deep things are, we can work out their addresses. */
1595 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
1596 {
1597 register_number = translate_rn_to_arch_reg_num (rn, media_mode);
1598
1599 if (where[rn] >= 0)
1600 {
1601 if (rn == fp_regnum)
1602 have_fp = 1;
1603
1604 /* Watch out! saved_regs is only for the real registers, and
1605 doesn't include space for the pseudo registers. */
1606 get_frame_saved_regs (fi)[register_number]= get_frame_base (fi) - where[rn] + depth;
1607
1608 }
1609 else
1610 get_frame_saved_regs (fi)[register_number] = 0;
1611 }
1612
1613 if (have_fp)
1614 {
1615 /* SP_REGNUM is 15. For shmedia 15 is the real register. For
1616 shcompact 15 is the arch register corresponding to the pseudo
1617 register r15 which still is the SP register. */
1618 /* The place on the stack where fp is stored contains the sp of
1619 the caller. */
1620 /* Again, saved_registers contains only space for the real
1621 registers, so we store in DEPRECATED_FP_REGNUM position. */
1622 int size;
1623 if (tdep->sh_abi == SH_ABI_32)
1624 size = 4;
1625 else
1626 size = REGISTER_RAW_SIZE (fp_regnum);
1627 get_frame_saved_regs (fi)[sp_regnum] = read_memory_integer (get_frame_saved_regs (fi)[fp_regnum], size);
1628 }
1629 else
1630 get_frame_saved_regs (fi)[sp_regnum] = get_frame_base (fi);
1631
1632 get_frame_extra_info (fi)->f_offset = depth - where[fp_regnum];
1633 }
1634
1635 static void
1636 sh_fp_frame_init_saved_regs (struct frame_info *fi)
1637 {
1638 int *where = (int *) alloca ((NUM_REGS + NUM_PSEUDO_REGS) * sizeof (int));
1639 int rn;
1640 int have_fp = 0;
1641 int depth;
1642 int pc;
1643 int opc;
1644 int insn;
1645 int r3_val = 0;
1646 char *dummy_regs = deprecated_generic_find_dummy_frame (get_frame_pc (fi), get_frame_base (fi));
1647 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1648
1649 if (get_frame_saved_regs (fi) == NULL)
1650 frame_saved_regs_zalloc (fi);
1651 else
1652 memset (get_frame_saved_regs (fi), 0, SIZEOF_FRAME_SAVED_REGS);
1653
1654 if (dummy_regs)
1655 {
1656 /* DANGER! This is ONLY going to work if the char buffer format of
1657 the saved registers is byte-for-byte identical to the
1658 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
1659 memcpy (get_frame_saved_regs (fi), dummy_regs, SIZEOF_FRAME_SAVED_REGS);
1660 return;
1661 }
1662
1663 get_frame_extra_info (fi)->leaf_function = 1;
1664 get_frame_extra_info (fi)->f_offset = 0;
1665
1666 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
1667 where[rn] = -1;
1668
1669 depth = 0;
1670
1671 /* Loop around examining the prologue insns until we find something
1672 that does not appear to be part of the prologue. But give up
1673 after 20 of them, since we're getting silly then. */
1674
1675 pc = get_frame_func (fi);
1676 if (!pc)
1677 {
1678 deprecated_update_frame_pc_hack (fi, 0);
1679 return;
1680 }
1681
1682 for (opc = pc + (2 * 28); pc < opc; pc += 2)
1683 {
1684 insn = read_memory_integer (pc, 2);
1685 /* See where the registers will be saved to */
1686 if (IS_PUSH (insn))
1687 {
1688 rn = GET_PUSHED_REG (insn);
1689 where[rn] = depth;
1690 depth += 4;
1691 }
1692 else if (IS_STS (insn))
1693 {
1694 where[tdep->PR_REGNUM] = depth;
1695 /* If we're storing the pr then this isn't a leaf */
1696 get_frame_extra_info (fi)->leaf_function = 0;
1697 depth += 4;
1698 }
1699 else if (IS_MOV_R3 (insn))
1700 {
1701 r3_val = ((insn & 0xff) ^ 0x80) - 0x80;
1702 }
1703 else if (IS_SHLL_R3 (insn))
1704 {
1705 r3_val <<= 1;
1706 }
1707 else if (IS_ADD_R3SP (insn))
1708 {
1709 depth += -r3_val;
1710 }
1711 else if (IS_ADD_SP (insn))
1712 {
1713 depth -= ((insn & 0xff) ^ 0x80) - 0x80;
1714 }
1715 else if (IS_FMOV (insn))
1716 {
1717 if (read_register (tdep->FPSCR_REGNUM) & FPSCR_SZ)
1718 {
1719 depth += 8;
1720 }
1721 else
1722 {
1723 depth += 4;
1724 }
1725 }
1726 else if (IS_MOV_SP_FP (insn))
1727 break;
1728 #if 0 /* This used to just stop when it found an instruction that
1729 was not considered part of the prologue. Now, we just
1730 keep going looking for likely instructions. */
1731 else
1732 break;
1733 #endif
1734 }
1735
1736 /* Now we know how deep things are, we can work out their addresses */
1737
1738 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
1739 {
1740 if (where[rn] >= 0)
1741 {
1742 if (rn == DEPRECATED_FP_REGNUM)
1743 have_fp = 1;
1744
1745 get_frame_saved_regs (fi)[rn] = get_frame_base (fi) - where[rn] + depth - 4;
1746 }
1747 else
1748 {
1749 get_frame_saved_regs (fi)[rn] = 0;
1750 }
1751 }
1752
1753 if (have_fp)
1754 {
1755 get_frame_saved_regs (fi)[SP_REGNUM] =
1756 read_memory_integer (get_frame_saved_regs (fi)[DEPRECATED_FP_REGNUM], 4);
1757 }
1758 else
1759 {
1760 get_frame_saved_regs (fi)[SP_REGNUM] = get_frame_base (fi) - 4;
1761 }
1762
1763 get_frame_extra_info (fi)->f_offset = depth - where[DEPRECATED_FP_REGNUM] - 4;
1764 /* Work out the return pc - either from the saved pr or the pr
1765 value */
1766 }
1767
1768 /* Initialize the extra info saved in a FRAME */
1769 static void
1770 sh_init_extra_frame_info (int fromleaf, struct frame_info *fi)
1771 {
1772
1773 frame_extra_info_zalloc (fi, sizeof (struct frame_extra_info));
1774
1775 if (get_next_frame (fi))
1776 deprecated_update_frame_pc_hack (fi, DEPRECATED_FRAME_SAVED_PC (get_next_frame (fi)));
1777
1778 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), get_frame_base (fi),
1779 get_frame_base (fi)))
1780 {
1781 /* We need to setup fi->frame here because call_function_by_hand
1782 gets it wrong by assuming it's always FP. */
1783 deprecated_update_frame_base_hack (fi, deprecated_read_register_dummy (get_frame_pc (fi), get_frame_base (fi),
1784 SP_REGNUM));
1785 get_frame_extra_info (fi)->return_pc = deprecated_read_register_dummy (get_frame_pc (fi),
1786 get_frame_base (fi),
1787 PC_REGNUM);
1788 get_frame_extra_info (fi)->f_offset = -(DEPRECATED_CALL_DUMMY_LENGTH + 4);
1789 get_frame_extra_info (fi)->leaf_function = 0;
1790 return;
1791 }
1792 else
1793 {
1794 DEPRECATED_FRAME_INIT_SAVED_REGS (fi);
1795 get_frame_extra_info (fi)->return_pc =
1796 sh_find_callers_reg (fi, gdbarch_tdep (current_gdbarch)->PR_REGNUM);
1797 }
1798 }
1799
1800 static void
1801 sh64_init_extra_frame_info (int fromleaf, struct frame_info *fi)
1802 {
1803 int media_mode = pc_is_isa32 (get_frame_pc (fi));
1804
1805 frame_extra_info_zalloc (fi, sizeof (struct frame_extra_info));
1806
1807 if (get_next_frame (fi))
1808 deprecated_update_frame_pc_hack (fi, DEPRECATED_FRAME_SAVED_PC (get_next_frame (fi)));
1809
1810 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), get_frame_base (fi),
1811 get_frame_base (fi)))
1812 {
1813 /* We need to setup fi->frame here because call_function_by_hand
1814 gets it wrong by assuming it's always FP. */
1815 deprecated_update_frame_base_hack (fi, deprecated_read_register_dummy (get_frame_pc (fi), get_frame_base (fi), SP_REGNUM));
1816 get_frame_extra_info (fi)->return_pc =
1817 deprecated_read_register_dummy (get_frame_pc (fi),
1818 get_frame_base (fi), PC_REGNUM);
1819 get_frame_extra_info (fi)->f_offset = -(DEPRECATED_CALL_DUMMY_LENGTH + 4);
1820 get_frame_extra_info (fi)->leaf_function = 0;
1821 return;
1822 }
1823 else
1824 {
1825 DEPRECATED_FRAME_INIT_SAVED_REGS (fi);
1826 get_frame_extra_info (fi)->return_pc =
1827 sh64_get_saved_pr (fi, gdbarch_tdep (current_gdbarch)->PR_REGNUM);
1828 }
1829 }
1830
1831 static void
1832 sh64_get_saved_register (char *raw_buffer, int *optimized, CORE_ADDR *addrp,
1833 struct frame_info *frame, int regnum,
1834 enum lval_type *lval)
1835 {
1836 int media_mode;
1837 int live_regnum = regnum;
1838 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1839
1840 if (!target_has_registers)
1841 error ("No registers.");
1842
1843 /* Normal systems don't optimize out things with register numbers. */
1844 if (optimized != NULL)
1845 *optimized = 0;
1846
1847 if (addrp) /* default assumption: not found in memory */
1848 *addrp = 0;
1849
1850 if (raw_buffer)
1851 memset (raw_buffer, 0, sizeof (raw_buffer));
1852
1853 /* We must do this here, before the following while loop changes
1854 frame, and makes it NULL. If this is a media register number,
1855 but we are in compact mode, it will become the corresponding
1856 compact pseudo register. If there is no corresponding compact
1857 pseudo-register what do we do?*/
1858 media_mode = pc_is_isa32 (get_frame_pc (frame));
1859 live_regnum = translate_insn_rn (regnum, media_mode);
1860
1861 /* Note: since the current frame's registers could only have been
1862 saved by frames INTERIOR TO the current frame, we skip examining
1863 the current frame itself: otherwise, we would be getting the
1864 previous frame's registers which were saved by the current frame. */
1865
1866 while (frame && ((frame = get_next_frame (frame)) != NULL))
1867 {
1868 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame),
1869 get_frame_base (frame),
1870 get_frame_base (frame)))
1871 {
1872 if (lval) /* found it in a CALL_DUMMY frame */
1873 *lval = not_lval;
1874 if (raw_buffer)
1875 memcpy (raw_buffer,
1876 (deprecated_generic_find_dummy_frame (get_frame_pc (frame), get_frame_base (frame))
1877 + REGISTER_BYTE (regnum)),
1878 REGISTER_RAW_SIZE (regnum));
1879 return;
1880 }
1881
1882 DEPRECATED_FRAME_INIT_SAVED_REGS (frame);
1883 if (get_frame_saved_regs (frame) != NULL
1884 && get_frame_saved_regs (frame)[regnum] != 0)
1885 {
1886 if (lval) /* found it saved on the stack */
1887 *lval = lval_memory;
1888 if (regnum == SP_REGNUM)
1889 {
1890 if (raw_buffer) /* SP register treated specially */
1891 store_unsigned_integer (raw_buffer, REGISTER_RAW_SIZE (regnum),
1892 get_frame_saved_regs (frame)[regnum]);
1893 }
1894 else
1895 { /* any other register */
1896
1897 if (addrp)
1898 *addrp = get_frame_saved_regs (frame)[regnum];
1899 if (raw_buffer)
1900 {
1901 int size;
1902 if (tdep->sh_abi == SH_ABI_32
1903 && (live_regnum == DEPRECATED_FP_REGNUM
1904 || live_regnum == tdep->PR_REGNUM))
1905 size = 4;
1906 else
1907 size = REGISTER_RAW_SIZE (live_regnum);
1908 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
1909 read_memory (get_frame_saved_regs (frame)[regnum], raw_buffer, size);
1910 else
1911 read_memory (get_frame_saved_regs (frame)[regnum],
1912 raw_buffer
1913 + REGISTER_RAW_SIZE (live_regnum)
1914 - size,
1915 size);
1916 }
1917 }
1918 return;
1919 }
1920 }
1921
1922 /* If we get thru the loop to this point, it means the register was
1923 not saved in any frame. Return the actual live-register value. */
1924
1925 if (lval) /* found it in a live register */
1926 *lval = lval_register;
1927 if (addrp)
1928 *addrp = REGISTER_BYTE (live_regnum);
1929 if (raw_buffer)
1930 deprecated_read_register_gen (live_regnum, raw_buffer);
1931 }
1932
1933 /* Extract from an array REGBUF containing the (raw) register state
1934 the address in which a function should return its structure value,
1935 as a CORE_ADDR (or an expression that can be used as one). */
1936 static CORE_ADDR
1937 sh_extract_struct_value_address (struct regcache *regcache)
1938 {
1939 ULONGEST addr;
1940 /*FIXME: Is R0 really correct here? Not STRUCT_RETURN_REGNUM? */
1941 regcache_cooked_read_unsigned (regcache, STRUCT_RETURN_REGNUM, &addr);
1942 return addr;
1943 }
1944
1945 static CORE_ADDR
1946 sh64_extract_struct_value_address (char *regbuf)
1947 {
1948 return (extract_unsigned_integer ((regbuf + REGISTER_BYTE (STRUCT_RETURN_REGNUM)),
1949 REGISTER_RAW_SIZE (STRUCT_RETURN_REGNUM)));
1950 }
1951
1952 static CORE_ADDR
1953 sh_frame_saved_pc (struct frame_info *frame)
1954 {
1955 return (get_frame_extra_info (frame)->return_pc);
1956 }
1957
1958 /* Discard from the stack the innermost frame,
1959 restoring all saved registers. */
1960 static void
1961 sh_pop_frame (void)
1962 {
1963 register struct frame_info *frame = get_current_frame ();
1964 register CORE_ADDR fp;
1965 register int regnum;
1966
1967 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame),
1968 get_frame_base (frame),
1969 get_frame_base (frame)))
1970 generic_pop_dummy_frame ();
1971 else
1972 {
1973 fp = get_frame_base (frame);
1974 DEPRECATED_FRAME_INIT_SAVED_REGS (frame);
1975
1976 /* Copy regs from where they were saved in the frame */
1977 for (regnum = 0; regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++)
1978 if (get_frame_saved_regs (frame)[regnum])
1979 write_register (regnum,
1980 read_memory_integer (get_frame_saved_regs (frame)[regnum], 4));
1981
1982 write_register (PC_REGNUM, get_frame_extra_info (frame)->return_pc);
1983 write_register (SP_REGNUM, fp + 4);
1984 }
1985 flush_cached_frames ();
1986 }
1987
1988 /* Used in the 'return' command. */
1989 static void
1990 sh64_pop_frame (void)
1991 {
1992 register struct frame_info *frame = get_current_frame ();
1993 register CORE_ADDR fp;
1994 register int regnum;
1995 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1996
1997 int media_mode = pc_is_isa32 (get_frame_pc (frame));
1998
1999 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame),
2000 get_frame_base (frame),
2001 get_frame_base (frame)))
2002 generic_pop_dummy_frame ();
2003 else
2004 {
2005 fp = get_frame_base (frame);
2006 DEPRECATED_FRAME_INIT_SAVED_REGS (frame);
2007
2008 /* Copy regs from where they were saved in the frame */
2009 for (regnum = 0; regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++)
2010 if (get_frame_saved_regs (frame)[regnum])
2011 {
2012 int size;
2013 if (tdep->sh_abi == SH_ABI_32
2014 && (regnum == DEPRECATED_FP_REGNUM
2015 || regnum == tdep->PR_REGNUM))
2016 size = 4;
2017 else
2018 size = REGISTER_RAW_SIZE (translate_insn_rn (regnum,
2019 media_mode));
2020 write_register (regnum,
2021 read_memory_integer (get_frame_saved_regs (frame)[regnum],
2022 size));
2023 }
2024
2025 write_register (PC_REGNUM, get_frame_extra_info (frame)->return_pc);
2026 write_register (SP_REGNUM, fp + 8);
2027 }
2028 flush_cached_frames ();
2029 }
2030
2031 static CORE_ADDR
2032 sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
2033 {
2034 return sp & ~3;
2035 }
2036
2037 /* Function: push_arguments
2038 Setup the function arguments for calling a function in the inferior.
2039
2040 On the Hitachi SH architecture, there are four registers (R4 to R7)
2041 which are dedicated for passing function arguments. Up to the first
2042 four arguments (depending on size) may go into these registers.
2043 The rest go on the stack.
2044
2045 Arguments that are smaller than 4 bytes will still take up a whole
2046 register or a whole 32-bit word on the stack, and will be
2047 right-justified in the register or the stack word. This includes
2048 chars, shorts, and small aggregate types.
2049
2050 Arguments that are larger than 4 bytes may be split between two or
2051 more registers. If there are not enough registers free, an argument
2052 may be passed partly in a register (or registers), and partly on the
2053 stack. This includes doubles, long longs, and larger aggregates.
2054 As far as I know, there is no upper limit to the size of aggregates
2055 that will be passed in this way; in other words, the convention of
2056 passing a pointer to a large aggregate instead of a copy is not used.
2057
2058 An exceptional case exists for struct arguments (and possibly other
2059 aggregates such as arrays) if the size is larger than 4 bytes but
2060 not a multiple of 4 bytes. In this case the argument is never split
2061 between the registers and the stack, but instead is copied in its
2062 entirety onto the stack, AND also copied into as many registers as
2063 there is room for. In other words, space in registers permitting,
2064 two copies of the same argument are passed in. As far as I can tell,
2065 only the one on the stack is used, although that may be a function
2066 of the level of compiler optimization. I suspect this is a compiler
2067 bug. Arguments of these odd sizes are left-justified within the
2068 word (as opposed to arguments smaller than 4 bytes, which are
2069 right-justified).
2070
2071 If the function is to return an aggregate type such as a struct, it
2072 is either returned in the normal return value register R0 (if its
2073 size is no greater than one byte), or else the caller must allocate
2074 space into which the callee will copy the return value (if the size
2075 is greater than one byte). In this case, a pointer to the return
2076 value location is passed into the callee in register R2, which does
2077 not displace any of the other arguments passed in via registers R4
2078 to R7. */
2079
2080 static CORE_ADDR
2081 sh_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
2082 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
2083 struct value **args, CORE_ADDR sp, int struct_return,
2084 CORE_ADDR struct_addr)
2085
2086 {
2087 int stack_offset, stack_alloc;
2088 int argreg;
2089 int argnum;
2090 struct type *type;
2091 CORE_ADDR regval;
2092 char *val;
2093 char valbuf[4];
2094 int len;
2095 int odd_sized_struct;
2096 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2097
2098 /* first force sp to a 4-byte alignment */
2099 sp = sh_frame_align (gdbarch, sp);
2100
2101 /* The "struct return pointer" pseudo-argument has its own dedicated
2102 register */
2103 if (struct_return)
2104 regcache_cooked_write_unsigned (regcache, STRUCT_RETURN_REGNUM, struct_addr);
2105
2106 /* Now make sure there's space on the stack */
2107 for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++)
2108 stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[argnum])) + 3) & ~3);
2109 sp -= stack_alloc; /* make room on stack for args */
2110
2111 /* Now load as many as possible of the first arguments into
2112 registers, and push the rest onto the stack. There are 16 bytes
2113 in four registers available. Loop thru args from first to last. */
2114
2115 argreg = tdep->ARG0_REGNUM;
2116 for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++)
2117 {
2118 type = VALUE_TYPE (args[argnum]);
2119 len = TYPE_LENGTH (type);
2120 memset (valbuf, 0, sizeof (valbuf));
2121 if (len < 4)
2122 {
2123 /* value gets right-justified in the register or stack word */
2124 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2125 memcpy (valbuf + (4 - len),
2126 (char *) VALUE_CONTENTS (args[argnum]), len);
2127 else
2128 memcpy (valbuf, (char *) VALUE_CONTENTS (args[argnum]), len);
2129 val = valbuf;
2130 }
2131 else
2132 val = (char *) VALUE_CONTENTS (args[argnum]);
2133
2134 if (len > 4 && (len & 3) != 0)
2135 odd_sized_struct = 1; /* such structs go entirely on stack */
2136 else
2137 odd_sized_struct = 0;
2138 while (len > 0)
2139 {
2140 if (argreg > tdep->ARGLAST_REGNUM
2141 || odd_sized_struct)
2142 {
2143 /* must go on the stack */
2144 write_memory (sp + stack_offset, val, 4);
2145 stack_offset += 4;
2146 }
2147 /* NOTE WELL!!!!! This is not an "else if" clause!!!
2148 That's because some *&^%$ things get passed on the stack
2149 AND in the registers! */
2150 if (argreg <= tdep->ARGLAST_REGNUM)
2151 {
2152 /* there's room in a register */
2153 regval = extract_unsigned_integer (val, register_size (gdbarch,
2154 argreg));
2155 regcache_cooked_write_unsigned (regcache, argreg++, regval);
2156 }
2157 /* Store the value 4 bytes at a time. This means that things
2158 larger than 4 bytes may go partly in registers and partly
2159 on the stack. */
2160 len -= register_size (gdbarch, argreg);
2161 val += register_size (gdbarch, argreg);
2162 }
2163 }
2164
2165 /* Store return address. */
2166 regcache_cooked_write_unsigned (regcache, tdep->PR_REGNUM, bp_addr);
2167
2168 /* Update stack pointer. */
2169 regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp);
2170
2171 return sp;
2172 }
2173
2174 /* R2-R9 for integer types and integer equivalent (char, pointers) and
2175 non-scalar (struct, union) elements (even if the elements are
2176 floats).
2177 FR0-FR11 for single precision floating point (float)
2178 DR0-DR10 for double precision floating point (double)
2179
2180 If a float is argument number 3 (for instance) and arguments number
2181 1,2, and 4 are integer, the mapping will be:
2182 arg1 -->R2, arg2 --> R3, arg3 -->FR0, arg4 --> R5. I.e. R4 is not used.
2183
2184 If a float is argument number 10 (for instance) and arguments number
2185 1 through 10 are integer, the mapping will be:
2186 arg1->R2, arg2->R3, arg3->R4, arg4->R5, arg5->R6, arg6->R7, arg7->R8,
2187 arg8->R9, arg9->(0,SP)stack(8-byte aligned), arg10->FR0, arg11->stack(16,SP).
2188 I.e. there is hole in the stack.
2189
2190 Different rules apply for variable arguments functions, and for functions
2191 for which the prototype is not known. */
2192
2193 static CORE_ADDR
2194 sh64_push_arguments (int nargs, struct value **args, CORE_ADDR sp,
2195 int struct_return, CORE_ADDR struct_addr)
2196 {
2197 int stack_offset, stack_alloc;
2198 int int_argreg;
2199 int float_argreg;
2200 int double_argreg;
2201 int float_arg_index = 0;
2202 int double_arg_index = 0;
2203 int argnum;
2204 struct type *type;
2205 CORE_ADDR regval;
2206 char *val;
2207 char valbuf[8];
2208 char valbuf_tmp[8];
2209 int len;
2210 int argreg_size;
2211 int fp_args[12];
2212 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2213
2214 memset (fp_args, 0, sizeof (fp_args));
2215
2216 /* first force sp to a 8-byte alignment */
2217 sp = sp & ~7;
2218
2219 /* The "struct return pointer" pseudo-argument has its own dedicated
2220 register */
2221
2222 if (struct_return)
2223 write_register (STRUCT_RETURN_REGNUM, struct_addr);
2224
2225 /* Now make sure there's space on the stack */
2226 for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++)
2227 stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[argnum])) + 7) & ~7);
2228 sp -= stack_alloc; /* make room on stack for args */
2229
2230 /* Now load as many as possible of the first arguments into
2231 registers, and push the rest onto the stack. There are 64 bytes
2232 in eight registers available. Loop thru args from first to last. */
2233
2234 int_argreg = tdep->ARG0_REGNUM;
2235 float_argreg = FP0_REGNUM;
2236 double_argreg = tdep->DR0_REGNUM;
2237
2238 for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++)
2239 {
2240 type = VALUE_TYPE (args[argnum]);
2241 len = TYPE_LENGTH (type);
2242 memset (valbuf, 0, sizeof (valbuf));
2243
2244 if (TYPE_CODE (type) != TYPE_CODE_FLT)
2245 {
2246 argreg_size = REGISTER_RAW_SIZE (int_argreg);
2247
2248 if (len < argreg_size)
2249 {
2250 /* value gets right-justified in the register or stack word */
2251 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2252 memcpy (valbuf + argreg_size - len,
2253 (char *) VALUE_CONTENTS (args[argnum]), len);
2254 else
2255 memcpy (valbuf, (char *) VALUE_CONTENTS (args[argnum]), len);
2256
2257 val = valbuf;
2258 }
2259 else
2260 val = (char *) VALUE_CONTENTS (args[argnum]);
2261
2262 while (len > 0)
2263 {
2264 if (int_argreg > tdep->ARGLAST_REGNUM)
2265 {
2266 /* must go on the stack */
2267 write_memory (sp + stack_offset, val, argreg_size);
2268 stack_offset += 8;/*argreg_size;*/
2269 }
2270 /* NOTE WELL!!!!! This is not an "else if" clause!!!
2271 That's because some *&^%$ things get passed on the stack
2272 AND in the registers! */
2273 if (int_argreg <= tdep->ARGLAST_REGNUM)
2274 {
2275 /* there's room in a register */
2276 regval = extract_unsigned_integer (val, argreg_size);
2277 write_register (int_argreg, regval);
2278 }
2279 /* Store the value 8 bytes at a time. This means that
2280 things larger than 8 bytes may go partly in registers
2281 and partly on the stack. FIXME: argreg is incremented
2282 before we use its size. */
2283 len -= argreg_size;
2284 val += argreg_size;
2285 int_argreg++;
2286 }
2287 }
2288 else
2289 {
2290 val = (char *) VALUE_CONTENTS (args[argnum]);
2291 if (len == 4)
2292 {
2293 /* Where is it going to be stored? */
2294 while (fp_args[float_arg_index])
2295 float_arg_index ++;
2296
2297 /* Now float_argreg points to the register where it
2298 should be stored. Are we still within the allowed
2299 register set? */
2300 if (float_arg_index <= tdep->FLOAT_ARGLAST_REGNUM)
2301 {
2302 /* Goes in FR0...FR11 */
2303 deprecated_write_register_gen (FP0_REGNUM + float_arg_index,
2304 val);
2305 fp_args[float_arg_index] = 1;
2306 /* Skip the corresponding general argument register. */
2307 int_argreg ++;
2308 }
2309 else
2310 ;
2311 /* Store it as the integers, 8 bytes at the time, if
2312 necessary spilling on the stack. */
2313
2314 }
2315 else if (len == 8)
2316 {
2317 /* Where is it going to be stored? */
2318 while (fp_args[double_arg_index])
2319 double_arg_index += 2;
2320 /* Now double_argreg points to the register
2321 where it should be stored.
2322 Are we still within the allowed register set? */
2323 if (double_arg_index < tdep->FLOAT_ARGLAST_REGNUM)
2324 {
2325 /* Goes in DR0...DR10 */
2326 /* The numbering of the DRi registers is consecutive,
2327 i.e. includes odd numbers. */
2328 int double_register_offset = double_arg_index / 2;
2329 int regnum = tdep->DR0_REGNUM +
2330 double_register_offset;
2331 #if 0
2332 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
2333 {
2334 memset (valbuf_tmp, 0, sizeof (valbuf_tmp));
2335 DEPRECATED_REGISTER_CONVERT_TO_VIRTUAL (regnum,
2336 type, val,
2337 valbuf_tmp);
2338 val = valbuf_tmp;
2339 }
2340 #endif
2341 /* Note: must use write_register_gen here instead
2342 of regcache_raw_write, because
2343 regcache_raw_write works only for real
2344 registers, not pseudo. write_register_gen will
2345 call the gdbarch function to do register
2346 writes, and that will properly know how to deal
2347 with pseudoregs. */
2348 deprecated_write_register_gen (regnum, val);
2349 fp_args[double_arg_index] = 1;
2350 fp_args[double_arg_index + 1] = 1;
2351 /* Skip the corresponding general argument register. */
2352 int_argreg ++;
2353 }
2354 else
2355 ;
2356 /* Store it as the integers, 8 bytes at the time, if
2357 necessary spilling on the stack. */
2358 }
2359 }
2360 }
2361 return sp;
2362 }
2363
2364 /* Function: push_return_address (pc)
2365 Set up the return address for the inferior function call.
2366 Needed for targets where we don't actually execute a JSR/BSR instruction */
2367
2368 static CORE_ADDR
2369 sh64_push_return_address (CORE_ADDR pc, CORE_ADDR sp)
2370 {
2371 write_register (gdbarch_tdep (current_gdbarch)->PR_REGNUM,
2372 CALL_DUMMY_ADDRESS ());
2373 return sp;
2374 }
2375
2376 /* Function: fix_call_dummy
2377 Poke the callee function's address into the destination part of
2378 the CALL_DUMMY. The address is actually stored in a data word
2379 following the actualy CALL_DUMMY instructions, which will load
2380 it into a register using PC-relative addressing. This function
2381 expects the CALL_DUMMY to look like this:
2382
2383 mov.w @(2,PC), R8
2384 jsr @R8
2385 nop
2386 trap
2387 <destination>
2388 */
2389
2390 #if 0
2391 void
2392 sh_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, int nargs,
2393 struct value **args, struct type *type, int gcc_p)
2394 {
2395 *(unsigned long *) (dummy + 8) = fun;
2396 }
2397 #endif
2398
2399 /* Find a function's return value in the appropriate registers (in
2400 regbuf), and copy it into valbuf. Extract from an array REGBUF
2401 containing the (raw) register state a function return value of type
2402 TYPE, and copy that, in virtual format, into VALBUF. */
2403 static void
2404 sh_default_extract_return_value (struct type *type, struct regcache *regcache,
2405 void *valbuf)
2406 {
2407 int len = TYPE_LENGTH (type);
2408 int return_register = R0_REGNUM;
2409 int offset;
2410
2411 if (len <= 4)
2412 {
2413 ULONGEST c;
2414
2415 regcache_cooked_read_unsigned (regcache, R0_REGNUM, &c);
2416 store_unsigned_integer (valbuf, len, c);
2417 }
2418 else if (len == 8)
2419 {
2420 int i, regnum = R0_REGNUM;
2421 for (i = 0; i < len; i += 4)
2422 regcache_raw_read (regcache, regnum++, (char *)valbuf + i);
2423 }
2424 else
2425 error ("bad size for return value");
2426 }
2427
2428 static void
2429 sh3e_sh4_extract_return_value (struct type *type, struct regcache *regcache,
2430 void *valbuf)
2431 {
2432 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2433 {
2434 int len = TYPE_LENGTH (type);
2435 int i, regnum = FP0_REGNUM;
2436 for (i = 0; i < len; i += 4)
2437 regcache_raw_read (regcache, regnum++, (char *)valbuf + i);
2438 }
2439 else
2440 sh_default_extract_return_value (type, regcache, valbuf);
2441 }
2442
2443 static void
2444 sh64_extract_return_value (struct type *type, char *regbuf, char *valbuf)
2445 {
2446 int offset;
2447 int return_register;
2448 int len = TYPE_LENGTH (type);
2449 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2450
2451 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2452 {
2453 if (len == 4)
2454 {
2455 /* Return value stored in FP0_REGNUM */
2456 return_register = FP0_REGNUM;
2457 offset = REGISTER_BYTE (return_register);
2458 memcpy (valbuf, (char *) regbuf + offset, len);
2459 }
2460 else if (len == 8)
2461 {
2462 /* return value stored in DR0_REGNUM */
2463 DOUBLEST val;
2464
2465 return_register = tdep->DR0_REGNUM;
2466 offset = REGISTER_BYTE (return_register);
2467
2468 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
2469 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
2470 (char *) regbuf + offset, &val);
2471 else
2472 floatformat_to_doublest (&floatformat_ieee_double_big,
2473 (char *) regbuf + offset, &val);
2474 deprecated_store_floating (valbuf, len, val);
2475 }
2476 }
2477 else
2478 {
2479 if (len <= 8)
2480 {
2481 /* Result is in register 2. If smaller than 8 bytes, it is padded
2482 at the most significant end. */
2483 return_register = tdep->RETURN_REGNUM;
2484 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2485 offset = REGISTER_BYTE (return_register) +
2486 REGISTER_RAW_SIZE (return_register) - len;
2487 else
2488 offset = REGISTER_BYTE (return_register);
2489 memcpy (valbuf, (char *) regbuf + offset, len);
2490 }
2491 else
2492 error ("bad size for return value");
2493 }
2494 }
2495
2496 /* Write into appropriate registers a function return value
2497 of type TYPE, given in virtual format.
2498 If the architecture is sh4 or sh3e, store a function's return value
2499 in the R0 general register or in the FP0 floating point register,
2500 depending on the type of the return value. In all the other cases
2501 the result is stored in r0, left-justified. */
2502 static void
2503 sh_default_store_return_value (struct type *type, struct regcache *regcache,
2504 const void *valbuf)
2505 {
2506 ULONGEST val;
2507 int len = TYPE_LENGTH (type);
2508
2509 if (len <= 4)
2510 {
2511 val = extract_unsigned_integer (valbuf, len);
2512 regcache_cooked_write_unsigned (regcache, R0_REGNUM, val);
2513 }
2514 else
2515 {
2516 int i, regnum = R0_REGNUM;
2517 for (i = 0; i < len; i += 4)
2518 regcache_raw_write (regcache, regnum++, (char *)valbuf + i);
2519 }
2520 }
2521
2522 static void
2523 sh3e_sh4_store_return_value (struct type *type, struct regcache *regcache,
2524 const void *valbuf)
2525 {
2526 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2527 {
2528 int len = TYPE_LENGTH (type);
2529 int i, regnum = FP0_REGNUM;
2530 for (i = 0; i < len; i += 4)
2531 regcache_raw_write (regcache, regnum++, (char *)valbuf + i);
2532 }
2533 else
2534 sh_default_store_return_value (type, regcache, valbuf);
2535 }
2536
2537 static void
2538 sh64_store_return_value (struct type *type, char *valbuf)
2539 {
2540 char buf[64]; /* more than enough... */
2541 int len = TYPE_LENGTH (type);
2542
2543 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2544 {
2545 if (len == 4)
2546 {
2547 /* Return value stored in FP0_REGNUM */
2548 deprecated_write_register_gen (FP0_REGNUM, valbuf);
2549 }
2550 if (len == 8)
2551 {
2552 /* return value stored in DR0_REGNUM */
2553 /* FIXME: Implement */
2554 }
2555 }
2556 else
2557 {
2558 int return_register = gdbarch_tdep (current_gdbarch)->RETURN_REGNUM;
2559 int offset = 0;
2560
2561 if (len <= REGISTER_RAW_SIZE (return_register))
2562 {
2563 /* Pad with zeros. */
2564 memset (buf, 0, REGISTER_RAW_SIZE (return_register));
2565 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
2566 offset = 0; /*REGISTER_RAW_SIZE (return_register) - len;*/
2567 else
2568 offset = REGISTER_RAW_SIZE (return_register) - len;
2569
2570 memcpy (buf + offset, valbuf, len);
2571 deprecated_write_register_gen (return_register, buf);
2572 }
2573 else
2574 deprecated_write_register_gen (return_register, valbuf);
2575 }
2576 }
2577
2578 /* Print the registers in a form similar to the E7000 */
2579
2580 static void
2581 sh_generic_show_regs (void)
2582 {
2583 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2584
2585 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2586 paddr (read_register (PC_REGNUM)),
2587 (long) read_register (tdep->SR_REGNUM),
2588 (long) read_register (tdep->PR_REGNUM),
2589 (long) read_register (MACH_REGNUM),
2590 (long) read_register (MACL_REGNUM));
2591
2592 printf_filtered ("GBR=%08lx VBR=%08lx",
2593 (long) read_register (GBR_REGNUM),
2594 (long) read_register (VBR_REGNUM));
2595
2596 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2597 (long) read_register (0),
2598 (long) read_register (1),
2599 (long) read_register (2),
2600 (long) read_register (3),
2601 (long) read_register (4),
2602 (long) read_register (5),
2603 (long) read_register (6),
2604 (long) read_register (7));
2605 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2606 (long) read_register (8),
2607 (long) read_register (9),
2608 (long) read_register (10),
2609 (long) read_register (11),
2610 (long) read_register (12),
2611 (long) read_register (13),
2612 (long) read_register (14),
2613 (long) read_register (15));
2614 }
2615
2616 static void
2617 sh3_show_regs (void)
2618 {
2619 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2620
2621 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2622 paddr (read_register (PC_REGNUM)),
2623 (long) read_register (tdep->SR_REGNUM),
2624 (long) read_register (tdep->PR_REGNUM),
2625 (long) read_register (MACH_REGNUM),
2626 (long) read_register (MACL_REGNUM));
2627
2628 printf_filtered ("GBR=%08lx VBR=%08lx",
2629 (long) read_register (GBR_REGNUM),
2630 (long) read_register (VBR_REGNUM));
2631 printf_filtered (" SSR=%08lx SPC=%08lx",
2632 (long) read_register (tdep->SSR_REGNUM),
2633 (long) read_register (tdep->SPC_REGNUM));
2634
2635 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2636 (long) read_register (0),
2637 (long) read_register (1),
2638 (long) read_register (2),
2639 (long) read_register (3),
2640 (long) read_register (4),
2641 (long) read_register (5),
2642 (long) read_register (6),
2643 (long) read_register (7));
2644 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2645 (long) read_register (8),
2646 (long) read_register (9),
2647 (long) read_register (10),
2648 (long) read_register (11),
2649 (long) read_register (12),
2650 (long) read_register (13),
2651 (long) read_register (14),
2652 (long) read_register (15));
2653 }
2654
2655
2656 static void
2657 sh2e_show_regs (void)
2658 {
2659 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2660 paddr (read_register (PC_REGNUM)),
2661 (long) read_register (SR_REGNUM),
2662 (long) read_register (PR_REGNUM),
2663 (long) read_register (MACH_REGNUM),
2664 (long) read_register (MACL_REGNUM));
2665
2666 printf_filtered ("GBR=%08lx VBR=%08lx",
2667 (long) read_register (GBR_REGNUM),
2668 (long) read_register (VBR_REGNUM));
2669 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
2670 (long) read_register (gdbarch_tdep (current_gdbarch)->FPUL_REGNUM),
2671 (long) read_register (gdbarch_tdep (current_gdbarch)->FPSCR_REGNUM));
2672
2673 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2674 (long) read_register (0),
2675 (long) read_register (1),
2676 (long) read_register (2),
2677 (long) read_register (3),
2678 (long) read_register (4),
2679 (long) read_register (5),
2680 (long) read_register (6),
2681 (long) read_register (7));
2682 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2683 (long) read_register (8),
2684 (long) read_register (9),
2685 (long) read_register (10),
2686 (long) read_register (11),
2687 (long) read_register (12),
2688 (long) read_register (13),
2689 (long) read_register (14),
2690 (long) read_register (15));
2691
2692 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2693 (long) read_register (FP0_REGNUM + 0),
2694 (long) read_register (FP0_REGNUM + 1),
2695 (long) read_register (FP0_REGNUM + 2),
2696 (long) read_register (FP0_REGNUM + 3),
2697 (long) read_register (FP0_REGNUM + 4),
2698 (long) read_register (FP0_REGNUM + 5),
2699 (long) read_register (FP0_REGNUM + 6),
2700 (long) read_register (FP0_REGNUM + 7));
2701 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2702 (long) read_register (FP0_REGNUM + 8),
2703 (long) read_register (FP0_REGNUM + 9),
2704 (long) read_register (FP0_REGNUM + 10),
2705 (long) read_register (FP0_REGNUM + 11),
2706 (long) read_register (FP0_REGNUM + 12),
2707 (long) read_register (FP0_REGNUM + 13),
2708 (long) read_register (FP0_REGNUM + 14),
2709 (long) read_register (FP0_REGNUM + 15));
2710 }
2711
2712 static void
2713 sh3e_show_regs (void)
2714 {
2715 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2716
2717 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2718 paddr (read_register (PC_REGNUM)),
2719 (long) read_register (tdep->SR_REGNUM),
2720 (long) read_register (tdep->PR_REGNUM),
2721 (long) read_register (MACH_REGNUM),
2722 (long) read_register (MACL_REGNUM));
2723
2724 printf_filtered ("GBR=%08lx VBR=%08lx",
2725 (long) read_register (GBR_REGNUM),
2726 (long) read_register (VBR_REGNUM));
2727 printf_filtered (" SSR=%08lx SPC=%08lx",
2728 (long) read_register (tdep->SSR_REGNUM),
2729 (long) read_register (tdep->SPC_REGNUM));
2730 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
2731 (long) read_register (tdep->FPUL_REGNUM),
2732 (long) read_register (tdep->FPSCR_REGNUM));
2733
2734 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2735 (long) read_register (0),
2736 (long) read_register (1),
2737 (long) read_register (2),
2738 (long) read_register (3),
2739 (long) read_register (4),
2740 (long) read_register (5),
2741 (long) read_register (6),
2742 (long) read_register (7));
2743 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2744 (long) read_register (8),
2745 (long) read_register (9),
2746 (long) read_register (10),
2747 (long) read_register (11),
2748 (long) read_register (12),
2749 (long) read_register (13),
2750 (long) read_register (14),
2751 (long) read_register (15));
2752
2753 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2754 (long) read_register (FP0_REGNUM + 0),
2755 (long) read_register (FP0_REGNUM + 1),
2756 (long) read_register (FP0_REGNUM + 2),
2757 (long) read_register (FP0_REGNUM + 3),
2758 (long) read_register (FP0_REGNUM + 4),
2759 (long) read_register (FP0_REGNUM + 5),
2760 (long) read_register (FP0_REGNUM + 6),
2761 (long) read_register (FP0_REGNUM + 7));
2762 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2763 (long) read_register (FP0_REGNUM + 8),
2764 (long) read_register (FP0_REGNUM + 9),
2765 (long) read_register (FP0_REGNUM + 10),
2766 (long) read_register (FP0_REGNUM + 11),
2767 (long) read_register (FP0_REGNUM + 12),
2768 (long) read_register (FP0_REGNUM + 13),
2769 (long) read_register (FP0_REGNUM + 14),
2770 (long) read_register (FP0_REGNUM + 15));
2771 }
2772
2773 static void
2774 sh3_dsp_show_regs (void)
2775 {
2776 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2777
2778 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2779 paddr (read_register (PC_REGNUM)),
2780 (long) read_register (tdep->SR_REGNUM),
2781 (long) read_register (tdep->PR_REGNUM),
2782 (long) read_register (MACH_REGNUM),
2783 (long) read_register (MACL_REGNUM));
2784
2785 printf_filtered ("GBR=%08lx VBR=%08lx",
2786 (long) read_register (GBR_REGNUM),
2787 (long) read_register (VBR_REGNUM));
2788
2789 printf_filtered (" SSR=%08lx SPC=%08lx",
2790 (long) read_register (tdep->SSR_REGNUM),
2791 (long) read_register (tdep->SPC_REGNUM));
2792
2793 printf_filtered (" DSR=%08lx",
2794 (long) read_register (tdep->DSR_REGNUM));
2795
2796 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2797 (long) read_register (0),
2798 (long) read_register (1),
2799 (long) read_register (2),
2800 (long) read_register (3),
2801 (long) read_register (4),
2802 (long) read_register (5),
2803 (long) read_register (6),
2804 (long) read_register (7));
2805 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2806 (long) read_register (8),
2807 (long) read_register (9),
2808 (long) read_register (10),
2809 (long) read_register (11),
2810 (long) read_register (12),
2811 (long) read_register (13),
2812 (long) read_register (14),
2813 (long) read_register (15));
2814
2815 printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
2816 (long) read_register (tdep->A0G_REGNUM) & 0xff,
2817 (long) read_register (tdep->A0_REGNUM),
2818 (long) read_register (tdep->M0_REGNUM),
2819 (long) read_register (tdep->X0_REGNUM),
2820 (long) read_register (tdep->Y0_REGNUM),
2821 (long) read_register (tdep->RS_REGNUM),
2822 (long) read_register (tdep->MOD_REGNUM));
2823 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
2824 (long) read_register (tdep->A1G_REGNUM) & 0xff,
2825 (long) read_register (tdep->A1_REGNUM),
2826 (long) read_register (tdep->M1_REGNUM),
2827 (long) read_register (tdep->X1_REGNUM),
2828 (long) read_register (tdep->Y1_REGNUM),
2829 (long) read_register (tdep->RE_REGNUM));
2830 }
2831
2832 static void
2833 sh4_show_regs (void)
2834 {
2835 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2836
2837 int pr = read_register (tdep->FPSCR_REGNUM) & 0x80000;
2838 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2839 paddr (read_register (PC_REGNUM)),
2840 (long) read_register (tdep->SR_REGNUM),
2841 (long) read_register (tdep->PR_REGNUM),
2842 (long) read_register (MACH_REGNUM),
2843 (long) read_register (MACL_REGNUM));
2844
2845 printf_filtered ("GBR=%08lx VBR=%08lx",
2846 (long) read_register (GBR_REGNUM),
2847 (long) read_register (VBR_REGNUM));
2848 printf_filtered (" SSR=%08lx SPC=%08lx",
2849 (long) read_register (tdep->SSR_REGNUM),
2850 (long) read_register (tdep->SPC_REGNUM));
2851 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
2852 (long) read_register (tdep->FPUL_REGNUM),
2853 (long) read_register (tdep->FPSCR_REGNUM));
2854
2855 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2856 (long) read_register (0),
2857 (long) read_register (1),
2858 (long) read_register (2),
2859 (long) read_register (3),
2860 (long) read_register (4),
2861 (long) read_register (5),
2862 (long) read_register (6),
2863 (long) read_register (7));
2864 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2865 (long) read_register (8),
2866 (long) read_register (9),
2867 (long) read_register (10),
2868 (long) read_register (11),
2869 (long) read_register (12),
2870 (long) read_register (13),
2871 (long) read_register (14),
2872 (long) read_register (15));
2873
2874 printf_filtered ((pr
2875 ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
2876 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2877 (long) read_register (FP0_REGNUM + 0),
2878 (long) read_register (FP0_REGNUM + 1),
2879 (long) read_register (FP0_REGNUM + 2),
2880 (long) read_register (FP0_REGNUM + 3),
2881 (long) read_register (FP0_REGNUM + 4),
2882 (long) read_register (FP0_REGNUM + 5),
2883 (long) read_register (FP0_REGNUM + 6),
2884 (long) read_register (FP0_REGNUM + 7));
2885 printf_filtered ((pr
2886 ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
2887 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2888 (long) read_register (FP0_REGNUM + 8),
2889 (long) read_register (FP0_REGNUM + 9),
2890 (long) read_register (FP0_REGNUM + 10),
2891 (long) read_register (FP0_REGNUM + 11),
2892 (long) read_register (FP0_REGNUM + 12),
2893 (long) read_register (FP0_REGNUM + 13),
2894 (long) read_register (FP0_REGNUM + 14),
2895 (long) read_register (FP0_REGNUM + 15));
2896 }
2897
2898 static void
2899 sh_dsp_show_regs (void)
2900 {
2901 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2902
2903 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2904 paddr (read_register (PC_REGNUM)),
2905 (long) read_register (tdep->SR_REGNUM),
2906 (long) read_register (tdep->PR_REGNUM),
2907 (long) read_register (MACH_REGNUM),
2908 (long) read_register (MACL_REGNUM));
2909
2910 printf_filtered ("GBR=%08lx VBR=%08lx",
2911 (long) read_register (GBR_REGNUM),
2912 (long) read_register (VBR_REGNUM));
2913
2914 printf_filtered (" DSR=%08lx",
2915 (long) read_register (tdep->DSR_REGNUM));
2916
2917 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2918 (long) read_register (0),
2919 (long) read_register (1),
2920 (long) read_register (2),
2921 (long) read_register (3),
2922 (long) read_register (4),
2923 (long) read_register (5),
2924 (long) read_register (6),
2925 (long) read_register (7));
2926 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2927 (long) read_register (8),
2928 (long) read_register (9),
2929 (long) read_register (10),
2930 (long) read_register (11),
2931 (long) read_register (12),
2932 (long) read_register (13),
2933 (long) read_register (14),
2934 (long) read_register (15));
2935
2936 printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
2937 (long) read_register (tdep->A0G_REGNUM) & 0xff,
2938 (long) read_register (tdep->A0_REGNUM),
2939 (long) read_register (tdep->M0_REGNUM),
2940 (long) read_register (tdep->X0_REGNUM),
2941 (long) read_register (tdep->Y0_REGNUM),
2942 (long) read_register (tdep->RS_REGNUM),
2943 (long) read_register (tdep->MOD_REGNUM));
2944 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
2945 (long) read_register (tdep->A1G_REGNUM) & 0xff,
2946 (long) read_register (tdep->A1_REGNUM),
2947 (long) read_register (tdep->M1_REGNUM),
2948 (long) read_register (tdep->X1_REGNUM),
2949 (long) read_register (tdep->Y1_REGNUM),
2950 (long) read_register (tdep->RE_REGNUM));
2951 }
2952
2953 static void
2954 sh64_show_media_regs (void)
2955 {
2956 int i;
2957 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2958
2959 printf_filtered ("PC=%s SR=%016llx \n",
2960 paddr (read_register (PC_REGNUM)),
2961 (long long) read_register (tdep->SR_REGNUM));
2962
2963 printf_filtered ("SSR=%016llx SPC=%016llx \n",
2964 (long long) read_register (tdep->SSR_REGNUM),
2965 (long long) read_register (tdep->SPC_REGNUM));
2966 printf_filtered ("FPSCR=%016lx\n ",
2967 (long) read_register (tdep->FPSCR_REGNUM));
2968
2969 for (i = 0; i < 64; i = i + 4)
2970 printf_filtered ("\nR%d-R%d %016llx %016llx %016llx %016llx\n",
2971 i, i + 3,
2972 (long long) read_register (i + 0),
2973 (long long) read_register (i + 1),
2974 (long long) read_register (i + 2),
2975 (long long) read_register (i + 3));
2976
2977 printf_filtered ("\n");
2978
2979 for (i = 0; i < 64; i = i + 8)
2980 printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2981 i, i + 7,
2982 (long) read_register (FP0_REGNUM + i + 0),
2983 (long) read_register (FP0_REGNUM + i + 1),
2984 (long) read_register (FP0_REGNUM + i + 2),
2985 (long) read_register (FP0_REGNUM + i + 3),
2986 (long) read_register (FP0_REGNUM + i + 4),
2987 (long) read_register (FP0_REGNUM + i + 5),
2988 (long) read_register (FP0_REGNUM + i + 6),
2989 (long) read_register (FP0_REGNUM + i + 7));
2990 }
2991
2992 static void
2993 sh64_show_compact_regs (void)
2994 {
2995 int i;
2996 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2997
2998 printf_filtered ("PC=%s \n",
2999 paddr (read_register (tdep->PC_C_REGNUM)));
3000
3001 printf_filtered ("GBR=%08lx MACH=%08lx MACL=%08lx PR=%08lx T=%08lx\n",
3002 (long) read_register (tdep->GBR_C_REGNUM),
3003 (long) read_register (tdep->MACH_C_REGNUM),
3004 (long) read_register (tdep->MACL_C_REGNUM),
3005 (long) read_register (tdep->PR_C_REGNUM),
3006 (long) read_register (tdep->T_C_REGNUM));
3007 printf_filtered ("FPSCR=%08lx FPUL=%08lx\n",
3008 (long) read_register (tdep->FPSCR_REGNUM),
3009 (long) read_register (tdep->FPUL_REGNUM));
3010
3011 for (i = 0; i < 16; i = i + 4)
3012 printf_filtered ("\nR%d-R%d %08lx %08lx %08lx %08lx\n",
3013 i, i + 3,
3014 (long) read_register (i + 0),
3015 (long) read_register (i + 1),
3016 (long) read_register (i + 2),
3017 (long) read_register (i + 3));
3018
3019 printf_filtered ("\n");
3020
3021 for (i = 0; i < 16; i = i + 8)
3022 printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
3023 i, i + 7,
3024 (long) read_register (FP0_REGNUM + i + 0),
3025 (long) read_register (FP0_REGNUM + i + 1),
3026 (long) read_register (FP0_REGNUM + i + 2),
3027 (long) read_register (FP0_REGNUM + i + 3),
3028 (long) read_register (FP0_REGNUM + i + 4),
3029 (long) read_register (FP0_REGNUM + i + 5),
3030 (long) read_register (FP0_REGNUM + i + 6),
3031 (long) read_register (FP0_REGNUM + i + 7));
3032 }
3033
3034 /*FIXME!!! This only shows the registers for shmedia, excluding the
3035 pseudo registers. */
3036 static void
3037 sh64_show_regs (void)
3038 {
3039 if (pc_is_isa32 (get_frame_pc (deprecated_selected_frame)))
3040 sh64_show_media_regs ();
3041 else
3042 sh64_show_compact_regs ();
3043 }
3044
3045 static void
3046 sh_show_regs_command (char *args, int from_tty)
3047 {
3048 if (sh_show_regs)
3049 (*sh_show_regs)();
3050 }
3051
3052 /* *INDENT-OFF* */
3053 /*
3054 SH MEDIA MODE (ISA 32)
3055 general registers (64-bit) 0-63
3056 0 r0, r1, r2, r3, r4, r5, r6, r7,
3057 64 r8, r9, r10, r11, r12, r13, r14, r15,
3058 128 r16, r17, r18, r19, r20, r21, r22, r23,
3059 192 r24, r25, r26, r27, r28, r29, r30, r31,
3060 256 r32, r33, r34, r35, r36, r37, r38, r39,
3061 320 r40, r41, r42, r43, r44, r45, r46, r47,
3062 384 r48, r49, r50, r51, r52, r53, r54, r55,
3063 448 r56, r57, r58, r59, r60, r61, r62, r63,
3064
3065 pc (64-bit) 64
3066 512 pc,
3067
3068 status reg., saved status reg., saved pc reg. (64-bit) 65-67
3069 520 sr, ssr, spc,
3070
3071 target registers (64-bit) 68-75
3072 544 tr0, tr1, tr2, tr3, tr4, tr5, tr6, tr7,
3073
3074 floating point state control register (32-bit) 76
3075 608 fpscr,
3076
3077 single precision floating point registers (32-bit) 77-140
3078 612 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7,
3079 644 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15,
3080 676 fr16, fr17, fr18, fr19, fr20, fr21, fr22, fr23,
3081 708 fr24, fr25, fr26, fr27, fr28, fr29, fr30, fr31,
3082 740 fr32, fr33, fr34, fr35, fr36, fr37, fr38, fr39,
3083 772 fr40, fr41, fr42, fr43, fr44, fr45, fr46, fr47,
3084 804 fr48, fr49, fr50, fr51, fr52, fr53, fr54, fr55,
3085 836 fr56, fr57, fr58, fr59, fr60, fr61, fr62, fr63,
3086
3087 TOTAL SPACE FOR REGISTERS: 868 bytes
3088
3089 From here on they are all pseudo registers: no memory allocated.
3090 REGISTER_BYTE returns the register byte for the base register.
3091
3092 double precision registers (pseudo) 141-172
3093 dr0, dr2, dr4, dr6, dr8, dr10, dr12, dr14,
3094 dr16, dr18, dr20, dr22, dr24, dr26, dr28, dr30,
3095 dr32, dr34, dr36, dr38, dr40, dr42, dr44, dr46,
3096 dr48, dr50, dr52, dr54, dr56, dr58, dr60, dr62,
3097
3098 floating point pairs (pseudo) 173-204
3099 fp0, fp2, fp4, fp6, fp8, fp10, fp12, fp14,
3100 fp16, fp18, fp20, fp22, fp24, fp26, fp28, fp30,
3101 fp32, fp34, fp36, fp38, fp40, fp42, fp44, fp46,
3102 fp48, fp50, fp52, fp54, fp56, fp58, fp60, fp62,
3103
3104 floating point vectors (4 floating point regs) (pseudo) 205-220
3105 fv0, fv4, fv8, fv12, fv16, fv20, fv24, fv28,
3106 fv32, fv36, fv40, fv44, fv48, fv52, fv56, fv60,
3107
3108 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
3109 r0_c, r1_c, r2_c, r3_c, r4_c, r5_c, r6_c, r7_c,
3110 r8_c, r9_c, r10_c, r11_c, r12_c, r13_c, r14_c, r15_c,
3111 pc_c,
3112 gbr_c, mach_c, macl_c, pr_c, t_c,
3113 fpscr_c, fpul_c,
3114 fr0_c, fr1_c, fr2_c, fr3_c, fr4_c, fr5_c, fr6_c, fr7_c,
3115 fr8_c, fr9_c, fr10_c, fr11_c, fr12_c, fr13_c, fr14_c, fr15_c
3116 dr0_c, dr2_c, dr4_c, dr6_c, dr8_c, dr10_c, dr12_c, dr14_c
3117 fv0_c, fv4_c, fv8_c, fv12_c
3118 */
3119 /* *INDENT-ON* */
3120 static int
3121 sh_sh64_register_byte (int reg_nr)
3122 {
3123 int base_regnum = -1;
3124 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3125
3126 /* If it is a pseudo register, get the number of the first floating
3127 point register that is part of it. */
3128 if (reg_nr >= tdep->DR0_REGNUM
3129 && reg_nr <= tdep->DR_LAST_REGNUM)
3130 base_regnum = dr_reg_base_num (reg_nr);
3131
3132 else if (reg_nr >= tdep->FPP0_REGNUM
3133 && reg_nr <= tdep->FPP_LAST_REGNUM)
3134 base_regnum = fpp_reg_base_num (reg_nr);
3135
3136 else if (reg_nr >= tdep->FV0_REGNUM
3137 && reg_nr <= tdep->FV_LAST_REGNUM)
3138 base_regnum = fv_reg_base_num (reg_nr);
3139
3140 /* sh compact pseudo register. FPSCR is a pathological case, need to
3141 treat it as special. */
3142 else if ((reg_nr >= tdep->R0_C_REGNUM
3143 && reg_nr <= tdep->FV_LAST_C_REGNUM)
3144 && reg_nr != tdep->FPSCR_C_REGNUM)
3145 base_regnum = sh64_compact_reg_base_num (reg_nr);
3146
3147 /* Now return the offset in bytes within the register cache. */
3148 /* sh media pseudo register, i.e. any of DR, FFP, FV registers. */
3149 if (reg_nr >= tdep->DR0_REGNUM
3150 && reg_nr <= tdep->FV_LAST_REGNUM)
3151 return (base_regnum - FP0_REGNUM + 1) * 4
3152 + (tdep->TR7_REGNUM + 1) * 8;
3153
3154 /* sh compact pseudo register: general register */
3155 if ((reg_nr >= tdep->R0_C_REGNUM
3156 && reg_nr <= tdep->R_LAST_C_REGNUM))
3157 return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3158 ? base_regnum * 8 + 4
3159 : base_regnum * 8);
3160
3161 /* sh compact pseudo register: */
3162 if (reg_nr == tdep->PC_C_REGNUM
3163 || reg_nr == tdep->GBR_C_REGNUM
3164 || reg_nr == tdep->MACL_C_REGNUM
3165 || reg_nr == tdep->PR_C_REGNUM)
3166 return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3167 ? base_regnum * 8 + 4
3168 : base_regnum * 8);
3169
3170 if (reg_nr == tdep->MACH_C_REGNUM)
3171 return base_regnum * 8;
3172
3173 if (reg_nr == tdep->T_C_REGNUM)
3174 return base_regnum * 8; /* FIXME??? how do we get bit 0? Do we have to? */
3175
3176 /* sh compact pseudo register: floating point register */
3177 else if (reg_nr >=tdep->FP0_C_REGNUM
3178 && reg_nr <= tdep->FV_LAST_C_REGNUM)
3179 return (base_regnum - FP0_REGNUM) * 4
3180 + (tdep->TR7_REGNUM + 1) * 8 + 4;
3181
3182 else if (reg_nr == tdep->FPSCR_C_REGNUM)
3183 /* This is complicated, for now return the beginning of the
3184 architectural FPSCR register. */
3185 return (tdep->TR7_REGNUM + 1) * 8;
3186
3187 else if (reg_nr == tdep->FPUL_C_REGNUM)
3188 return ((base_regnum - FP0_REGNUM) * 4 +
3189 (tdep->TR7_REGNUM + 1) * 8 + 4);
3190
3191 /* It is not a pseudo register. */
3192 /* It is a 64 bit register. */
3193 else if (reg_nr <= tdep->TR7_REGNUM)
3194 return reg_nr * 8;
3195
3196 /* It is a 32 bit register. */
3197 else
3198 if (reg_nr == tdep->FPSCR_REGNUM)
3199 return (tdep->FPSCR_REGNUM * 8);
3200
3201 /* It is floating point 32-bit register */
3202 else
3203 return ((tdep->TR7_REGNUM + 1) * 8
3204 + (reg_nr - FP0_REGNUM + 1) * 4);
3205 }
3206
3207 static int
3208 sh_sh64_register_raw_size (int reg_nr)
3209 {
3210 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3211
3212 if ((reg_nr >= tdep->DR0_REGNUM
3213 && reg_nr <= tdep->DR_LAST_REGNUM)
3214 || (reg_nr >= tdep->FPP0_REGNUM
3215 && reg_nr <= tdep->FPP_LAST_REGNUM)
3216 || (reg_nr >= tdep->DR0_C_REGNUM
3217 && reg_nr <= tdep->DR_LAST_C_REGNUM)
3218 || (reg_nr <= tdep->TR7_REGNUM))
3219 return 8;
3220
3221 else if ((reg_nr >= tdep->FV0_REGNUM
3222 && reg_nr <= tdep->FV_LAST_REGNUM)
3223 || (reg_nr >= tdep->FV0_C_REGNUM
3224 && reg_nr <= tdep->FV_LAST_C_REGNUM))
3225 return 16;
3226
3227 else /* this covers also the 32-bit SH compact registers. */
3228 return 4;
3229 }
3230
3231 /* ??????? FIXME */
3232 static int
3233 sh_sh64_register_virtual_size (int reg_nr)
3234 {
3235 if (reg_nr >= FP0_REGNUM
3236 && reg_nr <= gdbarch_tdep (current_gdbarch)->FP_LAST_REGNUM)
3237 return 4;
3238 else
3239 return 8;
3240 }
3241
3242 /* Return the GDB type object for the "standard" data type
3243 of data in register N. */
3244 static struct type *
3245 sh_sh3e_register_type (struct gdbarch *gdbarch, int reg_nr)
3246 {
3247 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3248
3249 if ((reg_nr >= FP0_REGNUM
3250 && (reg_nr <= tdep->FP_LAST_REGNUM))
3251 || (reg_nr == tdep->FPUL_REGNUM))
3252 return builtin_type_float;
3253 else
3254 return builtin_type_int;
3255 }
3256
3257 static struct type *
3258 sh_sh4_build_float_register_type (int high)
3259 {
3260 struct type *temp;
3261
3262 temp = create_range_type (NULL, builtin_type_int, 0, high);
3263 return create_array_type (NULL, builtin_type_float, temp);
3264 }
3265
3266 static struct type *
3267 sh_sh4_register_type (struct gdbarch *gdbarch, int reg_nr)
3268 {
3269 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3270
3271 if ((reg_nr >= FP0_REGNUM
3272 && (reg_nr <= tdep->FP_LAST_REGNUM))
3273 || (reg_nr == tdep->FPUL_REGNUM))
3274 return builtin_type_float;
3275 else if (reg_nr >= tdep->DR0_REGNUM
3276 && reg_nr <= tdep->DR_LAST_REGNUM)
3277 return builtin_type_double;
3278 else if (reg_nr >= tdep->FV0_REGNUM
3279 && reg_nr <= tdep->FV_LAST_REGNUM)
3280 return sh_sh4_build_float_register_type (3);
3281 else
3282 return builtin_type_int;
3283 }
3284
3285 static struct type *
3286 sh_sh64_register_virtual_type (int reg_nr)
3287 {
3288 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3289
3290 if ((reg_nr >= FP0_REGNUM
3291 && reg_nr <= tdep->FP_LAST_REGNUM)
3292 || (reg_nr >= tdep->FP0_C_REGNUM
3293 && reg_nr <= tdep->FP_LAST_C_REGNUM))
3294 return builtin_type_float;
3295 else if ((reg_nr >= tdep->DR0_REGNUM
3296 && reg_nr <= tdep->DR_LAST_REGNUM)
3297 || (reg_nr >= tdep->DR0_C_REGNUM
3298 && reg_nr <= tdep->DR_LAST_C_REGNUM))
3299 return builtin_type_double;
3300 else if (reg_nr >= tdep->FPP0_REGNUM
3301 && reg_nr <= tdep->FPP_LAST_REGNUM)
3302 return sh_sh4_build_float_register_type (1);
3303 else if ((reg_nr >= tdep->FV0_REGNUM
3304 && reg_nr <= tdep->FV_LAST_REGNUM)
3305 ||(reg_nr >= tdep->FV0_C_REGNUM
3306 && reg_nr <= tdep->FV_LAST_C_REGNUM))
3307 return sh_sh4_build_float_register_type (3);
3308 else if (reg_nr == tdep->FPSCR_REGNUM)
3309 return builtin_type_int;
3310 else if (reg_nr >= tdep->R0_C_REGNUM
3311 && reg_nr < tdep->FP0_C_REGNUM)
3312 return builtin_type_int;
3313 else
3314 return builtin_type_long_long;
3315 }
3316
3317 static struct type *
3318 sh_default_register_type (struct gdbarch *gdbarch, int reg_nr)
3319 {
3320 return builtin_type_int;
3321 }
3322
3323 /* On the sh4, the DRi pseudo registers are problematic if the target
3324 is little endian. When the user writes one of those registers, for
3325 instance with 'ser var $dr0=1', we want the double to be stored
3326 like this:
3327 fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
3328 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
3329
3330 This corresponds to little endian byte order & big endian word
3331 order. However if we let gdb write the register w/o conversion, it
3332 will write fr0 and fr1 this way:
3333 fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
3334 fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
3335 because it will consider fr0 and fr1 as a single LE stretch of memory.
3336
3337 To achieve what we want we must force gdb to store things in
3338 floatformat_ieee_double_littlebyte_bigword (which is defined in
3339 include/floatformat.h and libiberty/floatformat.c.
3340
3341 In case the target is big endian, there is no problem, the
3342 raw bytes will look like:
3343 fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
3344 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
3345
3346 The other pseudo registers (the FVs) also don't pose a problem
3347 because they are stored as 4 individual FP elements. */
3348
3349 static void
3350 sh_sh4_register_convert_to_virtual (int regnum, struct type *type,
3351 char *from, char *to)
3352 {
3353 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3354
3355 if (regnum >= tdep->DR0_REGNUM
3356 && regnum <= tdep->DR_LAST_REGNUM)
3357 {
3358 DOUBLEST val;
3359 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, from, &val);
3360 store_typed_floating (to, type, val);
3361 }
3362 else
3363 error ("sh_register_convert_to_virtual called with non DR register number");
3364 }
3365
3366 static void
3367 sh_sh64_register_convert_to_virtual (int regnum, struct type *type,
3368 char *from, char *to)
3369 {
3370 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3371
3372 if (TARGET_BYTE_ORDER != BFD_ENDIAN_LITTLE)
3373 {
3374 /* It is a no-op. */
3375 memcpy (to, from, REGISTER_RAW_SIZE (regnum));
3376 return;
3377 }
3378
3379 if ((regnum >= tdep->DR0_REGNUM
3380 && regnum <= tdep->DR_LAST_REGNUM)
3381 || (regnum >= tdep->DR0_C_REGNUM
3382 && regnum <= tdep->DR_LAST_C_REGNUM))
3383 {
3384 DOUBLEST val;
3385 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, from, &val);
3386 deprecated_store_floating(to, TYPE_LENGTH(type), val);
3387 }
3388 else
3389 error("sh_register_convert_to_virtual called with non DR register number");
3390 }
3391
3392 static void
3393 sh_sh4_register_convert_to_raw (struct type *type, int regnum,
3394 const void *from, void *to)
3395 {
3396 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3397
3398 if (regnum >= tdep->DR0_REGNUM
3399 && regnum <= tdep->DR_LAST_REGNUM)
3400 {
3401 DOUBLEST val = extract_typed_floating (from, type);
3402 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword, &val, to);
3403 }
3404 else
3405 error("sh_register_convert_to_raw called with non DR register number");
3406 }
3407
3408 static void
3409 sh_sh64_register_convert_to_raw (struct type *type, int regnum,
3410 const void *from, void *to)
3411 {
3412 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3413
3414 if (TARGET_BYTE_ORDER != BFD_ENDIAN_LITTLE)
3415 {
3416 /* It is a no-op. */
3417 memcpy (to, from, REGISTER_RAW_SIZE (regnum));
3418 return;
3419 }
3420
3421 if ((regnum >= tdep->DR0_REGNUM
3422 && regnum <= tdep->DR_LAST_REGNUM)
3423 || (regnum >= tdep->DR0_C_REGNUM
3424 && regnum <= tdep->DR_LAST_C_REGNUM))
3425 {
3426 DOUBLEST val = deprecated_extract_floating (from, TYPE_LENGTH(type));
3427 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword, &val, to);
3428 }
3429 else
3430 error("sh_register_convert_to_raw called with non DR register number");
3431 }
3432
3433 static void
3434 sh_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
3435 int reg_nr, void *buffer)
3436 {
3437 int base_regnum, portion;
3438 char temp_buffer[MAX_REGISTER_SIZE];
3439 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3440
3441 if (reg_nr >= tdep->DR0_REGNUM
3442 && reg_nr <= tdep->DR_LAST_REGNUM)
3443 {
3444 base_regnum = dr_reg_base_num (reg_nr);
3445
3446 /* Build the value in the provided buffer. */
3447 /* Read the real regs for which this one is an alias. */
3448 for (portion = 0; portion < 2; portion++)
3449 regcache_raw_read (regcache, base_regnum + portion,
3450 (temp_buffer
3451 + register_size (gdbarch, base_regnum) * portion));
3452 /* We must pay attention to the endiannes. */
3453 sh_sh4_register_convert_to_virtual (reg_nr,
3454 gdbarch_register_type (gdbarch, reg_nr),
3455 temp_buffer, buffer);
3456 }
3457 else if (reg_nr >= tdep->FV0_REGNUM
3458 && reg_nr <= tdep->FV_LAST_REGNUM)
3459 {
3460 base_regnum = fv_reg_base_num (reg_nr);
3461
3462 /* Read the real regs for which this one is an alias. */
3463 for (portion = 0; portion < 4; portion++)
3464 regcache_raw_read (regcache, base_regnum + portion,
3465 ((char *) buffer
3466 + register_size (gdbarch, base_regnum) * portion));
3467 }
3468 }
3469
3470 static void
3471 sh64_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
3472 int reg_nr, void *buffer)
3473 {
3474 int base_regnum;
3475 int portion;
3476 int offset = 0;
3477 char temp_buffer[MAX_REGISTER_SIZE];
3478 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3479
3480 if (reg_nr >= tdep->DR0_REGNUM
3481 && reg_nr <= tdep->DR_LAST_REGNUM)
3482 {
3483 base_regnum = dr_reg_base_num (reg_nr);
3484
3485 /* Build the value in the provided buffer. */
3486 /* DR regs are double precision registers obtained by
3487 concatenating 2 single precision floating point registers. */
3488 for (portion = 0; portion < 2; portion++)
3489 regcache_raw_read (regcache, base_regnum + portion,
3490 (temp_buffer
3491 + REGISTER_RAW_SIZE (base_regnum) * portion));
3492
3493 /* We must pay attention to the endiannes. */
3494 sh_sh64_register_convert_to_virtual (reg_nr, REGISTER_VIRTUAL_TYPE (reg_nr),
3495 temp_buffer, buffer);
3496
3497 }
3498
3499 else if (reg_nr >= tdep->FPP0_REGNUM
3500 && reg_nr <= tdep->FPP_LAST_REGNUM)
3501 {
3502 base_regnum = fpp_reg_base_num (reg_nr);
3503
3504 /* Build the value in the provided buffer. */
3505 /* FPP regs are pairs of single precision registers obtained by
3506 concatenating 2 single precision floating point registers. */
3507 for (portion = 0; portion < 2; portion++)
3508 regcache_raw_read (regcache, base_regnum + portion,
3509 ((char *) buffer
3510 + REGISTER_RAW_SIZE (base_regnum) * portion));
3511 }
3512
3513 else if (reg_nr >= tdep->FV0_REGNUM
3514 && reg_nr <= tdep->FV_LAST_REGNUM)
3515 {
3516 base_regnum = fv_reg_base_num (reg_nr);
3517
3518 /* Build the value in the provided buffer. */
3519 /* FV regs are vectors of single precision registers obtained by
3520 concatenating 4 single precision floating point registers. */
3521 for (portion = 0; portion < 4; portion++)
3522 regcache_raw_read (regcache, base_regnum + portion,
3523 ((char *) buffer
3524 + REGISTER_RAW_SIZE (base_regnum) * portion));
3525 }
3526
3527 /* sh compact pseudo registers. 1-to-1 with a shmedia register */
3528 else if (reg_nr >= tdep->R0_C_REGNUM
3529 && reg_nr <= tdep->T_C_REGNUM)
3530 {
3531 base_regnum = sh64_compact_reg_base_num (reg_nr);
3532
3533 /* Build the value in the provided buffer. */
3534 regcache_raw_read (regcache, base_regnum, temp_buffer);
3535 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3536 offset = 4;
3537 memcpy (buffer, temp_buffer + offset, 4); /* get LOWER 32 bits only????*/
3538 }
3539
3540 else if (reg_nr >= tdep->FP0_C_REGNUM
3541 && reg_nr <= tdep->FP_LAST_C_REGNUM)
3542 {
3543 base_regnum = sh64_compact_reg_base_num (reg_nr);
3544
3545 /* Build the value in the provided buffer. */
3546 /* Floating point registers map 1-1 to the media fp regs,
3547 they have the same size and endienness. */
3548 regcache_raw_read (regcache, base_regnum, buffer);
3549 }
3550
3551 else if (reg_nr >= tdep->DR0_C_REGNUM
3552 && reg_nr <= tdep->DR_LAST_C_REGNUM)
3553 {
3554 base_regnum = sh64_compact_reg_base_num (reg_nr);
3555
3556 /* DR_C regs are double precision registers obtained by
3557 concatenating 2 single precision floating point registers. */
3558 for (portion = 0; portion < 2; portion++)
3559 regcache_raw_read (regcache, base_regnum + portion,
3560 (temp_buffer
3561 + REGISTER_RAW_SIZE (base_regnum) * portion));
3562
3563 /* We must pay attention to the endiannes. */
3564 sh_sh64_register_convert_to_virtual (reg_nr, REGISTER_VIRTUAL_TYPE (reg_nr),
3565 temp_buffer, buffer);
3566 }
3567
3568 else if (reg_nr >= tdep->FV0_C_REGNUM
3569 && reg_nr <= tdep->FV_LAST_C_REGNUM)
3570 {
3571 base_regnum = sh64_compact_reg_base_num (reg_nr);
3572
3573 /* Build the value in the provided buffer. */
3574 /* FV_C regs are vectors of single precision registers obtained by
3575 concatenating 4 single precision floating point registers. */
3576 for (portion = 0; portion < 4; portion++)
3577 regcache_raw_read (regcache, base_regnum + portion,
3578 ((char *) buffer
3579 + REGISTER_RAW_SIZE (base_regnum) * portion));
3580 }
3581
3582 else if (reg_nr == tdep->FPSCR_C_REGNUM)
3583 {
3584 int fpscr_base_regnum;
3585 int sr_base_regnum;
3586 unsigned int fpscr_value;
3587 unsigned int sr_value;
3588 unsigned int fpscr_c_value;
3589 unsigned int fpscr_c_part1_value;
3590 unsigned int fpscr_c_part2_value;
3591
3592 fpscr_base_regnum = tdep->FPSCR_REGNUM;
3593 sr_base_regnum = tdep->SR_REGNUM;
3594
3595 /* Build the value in the provided buffer. */
3596 /* FPSCR_C is a very weird register that contains sparse bits
3597 from the FPSCR and the SR architectural registers.
3598 Specifically: */
3599 /* *INDENT-OFF* */
3600 /*
3601 FPSRC_C bit
3602 0 Bit 0 of FPSCR
3603 1 reserved
3604 2-17 Bit 2-18 of FPSCR
3605 18-20 Bits 12,13,14 of SR
3606 21-31 reserved
3607 */
3608 /* *INDENT-ON* */
3609 /* Get FPSCR into a local buffer */
3610 regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer);
3611 /* Get value as an int. */
3612 fpscr_value = extract_unsigned_integer (temp_buffer, 4);
3613 /* Get SR into a local buffer */
3614 regcache_raw_read (regcache, sr_base_regnum, temp_buffer);
3615 /* Get value as an int. */
3616 sr_value = extract_unsigned_integer (temp_buffer, 4);
3617 /* Build the new value. */
3618 fpscr_c_part1_value = fpscr_value & 0x3fffd;
3619 fpscr_c_part2_value = (sr_value & 0x7000) << 6;
3620 fpscr_c_value = fpscr_c_part1_value | fpscr_c_part2_value;
3621 /* Store that in out buffer!!! */
3622 store_unsigned_integer (buffer, 4, fpscr_c_value);
3623 /* FIXME There is surely an endianness gotcha here. */
3624 }
3625
3626 else if (reg_nr == tdep->FPUL_C_REGNUM)
3627 {
3628 base_regnum = sh64_compact_reg_base_num (reg_nr);
3629
3630 /* FPUL_C register is floating point register 32,
3631 same size, same endianness. */
3632 regcache_raw_read (regcache, base_regnum, buffer);
3633 }
3634 }
3635
3636 static void
3637 sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
3638 int reg_nr, const void *buffer)
3639 {
3640 int base_regnum, portion;
3641 char temp_buffer[MAX_REGISTER_SIZE];
3642 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3643
3644 if (reg_nr >= tdep->DR0_REGNUM
3645 && reg_nr <= tdep->DR_LAST_REGNUM)
3646 {
3647 base_regnum = dr_reg_base_num (reg_nr);
3648
3649 /* We must pay attention to the endiannes. */
3650 sh_sh4_register_convert_to_raw (gdbarch_register_type (gdbarch, reg_nr), reg_nr,
3651 buffer, temp_buffer);
3652
3653 /* Write the real regs for which this one is an alias. */
3654 for (portion = 0; portion < 2; portion++)
3655 regcache_raw_write (regcache, base_regnum + portion,
3656 (temp_buffer
3657 + register_size (gdbarch, base_regnum) * portion));
3658 }
3659 else if (reg_nr >= tdep->FV0_REGNUM
3660 && reg_nr <= tdep->FV_LAST_REGNUM)
3661 {
3662 base_regnum = fv_reg_base_num (reg_nr);
3663
3664 /* Write the real regs for which this one is an alias. */
3665 for (portion = 0; portion < 4; portion++)
3666 regcache_raw_write (regcache, base_regnum + portion,
3667 ((char *) buffer
3668 + register_size (gdbarch, base_regnum) * portion));
3669 }
3670 }
3671
3672 static void
3673 sh64_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
3674 int reg_nr, const void *buffer)
3675 {
3676 int base_regnum, portion;
3677 int offset;
3678 char temp_buffer[MAX_REGISTER_SIZE];
3679 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3680
3681 if (reg_nr >= tdep->DR0_REGNUM
3682 && reg_nr <= tdep->DR_LAST_REGNUM)
3683 {
3684 base_regnum = dr_reg_base_num (reg_nr);
3685 /* We must pay attention to the endiannes. */
3686 sh_sh64_register_convert_to_raw (REGISTER_VIRTUAL_TYPE (reg_nr), reg_nr,
3687 buffer, temp_buffer);
3688
3689
3690 /* Write the real regs for which this one is an alias. */
3691 for (portion = 0; portion < 2; portion++)
3692 regcache_raw_write (regcache, base_regnum + portion,
3693 (temp_buffer
3694 + REGISTER_RAW_SIZE (base_regnum) * portion));
3695 }
3696
3697 else if (reg_nr >= tdep->FPP0_REGNUM
3698 && reg_nr <= tdep->FPP_LAST_REGNUM)
3699 {
3700 base_regnum = fpp_reg_base_num (reg_nr);
3701
3702 /* Write the real regs for which this one is an alias. */
3703 for (portion = 0; portion < 2; portion++)
3704 regcache_raw_write (regcache, base_regnum + portion,
3705 ((char *) buffer
3706 + REGISTER_RAW_SIZE (base_regnum) * portion));
3707 }
3708
3709 else if (reg_nr >= tdep->FV0_REGNUM
3710 && reg_nr <= tdep->FV_LAST_REGNUM)
3711 {
3712 base_regnum = fv_reg_base_num (reg_nr);
3713
3714 /* Write the real regs for which this one is an alias. */
3715 for (portion = 0; portion < 4; portion++)
3716 regcache_raw_write (regcache, base_regnum + portion,
3717 ((char *) buffer
3718 + REGISTER_RAW_SIZE (base_regnum) * portion));
3719 }
3720
3721 /* sh compact general pseudo registers. 1-to-1 with a shmedia
3722 register but only 4 bytes of it. */
3723 else if (reg_nr >= tdep->R0_C_REGNUM
3724 && reg_nr <= tdep->T_C_REGNUM)
3725 {
3726 base_regnum = sh64_compact_reg_base_num (reg_nr);
3727 /* reg_nr is 32 bit here, and base_regnum is 64 bits. */
3728 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3729 offset = 4;
3730 else
3731 offset = 0;
3732 /* Let's read the value of the base register into a temporary
3733 buffer, so that overwriting the last four bytes with the new
3734 value of the pseudo will leave the upper 4 bytes unchanged. */
3735 regcache_raw_read (regcache, base_regnum, temp_buffer);
3736 /* Write as an 8 byte quantity */
3737 memcpy (temp_buffer + offset, buffer, 4);
3738 regcache_raw_write (regcache, base_regnum, temp_buffer);
3739 }
3740
3741 /* sh floating point compact pseudo registers. 1-to-1 with a shmedia
3742 registers. Both are 4 bytes. */
3743 else if (reg_nr >= tdep->FP0_C_REGNUM
3744 && reg_nr <= tdep->FP_LAST_C_REGNUM)
3745 {
3746 base_regnum = sh64_compact_reg_base_num (reg_nr);
3747 regcache_raw_write (regcache, base_regnum, buffer);
3748 }
3749
3750 else if (reg_nr >= tdep->DR0_C_REGNUM
3751 && reg_nr <= tdep->DR_LAST_C_REGNUM)
3752 {
3753 base_regnum = sh64_compact_reg_base_num (reg_nr);
3754 for (portion = 0; portion < 2; portion++)
3755 {
3756 /* We must pay attention to the endiannes. */
3757 sh_sh64_register_convert_to_raw (REGISTER_VIRTUAL_TYPE (reg_nr), reg_nr,
3758 buffer, temp_buffer);
3759
3760 regcache_raw_write (regcache, base_regnum + portion,
3761 (temp_buffer
3762 + REGISTER_RAW_SIZE (base_regnum) * portion));
3763 }
3764 }
3765
3766 else if (reg_nr >= tdep->FV0_C_REGNUM
3767 && reg_nr <= tdep->FV_LAST_C_REGNUM)
3768 {
3769 base_regnum = sh64_compact_reg_base_num (reg_nr);
3770
3771 for (portion = 0; portion < 4; portion++)
3772 {
3773 regcache_raw_write (regcache, base_regnum + portion,
3774 ((char *) buffer
3775 + REGISTER_RAW_SIZE (base_regnum) * portion));
3776 }
3777 }
3778
3779 else if (reg_nr == tdep->FPSCR_C_REGNUM)
3780 {
3781 int fpscr_base_regnum;
3782 int sr_base_regnum;
3783 unsigned int fpscr_value;
3784 unsigned int sr_value;
3785 unsigned int old_fpscr_value;
3786 unsigned int old_sr_value;
3787 unsigned int fpscr_c_value;
3788 unsigned int fpscr_mask;
3789 unsigned int sr_mask;
3790
3791 fpscr_base_regnum = tdep->FPSCR_REGNUM;
3792 sr_base_regnum = tdep->SR_REGNUM;
3793
3794 /* FPSCR_C is a very weird register that contains sparse bits
3795 from the FPSCR and the SR architectural registers.
3796 Specifically: */
3797 /* *INDENT-OFF* */
3798 /*
3799 FPSRC_C bit
3800 0 Bit 0 of FPSCR
3801 1 reserved
3802 2-17 Bit 2-18 of FPSCR
3803 18-20 Bits 12,13,14 of SR
3804 21-31 reserved
3805 */
3806 /* *INDENT-ON* */
3807 /* Get value as an int. */
3808 fpscr_c_value = extract_unsigned_integer (buffer, 4);
3809
3810 /* Build the new values. */
3811 fpscr_mask = 0x0003fffd;
3812 sr_mask = 0x001c0000;
3813
3814 fpscr_value = fpscr_c_value & fpscr_mask;
3815 sr_value = (fpscr_value & sr_mask) >> 6;
3816
3817 regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer);
3818 old_fpscr_value = extract_unsigned_integer (temp_buffer, 4);
3819 old_fpscr_value &= 0xfffc0002;
3820 fpscr_value |= old_fpscr_value;
3821 store_unsigned_integer (temp_buffer, 4, fpscr_value);
3822 regcache_raw_write (regcache, fpscr_base_regnum, temp_buffer);
3823
3824 regcache_raw_read (regcache, sr_base_regnum, temp_buffer);
3825 old_sr_value = extract_unsigned_integer (temp_buffer, 4);
3826 old_sr_value &= 0xffff8fff;
3827 sr_value |= old_sr_value;
3828 store_unsigned_integer (temp_buffer, 4, sr_value);
3829 regcache_raw_write (regcache, sr_base_regnum, temp_buffer);
3830 }
3831
3832 else if (reg_nr == tdep->FPUL_C_REGNUM)
3833 {
3834 base_regnum = sh64_compact_reg_base_num (reg_nr);
3835 regcache_raw_write (regcache, base_regnum, buffer);
3836 }
3837 }
3838
3839 /* Floating point vector of 4 float registers. */
3840 static void
3841 do_fv_register_info (struct gdbarch *gdbarch, struct ui_file *file,
3842 int fv_regnum)
3843 {
3844 int first_fp_reg_num = fv_reg_base_num (fv_regnum);
3845 fprintf_filtered (file, "fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
3846 fv_regnum - gdbarch_tdep (gdbarch)->FV0_REGNUM,
3847 (int) read_register (first_fp_reg_num),
3848 (int) read_register (first_fp_reg_num + 1),
3849 (int) read_register (first_fp_reg_num + 2),
3850 (int) read_register (first_fp_reg_num + 3));
3851 }
3852
3853 /* Floating point vector of 4 float registers, compact mode. */
3854 static void
3855 do_fv_c_register_info (int fv_regnum)
3856 {
3857 int first_fp_reg_num = sh64_compact_reg_base_num (fv_regnum);
3858 printf_filtered ("fv%d_c\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
3859 fv_regnum - gdbarch_tdep (current_gdbarch)->FV0_C_REGNUM,
3860 (int) read_register (first_fp_reg_num),
3861 (int) read_register (first_fp_reg_num + 1),
3862 (int) read_register (first_fp_reg_num + 2),
3863 (int) read_register (first_fp_reg_num + 3));
3864 }
3865
3866 /* Pairs of single regs. The DR are instead double precision
3867 registers. */
3868 static void
3869 do_fpp_register_info (int fpp_regnum)
3870 {
3871 int first_fp_reg_num = fpp_reg_base_num (fpp_regnum);
3872
3873 printf_filtered ("fpp%d\t0x%08x\t0x%08x\n",
3874 fpp_regnum - gdbarch_tdep (current_gdbarch)->FPP0_REGNUM,
3875 (int) read_register (first_fp_reg_num),
3876 (int) read_register (first_fp_reg_num + 1));
3877 }
3878
3879 /* Double precision registers. */
3880 static void
3881 do_dr_register_info (struct gdbarch *gdbarch, struct ui_file *file,
3882 int dr_regnum)
3883 {
3884 int first_fp_reg_num = dr_reg_base_num (dr_regnum);
3885
3886 fprintf_filtered (file, "dr%d\t0x%08x%08x\n",
3887 dr_regnum - gdbarch_tdep (gdbarch)->DR0_REGNUM,
3888 (int) read_register (first_fp_reg_num),
3889 (int) read_register (first_fp_reg_num + 1));
3890 }
3891
3892 /* Double precision registers, compact mode. */
3893 static void
3894 do_dr_c_register_info (int dr_regnum)
3895 {
3896 int first_fp_reg_num = sh64_compact_reg_base_num (dr_regnum);
3897
3898 printf_filtered ("dr%d_c\t0x%08x%08x\n",
3899 dr_regnum - gdbarch_tdep (current_gdbarch)->DR0_C_REGNUM,
3900 (int) read_register (first_fp_reg_num),
3901 (int) read_register (first_fp_reg_num +1));
3902 }
3903
3904 /* General register in compact mode. */
3905 static void
3906 do_r_c_register_info (int r_c_regnum)
3907 {
3908 int regnum = sh64_compact_reg_base_num (r_c_regnum);
3909
3910 printf_filtered ("r%d_c\t0x%08x\n",
3911 r_c_regnum - gdbarch_tdep (current_gdbarch)->R0_C_REGNUM,
3912 /*FIXME!!!*/ (int) read_register (regnum));
3913 }
3914
3915 /* FIXME:!! THIS SHOULD TAKE CARE OF GETTING THE RIGHT PORTION OF THE
3916 shmedia REGISTERS. */
3917 /* Control registers, compact mode. */
3918 static void
3919 do_cr_c_register_info (int cr_c_regnum)
3920 {
3921 switch (cr_c_regnum)
3922 {
3923 case 237: printf_filtered ("pc_c\t0x%08x\n", (int) read_register (cr_c_regnum));
3924 break;
3925 case 238: printf_filtered ("gbr_c\t0x%08x\n", (int) read_register (cr_c_regnum));
3926 break;
3927 case 239: printf_filtered ("mach_c\t0x%08x\n", (int) read_register (cr_c_regnum));
3928 break;
3929 case 240: printf_filtered ("macl_c\t0x%08x\n", (int) read_register (cr_c_regnum));
3930 break;
3931 case 241: printf_filtered ("pr_c\t0x%08x\n", (int) read_register (cr_c_regnum));
3932 break;
3933 case 242: printf_filtered ("t_c\t0x%08x\n", (int) read_register (cr_c_regnum));
3934 break;
3935 case 243: printf_filtered ("fpscr_c\t0x%08x\n", (int) read_register (cr_c_regnum));
3936 break;
3937 case 244: printf_filtered ("fpul_c\t0x%08x\n", (int)read_register (cr_c_regnum));
3938 break;
3939 }
3940 }
3941
3942 static void
3943 sh_print_pseudo_register (struct gdbarch *gdbarch, struct ui_file *file,
3944 int regnum)
3945 {
3946 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3947
3948 if (regnum < NUM_REGS || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
3949 internal_error (__FILE__, __LINE__,
3950 "Invalid pseudo register number %d\n", regnum);
3951 else if (regnum >= tdep->DR0_REGNUM
3952 && regnum <= tdep->DR_LAST_REGNUM)
3953 do_dr_register_info (gdbarch, file, regnum);
3954 else if (regnum >= tdep->FV0_REGNUM
3955 && regnum <= tdep->FV_LAST_REGNUM)
3956 do_fv_register_info (gdbarch, file, regnum);
3957 }
3958
3959 static void
3960 sh_do_fp_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
3961 { /* do values for FP (float) regs */
3962 char *raw_buffer;
3963 double flt; /* double extracted from raw hex data */
3964 int inv;
3965 int j;
3966
3967 /* Allocate space for the float. */
3968 raw_buffer = (char *) alloca (register_size (gdbarch, FP0_REGNUM));
3969
3970 /* Get the data in raw format. */
3971 if (!frame_register_read (get_selected_frame (), regnum, raw_buffer))
3972 error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum));
3973
3974 /* Get the register as a number */
3975 flt = unpack_double (builtin_type_float, raw_buffer, &inv);
3976
3977 /* Print the name and some spaces. */
3978 fputs_filtered (REGISTER_NAME (regnum), file);
3979 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file);
3980
3981 /* Print the value. */
3982 if (inv)
3983 fprintf_filtered (file, "<invalid float>");
3984 else
3985 fprintf_filtered (file, "%-10.9g", flt);
3986
3987 /* Print the fp register as hex. */
3988 fprintf_filtered (file, "\t(raw 0x");
3989 for (j = 0; j < register_size (gdbarch, regnum); j++)
3990 {
3991 register int idx = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? j
3992 : register_size (gdbarch, regnum) - 1 - j;
3993 fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[idx]);
3994 }
3995 fprintf_filtered (file, ")");
3996 fprintf_filtered (file, "\n");
3997 }
3998
3999 static void
4000 sh64_do_pseudo_register (int regnum)
4001 {
4002 /* All the sh64-compact mode registers are pseudo registers. */
4003 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
4004
4005 if (regnum < NUM_REGS
4006 || regnum >= NUM_REGS + NUM_PSEUDO_REGS_SH_MEDIA + NUM_PSEUDO_REGS_SH_COMPACT)
4007 internal_error (__FILE__, __LINE__,
4008 "Invalid pseudo register number %d\n", regnum);
4009
4010 else if ((regnum >= tdep->DR0_REGNUM
4011 && regnum <= tdep->DR_LAST_REGNUM))
4012 do_dr_register_info (current_gdbarch, gdb_stdout, regnum);
4013
4014 else if ((regnum >= tdep->DR0_C_REGNUM
4015 && regnum <= tdep->DR_LAST_C_REGNUM))
4016 do_dr_c_register_info (regnum);
4017
4018 else if ((regnum >= tdep->FV0_REGNUM
4019 && regnum <= tdep->FV_LAST_REGNUM))
4020 do_fv_register_info (current_gdbarch, gdb_stdout, regnum);
4021
4022 else if ((regnum >= tdep->FV0_C_REGNUM
4023 && regnum <= tdep->FV_LAST_C_REGNUM))
4024 do_fv_c_register_info (regnum);
4025
4026 else if (regnum >= tdep->FPP0_REGNUM
4027 && regnum <= tdep->FPP_LAST_REGNUM)
4028 do_fpp_register_info (regnum);
4029
4030 else if (regnum >= tdep->R0_C_REGNUM
4031 && regnum <= tdep->R_LAST_C_REGNUM)
4032 do_r_c_register_info (regnum); /* FIXME, this function will not print the right format */
4033
4034 else if (regnum >= tdep->FP0_C_REGNUM
4035 && regnum <= tdep->FP_LAST_C_REGNUM)
4036 sh_do_fp_register (current_gdbarch, gdb_stdout, regnum); /* this should work also for pseudoregs */
4037
4038 else if (regnum >= tdep->PC_C_REGNUM
4039 && regnum <= tdep->FPUL_C_REGNUM)
4040 do_cr_c_register_info (regnum);
4041
4042 }
4043
4044 static void
4045 sh_do_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
4046 {
4047 char raw_buffer[MAX_REGISTER_SIZE];
4048
4049 fputs_filtered (REGISTER_NAME (regnum), file);
4050 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file);
4051
4052 /* Get the data in raw format. */
4053 if (!frame_register_read (get_selected_frame (), regnum, raw_buffer))
4054 fprintf_filtered (file, "*value not available*\n");
4055
4056 val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0,
4057 file, 'x', 1, 0, Val_pretty_default);
4058 fprintf_filtered (file, "\t");
4059 val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0,
4060 file, 0, 1, 0, Val_pretty_default);
4061 fprintf_filtered (file, "\n");
4062 }
4063
4064 static void
4065 sh_print_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
4066 {
4067 if (regnum < 0 || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
4068 internal_error (__FILE__, __LINE__,
4069 "Invalid register number %d\n", regnum);
4070
4071 else if (regnum >= 0 && regnum < NUM_REGS)
4072 {
4073 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT)
4074 sh_do_fp_register (gdbarch, file, regnum); /* FP regs */
4075 else
4076 sh_do_register (gdbarch, file, regnum); /* All other regs */
4077 }
4078
4079 else if (regnum < NUM_REGS + NUM_PSEUDO_REGS)
4080 {
4081 if (gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh5)
4082 sh64_do_pseudo_register (regnum);
4083 else
4084 sh_print_pseudo_register (gdbarch, file, regnum);
4085 }
4086 }
4087
4088 static void
4089 sh_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
4090 struct frame_info *frame, int regnum, int fpregs)
4091 {
4092 if (regnum != -1) /* do one specified register */
4093 {
4094 if (*(REGISTER_NAME (regnum)) == '\0')
4095 error ("Not a valid register for the current processor type");
4096
4097 sh_print_register (gdbarch, file, regnum);
4098 }
4099 else
4100 /* do all (or most) registers */
4101 {
4102 regnum = 0;
4103 while (regnum < NUM_REGS)
4104 {
4105 /* If the register name is empty, it is undefined for this
4106 processor, so don't display anything. */
4107 if (REGISTER_NAME (regnum) == NULL
4108 || *(REGISTER_NAME (regnum)) == '\0')
4109 {
4110 regnum++;
4111 continue;
4112 }
4113
4114 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT)
4115 {
4116 if (fpregs)
4117 {
4118 /* true for "INFO ALL-REGISTERS" command */
4119 sh_do_fp_register (gdbarch, file, regnum); /* FP regs */
4120 regnum ++;
4121 }
4122 else
4123 regnum += (gdbarch_tdep (gdbarch)->FP_LAST_REGNUM - FP0_REGNUM); /* skip FP regs */
4124 }
4125 else
4126 {
4127 sh_do_register (gdbarch, file, regnum); /* All other regs */
4128 regnum++;
4129 }
4130 }
4131
4132 if (fpregs)
4133 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
4134 {
4135 if (gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh5)
4136 sh64_do_pseudo_register (regnum);
4137 else
4138 sh_print_pseudo_register (gdbarch, file, regnum);
4139 regnum++;
4140 }
4141 }
4142 }
4143
4144 static void
4145 sh_compact_do_registers_info (int regnum, int fpregs)
4146 {
4147 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
4148 if (regnum != -1) /* do one specified register */
4149 {
4150 if (*(REGISTER_NAME (regnum)) == '\0')
4151 error ("Not a valid register for the current processor type");
4152
4153 if (regnum >= 0 && regnum < tdep->R0_C_REGNUM)
4154 error ("Not a valid register for the current processor mode.");
4155
4156 sh_print_register (current_gdbarch, gdb_stdout, regnum);
4157 }
4158 else
4159 /* do all compact registers */
4160 {
4161 regnum = tdep->R0_C_REGNUM;
4162 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
4163 {
4164 sh64_do_pseudo_register (regnum);
4165 regnum++;
4166 }
4167 }
4168 }
4169
4170 static void
4171 sh64_do_registers_info (int regnum, int fpregs)
4172 {
4173 if (pc_is_isa32 (get_frame_pc (deprecated_selected_frame)))
4174 sh_print_registers_info (current_gdbarch, gdb_stdout,
4175 deprecated_selected_frame, regnum, fpregs);
4176 else
4177 sh_compact_do_registers_info (regnum, fpregs);
4178 }
4179
4180 #ifdef SVR4_SHARED_LIBS
4181
4182 /* Fetch (and possibly build) an appropriate link_map_offsets structure
4183 for native i386 linux targets using the struct offsets defined in
4184 link.h (but without actual reference to that file).
4185
4186 This makes it possible to access i386-linux shared libraries from
4187 a gdb that was not built on an i386-linux host (for cross debugging).
4188 */
4189
4190 struct link_map_offsets *
4191 sh_linux_svr4_fetch_link_map_offsets (void)
4192 {
4193 static struct link_map_offsets lmo;
4194 static struct link_map_offsets *lmp = 0;
4195
4196 if (lmp == 0)
4197 {
4198 lmp = &lmo;
4199
4200 lmo.r_debug_size = 8; /* 20 not actual size but all we need */
4201
4202 lmo.r_map_offset = 4;
4203 lmo.r_map_size = 4;
4204
4205 lmo.link_map_size = 20; /* 552 not actual size but all we need */
4206
4207 lmo.l_addr_offset = 0;
4208 lmo.l_addr_size = 4;
4209
4210 lmo.l_name_offset = 4;
4211 lmo.l_name_size = 4;
4212
4213 lmo.l_next_offset = 12;
4214 lmo.l_next_size = 4;
4215
4216 lmo.l_prev_offset = 16;
4217 lmo.l_prev_size = 4;
4218 }
4219
4220 return lmp;
4221 }
4222 #endif /* SVR4_SHARED_LIBS */
4223
4224 \f
4225 enum
4226 {
4227 DSP_DSR_REGNUM = 24,
4228 DSP_A0G_REGNUM,
4229 DSP_A0_REGNUM,
4230 DSP_A1G_REGNUM,
4231 DSP_A1_REGNUM,
4232 DSP_M0_REGNUM,
4233 DSP_M1_REGNUM,
4234 DSP_X0_REGNUM,
4235 DSP_X1_REGNUM,
4236 DSP_Y0_REGNUM,
4237 DSP_Y1_REGNUM,
4238
4239 DSP_MOD_REGNUM = 40,
4240
4241 DSP_RS_REGNUM = 43,
4242 DSP_RE_REGNUM,
4243
4244 DSP_R0_BANK_REGNUM = 51,
4245 DSP_R7_BANK_REGNUM = DSP_R0_BANK_REGNUM + 7
4246 };
4247
4248 static int
4249 sh_dsp_register_sim_regno (int nr)
4250 {
4251 if (legacy_register_sim_regno (nr) < 0)
4252 return legacy_register_sim_regno (nr);
4253 if (nr >= DSP_DSR_REGNUM && nr <= DSP_Y1_REGNUM)
4254 return nr - DSP_DSR_REGNUM + SIM_SH_DSR_REGNUM;
4255 if (nr == DSP_MOD_REGNUM)
4256 return SIM_SH_MOD_REGNUM;
4257 if (nr == DSP_RS_REGNUM)
4258 return SIM_SH_RS_REGNUM;
4259 if (nr == DSP_RE_REGNUM)
4260 return SIM_SH_RE_REGNUM;
4261 if (nr >= DSP_R0_BANK_REGNUM && nr <= DSP_R7_BANK_REGNUM)
4262 return nr - DSP_R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM;
4263 return nr;
4264 }
4265 \f
4266 static gdbarch_init_ftype sh_gdbarch_init;
4267
4268 static struct gdbarch *
4269 sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
4270 {
4271 static LONGEST sh64_call_dummy_words[] = {0};
4272 struct gdbarch *gdbarch;
4273 struct gdbarch_tdep *tdep;
4274
4275 /* If there is already a candidate, use it. */
4276 arches = gdbarch_list_lookup_by_info (arches, &info);
4277 if (arches != NULL)
4278 return arches->gdbarch;
4279
4280 /* None found, create a new architecture from the information
4281 provided. */
4282 tdep = XMALLOC (struct gdbarch_tdep);
4283 gdbarch = gdbarch_alloc (&info, tdep);
4284
4285 /* NOTE: cagney/2002-12-06: This can be deleted when this arch is
4286 ready to unwind the PC first (see frame.c:get_prev_frame()). */
4287 set_gdbarch_deprecated_init_frame_pc (gdbarch, init_frame_pc_default);
4288
4289 /* Initialize the register numbers that are not common to all the
4290 variants to -1, if necessary thse will be overwritten in the case
4291 statement below. */
4292 tdep->FPUL_REGNUM = -1;
4293 tdep->FPSCR_REGNUM = -1;
4294 tdep->PR_REGNUM = 17;
4295 tdep->SR_REGNUM = 22;
4296 tdep->DSR_REGNUM = -1;
4297 tdep->FP_LAST_REGNUM = -1;
4298 tdep->A0G_REGNUM = -1;
4299 tdep->A0_REGNUM = -1;
4300 tdep->A1G_REGNUM = -1;
4301 tdep->A1_REGNUM = -1;
4302 tdep->M0_REGNUM = -1;
4303 tdep->M1_REGNUM = -1;
4304 tdep->X0_REGNUM = -1;
4305 tdep->X1_REGNUM = -1;
4306 tdep->Y0_REGNUM = -1;
4307 tdep->Y1_REGNUM = -1;
4308 tdep->MOD_REGNUM = -1;
4309 tdep->RS_REGNUM = -1;
4310 tdep->RE_REGNUM = -1;
4311 tdep->SSR_REGNUM = -1;
4312 tdep->SPC_REGNUM = -1;
4313 tdep->DR0_REGNUM = -1;
4314 tdep->DR_LAST_REGNUM = -1;
4315 tdep->FV0_REGNUM = -1;
4316 tdep->FV_LAST_REGNUM = -1;
4317 tdep->ARG0_REGNUM = 4;
4318 tdep->ARGLAST_REGNUM = 7;
4319 tdep->RETURN_REGNUM = 0;
4320 tdep->FLOAT_ARGLAST_REGNUM = -1;
4321
4322 tdep->sh_abi = SH_ABI_UNKNOWN;
4323
4324 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
4325 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
4326 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
4327 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
4328 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
4329 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
4330 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
4331 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
4332
4333 set_gdbarch_num_regs (gdbarch, SH_DEFAULT_NUM_REGS);
4334 set_gdbarch_sp_regnum (gdbarch, 15);
4335 set_gdbarch_deprecated_fp_regnum (gdbarch, 14);
4336 set_gdbarch_pc_regnum (gdbarch, 16);
4337 set_gdbarch_fp0_regnum (gdbarch, -1);
4338 set_gdbarch_num_pseudo_regs (gdbarch, 0);
4339
4340 set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc);
4341 set_gdbarch_use_struct_convention (gdbarch, sh_use_struct_convention);
4342
4343 set_gdbarch_print_insn (gdbarch, gdb_print_insn_sh);
4344 set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno);
4345
4346 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
4347
4348 set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue);
4349 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
4350 set_gdbarch_decr_pc_after_break (gdbarch, 0);
4351 set_gdbarch_function_start_offset (gdbarch, 0);
4352
4353 set_gdbarch_frame_args_skip (gdbarch, 0);
4354 set_gdbarch_frameless_function_invocation (gdbarch, frameless_look_for_prologue);
4355 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
4356
4357 skip_prologue_hard_way = sh_skip_prologue_hard_way;
4358
4359 set_gdbarch_deprecated_frame_chain (gdbarch, sh_frame_chain);
4360 set_gdbarch_deprecated_get_saved_register (gdbarch, deprecated_generic_get_saved_register);
4361 set_gdbarch_deprecated_init_extra_frame_info (gdbarch, sh_init_extra_frame_info);
4362 set_gdbarch_deprecated_pop_frame (gdbarch, sh_pop_frame);
4363 set_gdbarch_deprecated_frame_saved_pc (gdbarch, sh_frame_saved_pc);
4364 set_gdbarch_deprecated_saved_pc_after_call (gdbarch, sh_saved_pc_after_call);
4365 set_gdbarch_frame_align (gdbarch, sh_frame_align);
4366
4367 switch (info.bfd_arch_info->mach)
4368 {
4369 case bfd_mach_sh:
4370 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
4371 set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info);
4372 sh_show_regs = sh_generic_show_regs;
4373 set_gdbarch_register_type (gdbarch, sh_default_register_type);
4374 set_gdbarch_push_dummy_code (gdbarch, sh_push_dummy_code);
4375 set_gdbarch_store_return_value (gdbarch, sh_default_store_return_value);
4376 set_gdbarch_extract_return_value (gdbarch, sh_default_extract_return_value);
4377 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call);
4378 set_gdbarch_extract_struct_value_address (gdbarch, sh_extract_struct_value_address);
4379
4380 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
4381 break;
4382 case bfd_mach_sh2:
4383 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
4384 set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info);
4385 sh_show_regs = sh_generic_show_regs;
4386 set_gdbarch_register_type (gdbarch, sh_default_register_type);
4387 set_gdbarch_push_dummy_code (gdbarch, sh_push_dummy_code);
4388 set_gdbarch_store_return_value (gdbarch, sh_default_store_return_value);
4389 set_gdbarch_extract_return_value (gdbarch, sh_default_extract_return_value);
4390 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call);
4391 set_gdbarch_extract_struct_value_address (gdbarch, sh_extract_struct_value_address);
4392
4393 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
4394 break;
4395 case bfd_mach_sh2e:
4396 /* doubles on sh2e and sh3e are actually 4 byte. */
4397 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
4398
4399 set_gdbarch_register_name (gdbarch, sh_sh2e_register_name);
4400 set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info);
4401 sh_show_regs = sh2e_show_regs;
4402 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
4403 set_gdbarch_push_dummy_code (gdbarch, sh_push_dummy_code);
4404 set_gdbarch_fp0_regnum (gdbarch, 25);
4405 set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value);
4406 set_gdbarch_extract_return_value (gdbarch, sh3e_sh4_extract_return_value);
4407 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call);
4408 set_gdbarch_extract_struct_value_address (gdbarch, sh_extract_struct_value_address);
4409 tdep->FPUL_REGNUM = 23;
4410 tdep->FPSCR_REGNUM = 24;
4411 tdep->FP_LAST_REGNUM = 40;
4412
4413 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
4414 break;
4415 case bfd_mach_sh_dsp:
4416 set_gdbarch_register_name (gdbarch, sh_sh_dsp_register_name);
4417 set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info);
4418 sh_show_regs = sh_dsp_show_regs;
4419 set_gdbarch_register_type (gdbarch, sh_default_register_type);
4420 set_gdbarch_push_dummy_code (gdbarch, sh_push_dummy_code);
4421 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
4422 set_gdbarch_store_return_value (gdbarch, sh_default_store_return_value);
4423 set_gdbarch_extract_return_value (gdbarch, sh_default_extract_return_value);
4424 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call);
4425 set_gdbarch_extract_struct_value_address (gdbarch, sh_extract_struct_value_address);
4426 tdep->DSR_REGNUM = 24;
4427 tdep->A0G_REGNUM = 25;
4428 tdep->A0_REGNUM = 26;
4429 tdep->A1G_REGNUM = 27;
4430 tdep->A1_REGNUM = 28;
4431 tdep->M0_REGNUM = 29;
4432 tdep->M1_REGNUM = 30;
4433 tdep->X0_REGNUM = 31;
4434 tdep->X1_REGNUM = 32;
4435 tdep->Y0_REGNUM = 33;
4436 tdep->Y1_REGNUM = 34;
4437 tdep->MOD_REGNUM = 40;
4438 tdep->RS_REGNUM = 43;
4439 tdep->RE_REGNUM = 44;
4440
4441 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
4442 break;
4443 case bfd_mach_sh3:
4444 set_gdbarch_register_name (gdbarch, sh_sh3_register_name);
4445 set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info);
4446 sh_show_regs = sh3_show_regs;
4447 set_gdbarch_register_type (gdbarch, sh_default_register_type);
4448 set_gdbarch_push_dummy_code (gdbarch, sh_push_dummy_code);
4449 set_gdbarch_store_return_value (gdbarch, sh_default_store_return_value);
4450 set_gdbarch_extract_return_value (gdbarch, sh_default_extract_return_value);
4451 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call);
4452 set_gdbarch_extract_struct_value_address (gdbarch, sh_extract_struct_value_address);
4453 tdep->SSR_REGNUM = 41;
4454 tdep->SPC_REGNUM = 42;
4455
4456 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
4457 break;
4458 case bfd_mach_sh3e:
4459 /* doubles on sh2e and sh3e are actually 4 byte. */
4460 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
4461
4462 set_gdbarch_register_name (gdbarch, sh_sh3e_register_name);
4463 set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info);
4464 sh_show_regs = sh3e_show_regs;
4465 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
4466 set_gdbarch_push_dummy_code (gdbarch, sh_push_dummy_code);
4467 set_gdbarch_fp0_regnum (gdbarch, 25);
4468 set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value);
4469 set_gdbarch_extract_return_value (gdbarch, sh3e_sh4_extract_return_value);
4470 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call);
4471 set_gdbarch_extract_struct_value_address (gdbarch, sh_extract_struct_value_address);
4472 tdep->FPUL_REGNUM = 23;
4473 tdep->FPSCR_REGNUM = 24;
4474 tdep->FP_LAST_REGNUM = 40;
4475 tdep->SSR_REGNUM = 41;
4476 tdep->SPC_REGNUM = 42;
4477
4478 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh_fp_frame_init_saved_regs);
4479 break;
4480 case bfd_mach_sh3_dsp:
4481 set_gdbarch_register_name (gdbarch, sh_sh3_dsp_register_name);
4482 set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info);
4483 sh_show_regs = sh3_dsp_show_regs;
4484 set_gdbarch_register_type (gdbarch, sh_default_register_type);
4485 set_gdbarch_push_dummy_code (gdbarch, sh_push_dummy_code);
4486 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
4487 set_gdbarch_store_return_value (gdbarch, sh_default_store_return_value);
4488 set_gdbarch_extract_return_value (gdbarch, sh_default_extract_return_value);
4489 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call);
4490 set_gdbarch_extract_struct_value_address (gdbarch, sh_extract_struct_value_address);
4491 tdep->DSR_REGNUM = 24;
4492 tdep->A0G_REGNUM = 25;
4493 tdep->A0_REGNUM = 26;
4494 tdep->A1G_REGNUM = 27;
4495 tdep->A1_REGNUM = 28;
4496 tdep->M0_REGNUM = 29;
4497 tdep->M1_REGNUM = 30;
4498 tdep->X0_REGNUM = 31;
4499 tdep->X1_REGNUM = 32;
4500 tdep->Y0_REGNUM = 33;
4501 tdep->Y1_REGNUM = 34;
4502 tdep->MOD_REGNUM = 40;
4503 tdep->RS_REGNUM = 43;
4504 tdep->RE_REGNUM = 44;
4505 tdep->SSR_REGNUM = 41;
4506 tdep->SPC_REGNUM = 42;
4507
4508 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
4509 break;
4510 case bfd_mach_sh4:
4511 set_gdbarch_register_name (gdbarch, sh_sh4_register_name);
4512 set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info);
4513 sh_show_regs = sh4_show_regs;
4514 set_gdbarch_register_type (gdbarch, sh_sh4_register_type);
4515 set_gdbarch_push_dummy_code (gdbarch, sh_push_dummy_code);
4516 set_gdbarch_fp0_regnum (gdbarch, 25);
4517 set_gdbarch_num_pseudo_regs (gdbarch, 12);
4518 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
4519 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
4520 set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value);
4521 set_gdbarch_extract_return_value (gdbarch, sh3e_sh4_extract_return_value);
4522 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call);
4523 set_gdbarch_extract_struct_value_address (gdbarch, sh_extract_struct_value_address);
4524 tdep->FPUL_REGNUM = 23;
4525 tdep->FPSCR_REGNUM = 24;
4526 tdep->FP_LAST_REGNUM = 40;
4527 tdep->SSR_REGNUM = 41;
4528 tdep->SPC_REGNUM = 42;
4529 tdep->DR0_REGNUM = 59;
4530 tdep->DR_LAST_REGNUM = 66;
4531 tdep->FV0_REGNUM = 67;
4532 tdep->FV_LAST_REGNUM = 70;
4533
4534 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh_fp_frame_init_saved_regs);
4535 break;
4536 case bfd_mach_sh5:
4537 tdep->PR_REGNUM = 18;
4538 tdep->SR_REGNUM = 65;
4539 tdep->FPSCR_REGNUM = SIM_SH64_FPCSR_REGNUM;
4540 tdep->FP_LAST_REGNUM = SIM_SH64_FR0_REGNUM + SIM_SH64_NR_FP_REGS - 1;
4541 tdep->SSR_REGNUM = SIM_SH64_SSR_REGNUM;
4542 tdep->SPC_REGNUM = SIM_SH64_SPC_REGNUM;
4543 tdep->TR7_REGNUM = SIM_SH64_TR0_REGNUM + 7;
4544 tdep->FPP0_REGNUM = 173;
4545 tdep->FPP_LAST_REGNUM = 204;
4546 tdep->DR0_REGNUM = 141;
4547 tdep->DR_LAST_REGNUM = 172;
4548 tdep->FV0_REGNUM = 205;
4549 tdep->FV_LAST_REGNUM = 220;
4550 tdep->R0_C_REGNUM = 221;
4551 tdep->R_LAST_C_REGNUM = 236;
4552 tdep->PC_C_REGNUM = 237;
4553 tdep->GBR_C_REGNUM = 238;
4554 tdep->MACH_C_REGNUM = 239;
4555 tdep->MACL_C_REGNUM = 240;
4556 tdep->PR_C_REGNUM = 241;
4557 tdep->T_C_REGNUM = 242;
4558 tdep->FPSCR_C_REGNUM = 243;
4559 tdep->FPUL_C_REGNUM = 244;
4560 tdep->FP0_C_REGNUM = 245;
4561 tdep->FP_LAST_C_REGNUM = 260;
4562 tdep->DR0_C_REGNUM = 261;
4563 tdep->DR_LAST_C_REGNUM = 268;
4564 tdep->FV0_C_REGNUM = 269;
4565 tdep->FV_LAST_C_REGNUM = 272;
4566 tdep->ARG0_REGNUM = 2;
4567 tdep->ARGLAST_REGNUM = 9;
4568 tdep->RETURN_REGNUM = 2;
4569 tdep->FLOAT_ARGLAST_REGNUM = 11;
4570
4571 set_gdbarch_num_pseudo_regs (gdbarch, NUM_PSEUDO_REGS_SH_MEDIA + NUM_PSEUDO_REGS_SH_COMPACT);
4572 set_gdbarch_fp0_regnum (gdbarch, SIM_SH64_FR0_REGNUM);
4573 set_gdbarch_pc_regnum (gdbarch, 64);
4574
4575 /* Determine the ABI */
4576 if (bfd_get_arch_size (info.abfd) == 64)
4577 {
4578 /* If the ABI is the 64-bit one, it can only be sh-media. */
4579 tdep->sh_abi = SH_ABI_64;
4580 set_gdbarch_ptr_bit (gdbarch, 8 * TARGET_CHAR_BIT);
4581 set_gdbarch_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
4582 }
4583 else
4584 {
4585 /* If the ABI is the 32-bit one it could be either media or
4586 compact. */
4587 tdep->sh_abi = SH_ABI_32;
4588 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
4589 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
4590 }
4591
4592 /* the number of real registers is the same whether we are in
4593 ISA16(compact) or ISA32(media). */
4594 set_gdbarch_num_regs (gdbarch, SIM_SH64_NR_REGS);
4595 set_gdbarch_deprecated_register_size (gdbarch, 8); /*????*/
4596 set_gdbarch_deprecated_register_bytes (gdbarch,
4597 ((SIM_SH64_NR_FP_REGS + 1) * 4)
4598 + (SIM_SH64_NR_REGS - SIM_SH64_NR_FP_REGS -1) * 8);
4599
4600 set_gdbarch_register_name (gdbarch, sh_sh64_register_name);
4601 sh_show_regs = sh64_show_regs;
4602 set_gdbarch_deprecated_register_virtual_type (gdbarch, sh_sh64_register_virtual_type);
4603 set_gdbarch_deprecated_store_return_value (gdbarch, sh64_store_return_value);
4604 skip_prologue_hard_way = sh64_skip_prologue_hard_way;
4605 set_gdbarch_deprecated_register_raw_size (gdbarch, sh_sh64_register_raw_size);
4606 set_gdbarch_deprecated_register_virtual_size (gdbarch, sh_sh64_register_raw_size);
4607 set_gdbarch_deprecated_register_byte (gdbarch, sh_sh64_register_byte);
4608 /* This seems awfully wrong!*/
4609 /*set_gdbarch_deprecated_max_register_raw_size (gdbarch, 8);*/
4610 /* should include the size of the pseudo regs. */
4611 set_gdbarch_deprecated_max_register_raw_size (gdbarch, 4 * 4);
4612 /* Or should that go in the virtual_size? */
4613 /*set_gdbarch_deprecated_max_register_virtual_size (gdbarch, 8);*/
4614 set_gdbarch_deprecated_max_register_virtual_size (gdbarch, 4 * 4);
4615 set_gdbarch_pseudo_register_read (gdbarch, sh64_pseudo_register_read);
4616 set_gdbarch_pseudo_register_write (gdbarch, sh64_pseudo_register_write);
4617
4618 set_gdbarch_deprecated_do_registers_info (gdbarch, sh64_do_registers_info);
4619 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh64_nofp_frame_init_saved_regs);
4620 set_gdbarch_breakpoint_from_pc (gdbarch, sh_sh64_breakpoint_from_pc);
4621 set_gdbarch_deprecated_call_dummy_words (gdbarch, sh64_call_dummy_words);
4622 set_gdbarch_deprecated_sizeof_call_dummy_words (gdbarch, sizeof (sh64_call_dummy_words));
4623
4624 set_gdbarch_deprecated_init_extra_frame_info (gdbarch, sh64_init_extra_frame_info);
4625 set_gdbarch_deprecated_frame_chain (gdbarch, sh64_frame_chain);
4626 set_gdbarch_deprecated_get_saved_register (gdbarch, sh64_get_saved_register);
4627 set_gdbarch_deprecated_extract_return_value (gdbarch, sh64_extract_return_value);
4628 set_gdbarch_deprecated_push_arguments (gdbarch, sh64_push_arguments);
4629 set_gdbarch_deprecated_push_return_address (gdbarch, sh64_push_return_address);
4630 set_gdbarch_deprecated_dummy_write_sp (gdbarch, deprecated_write_sp);
4631 set_gdbarch_deprecated_store_struct_return (gdbarch, sh64_store_struct_return);
4632 set_gdbarch_deprecated_extract_struct_value_address (gdbarch, sh64_extract_struct_value_address);
4633 set_gdbarch_use_struct_convention (gdbarch, sh64_use_struct_convention);
4634 set_gdbarch_deprecated_pop_frame (gdbarch, sh64_pop_frame);
4635 set_gdbarch_elf_make_msymbol_special (gdbarch,
4636 sh64_elf_make_msymbol_special);
4637 break;
4638 default:
4639 set_gdbarch_register_name (gdbarch, sh_generic_register_name);
4640 set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info);
4641 sh_show_regs = sh_generic_show_regs;
4642 set_gdbarch_register_type (gdbarch, sh_default_register_type);
4643 set_gdbarch_push_dummy_code (gdbarch, sh_push_dummy_code);
4644 set_gdbarch_store_return_value (gdbarch, sh_default_store_return_value);
4645 set_gdbarch_extract_return_value (gdbarch, sh_default_extract_return_value);
4646
4647 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
4648 break;
4649 }
4650
4651 /* Hook in ABI-specific overrides, if they have been registered. */
4652 gdbarch_init_osabi (info, gdbarch);
4653
4654 return gdbarch;
4655 }
4656
4657 static void
4658 sh_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
4659 {
4660 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
4661
4662 if (tdep == NULL)
4663 return;
4664
4665 /* FIXME: dump the rest of gdbarch_tdep. */
4666 }
4667
4668 extern initialize_file_ftype _initialize_sh_tdep; /* -Wmissing-prototypes */
4669
4670 void
4671 _initialize_sh_tdep (void)
4672 {
4673 struct cmd_list_element *c;
4674
4675 gdbarch_register (bfd_arch_sh, sh_gdbarch_init, sh_dump_tdep);
4676
4677 add_com ("regs", class_vars, sh_show_regs_command, "Print all registers");
4678 }