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* sh-tdep.c (struct frame_extra_info): Remove.
[binutils-gdb.git] / gdb / sh-tdep.c
1 /* Target-dependent code for Hitachi Super-H, for GDB.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
21
22 /*
23 Contributed by Steve Chamberlain
24 sac@cygnus.com
25 */
26
27 #include "defs.h"
28 #include "frame.h"
29 #include "frame-base.h"
30 #include "frame-unwind.h"
31 #include "dwarf2-frame.h"
32 #include "symtab.h"
33 #include "symfile.h"
34 #include "gdbtypes.h"
35 #include "gdbcmd.h"
36 #include "gdbcore.h"
37 #include "value.h"
38 #include "dis-asm.h"
39 #include "inferior.h"
40 #include "gdb_string.h"
41 #include "gdb_assert.h"
42 #include "arch-utils.h"
43 #include "floatformat.h"
44 #include "regcache.h"
45 #include "doublest.h"
46 #include "osabi.h"
47
48 #include "sh-tdep.h"
49
50 #include "elf-bfd.h"
51 #include "solib-svr4.h"
52
53 /* sh flags */
54 #include "elf/sh.h"
55 /* registers numbers shared with the simulator */
56 #include "gdb/sim-sh.h"
57
58 static void (*sh_show_regs) (void);
59
60 #define SH_NUM_REGS 59
61
62 struct sh_frame_cache
63 {
64 /* Base address. */
65 CORE_ADDR base;
66 LONGEST sp_offset;
67 CORE_ADDR pc;
68
69 /* Flag showing that a frame has been created in the prologue code. */
70 int uses_fp;
71
72 /* Saved registers. */
73 CORE_ADDR saved_regs[SH_NUM_REGS];
74 CORE_ADDR saved_sp;
75 };
76
77 static const char *
78 sh_generic_register_name (int reg_nr)
79 {
80 static char *register_names[] =
81 {
82 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
83 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
84 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
85 "fpul", "fpscr",
86 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
87 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
88 "ssr", "spc",
89 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
90 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
91 };
92 if (reg_nr < 0)
93 return NULL;
94 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
95 return NULL;
96 return register_names[reg_nr];
97 }
98
99 static const char *
100 sh_sh_register_name (int reg_nr)
101 {
102 static char *register_names[] =
103 {
104 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
105 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
106 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
107 "", "",
108 "", "", "", "", "", "", "", "",
109 "", "", "", "", "", "", "", "",
110 "", "",
111 "", "", "", "", "", "", "", "",
112 "", "", "", "", "", "", "", "",
113 };
114 if (reg_nr < 0)
115 return NULL;
116 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
117 return NULL;
118 return register_names[reg_nr];
119 }
120
121 static const char *
122 sh_sh3_register_name (int reg_nr)
123 {
124 static char *register_names[] =
125 {
126 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
127 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
128 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
129 "", "",
130 "", "", "", "", "", "", "", "",
131 "", "", "", "", "", "", "", "",
132 "ssr", "spc",
133 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
134 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
135 };
136 if (reg_nr < 0)
137 return NULL;
138 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
139 return NULL;
140 return register_names[reg_nr];
141 }
142
143 static const char *
144 sh_sh3e_register_name (int reg_nr)
145 {
146 static char *register_names[] =
147 {
148 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
149 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
150 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
151 "fpul", "fpscr",
152 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
153 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
154 "ssr", "spc",
155 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
156 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
157 };
158 if (reg_nr < 0)
159 return NULL;
160 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
161 return NULL;
162 return register_names[reg_nr];
163 }
164
165 static const char *
166 sh_sh2e_register_name (int reg_nr)
167 {
168 static char *register_names[] =
169 {
170 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
171 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
172 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
173 "fpul", "fpscr",
174 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
175 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
176 "", "",
177 "", "", "", "", "", "", "", "",
178 "", "", "", "", "", "", "", "",
179 };
180 if (reg_nr < 0)
181 return NULL;
182 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
183 return NULL;
184 return register_names[reg_nr];
185 }
186
187 static const char *
188 sh_sh_dsp_register_name (int reg_nr)
189 {
190 static char *register_names[] =
191 {
192 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
193 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
194 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
195 "", "dsr",
196 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
197 "y0", "y1", "", "", "", "", "", "mod",
198 "", "",
199 "rs", "re", "", "", "", "", "", "",
200 "", "", "", "", "", "", "", "",
201 };
202 if (reg_nr < 0)
203 return NULL;
204 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
205 return NULL;
206 return register_names[reg_nr];
207 }
208
209 static const char *
210 sh_sh3_dsp_register_name (int reg_nr)
211 {
212 static char *register_names[] =
213 {
214 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
215 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
216 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
217 "", "dsr",
218 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
219 "y0", "y1", "", "", "", "", "", "mod",
220 "ssr", "spc",
221 "rs", "re", "", "", "", "", "", "",
222 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b"
223 "", "", "", "", "", "", "", "",
224 };
225 if (reg_nr < 0)
226 return NULL;
227 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
228 return NULL;
229 return register_names[reg_nr];
230 }
231
232 static const char *
233 sh_sh4_register_name (int reg_nr)
234 {
235 static char *register_names[] =
236 {
237 /* general registers 0-15 */
238 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
239 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
240 /* 16 - 22 */
241 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
242 /* 23, 24 */
243 "fpul", "fpscr",
244 /* floating point registers 25 - 40 */
245 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
246 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
247 /* 41, 42 */
248 "ssr", "spc",
249 /* bank 0 43 - 50 */
250 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
251 /* bank 1 51 - 58 */
252 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
253 /* double precision (pseudo) 59 - 66 */
254 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
255 /* vectors (pseudo) 67 - 70 */
256 "fv0", "fv4", "fv8", "fv12",
257 /* FIXME: missing XF 71 - 86 */
258 /* FIXME: missing XD 87 - 94 */
259 };
260 if (reg_nr < 0)
261 return NULL;
262 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
263 return NULL;
264 return register_names[reg_nr];
265 }
266
267 static const unsigned char *
268 sh_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
269 {
270 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */
271 static unsigned char breakpoint[] = {0xc3, 0xc3};
272
273 *lenptr = sizeof (breakpoint);
274 return breakpoint;
275 }
276
277 static CORE_ADDR
278 sh_push_dummy_code (struct gdbarch *gdbarch,
279 CORE_ADDR sp, CORE_ADDR funaddr, int using_gcc,
280 struct value **args, int nargs,
281 struct type *value_type,
282 CORE_ADDR *real_pc, CORE_ADDR *bp_addr)
283 {
284 /* Allocate space sufficient for a breakpoint. */
285 sp = (sp - 2) & ~1;
286 /* Store the address of that breakpoint */
287 *bp_addr = sp;
288 /* sh always starts the call at the callee's entry point. */
289 *real_pc = funaddr;
290 return sp;
291 }
292
293 /* Prologue looks like
294 mov.l r14,@-r15
295 sts.l pr,@-r15
296 mov.l <regs>,@-r15
297 sub <room_for_loca_vars>,r15
298 mov r15,r14
299
300 Actually it can be more complicated than this but that's it, basically.
301 */
302
303 #define GET_SOURCE_REG(x) (((x) >> 4) & 0xf)
304 #define GET_TARGET_REG(x) (((x) >> 8) & 0xf)
305
306 /* STS.L PR,@-r15 0100111100100010
307 r15-4-->r15, PR-->(r15) */
308 #define IS_STS(x) ((x) == 0x4f22)
309
310 /* MOV.L Rm,@-r15 00101111mmmm0110
311 r15-4-->r15, Rm-->(R15) */
312 #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
313
314 /* MOV r15,r14 0110111011110011
315 r15-->r14 */
316 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
317
318 /* ADD #imm,r15 01111111iiiiiiii
319 r15+imm-->r15 */
320 #define IS_ADD_IMM_SP(x) (((x) & 0xff00) == 0x7f00)
321
322 #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
323 #define IS_SHLL_R3(x) ((x) == 0x4300)
324
325 /* ADD r3,r15 0011111100111100
326 r15+r3-->r15 */
327 #define IS_ADD_R3SP(x) ((x) == 0x3f3c)
328
329 /* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
330 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
331 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
332 /* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to
333 make this entirely clear. */
334 /* #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b) */
335 #define IS_FPUSH(x) (((x) & 0xff0f) == 0xff0b)
336
337 /* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011 4 <= m <= 7 */
338 #define IS_MOV_ARG_TO_REG(x) \
339 (((x) & 0xf00f) == 0x6003 && \
340 ((x) & 0x00f0) >= 0x0040 && \
341 ((x) & 0x00f0) <= 0x0070)
342 /* MOV.L Rm,@Rn 0010nnnnmmmm0010 n = 14, 4 <= m <= 7 */
343 #define IS_MOV_ARG_TO_IND_R14(x) \
344 (((x) & 0xff0f) == 0x2e02 && \
345 ((x) & 0x00f0) >= 0x0040 && \
346 ((x) & 0x00f0) <= 0x0070)
347 /* MOV.L Rm,@(disp*4,Rn) 00011110mmmmdddd n = 14, 4 <= m <= 7 */
348 #define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \
349 (((x) & 0xff00) == 0x1e00 && \
350 ((x) & 0x00f0) >= 0x0040 && \
351 ((x) & 0x00f0) <= 0x0070)
352
353 /* MOV.W @(disp*2,PC),Rn 1001nnnndddddddd */
354 #define IS_MOVW_PCREL_TO_REG(x) (((x) & 0xf000) == 0x9000)
355 /* MOV.L @(disp*4,PC),Rn 1101nnnndddddddd */
356 #define IS_MOVL_PCREL_TO_REG(x) (((x) & 0xf000) == 0xd000)
357 /* SUB Rn,R15 00111111nnnn1000 */
358 #define IS_SUB_REG_FROM_SP(x) (((x) & 0xff0f) == 0x3f08)
359
360 #define FPSCR_SZ (1 << 20)
361
362 /* The following instructions are used for epilogue testing. */
363 #define IS_RESTORE_FP(x) ((x) == 0x6ef6)
364 #define IS_RTS(x) ((x) == 0x000b)
365 #define IS_LDS(x) ((x) == 0x4f26)
366 #define IS_MOV_FP_SP(x) ((x) == 0x6fe3)
367 #define IS_ADD_REG_TO_FP(x) (((x) & 0xff0f) == 0x3e0c)
368 #define IS_ADD_IMM_FP(x) (((x) & 0xff00) == 0x7e00)
369
370 /* Disassemble an instruction. */
371 static int
372 gdb_print_insn_sh (bfd_vma memaddr, disassemble_info *info)
373 {
374 info->endian = TARGET_BYTE_ORDER;
375 return print_insn_sh (memaddr, info);
376 }
377
378 static CORE_ADDR
379 sh_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc,
380 struct sh_frame_cache *cache)
381 {
382 ULONGEST inst;
383 CORE_ADDR opc;
384 int offset;
385 int sav_offset = 0;
386 int r3_val = 0;
387 int reg, sav_reg = -1;
388
389 if (pc >= current_pc)
390 return current_pc;
391
392 cache->uses_fp = 0;
393 for (opc = pc + (2 * 28); pc < opc; pc += 2)
394 {
395 inst = read_memory_unsigned_integer (pc, 2);
396 /* See where the registers will be saved to */
397 if (IS_PUSH (inst))
398 {
399 cache->saved_regs[GET_SOURCE_REG (inst)] = cache->sp_offset;
400 cache->sp_offset += 4;
401 }
402 else if (IS_STS (inst))
403 {
404 cache->saved_regs[PR_REGNUM] = cache->sp_offset;
405 cache->sp_offset += 4;
406 }
407 else if (IS_MOV_R3 (inst))
408 {
409 r3_val = ((inst & 0xff) ^ 0x80) - 0x80;
410 }
411 else if (IS_SHLL_R3 (inst))
412 {
413 r3_val <<= 1;
414 }
415 else if (IS_ADD_R3SP (inst))
416 {
417 cache->sp_offset += -r3_val;
418 }
419 else if (IS_ADD_IMM_SP (inst))
420 {
421 offset = ((inst & 0xff) ^ 0x80) - 0x80;
422 cache->sp_offset -= offset;
423 }
424 else if (IS_MOVW_PCREL_TO_REG (inst))
425 {
426 if (sav_reg < 0)
427 {
428 reg = GET_TARGET_REG (inst);
429 if (reg < 14)
430 {
431 sav_reg = reg;
432 offset = (((inst & 0xff) ^ 0x80) - 0x80) << 1;
433 sav_offset =
434 read_memory_integer (((pc + 4) & ~3) + offset, 2);
435 }
436 }
437 }
438 else if (IS_MOVL_PCREL_TO_REG (inst))
439 {
440 if (sav_reg < 0)
441 {
442 reg = (inst & 0x0f00) >> 8;
443 if (reg < 14)
444 {
445 sav_reg = reg;
446 offset = (((inst & 0xff) ^ 0x80) - 0x80) << 1;
447 sav_offset =
448 read_memory_integer (((pc + 4) & ~3) + offset, 4);
449 }
450 }
451 }
452 else if (IS_SUB_REG_FROM_SP (inst))
453 {
454 reg = GET_SOURCE_REG (inst);
455 if (sav_reg > 0 && reg == sav_reg)
456 {
457 sav_reg = -1;
458 }
459 cache->sp_offset += sav_offset;
460 }
461 else if (IS_FPUSH (inst))
462 {
463 if (read_register (FPSCR_REGNUM) & FPSCR_SZ)
464 {
465 cache->sp_offset += 8;
466 }
467 else
468 {
469 cache->sp_offset += 4;
470 }
471 }
472 else if (IS_MOV_SP_FP (inst))
473 {
474 if (!cache->uses_fp)
475 cache->uses_fp = 1;
476 /* At this point, only allow argument register moves to other
477 registers or argument register moves to @(X,fp) which are
478 moving the register arguments onto the stack area allocated
479 by a former add somenumber to SP call. Don't allow moving
480 to an fp indirect address above fp + cache->sp_offset. */
481 pc += 2;
482 for (opc = pc + 12; pc < opc; pc += 2)
483 {
484 inst = read_memory_integer (pc, 2);
485 if (IS_MOV_ARG_TO_IND_R14 (inst))
486 {
487 reg = GET_SOURCE_REG (inst);
488 if (cache->sp_offset > 0)
489 cache->saved_regs[reg] = cache->sp_offset;
490 }
491 else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst))
492 {
493 reg = GET_SOURCE_REG (inst);
494 offset = (inst & 0xf) * 4;
495 if (cache->sp_offset > offset)
496 cache->saved_regs[reg] = cache->sp_offset - offset;
497 }
498 else if (IS_MOV_ARG_TO_REG (inst))
499 continue;
500 else
501 break;
502 }
503 break;
504 }
505 #if 0 /* This used to just stop when it found an instruction that
506 was not considered part of the prologue. Now, we just
507 keep going looking for likely instructions. */
508 else
509 break;
510 #endif
511 }
512
513 return pc;
514 }
515
516 /* Skip any prologue before the guts of a function */
517
518 /* Skip the prologue using the debug information. If this fails we'll
519 fall back on the 'guess' method below. */
520 static CORE_ADDR
521 after_prologue (CORE_ADDR pc)
522 {
523 struct symtab_and_line sal;
524 CORE_ADDR func_addr, func_end;
525
526 /* If we can not find the symbol in the partial symbol table, then
527 there is no hope we can determine the function's start address
528 with this code. */
529 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
530 return 0;
531
532 /* Get the line associated with FUNC_ADDR. */
533 sal = find_pc_line (func_addr, 0);
534
535 /* There are only two cases to consider. First, the end of the source line
536 is within the function bounds. In that case we return the end of the
537 source line. Second is the end of the source line extends beyond the
538 bounds of the current function. We need to use the slow code to
539 examine instructions in that case. */
540 if (sal.end < func_end)
541 return sal.end;
542 else
543 return 0;
544 }
545
546 static CORE_ADDR
547 sh_skip_prologue (CORE_ADDR start_pc)
548 {
549 CORE_ADDR pc;
550 struct sh_frame_cache cache;
551
552 /* See if we can determine the end of the prologue via the symbol table.
553 If so, then return either PC, or the PC after the prologue, whichever
554 is greater. */
555 pc = after_prologue (start_pc);
556
557 /* If after_prologue returned a useful address, then use it. Else
558 fall back on the instruction skipping code. */
559 if (pc)
560 return max (pc, start_pc);
561
562 cache.sp_offset = -4;
563 pc = sh_analyze_prologue (start_pc, (CORE_ADDR) -1, &cache);
564 if (!cache.uses_fp)
565 return start_pc;
566
567 return pc;
568 }
569
570 /* Should call_function allocate stack space for a struct return? */
571 static int
572 sh_use_struct_convention (int gcc_p, struct type *type)
573 {
574 int len = TYPE_LENGTH (type);
575 int nelem = TYPE_NFIELDS (type);
576 return ((len != 1 && len != 2 && len != 4 && len != 8) || nelem != 1) &&
577 (len != 8 || TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) != 4);
578 }
579
580 /* Extract from an array REGBUF containing the (raw) register state
581 the address in which a function should return its structure value,
582 as a CORE_ADDR (or an expression that can be used as one). */
583 static CORE_ADDR
584 sh_extract_struct_value_address (struct regcache *regcache)
585 {
586 ULONGEST addr;
587
588 regcache_cooked_read_unsigned (regcache, STRUCT_RETURN_REGNUM, &addr);
589 return addr;
590 }
591
592 static CORE_ADDR
593 sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
594 {
595 return sp & ~3;
596 }
597
598 /* Function: push_dummy_call (formerly push_arguments)
599 Setup the function arguments for calling a function in the inferior.
600
601 On the Hitachi SH architecture, there are four registers (R4 to R7)
602 which are dedicated for passing function arguments. Up to the first
603 four arguments (depending on size) may go into these registers.
604 The rest go on the stack.
605
606 MVS: Except on SH variants that have floating point registers.
607 In that case, float and double arguments are passed in the same
608 manner, but using FP registers instead of GP registers.
609
610 Arguments that are smaller than 4 bytes will still take up a whole
611 register or a whole 32-bit word on the stack, and will be
612 right-justified in the register or the stack word. This includes
613 chars, shorts, and small aggregate types.
614
615 Arguments that are larger than 4 bytes may be split between two or
616 more registers. If there are not enough registers free, an argument
617 may be passed partly in a register (or registers), and partly on the
618 stack. This includes doubles, long longs, and larger aggregates.
619 As far as I know, there is no upper limit to the size of aggregates
620 that will be passed in this way; in other words, the convention of
621 passing a pointer to a large aggregate instead of a copy is not used.
622
623 MVS: The above appears to be true for the SH variants that do not
624 have an FPU, however those that have an FPU appear to copy the
625 aggregate argument onto the stack (and not place it in registers)
626 if it is larger than 16 bytes (four GP registers).
627
628 An exceptional case exists for struct arguments (and possibly other
629 aggregates such as arrays) if the size is larger than 4 bytes but
630 not a multiple of 4 bytes. In this case the argument is never split
631 between the registers and the stack, but instead is copied in its
632 entirety onto the stack, AND also copied into as many registers as
633 there is room for. In other words, space in registers permitting,
634 two copies of the same argument are passed in. As far as I can tell,
635 only the one on the stack is used, although that may be a function
636 of the level of compiler optimization. I suspect this is a compiler
637 bug. Arguments of these odd sizes are left-justified within the
638 word (as opposed to arguments smaller than 4 bytes, which are
639 right-justified).
640
641 If the function is to return an aggregate type such as a struct, it
642 is either returned in the normal return value register R0 (if its
643 size is no greater than one byte), or else the caller must allocate
644 space into which the callee will copy the return value (if the size
645 is greater than one byte). In this case, a pointer to the return
646 value location is passed into the callee in register R2, which does
647 not displace any of the other arguments passed in via registers R4
648 to R7. */
649
650 static CORE_ADDR
651 sh_push_dummy_call_fpu (struct gdbarch *gdbarch,
652 CORE_ADDR func_addr,
653 struct regcache *regcache,
654 CORE_ADDR bp_addr, int nargs,
655 struct value **args,
656 CORE_ADDR sp, int struct_return,
657 CORE_ADDR struct_addr)
658 {
659 int stack_offset, stack_alloc;
660 int argreg, flt_argreg;
661 int argnum;
662 struct type *type;
663 CORE_ADDR regval;
664 char *val;
665 char valbuf[4];
666 int len;
667 int odd_sized_struct;
668
669 /* first force sp to a 4-byte alignment */
670 sp = sh_frame_align (gdbarch, sp);
671
672 if (struct_return)
673 regcache_cooked_write_unsigned (regcache,
674 STRUCT_RETURN_REGNUM,
675 struct_addr);
676
677 /* Now make sure there's space on the stack */
678 for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++)
679 stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[argnum])) + 3) & ~3);
680 sp -= stack_alloc; /* make room on stack for args */
681
682 /* Now load as many as possible of the first arguments into
683 registers, and push the rest onto the stack. There are 16 bytes
684 in four registers available. Loop thru args from first to last. */
685
686 argreg = ARG0_REGNUM;
687 flt_argreg = FLOAT_ARG0_REGNUM;
688 for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++)
689 {
690 type = VALUE_TYPE (args[argnum]);
691 len = TYPE_LENGTH (type);
692 memset (valbuf, 0, sizeof (valbuf));
693 if (len < 4)
694 {
695 /* value gets right-justified in the register or stack word */
696 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
697 memcpy (valbuf + (4 - len),
698 (char *) VALUE_CONTENTS (args[argnum]), len);
699 else
700 memcpy (valbuf, (char *) VALUE_CONTENTS (args[argnum]), len);
701 val = valbuf;
702 }
703 else
704 val = (char *) VALUE_CONTENTS (args[argnum]);
705
706 if (len > 4 && (len & 3) != 0)
707 odd_sized_struct = 1; /* Such structs go entirely on stack. */
708 else if (len > 16)
709 odd_sized_struct = 1; /* So do aggregates bigger than 4 words. */
710 else
711 odd_sized_struct = 0;
712 while (len > 0)
713 {
714 if ((TYPE_CODE (type) == TYPE_CODE_FLT
715 && flt_argreg > FLOAT_ARGLAST_REGNUM)
716 || argreg > ARGLAST_REGNUM
717 || odd_sized_struct)
718 {
719 /* must go on the stack */
720 write_memory (sp + stack_offset, val, 4);
721 stack_offset += 4;
722 }
723 /* NOTE WELL!!!!! This is not an "else if" clause!!!
724 That's because some *&^%$ things get passed on the stack
725 AND in the registers! */
726 if (TYPE_CODE (type) == TYPE_CODE_FLT &&
727 flt_argreg > 0 && flt_argreg <= FLOAT_ARGLAST_REGNUM)
728 {
729 /* Argument goes in a single-precision fp reg. */
730 regval = extract_unsigned_integer (val, register_size (gdbarch,
731 argreg));
732 regcache_cooked_write_unsigned (regcache, flt_argreg++, regval);
733 }
734 else if (argreg <= ARGLAST_REGNUM)
735 {
736 /* there's room in a register */
737 regval = extract_unsigned_integer (val, register_size (gdbarch,
738 argreg));
739 regcache_cooked_write_unsigned (regcache, argreg++, regval);
740 }
741 /* Store the value 4 bytes at a time. This means that things
742 larger than 4 bytes may go partly in registers and partly
743 on the stack. */
744 len -= register_size (gdbarch, argreg);
745 val += register_size (gdbarch, argreg);
746 }
747 }
748
749 /* Store return address. */
750 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
751
752 /* Update stack pointer. */
753 regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp);
754
755 return sp;
756 }
757
758 static CORE_ADDR
759 sh_push_dummy_call_nofpu (struct gdbarch *gdbarch,
760 CORE_ADDR func_addr,
761 struct regcache *regcache,
762 CORE_ADDR bp_addr,
763 int nargs, struct value **args,
764 CORE_ADDR sp, int struct_return,
765 CORE_ADDR struct_addr)
766 {
767 int stack_offset, stack_alloc;
768 int argreg;
769 int argnum;
770 struct type *type;
771 CORE_ADDR regval;
772 char *val;
773 char valbuf[4];
774 int len;
775 int odd_sized_struct;
776
777 /* first force sp to a 4-byte alignment */
778 sp = sh_frame_align (gdbarch, sp);
779
780 if (struct_return)
781 regcache_cooked_write_unsigned (regcache,
782 STRUCT_RETURN_REGNUM,
783 struct_addr);
784
785 /* Now make sure there's space on the stack */
786 for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++)
787 stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[argnum])) + 3) & ~3);
788 sp -= stack_alloc; /* make room on stack for args */
789
790 /* Now load as many as possible of the first arguments into
791 registers, and push the rest onto the stack. There are 16 bytes
792 in four registers available. Loop thru args from first to last. */
793
794 argreg = ARG0_REGNUM;
795 for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++)
796 {
797 type = VALUE_TYPE (args[argnum]);
798 len = TYPE_LENGTH (type);
799 memset (valbuf, 0, sizeof (valbuf));
800 if (len < 4)
801 {
802 /* value gets right-justified in the register or stack word */
803 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
804 memcpy (valbuf + (4 - len),
805 (char *) VALUE_CONTENTS (args[argnum]), len);
806 else
807 memcpy (valbuf, (char *) VALUE_CONTENTS (args[argnum]), len);
808 val = valbuf;
809 }
810 else
811 val = (char *) VALUE_CONTENTS (args[argnum]);
812
813 if (len > 4 && (len & 3) != 0)
814 odd_sized_struct = 1; /* such structs go entirely on stack */
815 else
816 odd_sized_struct = 0;
817 while (len > 0)
818 {
819 if (argreg > ARGLAST_REGNUM
820 || odd_sized_struct)
821 {
822 /* must go on the stack */
823 write_memory (sp + stack_offset, val, 4);
824 stack_offset += 4;
825 }
826 /* NOTE WELL!!!!! This is not an "else if" clause!!!
827 That's because some *&^%$ things get passed on the stack
828 AND in the registers! */
829 if (argreg <= ARGLAST_REGNUM)
830 {
831 /* there's room in a register */
832 regval = extract_unsigned_integer (val, register_size (gdbarch,
833 argreg));
834 regcache_cooked_write_unsigned (regcache, argreg++, regval);
835 }
836 /* Store the value 4 bytes at a time. This means that things
837 larger than 4 bytes may go partly in registers and partly
838 on the stack. */
839 len -= register_size (gdbarch, argreg);
840 val += register_size (gdbarch, argreg);
841 }
842 }
843
844 /* Store return address. */
845 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
846
847 /* Update stack pointer. */
848 regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp);
849
850 return sp;
851 }
852
853 /* Find a function's return value in the appropriate registers (in
854 regbuf), and copy it into valbuf. Extract from an array REGBUF
855 containing the (raw) register state a function return value of type
856 TYPE, and copy that, in virtual format, into VALBUF. */
857 static void
858 sh_default_extract_return_value (struct type *type, struct regcache *regcache,
859 void *valbuf)
860 {
861 int len = TYPE_LENGTH (type);
862 int return_register = R0_REGNUM;
863 int offset;
864
865 if (len <= 4)
866 {
867 ULONGEST c;
868
869 regcache_cooked_read_unsigned (regcache, R0_REGNUM, &c);
870 store_unsigned_integer (valbuf, len, c);
871 }
872 else if (len == 8)
873 {
874 int i, regnum = R0_REGNUM;
875 for (i = 0; i < len; i += 4)
876 regcache_raw_read (regcache, regnum++, (char *)valbuf + i);
877 }
878 else
879 error ("bad size for return value");
880 }
881
882 static void
883 sh3e_sh4_extract_return_value (struct type *type, struct regcache *regcache,
884 void *valbuf)
885 {
886 if (TYPE_CODE (type) == TYPE_CODE_FLT)
887 {
888 int len = TYPE_LENGTH (type);
889 int i, regnum = FP0_REGNUM;
890 for (i = 0; i < len; i += 4)
891 regcache_raw_read (regcache, regnum++, (char *)valbuf + i);
892 }
893 else
894 sh_default_extract_return_value (type, regcache, valbuf);
895 }
896
897 /* Write into appropriate registers a function return value
898 of type TYPE, given in virtual format.
899 If the architecture is sh4 or sh3e, store a function's return value
900 in the R0 general register or in the FP0 floating point register,
901 depending on the type of the return value. In all the other cases
902 the result is stored in r0, left-justified. */
903 static void
904 sh_default_store_return_value (struct type *type, struct regcache *regcache,
905 const void *valbuf)
906 {
907 ULONGEST val;
908 int len = TYPE_LENGTH (type);
909
910 if (len <= 4)
911 {
912 val = extract_unsigned_integer (valbuf, len);
913 regcache_cooked_write_unsigned (regcache, R0_REGNUM, val);
914 }
915 else
916 {
917 int i, regnum = R0_REGNUM;
918 for (i = 0; i < len; i += 4)
919 regcache_raw_write (regcache, regnum++, (char *)valbuf + i);
920 }
921 }
922
923 static void
924 sh3e_sh4_store_return_value (struct type *type, struct regcache *regcache,
925 const void *valbuf)
926 {
927 if (TYPE_CODE (type) == TYPE_CODE_FLT)
928 {
929 int len = TYPE_LENGTH (type);
930 int i, regnum = FP0_REGNUM;
931 for (i = 0; i < len; i += 4)
932 regcache_raw_write (regcache, regnum++, (char *)valbuf + i);
933 }
934 else
935 sh_default_store_return_value (type, regcache, valbuf);
936 }
937
938 /* Print the registers in a form similar to the E7000 */
939
940 static void
941 sh_generic_show_regs (void)
942 {
943 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
944 paddr (read_register (PC_REGNUM)),
945 (long) read_register (SR_REGNUM),
946 (long) read_register (PR_REGNUM),
947 (long) read_register (MACH_REGNUM),
948 (long) read_register (MACL_REGNUM));
949
950 printf_filtered ("GBR=%08lx VBR=%08lx",
951 (long) read_register (GBR_REGNUM),
952 (long) read_register (VBR_REGNUM));
953
954 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
955 (long) read_register (0),
956 (long) read_register (1),
957 (long) read_register (2),
958 (long) read_register (3),
959 (long) read_register (4),
960 (long) read_register (5),
961 (long) read_register (6),
962 (long) read_register (7));
963 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
964 (long) read_register (8),
965 (long) read_register (9),
966 (long) read_register (10),
967 (long) read_register (11),
968 (long) read_register (12),
969 (long) read_register (13),
970 (long) read_register (14),
971 (long) read_register (15));
972 }
973
974 static void
975 sh3_show_regs (void)
976 {
977 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
978 paddr (read_register (PC_REGNUM)),
979 (long) read_register (SR_REGNUM),
980 (long) read_register (PR_REGNUM),
981 (long) read_register (MACH_REGNUM),
982 (long) read_register (MACL_REGNUM));
983
984 printf_filtered ("GBR=%08lx VBR=%08lx",
985 (long) read_register (GBR_REGNUM),
986 (long) read_register (VBR_REGNUM));
987 printf_filtered (" SSR=%08lx SPC=%08lx",
988 (long) read_register (SSR_REGNUM),
989 (long) read_register (SPC_REGNUM));
990
991 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
992 (long) read_register (0),
993 (long) read_register (1),
994 (long) read_register (2),
995 (long) read_register (3),
996 (long) read_register (4),
997 (long) read_register (5),
998 (long) read_register (6),
999 (long) read_register (7));
1000 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1001 (long) read_register (8),
1002 (long) read_register (9),
1003 (long) read_register (10),
1004 (long) read_register (11),
1005 (long) read_register (12),
1006 (long) read_register (13),
1007 (long) read_register (14),
1008 (long) read_register (15));
1009 }
1010
1011
1012 static void
1013 sh2e_show_regs (void)
1014 {
1015 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1016 paddr (read_register (PC_REGNUM)),
1017 (long) read_register (SR_REGNUM),
1018 (long) read_register (PR_REGNUM),
1019 (long) read_register (MACH_REGNUM),
1020 (long) read_register (MACL_REGNUM));
1021
1022 printf_filtered ("GBR=%08lx VBR=%08lx",
1023 (long) read_register (GBR_REGNUM),
1024 (long) read_register (VBR_REGNUM));
1025 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1026 (long) read_register (FPUL_REGNUM),
1027 (long) read_register (FPSCR_REGNUM));
1028
1029 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1030 (long) read_register (0),
1031 (long) read_register (1),
1032 (long) read_register (2),
1033 (long) read_register (3),
1034 (long) read_register (4),
1035 (long) read_register (5),
1036 (long) read_register (6),
1037 (long) read_register (7));
1038 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1039 (long) read_register (8),
1040 (long) read_register (9),
1041 (long) read_register (10),
1042 (long) read_register (11),
1043 (long) read_register (12),
1044 (long) read_register (13),
1045 (long) read_register (14),
1046 (long) read_register (15));
1047
1048 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1049 (long) read_register (FP0_REGNUM + 0),
1050 (long) read_register (FP0_REGNUM + 1),
1051 (long) read_register (FP0_REGNUM + 2),
1052 (long) read_register (FP0_REGNUM + 3),
1053 (long) read_register (FP0_REGNUM + 4),
1054 (long) read_register (FP0_REGNUM + 5),
1055 (long) read_register (FP0_REGNUM + 6),
1056 (long) read_register (FP0_REGNUM + 7));
1057 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1058 (long) read_register (FP0_REGNUM + 8),
1059 (long) read_register (FP0_REGNUM + 9),
1060 (long) read_register (FP0_REGNUM + 10),
1061 (long) read_register (FP0_REGNUM + 11),
1062 (long) read_register (FP0_REGNUM + 12),
1063 (long) read_register (FP0_REGNUM + 13),
1064 (long) read_register (FP0_REGNUM + 14),
1065 (long) read_register (FP0_REGNUM + 15));
1066 }
1067
1068 static void
1069 sh3e_show_regs (void)
1070 {
1071 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1072 paddr (read_register (PC_REGNUM)),
1073 (long) read_register (SR_REGNUM),
1074 (long) read_register (PR_REGNUM),
1075 (long) read_register (MACH_REGNUM),
1076 (long) read_register (MACL_REGNUM));
1077
1078 printf_filtered ("GBR=%08lx VBR=%08lx",
1079 (long) read_register (GBR_REGNUM),
1080 (long) read_register (VBR_REGNUM));
1081 printf_filtered (" SSR=%08lx SPC=%08lx",
1082 (long) read_register (SSR_REGNUM),
1083 (long) read_register (SPC_REGNUM));
1084 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1085 (long) read_register (FPUL_REGNUM),
1086 (long) read_register (FPSCR_REGNUM));
1087
1088 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1089 (long) read_register (0),
1090 (long) read_register (1),
1091 (long) read_register (2),
1092 (long) read_register (3),
1093 (long) read_register (4),
1094 (long) read_register (5),
1095 (long) read_register (6),
1096 (long) read_register (7));
1097 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1098 (long) read_register (8),
1099 (long) read_register (9),
1100 (long) read_register (10),
1101 (long) read_register (11),
1102 (long) read_register (12),
1103 (long) read_register (13),
1104 (long) read_register (14),
1105 (long) read_register (15));
1106
1107 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1108 (long) read_register (FP0_REGNUM + 0),
1109 (long) read_register (FP0_REGNUM + 1),
1110 (long) read_register (FP0_REGNUM + 2),
1111 (long) read_register (FP0_REGNUM + 3),
1112 (long) read_register (FP0_REGNUM + 4),
1113 (long) read_register (FP0_REGNUM + 5),
1114 (long) read_register (FP0_REGNUM + 6),
1115 (long) read_register (FP0_REGNUM + 7));
1116 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1117 (long) read_register (FP0_REGNUM + 8),
1118 (long) read_register (FP0_REGNUM + 9),
1119 (long) read_register (FP0_REGNUM + 10),
1120 (long) read_register (FP0_REGNUM + 11),
1121 (long) read_register (FP0_REGNUM + 12),
1122 (long) read_register (FP0_REGNUM + 13),
1123 (long) read_register (FP0_REGNUM + 14),
1124 (long) read_register (FP0_REGNUM + 15));
1125 }
1126
1127 static void
1128 sh3_dsp_show_regs (void)
1129 {
1130 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1131 paddr (read_register (PC_REGNUM)),
1132 (long) read_register (SR_REGNUM),
1133 (long) read_register (PR_REGNUM),
1134 (long) read_register (MACH_REGNUM),
1135 (long) read_register (MACL_REGNUM));
1136
1137 printf_filtered ("GBR=%08lx VBR=%08lx",
1138 (long) read_register (GBR_REGNUM),
1139 (long) read_register (VBR_REGNUM));
1140
1141 printf_filtered (" SSR=%08lx SPC=%08lx",
1142 (long) read_register (SSR_REGNUM),
1143 (long) read_register (SPC_REGNUM));
1144
1145 printf_filtered (" DSR=%08lx",
1146 (long) read_register (DSR_REGNUM));
1147
1148 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1149 (long) read_register (0),
1150 (long) read_register (1),
1151 (long) read_register (2),
1152 (long) read_register (3),
1153 (long) read_register (4),
1154 (long) read_register (5),
1155 (long) read_register (6),
1156 (long) read_register (7));
1157 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1158 (long) read_register (8),
1159 (long) read_register (9),
1160 (long) read_register (10),
1161 (long) read_register (11),
1162 (long) read_register (12),
1163 (long) read_register (13),
1164 (long) read_register (14),
1165 (long) read_register (15));
1166
1167 printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1168 (long) read_register (A0G_REGNUM) & 0xff,
1169 (long) read_register (A0_REGNUM),
1170 (long) read_register (M0_REGNUM),
1171 (long) read_register (X0_REGNUM),
1172 (long) read_register (Y0_REGNUM),
1173 (long) read_register (RS_REGNUM),
1174 (long) read_register (MOD_REGNUM));
1175 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1176 (long) read_register (A1G_REGNUM) & 0xff,
1177 (long) read_register (A1_REGNUM),
1178 (long) read_register (M1_REGNUM),
1179 (long) read_register (X1_REGNUM),
1180 (long) read_register (Y1_REGNUM),
1181 (long) read_register (RE_REGNUM));
1182 }
1183
1184 static void
1185 sh4_show_regs (void)
1186 {
1187 int pr = read_register (FPSCR_REGNUM) & 0x80000;
1188 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1189 paddr (read_register (PC_REGNUM)),
1190 (long) read_register (SR_REGNUM),
1191 (long) read_register (PR_REGNUM),
1192 (long) read_register (MACH_REGNUM),
1193 (long) read_register (MACL_REGNUM));
1194
1195 printf_filtered ("GBR=%08lx VBR=%08lx",
1196 (long) read_register (GBR_REGNUM),
1197 (long) read_register (VBR_REGNUM));
1198 printf_filtered (" SSR=%08lx SPC=%08lx",
1199 (long) read_register (SSR_REGNUM),
1200 (long) read_register (SPC_REGNUM));
1201 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1202 (long) read_register (FPUL_REGNUM),
1203 (long) read_register (FPSCR_REGNUM));
1204
1205 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1206 (long) read_register (0),
1207 (long) read_register (1),
1208 (long) read_register (2),
1209 (long) read_register (3),
1210 (long) read_register (4),
1211 (long) read_register (5),
1212 (long) read_register (6),
1213 (long) read_register (7));
1214 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1215 (long) read_register (8),
1216 (long) read_register (9),
1217 (long) read_register (10),
1218 (long) read_register (11),
1219 (long) read_register (12),
1220 (long) read_register (13),
1221 (long) read_register (14),
1222 (long) read_register (15));
1223
1224 printf_filtered ((pr
1225 ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1226 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1227 (long) read_register (FP0_REGNUM + 0),
1228 (long) read_register (FP0_REGNUM + 1),
1229 (long) read_register (FP0_REGNUM + 2),
1230 (long) read_register (FP0_REGNUM + 3),
1231 (long) read_register (FP0_REGNUM + 4),
1232 (long) read_register (FP0_REGNUM + 5),
1233 (long) read_register (FP0_REGNUM + 6),
1234 (long) read_register (FP0_REGNUM + 7));
1235 printf_filtered ((pr
1236 ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1237 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1238 (long) read_register (FP0_REGNUM + 8),
1239 (long) read_register (FP0_REGNUM + 9),
1240 (long) read_register (FP0_REGNUM + 10),
1241 (long) read_register (FP0_REGNUM + 11),
1242 (long) read_register (FP0_REGNUM + 12),
1243 (long) read_register (FP0_REGNUM + 13),
1244 (long) read_register (FP0_REGNUM + 14),
1245 (long) read_register (FP0_REGNUM + 15));
1246 }
1247
1248 static void
1249 sh_dsp_show_regs (void)
1250 {
1251 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1252 paddr (read_register (PC_REGNUM)),
1253 (long) read_register (SR_REGNUM),
1254 (long) read_register (PR_REGNUM),
1255 (long) read_register (MACH_REGNUM),
1256 (long) read_register (MACL_REGNUM));
1257
1258 printf_filtered ("GBR=%08lx VBR=%08lx",
1259 (long) read_register (GBR_REGNUM),
1260 (long) read_register (VBR_REGNUM));
1261
1262 printf_filtered (" DSR=%08lx",
1263 (long) read_register (DSR_REGNUM));
1264
1265 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1266 (long) read_register (0),
1267 (long) read_register (1),
1268 (long) read_register (2),
1269 (long) read_register (3),
1270 (long) read_register (4),
1271 (long) read_register (5),
1272 (long) read_register (6),
1273 (long) read_register (7));
1274 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1275 (long) read_register (8),
1276 (long) read_register (9),
1277 (long) read_register (10),
1278 (long) read_register (11),
1279 (long) read_register (12),
1280 (long) read_register (13),
1281 (long) read_register (14),
1282 (long) read_register (15));
1283
1284 printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1285 (long) read_register (A0G_REGNUM) & 0xff,
1286 (long) read_register (A0_REGNUM),
1287 (long) read_register (M0_REGNUM),
1288 (long) read_register (X0_REGNUM),
1289 (long) read_register (Y0_REGNUM),
1290 (long) read_register (RS_REGNUM),
1291 (long) read_register (MOD_REGNUM));
1292 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1293 (long) read_register (A1G_REGNUM) & 0xff,
1294 (long) read_register (A1_REGNUM),
1295 (long) read_register (M1_REGNUM),
1296 (long) read_register (X1_REGNUM),
1297 (long) read_register (Y1_REGNUM),
1298 (long) read_register (RE_REGNUM));
1299 }
1300
1301 static void
1302 sh_show_regs_command (char *args, int from_tty)
1303 {
1304 if (sh_show_regs)
1305 (*sh_show_regs)();
1306 }
1307
1308 /* Return the GDB type object for the "standard" data type
1309 of data in register N. */
1310 static struct type *
1311 sh_sh3e_register_type (struct gdbarch *gdbarch, int reg_nr)
1312 {
1313 if ((reg_nr >= FP0_REGNUM
1314 && (reg_nr <= FP_LAST_REGNUM))
1315 || (reg_nr == FPUL_REGNUM))
1316 return builtin_type_float;
1317 else
1318 return builtin_type_int;
1319 }
1320
1321 static struct type *
1322 sh_sh4_build_float_register_type (int high)
1323 {
1324 struct type *temp;
1325
1326 temp = create_range_type (NULL, builtin_type_int, 0, high);
1327 return create_array_type (NULL, builtin_type_float, temp);
1328 }
1329
1330 static struct type *
1331 sh_sh4_register_type (struct gdbarch *gdbarch, int reg_nr)
1332 {
1333 if ((reg_nr >= FP0_REGNUM
1334 && (reg_nr <= FP_LAST_REGNUM))
1335 || (reg_nr == FPUL_REGNUM))
1336 return builtin_type_float;
1337 else if (reg_nr >= DR0_REGNUM
1338 && reg_nr <= DR_LAST_REGNUM)
1339 return builtin_type_double;
1340 else if (reg_nr >= FV0_REGNUM
1341 && reg_nr <= FV_LAST_REGNUM)
1342 return sh_sh4_build_float_register_type (3);
1343 else
1344 return builtin_type_int;
1345 }
1346
1347 static struct type *
1348 sh_default_register_type (struct gdbarch *gdbarch, int reg_nr)
1349 {
1350 return builtin_type_int;
1351 }
1352
1353 /* On the sh4, the DRi pseudo registers are problematic if the target
1354 is little endian. When the user writes one of those registers, for
1355 instance with 'ser var $dr0=1', we want the double to be stored
1356 like this:
1357 fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
1358 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1359
1360 This corresponds to little endian byte order & big endian word
1361 order. However if we let gdb write the register w/o conversion, it
1362 will write fr0 and fr1 this way:
1363 fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1364 fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
1365 because it will consider fr0 and fr1 as a single LE stretch of memory.
1366
1367 To achieve what we want we must force gdb to store things in
1368 floatformat_ieee_double_littlebyte_bigword (which is defined in
1369 include/floatformat.h and libiberty/floatformat.c.
1370
1371 In case the target is big endian, there is no problem, the
1372 raw bytes will look like:
1373 fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
1374 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1375
1376 The other pseudo registers (the FVs) also don't pose a problem
1377 because they are stored as 4 individual FP elements. */
1378
1379 static void
1380 sh_sh4_register_convert_to_virtual (int regnum, struct type *type,
1381 char *from, char *to)
1382 {
1383 if (regnum >= DR0_REGNUM
1384 && regnum <= DR_LAST_REGNUM)
1385 {
1386 DOUBLEST val;
1387 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, from, &val);
1388 store_typed_floating (to, type, val);
1389 }
1390 else
1391 error ("sh_register_convert_to_virtual called with non DR register number");
1392 }
1393
1394 static void
1395 sh_sh4_register_convert_to_raw (struct type *type, int regnum,
1396 const void *from, void *to)
1397 {
1398 if (regnum >= DR0_REGNUM
1399 && regnum <= DR_LAST_REGNUM)
1400 {
1401 DOUBLEST val = extract_typed_floating (from, type);
1402 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword, &val, to);
1403 }
1404 else
1405 error("sh_register_convert_to_raw called with non DR register number");
1406 }
1407
1408 /* For vectors of 4 floating point registers. */
1409 static int
1410 fv_reg_base_num (int fv_regnum)
1411 {
1412 int fp_regnum;
1413
1414 fp_regnum = FP0_REGNUM +
1415 (fv_regnum - FV0_REGNUM) * 4;
1416 return fp_regnum;
1417 }
1418
1419 /* For double precision floating point registers, i.e 2 fp regs.*/
1420 static int
1421 dr_reg_base_num (int dr_regnum)
1422 {
1423 int fp_regnum;
1424
1425 fp_regnum = FP0_REGNUM +
1426 (dr_regnum - DR0_REGNUM) * 2;
1427 return fp_regnum;
1428 }
1429
1430 static void
1431 sh_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
1432 int reg_nr, void *buffer)
1433 {
1434 int base_regnum, portion;
1435 char temp_buffer[MAX_REGISTER_SIZE];
1436
1437 if (reg_nr >= DR0_REGNUM
1438 && reg_nr <= DR_LAST_REGNUM)
1439 {
1440 base_regnum = dr_reg_base_num (reg_nr);
1441
1442 /* Build the value in the provided buffer. */
1443 /* Read the real regs for which this one is an alias. */
1444 for (portion = 0; portion < 2; portion++)
1445 regcache_raw_read (regcache, base_regnum + portion,
1446 (temp_buffer
1447 + register_size (gdbarch, base_regnum) * portion));
1448 /* We must pay attention to the endiannes. */
1449 sh_sh4_register_convert_to_virtual (reg_nr,
1450 gdbarch_register_type (gdbarch, reg_nr),
1451 temp_buffer, buffer);
1452 }
1453 else if (reg_nr >= FV0_REGNUM
1454 && reg_nr <= FV_LAST_REGNUM)
1455 {
1456 base_regnum = fv_reg_base_num (reg_nr);
1457
1458 /* Read the real regs for which this one is an alias. */
1459 for (portion = 0; portion < 4; portion++)
1460 regcache_raw_read (regcache, base_regnum + portion,
1461 ((char *) buffer
1462 + register_size (gdbarch, base_regnum) * portion));
1463 }
1464 }
1465
1466 static void
1467 sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
1468 int reg_nr, const void *buffer)
1469 {
1470 int base_regnum, portion;
1471 char temp_buffer[MAX_REGISTER_SIZE];
1472
1473 if (reg_nr >= DR0_REGNUM
1474 && reg_nr <= DR_LAST_REGNUM)
1475 {
1476 base_regnum = dr_reg_base_num (reg_nr);
1477
1478 /* We must pay attention to the endiannes. */
1479 sh_sh4_register_convert_to_raw (gdbarch_register_type (gdbarch, reg_nr), reg_nr,
1480 buffer, temp_buffer);
1481
1482 /* Write the real regs for which this one is an alias. */
1483 for (portion = 0; portion < 2; portion++)
1484 regcache_raw_write (regcache, base_regnum + portion,
1485 (temp_buffer
1486 + register_size (gdbarch, base_regnum) * portion));
1487 }
1488 else if (reg_nr >= FV0_REGNUM
1489 && reg_nr <= FV_LAST_REGNUM)
1490 {
1491 base_regnum = fv_reg_base_num (reg_nr);
1492
1493 /* Write the real regs for which this one is an alias. */
1494 for (portion = 0; portion < 4; portion++)
1495 regcache_raw_write (regcache, base_regnum + portion,
1496 ((char *) buffer
1497 + register_size (gdbarch, base_regnum) * portion));
1498 }
1499 }
1500
1501 /* Floating point vector of 4 float registers. */
1502 static void
1503 do_fv_register_info (struct gdbarch *gdbarch, struct ui_file *file,
1504 int fv_regnum)
1505 {
1506 int first_fp_reg_num = fv_reg_base_num (fv_regnum);
1507 fprintf_filtered (file, "fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
1508 fv_regnum - FV0_REGNUM,
1509 (int) read_register (first_fp_reg_num),
1510 (int) read_register (first_fp_reg_num + 1),
1511 (int) read_register (first_fp_reg_num + 2),
1512 (int) read_register (first_fp_reg_num + 3));
1513 }
1514
1515 /* Double precision registers. */
1516 static void
1517 do_dr_register_info (struct gdbarch *gdbarch, struct ui_file *file,
1518 int dr_regnum)
1519 {
1520 int first_fp_reg_num = dr_reg_base_num (dr_regnum);
1521
1522 fprintf_filtered (file, "dr%d\t0x%08x%08x\n",
1523 dr_regnum - DR0_REGNUM,
1524 (int) read_register (first_fp_reg_num),
1525 (int) read_register (first_fp_reg_num + 1));
1526 }
1527
1528 static void
1529 sh_print_pseudo_register (struct gdbarch *gdbarch, struct ui_file *file,
1530 int regnum)
1531 {
1532 if (regnum < NUM_REGS || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
1533 internal_error (__FILE__, __LINE__,
1534 "Invalid pseudo register number %d\n", regnum);
1535 else if (regnum >= DR0_REGNUM
1536 && regnum <= DR_LAST_REGNUM)
1537 do_dr_register_info (gdbarch, file, regnum);
1538 else if (regnum >= FV0_REGNUM
1539 && regnum <= FV_LAST_REGNUM)
1540 do_fv_register_info (gdbarch, file, regnum);
1541 }
1542
1543 static void
1544 sh_do_fp_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
1545 { /* do values for FP (float) regs */
1546 char *raw_buffer;
1547 double flt; /* double extracted from raw hex data */
1548 int inv;
1549 int j;
1550
1551 /* Allocate space for the float. */
1552 raw_buffer = (char *) alloca (register_size (gdbarch, FP0_REGNUM));
1553
1554 /* Get the data in raw format. */
1555 if (!frame_register_read (get_selected_frame (), regnum, raw_buffer))
1556 error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum));
1557
1558 /* Get the register as a number */
1559 flt = unpack_double (builtin_type_float, raw_buffer, &inv);
1560
1561 /* Print the name and some spaces. */
1562 fputs_filtered (REGISTER_NAME (regnum), file);
1563 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file);
1564
1565 /* Print the value. */
1566 if (inv)
1567 fprintf_filtered (file, "<invalid float>");
1568 else
1569 fprintf_filtered (file, "%-10.9g", flt);
1570
1571 /* Print the fp register as hex. */
1572 fprintf_filtered (file, "\t(raw 0x");
1573 for (j = 0; j < register_size (gdbarch, regnum); j++)
1574 {
1575 register int idx = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? j
1576 : register_size (gdbarch, regnum) - 1 - j;
1577 fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[idx]);
1578 }
1579 fprintf_filtered (file, ")");
1580 fprintf_filtered (file, "\n");
1581 }
1582
1583 static void
1584 sh_do_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
1585 {
1586 char raw_buffer[MAX_REGISTER_SIZE];
1587
1588 fputs_filtered (REGISTER_NAME (regnum), file);
1589 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file);
1590
1591 /* Get the data in raw format. */
1592 if (!frame_register_read (get_selected_frame (), regnum, raw_buffer))
1593 fprintf_filtered (file, "*value not available*\n");
1594
1595 val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0,
1596 file, 'x', 1, 0, Val_pretty_default);
1597 fprintf_filtered (file, "\t");
1598 val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0,
1599 file, 0, 1, 0, Val_pretty_default);
1600 fprintf_filtered (file, "\n");
1601 }
1602
1603 static void
1604 sh_print_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
1605 {
1606 if (regnum < 0 || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
1607 internal_error (__FILE__, __LINE__,
1608 "Invalid register number %d\n", regnum);
1609
1610 else if (regnum >= 0 && regnum < NUM_REGS)
1611 {
1612 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT)
1613 sh_do_fp_register (gdbarch, file, regnum); /* FP regs */
1614 else
1615 sh_do_register (gdbarch, file, regnum); /* All other regs */
1616 }
1617
1618 else if (regnum < NUM_REGS + NUM_PSEUDO_REGS)
1619 {
1620 sh_print_pseudo_register (gdbarch, file, regnum);
1621 }
1622 }
1623
1624 static void
1625 sh_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
1626 struct frame_info *frame, int regnum, int fpregs)
1627 {
1628 if (regnum != -1) /* do one specified register */
1629 {
1630 if (*(REGISTER_NAME (regnum)) == '\0')
1631 error ("Not a valid register for the current processor type");
1632
1633 sh_print_register (gdbarch, file, regnum);
1634 }
1635 else
1636 /* do all (or most) registers */
1637 {
1638 regnum = 0;
1639 while (regnum < NUM_REGS)
1640 {
1641 /* If the register name is empty, it is undefined for this
1642 processor, so don't display anything. */
1643 if (REGISTER_NAME (regnum) == NULL
1644 || *(REGISTER_NAME (regnum)) == '\0')
1645 {
1646 regnum++;
1647 continue;
1648 }
1649
1650 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT)
1651 {
1652 if (fpregs)
1653 {
1654 /* true for "INFO ALL-REGISTERS" command */
1655 sh_do_fp_register (gdbarch, file, regnum); /* FP regs */
1656 regnum ++;
1657 }
1658 else
1659 regnum += (FP_LAST_REGNUM - FP0_REGNUM); /* skip FP regs */
1660 }
1661 else
1662 {
1663 sh_do_register (gdbarch, file, regnum); /* All other regs */
1664 regnum++;
1665 }
1666 }
1667
1668 if (fpregs)
1669 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
1670 {
1671 sh_print_pseudo_register (gdbarch, file, regnum);
1672 regnum++;
1673 }
1674 }
1675 }
1676
1677 #ifdef SVR4_SHARED_LIBS
1678
1679 /* Fetch (and possibly build) an appropriate link_map_offsets structure
1680 for native i386 linux targets using the struct offsets defined in
1681 link.h (but without actual reference to that file).
1682
1683 This makes it possible to access i386-linux shared libraries from
1684 a gdb that was not built on an i386-linux host (for cross debugging).
1685 */
1686
1687 struct link_map_offsets *
1688 sh_linux_svr4_fetch_link_map_offsets (void)
1689 {
1690 static struct link_map_offsets lmo;
1691 static struct link_map_offsets *lmp = 0;
1692
1693 if (lmp == 0)
1694 {
1695 lmp = &lmo;
1696
1697 lmo.r_debug_size = 8; /* 20 not actual size but all we need */
1698
1699 lmo.r_map_offset = 4;
1700 lmo.r_map_size = 4;
1701
1702 lmo.link_map_size = 20; /* 552 not actual size but all we need */
1703
1704 lmo.l_addr_offset = 0;
1705 lmo.l_addr_size = 4;
1706
1707 lmo.l_name_offset = 4;
1708 lmo.l_name_size = 4;
1709
1710 lmo.l_next_offset = 12;
1711 lmo.l_next_size = 4;
1712
1713 lmo.l_prev_offset = 16;
1714 lmo.l_prev_size = 4;
1715 }
1716
1717 return lmp;
1718 }
1719 #endif /* SVR4_SHARED_LIBS */
1720
1721 static int
1722 sh_dsp_register_sim_regno (int nr)
1723 {
1724 if (legacy_register_sim_regno (nr) < 0)
1725 return legacy_register_sim_regno (nr);
1726 if (nr >= DSR_REGNUM && nr <= Y1_REGNUM)
1727 return nr - DSR_REGNUM + SIM_SH_DSR_REGNUM;
1728 if (nr == MOD_REGNUM)
1729 return SIM_SH_MOD_REGNUM;
1730 if (nr == RS_REGNUM)
1731 return SIM_SH_RS_REGNUM;
1732 if (nr == RE_REGNUM)
1733 return SIM_SH_RE_REGNUM;
1734 if (nr >= R0_BANK_REGNUM && nr <= R7_BANK_REGNUM)
1735 return nr - R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM;
1736 return nr;
1737 }
1738
1739 static struct sh_frame_cache *
1740 sh_alloc_frame_cache (void)
1741 {
1742 struct sh_frame_cache *cache;
1743 int i;
1744
1745 cache = FRAME_OBSTACK_ZALLOC (struct sh_frame_cache);
1746
1747 /* Base address. */
1748 cache->base = 0;
1749 cache->saved_sp = 0;
1750 cache->sp_offset = 0;
1751 cache->pc = 0;
1752
1753 /* Frameless until proven otherwise. */
1754 cache->uses_fp = 0;
1755
1756 /* Saved registers. We initialize these to -1 since zero is a valid
1757 offset (that's where fp is supposed to be stored). */
1758 for (i = 0; i < SH_NUM_REGS; i++)
1759 {
1760 cache->saved_regs[i] = -1;
1761 }
1762
1763 return cache;
1764 }
1765
1766 static struct sh_frame_cache *
1767 sh_frame_cache (struct frame_info *next_frame, void **this_cache)
1768 {
1769 struct sh_frame_cache *cache;
1770 CORE_ADDR current_pc;
1771 int i;
1772
1773 if (*this_cache)
1774 return *this_cache;
1775
1776 cache = sh_alloc_frame_cache ();
1777 *this_cache = cache;
1778
1779 /* In principle, for normal frames, fp holds the frame pointer,
1780 which holds the base address for the current stack frame.
1781 However, for functions that don't need it, the frame pointer is
1782 optional. For these "frameless" functions the frame pointer is
1783 actually the frame pointer of the calling frame. */
1784 cache->base = frame_unwind_register_unsigned (next_frame, FP_REGNUM);
1785 if (cache->base == 0)
1786 return cache;
1787
1788 cache->pc = frame_func_unwind (next_frame);
1789 current_pc = frame_pc_unwind (next_frame);
1790 if (cache->pc != 0)
1791 sh_analyze_prologue (cache->pc, current_pc, cache);
1792
1793 if (!cache->uses_fp)
1794 {
1795 /* We didn't find a valid frame, which means that CACHE->base
1796 currently holds the frame pointer for our calling frame. If
1797 we're at the start of a function, or somewhere half-way its
1798 prologue, the function's frame probably hasn't been fully
1799 setup yet. Try to reconstruct the base address for the stack
1800 frame by looking at the stack pointer. For truly "frameless"
1801 functions this might work too. */
1802 cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
1803 }
1804
1805 /* Now that we have the base address for the stack frame we can
1806 calculate the value of sp in the calling frame. */
1807 cache->saved_sp = cache->base + cache->sp_offset;
1808
1809 /* Adjust all the saved registers such that they contain addresses
1810 instead of offsets. */
1811 for (i = 0; i < SH_NUM_REGS; i++)
1812 if (cache->saved_regs[i] != -1)
1813 cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i] - 4;
1814
1815 return cache;
1816 }
1817
1818 static void
1819 sh_frame_prev_register (struct frame_info *next_frame, void **this_cache,
1820 int regnum, int *optimizedp,
1821 enum lval_type *lvalp, CORE_ADDR *addrp,
1822 int *realnump, void *valuep)
1823 {
1824 struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
1825
1826 gdb_assert (regnum >= 0);
1827
1828 if (regnum == SP_REGNUM && cache->saved_sp)
1829 {
1830 *optimizedp = 0;
1831 *lvalp = not_lval;
1832 *addrp = 0;
1833 *realnump = -1;
1834 if (valuep)
1835 {
1836 /* Store the value. */
1837 store_unsigned_integer (valuep, 4, cache->saved_sp);
1838 }
1839 return;
1840 }
1841
1842 /* The PC of the previous frame is stored in the PR register of
1843 the current frame. Frob regnum so that we pull the value from
1844 the correct place. */
1845 if (regnum == PC_REGNUM)
1846 regnum = PR_REGNUM;
1847
1848 if (regnum < SH_NUM_REGS && cache->saved_regs[regnum] != -1)
1849 {
1850 *optimizedp = 0;
1851 *lvalp = lval_memory;
1852 *addrp = cache->saved_regs[regnum];
1853 *realnump = -1;
1854 if (valuep)
1855 {
1856 /* Read the value in from memory. */
1857 read_memory (*addrp, valuep,
1858 register_size (current_gdbarch, regnum));
1859 }
1860 return;
1861 }
1862
1863 frame_register_unwind (next_frame, regnum,
1864 optimizedp, lvalp, addrp, realnump, valuep);
1865 }
1866
1867 static void
1868 sh_frame_this_id (struct frame_info *next_frame, void **this_cache,
1869 struct frame_id *this_id)
1870 {
1871 struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
1872
1873 /* This marks the outermost frame. */
1874 if (cache->base == 0)
1875 return;
1876
1877 *this_id = frame_id_build (cache->saved_sp, cache->pc);
1878 }
1879
1880 static const struct frame_unwind sh_frame_unwind =
1881 {
1882 NORMAL_FRAME,
1883 sh_frame_this_id,
1884 sh_frame_prev_register
1885 };
1886
1887 static const struct frame_unwind *
1888 sh_frame_sniffer (struct frame_info *next_frame)
1889 {
1890 return &sh_frame_unwind;
1891 }
1892
1893 static CORE_ADDR
1894 sh_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1895 {
1896 return frame_unwind_register_unsigned (next_frame, SP_REGNUM);
1897 }
1898
1899 static CORE_ADDR
1900 sh_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1901 {
1902 return frame_unwind_register_unsigned (next_frame, PC_REGNUM);
1903 }
1904
1905 static struct frame_id
1906 sh_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
1907 {
1908 return frame_id_build (sh_unwind_sp (gdbarch, next_frame),
1909 frame_pc_unwind (next_frame));
1910 }
1911
1912 static CORE_ADDR
1913 sh_frame_base_address (struct frame_info *next_frame, void **this_cache)
1914 {
1915 struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
1916
1917 return cache->base;
1918 }
1919
1920 static const struct frame_base sh_frame_base =
1921 {
1922 &sh_frame_unwind,
1923 sh_frame_base_address,
1924 sh_frame_base_address,
1925 sh_frame_base_address
1926 };
1927
1928 /* The epilogue is defined here as the area at the end of a function,
1929 either on the `ret' instruction itself or after an instruction which
1930 destroys the function's stack frame. */
1931 static int
1932 sh_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
1933 {
1934 CORE_ADDR func_addr = 0, func_end = 0;
1935
1936 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
1937 {
1938 ULONGEST inst;
1939 /* The sh epilogue is max. 14 bytes long. Give another 14 bytes
1940 for a nop and some fixed data (e.g. big offsets) which are
1941 unfortunately also treated as part of the function (which
1942 means, they are below func_end. */
1943 CORE_ADDR addr = func_end - 28;
1944 if (addr < func_addr + 4)
1945 addr = func_addr + 4;
1946 if (pc < addr)
1947 return 0;
1948
1949 /* First search forward until hitting an rts. */
1950 while (addr < func_end
1951 && !IS_RTS (read_memory_unsigned_integer (addr, 2)))
1952 addr += 2;
1953 if (addr >= func_end)
1954 return 0;
1955
1956 /* At this point we should find a mov.l @r15+,r14 instruction,
1957 either before or after the rts. If not, then the function has
1958 probably no "normal" epilogue and we bail out here. */
1959 inst = read_memory_unsigned_integer (addr - 2, 2);
1960 if (IS_RESTORE_FP (read_memory_unsigned_integer (addr - 2, 2)))
1961 addr -= 2;
1962 else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr + 2, 2)))
1963 return 0;
1964
1965 /* Step over possible lds.l @r15+,pr. */
1966 inst = read_memory_unsigned_integer (addr - 2, 2);
1967 if (IS_LDS (inst))
1968 {
1969 addr -= 2;
1970 inst = read_memory_unsigned_integer (addr - 2, 2);
1971 }
1972
1973 /* Step over possible mov r14,r15. */
1974 if (IS_MOV_FP_SP (inst))
1975 {
1976 addr -= 2;
1977 inst = read_memory_unsigned_integer (addr - 2, 2);
1978 }
1979
1980 /* Now check for FP adjustments, using add #imm,r14 or add rX, r14
1981 instructions. */
1982 while (addr > func_addr + 4
1983 && (IS_ADD_REG_TO_FP (inst) || IS_ADD_IMM_FP (inst)))
1984 {
1985 addr -= 2;
1986 inst = read_memory_unsigned_integer (addr - 2, 2);
1987 }
1988
1989 if (pc >= addr)
1990 return 1;
1991 }
1992 return 0;
1993 }
1994
1995 static gdbarch_init_ftype sh_gdbarch_init;
1996
1997 static struct gdbarch *
1998 sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1999 {
2000 struct gdbarch *gdbarch;
2001
2002 sh_show_regs = sh_generic_show_regs;
2003 switch (info.bfd_arch_info->mach)
2004 {
2005 case bfd_mach_sh2e:
2006 sh_show_regs = sh2e_show_regs;
2007 break;
2008 case bfd_mach_sh_dsp:
2009 sh_show_regs = sh_dsp_show_regs;
2010 break;
2011
2012 case bfd_mach_sh3:
2013 sh_show_regs = sh3_show_regs;
2014 break;
2015
2016 case bfd_mach_sh3e:
2017 sh_show_regs = sh3e_show_regs;
2018 break;
2019
2020 case bfd_mach_sh3_dsp:
2021 sh_show_regs = sh3_dsp_show_regs;
2022 break;
2023
2024 case bfd_mach_sh4:
2025 sh_show_regs = sh4_show_regs;
2026 break;
2027
2028 case bfd_mach_sh5:
2029 sh_show_regs = sh64_show_regs;
2030 /* SH5 is handled entirely in sh64-tdep.c */
2031 return sh64_gdbarch_init (info, arches);
2032 }
2033
2034 /* If there is already a candidate, use it. */
2035 arches = gdbarch_list_lookup_by_info (arches, &info);
2036 if (arches != NULL)
2037 return arches->gdbarch;
2038
2039 /* None found, create a new architecture from the information
2040 provided. */
2041 gdbarch = gdbarch_alloc (&info, NULL);
2042
2043 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2044 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2045 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2046 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2047 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2048 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2049 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2050 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2051
2052 set_gdbarch_num_regs (gdbarch, SH_NUM_REGS);
2053 set_gdbarch_sp_regnum (gdbarch, 15);
2054 set_gdbarch_pc_regnum (gdbarch, 16);
2055 set_gdbarch_fp0_regnum (gdbarch, -1);
2056 set_gdbarch_num_pseudo_regs (gdbarch, 0);
2057
2058 set_gdbarch_register_type (gdbarch, sh_default_register_type);
2059
2060 set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info);
2061
2062 set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc);
2063 set_gdbarch_use_struct_convention (gdbarch, sh_use_struct_convention);
2064
2065 set_gdbarch_print_insn (gdbarch, gdb_print_insn_sh);
2066 set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno);
2067
2068 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
2069
2070 set_gdbarch_store_return_value (gdbarch, sh_default_store_return_value);
2071 set_gdbarch_extract_return_value (gdbarch, sh_default_extract_return_value);
2072 set_gdbarch_extract_struct_value_address (gdbarch,
2073 sh_extract_struct_value_address);
2074
2075 set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue);
2076 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2077 set_gdbarch_decr_pc_after_break (gdbarch, 0);
2078 set_gdbarch_function_start_offset (gdbarch, 0);
2079
2080 set_gdbarch_push_dummy_code (gdbarch, sh_push_dummy_code);
2081 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu);
2082
2083 set_gdbarch_frame_args_skip (gdbarch, 0);
2084 set_gdbarch_frameless_function_invocation (gdbarch,
2085 frameless_look_for_prologue);
2086 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2087
2088 set_gdbarch_frame_align (gdbarch, sh_frame_align);
2089 set_gdbarch_unwind_sp (gdbarch, sh_unwind_sp);
2090 set_gdbarch_unwind_pc (gdbarch, sh_unwind_pc);
2091 set_gdbarch_unwind_dummy_id (gdbarch, sh_unwind_dummy_id);
2092 frame_base_set_default (gdbarch, &sh_frame_base);
2093
2094 set_gdbarch_in_function_epilogue_p (gdbarch,
2095 sh_in_function_epilogue_p);
2096
2097 switch (info.bfd_arch_info->mach)
2098 {
2099 case bfd_mach_sh:
2100 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
2101 break;
2102
2103 case bfd_mach_sh2:
2104 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
2105 break;
2106
2107 case bfd_mach_sh2e:
2108 /* doubles on sh2e and sh3e are actually 4 byte. */
2109 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2110
2111 set_gdbarch_register_name (gdbarch, sh_sh2e_register_name);
2112 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
2113 set_gdbarch_fp0_regnum (gdbarch, 25);
2114 set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value);
2115 set_gdbarch_extract_return_value (gdbarch, sh3e_sh4_extract_return_value);
2116 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2117 break;
2118
2119 case bfd_mach_sh_dsp:
2120 set_gdbarch_register_name (gdbarch, sh_sh_dsp_register_name);
2121 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
2122 break;
2123
2124 case bfd_mach_sh3:
2125 set_gdbarch_register_name (gdbarch, sh_sh3_register_name);
2126 break;
2127
2128 case bfd_mach_sh3e:
2129 /* doubles on sh2e and sh3e are actually 4 byte. */
2130 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2131
2132 set_gdbarch_register_name (gdbarch, sh_sh3e_register_name);
2133 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
2134 set_gdbarch_fp0_regnum (gdbarch, 25);
2135 set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value);
2136 set_gdbarch_extract_return_value (gdbarch, sh3e_sh4_extract_return_value);
2137 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2138 break;
2139
2140 case bfd_mach_sh3_dsp:
2141 set_gdbarch_register_name (gdbarch, sh_sh3_dsp_register_name);
2142 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
2143 break;
2144
2145 case bfd_mach_sh4:
2146 set_gdbarch_register_name (gdbarch, sh_sh4_register_name);
2147 set_gdbarch_register_type (gdbarch, sh_sh4_register_type);
2148 set_gdbarch_fp0_regnum (gdbarch, 25);
2149 set_gdbarch_num_pseudo_regs (gdbarch, 12);
2150 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
2151 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
2152 set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value);
2153 set_gdbarch_extract_return_value (gdbarch, sh3e_sh4_extract_return_value);
2154 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2155 break;
2156
2157 default:
2158 set_gdbarch_register_name (gdbarch, sh_generic_register_name);
2159 break;
2160 }
2161
2162 /* Hook in ABI-specific overrides, if they have been registered. */
2163 gdbarch_init_osabi (info, gdbarch);
2164
2165 frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer);
2166 frame_unwind_append_sniffer (gdbarch, sh_frame_sniffer);
2167
2168 return gdbarch;
2169 }
2170
2171 extern initialize_file_ftype _initialize_sh_tdep; /* -Wmissing-prototypes */
2172
2173 void
2174 _initialize_sh_tdep (void)
2175 {
2176 struct cmd_list_element *c;
2177
2178 gdbarch_register (bfd_arch_sh, sh_gdbarch_init, NULL);
2179
2180 add_com ("regs", class_vars, sh_show_regs_command, "Print all registers");
2181 }