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* sh-tdep.c (sh_use_struct_convention): Clean up to have a
[binutils-gdb.git] / gdb / sh-tdep.c
1 /* Target-dependent code for Renesas Super-H, for GDB.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
21
22 /*
23 Contributed by Steve Chamberlain
24 sac@cygnus.com
25 */
26
27 #include "defs.h"
28 #include "frame.h"
29 #include "frame-base.h"
30 #include "frame-unwind.h"
31 #include "dwarf2-frame.h"
32 #include "symtab.h"
33 #include "symfile.h"
34 #include "gdbtypes.h"
35 #include "gdbcmd.h"
36 #include "gdbcore.h"
37 #include "value.h"
38 #include "dis-asm.h"
39 #include "inferior.h"
40 #include "gdb_string.h"
41 #include "gdb_assert.h"
42 #include "arch-utils.h"
43 #include "floatformat.h"
44 #include "regcache.h"
45 #include "doublest.h"
46 #include "osabi.h"
47
48 #include "sh-tdep.h"
49
50 #include "elf-bfd.h"
51 #include "solib-svr4.h"
52
53 /* sh flags */
54 #include "elf/sh.h"
55 /* registers numbers shared with the simulator */
56 #include "gdb/sim-sh.h"
57
58 static void (*sh_show_regs) (void);
59
60 #define SH_NUM_REGS 59
61
62 struct sh_frame_cache
63 {
64 /* Base address. */
65 CORE_ADDR base;
66 LONGEST sp_offset;
67 CORE_ADDR pc;
68
69 /* Flag showing that a frame has been created in the prologue code. */
70 int uses_fp;
71
72 /* Saved registers. */
73 CORE_ADDR saved_regs[SH_NUM_REGS];
74 CORE_ADDR saved_sp;
75 };
76
77 static const char *
78 sh_generic_register_name (int reg_nr)
79 {
80 static char *register_names[] = {
81 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
82 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
83 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
84 "fpul", "fpscr",
85 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
86 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
87 "ssr", "spc",
88 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
89 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
90 };
91 if (reg_nr < 0)
92 return NULL;
93 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
94 return NULL;
95 return register_names[reg_nr];
96 }
97
98 static const char *
99 sh_sh_register_name (int reg_nr)
100 {
101 static char *register_names[] = {
102 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
103 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
104 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
105 "", "",
106 "", "", "", "", "", "", "", "",
107 "", "", "", "", "", "", "", "",
108 "", "",
109 "", "", "", "", "", "", "", "",
110 "", "", "", "", "", "", "", "",
111 };
112 if (reg_nr < 0)
113 return NULL;
114 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
115 return NULL;
116 return register_names[reg_nr];
117 }
118
119 static const char *
120 sh_sh3_register_name (int reg_nr)
121 {
122 static char *register_names[] = {
123 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
124 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
125 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
126 "", "",
127 "", "", "", "", "", "", "", "",
128 "", "", "", "", "", "", "", "",
129 "ssr", "spc",
130 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
131 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
132 };
133 if (reg_nr < 0)
134 return NULL;
135 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
136 return NULL;
137 return register_names[reg_nr];
138 }
139
140 static const char *
141 sh_sh3e_register_name (int reg_nr)
142 {
143 static char *register_names[] = {
144 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
145 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
146 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
147 "fpul", "fpscr",
148 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
149 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
150 "ssr", "spc",
151 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
152 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
153 };
154 if (reg_nr < 0)
155 return NULL;
156 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
157 return NULL;
158 return register_names[reg_nr];
159 }
160
161 static const char *
162 sh_sh2e_register_name (int reg_nr)
163 {
164 static char *register_names[] = {
165 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
166 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
167 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
168 "fpul", "fpscr",
169 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
170 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
171 "", "",
172 "", "", "", "", "", "", "", "",
173 "", "", "", "", "", "", "", "",
174 };
175 if (reg_nr < 0)
176 return NULL;
177 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
178 return NULL;
179 return register_names[reg_nr];
180 }
181
182 static const char *
183 sh_sh_dsp_register_name (int reg_nr)
184 {
185 static char *register_names[] = {
186 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
187 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
188 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
189 "", "dsr",
190 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
191 "y0", "y1", "", "", "", "", "", "mod",
192 "", "",
193 "rs", "re", "", "", "", "", "", "",
194 "", "", "", "", "", "", "", "",
195 };
196 if (reg_nr < 0)
197 return NULL;
198 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
199 return NULL;
200 return register_names[reg_nr];
201 }
202
203 static const char *
204 sh_sh3_dsp_register_name (int reg_nr)
205 {
206 static char *register_names[] = {
207 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
208 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
209 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
210 "", "dsr",
211 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
212 "y0", "y1", "", "", "", "", "", "mod",
213 "ssr", "spc",
214 "rs", "re", "", "", "", "", "", "",
215 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b"
216 "", "", "", "", "", "", "", "",
217 };
218 if (reg_nr < 0)
219 return NULL;
220 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
221 return NULL;
222 return register_names[reg_nr];
223 }
224
225 static const char *
226 sh_sh4_register_name (int reg_nr)
227 {
228 static char *register_names[] = {
229 /* general registers 0-15 */
230 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
231 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
232 /* 16 - 22 */
233 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
234 /* 23, 24 */
235 "fpul", "fpscr",
236 /* floating point registers 25 - 40 */
237 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
238 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
239 /* 41, 42 */
240 "ssr", "spc",
241 /* bank 0 43 - 50 */
242 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
243 /* bank 1 51 - 58 */
244 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
245 /* double precision (pseudo) 59 - 66 */
246 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
247 /* vectors (pseudo) 67 - 70 */
248 "fv0", "fv4", "fv8", "fv12",
249 /* FIXME: missing XF 71 - 86 */
250 /* FIXME: missing XD 87 - 94 */
251 };
252 if (reg_nr < 0)
253 return NULL;
254 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
255 return NULL;
256 return register_names[reg_nr];
257 }
258
259 static const unsigned char *
260 sh_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
261 {
262 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */
263 static unsigned char breakpoint[] = { 0xc3, 0xc3 };
264
265 *lenptr = sizeof (breakpoint);
266 return breakpoint;
267 }
268
269 /* Prologue looks like
270 mov.l r14,@-r15
271 sts.l pr,@-r15
272 mov.l <regs>,@-r15
273 sub <room_for_loca_vars>,r15
274 mov r15,r14
275
276 Actually it can be more complicated than this but that's it, basically.
277 */
278
279 #define GET_SOURCE_REG(x) (((x) >> 4) & 0xf)
280 #define GET_TARGET_REG(x) (((x) >> 8) & 0xf)
281
282 /* STS.L PR,@-r15 0100111100100010
283 r15-4-->r15, PR-->(r15) */
284 #define IS_STS(x) ((x) == 0x4f22)
285
286 /* MOV.L Rm,@-r15 00101111mmmm0110
287 r15-4-->r15, Rm-->(R15) */
288 #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
289
290 /* MOV r15,r14 0110111011110011
291 r15-->r14 */
292 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
293
294 /* ADD #imm,r15 01111111iiiiiiii
295 r15+imm-->r15 */
296 #define IS_ADD_IMM_SP(x) (((x) & 0xff00) == 0x7f00)
297
298 #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
299 #define IS_SHLL_R3(x) ((x) == 0x4300)
300
301 /* ADD r3,r15 0011111100111100
302 r15+r3-->r15 */
303 #define IS_ADD_R3SP(x) ((x) == 0x3f3c)
304
305 /* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
306 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
307 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
308 /* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to
309 make this entirely clear. */
310 /* #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b) */
311 #define IS_FPUSH(x) (((x) & 0xff0f) == 0xff0b)
312
313 /* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011 4 <= m <= 7 */
314 #define IS_MOV_ARG_TO_REG(x) \
315 (((x) & 0xf00f) == 0x6003 && \
316 ((x) & 0x00f0) >= 0x0040 && \
317 ((x) & 0x00f0) <= 0x0070)
318 /* MOV.L Rm,@Rn 0010nnnnmmmm0010 n = 14, 4 <= m <= 7 */
319 #define IS_MOV_ARG_TO_IND_R14(x) \
320 (((x) & 0xff0f) == 0x2e02 && \
321 ((x) & 0x00f0) >= 0x0040 && \
322 ((x) & 0x00f0) <= 0x0070)
323 /* MOV.L Rm,@(disp*4,Rn) 00011110mmmmdddd n = 14, 4 <= m <= 7 */
324 #define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \
325 (((x) & 0xff00) == 0x1e00 && \
326 ((x) & 0x00f0) >= 0x0040 && \
327 ((x) & 0x00f0) <= 0x0070)
328
329 /* MOV.W @(disp*2,PC),Rn 1001nnnndddddddd */
330 #define IS_MOVW_PCREL_TO_REG(x) (((x) & 0xf000) == 0x9000)
331 /* MOV.L @(disp*4,PC),Rn 1101nnnndddddddd */
332 #define IS_MOVL_PCREL_TO_REG(x) (((x) & 0xf000) == 0xd000)
333 /* SUB Rn,R15 00111111nnnn1000 */
334 #define IS_SUB_REG_FROM_SP(x) (((x) & 0xff0f) == 0x3f08)
335
336 #define FPSCR_SZ (1 << 20)
337
338 /* The following instructions are used for epilogue testing. */
339 #define IS_RESTORE_FP(x) ((x) == 0x6ef6)
340 #define IS_RTS(x) ((x) == 0x000b)
341 #define IS_LDS(x) ((x) == 0x4f26)
342 #define IS_MOV_FP_SP(x) ((x) == 0x6fe3)
343 #define IS_ADD_REG_TO_FP(x) (((x) & 0xff0f) == 0x3e0c)
344 #define IS_ADD_IMM_FP(x) (((x) & 0xff00) == 0x7e00)
345
346 /* Disassemble an instruction. */
347 static int
348 gdb_print_insn_sh (bfd_vma memaddr, disassemble_info * info)
349 {
350 info->endian = TARGET_BYTE_ORDER;
351 return print_insn_sh (memaddr, info);
352 }
353
354 static CORE_ADDR
355 sh_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc,
356 struct sh_frame_cache *cache)
357 {
358 ULONGEST inst;
359 CORE_ADDR opc;
360 int offset;
361 int sav_offset = 0;
362 int r3_val = 0;
363 int reg, sav_reg = -1;
364
365 if (pc >= current_pc)
366 return current_pc;
367
368 cache->uses_fp = 0;
369 for (opc = pc + (2 * 28); pc < opc; pc += 2)
370 {
371 inst = read_memory_unsigned_integer (pc, 2);
372 /* See where the registers will be saved to */
373 if (IS_PUSH (inst))
374 {
375 cache->saved_regs[GET_SOURCE_REG (inst)] = cache->sp_offset;
376 cache->sp_offset += 4;
377 }
378 else if (IS_STS (inst))
379 {
380 cache->saved_regs[PR_REGNUM] = cache->sp_offset;
381 cache->sp_offset += 4;
382 }
383 else if (IS_MOV_R3 (inst))
384 {
385 r3_val = ((inst & 0xff) ^ 0x80) - 0x80;
386 }
387 else if (IS_SHLL_R3 (inst))
388 {
389 r3_val <<= 1;
390 }
391 else if (IS_ADD_R3SP (inst))
392 {
393 cache->sp_offset += -r3_val;
394 }
395 else if (IS_ADD_IMM_SP (inst))
396 {
397 offset = ((inst & 0xff) ^ 0x80) - 0x80;
398 cache->sp_offset -= offset;
399 }
400 else if (IS_MOVW_PCREL_TO_REG (inst))
401 {
402 if (sav_reg < 0)
403 {
404 reg = GET_TARGET_REG (inst);
405 if (reg < 14)
406 {
407 sav_reg = reg;
408 offset = (((inst & 0xff) ^ 0x80) - 0x80) << 1;
409 sav_offset =
410 read_memory_integer (((pc + 4) & ~3) + offset, 2);
411 }
412 }
413 }
414 else if (IS_MOVL_PCREL_TO_REG (inst))
415 {
416 if (sav_reg < 0)
417 {
418 reg = (inst & 0x0f00) >> 8;
419 if (reg < 14)
420 {
421 sav_reg = reg;
422 offset = (((inst & 0xff) ^ 0x80) - 0x80) << 1;
423 sav_offset =
424 read_memory_integer (((pc + 4) & ~3) + offset, 4);
425 }
426 }
427 }
428 else if (IS_SUB_REG_FROM_SP (inst))
429 {
430 reg = GET_SOURCE_REG (inst);
431 if (sav_reg > 0 && reg == sav_reg)
432 {
433 sav_reg = -1;
434 }
435 cache->sp_offset += sav_offset;
436 }
437 else if (IS_FPUSH (inst))
438 {
439 if (read_register (FPSCR_REGNUM) & FPSCR_SZ)
440 {
441 cache->sp_offset += 8;
442 }
443 else
444 {
445 cache->sp_offset += 4;
446 }
447 }
448 else if (IS_MOV_SP_FP (inst))
449 {
450 if (!cache->uses_fp)
451 cache->uses_fp = 1;
452 /* At this point, only allow argument register moves to other
453 registers or argument register moves to @(X,fp) which are
454 moving the register arguments onto the stack area allocated
455 by a former add somenumber to SP call. Don't allow moving
456 to an fp indirect address above fp + cache->sp_offset. */
457 pc += 2;
458 for (opc = pc + 12; pc < opc; pc += 2)
459 {
460 inst = read_memory_integer (pc, 2);
461 if (IS_MOV_ARG_TO_IND_R14 (inst))
462 {
463 reg = GET_SOURCE_REG (inst);
464 if (cache->sp_offset > 0)
465 cache->saved_regs[reg] = cache->sp_offset;
466 }
467 else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst))
468 {
469 reg = GET_SOURCE_REG (inst);
470 offset = (inst & 0xf) * 4;
471 if (cache->sp_offset > offset)
472 cache->saved_regs[reg] = cache->sp_offset - offset;
473 }
474 else if (IS_MOV_ARG_TO_REG (inst))
475 continue;
476 else
477 break;
478 }
479 break;
480 }
481 #if 0 /* This used to just stop when it found an instruction that
482 was not considered part of the prologue. Now, we just
483 keep going looking for likely instructions. */
484 else
485 break;
486 #endif
487 }
488
489 return pc;
490 }
491
492 /* Skip any prologue before the guts of a function */
493
494 /* Skip the prologue using the debug information. If this fails we'll
495 fall back on the 'guess' method below. */
496 static CORE_ADDR
497 after_prologue (CORE_ADDR pc)
498 {
499 struct symtab_and_line sal;
500 CORE_ADDR func_addr, func_end;
501
502 /* If we can not find the symbol in the partial symbol table, then
503 there is no hope we can determine the function's start address
504 with this code. */
505 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
506 return 0;
507
508 /* Get the line associated with FUNC_ADDR. */
509 sal = find_pc_line (func_addr, 0);
510
511 /* There are only two cases to consider. First, the end of the source line
512 is within the function bounds. In that case we return the end of the
513 source line. Second is the end of the source line extends beyond the
514 bounds of the current function. We need to use the slow code to
515 examine instructions in that case. */
516 if (sal.end < func_end)
517 return sal.end;
518 else
519 return 0;
520 }
521
522 static CORE_ADDR
523 sh_skip_prologue (CORE_ADDR start_pc)
524 {
525 CORE_ADDR pc;
526 struct sh_frame_cache cache;
527
528 /* See if we can determine the end of the prologue via the symbol table.
529 If so, then return either PC, or the PC after the prologue, whichever
530 is greater. */
531 pc = after_prologue (start_pc);
532
533 /* If after_prologue returned a useful address, then use it. Else
534 fall back on the instruction skipping code. */
535 if (pc)
536 return max (pc, start_pc);
537
538 cache.sp_offset = -4;
539 pc = sh_analyze_prologue (start_pc, (CORE_ADDR) -1, &cache);
540 if (!cache.uses_fp)
541 return start_pc;
542
543 return pc;
544 }
545
546 /* Should call_function allocate stack space for a struct return?
547
548 The ABI says:
549
550 Aggregate types not bigger than 8 bytes that have the same size and
551 alignment as one of the integer scalar types are returned in the
552 same registers as the integer type they match.
553
554 For example, a 2-byte aligned structure with size 2 bytes has the
555 same size and alignment as a short int, and will be returned in R0.
556 A 4-byte aligned structure with size 8 bytes has the same size and
557 alignment as a long long int, and will be returned in R0 and R1.
558
559 When an aggregate type is returned in R0 and R1, R0 contains the
560 first four bytes of the aggregate, and R1 contains the
561 remainder. If the size of the aggregate type is not a multiple of 4
562 bytes, the aggregate is tail-padded up to a multiple of 4
563 bytes. The value of the padding is undefined. For little-endian
564 targets the padding will appear at the most significant end of the
565 last element, for big-endian targets the padding appears at the
566 least significant end of the last element.
567
568 All other aggregate types are returned by address. The caller
569 function passes the address of an area large enough to hold the
570 aggregate value in R2. The called function stores the result in
571 this location."
572
573 To reiterate, structs smaller than 8 bytes could also be returned
574 in memory, if they don't pass the "same size and alignment as an
575 integer type" rule.
576
577 For example, in
578
579 struct s { char c[3]; } wibble;
580 struct s foo(void) { return wibble; }
581
582 the return value from foo() will be in memory, not
583 in R0, because there is no 3-byte integer type.
584
585 */
586
587 static int
588 sh_use_struct_convention (int gcc_p, struct type *type)
589 {
590 int len = TYPE_LENGTH (type);
591 int nelem = TYPE_NFIELDS (type);
592
593 /* Non-power of 2 length types and types bigger than 8 bytes (which don't
594 fit in two registers anyway) use struct convention. */
595 if (len != 1 && len != 2 && len != 4 && len != 8)
596 return 1;
597
598 /* Scalar types and aggregate types with exactly one field are aligned
599 by definition. They are returned in registers. */
600 if (nelem <= 1)
601 return 0;
602
603 /* If the first field in the aggregate has the same length as the entire
604 aggregate type, the type is returned in registers. */
605 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == len)
606 return 0;
607
608 /* If the size of the aggregate is 8 bytes and the first field is
609 of size 4 bytes its alignment is equal to long long's alignment,
610 so it's returned in registers. */
611 if (len == 8 && TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == 4)
612 return 0;
613
614 /* Otherwise use struct convention. */
615 return 1;
616 }
617
618 /* Extract from an array REGBUF containing the (raw) register state
619 the address in which a function should return its structure value,
620 as a CORE_ADDR (or an expression that can be used as one). */
621 static CORE_ADDR
622 sh_extract_struct_value_address (struct regcache *regcache)
623 {
624 ULONGEST addr;
625
626 regcache_cooked_read_unsigned (regcache, STRUCT_RETURN_REGNUM, &addr);
627 return addr;
628 }
629
630 static CORE_ADDR
631 sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
632 {
633 return sp & ~3;
634 }
635
636 /* Function: push_dummy_call (formerly push_arguments)
637 Setup the function arguments for calling a function in the inferior.
638
639 On the Renesas SH architecture, there are four registers (R4 to R7)
640 which are dedicated for passing function arguments. Up to the first
641 four arguments (depending on size) may go into these registers.
642 The rest go on the stack.
643
644 MVS: Except on SH variants that have floating point registers.
645 In that case, float and double arguments are passed in the same
646 manner, but using FP registers instead of GP registers.
647
648 Arguments that are smaller than 4 bytes will still take up a whole
649 register or a whole 32-bit word on the stack, and will be
650 right-justified in the register or the stack word. This includes
651 chars, shorts, and small aggregate types.
652
653 Arguments that are larger than 4 bytes may be split between two or
654 more registers. If there are not enough registers free, an argument
655 may be passed partly in a register (or registers), and partly on the
656 stack. This includes doubles, long longs, and larger aggregates.
657 As far as I know, there is no upper limit to the size of aggregates
658 that will be passed in this way; in other words, the convention of
659 passing a pointer to a large aggregate instead of a copy is not used.
660
661 MVS: The above appears to be true for the SH variants that do not
662 have an FPU, however those that have an FPU appear to copy the
663 aggregate argument onto the stack (and not place it in registers)
664 if it is larger than 16 bytes (four GP registers).
665
666 An exceptional case exists for struct arguments (and possibly other
667 aggregates such as arrays) if the size is larger than 4 bytes but
668 not a multiple of 4 bytes. In this case the argument is never split
669 between the registers and the stack, but instead is copied in its
670 entirety onto the stack, AND also copied into as many registers as
671 there is room for. In other words, space in registers permitting,
672 two copies of the same argument are passed in. As far as I can tell,
673 only the one on the stack is used, although that may be a function
674 of the level of compiler optimization. I suspect this is a compiler
675 bug. Arguments of these odd sizes are left-justified within the
676 word (as opposed to arguments smaller than 4 bytes, which are
677 right-justified).
678
679 If the function is to return an aggregate type such as a struct, it
680 is either returned in the normal return value register R0 (if its
681 size is no greater than one byte), or else the caller must allocate
682 space into which the callee will copy the return value (if the size
683 is greater than one byte). In this case, a pointer to the return
684 value location is passed into the callee in register R2, which does
685 not displace any of the other arguments passed in via registers R4
686 to R7. */
687
688 /* Helper function to justify value in register according to endianess. */
689 static char *
690 sh_justify_value_in_reg (struct value *val, int len)
691 {
692 static char valbuf[4];
693
694 memset (valbuf, 0, sizeof (valbuf));
695 if (len < 4)
696 {
697 /* value gets right-justified in the register or stack word */
698 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
699 memcpy (valbuf + (4 - len), (char *) VALUE_CONTENTS (val), len);
700 else
701 memcpy (valbuf, (char *) VALUE_CONTENTS (val), len);
702 return valbuf;
703 }
704 return (char *) VALUE_CONTENTS (val);
705 }
706
707 /* Helper function to eval number of bytes to allocate on stack. */
708 static CORE_ADDR
709 sh_stack_allocsize (int nargs, struct value **args)
710 {
711 int stack_alloc = 0;
712 while (nargs-- > 0)
713 stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[nargs])) + 3) & ~3);
714 return stack_alloc;
715 }
716
717 /* Helper functions for getting the float arguments right. Registers usage
718 depends on the ABI and the endianess. The comments should enlighten how
719 it's intended to work. */
720
721 /* This array stores which of the float arg registers are already in use. */
722 static int flt_argreg_array[FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM + 1];
723
724 /* This function just resets the above array to "no reg used so far". */
725 static void
726 sh_init_flt_argreg (void)
727 {
728 memset (flt_argreg_array, 0, sizeof flt_argreg_array);
729 }
730
731 /* This function returns the next register to use for float arg passing.
732 It returns either a valid value between FLOAT_ARG0_REGNUM and
733 FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns
734 FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available.
735
736 Note that register number 0 in flt_argreg_array corresponds with the
737 real float register fr4. In contrast to FLOAT_ARG0_REGNUM (value is
738 29) the parity of the register number is preserved, which is important
739 for the double register passing test (see the "argreg & 1" test below). */
740 static int
741 sh_next_flt_argreg (int len)
742 {
743 int argreg;
744
745 /* First search for the next free register. */
746 for (argreg = 0; argreg <= FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM;
747 ++argreg)
748 if (!flt_argreg_array[argreg])
749 break;
750
751 /* No register left? */
752 if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
753 return FLOAT_ARGLAST_REGNUM + 1;
754
755 if (len == 8)
756 {
757 /* Doubles are always starting in a even register number. */
758 if (argreg & 1)
759 {
760 flt_argreg_array[argreg] = 1;
761
762 ++argreg;
763
764 /* No register left? */
765 if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
766 return FLOAT_ARGLAST_REGNUM + 1;
767 }
768 /* Also mark the next register as used. */
769 flt_argreg_array[argreg + 1] = 1;
770 }
771 else if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
772 {
773 /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */
774 if (!flt_argreg_array[argreg + 1])
775 ++argreg;
776 }
777 flt_argreg_array[argreg] = 1;
778 return FLOAT_ARG0_REGNUM + argreg;
779 }
780
781 static CORE_ADDR
782 sh_push_dummy_call_fpu (struct gdbarch *gdbarch,
783 CORE_ADDR func_addr,
784 struct regcache *regcache,
785 CORE_ADDR bp_addr, int nargs,
786 struct value **args,
787 CORE_ADDR sp, int struct_return,
788 CORE_ADDR struct_addr)
789 {
790 int stack_offset = 0;
791 int argreg = ARG0_REGNUM;
792 int flt_argreg = 0;
793 int argnum;
794 struct type *type;
795 CORE_ADDR regval;
796 char *val;
797 int len, reg_size = 0;
798 int pass_on_stack;
799
800 /* first force sp to a 4-byte alignment */
801 sp = sh_frame_align (gdbarch, sp);
802
803 if (struct_return)
804 regcache_cooked_write_unsigned (regcache,
805 STRUCT_RETURN_REGNUM, struct_addr);
806
807 /* make room on stack for args */
808 sp -= sh_stack_allocsize (nargs, args);
809
810 /* Initialize float argument mechanism. */
811 sh_init_flt_argreg ();
812
813 /* Now load as many as possible of the first arguments into
814 registers, and push the rest onto the stack. There are 16 bytes
815 in four registers available. Loop thru args from first to last. */
816 for (argnum = 0; argnum < nargs; argnum++)
817 {
818 type = VALUE_TYPE (args[argnum]);
819 len = TYPE_LENGTH (type);
820 val = sh_justify_value_in_reg (args[argnum], len);
821
822 /* Some decisions have to be made how various types are handled.
823 This also differs in different ABIs. */
824 pass_on_stack = 0;
825 if (len > 16)
826 pass_on_stack = 1; /* Types bigger than 16 bytes are passed on stack. */
827
828 /* Find out the next register to use for a floating point value. */
829 if (TYPE_CODE (type) == TYPE_CODE_FLT)
830 flt_argreg = sh_next_flt_argreg (len);
831
832 while (len > 0)
833 {
834 if ((TYPE_CODE (type) == TYPE_CODE_FLT
835 && flt_argreg > FLOAT_ARGLAST_REGNUM)
836 || argreg > ARGLAST_REGNUM || pass_on_stack)
837 {
838 /* The remainder of the data goes entirely on the stack,
839 4-byte aligned. */
840 reg_size = (len + 3) & ~3;
841 write_memory (sp + stack_offset, val, reg_size);
842 stack_offset += reg_size;
843 }
844 else if (TYPE_CODE (type) == TYPE_CODE_FLT
845 && flt_argreg <= FLOAT_ARGLAST_REGNUM)
846 {
847 /* Argument goes in a float argument register. */
848 reg_size = register_size (gdbarch, flt_argreg);
849 regval = extract_unsigned_integer (val, reg_size);
850 regcache_cooked_write_unsigned (regcache, flt_argreg++, regval);
851 }
852 else if (argreg <= ARGLAST_REGNUM)
853 {
854 /* there's room in a register */
855 reg_size = register_size (gdbarch, argreg);
856 regval = extract_unsigned_integer (val, reg_size);
857 regcache_cooked_write_unsigned (regcache, argreg++, regval);
858 }
859 /* Store the value reg_size bytes at a time. This means that things
860 larger than reg_size bytes may go partly in registers and partly
861 on the stack. */
862 len -= reg_size;
863 val += reg_size;
864 }
865 }
866
867 /* Store return address. */
868 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
869
870 /* Update stack pointer. */
871 regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp);
872
873 return sp;
874 }
875
876 static CORE_ADDR
877 sh_push_dummy_call_nofpu (struct gdbarch *gdbarch,
878 CORE_ADDR func_addr,
879 struct regcache *regcache,
880 CORE_ADDR bp_addr,
881 int nargs, struct value **args,
882 CORE_ADDR sp, int struct_return,
883 CORE_ADDR struct_addr)
884 {
885 int stack_offset = 0;
886 int argreg = ARG0_REGNUM;
887 int argnum;
888 struct type *type;
889 CORE_ADDR regval;
890 char *val;
891 int len, reg_size;
892
893 /* first force sp to a 4-byte alignment */
894 sp = sh_frame_align (gdbarch, sp);
895
896 if (struct_return)
897 regcache_cooked_write_unsigned (regcache,
898 STRUCT_RETURN_REGNUM, struct_addr);
899
900 /* make room on stack for args */
901 sp -= sh_stack_allocsize (nargs, args);
902
903 /* Now load as many as possible of the first arguments into
904 registers, and push the rest onto the stack. There are 16 bytes
905 in four registers available. Loop thru args from first to last. */
906 for (argnum = 0; argnum < nargs; argnum++)
907 {
908 type = VALUE_TYPE (args[argnum]);
909 len = TYPE_LENGTH (type);
910 val = sh_justify_value_in_reg (args[argnum], len);
911
912 while (len > 0)
913 {
914 if (argreg > ARGLAST_REGNUM)
915 {
916 /* The remainder of the data goes entirely on the stack,
917 4-byte aligned. */
918 reg_size = (len + 3) & ~3;
919 write_memory (sp + stack_offset, val, reg_size);
920 stack_offset += reg_size;
921 }
922 else if (argreg <= ARGLAST_REGNUM)
923 {
924 /* there's room in a register */
925 reg_size = register_size (gdbarch, argreg);
926 regval = extract_unsigned_integer (val, reg_size);
927 regcache_cooked_write_unsigned (regcache, argreg++, regval);
928 }
929 /* Store the value reg_size bytes at a time. This means that things
930 larger than reg_size bytes may go partly in registers and partly
931 on the stack. */
932 len -= reg_size;
933 val += reg_size;
934 }
935 }
936
937 /* Store return address. */
938 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
939
940 /* Update stack pointer. */
941 regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp);
942
943 return sp;
944 }
945
946 /* Find a function's return value in the appropriate registers (in
947 regbuf), and copy it into valbuf. Extract from an array REGBUF
948 containing the (raw) register state a function return value of type
949 TYPE, and copy that, in virtual format, into VALBUF. */
950 static void
951 sh_default_extract_return_value (struct type *type, struct regcache *regcache,
952 void *valbuf)
953 {
954 int len = TYPE_LENGTH (type);
955 int return_register = R0_REGNUM;
956 int offset;
957
958 if (len <= 4)
959 {
960 ULONGEST c;
961
962 regcache_cooked_read_unsigned (regcache, R0_REGNUM, &c);
963 store_unsigned_integer (valbuf, len, c);
964 }
965 else if (len == 8)
966 {
967 int i, regnum = R0_REGNUM;
968 for (i = 0; i < len; i += 4)
969 regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
970 }
971 else
972 error ("bad size for return value");
973 }
974
975 static void
976 sh3e_sh4_extract_return_value (struct type *type, struct regcache *regcache,
977 void *valbuf)
978 {
979 if (TYPE_CODE (type) == TYPE_CODE_FLT)
980 {
981 int len = TYPE_LENGTH (type);
982 int i, regnum = FP0_REGNUM;
983 for (i = 0; i < len; i += 4)
984 regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
985 }
986 else
987 sh_default_extract_return_value (type, regcache, valbuf);
988 }
989
990 /* Write into appropriate registers a function return value
991 of type TYPE, given in virtual format.
992 If the architecture is sh4 or sh3e, store a function's return value
993 in the R0 general register or in the FP0 floating point register,
994 depending on the type of the return value. In all the other cases
995 the result is stored in r0, left-justified. */
996 static void
997 sh_default_store_return_value (struct type *type, struct regcache *regcache,
998 const void *valbuf)
999 {
1000 ULONGEST val;
1001 int len = TYPE_LENGTH (type);
1002
1003 if (len <= 4)
1004 {
1005 val = extract_unsigned_integer (valbuf, len);
1006 regcache_cooked_write_unsigned (regcache, R0_REGNUM, val);
1007 }
1008 else
1009 {
1010 int i, regnum = R0_REGNUM;
1011 for (i = 0; i < len; i += 4)
1012 regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
1013 }
1014 }
1015
1016 static void
1017 sh3e_sh4_store_return_value (struct type *type, struct regcache *regcache,
1018 const void *valbuf)
1019 {
1020 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1021 {
1022 int len = TYPE_LENGTH (type);
1023 int i, regnum = FP0_REGNUM;
1024 for (i = 0; i < len; i += 4)
1025 regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
1026 }
1027 else
1028 sh_default_store_return_value (type, regcache, valbuf);
1029 }
1030
1031 /* Print the registers in a form similar to the E7000 */
1032
1033 static void
1034 sh_generic_show_regs (void)
1035 {
1036 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1037 paddr (read_register (PC_REGNUM)),
1038 (long) read_register (SR_REGNUM),
1039 (long) read_register (PR_REGNUM),
1040 (long) read_register (MACH_REGNUM),
1041 (long) read_register (MACL_REGNUM));
1042
1043 printf_filtered ("GBR=%08lx VBR=%08lx",
1044 (long) read_register (GBR_REGNUM),
1045 (long) read_register (VBR_REGNUM));
1046
1047 printf_filtered
1048 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1049 (long) read_register (0), (long) read_register (1),
1050 (long) read_register (2), (long) read_register (3),
1051 (long) read_register (4), (long) read_register (5),
1052 (long) read_register (6), (long) read_register (7));
1053 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1054 (long) read_register (8), (long) read_register (9),
1055 (long) read_register (10), (long) read_register (11),
1056 (long) read_register (12), (long) read_register (13),
1057 (long) read_register (14), (long) read_register (15));
1058 }
1059
1060 static void
1061 sh3_show_regs (void)
1062 {
1063 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1064 paddr (read_register (PC_REGNUM)),
1065 (long) read_register (SR_REGNUM),
1066 (long) read_register (PR_REGNUM),
1067 (long) read_register (MACH_REGNUM),
1068 (long) read_register (MACL_REGNUM));
1069
1070 printf_filtered ("GBR=%08lx VBR=%08lx",
1071 (long) read_register (GBR_REGNUM),
1072 (long) read_register (VBR_REGNUM));
1073 printf_filtered (" SSR=%08lx SPC=%08lx",
1074 (long) read_register (SSR_REGNUM),
1075 (long) read_register (SPC_REGNUM));
1076
1077 printf_filtered
1078 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1079 (long) read_register (0), (long) read_register (1),
1080 (long) read_register (2), (long) read_register (3),
1081 (long) read_register (4), (long) read_register (5),
1082 (long) read_register (6), (long) read_register (7));
1083 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1084 (long) read_register (8), (long) read_register (9),
1085 (long) read_register (10), (long) read_register (11),
1086 (long) read_register (12), (long) read_register (13),
1087 (long) read_register (14), (long) read_register (15));
1088 }
1089
1090
1091 static void
1092 sh2e_show_regs (void)
1093 {
1094 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1095 paddr (read_register (PC_REGNUM)),
1096 (long) read_register (SR_REGNUM),
1097 (long) read_register (PR_REGNUM),
1098 (long) read_register (MACH_REGNUM),
1099 (long) read_register (MACL_REGNUM));
1100
1101 printf_filtered ("GBR=%08lx VBR=%08lx",
1102 (long) read_register (GBR_REGNUM),
1103 (long) read_register (VBR_REGNUM));
1104 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1105 (long) read_register (FPUL_REGNUM),
1106 (long) read_register (FPSCR_REGNUM));
1107
1108 printf_filtered
1109 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1110 (long) read_register (0), (long) read_register (1),
1111 (long) read_register (2), (long) read_register (3),
1112 (long) read_register (4), (long) read_register (5),
1113 (long) read_register (6), (long) read_register (7));
1114 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1115 (long) read_register (8), (long) read_register (9),
1116 (long) read_register (10), (long) read_register (11),
1117 (long) read_register (12), (long) read_register (13),
1118 (long) read_register (14), (long) read_register (15));
1119
1120 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 0), (long) read_register (FP0_REGNUM + 1), (long) read_register (FP0_REGNUM + 2), (long) read_register (FP0_REGNUM + 3), (long) read_register (FP0_REGNUM + 4), (long) read_register (FP0_REGNUM + 5), (long) read_register (FP0_REGNUM + 6), (long) read_register (FP0_REGNUM + 7));
1121 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 8), (long) read_register (FP0_REGNUM + 9), (long) read_register (FP0_REGNUM + 10), (long) read_register (FP0_REGNUM + 11), (long) read_register (FP0_REGNUM + 12), (long) read_register (FP0_REGNUM + 13), (long) read_register (FP0_REGNUM + 14), (long) read_register (FP0_REGNUM + 15));
1122 }
1123
1124 static void
1125 sh3e_show_regs (void)
1126 {
1127 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1128 paddr (read_register (PC_REGNUM)),
1129 (long) read_register (SR_REGNUM),
1130 (long) read_register (PR_REGNUM),
1131 (long) read_register (MACH_REGNUM),
1132 (long) read_register (MACL_REGNUM));
1133
1134 printf_filtered ("GBR=%08lx VBR=%08lx",
1135 (long) read_register (GBR_REGNUM),
1136 (long) read_register (VBR_REGNUM));
1137 printf_filtered (" SSR=%08lx SPC=%08lx",
1138 (long) read_register (SSR_REGNUM),
1139 (long) read_register (SPC_REGNUM));
1140 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1141 (long) read_register (FPUL_REGNUM),
1142 (long) read_register (FPSCR_REGNUM));
1143
1144 printf_filtered
1145 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1146 (long) read_register (0), (long) read_register (1),
1147 (long) read_register (2), (long) read_register (3),
1148 (long) read_register (4), (long) read_register (5),
1149 (long) read_register (6), (long) read_register (7));
1150 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1151 (long) read_register (8), (long) read_register (9),
1152 (long) read_register (10), (long) read_register (11),
1153 (long) read_register (12), (long) read_register (13),
1154 (long) read_register (14), (long) read_register (15));
1155
1156 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 0), (long) read_register (FP0_REGNUM + 1), (long) read_register (FP0_REGNUM + 2), (long) read_register (FP0_REGNUM + 3), (long) read_register (FP0_REGNUM + 4), (long) read_register (FP0_REGNUM + 5), (long) read_register (FP0_REGNUM + 6), (long) read_register (FP0_REGNUM + 7));
1157 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 8), (long) read_register (FP0_REGNUM + 9), (long) read_register (FP0_REGNUM + 10), (long) read_register (FP0_REGNUM + 11), (long) read_register (FP0_REGNUM + 12), (long) read_register (FP0_REGNUM + 13), (long) read_register (FP0_REGNUM + 14), (long) read_register (FP0_REGNUM + 15));
1158 }
1159
1160 static void
1161 sh3_dsp_show_regs (void)
1162 {
1163 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1164 paddr (read_register (PC_REGNUM)),
1165 (long) read_register (SR_REGNUM),
1166 (long) read_register (PR_REGNUM),
1167 (long) read_register (MACH_REGNUM),
1168 (long) read_register (MACL_REGNUM));
1169
1170 printf_filtered ("GBR=%08lx VBR=%08lx",
1171 (long) read_register (GBR_REGNUM),
1172 (long) read_register (VBR_REGNUM));
1173
1174 printf_filtered (" SSR=%08lx SPC=%08lx",
1175 (long) read_register (SSR_REGNUM),
1176 (long) read_register (SPC_REGNUM));
1177
1178 printf_filtered (" DSR=%08lx", (long) read_register (DSR_REGNUM));
1179
1180 printf_filtered
1181 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1182 (long) read_register (0), (long) read_register (1),
1183 (long) read_register (2), (long) read_register (3),
1184 (long) read_register (4), (long) read_register (5),
1185 (long) read_register (6), (long) read_register (7));
1186 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1187 (long) read_register (8), (long) read_register (9),
1188 (long) read_register (10), (long) read_register (11),
1189 (long) read_register (12), (long) read_register (13),
1190 (long) read_register (14), (long) read_register (15));
1191
1192 printf_filtered
1193 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1194 (long) read_register (A0G_REGNUM) & 0xff,
1195 (long) read_register (A0_REGNUM), (long) read_register (M0_REGNUM),
1196 (long) read_register (X0_REGNUM), (long) read_register (Y0_REGNUM),
1197 (long) read_register (RS_REGNUM), (long) read_register (MOD_REGNUM));
1198 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1199 (long) read_register (A1G_REGNUM) & 0xff,
1200 (long) read_register (A1_REGNUM),
1201 (long) read_register (M1_REGNUM),
1202 (long) read_register (X1_REGNUM),
1203 (long) read_register (Y1_REGNUM),
1204 (long) read_register (RE_REGNUM));
1205 }
1206
1207 static void
1208 sh4_show_regs (void)
1209 {
1210 int pr = read_register (FPSCR_REGNUM) & 0x80000;
1211 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1212 paddr (read_register (PC_REGNUM)),
1213 (long) read_register (SR_REGNUM),
1214 (long) read_register (PR_REGNUM),
1215 (long) read_register (MACH_REGNUM),
1216 (long) read_register (MACL_REGNUM));
1217
1218 printf_filtered ("GBR=%08lx VBR=%08lx",
1219 (long) read_register (GBR_REGNUM),
1220 (long) read_register (VBR_REGNUM));
1221 printf_filtered (" SSR=%08lx SPC=%08lx",
1222 (long) read_register (SSR_REGNUM),
1223 (long) read_register (SPC_REGNUM));
1224 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1225 (long) read_register (FPUL_REGNUM),
1226 (long) read_register (FPSCR_REGNUM));
1227
1228 printf_filtered
1229 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1230 (long) read_register (0), (long) read_register (1),
1231 (long) read_register (2), (long) read_register (3),
1232 (long) read_register (4), (long) read_register (5),
1233 (long) read_register (6), (long) read_register (7));
1234 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1235 (long) read_register (8), (long) read_register (9),
1236 (long) read_register (10), (long) read_register (11),
1237 (long) read_register (12), (long) read_register (13),
1238 (long) read_register (14), (long) read_register (15));
1239
1240 printf_filtered ((pr
1241 ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1242 :
1243 "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1244 (long) read_register (FP0_REGNUM + 0),
1245 (long) read_register (FP0_REGNUM + 1),
1246 (long) read_register (FP0_REGNUM + 2),
1247 (long) read_register (FP0_REGNUM + 3),
1248 (long) read_register (FP0_REGNUM + 4),
1249 (long) read_register (FP0_REGNUM + 5),
1250 (long) read_register (FP0_REGNUM + 6),
1251 (long) read_register (FP0_REGNUM + 7));
1252 printf_filtered ((pr ?
1253 "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n" :
1254 "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1255 (long) read_register (FP0_REGNUM + 8),
1256 (long) read_register (FP0_REGNUM + 9),
1257 (long) read_register (FP0_REGNUM + 10),
1258 (long) read_register (FP0_REGNUM + 11),
1259 (long) read_register (FP0_REGNUM + 12),
1260 (long) read_register (FP0_REGNUM + 13),
1261 (long) read_register (FP0_REGNUM + 14),
1262 (long) read_register (FP0_REGNUM + 15));
1263 }
1264
1265 static void
1266 sh_dsp_show_regs (void)
1267 {
1268 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1269 paddr (read_register (PC_REGNUM)),
1270 (long) read_register (SR_REGNUM),
1271 (long) read_register (PR_REGNUM),
1272 (long) read_register (MACH_REGNUM),
1273 (long) read_register (MACL_REGNUM));
1274
1275 printf_filtered ("GBR=%08lx VBR=%08lx",
1276 (long) read_register (GBR_REGNUM),
1277 (long) read_register (VBR_REGNUM));
1278
1279 printf_filtered (" DSR=%08lx", (long) read_register (DSR_REGNUM));
1280
1281 printf_filtered
1282 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1283 (long) read_register (0), (long) read_register (1),
1284 (long) read_register (2), (long) read_register (3),
1285 (long) read_register (4), (long) read_register (5),
1286 (long) read_register (6), (long) read_register (7));
1287 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1288 (long) read_register (8), (long) read_register (9),
1289 (long) read_register (10), (long) read_register (11),
1290 (long) read_register (12), (long) read_register (13),
1291 (long) read_register (14), (long) read_register (15));
1292
1293 printf_filtered
1294 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1295 (long) read_register (A0G_REGNUM) & 0xff,
1296 (long) read_register (A0_REGNUM), (long) read_register (M0_REGNUM),
1297 (long) read_register (X0_REGNUM), (long) read_register (Y0_REGNUM),
1298 (long) read_register (RS_REGNUM), (long) read_register (MOD_REGNUM));
1299 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1300 (long) read_register (A1G_REGNUM) & 0xff,
1301 (long) read_register (A1_REGNUM),
1302 (long) read_register (M1_REGNUM),
1303 (long) read_register (X1_REGNUM),
1304 (long) read_register (Y1_REGNUM),
1305 (long) read_register (RE_REGNUM));
1306 }
1307
1308 static void
1309 sh_show_regs_command (char *args, int from_tty)
1310 {
1311 if (sh_show_regs)
1312 (*sh_show_regs) ();
1313 }
1314
1315 /* Return the GDB type object for the "standard" data type
1316 of data in register N. */
1317 static struct type *
1318 sh_sh3e_register_type (struct gdbarch *gdbarch, int reg_nr)
1319 {
1320 if ((reg_nr >= FP0_REGNUM
1321 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
1322 return builtin_type_float;
1323 else
1324 return builtin_type_int;
1325 }
1326
1327 static struct type *
1328 sh_sh4_build_float_register_type (int high)
1329 {
1330 struct type *temp;
1331
1332 temp = create_range_type (NULL, builtin_type_int, 0, high);
1333 return create_array_type (NULL, builtin_type_float, temp);
1334 }
1335
1336 static struct type *
1337 sh_sh4_register_type (struct gdbarch *gdbarch, int reg_nr)
1338 {
1339 if ((reg_nr >= FP0_REGNUM
1340 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
1341 return builtin_type_float;
1342 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
1343 return builtin_type_double;
1344 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
1345 return sh_sh4_build_float_register_type (3);
1346 else
1347 return builtin_type_int;
1348 }
1349
1350 static struct type *
1351 sh_default_register_type (struct gdbarch *gdbarch, int reg_nr)
1352 {
1353 return builtin_type_int;
1354 }
1355
1356 /* On the sh4, the DRi pseudo registers are problematic if the target
1357 is little endian. When the user writes one of those registers, for
1358 instance with 'ser var $dr0=1', we want the double to be stored
1359 like this:
1360 fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
1361 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1362
1363 This corresponds to little endian byte order & big endian word
1364 order. However if we let gdb write the register w/o conversion, it
1365 will write fr0 and fr1 this way:
1366 fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1367 fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
1368 because it will consider fr0 and fr1 as a single LE stretch of memory.
1369
1370 To achieve what we want we must force gdb to store things in
1371 floatformat_ieee_double_littlebyte_bigword (which is defined in
1372 include/floatformat.h and libiberty/floatformat.c.
1373
1374 In case the target is big endian, there is no problem, the
1375 raw bytes will look like:
1376 fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
1377 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1378
1379 The other pseudo registers (the FVs) also don't pose a problem
1380 because they are stored as 4 individual FP elements. */
1381
1382 static void
1383 sh_sh4_register_convert_to_virtual (int regnum, struct type *type,
1384 char *from, char *to)
1385 {
1386 if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
1387 {
1388 DOUBLEST val;
1389 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
1390 from, &val);
1391 store_typed_floating (to, type, val);
1392 }
1393 else
1394 error
1395 ("sh_register_convert_to_virtual called with non DR register number");
1396 }
1397
1398 static void
1399 sh_sh4_register_convert_to_raw (struct type *type, int regnum,
1400 const void *from, void *to)
1401 {
1402 if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
1403 {
1404 DOUBLEST val = extract_typed_floating (from, type);
1405 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword,
1406 &val, to);
1407 }
1408 else
1409 error ("sh_register_convert_to_raw called with non DR register number");
1410 }
1411
1412 /* For vectors of 4 floating point registers. */
1413 static int
1414 fv_reg_base_num (int fv_regnum)
1415 {
1416 int fp_regnum;
1417
1418 fp_regnum = FP0_REGNUM + (fv_regnum - FV0_REGNUM) * 4;
1419 return fp_regnum;
1420 }
1421
1422 /* For double precision floating point registers, i.e 2 fp regs.*/
1423 static int
1424 dr_reg_base_num (int dr_regnum)
1425 {
1426 int fp_regnum;
1427
1428 fp_regnum = FP0_REGNUM + (dr_regnum - DR0_REGNUM) * 2;
1429 return fp_regnum;
1430 }
1431
1432 static void
1433 sh_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
1434 int reg_nr, void *buffer)
1435 {
1436 int base_regnum, portion;
1437 char temp_buffer[MAX_REGISTER_SIZE];
1438
1439 if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
1440 {
1441 base_regnum = dr_reg_base_num (reg_nr);
1442
1443 /* Build the value in the provided buffer. */
1444 /* Read the real regs for which this one is an alias. */
1445 for (portion = 0; portion < 2; portion++)
1446 regcache_raw_read (regcache, base_regnum + portion,
1447 (temp_buffer
1448 + register_size (gdbarch,
1449 base_regnum) * portion));
1450 /* We must pay attention to the endiannes. */
1451 sh_sh4_register_convert_to_virtual (reg_nr,
1452 gdbarch_register_type (gdbarch,
1453 reg_nr),
1454 temp_buffer, buffer);
1455 }
1456 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
1457 {
1458 base_regnum = fv_reg_base_num (reg_nr);
1459
1460 /* Read the real regs for which this one is an alias. */
1461 for (portion = 0; portion < 4; portion++)
1462 regcache_raw_read (regcache, base_regnum + portion,
1463 ((char *) buffer
1464 + register_size (gdbarch,
1465 base_regnum) * portion));
1466 }
1467 }
1468
1469 static void
1470 sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
1471 int reg_nr, const void *buffer)
1472 {
1473 int base_regnum, portion;
1474 char temp_buffer[MAX_REGISTER_SIZE];
1475
1476 if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
1477 {
1478 base_regnum = dr_reg_base_num (reg_nr);
1479
1480 /* We must pay attention to the endiannes. */
1481 sh_sh4_register_convert_to_raw (gdbarch_register_type (gdbarch, reg_nr),
1482 reg_nr, buffer, temp_buffer);
1483
1484 /* Write the real regs for which this one is an alias. */
1485 for (portion = 0; portion < 2; portion++)
1486 regcache_raw_write (regcache, base_regnum + portion,
1487 (temp_buffer
1488 + register_size (gdbarch,
1489 base_regnum) * portion));
1490 }
1491 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
1492 {
1493 base_regnum = fv_reg_base_num (reg_nr);
1494
1495 /* Write the real regs for which this one is an alias. */
1496 for (portion = 0; portion < 4; portion++)
1497 regcache_raw_write (regcache, base_regnum + portion,
1498 ((char *) buffer
1499 + register_size (gdbarch,
1500 base_regnum) * portion));
1501 }
1502 }
1503
1504 /* Floating point vector of 4 float registers. */
1505 static void
1506 do_fv_register_info (struct gdbarch *gdbarch, struct ui_file *file,
1507 int fv_regnum)
1508 {
1509 int first_fp_reg_num = fv_reg_base_num (fv_regnum);
1510 fprintf_filtered (file, "fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
1511 fv_regnum - FV0_REGNUM,
1512 (int) read_register (first_fp_reg_num),
1513 (int) read_register (first_fp_reg_num + 1),
1514 (int) read_register (first_fp_reg_num + 2),
1515 (int) read_register (first_fp_reg_num + 3));
1516 }
1517
1518 /* Double precision registers. */
1519 static void
1520 do_dr_register_info (struct gdbarch *gdbarch, struct ui_file *file,
1521 int dr_regnum)
1522 {
1523 int first_fp_reg_num = dr_reg_base_num (dr_regnum);
1524
1525 fprintf_filtered (file, "dr%d\t0x%08x%08x\n",
1526 dr_regnum - DR0_REGNUM,
1527 (int) read_register (first_fp_reg_num),
1528 (int) read_register (first_fp_reg_num + 1));
1529 }
1530
1531 static void
1532 sh_print_pseudo_register (struct gdbarch *gdbarch, struct ui_file *file,
1533 int regnum)
1534 {
1535 if (regnum < NUM_REGS || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
1536 internal_error (__FILE__, __LINE__,
1537 "Invalid pseudo register number %d\n", regnum);
1538 else if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
1539 do_dr_register_info (gdbarch, file, regnum);
1540 else if (regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM)
1541 do_fv_register_info (gdbarch, file, regnum);
1542 }
1543
1544 static void
1545 sh_do_fp_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
1546 { /* do values for FP (float) regs */
1547 char *raw_buffer;
1548 double flt; /* double extracted from raw hex data */
1549 int inv;
1550 int j;
1551
1552 /* Allocate space for the float. */
1553 raw_buffer = (char *) alloca (register_size (gdbarch, FP0_REGNUM));
1554
1555 /* Get the data in raw format. */
1556 if (!frame_register_read (get_selected_frame (), regnum, raw_buffer))
1557 error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum));
1558
1559 /* Get the register as a number */
1560 flt = unpack_double (builtin_type_float, raw_buffer, &inv);
1561
1562 /* Print the name and some spaces. */
1563 fputs_filtered (REGISTER_NAME (regnum), file);
1564 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file);
1565
1566 /* Print the value. */
1567 if (inv)
1568 fprintf_filtered (file, "<invalid float>");
1569 else
1570 fprintf_filtered (file, "%-10.9g", flt);
1571
1572 /* Print the fp register as hex. */
1573 fprintf_filtered (file, "\t(raw 0x");
1574 for (j = 0; j < register_size (gdbarch, regnum); j++)
1575 {
1576 int idx = (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
1577 ? j
1578 : register_size (gdbarch, regnum) - 1 - j);
1579 fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[idx]);
1580 }
1581 fprintf_filtered (file, ")");
1582 fprintf_filtered (file, "\n");
1583 }
1584
1585 static void
1586 sh_do_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
1587 {
1588 char raw_buffer[MAX_REGISTER_SIZE];
1589
1590 fputs_filtered (REGISTER_NAME (regnum), file);
1591 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file);
1592
1593 /* Get the data in raw format. */
1594 if (!frame_register_read (get_selected_frame (), regnum, raw_buffer))
1595 fprintf_filtered (file, "*value not available*\n");
1596
1597 val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0,
1598 file, 'x', 1, 0, Val_pretty_default);
1599 fprintf_filtered (file, "\t");
1600 val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0,
1601 file, 0, 1, 0, Val_pretty_default);
1602 fprintf_filtered (file, "\n");
1603 }
1604
1605 static void
1606 sh_print_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
1607 {
1608 if (regnum < 0 || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
1609 internal_error (__FILE__, __LINE__,
1610 "Invalid register number %d\n", regnum);
1611
1612 else if (regnum >= 0 && regnum < NUM_REGS)
1613 {
1614 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) ==
1615 TYPE_CODE_FLT)
1616 sh_do_fp_register (gdbarch, file, regnum); /* FP regs */
1617 else
1618 sh_do_register (gdbarch, file, regnum); /* All other regs */
1619 }
1620
1621 else if (regnum < NUM_REGS + NUM_PSEUDO_REGS)
1622 {
1623 sh_print_pseudo_register (gdbarch, file, regnum);
1624 }
1625 }
1626
1627 static void
1628 sh_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
1629 struct frame_info *frame, int regnum, int fpregs)
1630 {
1631 if (regnum != -1) /* do one specified register */
1632 {
1633 if (*(REGISTER_NAME (regnum)) == '\0')
1634 error ("Not a valid register for the current processor type");
1635
1636 sh_print_register (gdbarch, file, regnum);
1637 }
1638 else
1639 /* do all (or most) registers */
1640 {
1641 regnum = 0;
1642 while (regnum < NUM_REGS)
1643 {
1644 /* If the register name is empty, it is undefined for this
1645 processor, so don't display anything. */
1646 if (REGISTER_NAME (regnum) == NULL
1647 || *(REGISTER_NAME (regnum)) == '\0')
1648 {
1649 regnum++;
1650 continue;
1651 }
1652
1653 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) ==
1654 TYPE_CODE_FLT)
1655 {
1656 if (fpregs)
1657 {
1658 /* true for "INFO ALL-REGISTERS" command */
1659 sh_do_fp_register (gdbarch, file, regnum); /* FP regs */
1660 regnum++;
1661 }
1662 else
1663 regnum += (FP_LAST_REGNUM - FP0_REGNUM); /* skip FP regs */
1664 }
1665 else
1666 {
1667 sh_do_register (gdbarch, file, regnum); /* All other regs */
1668 regnum++;
1669 }
1670 }
1671
1672 if (fpregs)
1673 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
1674 {
1675 sh_print_pseudo_register (gdbarch, file, regnum);
1676 regnum++;
1677 }
1678 }
1679 }
1680
1681 #ifdef SVR4_SHARED_LIBS
1682
1683 /* Fetch (and possibly build) an appropriate link_map_offsets structure
1684 for native i386 linux targets using the struct offsets defined in
1685 link.h (but without actual reference to that file).
1686
1687 This makes it possible to access i386-linux shared libraries from
1688 a gdb that was not built on an i386-linux host (for cross debugging).
1689 */
1690
1691 struct link_map_offsets *
1692 sh_linux_svr4_fetch_link_map_offsets (void)
1693 {
1694 static struct link_map_offsets lmo;
1695 static struct link_map_offsets *lmp = 0;
1696
1697 if (lmp == 0)
1698 {
1699 lmp = &lmo;
1700
1701 lmo.r_debug_size = 8; /* 20 not actual size but all we need */
1702
1703 lmo.r_map_offset = 4;
1704 lmo.r_map_size = 4;
1705
1706 lmo.link_map_size = 20; /* 552 not actual size but all we need */
1707
1708 lmo.l_addr_offset = 0;
1709 lmo.l_addr_size = 4;
1710
1711 lmo.l_name_offset = 4;
1712 lmo.l_name_size = 4;
1713
1714 lmo.l_next_offset = 12;
1715 lmo.l_next_size = 4;
1716
1717 lmo.l_prev_offset = 16;
1718 lmo.l_prev_size = 4;
1719 }
1720
1721 return lmp;
1722 }
1723 #endif /* SVR4_SHARED_LIBS */
1724
1725 static int
1726 sh_dsp_register_sim_regno (int nr)
1727 {
1728 if (legacy_register_sim_regno (nr) < 0)
1729 return legacy_register_sim_regno (nr);
1730 if (nr >= DSR_REGNUM && nr <= Y1_REGNUM)
1731 return nr - DSR_REGNUM + SIM_SH_DSR_REGNUM;
1732 if (nr == MOD_REGNUM)
1733 return SIM_SH_MOD_REGNUM;
1734 if (nr == RS_REGNUM)
1735 return SIM_SH_RS_REGNUM;
1736 if (nr == RE_REGNUM)
1737 return SIM_SH_RE_REGNUM;
1738 if (nr >= R0_BANK_REGNUM && nr <= R7_BANK_REGNUM)
1739 return nr - R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM;
1740 return nr;
1741 }
1742
1743 static struct sh_frame_cache *
1744 sh_alloc_frame_cache (void)
1745 {
1746 struct sh_frame_cache *cache;
1747 int i;
1748
1749 cache = FRAME_OBSTACK_ZALLOC (struct sh_frame_cache);
1750
1751 /* Base address. */
1752 cache->base = 0;
1753 cache->saved_sp = 0;
1754 cache->sp_offset = 0;
1755 cache->pc = 0;
1756
1757 /* Frameless until proven otherwise. */
1758 cache->uses_fp = 0;
1759
1760 /* Saved registers. We initialize these to -1 since zero is a valid
1761 offset (that's where fp is supposed to be stored). */
1762 for (i = 0; i < SH_NUM_REGS; i++)
1763 {
1764 cache->saved_regs[i] = -1;
1765 }
1766
1767 return cache;
1768 }
1769
1770 static struct sh_frame_cache *
1771 sh_frame_cache (struct frame_info *next_frame, void **this_cache)
1772 {
1773 struct sh_frame_cache *cache;
1774 CORE_ADDR current_pc;
1775 int i;
1776
1777 if (*this_cache)
1778 return *this_cache;
1779
1780 cache = sh_alloc_frame_cache ();
1781 *this_cache = cache;
1782
1783 /* In principle, for normal frames, fp holds the frame pointer,
1784 which holds the base address for the current stack frame.
1785 However, for functions that don't need it, the frame pointer is
1786 optional. For these "frameless" functions the frame pointer is
1787 actually the frame pointer of the calling frame. */
1788 cache->base = frame_unwind_register_unsigned (next_frame, FP_REGNUM);
1789 if (cache->base == 0)
1790 return cache;
1791
1792 cache->pc = frame_func_unwind (next_frame);
1793 current_pc = frame_pc_unwind (next_frame);
1794 if (cache->pc != 0)
1795 sh_analyze_prologue (cache->pc, current_pc, cache);
1796
1797 if (!cache->uses_fp)
1798 {
1799 /* We didn't find a valid frame, which means that CACHE->base
1800 currently holds the frame pointer for our calling frame. If
1801 we're at the start of a function, or somewhere half-way its
1802 prologue, the function's frame probably hasn't been fully
1803 setup yet. Try to reconstruct the base address for the stack
1804 frame by looking at the stack pointer. For truly "frameless"
1805 functions this might work too. */
1806 cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
1807 }
1808
1809 /* Now that we have the base address for the stack frame we can
1810 calculate the value of sp in the calling frame. */
1811 cache->saved_sp = cache->base + cache->sp_offset;
1812
1813 /* Adjust all the saved registers such that they contain addresses
1814 instead of offsets. */
1815 for (i = 0; i < SH_NUM_REGS; i++)
1816 if (cache->saved_regs[i] != -1)
1817 cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i] - 4;
1818
1819 return cache;
1820 }
1821
1822 static void
1823 sh_frame_prev_register (struct frame_info *next_frame, void **this_cache,
1824 int regnum, int *optimizedp,
1825 enum lval_type *lvalp, CORE_ADDR *addrp,
1826 int *realnump, void *valuep)
1827 {
1828 struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
1829
1830 gdb_assert (regnum >= 0);
1831
1832 if (regnum == SP_REGNUM && cache->saved_sp)
1833 {
1834 *optimizedp = 0;
1835 *lvalp = not_lval;
1836 *addrp = 0;
1837 *realnump = -1;
1838 if (valuep)
1839 {
1840 /* Store the value. */
1841 store_unsigned_integer (valuep, 4, cache->saved_sp);
1842 }
1843 return;
1844 }
1845
1846 /* The PC of the previous frame is stored in the PR register of
1847 the current frame. Frob regnum so that we pull the value from
1848 the correct place. */
1849 if (regnum == PC_REGNUM)
1850 regnum = PR_REGNUM;
1851
1852 if (regnum < SH_NUM_REGS && cache->saved_regs[regnum] != -1)
1853 {
1854 *optimizedp = 0;
1855 *lvalp = lval_memory;
1856 *addrp = cache->saved_regs[regnum];
1857 *realnump = -1;
1858 if (valuep)
1859 {
1860 /* Read the value in from memory. */
1861 read_memory (*addrp, valuep,
1862 register_size (current_gdbarch, regnum));
1863 }
1864 return;
1865 }
1866
1867 frame_register_unwind (next_frame, regnum,
1868 optimizedp, lvalp, addrp, realnump, valuep);
1869 }
1870
1871 static void
1872 sh_frame_this_id (struct frame_info *next_frame, void **this_cache,
1873 struct frame_id *this_id)
1874 {
1875 struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
1876
1877 /* This marks the outermost frame. */
1878 if (cache->base == 0)
1879 return;
1880
1881 *this_id = frame_id_build (cache->saved_sp, cache->pc);
1882 }
1883
1884 static const struct frame_unwind sh_frame_unwind = {
1885 NORMAL_FRAME,
1886 sh_frame_this_id,
1887 sh_frame_prev_register
1888 };
1889
1890 static const struct frame_unwind *
1891 sh_frame_sniffer (struct frame_info *next_frame)
1892 {
1893 return &sh_frame_unwind;
1894 }
1895
1896 static CORE_ADDR
1897 sh_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1898 {
1899 return frame_unwind_register_unsigned (next_frame, SP_REGNUM);
1900 }
1901
1902 static CORE_ADDR
1903 sh_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1904 {
1905 return frame_unwind_register_unsigned (next_frame, PC_REGNUM);
1906 }
1907
1908 static struct frame_id
1909 sh_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
1910 {
1911 return frame_id_build (sh_unwind_sp (gdbarch, next_frame),
1912 frame_pc_unwind (next_frame));
1913 }
1914
1915 static CORE_ADDR
1916 sh_frame_base_address (struct frame_info *next_frame, void **this_cache)
1917 {
1918 struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
1919
1920 return cache->base;
1921 }
1922
1923 static const struct frame_base sh_frame_base = {
1924 &sh_frame_unwind,
1925 sh_frame_base_address,
1926 sh_frame_base_address,
1927 sh_frame_base_address
1928 };
1929
1930 /* The epilogue is defined here as the area at the end of a function,
1931 either on the `ret' instruction itself or after an instruction which
1932 destroys the function's stack frame. */
1933 static int
1934 sh_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
1935 {
1936 CORE_ADDR func_addr = 0, func_end = 0;
1937
1938 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
1939 {
1940 ULONGEST inst;
1941 /* The sh epilogue is max. 14 bytes long. Give another 14 bytes
1942 for a nop and some fixed data (e.g. big offsets) which are
1943 unfortunately also treated as part of the function (which
1944 means, they are below func_end. */
1945 CORE_ADDR addr = func_end - 28;
1946 if (addr < func_addr + 4)
1947 addr = func_addr + 4;
1948 if (pc < addr)
1949 return 0;
1950
1951 /* First search forward until hitting an rts. */
1952 while (addr < func_end
1953 && !IS_RTS (read_memory_unsigned_integer (addr, 2)))
1954 addr += 2;
1955 if (addr >= func_end)
1956 return 0;
1957
1958 /* At this point we should find a mov.l @r15+,r14 instruction,
1959 either before or after the rts. If not, then the function has
1960 probably no "normal" epilogue and we bail out here. */
1961 inst = read_memory_unsigned_integer (addr - 2, 2);
1962 if (IS_RESTORE_FP (read_memory_unsigned_integer (addr - 2, 2)))
1963 addr -= 2;
1964 else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr + 2, 2)))
1965 return 0;
1966
1967 /* Step over possible lds.l @r15+,pr. */
1968 inst = read_memory_unsigned_integer (addr - 2, 2);
1969 if (IS_LDS (inst))
1970 {
1971 addr -= 2;
1972 inst = read_memory_unsigned_integer (addr - 2, 2);
1973 }
1974
1975 /* Step over possible mov r14,r15. */
1976 if (IS_MOV_FP_SP (inst))
1977 {
1978 addr -= 2;
1979 inst = read_memory_unsigned_integer (addr - 2, 2);
1980 }
1981
1982 /* Now check for FP adjustments, using add #imm,r14 or add rX, r14
1983 instructions. */
1984 while (addr > func_addr + 4
1985 && (IS_ADD_REG_TO_FP (inst) || IS_ADD_IMM_FP (inst)))
1986 {
1987 addr -= 2;
1988 inst = read_memory_unsigned_integer (addr - 2, 2);
1989 }
1990
1991 if (pc >= addr)
1992 return 1;
1993 }
1994 return 0;
1995 }
1996
1997 static gdbarch_init_ftype sh_gdbarch_init;
1998
1999 static struct gdbarch *
2000 sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2001 {
2002 struct gdbarch *gdbarch;
2003
2004 sh_show_regs = sh_generic_show_regs;
2005 switch (info.bfd_arch_info->mach)
2006 {
2007 case bfd_mach_sh2e:
2008 sh_show_regs = sh2e_show_regs;
2009 break;
2010 case bfd_mach_sh_dsp:
2011 sh_show_regs = sh_dsp_show_regs;
2012 break;
2013
2014 case bfd_mach_sh3:
2015 sh_show_regs = sh3_show_regs;
2016 break;
2017
2018 case bfd_mach_sh3e:
2019 sh_show_regs = sh3e_show_regs;
2020 break;
2021
2022 case bfd_mach_sh3_dsp:
2023 sh_show_regs = sh3_dsp_show_regs;
2024 break;
2025
2026 case bfd_mach_sh4:
2027 sh_show_regs = sh4_show_regs;
2028 break;
2029
2030 case bfd_mach_sh5:
2031 sh_show_regs = sh64_show_regs;
2032 /* SH5 is handled entirely in sh64-tdep.c */
2033 return sh64_gdbarch_init (info, arches);
2034 }
2035
2036 /* If there is already a candidate, use it. */
2037 arches = gdbarch_list_lookup_by_info (arches, &info);
2038 if (arches != NULL)
2039 return arches->gdbarch;
2040
2041 /* None found, create a new architecture from the information
2042 provided. */
2043 gdbarch = gdbarch_alloc (&info, NULL);
2044
2045 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2046 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2047 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2048 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2049 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2050 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2051 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2052 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2053
2054 set_gdbarch_num_regs (gdbarch, SH_NUM_REGS);
2055 set_gdbarch_sp_regnum (gdbarch, 15);
2056 set_gdbarch_pc_regnum (gdbarch, 16);
2057 set_gdbarch_fp0_regnum (gdbarch, -1);
2058 set_gdbarch_num_pseudo_regs (gdbarch, 0);
2059
2060 set_gdbarch_register_type (gdbarch, sh_default_register_type);
2061
2062 set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info);
2063
2064 set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc);
2065 set_gdbarch_use_struct_convention (gdbarch, sh_use_struct_convention);
2066
2067 set_gdbarch_print_insn (gdbarch, gdb_print_insn_sh);
2068 set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno);
2069
2070 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
2071
2072 set_gdbarch_store_return_value (gdbarch, sh_default_store_return_value);
2073 set_gdbarch_extract_return_value (gdbarch, sh_default_extract_return_value);
2074 set_gdbarch_extract_struct_value_address (gdbarch,
2075 sh_extract_struct_value_address);
2076
2077 set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue);
2078 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2079 set_gdbarch_decr_pc_after_break (gdbarch, 0);
2080 set_gdbarch_function_start_offset (gdbarch, 0);
2081
2082 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu);
2083
2084 set_gdbarch_frame_args_skip (gdbarch, 0);
2085 set_gdbarch_frameless_function_invocation (gdbarch,
2086 frameless_look_for_prologue);
2087 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2088
2089 set_gdbarch_frame_align (gdbarch, sh_frame_align);
2090 set_gdbarch_unwind_sp (gdbarch, sh_unwind_sp);
2091 set_gdbarch_unwind_pc (gdbarch, sh_unwind_pc);
2092 set_gdbarch_unwind_dummy_id (gdbarch, sh_unwind_dummy_id);
2093 frame_base_set_default (gdbarch, &sh_frame_base);
2094
2095 set_gdbarch_in_function_epilogue_p (gdbarch, sh_in_function_epilogue_p);
2096
2097 switch (info.bfd_arch_info->mach)
2098 {
2099 case bfd_mach_sh:
2100 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
2101 break;
2102
2103 case bfd_mach_sh2:
2104 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
2105 break;
2106
2107 case bfd_mach_sh2e:
2108 /* doubles on sh2e and sh3e are actually 4 byte. */
2109 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2110
2111 set_gdbarch_register_name (gdbarch, sh_sh2e_register_name);
2112 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
2113 set_gdbarch_fp0_regnum (gdbarch, 25);
2114 set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value);
2115 set_gdbarch_extract_return_value (gdbarch,
2116 sh3e_sh4_extract_return_value);
2117 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2118 break;
2119
2120 case bfd_mach_sh_dsp:
2121 set_gdbarch_register_name (gdbarch, sh_sh_dsp_register_name);
2122 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
2123 break;
2124
2125 case bfd_mach_sh3:
2126 set_gdbarch_register_name (gdbarch, sh_sh3_register_name);
2127 break;
2128
2129 case bfd_mach_sh3e:
2130 /* doubles on sh2e and sh3e are actually 4 byte. */
2131 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2132
2133 set_gdbarch_register_name (gdbarch, sh_sh3e_register_name);
2134 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
2135 set_gdbarch_fp0_regnum (gdbarch, 25);
2136 set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value);
2137 set_gdbarch_extract_return_value (gdbarch,
2138 sh3e_sh4_extract_return_value);
2139 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2140 break;
2141
2142 case bfd_mach_sh3_dsp:
2143 set_gdbarch_register_name (gdbarch, sh_sh3_dsp_register_name);
2144 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
2145 break;
2146
2147 case bfd_mach_sh4:
2148 set_gdbarch_register_name (gdbarch, sh_sh4_register_name);
2149 set_gdbarch_register_type (gdbarch, sh_sh4_register_type);
2150 set_gdbarch_fp0_regnum (gdbarch, 25);
2151 set_gdbarch_num_pseudo_regs (gdbarch, 12);
2152 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
2153 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
2154 set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value);
2155 set_gdbarch_extract_return_value (gdbarch,
2156 sh3e_sh4_extract_return_value);
2157 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2158 break;
2159
2160 default:
2161 set_gdbarch_register_name (gdbarch, sh_generic_register_name);
2162 break;
2163 }
2164
2165 /* Hook in ABI-specific overrides, if they have been registered. */
2166 gdbarch_init_osabi (info, gdbarch);
2167
2168 frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer);
2169 frame_unwind_append_sniffer (gdbarch, sh_frame_sniffer);
2170
2171 return gdbarch;
2172 }
2173
2174 extern initialize_file_ftype _initialize_sh_tdep; /* -Wmissing-prototypes */
2175
2176 void
2177 _initialize_sh_tdep (void)
2178 {
2179 struct cmd_list_element *c;
2180
2181 gdbarch_register (bfd_arch_sh, sh_gdbarch_init, NULL);
2182
2183 add_com ("regs", class_vars, sh_show_regs_command, "Print all registers");
2184 }