1 /* Target-dependent code for Hitachi Super-H, for GDB.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
3 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
23 Contributed by Steve Chamberlain
36 #include "inferior.h" /* for BEFORE_TEXT_END etc. */
37 #include "gdb_string.h"
38 #include "arch-utils.h"
39 #include "floatformat.h"
46 #include "solib-svr4.h"
50 /* registers numbers shared with the simulator */
51 #include "gdb/sim-sh.h"
53 void (*sh_show_regs
) (void);
54 CORE_ADDR (*skip_prologue_hard_way
) (CORE_ADDR
);
55 void (*do_pseudo_register
) (int);
57 #define SH_DEFAULT_NUM_REGS 59
59 /* Define other aspects of the stack frame.
60 we keep a copy of the worked out return pc lying around, since it
61 is a useful bit of info */
63 struct frame_extra_info
71 sh_generic_register_name (int reg_nr
)
73 static char *register_names
[] =
75 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
76 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
77 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
79 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
80 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
82 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
83 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
87 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
89 return register_names
[reg_nr
];
93 sh_sh_register_name (int reg_nr
)
95 static char *register_names
[] =
97 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
98 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
99 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
101 "", "", "", "", "", "", "", "",
102 "", "", "", "", "", "", "", "",
104 "", "", "", "", "", "", "", "",
105 "", "", "", "", "", "", "", "",
109 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
111 return register_names
[reg_nr
];
115 sh_sh3_register_name (int reg_nr
)
117 static char *register_names
[] =
119 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
120 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
121 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
123 "", "", "", "", "", "", "", "",
124 "", "", "", "", "", "", "", "",
126 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
127 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
131 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
133 return register_names
[reg_nr
];
137 sh_sh3e_register_name (int reg_nr
)
139 static char *register_names
[] =
141 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
142 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
143 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
145 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
146 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
148 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
149 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
153 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
155 return register_names
[reg_nr
];
159 sh_sh_dsp_register_name (int reg_nr
)
161 static char *register_names
[] =
163 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
164 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
165 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
167 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
168 "y0", "y1", "", "", "", "", "", "mod",
170 "rs", "re", "", "", "", "", "", "",
171 "", "", "", "", "", "", "", "",
175 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
177 return register_names
[reg_nr
];
181 sh_sh3_dsp_register_name (int reg_nr
)
183 static char *register_names
[] =
185 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
186 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
187 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
189 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
190 "y0", "y1", "", "", "", "", "", "mod",
192 "rs", "re", "", "", "", "", "", "",
193 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b"
194 "", "", "", "", "", "", "", "",
198 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
200 return register_names
[reg_nr
];
204 sh_sh4_register_name (int reg_nr
)
206 static char *register_names
[] =
208 /* general registers 0-15 */
209 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
210 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
212 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
215 /* floating point registers 25 - 40 */
216 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
217 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
221 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
223 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
224 /* double precision (pseudo) 59 - 66 */
225 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
226 /* vectors (pseudo) 67 - 70 */
227 "fv0", "fv4", "fv8", "fv12",
228 /* FIXME: missing XF 71 - 86 */
229 /* FIXME: missing XD 87 - 94 */
233 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
235 return register_names
[reg_nr
];
239 sh_sh64_register_name (int reg_nr
)
241 static char *register_names
[] =
243 /* SH MEDIA MODE (ISA 32) */
244 /* general registers (64-bit) 0-63 */
245 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
246 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
247 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
248 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
249 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
250 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
251 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
252 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
257 /* status reg., saved status reg., saved pc reg. (64-bit) 65-67 */
260 /* target registers (64-bit) 68-75*/
261 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7",
263 /* floating point state control register (32-bit) 76 */
266 /* single precision floating point registers (32-bit) 77-140*/
267 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
268 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
269 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23",
270 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31",
271 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39",
272 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47",
273 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55",
274 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63",
276 /* double precision registers (pseudo) 141-172 */
277 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
278 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30",
279 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46",
280 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62",
282 /* floating point pairs (pseudo) 173-204*/
283 "fp0", "fp2", "fp4", "fp6", "fp8", "fp10", "fp12", "fp14",
284 "fp16", "fp18", "fp20", "fp22", "fp24", "fp26", "fp28", "fp30",
285 "fp32", "fp34", "fp36", "fp38", "fp40", "fp42", "fp44", "fp46",
286 "fp48", "fp50", "fp52", "fp54", "fp56", "fp58", "fp60", "fp62",
288 /* floating point vectors (4 floating point regs) (pseudo) 205-220*/
289 "fv0", "fv4", "fv8", "fv12", "fv16", "fv20", "fv24", "fv28",
290 "fv32", "fv36", "fv40", "fv44", "fv48", "fv52", "fv56", "fv60",
292 /* SH COMPACT MODE (ISA 16) (all pseudo) 221-272*/
293 "r0_c", "r1_c", "r2_c", "r3_c", "r4_c", "r5_c", "r6_c", "r7_c",
294 "r8_c", "r9_c", "r10_c", "r11_c", "r12_c", "r13_c", "r14_c", "r15_c",
296 "gbr_c", "mach_c", "macl_c", "pr_c", "t_c",
298 "fr0_c", "fr1_c", "fr2_c", "fr3_c", "fr4_c", "fr5_c", "fr6_c", "fr7_c",
299 "fr8_c", "fr9_c", "fr10_c", "fr11_c", "fr12_c", "fr13_c", "fr14_c", "fr15_c",
300 "dr0_c", "dr2_c", "dr4_c", "dr6_c", "dr8_c", "dr10_c", "dr12_c", "dr14_c",
301 "fv0_c", "fv4_c", "fv8_c", "fv12_c",
302 /* FIXME!!!! XF0 XF15, XD0 XD14 ?????*/
307 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
309 return register_names
[reg_nr
];
312 #define NUM_PSEUDO_REGS_SH_MEDIA 80
313 #define NUM_PSEUDO_REGS_SH_COMPACT 51
315 static const unsigned char *
316 sh_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
318 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */
319 static unsigned char breakpoint
[] = {0xc3, 0xc3};
321 *lenptr
= sizeof (breakpoint
);
325 /* Macros and functions for setting and testing a bit in a minimal
326 symbol that marks it as 32-bit function. The MSB of the minimal
327 symbol's "info" field is used for this purpose. This field is
328 already being used to store the symbol size, so the assumption is
329 that the symbol size cannot exceed 2^31.
331 ELF_MAKE_MSYMBOL_SPECIAL
332 tests whether an ELF symbol is "special", i.e. refers
333 to a 32-bit function, and sets a "special" bit in a
334 minimal symbol to mark it as a 32-bit function
335 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol
336 MSYMBOL_SIZE returns the size of the minimal symbol, i.e.
337 the "info" field with the "special" bit masked out */
339 #define MSYMBOL_IS_SPECIAL(msym) \
340 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
343 sh64_elf_make_msymbol_special (asymbol
*sym
, struct minimal_symbol
*msym
)
348 if (((elf_symbol_type
*)(sym
))->internal_elf_sym
.st_other
== STO_SH5_ISA32
)
350 MSYMBOL_INFO (msym
) = (char *) (((long) MSYMBOL_INFO (msym
)) | 0x80000000);
351 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
355 /* ISA32 (shmedia) function addresses are odd (bit 0 is set). Here
356 are some macros to test, set, or clear bit 0 of addresses. */
357 #define IS_ISA32_ADDR(addr) ((addr) & 1)
358 #define MAKE_ISA32_ADDR(addr) ((addr) | 1)
359 #define UNMAKE_ISA32_ADDR(addr) ((addr) & ~1)
362 pc_is_isa32 (bfd_vma memaddr
)
364 struct minimal_symbol
*sym
;
366 /* If bit 0 of the address is set, assume this is a
367 ISA32 (shmedia) address. */
368 if (IS_ISA32_ADDR (memaddr
))
371 /* A flag indicating that this is a ISA32 function is stored by elfread.c in
372 the high bit of the info field. Use this to decide if the function is
374 sym
= lookup_minimal_symbol_by_pc (memaddr
);
376 return MSYMBOL_IS_SPECIAL (sym
);
381 static const unsigned char *
382 sh_sh64_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
384 /* The BRK instruction for shmedia is
385 01101111 11110101 11111111 11110000
386 which translates in big endian mode to 0x6f, 0xf5, 0xff, 0xf0
387 and in little endian mode to 0xf0, 0xff, 0xf5, 0x6f */
389 /* The BRK instruction for shcompact is
391 which translates in big endian mode to 0x0, 0x3b
392 and in little endian mode to 0x3b, 0x0*/
394 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
396 if (pc_is_isa32 (*pcptr
))
398 static unsigned char big_breakpoint_media
[] = {0x6f, 0xf5, 0xff, 0xf0};
399 *pcptr
= UNMAKE_ISA32_ADDR (*pcptr
);
400 *lenptr
= sizeof (big_breakpoint_media
);
401 return big_breakpoint_media
;
405 static unsigned char big_breakpoint_compact
[] = {0x0, 0x3b};
406 *lenptr
= sizeof (big_breakpoint_compact
);
407 return big_breakpoint_compact
;
412 if (pc_is_isa32 (*pcptr
))
414 static unsigned char little_breakpoint_media
[] = {0xf0, 0xff, 0xf5, 0x6f};
415 *pcptr
= UNMAKE_ISA32_ADDR (*pcptr
);
416 *lenptr
= sizeof (little_breakpoint_media
);
417 return little_breakpoint_media
;
421 static unsigned char little_breakpoint_compact
[] = {0x3b, 0x0};
422 *lenptr
= sizeof (little_breakpoint_compact
);
423 return little_breakpoint_compact
;
428 /* Prologue looks like
429 [mov.l <regs>,@-r15]...
434 Actually it can be more complicated than this. For instance, with
452 /* PTABS/L Rn, TRa 0110101111110001nnnnnnl00aaa0000
453 with l=1 and n = 18 0110101111110001010010100aaa0000 */
454 #define IS_PTABSL_R18(x) (((x) & 0xffffff8f) == 0x6bf14a00)
456 /* STS.L PR,@-r0 0100000000100010
457 r0-4-->r0, PR-->(r0) */
458 #define IS_STS_R0(x) ((x) == 0x4022)
460 /* STS PR, Rm 0000mmmm00101010
462 #define IS_STS_PR(x) (((x) & 0xf0ff) == 0x2a)
464 /* MOV.L Rm,@(disp,r15) 00011111mmmmdddd
466 #define IS_MOV_TO_R15(x) (((x) & 0xff00) == 0x1f00)
468 /* MOV.L R14,@(disp,r15) 000111111110dddd
469 R14-->(dispx4+r15) */
470 #define IS_MOV_R14(x) (((x) & 0xfff0) == 0x1fe0)
472 /* ST.Q R14, disp, R18 101011001110dddddddddd0100100000
473 R18-->(dispx8+R14) */
474 #define IS_STQ_R18_R14(x) (((x) & 0xfff003ff) == 0xace00120)
476 /* ST.Q R15, disp, R18 101011001111dddddddddd0100100000
477 R18-->(dispx8+R15) */
478 #define IS_STQ_R18_R15(x) (((x) & 0xfff003ff) == 0xacf00120)
480 /* ST.L R15, disp, R18 101010001111dddddddddd0100100000
481 R18-->(dispx4+R15) */
482 #define IS_STL_R18_R15(x) (((x) & 0xfff003ff) == 0xa8f00120)
484 /* ST.Q R15, disp, R14 1010 1100 1111 dddd dddd dd00 1110 0000
485 R14-->(dispx8+R15) */
486 #define IS_STQ_R14_R15(x) (((x) & 0xfff003ff) == 0xacf000e0)
488 /* ST.L R15, disp, R14 1010 1000 1111 dddd dddd dd00 1110 0000
489 R14-->(dispx4+R15) */
490 #define IS_STL_R14_R15(x) (((x) & 0xfff003ff) == 0xa8f000e0)
492 /* ADDI.L R15,imm,R15 1101 0100 1111 ssss ssss ss00 1111 0000
494 #define IS_ADDIL_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd4f000f0)
496 /* ADDI R15,imm,R15 1101 0000 1111 ssss ssss ss00 1111 0000
498 #define IS_ADDI_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd0f000f0)
500 /* ADD.L R15,R63,R14 0000 0000 1111 1000 1111 1100 1110 0000
502 #define IS_ADDL_SP_FP_MEDIA(x) ((x) == 0x00f8fce0)
504 /* ADD R15,R63,R14 0000 0000 1111 1001 1111 1100 1110 0000
506 #define IS_ADD_SP_FP_MEDIA(x) ((x) == 0x00f9fce0)
508 #define IS_MOV_SP_FP_MEDIA(x) (IS_ADDL_SP_FP_MEDIA(x) || IS_ADD_SP_FP_MEDIA(x))
510 /* MOV #imm, R0 1110 0000 ssss ssss
512 #define IS_MOV_R0(x) (((x) & 0xff00) == 0xe000)
514 /* MOV.L @(disp,PC), R0 1101 0000 iiii iiii */
515 #define IS_MOVL_R0(x) (((x) & 0xff00) == 0xd000)
517 /* ADD r15,r0 0011 0000 1111 1100
519 #define IS_ADD_SP_R0(x) ((x) == 0x30fc)
521 /* MOV.L R14 @-R0 0010 0000 1110 0110
522 R14-->(R0-4), R0-4-->R0 */
523 #define IS_MOV_R14_R0(x) ((x) == 0x20e6)
525 /* ADD Rm,R63,Rn Rm+R63-->Rn 0000 00mm mmmm 1001 1111 11nn nnnn 0000
526 where Rm is one of r2-r9 which are the argument registers. */
527 /* FIXME: Recognize the float and double register moves too! */
528 #define IS_MEDIA_IND_ARG_MOV(x) \
529 ((((x) & 0xfc0ffc0f) == 0x0009fc00) && (((x) & 0x03f00000) >= 0x00200000 && ((x) & 0x03f00000) <= 0x00900000))
531 /* ST.Q Rn,0,Rm Rm-->Rn+0 1010 11nn nnnn 0000 0000 00mm mmmm 0000
532 or ST.L Rn,0,Rm Rm-->Rn+0 1010 10nn nnnn 0000 0000 00mm mmmm 0000
533 where Rm is one of r2-r9 which are the argument registers. */
534 #define IS_MEDIA_ARG_MOV(x) \
535 (((((x) & 0xfc0ffc0f) == 0xac000000) || (((x) & 0xfc0ffc0f) == 0xa8000000)) \
536 && (((x) & 0x000003f0) >= 0x00000020 && ((x) & 0x000003f0) <= 0x00000090))
538 /* ST.B R14,0,Rn Rn-->(R14+0) 1010 0000 1110 0000 0000 00nn nnnn 0000*/
539 /* ST.W R14,0,Rn Rn-->(R14+0) 1010 0100 1110 0000 0000 00nn nnnn 0000*/
540 /* ST.L R14,0,Rn Rn-->(R14+0) 1010 1000 1110 0000 0000 00nn nnnn 0000*/
541 /* FST.S R14,0,FRn Rn-->(R14+0) 1011 0100 1110 0000 0000 00nn nnnn 0000*/
542 /* FST.D R14,0,DRn Rn-->(R14+0) 1011 1100 1110 0000 0000 00nn nnnn 0000*/
543 #define IS_MEDIA_MOV_TO_R14(x) \
544 ((((x) & 0xfffffc0f) == 0xa0e00000) \
545 || (((x) & 0xfffffc0f) == 0xa4e00000) \
546 || (((x) & 0xfffffc0f) == 0xa8e00000) \
547 || (((x) & 0xfffffc0f) == 0xb4e00000) \
548 || (((x) & 0xfffffc0f) == 0xbce00000))
550 /* MOV Rm, Rn Rm-->Rn 0110 nnnn mmmm 0011
552 #define IS_COMPACT_IND_ARG_MOV(x) \
553 ((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0020) && (((x) & 0x00f0) <= 0x0090))
555 /* compact direct arg move!
556 MOV.L Rn, @r14 0010 1110 mmmm 0010 */
557 #define IS_COMPACT_ARG_MOV(x) \
558 (((((x) & 0xff0f) == 0x2e02) && (((x) & 0x00f0) >= 0x0020) && ((x) & 0x00f0) <= 0x0090))
560 /* MOV.B Rm, @R14 0010 1110 mmmm 0000
561 MOV.W Rm, @R14 0010 1110 mmmm 0001 */
562 #define IS_COMPACT_MOV_TO_R14(x) \
563 ((((x) & 0xff0f) == 0x2e00) || (((x) & 0xff0f) == 0x2e01))
565 #define IS_JSR_R0(x) ((x) == 0x400b)
566 #define IS_NOP(x) ((x) == 0x0009)
569 /* STS.L PR,@-r15 0100111100100010
570 r15-4-->r15, PR-->(r15) */
571 #define IS_STS(x) ((x) == 0x4f22)
573 /* MOV.L Rm,@-r15 00101111mmmm0110
574 r15-4-->r15, Rm-->(R15) */
575 #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
577 #define GET_PUSHED_REG(x) (((x) >> 4) & 0xf)
579 /* MOV r15,r14 0110111011110011
581 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
583 /* ADD #imm,r15 01111111iiiiiiii
585 #define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00)
587 #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
588 #define IS_SHLL_R3(x) ((x) == 0x4300)
590 /* ADD r3,r15 0011111100111100
592 #define IS_ADD_R3SP(x) ((x) == 0x3f3c)
594 /* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
595 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
596 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
597 #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b)
599 /* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011
600 MOV.L Rm,@(disp,Rn) Rm-->(dispx4+Rn) 0001nnnnmmmmdddd
601 MOV.L Rm,@Rn Rm-->(Rn) 0010nnnnmmmm0010
602 where Rm is one of r4,r5,r6,r7 which are the argument registers. */
603 #define IS_ARG_MOV(x) \
604 (((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) \
605 || ((((x) & 0xf000) == 0x1000) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) \
606 || ((((x) & 0xf00f) == 0x2002) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)))
608 /* MOV.L Rm,@(disp,r14) 00011110mmmmdddd
609 Rm-->(dispx4+r14) where Rm is one of r4,r5,r6,r7 */
610 #define IS_MOV_TO_R14(x) \
611 ((((x) & 0xff00) == 0x1e) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070))
613 #define FPSCR_SZ (1 << 20)
615 /* Skip any prologue before the guts of a function */
617 /* Skip the prologue using the debug information. If this fails we'll
618 fall back on the 'guess' method below. */
620 after_prologue (CORE_ADDR pc
)
622 struct symtab_and_line sal
;
623 CORE_ADDR func_addr
, func_end
;
625 /* If we can not find the symbol in the partial symbol table, then
626 there is no hope we can determine the function's start address
628 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
631 /* Get the line associated with FUNC_ADDR. */
632 sal
= find_pc_line (func_addr
, 0);
634 /* There are only two cases to consider. First, the end of the source line
635 is within the function bounds. In that case we return the end of the
636 source line. Second is the end of the source line extends beyond the
637 bounds of the current function. We need to use the slow code to
638 examine instructions in that case. */
639 if (sal
.end
< func_end
)
645 /* Here we look at each instruction in the function, and try to guess
646 where the prologue ends. Unfortunately this is not always
649 sh_skip_prologue_hard_way (CORE_ADDR start_pc
)
657 for (here
= start_pc
, end
= start_pc
+ (2 * 28); here
< end
;)
659 int w
= read_memory_integer (here
, 2);
661 if (IS_FMOV (w
) || IS_PUSH (w
) || IS_STS (w
) || IS_MOV_R3 (w
)
662 || IS_ADD_R3SP (w
) || IS_ADD_SP (w
) || IS_SHLL_R3 (w
)
663 || IS_ARG_MOV (w
) || IS_MOV_TO_R14 (w
))
667 else if (IS_MOV_SP_FP (w
))
673 /* Don't bail out yet, if we are before the copy of sp. */
682 look_for_args_moves (CORE_ADDR start_pc
, int media_mode
)
686 int insn_size
= (media_mode
? 4 : 2);
688 for (here
= start_pc
, end
= start_pc
+ (insn_size
* 28); here
< end
;)
692 w
= read_memory_integer (UNMAKE_ISA32_ADDR (here
), insn_size
);
694 if (IS_MEDIA_IND_ARG_MOV (w
))
696 /* This must be followed by a store to r14, so the argument
697 is where the debug info says it is. This can happen after
698 the SP has been saved, unfortunately. */
700 int next_insn
= read_memory_integer (UNMAKE_ISA32_ADDR (here
),
703 if (IS_MEDIA_MOV_TO_R14 (next_insn
))
706 else if (IS_MEDIA_ARG_MOV (w
))
708 /* These instructions store directly the argument in r14. */
716 w
= read_memory_integer (here
, insn_size
);
719 if (IS_COMPACT_IND_ARG_MOV (w
))
721 /* This must be followed by a store to r14, so the argument
722 is where the debug info says it is. This can happen after
723 the SP has been saved, unfortunately. */
725 int next_insn
= 0xffff & read_memory_integer (here
, insn_size
);
727 if (IS_COMPACT_MOV_TO_R14 (next_insn
))
730 else if (IS_COMPACT_ARG_MOV (w
))
732 /* These instructions store directly the argument in r14. */
735 else if (IS_MOVL_R0 (w
))
737 /* There is a function that gcc calls to get the arguments
738 passed correctly to the function. Only after this
739 function call the arguments will be found at the place
740 where they are supposed to be. This happens in case the
741 argument has to be stored into a 64-bit register (for
742 instance doubles, long longs). SHcompact doesn't have
743 access to the full 64-bits, so we store the register in
744 stack slot and store the address of the stack slot in
745 the register, then do a call through a wrapper that
746 loads the memory value into the register. A SHcompact
747 callee calls an argument decoder
748 (GCC_shcompact_incoming_args) that stores the 64-bit
749 value in a stack slot and stores the address of the
750 stack slot in the register. GCC thinks the argument is
751 just passed by transparent reference, but this is only
752 true after the argument decoder is called. Such a call
753 needs to be considered part of the prologue. */
755 /* This must be followed by a JSR @r0 instruction and by
756 a NOP instruction. After these, the prologue is over! */
758 int next_insn
= 0xffff & read_memory_integer (here
, insn_size
);
760 if (IS_JSR_R0 (next_insn
))
762 next_insn
= 0xffff & read_memory_integer (here
, insn_size
);
765 if (IS_NOP (next_insn
))
778 sh64_skip_prologue_hard_way (CORE_ADDR start_pc
)
788 if (pc_is_isa32 (start_pc
) == 0)
794 for (here
= start_pc
, end
= start_pc
+ (insn_size
* 28); here
< end
;)
799 int w
= read_memory_integer (UNMAKE_ISA32_ADDR (here
), insn_size
);
801 if (IS_STQ_R18_R14 (w
) || IS_STQ_R18_R15 (w
) || IS_STQ_R14_R15 (w
)
802 || IS_STL_R14_R15 (w
) || IS_STL_R18_R15 (w
)
803 || IS_ADDIL_SP_MEDIA (w
) || IS_ADDI_SP_MEDIA (w
) || IS_PTABSL_R18 (w
))
807 else if (IS_MOV_SP_FP (w
) || IS_MOV_SP_FP_MEDIA(w
))
815 /* Don't bail out yet, we may have arguments stored in
816 registers here, according to the debug info, so that
817 gdb can print the frames correctly. */
818 start_pc
= look_for_args_moves (here
- insn_size
, media_mode
);
824 int w
= 0xffff & read_memory_integer (here
, insn_size
);
827 if (IS_STS_R0 (w
) || IS_STS_PR (w
)
828 || IS_MOV_TO_R15 (w
) || IS_MOV_R14 (w
)
829 || IS_MOV_R0 (w
) || IS_ADD_SP_R0 (w
) || IS_MOV_R14_R0 (w
))
833 else if (IS_MOV_SP_FP (w
))
841 /* Don't bail out yet, we may have arguments stored in
842 registers here, according to the debug info, so that
843 gdb can print the frames correctly. */
844 start_pc
= look_for_args_moves (here
- insn_size
, media_mode
);
854 sh_skip_prologue (CORE_ADDR pc
)
856 CORE_ADDR post_prologue_pc
;
858 /* See if we can determine the end of the prologue via the symbol table.
859 If so, then return either PC, or the PC after the prologue, whichever
861 post_prologue_pc
= after_prologue (pc
);
863 /* If after_prologue returned a useful address, then use it. Else
864 fall back on the instruction skipping code. */
865 if (post_prologue_pc
!= 0)
866 return max (pc
, post_prologue_pc
);
868 return (skip_prologue_hard_way (pc
));
871 /* Immediately after a function call, return the saved pc.
872 Can't always go through the frames for this because on some machines
873 the new frame is not set up until the new function executes
876 The return address is the value saved in the PR register + 4 */
878 sh_saved_pc_after_call (struct frame_info
*frame
)
880 return (ADDR_BITS_REMOVE (read_register (gdbarch_tdep (current_gdbarch
)->PR_REGNUM
)));
883 /* Should call_function allocate stack space for a struct return? */
885 sh_use_struct_convention (int gcc_p
, struct type
*type
)
887 return (TYPE_LENGTH (type
) > 1);
891 sh64_use_struct_convention (int gcc_p
, struct type
*type
)
893 return (TYPE_LENGTH (type
) > 8);
896 /* Store the address of the place in which to copy the structure the
897 subroutine will return. This is called from call_function.
899 We store structs through a pointer passed in R2 */
901 sh_store_struct_return (CORE_ADDR addr
, CORE_ADDR sp
)
903 write_register (STRUCT_RETURN_REGNUM
, (addr
));
906 /* Disassemble an instruction. */
908 gdb_print_insn_sh (bfd_vma memaddr
, disassemble_info
*info
)
910 info
->endian
= TARGET_BYTE_ORDER
;
911 return print_insn_sh (memaddr
, info
);
914 /* Given a GDB frame, determine the address of the calling function's frame.
915 This will be used to create a new GDB frame struct, and then
916 INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame.
918 For us, the frame address is its stack pointer value, so we look up
919 the function prologue to determine the caller's sp value, and return it. */
921 sh_frame_chain (struct frame_info
*frame
)
923 if (PC_IN_CALL_DUMMY (frame
->pc
, frame
->frame
, frame
->frame
))
924 return frame
->frame
; /* dummy frame same as caller's frame */
925 if (frame
->pc
&& !inside_entry_file (frame
->pc
))
926 return read_memory_integer (FRAME_FP (frame
) + frame
->extra_info
->f_offset
, 4);
931 /* Given a register number RN as it appears in an assembly
932 instruction, find the corresponding register number in the GDB
935 translate_insn_rn (int rn
, int media_mode
)
937 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
939 /* FIXME: this assumes that the number rn is for a not pseudo
945 /* These registers don't have a corresponding compact one. */
946 /* FIXME: This is probably not enough. */
948 if ((rn
>= 16 && rn
<= 63) || (rn
>= 93 && rn
<= 140))
951 if (rn
>= 0 && rn
<= tdep
->R0_C_REGNUM
)
952 return tdep
->R0_C_REGNUM
+ rn
;
959 sh64_frame_chain (struct frame_info
*frame
)
961 if (PC_IN_CALL_DUMMY (frame
->pc
, frame
->frame
, frame
->frame
))
962 return frame
->frame
; /* dummy frame same as caller's frame */
963 if (frame
->pc
&& !inside_entry_file (frame
->pc
))
965 int media_mode
= pc_is_isa32 (frame
->pc
);
967 if (gdbarch_tdep (current_gdbarch
)->sh_abi
== SH_ABI_32
)
970 size
= REGISTER_RAW_SIZE (translate_insn_rn (FP_REGNUM
, media_mode
));
971 return read_memory_integer (FRAME_FP (frame
) + frame
->extra_info
->f_offset
, size
);
977 /* Find REGNUM on the stack. Otherwise, it's in an active register. One thing
978 we might want to do here is to check REGNUM against the clobber mask, and
979 somehow flag it as invalid if it isn't saved on the stack somewhere. This
980 would provide a graceful failure mode when trying to get the value of
981 caller-saves registers for an inner frame. */
983 sh_find_callers_reg (struct frame_info
*fi
, int regnum
)
985 for (; fi
; fi
= fi
->next
)
986 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
987 /* When the caller requests PR from the dummy frame, we return PC because
988 that's where the previous routine appears to have done a call from. */
989 return generic_read_register_dummy (fi
->pc
, fi
->frame
, regnum
);
992 FRAME_INIT_SAVED_REGS (fi
);
995 if (fi
->saved_regs
[regnum
] != 0)
996 return read_memory_integer (fi
->saved_regs
[regnum
],
997 REGISTER_RAW_SIZE (regnum
));
999 return read_register (regnum
);
1003 sh64_get_saved_pr (struct frame_info
*fi
, int pr_regnum
)
1007 for (; fi
; fi
= fi
->next
)
1008 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
1009 /* When the caller requests PR from the dummy frame, we return PC because
1010 that's where the previous routine appears to have done a call from. */
1011 return generic_read_register_dummy (fi
->pc
, fi
->frame
, pr_regnum
);
1014 FRAME_INIT_SAVED_REGS (fi
);
1018 media_mode
= pc_is_isa32 (fi
->pc
);
1020 if (fi
->saved_regs
[pr_regnum
] != 0)
1022 int gdb_reg_num
= translate_insn_rn (pr_regnum
, media_mode
);
1023 int size
= ((gdbarch_tdep (current_gdbarch
)->sh_abi
== SH_ABI_32
)
1025 : REGISTER_RAW_SIZE (gdb_reg_num
));
1026 return read_memory_integer (fi
->saved_regs
[pr_regnum
], size
);
1029 return read_register (pr_regnum
);
1032 /* Put here the code to store, into a struct frame_saved_regs, the
1033 addresses of the saved registers of frame described by FRAME_INFO.
1034 This includes special registers such as pc and fp saved in special
1035 ways in the stack frame. sp is even more special: the address we
1036 return for it IS the sp for the next frame. */
1038 sh_nofp_frame_init_saved_regs (struct frame_info
*fi
)
1040 int *where
= (int *) alloca ((NUM_REGS
+ NUM_PSEUDO_REGS
) * sizeof(int));
1048 char *dummy_regs
= deprecated_generic_find_dummy_frame (fi
->pc
, fi
->frame
);
1050 if (fi
->saved_regs
== NULL
)
1051 frame_saved_regs_zalloc (fi
);
1053 memset (fi
->saved_regs
, 0, SIZEOF_FRAME_SAVED_REGS
);
1057 /* DANGER! This is ONLY going to work if the char buffer format of
1058 the saved registers is byte-for-byte identical to the
1059 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
1060 memcpy (fi
->saved_regs
, dummy_regs
, sizeof (fi
->saved_regs
));
1064 fi
->extra_info
->leaf_function
= 1;
1065 fi
->extra_info
->f_offset
= 0;
1067 for (rn
= 0; rn
< NUM_REGS
+ NUM_PSEUDO_REGS
; rn
++)
1072 /* Loop around examining the prologue insns until we find something
1073 that does not appear to be part of the prologue. But give up
1074 after 20 of them, since we're getting silly then. */
1076 pc
= get_pc_function_start (fi
->pc
);
1083 for (opc
= pc
+ (2 * 28); pc
< opc
; pc
+= 2)
1085 insn
= read_memory_integer (pc
, 2);
1086 /* See where the registers will be saved to */
1089 rn
= GET_PUSHED_REG (insn
);
1093 else if (IS_STS (insn
))
1095 where
[gdbarch_tdep (current_gdbarch
)->PR_REGNUM
] = depth
;
1096 /* If we're storing the pr then this isn't a leaf */
1097 fi
->extra_info
->leaf_function
= 0;
1100 else if (IS_MOV_R3 (insn
))
1102 r3_val
= ((insn
& 0xff) ^ 0x80) - 0x80;
1104 else if (IS_SHLL_R3 (insn
))
1108 else if (IS_ADD_R3SP (insn
))
1112 else if (IS_ADD_SP (insn
))
1114 depth
-= ((insn
& 0xff) ^ 0x80) - 0x80;
1116 else if (IS_MOV_SP_FP (insn
))
1118 #if 0 /* This used to just stop when it found an instruction that
1119 was not considered part of the prologue. Now, we just
1120 keep going looking for likely instructions. */
1126 /* Now we know how deep things are, we can work out their addresses */
1128 for (rn
= 0; rn
< NUM_REGS
+ NUM_PSEUDO_REGS
; rn
++)
1132 if (rn
== FP_REGNUM
)
1135 fi
->saved_regs
[rn
] = fi
->frame
- where
[rn
] + depth
- 4;
1139 fi
->saved_regs
[rn
] = 0;
1145 fi
->saved_regs
[SP_REGNUM
] = read_memory_integer (fi
->saved_regs
[FP_REGNUM
], 4);
1149 fi
->saved_regs
[SP_REGNUM
] = fi
->frame
- 4;
1152 fi
->extra_info
->f_offset
= depth
- where
[FP_REGNUM
] - 4;
1153 /* Work out the return pc - either from the saved pr or the pr
1157 /* For vectors of 4 floating point registers. */
1159 fv_reg_base_num (int fv_regnum
)
1163 fp_regnum
= FP0_REGNUM
+
1164 (fv_regnum
- gdbarch_tdep (current_gdbarch
)->FV0_REGNUM
) * 4;
1168 /* For double precision floating point registers, i.e 2 fp regs.*/
1170 dr_reg_base_num (int dr_regnum
)
1174 fp_regnum
= FP0_REGNUM
+
1175 (dr_regnum
- gdbarch_tdep (current_gdbarch
)->DR0_REGNUM
) * 2;
1179 /* For pairs of floating point registers */
1181 fpp_reg_base_num (int fpp_regnum
)
1185 fp_regnum
= FP0_REGNUM
+
1186 (fpp_regnum
- gdbarch_tdep (current_gdbarch
)->FPP0_REGNUM
) * 2;
1191 is_media_pseudo (int rn
)
1193 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1195 return (rn
>= tdep
->DR0_REGNUM
1196 && rn
<= tdep
->FV_LAST_REGNUM
);
1200 sh64_get_gdb_regnum (int gcc_regnum
, CORE_ADDR pc
)
1202 return translate_insn_rn (gcc_regnum
, pc_is_isa32 (pc
));
1206 sh64_media_reg_base_num (int reg_nr
)
1208 int base_regnum
= -1;
1209 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1211 if (reg_nr
>= tdep
->DR0_REGNUM
1212 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
1213 base_regnum
= dr_reg_base_num (reg_nr
);
1215 else if (reg_nr
>= tdep
->FPP0_REGNUM
1216 && reg_nr
<= tdep
->FPP_LAST_REGNUM
)
1217 base_regnum
= fpp_reg_base_num (reg_nr
);
1219 else if (reg_nr
>= tdep
->FV0_REGNUM
1220 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
1221 base_regnum
= fv_reg_base_num (reg_nr
);
1228 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
1229 GDB_REGNUM BASE_REGNUM
1289 sh64_compact_reg_base_num (int reg_nr
)
1291 int base_regnum
= -1;
1292 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1294 /* general register N maps to general register N */
1295 if (reg_nr
>= tdep
->R0_C_REGNUM
1296 && reg_nr
<= tdep
->R_LAST_C_REGNUM
)
1297 base_regnum
= reg_nr
- tdep
->R0_C_REGNUM
;
1299 /* floating point register N maps to floating point register N */
1300 else if (reg_nr
>= tdep
->FP0_C_REGNUM
1301 && reg_nr
<= tdep
->FP_LAST_C_REGNUM
)
1302 base_regnum
= reg_nr
- tdep
->FP0_C_REGNUM
+ FP0_REGNUM
;
1304 /* double prec register N maps to base regnum for double prec register N */
1305 else if (reg_nr
>= tdep
->DR0_C_REGNUM
1306 && reg_nr
<= tdep
->DR_LAST_C_REGNUM
)
1307 base_regnum
= dr_reg_base_num (tdep
->DR0_REGNUM
1308 + reg_nr
- tdep
->DR0_C_REGNUM
);
1310 /* vector N maps to base regnum for vector register N */
1311 else if (reg_nr
>= tdep
->FV0_C_REGNUM
1312 && reg_nr
<= tdep
->FV_LAST_C_REGNUM
)
1313 base_regnum
= fv_reg_base_num (tdep
->FV0_REGNUM
1314 + reg_nr
- tdep
->FV0_C_REGNUM
);
1316 else if (reg_nr
== tdep
->PC_C_REGNUM
)
1317 base_regnum
= PC_REGNUM
;
1319 else if (reg_nr
== tdep
->GBR_C_REGNUM
)
1322 else if (reg_nr
== tdep
->MACH_C_REGNUM
1323 || reg_nr
== tdep
->MACL_C_REGNUM
)
1326 else if (reg_nr
== tdep
->PR_C_REGNUM
)
1329 else if (reg_nr
== tdep
->T_C_REGNUM
)
1332 else if (reg_nr
== tdep
->FPSCR_C_REGNUM
)
1333 base_regnum
= tdep
->FPSCR_REGNUM
; /*???? this register is a mess. */
1335 else if (reg_nr
== tdep
->FPUL_C_REGNUM
)
1336 base_regnum
= FP0_REGNUM
+ 32;
1341 /* Given a register number RN (according to the gdb scheme) , return
1342 its corresponding architectural register. In media mode, only a
1343 subset of the registers is pseudo registers. For compact mode, all
1344 the registers are pseudo. */
1346 translate_rn_to_arch_reg_num (int rn
, int media_mode
)
1351 if (!is_media_pseudo (rn
))
1354 return sh64_media_reg_base_num (rn
);
1357 /* All compact registers are pseudo. */
1358 return sh64_compact_reg_base_num (rn
);
1362 sign_extend (int value
, int bits
)
1364 value
= value
& ((1 << bits
) - 1);
1365 return (value
& (1 << (bits
- 1))
1366 ? value
| (~((1 << bits
) - 1))
1371 sh64_nofp_frame_init_saved_regs (struct frame_info
*fi
)
1373 int *where
= (int *) alloca ((NUM_REGS
+ NUM_PSEUDO_REGS
) * sizeof (int));
1385 int gdb_register_number
;
1386 int register_number
;
1387 char *dummy_regs
= deprecated_generic_find_dummy_frame (fi
->pc
, fi
->frame
);
1388 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1390 if (fi
->saved_regs
== NULL
)
1391 frame_saved_regs_zalloc (fi
);
1393 memset (fi
->saved_regs
, 0, SIZEOF_FRAME_SAVED_REGS
);
1397 /* DANGER! This is ONLY going to work if the char buffer format of
1398 the saved registers is byte-for-byte identical to the
1399 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
1400 memcpy (fi
->saved_regs
, dummy_regs
, sizeof (fi
->saved_regs
));
1404 fi
->extra_info
->leaf_function
= 1;
1405 fi
->extra_info
->f_offset
= 0;
1407 for (rn
= 0; rn
< NUM_REGS
+ NUM_PSEUDO_REGS
; rn
++)
1412 /* Loop around examining the prologue insns until we find something
1413 that does not appear to be part of the prologue. But give up
1414 after 20 of them, since we're getting silly then. */
1416 pc
= get_pc_function_start (fi
->pc
);
1423 if (pc_is_isa32 (pc
))
1434 /* The frame pointer register is general register 14 in shmedia and
1435 shcompact modes. In sh compact it is a pseudo register. Same goes
1436 for the stack pointer register, which is register 15. */
1437 fp_regnum
= translate_insn_rn (FP_REGNUM
, media_mode
);
1438 sp_regnum
= translate_insn_rn (SP_REGNUM
, media_mode
);
1440 for (opc
= pc
+ (insn_size
* 28); pc
< opc
; pc
+= insn_size
)
1442 insn
= read_memory_integer (media_mode
? UNMAKE_ISA32_ADDR (pc
) : pc
,
1445 if (media_mode
== 0)
1447 if (IS_STS_PR (insn
))
1449 int next_insn
= read_memory_integer (pc
+ insn_size
, insn_size
);
1450 if (IS_MOV_TO_R15 (next_insn
))
1452 int reg_nr
= tdep
->PR_C_REGNUM
;
1454 where
[reg_nr
] = depth
- ((((next_insn
& 0xf) ^ 0x8) - 0x8) << 2);
1455 fi
->extra_info
->leaf_function
= 0;
1459 else if (IS_MOV_R14 (insn
))
1461 where
[fp_regnum
] = depth
- ((((insn
& 0xf) ^ 0x8) - 0x8) << 2);
1464 else if (IS_MOV_R0 (insn
))
1466 /* Put in R0 the offset from SP at which to store some
1467 registers. We are interested in this value, because it
1468 will tell us where the given registers are stored within
1470 r0_val
= ((insn
& 0xff) ^ 0x80) - 0x80;
1472 else if (IS_ADD_SP_R0 (insn
))
1474 /* This instruction still prepares r0, but we don't care.
1475 We already have the offset in r0_val. */
1477 else if (IS_STS_R0 (insn
))
1479 /* Store PR at r0_val-4 from SP. Decrement r0 by 4*/
1480 int reg_nr
= tdep
->PR_C_REGNUM
;
1481 where
[reg_nr
] = depth
- (r0_val
- 4);
1483 fi
->extra_info
->leaf_function
= 0;
1485 else if (IS_MOV_R14_R0 (insn
))
1487 /* Store R14 at r0_val-4 from SP. Decrement r0 by 4 */
1488 where
[fp_regnum
] = depth
- (r0_val
- 4);
1492 else if (IS_ADD_SP (insn
))
1494 depth
-= ((insn
& 0xff) ^ 0x80) - 0x80;
1496 else if (IS_MOV_SP_FP (insn
))
1501 if (IS_ADDIL_SP_MEDIA (insn
)
1502 || IS_ADDI_SP_MEDIA (insn
))
1504 depth
-= sign_extend ((((insn
& 0xffc00) ^ 0x80000) - 0x80000) >> 10, 9);
1507 else if (IS_STQ_R18_R15 (insn
))
1509 where
[tdep
->PR_REGNUM
] =
1510 depth
- (sign_extend ((insn
& 0xffc00) >> 10, 9) << 3);
1511 fi
->extra_info
->leaf_function
= 0;
1514 else if (IS_STL_R18_R15 (insn
))
1516 where
[tdep
->PR_REGNUM
] =
1517 depth
- (sign_extend ((insn
& 0xffc00) >> 10, 9) << 2);
1518 fi
->extra_info
->leaf_function
= 0;
1521 else if (IS_STQ_R14_R15 (insn
))
1523 where
[fp_regnum
] = depth
- (sign_extend ((insn
& 0xffc00) >> 10, 9) << 3);
1526 else if (IS_STL_R14_R15 (insn
))
1528 where
[fp_regnum
] = depth
- (sign_extend ((insn
& 0xffc00) >> 10, 9) << 2);
1531 else if (IS_MOV_SP_FP_MEDIA (insn
))
1536 /* Now we know how deep things are, we can work out their addresses. */
1537 for (rn
= 0; rn
< NUM_REGS
+ NUM_PSEUDO_REGS
; rn
++)
1539 register_number
= translate_rn_to_arch_reg_num (rn
, media_mode
);
1543 if (rn
== fp_regnum
)
1546 /* Watch out! saved_regs is only for the real registers, and
1547 doesn't include space for the pseudo registers. */
1548 fi
->saved_regs
[register_number
]= fi
->frame
- where
[rn
] + depth
;
1552 fi
->saved_regs
[register_number
] = 0;
1557 /* SP_REGNUM is 15. For shmedia 15 is the real register. For
1558 shcompact 15 is the arch register corresponding to the pseudo
1559 register r15 which still is the SP register. */
1560 /* The place on the stack where fp is stored contains the sp of
1562 /* Again, saved_registers contains only space for the real registers,
1563 so we store in FP_REGNUM position. */
1565 if (tdep
->sh_abi
== SH_ABI_32
)
1568 size
= REGISTER_RAW_SIZE (fp_regnum
);
1569 fi
->saved_regs
[sp_regnum
] = read_memory_integer (fi
->saved_regs
[fp_regnum
], size
);
1572 fi
->saved_regs
[sp_regnum
] = fi
->frame
;
1574 fi
->extra_info
->f_offset
= depth
- where
[fp_regnum
];
1578 sh_fp_frame_init_saved_regs (struct frame_info
*fi
)
1580 int *where
= (int *) alloca ((NUM_REGS
+ NUM_PSEUDO_REGS
) * sizeof (int));
1588 char *dummy_regs
= deprecated_generic_find_dummy_frame (fi
->pc
, fi
->frame
);
1589 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1591 if (fi
->saved_regs
== NULL
)
1592 frame_saved_regs_zalloc (fi
);
1594 memset (fi
->saved_regs
, 0, SIZEOF_FRAME_SAVED_REGS
);
1598 /* DANGER! This is ONLY going to work if the char buffer format of
1599 the saved registers is byte-for-byte identical to the
1600 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
1601 memcpy (fi
->saved_regs
, dummy_regs
, sizeof (fi
->saved_regs
));
1605 fi
->extra_info
->leaf_function
= 1;
1606 fi
->extra_info
->f_offset
= 0;
1608 for (rn
= 0; rn
< NUM_REGS
+ NUM_PSEUDO_REGS
; rn
++)
1613 /* Loop around examining the prologue insns until we find something
1614 that does not appear to be part of the prologue. But give up
1615 after 20 of them, since we're getting silly then. */
1617 pc
= get_pc_function_start (fi
->pc
);
1624 for (opc
= pc
+ (2 * 28); pc
< opc
; pc
+= 2)
1626 insn
= read_memory_integer (pc
, 2);
1627 /* See where the registers will be saved to */
1630 rn
= GET_PUSHED_REG (insn
);
1634 else if (IS_STS (insn
))
1636 where
[tdep
->PR_REGNUM
] = depth
;
1637 /* If we're storing the pr then this isn't a leaf */
1638 fi
->extra_info
->leaf_function
= 0;
1641 else if (IS_MOV_R3 (insn
))
1643 r3_val
= ((insn
& 0xff) ^ 0x80) - 0x80;
1645 else if (IS_SHLL_R3 (insn
))
1649 else if (IS_ADD_R3SP (insn
))
1653 else if (IS_ADD_SP (insn
))
1655 depth
-= ((insn
& 0xff) ^ 0x80) - 0x80;
1657 else if (IS_FMOV (insn
))
1659 if (read_register (tdep
->FPSCR_REGNUM
) & FPSCR_SZ
)
1668 else if (IS_MOV_SP_FP (insn
))
1670 #if 0 /* This used to just stop when it found an instruction that
1671 was not considered part of the prologue. Now, we just
1672 keep going looking for likely instructions. */
1678 /* Now we know how deep things are, we can work out their addresses */
1680 for (rn
= 0; rn
< NUM_REGS
+ NUM_PSEUDO_REGS
; rn
++)
1684 if (rn
== FP_REGNUM
)
1687 fi
->saved_regs
[rn
] = fi
->frame
- where
[rn
] + depth
- 4;
1691 fi
->saved_regs
[rn
] = 0;
1697 fi
->saved_regs
[SP_REGNUM
] =
1698 read_memory_integer (fi
->saved_regs
[FP_REGNUM
], 4);
1702 fi
->saved_regs
[SP_REGNUM
] = fi
->frame
- 4;
1705 fi
->extra_info
->f_offset
= depth
- where
[FP_REGNUM
] - 4;
1706 /* Work out the return pc - either from the saved pr or the pr
1710 /* Initialize the extra info saved in a FRAME */
1712 sh_init_extra_frame_info (int fromleaf
, struct frame_info
*fi
)
1715 fi
->extra_info
= (struct frame_extra_info
*)
1716 frame_obstack_alloc (sizeof (struct frame_extra_info
));
1719 fi
->pc
= FRAME_SAVED_PC (fi
->next
);
1721 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
1723 /* We need to setup fi->frame here because run_stack_dummy gets it wrong
1724 by assuming it's always FP. */
1725 fi
->frame
= generic_read_register_dummy (fi
->pc
, fi
->frame
,
1727 fi
->extra_info
->return_pc
= generic_read_register_dummy (fi
->pc
,
1730 fi
->extra_info
->f_offset
= -(CALL_DUMMY_LENGTH
+ 4);
1731 fi
->extra_info
->leaf_function
= 0;
1736 FRAME_INIT_SAVED_REGS (fi
);
1737 fi
->extra_info
->return_pc
=
1738 sh_find_callers_reg (fi
, gdbarch_tdep (current_gdbarch
)->PR_REGNUM
);
1743 sh64_init_extra_frame_info (int fromleaf
, struct frame_info
*fi
)
1745 int media_mode
= pc_is_isa32 (fi
->pc
);
1747 fi
->extra_info
= (struct frame_extra_info
*)
1748 frame_obstack_alloc (sizeof (struct frame_extra_info
));
1751 fi
->pc
= FRAME_SAVED_PC (fi
->next
);
1753 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
1755 /* We need to setup fi->frame here because run_stack_dummy gets it wrong
1756 by assuming it's always FP. */
1757 fi
->frame
= generic_read_register_dummy (fi
->pc
, fi
->frame
,
1759 fi
->extra_info
->return_pc
=
1760 generic_read_register_dummy (fi
->pc
, fi
->frame
, PC_REGNUM
);
1761 fi
->extra_info
->f_offset
= -(CALL_DUMMY_LENGTH
+ 4);
1762 fi
->extra_info
->leaf_function
= 0;
1767 FRAME_INIT_SAVED_REGS (fi
);
1768 fi
->extra_info
->return_pc
=
1769 sh64_get_saved_pr (fi
, gdbarch_tdep (current_gdbarch
)->PR_REGNUM
);
1774 sh64_get_saved_register (char *raw_buffer
, int *optimized
, CORE_ADDR
*addrp
,
1775 struct frame_info
*frame
, int regnum
,
1776 enum lval_type
*lval
)
1779 int live_regnum
= regnum
;
1780 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1782 if (!target_has_registers
)
1783 error ("No registers.");
1785 /* Normal systems don't optimize out things with register numbers. */
1786 if (optimized
!= NULL
)
1789 if (addrp
) /* default assumption: not found in memory */
1793 memset (raw_buffer
, 0, sizeof (raw_buffer
));
1795 /* We must do this here, before the following while loop changes
1796 frame, and makes it NULL. If this is a media register number,
1797 but we are in compact mode, it will become the corresponding
1798 compact pseudo register. If there is no corresponding compact
1799 pseudo-register what do we do?*/
1800 media_mode
= pc_is_isa32 (frame
->pc
);
1801 live_regnum
= translate_insn_rn (regnum
, media_mode
);
1803 /* Note: since the current frame's registers could only have been
1804 saved by frames INTERIOR TO the current frame, we skip examining
1805 the current frame itself: otherwise, we would be getting the
1806 previous frame's registers which were saved by the current frame. */
1808 while (frame
&& ((frame
= frame
->next
) != NULL
))
1810 if (PC_IN_CALL_DUMMY (frame
->pc
, frame
->frame
, frame
->frame
))
1812 if (lval
) /* found it in a CALL_DUMMY frame */
1816 (deprecated_generic_find_dummy_frame (frame
->pc
, frame
->frame
)
1817 + REGISTER_BYTE (regnum
)),
1818 REGISTER_RAW_SIZE (regnum
));
1822 FRAME_INIT_SAVED_REGS (frame
);
1823 if (frame
->saved_regs
!= NULL
1824 && frame
->saved_regs
[regnum
] != 0)
1826 if (lval
) /* found it saved on the stack */
1827 *lval
= lval_memory
;
1828 if (regnum
== SP_REGNUM
)
1830 if (raw_buffer
) /* SP register treated specially */
1831 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
),
1832 frame
->saved_regs
[regnum
]);
1835 { /* any other register */
1838 *addrp
= frame
->saved_regs
[regnum
];
1842 if (tdep
->sh_abi
== SH_ABI_32
1843 && (live_regnum
== FP_REGNUM
1844 || live_regnum
== tdep
->PR_REGNUM
))
1847 size
= REGISTER_RAW_SIZE (live_regnum
);
1848 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
1849 read_memory (frame
->saved_regs
[regnum
], raw_buffer
, size
);
1851 read_memory (frame
->saved_regs
[regnum
],
1853 + REGISTER_RAW_SIZE (live_regnum
)
1862 /* If we get thru the loop to this point, it means the register was
1863 not saved in any frame. Return the actual live-register value. */
1865 if (lval
) /* found it in a live register */
1866 *lval
= lval_register
;
1868 *addrp
= REGISTER_BYTE (live_regnum
);
1870 read_register_gen (live_regnum
, raw_buffer
);
1873 /* Extract from an array REGBUF containing the (raw) register state
1874 the address in which a function should return its structure value,
1875 as a CORE_ADDR (or an expression that can be used as one). */
1877 sh_extract_struct_value_address (char *regbuf
)
1879 return (extract_address ((regbuf
), REGISTER_RAW_SIZE (0)));
1883 sh64_extract_struct_value_address (char *regbuf
)
1885 return (extract_address ((regbuf
+ REGISTER_BYTE (STRUCT_RETURN_REGNUM
)),
1886 REGISTER_RAW_SIZE (STRUCT_RETURN_REGNUM
)));
1890 sh_frame_saved_pc (struct frame_info
*frame
)
1892 return ((frame
)->extra_info
->return_pc
);
1895 /* Discard from the stack the innermost frame,
1896 restoring all saved registers. */
1900 register struct frame_info
*frame
= get_current_frame ();
1901 register CORE_ADDR fp
;
1902 register int regnum
;
1904 if (PC_IN_CALL_DUMMY (frame
->pc
, frame
->frame
, frame
->frame
))
1905 generic_pop_dummy_frame ();
1908 fp
= FRAME_FP (frame
);
1909 FRAME_INIT_SAVED_REGS (frame
);
1911 /* Copy regs from where they were saved in the frame */
1912 for (regnum
= 0; regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
1913 if (frame
->saved_regs
[regnum
])
1914 write_register (regnum
,
1915 read_memory_integer (frame
->saved_regs
[regnum
], 4));
1917 write_register (PC_REGNUM
, frame
->extra_info
->return_pc
);
1918 write_register (SP_REGNUM
, fp
+ 4);
1920 flush_cached_frames ();
1923 /* Used in the 'return' command. */
1925 sh64_pop_frame (void)
1927 register struct frame_info
*frame
= get_current_frame ();
1928 register CORE_ADDR fp
;
1929 register int regnum
;
1930 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1932 int media_mode
= pc_is_isa32 (frame
->pc
);
1934 if (PC_IN_CALL_DUMMY (frame
->pc
, frame
->frame
, frame
->frame
))
1935 generic_pop_dummy_frame ();
1938 fp
= FRAME_FP (frame
);
1939 FRAME_INIT_SAVED_REGS (frame
);
1941 /* Copy regs from where they were saved in the frame */
1942 for (regnum
= 0; regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
1943 if (frame
->saved_regs
[regnum
])
1946 if (tdep
->sh_abi
== SH_ABI_32
1947 && (regnum
== FP_REGNUM
1948 || regnum
== tdep
->PR_REGNUM
))
1951 size
= REGISTER_RAW_SIZE (translate_insn_rn (regnum
,
1953 write_register (regnum
,
1954 read_memory_integer (frame
->saved_regs
[regnum
],
1958 write_register (PC_REGNUM
, frame
->extra_info
->return_pc
);
1959 write_register (SP_REGNUM
, fp
+ 8);
1961 flush_cached_frames ();
1964 /* Function: push_arguments
1965 Setup the function arguments for calling a function in the inferior.
1967 On the Hitachi SH architecture, there are four registers (R4 to R7)
1968 which are dedicated for passing function arguments. Up to the first
1969 four arguments (depending on size) may go into these registers.
1970 The rest go on the stack.
1972 Arguments that are smaller than 4 bytes will still take up a whole
1973 register or a whole 32-bit word on the stack, and will be
1974 right-justified in the register or the stack word. This includes
1975 chars, shorts, and small aggregate types.
1977 Arguments that are larger than 4 bytes may be split between two or
1978 more registers. If there are not enough registers free, an argument
1979 may be passed partly in a register (or registers), and partly on the
1980 stack. This includes doubles, long longs, and larger aggregates.
1981 As far as I know, there is no upper limit to the size of aggregates
1982 that will be passed in this way; in other words, the convention of
1983 passing a pointer to a large aggregate instead of a copy is not used.
1985 An exceptional case exists for struct arguments (and possibly other
1986 aggregates such as arrays) if the size is larger than 4 bytes but
1987 not a multiple of 4 bytes. In this case the argument is never split
1988 between the registers and the stack, but instead is copied in its
1989 entirety onto the stack, AND also copied into as many registers as
1990 there is room for. In other words, space in registers permitting,
1991 two copies of the same argument are passed in. As far as I can tell,
1992 only the one on the stack is used, although that may be a function
1993 of the level of compiler optimization. I suspect this is a compiler
1994 bug. Arguments of these odd sizes are left-justified within the
1995 word (as opposed to arguments smaller than 4 bytes, which are
1998 If the function is to return an aggregate type such as a struct, it
1999 is either returned in the normal return value register R0 (if its
2000 size is no greater than one byte), or else the caller must allocate
2001 space into which the callee will copy the return value (if the size
2002 is greater than one byte). In this case, a pointer to the return
2003 value location is passed into the callee in register R2, which does
2004 not displace any of the other arguments passed in via registers R4
2008 sh_push_arguments (int nargs
, struct value
**args
, CORE_ADDR sp
,
2009 int struct_return
, CORE_ADDR struct_addr
)
2011 int stack_offset
, stack_alloc
;
2019 int odd_sized_struct
;
2020 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2022 /* first force sp to a 4-byte alignment */
2025 /* The "struct return pointer" pseudo-argument has its own dedicated
2028 write_register (STRUCT_RETURN_REGNUM
, struct_addr
);
2030 /* Now make sure there's space on the stack */
2031 for (argnum
= 0, stack_alloc
= 0; argnum
< nargs
; argnum
++)
2032 stack_alloc
+= ((TYPE_LENGTH (VALUE_TYPE (args
[argnum
])) + 3) & ~3);
2033 sp
-= stack_alloc
; /* make room on stack for args */
2035 /* Now load as many as possible of the first arguments into
2036 registers, and push the rest onto the stack. There are 16 bytes
2037 in four registers available. Loop thru args from first to last. */
2039 argreg
= tdep
->ARG0_REGNUM
;
2040 for (argnum
= 0, stack_offset
= 0; argnum
< nargs
; argnum
++)
2042 type
= VALUE_TYPE (args
[argnum
]);
2043 len
= TYPE_LENGTH (type
);
2044 memset (valbuf
, 0, sizeof (valbuf
));
2047 /* value gets right-justified in the register or stack word */
2048 memcpy (valbuf
+ (4 - len
),
2049 (char *) VALUE_CONTENTS (args
[argnum
]), len
);
2053 val
= (char *) VALUE_CONTENTS (args
[argnum
]);
2055 if (len
> 4 && (len
& 3) != 0)
2056 odd_sized_struct
= 1; /* such structs go entirely on stack */
2058 odd_sized_struct
= 0;
2061 if (argreg
> tdep
->ARGLAST_REGNUM
2062 || odd_sized_struct
)
2064 /* must go on the stack */
2065 write_memory (sp
+ stack_offset
, val
, 4);
2068 /* NOTE WELL!!!!! This is not an "else if" clause!!!
2069 That's because some *&^%$ things get passed on the stack
2070 AND in the registers! */
2071 if (argreg
<= tdep
->ARGLAST_REGNUM
)
2073 /* there's room in a register */
2074 regval
= extract_address (val
, REGISTER_RAW_SIZE (argreg
));
2075 write_register (argreg
++, regval
);
2077 /* Store the value 4 bytes at a time. This means that things
2078 larger than 4 bytes may go partly in registers and partly
2080 len
-= REGISTER_RAW_SIZE (argreg
);
2081 val
+= REGISTER_RAW_SIZE (argreg
);
2087 /* R2-R9 for integer types and integer equivalent (char, pointers) and
2088 non-scalar (struct, union) elements (even if the elements are
2090 FR0-FR11 for single precision floating point (float)
2091 DR0-DR10 for double precision floating point (double)
2093 If a float is argument number 3 (for instance) and arguments number
2094 1,2, and 4 are integer, the mapping will be:
2095 arg1 -->R2, arg2 --> R3, arg3 -->FR0, arg4 --> R5. I.e. R4 is not used.
2097 If a float is argument number 10 (for instance) and arguments number
2098 1 through 10 are integer, the mapping will be:
2099 arg1->R2, arg2->R3, arg3->R4, arg4->R5, arg5->R6, arg6->R7, arg7->R8,
2100 arg8->R9, arg9->(0,SP)stack(8-byte aligned), arg10->FR0, arg11->stack(16,SP).
2101 I.e. there is hole in the stack.
2103 Different rules apply for variable arguments functions, and for functions
2104 for which the prototype is not known. */
2107 sh64_push_arguments (int nargs
, struct value
**args
, CORE_ADDR sp
,
2108 int struct_return
, CORE_ADDR struct_addr
)
2110 int stack_offset
, stack_alloc
;
2114 int float_arg_index
= 0;
2115 int double_arg_index
= 0;
2125 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2127 memset (fp_args
, 0, sizeof (fp_args
));
2129 /* first force sp to a 8-byte alignment */
2132 /* The "struct return pointer" pseudo-argument has its own dedicated
2136 write_register (STRUCT_RETURN_REGNUM
, struct_addr
);
2138 /* Now make sure there's space on the stack */
2139 for (argnum
= 0, stack_alloc
= 0; argnum
< nargs
; argnum
++)
2140 stack_alloc
+= ((TYPE_LENGTH (VALUE_TYPE (args
[argnum
])) + 7) & ~7);
2141 sp
-= stack_alloc
; /* make room on stack for args */
2143 /* Now load as many as possible of the first arguments into
2144 registers, and push the rest onto the stack. There are 64 bytes
2145 in eight registers available. Loop thru args from first to last. */
2147 int_argreg
= tdep
->ARG0_REGNUM
;
2148 float_argreg
= FP0_REGNUM
;
2149 double_argreg
= tdep
->DR0_REGNUM
;
2151 for (argnum
= 0, stack_offset
= 0; argnum
< nargs
; argnum
++)
2153 type
= VALUE_TYPE (args
[argnum
]);
2154 len
= TYPE_LENGTH (type
);
2155 memset (valbuf
, 0, sizeof (valbuf
));
2157 if (TYPE_CODE (type
) != TYPE_CODE_FLT
)
2159 argreg_size
= REGISTER_RAW_SIZE (int_argreg
);
2161 if (len
< argreg_size
)
2163 /* value gets right-justified in the register or stack word */
2164 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2165 memcpy (valbuf
+ argreg_size
- len
,
2166 (char *) VALUE_CONTENTS (args
[argnum
]), len
);
2168 memcpy (valbuf
, (char *) VALUE_CONTENTS (args
[argnum
]), len
);
2173 val
= (char *) VALUE_CONTENTS (args
[argnum
]);
2177 if (int_argreg
> tdep
->ARGLAST_REGNUM
)
2179 /* must go on the stack */
2180 write_memory (sp
+ stack_offset
, val
, argreg_size
);
2181 stack_offset
+= 8;/*argreg_size;*/
2183 /* NOTE WELL!!!!! This is not an "else if" clause!!!
2184 That's because some *&^%$ things get passed on the stack
2185 AND in the registers! */
2186 if (int_argreg
<= tdep
->ARGLAST_REGNUM
)
2188 /* there's room in a register */
2189 regval
= extract_address (val
, argreg_size
);
2190 write_register (int_argreg
, regval
);
2192 /* Store the value 8 bytes at a time. This means that
2193 things larger than 8 bytes may go partly in registers
2194 and partly on the stack. FIXME: argreg is incremented
2195 before we use its size. */
2203 val
= (char *) VALUE_CONTENTS (args
[argnum
]);
2206 /* Where is it going to be stored? */
2207 while (fp_args
[float_arg_index
])
2210 /* Now float_argreg points to the register where it
2211 should be stored. Are we still within the allowed
2213 if (float_arg_index
<= tdep
->FLOAT_ARGLAST_REGNUM
)
2215 /* Goes in FR0...FR11 */
2216 write_register_gen (FP0_REGNUM
+ float_arg_index
, val
);
2217 fp_args
[float_arg_index
] = 1;
2218 /* Skip the corresponding general argument register. */
2223 /* Store it as the integers, 8 bytes at the time, if
2224 necessary spilling on the stack. */
2229 /* Where is it going to be stored? */
2230 while (fp_args
[double_arg_index
])
2231 double_arg_index
+= 2;
2232 /* Now double_argreg points to the register
2233 where it should be stored.
2234 Are we still within the allowed register set? */
2235 if (double_arg_index
< tdep
->FLOAT_ARGLAST_REGNUM
)
2237 /* Goes in DR0...DR10 */
2238 /* The numbering of the DRi registers is consecutive,
2239 i.e. includes odd numbers. */
2240 int double_register_offset
= double_arg_index
/ 2;
2241 int regnum
= tdep
->DR0_REGNUM
+
2242 double_register_offset
;
2244 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
2246 memset (valbuf_tmp
, 0, sizeof (valbuf_tmp
));
2247 REGISTER_CONVERT_TO_VIRTUAL (regnum
,
2248 type
, val
, valbuf_tmp
);
2252 /* Note: must use write_register_gen here instead
2253 of regcache_raw_write, because
2254 regcache_raw_write works only for real
2255 registers, not pseudo. write_register_gen will
2256 call the gdbarch function to do register
2257 writes, and that will properly know how to deal
2259 write_register_gen (regnum
, val
);
2260 fp_args
[double_arg_index
] = 1;
2261 fp_args
[double_arg_index
+ 1] = 1;
2262 /* Skip the corresponding general argument register. */
2267 /* Store it as the integers, 8 bytes at the time, if
2268 necessary spilling on the stack. */
2275 /* Function: push_return_address (pc)
2276 Set up the return address for the inferior function call.
2277 Needed for targets where we don't actually execute a JSR/BSR instruction */
2280 sh_push_return_address (CORE_ADDR pc
, CORE_ADDR sp
)
2282 write_register (gdbarch_tdep (current_gdbarch
)->PR_REGNUM
,
2283 CALL_DUMMY_ADDRESS ());
2287 /* Function: fix_call_dummy
2288 Poke the callee function's address into the destination part of
2289 the CALL_DUMMY. The address is actually stored in a data word
2290 following the actualy CALL_DUMMY instructions, which will load
2291 it into a register using PC-relative addressing. This function
2292 expects the CALL_DUMMY to look like this:
2303 sh_fix_call_dummy (char *dummy
, CORE_ADDR pc
, CORE_ADDR fun
, int nargs
,
2304 struct value
**args
, struct type
*type
, int gcc_p
)
2306 *(unsigned long *) (dummy
+ 8) = fun
;
2311 sh_coerce_float_to_double (struct type
*formal
, struct type
*actual
)
2316 /* Find a function's return value in the appropriate registers (in
2317 regbuf), and copy it into valbuf. Extract from an array REGBUF
2318 containing the (raw) register state a function return value of type
2319 TYPE, and copy that, in virtual format, into VALBUF. */
2321 sh_extract_return_value (struct type
*type
, char *regbuf
, char *valbuf
)
2323 int len
= TYPE_LENGTH (type
);
2324 int return_register
= R0_REGNUM
;
2329 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2330 offset
= REGISTER_BYTE (return_register
) + 4 - len
;
2332 offset
= REGISTER_BYTE (return_register
);
2333 memcpy (valbuf
, regbuf
+ offset
, len
);
2337 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2338 offset
= REGISTER_BYTE (return_register
) + 8 - len
;
2340 offset
= REGISTER_BYTE (return_register
);
2341 memcpy (valbuf
, regbuf
+ offset
, len
);
2344 error ("bad size for return value");
2348 sh3e_sh4_extract_return_value (struct type
*type
, char *regbuf
, char *valbuf
)
2350 int return_register
;
2352 int len
= TYPE_LENGTH (type
);
2354 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2355 return_register
= FP0_REGNUM
;
2357 return_register
= R0_REGNUM
;
2359 if (len
== 8 && TYPE_CODE (type
) == TYPE_CODE_FLT
)
2362 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
2363 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword
,
2364 (char *) regbuf
+ REGISTER_BYTE (return_register
),
2367 floatformat_to_doublest (&floatformat_ieee_double_big
,
2368 (char *) regbuf
+ REGISTER_BYTE (return_register
),
2370 store_floating (valbuf
, len
, val
);
2374 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2375 offset
= REGISTER_BYTE (return_register
) + 4 - len
;
2377 offset
= REGISTER_BYTE (return_register
);
2378 memcpy (valbuf
, regbuf
+ offset
, len
);
2382 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2383 offset
= REGISTER_BYTE (return_register
) + 8 - len
;
2385 offset
= REGISTER_BYTE (return_register
);
2386 memcpy (valbuf
, regbuf
+ offset
, len
);
2389 error ("bad size for return value");
2393 sh64_extract_return_value (struct type
*type
, char *regbuf
, char *valbuf
)
2396 int return_register
;
2397 int len
= TYPE_LENGTH (type
);
2398 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2400 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2404 /* Return value stored in FP0_REGNUM */
2405 return_register
= FP0_REGNUM
;
2406 offset
= REGISTER_BYTE (return_register
);
2407 memcpy (valbuf
, (char *) regbuf
+ offset
, len
);
2411 /* return value stored in DR0_REGNUM */
2414 return_register
= tdep
->DR0_REGNUM
;
2415 offset
= REGISTER_BYTE (return_register
);
2417 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
2418 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword
,
2419 (char *) regbuf
+ offset
, &val
);
2421 floatformat_to_doublest (&floatformat_ieee_double_big
,
2422 (char *) regbuf
+ offset
, &val
);
2423 store_floating (valbuf
, len
, val
);
2430 /* Result is in register 2. If smaller than 8 bytes, it is padded
2431 at the most significant end. */
2432 return_register
= tdep
->RETURN_REGNUM
;
2433 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2434 offset
= REGISTER_BYTE (return_register
) +
2435 REGISTER_RAW_SIZE (return_register
) - len
;
2437 offset
= REGISTER_BYTE (return_register
);
2438 memcpy (valbuf
, (char *) regbuf
+ offset
, len
);
2441 error ("bad size for return value");
2445 /* Write into appropriate registers a function return value
2446 of type TYPE, given in virtual format.
2447 If the architecture is sh4 or sh3e, store a function's return value
2448 in the R0 general register or in the FP0 floating point register,
2449 depending on the type of the return value. In all the other cases
2450 the result is stored in r0, left-justified. */
2452 sh_default_store_return_value (struct type
*type
, char *valbuf
)
2454 char buf
[32]; /* more than enough... */
2456 if (TYPE_LENGTH (type
) < REGISTER_RAW_SIZE (R0_REGNUM
))
2458 /* Add leading zeros to the value. */
2459 memset (buf
, 0, REGISTER_RAW_SIZE (R0_REGNUM
));
2460 memcpy (buf
+ REGISTER_RAW_SIZE (R0_REGNUM
) - TYPE_LENGTH (type
),
2461 valbuf
, TYPE_LENGTH (type
));
2462 write_register_bytes (REGISTER_BYTE (R0_REGNUM
), buf
,
2463 REGISTER_RAW_SIZE (R0_REGNUM
));
2466 write_register_bytes (REGISTER_BYTE (R0_REGNUM
), valbuf
,
2467 TYPE_LENGTH (type
));
2471 sh3e_sh4_store_return_value (struct type
*type
, char *valbuf
)
2473 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2474 write_register_bytes (REGISTER_BYTE (FP0_REGNUM
),
2475 valbuf
, TYPE_LENGTH (type
));
2477 sh_default_store_return_value (type
, valbuf
);
2481 sh64_store_return_value (struct type
*type
, char *valbuf
)
2483 char buf
[64]; /* more than enough... */
2484 int len
= TYPE_LENGTH (type
);
2486 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2490 /* Return value stored in FP0_REGNUM */
2491 write_register_gen (FP0_REGNUM
, valbuf
);
2495 /* return value stored in DR0_REGNUM */
2496 /* FIXME: Implement */
2501 int return_register
= gdbarch_tdep (current_gdbarch
)->RETURN_REGNUM
;
2504 if (len
<= REGISTER_RAW_SIZE (return_register
))
2506 /* Pad with zeros. */
2507 memset (buf
, 0, REGISTER_RAW_SIZE (return_register
));
2508 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
2509 offset
= 0; /*REGISTER_RAW_SIZE (return_register) - len;*/
2511 offset
= REGISTER_RAW_SIZE (return_register
) - len
;
2513 memcpy (buf
+ offset
, valbuf
, len
);
2514 write_register_gen (return_register
, buf
);
2517 write_register_gen (return_register
, valbuf
);
2521 /* Print the registers in a form similar to the E7000 */
2524 sh_generic_show_regs (void)
2526 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2528 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2529 paddr (read_register (PC_REGNUM
)),
2530 (long) read_register (tdep
->SR_REGNUM
),
2531 (long) read_register (tdep
->PR_REGNUM
),
2532 (long) read_register (MACH_REGNUM
),
2533 (long) read_register (MACL_REGNUM
));
2535 printf_filtered ("GBR=%08lx VBR=%08lx",
2536 (long) read_register (GBR_REGNUM
),
2537 (long) read_register (VBR_REGNUM
));
2539 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2540 (long) read_register (0),
2541 (long) read_register (1),
2542 (long) read_register (2),
2543 (long) read_register (3),
2544 (long) read_register (4),
2545 (long) read_register (5),
2546 (long) read_register (6),
2547 (long) read_register (7));
2548 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2549 (long) read_register (8),
2550 (long) read_register (9),
2551 (long) read_register (10),
2552 (long) read_register (11),
2553 (long) read_register (12),
2554 (long) read_register (13),
2555 (long) read_register (14),
2556 (long) read_register (15));
2560 sh3_show_regs (void)
2562 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2564 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2565 paddr (read_register (PC_REGNUM
)),
2566 (long) read_register (tdep
->SR_REGNUM
),
2567 (long) read_register (tdep
->PR_REGNUM
),
2568 (long) read_register (MACH_REGNUM
),
2569 (long) read_register (MACL_REGNUM
));
2571 printf_filtered ("GBR=%08lx VBR=%08lx",
2572 (long) read_register (GBR_REGNUM
),
2573 (long) read_register (VBR_REGNUM
));
2574 printf_filtered (" SSR=%08lx SPC=%08lx",
2575 (long) read_register (tdep
->SSR_REGNUM
),
2576 (long) read_register (tdep
->SPC_REGNUM
));
2578 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2579 (long) read_register (0),
2580 (long) read_register (1),
2581 (long) read_register (2),
2582 (long) read_register (3),
2583 (long) read_register (4),
2584 (long) read_register (5),
2585 (long) read_register (6),
2586 (long) read_register (7));
2587 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2588 (long) read_register (8),
2589 (long) read_register (9),
2590 (long) read_register (10),
2591 (long) read_register (11),
2592 (long) read_register (12),
2593 (long) read_register (13),
2594 (long) read_register (14),
2595 (long) read_register (15));
2600 sh3e_show_regs (void)
2602 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2604 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2605 paddr (read_register (PC_REGNUM
)),
2606 (long) read_register (tdep
->SR_REGNUM
),
2607 (long) read_register (tdep
->PR_REGNUM
),
2608 (long) read_register (MACH_REGNUM
),
2609 (long) read_register (MACL_REGNUM
));
2611 printf_filtered ("GBR=%08lx VBR=%08lx",
2612 (long) read_register (GBR_REGNUM
),
2613 (long) read_register (VBR_REGNUM
));
2614 printf_filtered (" SSR=%08lx SPC=%08lx",
2615 (long) read_register (tdep
->SSR_REGNUM
),
2616 (long) read_register (tdep
->SPC_REGNUM
));
2617 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
2618 (long) read_register (tdep
->FPUL_REGNUM
),
2619 (long) read_register (tdep
->FPSCR_REGNUM
));
2621 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2622 (long) read_register (0),
2623 (long) read_register (1),
2624 (long) read_register (2),
2625 (long) read_register (3),
2626 (long) read_register (4),
2627 (long) read_register (5),
2628 (long) read_register (6),
2629 (long) read_register (7));
2630 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2631 (long) read_register (8),
2632 (long) read_register (9),
2633 (long) read_register (10),
2634 (long) read_register (11),
2635 (long) read_register (12),
2636 (long) read_register (13),
2637 (long) read_register (14),
2638 (long) read_register (15));
2640 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2641 (long) read_register (FP0_REGNUM
+ 0),
2642 (long) read_register (FP0_REGNUM
+ 1),
2643 (long) read_register (FP0_REGNUM
+ 2),
2644 (long) read_register (FP0_REGNUM
+ 3),
2645 (long) read_register (FP0_REGNUM
+ 4),
2646 (long) read_register (FP0_REGNUM
+ 5),
2647 (long) read_register (FP0_REGNUM
+ 6),
2648 (long) read_register (FP0_REGNUM
+ 7));
2649 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2650 (long) read_register (FP0_REGNUM
+ 8),
2651 (long) read_register (FP0_REGNUM
+ 9),
2652 (long) read_register (FP0_REGNUM
+ 10),
2653 (long) read_register (FP0_REGNUM
+ 11),
2654 (long) read_register (FP0_REGNUM
+ 12),
2655 (long) read_register (FP0_REGNUM
+ 13),
2656 (long) read_register (FP0_REGNUM
+ 14),
2657 (long) read_register (FP0_REGNUM
+ 15));
2661 sh3_dsp_show_regs (void)
2663 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2665 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2666 paddr (read_register (PC_REGNUM
)),
2667 (long) read_register (tdep
->SR_REGNUM
),
2668 (long) read_register (tdep
->PR_REGNUM
),
2669 (long) read_register (MACH_REGNUM
),
2670 (long) read_register (MACL_REGNUM
));
2672 printf_filtered ("GBR=%08lx VBR=%08lx",
2673 (long) read_register (GBR_REGNUM
),
2674 (long) read_register (VBR_REGNUM
));
2676 printf_filtered (" SSR=%08lx SPC=%08lx",
2677 (long) read_register (tdep
->SSR_REGNUM
),
2678 (long) read_register (tdep
->SPC_REGNUM
));
2680 printf_filtered (" DSR=%08lx",
2681 (long) read_register (tdep
->DSR_REGNUM
));
2683 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2684 (long) read_register (0),
2685 (long) read_register (1),
2686 (long) read_register (2),
2687 (long) read_register (3),
2688 (long) read_register (4),
2689 (long) read_register (5),
2690 (long) read_register (6),
2691 (long) read_register (7));
2692 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2693 (long) read_register (8),
2694 (long) read_register (9),
2695 (long) read_register (10),
2696 (long) read_register (11),
2697 (long) read_register (12),
2698 (long) read_register (13),
2699 (long) read_register (14),
2700 (long) read_register (15));
2702 printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
2703 (long) read_register (tdep
->A0G_REGNUM
) & 0xff,
2704 (long) read_register (tdep
->A0_REGNUM
),
2705 (long) read_register (tdep
->M0_REGNUM
),
2706 (long) read_register (tdep
->X0_REGNUM
),
2707 (long) read_register (tdep
->Y0_REGNUM
),
2708 (long) read_register (tdep
->RS_REGNUM
),
2709 (long) read_register (tdep
->MOD_REGNUM
));
2710 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
2711 (long) read_register (tdep
->A1G_REGNUM
) & 0xff,
2712 (long) read_register (tdep
->A1_REGNUM
),
2713 (long) read_register (tdep
->M1_REGNUM
),
2714 (long) read_register (tdep
->X1_REGNUM
),
2715 (long) read_register (tdep
->Y1_REGNUM
),
2716 (long) read_register (tdep
->RE_REGNUM
));
2720 sh4_show_regs (void)
2722 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2724 int pr
= read_register (tdep
->FPSCR_REGNUM
) & 0x80000;
2725 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2726 paddr (read_register (PC_REGNUM
)),
2727 (long) read_register (tdep
->SR_REGNUM
),
2728 (long) read_register (tdep
->PR_REGNUM
),
2729 (long) read_register (MACH_REGNUM
),
2730 (long) read_register (MACL_REGNUM
));
2732 printf_filtered ("GBR=%08lx VBR=%08lx",
2733 (long) read_register (GBR_REGNUM
),
2734 (long) read_register (VBR_REGNUM
));
2735 printf_filtered (" SSR=%08lx SPC=%08lx",
2736 (long) read_register (tdep
->SSR_REGNUM
),
2737 (long) read_register (tdep
->SPC_REGNUM
));
2738 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
2739 (long) read_register (tdep
->FPUL_REGNUM
),
2740 (long) read_register (tdep
->FPSCR_REGNUM
));
2742 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2743 (long) read_register (0),
2744 (long) read_register (1),
2745 (long) read_register (2),
2746 (long) read_register (3),
2747 (long) read_register (4),
2748 (long) read_register (5),
2749 (long) read_register (6),
2750 (long) read_register (7));
2751 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2752 (long) read_register (8),
2753 (long) read_register (9),
2754 (long) read_register (10),
2755 (long) read_register (11),
2756 (long) read_register (12),
2757 (long) read_register (13),
2758 (long) read_register (14),
2759 (long) read_register (15));
2761 printf_filtered ((pr
2762 ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
2763 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2764 (long) read_register (FP0_REGNUM
+ 0),
2765 (long) read_register (FP0_REGNUM
+ 1),
2766 (long) read_register (FP0_REGNUM
+ 2),
2767 (long) read_register (FP0_REGNUM
+ 3),
2768 (long) read_register (FP0_REGNUM
+ 4),
2769 (long) read_register (FP0_REGNUM
+ 5),
2770 (long) read_register (FP0_REGNUM
+ 6),
2771 (long) read_register (FP0_REGNUM
+ 7));
2772 printf_filtered ((pr
2773 ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
2774 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2775 (long) read_register (FP0_REGNUM
+ 8),
2776 (long) read_register (FP0_REGNUM
+ 9),
2777 (long) read_register (FP0_REGNUM
+ 10),
2778 (long) read_register (FP0_REGNUM
+ 11),
2779 (long) read_register (FP0_REGNUM
+ 12),
2780 (long) read_register (FP0_REGNUM
+ 13),
2781 (long) read_register (FP0_REGNUM
+ 14),
2782 (long) read_register (FP0_REGNUM
+ 15));
2786 sh_dsp_show_regs (void)
2788 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2790 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2791 paddr (read_register (PC_REGNUM
)),
2792 (long) read_register (tdep
->SR_REGNUM
),
2793 (long) read_register (tdep
->PR_REGNUM
),
2794 (long) read_register (MACH_REGNUM
),
2795 (long) read_register (MACL_REGNUM
));
2797 printf_filtered ("GBR=%08lx VBR=%08lx",
2798 (long) read_register (GBR_REGNUM
),
2799 (long) read_register (VBR_REGNUM
));
2801 printf_filtered (" DSR=%08lx",
2802 (long) read_register (tdep
->DSR_REGNUM
));
2804 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2805 (long) read_register (0),
2806 (long) read_register (1),
2807 (long) read_register (2),
2808 (long) read_register (3),
2809 (long) read_register (4),
2810 (long) read_register (5),
2811 (long) read_register (6),
2812 (long) read_register (7));
2813 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2814 (long) read_register (8),
2815 (long) read_register (9),
2816 (long) read_register (10),
2817 (long) read_register (11),
2818 (long) read_register (12),
2819 (long) read_register (13),
2820 (long) read_register (14),
2821 (long) read_register (15));
2823 printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
2824 (long) read_register (tdep
->A0G_REGNUM
) & 0xff,
2825 (long) read_register (tdep
->A0_REGNUM
),
2826 (long) read_register (tdep
->M0_REGNUM
),
2827 (long) read_register (tdep
->X0_REGNUM
),
2828 (long) read_register (tdep
->Y0_REGNUM
),
2829 (long) read_register (tdep
->RS_REGNUM
),
2830 (long) read_register (tdep
->MOD_REGNUM
));
2831 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
2832 (long) read_register (tdep
->A1G_REGNUM
) & 0xff,
2833 (long) read_register (tdep
->A1_REGNUM
),
2834 (long) read_register (tdep
->M1_REGNUM
),
2835 (long) read_register (tdep
->X1_REGNUM
),
2836 (long) read_register (tdep
->Y1_REGNUM
),
2837 (long) read_register (tdep
->RE_REGNUM
));
2841 sh64_show_media_regs (void)
2844 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2846 printf_filtered ("PC=%s SR=%016llx \n",
2847 paddr (read_register (PC_REGNUM
)),
2848 (long long) read_register (tdep
->SR_REGNUM
));
2850 printf_filtered ("SSR=%016llx SPC=%016llx \n",
2851 (long long) read_register (tdep
->SSR_REGNUM
),
2852 (long long) read_register (tdep
->SPC_REGNUM
));
2853 printf_filtered ("FPSCR=%016lx\n ",
2854 (long) read_register (tdep
->FPSCR_REGNUM
));
2856 for (i
= 0; i
< 64; i
= i
+ 4)
2857 printf_filtered ("\nR%d-R%d %016llx %016llx %016llx %016llx\n",
2859 (long long) read_register (i
+ 0),
2860 (long long) read_register (i
+ 1),
2861 (long long) read_register (i
+ 2),
2862 (long long) read_register (i
+ 3));
2864 printf_filtered ("\n");
2866 for (i
= 0; i
< 64; i
= i
+ 8)
2867 printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2869 (long) read_register (FP0_REGNUM
+ i
+ 0),
2870 (long) read_register (FP0_REGNUM
+ i
+ 1),
2871 (long) read_register (FP0_REGNUM
+ i
+ 2),
2872 (long) read_register (FP0_REGNUM
+ i
+ 3),
2873 (long) read_register (FP0_REGNUM
+ i
+ 4),
2874 (long) read_register (FP0_REGNUM
+ i
+ 5),
2875 (long) read_register (FP0_REGNUM
+ i
+ 6),
2876 (long) read_register (FP0_REGNUM
+ i
+ 7));
2880 sh64_show_compact_regs (void)
2883 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2885 printf_filtered ("PC=%s \n",
2886 paddr (read_register (tdep
->PC_C_REGNUM
)));
2888 printf_filtered ("GBR=%08lx MACH=%08lx MACL=%08lx PR=%08lx T=%08lx\n",
2889 (long) read_register (tdep
->GBR_C_REGNUM
),
2890 (long) read_register (tdep
->MACH_C_REGNUM
),
2891 (long) read_register (tdep
->MACL_C_REGNUM
),
2892 (long) read_register (tdep
->PR_C_REGNUM
),
2893 (long) read_register (tdep
->T_C_REGNUM
));
2894 printf_filtered ("FPSCR=%08lx FPUL=%08lx\n",
2895 (long) read_register (tdep
->FPSCR_REGNUM
),
2896 (long) read_register (tdep
->FPUL_REGNUM
));
2898 for (i
= 0; i
< 16; i
= i
+ 4)
2899 printf_filtered ("\nR%d-R%d %08lx %08lx %08lx %08lx\n",
2901 (long) read_register (i
+ 0),
2902 (long) read_register (i
+ 1),
2903 (long) read_register (i
+ 2),
2904 (long) read_register (i
+ 3));
2906 printf_filtered ("\n");
2908 for (i
= 0; i
< 16; i
= i
+ 8)
2909 printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2911 (long) read_register (FP0_REGNUM
+ i
+ 0),
2912 (long) read_register (FP0_REGNUM
+ i
+ 1),
2913 (long) read_register (FP0_REGNUM
+ i
+ 2),
2914 (long) read_register (FP0_REGNUM
+ i
+ 3),
2915 (long) read_register (FP0_REGNUM
+ i
+ 4),
2916 (long) read_register (FP0_REGNUM
+ i
+ 5),
2917 (long) read_register (FP0_REGNUM
+ i
+ 6),
2918 (long) read_register (FP0_REGNUM
+ i
+ 7));
2921 /*FIXME!!! This only shows the registers for shmedia, excluding the
2922 pseudo registers. */
2924 sh64_show_regs (void)
2926 if (pc_is_isa32 (selected_frame
->pc
))
2927 sh64_show_media_regs ();
2929 sh64_show_compact_regs ();
2932 void sh_show_regs_command (char *args
, int from_tty
)
2938 /* Index within `registers' of the first byte of the space for
2941 sh_default_register_byte (int reg_nr
)
2943 return (reg_nr
* 4);
2947 sh_sh4_register_byte (int reg_nr
)
2949 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2951 if (reg_nr
>= tdep
->DR0_REGNUM
2952 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
2953 return (dr_reg_base_num (reg_nr
) * 4);
2954 else if (reg_nr
>= tdep
->FV0_REGNUM
2955 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
2956 return (fv_reg_base_num (reg_nr
) * 4);
2958 return (reg_nr
* 4);
2963 SH MEDIA MODE (ISA 32)
2964 general registers (64-bit) 0-63
2965 0 r0, r1, r2, r3, r4, r5, r6, r7,
2966 64 r8, r9, r10, r11, r12, r13, r14, r15,
2967 128 r16, r17, r18, r19, r20, r21, r22, r23,
2968 192 r24, r25, r26, r27, r28, r29, r30, r31,
2969 256 r32, r33, r34, r35, r36, r37, r38, r39,
2970 320 r40, r41, r42, r43, r44, r45, r46, r47,
2971 384 r48, r49, r50, r51, r52, r53, r54, r55,
2972 448 r56, r57, r58, r59, r60, r61, r62, r63,
2977 status reg., saved status reg., saved pc reg. (64-bit) 65-67
2980 target registers (64-bit) 68-75
2981 544 tr0, tr1, tr2, tr3, tr4, tr5, tr6, tr7,
2983 floating point state control register (32-bit) 76
2986 single precision floating point registers (32-bit) 77-140
2987 612 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7,
2988 644 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15,
2989 676 fr16, fr17, fr18, fr19, fr20, fr21, fr22, fr23,
2990 708 fr24, fr25, fr26, fr27, fr28, fr29, fr30, fr31,
2991 740 fr32, fr33, fr34, fr35, fr36, fr37, fr38, fr39,
2992 772 fr40, fr41, fr42, fr43, fr44, fr45, fr46, fr47,
2993 804 fr48, fr49, fr50, fr51, fr52, fr53, fr54, fr55,
2994 836 fr56, fr57, fr58, fr59, fr60, fr61, fr62, fr63,
2996 TOTAL SPACE FOR REGISTERS: 868 bytes
2998 From here on they are all pseudo registers: no memory allocated.
2999 REGISTER_BYTE returns the register byte for the base register.
3001 double precision registers (pseudo) 141-172
3002 dr0, dr2, dr4, dr6, dr8, dr10, dr12, dr14,
3003 dr16, dr18, dr20, dr22, dr24, dr26, dr28, dr30,
3004 dr32, dr34, dr36, dr38, dr40, dr42, dr44, dr46,
3005 dr48, dr50, dr52, dr54, dr56, dr58, dr60, dr62,
3007 floating point pairs (pseudo) 173-204
3008 fp0, fp2, fp4, fp6, fp8, fp10, fp12, fp14,
3009 fp16, fp18, fp20, fp22, fp24, fp26, fp28, fp30,
3010 fp32, fp34, fp36, fp38, fp40, fp42, fp44, fp46,
3011 fp48, fp50, fp52, fp54, fp56, fp58, fp60, fp62,
3013 floating point vectors (4 floating point regs) (pseudo) 205-220
3014 fv0, fv4, fv8, fv12, fv16, fv20, fv24, fv28,
3015 fv32, fv36, fv40, fv44, fv48, fv52, fv56, fv60,
3017 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
3018 r0_c, r1_c, r2_c, r3_c, r4_c, r5_c, r6_c, r7_c,
3019 r8_c, r9_c, r10_c, r11_c, r12_c, r13_c, r14_c, r15_c,
3021 gbr_c, mach_c, macl_c, pr_c, t_c,
3023 fr0_c, fr1_c, fr2_c, fr3_c, fr4_c, fr5_c, fr6_c, fr7_c,
3024 fr8_c, fr9_c, fr10_c, fr11_c, fr12_c, fr13_c, fr14_c, fr15_c
3025 dr0_c, dr2_c, dr4_c, dr6_c, dr8_c, dr10_c, dr12_c, dr14_c
3026 fv0_c, fv4_c, fv8_c, fv12_c
3030 sh_sh64_register_byte (int reg_nr
)
3032 int base_regnum
= -1;
3033 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3035 /* If it is a pseudo register, get the number of the first floating
3036 point register that is part of it. */
3037 if (reg_nr
>= tdep
->DR0_REGNUM
3038 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
3039 base_regnum
= dr_reg_base_num (reg_nr
);
3041 else if (reg_nr
>= tdep
->FPP0_REGNUM
3042 && reg_nr
<= tdep
->FPP_LAST_REGNUM
)
3043 base_regnum
= fpp_reg_base_num (reg_nr
);
3045 else if (reg_nr
>= tdep
->FV0_REGNUM
3046 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
3047 base_regnum
= fv_reg_base_num (reg_nr
);
3049 /* sh compact pseudo register. FPSCR is a pathological case, need to
3050 treat it as special. */
3051 else if ((reg_nr
>= tdep
->R0_C_REGNUM
3052 && reg_nr
<= tdep
->FV_LAST_C_REGNUM
)
3053 && reg_nr
!= tdep
->FPSCR_C_REGNUM
)
3054 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3056 /* Now return the offset in bytes within the register cache. */
3057 /* sh media pseudo register, i.e. any of DR, FFP, FV registers. */
3058 if (reg_nr
>= tdep
->DR0_REGNUM
3059 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
3060 return (base_regnum
- FP0_REGNUM
+ 1) * 4
3061 + (tdep
->TR7_REGNUM
+ 1) * 8;
3063 /* sh compact pseudo register: general register */
3064 if ((reg_nr
>= tdep
->R0_C_REGNUM
3065 && reg_nr
<= tdep
->R_LAST_C_REGNUM
))
3066 return (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3067 ? base_regnum
* 8 + 4
3070 /* sh compact pseudo register: */
3071 if (reg_nr
== tdep
->PC_C_REGNUM
3072 || reg_nr
== tdep
->GBR_C_REGNUM
3073 || reg_nr
== tdep
->MACL_C_REGNUM
3074 || reg_nr
== tdep
->PR_C_REGNUM
)
3075 return (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3076 ? base_regnum
* 8 + 4
3079 if (reg_nr
== tdep
->MACH_C_REGNUM
)
3080 return base_regnum
* 8;
3082 if (reg_nr
== tdep
->T_C_REGNUM
)
3083 return base_regnum
* 8; /* FIXME??? how do we get bit 0? Do we have to? */
3085 /* sh compact pseudo register: floating point register */
3086 else if (reg_nr
>=tdep
->FP0_C_REGNUM
3087 && reg_nr
<= tdep
->FV_LAST_C_REGNUM
)
3088 return (base_regnum
- FP0_REGNUM
) * 4
3089 + (tdep
->TR7_REGNUM
+ 1) * 8 + 4;
3091 else if (reg_nr
== tdep
->FPSCR_C_REGNUM
)
3092 /* This is complicated, for now return the beginning of the
3093 architectural FPSCR register. */
3094 return (tdep
->TR7_REGNUM
+ 1) * 8;
3096 else if (reg_nr
== tdep
->FPUL_C_REGNUM
)
3097 return ((base_regnum
- FP0_REGNUM
) * 4 +
3098 (tdep
->TR7_REGNUM
+ 1) * 8 + 4);
3100 /* It is not a pseudo register. */
3101 /* It is a 64 bit register. */
3102 else if (reg_nr
<= tdep
->TR7_REGNUM
)
3105 /* It is a 32 bit register. */
3107 if (reg_nr
== tdep
->FPSCR_REGNUM
)
3108 return (tdep
->FPSCR_REGNUM
* 8);
3110 /* It is floating point 32-bit register */
3112 return ((tdep
->TR7_REGNUM
+ 1) * 8
3113 + (reg_nr
- FP0_REGNUM
+ 1) * 4);
3116 /* Number of bytes of storage in the actual machine representation for
3119 sh_default_register_raw_size (int reg_nr
)
3125 sh_sh4_register_raw_size (int reg_nr
)
3127 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3129 if (reg_nr
>= tdep
->DR0_REGNUM
3130 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
3132 else if (reg_nr
>= tdep
->FV0_REGNUM
3133 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
3140 sh_sh64_register_raw_size (int reg_nr
)
3142 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3144 if ((reg_nr
>= tdep
->DR0_REGNUM
3145 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
3146 || (reg_nr
>= tdep
->FPP0_REGNUM
3147 && reg_nr
<= tdep
->FPP_LAST_REGNUM
)
3148 || (reg_nr
>= tdep
->DR0_C_REGNUM
3149 && reg_nr
<= tdep
->DR_LAST_C_REGNUM
)
3150 || (reg_nr
<= tdep
->TR7_REGNUM
))
3153 else if ((reg_nr
>= tdep
->FV0_REGNUM
3154 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
3155 || (reg_nr
>= tdep
->FV0_C_REGNUM
3156 && reg_nr
<= tdep
->FV_LAST_C_REGNUM
))
3159 else /* this covers also the 32-bit SH compact registers. */
3163 /* Number of bytes of storage in the program's representation
3166 sh_register_virtual_size (int reg_nr
)
3173 sh_sh64_register_virtual_size (int reg_nr
)
3175 if (reg_nr
>= FP0_REGNUM
3176 && reg_nr
<= gdbarch_tdep (current_gdbarch
)->FP_LAST_REGNUM
)
3182 /* Return the GDB type object for the "standard" data type
3183 of data in register N. */
3184 static struct type
*
3185 sh_sh3e_register_virtual_type (int reg_nr
)
3187 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3189 if ((reg_nr
>= FP0_REGNUM
3190 && (reg_nr
<= tdep
->FP_LAST_REGNUM
))
3191 || (reg_nr
== tdep
->FPUL_REGNUM
))
3192 return builtin_type_float
;
3194 return builtin_type_int
;
3197 static struct type
*
3198 sh_sh4_build_float_register_type (int high
)
3202 temp
= create_range_type (NULL
, builtin_type_int
, 0, high
);
3203 return create_array_type (NULL
, builtin_type_float
, temp
);
3206 static struct type
*
3207 sh_sh4_register_virtual_type (int reg_nr
)
3209 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3211 if ((reg_nr
>= FP0_REGNUM
3212 && (reg_nr
<= tdep
->FP_LAST_REGNUM
))
3213 || (reg_nr
== tdep
->FPUL_REGNUM
))
3214 return builtin_type_float
;
3215 else if (reg_nr
>= tdep
->DR0_REGNUM
3216 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
3217 return builtin_type_double
;
3218 else if (reg_nr
>= tdep
->FV0_REGNUM
3219 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
3220 return sh_sh4_build_float_register_type (3);
3222 return builtin_type_int
;
3225 static struct type
*
3226 sh_sh64_register_virtual_type (int reg_nr
)
3228 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3230 if ((reg_nr
>= FP0_REGNUM
3231 && reg_nr
<= tdep
->FP_LAST_REGNUM
)
3232 || (reg_nr
>= tdep
->FP0_C_REGNUM
3233 && reg_nr
<= tdep
->FP_LAST_C_REGNUM
))
3234 return builtin_type_float
;
3235 else if ((reg_nr
>= tdep
->DR0_REGNUM
3236 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
3237 || (reg_nr
>= tdep
->DR0_C_REGNUM
3238 && reg_nr
<= tdep
->DR_LAST_C_REGNUM
))
3239 return builtin_type_double
;
3240 else if (reg_nr
>= tdep
->FPP0_REGNUM
3241 && reg_nr
<= tdep
->FPP_LAST_REGNUM
)
3242 return sh_sh4_build_float_register_type (1);
3243 else if ((reg_nr
>= tdep
->FV0_REGNUM
3244 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
3245 ||(reg_nr
>= tdep
->FV0_C_REGNUM
3246 && reg_nr
<= tdep
->FV_LAST_C_REGNUM
))
3247 return sh_sh4_build_float_register_type (3);
3248 else if (reg_nr
== tdep
->FPSCR_REGNUM
)
3249 return builtin_type_int
;
3250 else if (reg_nr
>= tdep
->R0_C_REGNUM
3251 && reg_nr
< tdep
->FP0_C_REGNUM
)
3252 return builtin_type_int
;
3254 return builtin_type_long_long
;
3257 static struct type
*
3258 sh_default_register_virtual_type (int reg_nr
)
3260 return builtin_type_int
;
3263 /* On the sh4, the DRi pseudo registers are problematic if the target
3264 is little endian. When the user writes one of those registers, for
3265 instance with 'ser var $dr0=1', we want the double to be stored
3267 fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
3268 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
3270 This corresponds to little endian byte order & big endian word
3271 order. However if we let gdb write the register w/o conversion, it
3272 will write fr0 and fr1 this way:
3273 fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
3274 fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
3275 because it will consider fr0 and fr1 as a single LE stretch of memory.
3277 To achieve what we want we must force gdb to store things in
3278 floatformat_ieee_double_littlebyte_bigword (which is defined in
3279 include/floatformat.h and libiberty/floatformat.c.
3281 In case the target is big endian, there is no problem, the
3282 raw bytes will look like:
3283 fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
3284 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
3286 The other pseudo registers (the FVs) also don't pose a problem
3287 because they are stored as 4 individual FP elements. */
3290 sh_sh4_register_convert_to_virtual (int regnum
, struct type
*type
,
3291 char *from
, char *to
)
3293 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3295 if (regnum
>= tdep
->DR0_REGNUM
3296 && regnum
<= tdep
->DR_LAST_REGNUM
)
3299 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword
, from
, &val
);
3300 store_floating (to
, TYPE_LENGTH (type
), val
);
3303 error ("sh_register_convert_to_virtual called with non DR register number");
3307 sh_sh64_register_convert_to_virtual (int regnum
, struct type
*type
,
3308 char *from
, char *to
)
3310 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3312 if (TARGET_BYTE_ORDER
!= BFD_ENDIAN_LITTLE
)
3314 /* It is a no-op. */
3315 memcpy (to
, from
, REGISTER_RAW_SIZE (regnum
));
3319 if ((regnum
>= tdep
->DR0_REGNUM
3320 && regnum
<= tdep
->DR_LAST_REGNUM
)
3321 || (regnum
>= tdep
->DR0_C_REGNUM
3322 && regnum
<= tdep
->DR_LAST_C_REGNUM
))
3325 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword
, from
, &val
);
3326 store_floating(to
, TYPE_LENGTH(type
), val
);
3329 error("sh_register_convert_to_virtual called with non DR register number");
3333 sh_sh4_register_convert_to_raw (struct type
*type
, int regnum
,
3334 char *from
, char *to
)
3336 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3338 if (regnum
>= tdep
->DR0_REGNUM
3339 && regnum
<= tdep
->DR_LAST_REGNUM
)
3341 DOUBLEST val
= extract_floating (from
, TYPE_LENGTH(type
));
3342 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword
, &val
, to
);
3345 error("sh_register_convert_to_raw called with non DR register number");
3349 sh_sh64_register_convert_to_raw (struct type
*type
, int regnum
,
3350 char *from
, char *to
)
3352 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3354 if (TARGET_BYTE_ORDER
!= BFD_ENDIAN_LITTLE
)
3356 /* It is a no-op. */
3357 memcpy (to
, from
, REGISTER_RAW_SIZE (regnum
));
3361 if ((regnum
>= tdep
->DR0_REGNUM
3362 && regnum
<= tdep
->DR_LAST_REGNUM
)
3363 || (regnum
>= tdep
->DR0_C_REGNUM
3364 && regnum
<= tdep
->DR_LAST_C_REGNUM
))
3366 DOUBLEST val
= extract_floating (from
, TYPE_LENGTH(type
));
3367 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword
, &val
, to
);
3370 error("sh_register_convert_to_raw called with non DR register number");
3374 sh_pseudo_register_read (int reg_nr
, char *buffer
)
3376 int base_regnum
, portion
;
3377 char *temp_buffer
= (char*) alloca (MAX_REGISTER_RAW_SIZE
);
3378 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3380 if (reg_nr
>= tdep
->DR0_REGNUM
3381 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
3383 base_regnum
= dr_reg_base_num (reg_nr
);
3385 /* Build the value in the provided buffer. */
3386 /* Read the real regs for which this one is an alias. */
3387 for (portion
= 0; portion
< 2; portion
++)
3388 regcache_raw_read (current_regcache
, base_regnum
+ portion
,
3390 + REGISTER_RAW_SIZE (base_regnum
) * portion
));
3391 /* We must pay attention to the endiannes. */
3392 sh_sh4_register_convert_to_virtual (reg_nr
,
3393 REGISTER_VIRTUAL_TYPE (reg_nr
),
3394 temp_buffer
, buffer
);
3396 else if (reg_nr
>= tdep
->FV0_REGNUM
3397 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
3399 base_regnum
= fv_reg_base_num (reg_nr
);
3401 /* Read the real regs for which this one is an alias. */
3402 for (portion
= 0; portion
< 4; portion
++)
3403 regcache_raw_read (current_regcache
, base_regnum
+ portion
,
3404 buffer
+ REGISTER_RAW_SIZE (base_regnum
) * portion
);
3409 sh4_register_read (struct gdbarch
*gdbarch
, int reg_nr
, char *buffer
)
3411 if (reg_nr
>= 0 && reg_nr
< gdbarch_tdep (current_gdbarch
)->DR0_REGNUM
)
3412 /* It is a regular register. */
3413 regcache_raw_read (current_regcache
, reg_nr
, buffer
);
3415 /* It is a pseudo register and we need to construct its value */
3416 sh_pseudo_register_read (reg_nr
, buffer
);
3420 sh64_pseudo_register_read (int reg_nr
, char *buffer
)
3425 char *temp_buffer
= (char*) alloca (MAX_REGISTER_RAW_SIZE
);
3426 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3428 if (reg_nr
>= tdep
->DR0_REGNUM
3429 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
3431 base_regnum
= dr_reg_base_num (reg_nr
);
3433 /* Build the value in the provided buffer. */
3434 /* DR regs are double precision registers obtained by
3435 concatenating 2 single precision floating point registers. */
3436 for (portion
= 0; portion
< 2; portion
++)
3437 regcache_raw_read (current_regcache
, base_regnum
+ portion
,
3439 + REGISTER_RAW_SIZE (base_regnum
) * portion
));
3441 /* We must pay attention to the endiannes. */
3442 sh_sh64_register_convert_to_virtual (reg_nr
, REGISTER_VIRTUAL_TYPE (reg_nr
),
3443 temp_buffer
, buffer
);
3447 else if (reg_nr
>= tdep
->FPP0_REGNUM
3448 && reg_nr
<= tdep
->FPP_LAST_REGNUM
)
3450 base_regnum
= fpp_reg_base_num (reg_nr
);
3452 /* Build the value in the provided buffer. */
3453 /* FPP regs are pairs of single precision registers obtained by
3454 concatenating 2 single precision floating point registers. */
3455 for (portion
= 0; portion
< 2; portion
++)
3456 regcache_raw_read (current_regcache
, base_regnum
+ portion
,
3458 + REGISTER_RAW_SIZE (base_regnum
) * portion
));
3461 else if (reg_nr
>= tdep
->FV0_REGNUM
3462 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
3464 base_regnum
= fv_reg_base_num (reg_nr
);
3466 /* Build the value in the provided buffer. */
3467 /* FV regs are vectors of single precision registers obtained by
3468 concatenating 4 single precision floating point registers. */
3469 for (portion
= 0; portion
< 4; portion
++)
3470 regcache_raw_read (current_regcache
, base_regnum
+ portion
,
3472 + REGISTER_RAW_SIZE (base_regnum
) * portion
));
3475 /* sh compact pseudo registers. 1-to-1 with a shmedia register */
3476 else if (reg_nr
>= tdep
->R0_C_REGNUM
3477 && reg_nr
<= tdep
->T_C_REGNUM
)
3479 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3481 /* Build the value in the provided buffer. */
3482 regcache_raw_read (current_regcache
, base_regnum
, temp_buffer
);
3483 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3485 memcpy (buffer
, temp_buffer
+ offset
, 4); /* get LOWER 32 bits only????*/
3488 else if (reg_nr
>= tdep
->FP0_C_REGNUM
3489 && reg_nr
<= tdep
->FP_LAST_C_REGNUM
)
3491 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3493 /* Build the value in the provided buffer. */
3494 /* Floating point registers map 1-1 to the media fp regs,
3495 they have the same size and endienness. */
3496 regcache_raw_read (current_regcache
, base_regnum
, buffer
);
3499 else if (reg_nr
>= tdep
->DR0_C_REGNUM
3500 && reg_nr
<= tdep
->DR_LAST_C_REGNUM
)
3502 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3504 /* DR_C regs are double precision registers obtained by
3505 concatenating 2 single precision floating point registers. */
3506 for (portion
= 0; portion
< 2; portion
++)
3507 regcache_raw_read (current_regcache
, base_regnum
+ portion
,
3509 + REGISTER_RAW_SIZE (base_regnum
) * portion
));
3511 /* We must pay attention to the endiannes. */
3512 sh_sh64_register_convert_to_virtual (reg_nr
, REGISTER_VIRTUAL_TYPE (reg_nr
),
3513 temp_buffer
, buffer
);
3516 else if (reg_nr
>= tdep
->FV0_C_REGNUM
3517 && reg_nr
<= tdep
->FV_LAST_C_REGNUM
)
3519 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3521 /* Build the value in the provided buffer. */
3522 /* FV_C regs are vectors of single precision registers obtained by
3523 concatenating 4 single precision floating point registers. */
3524 for (portion
= 0; portion
< 4; portion
++)
3525 regcache_raw_read (current_regcache
, base_regnum
+ portion
,
3527 + REGISTER_RAW_SIZE (base_regnum
) * portion
));
3530 else if (reg_nr
== tdep
->FPSCR_C_REGNUM
)
3532 int fpscr_base_regnum
;
3534 unsigned int fpscr_value
;
3535 unsigned int sr_value
;
3536 unsigned int fpscr_c_value
;
3537 unsigned int fpscr_c_part1_value
;
3538 unsigned int fpscr_c_part2_value
;
3540 fpscr_base_regnum
= tdep
->FPSCR_REGNUM
;
3541 sr_base_regnum
= tdep
->SR_REGNUM
;
3543 /* Build the value in the provided buffer. */
3544 /* FPSCR_C is a very weird register that contains sparse bits
3545 from the FPSCR and the SR architectural registers.
3552 2-17 Bit 2-18 of FPSCR
3553 18-20 Bits 12,13,14 of SR
3557 /* Get FPSCR into a local buffer */
3558 regcache_raw_read (current_regcache
, fpscr_base_regnum
, temp_buffer
);
3559 /* Get value as an int. */
3560 fpscr_value
= extract_unsigned_integer (temp_buffer
, 4);
3561 /* Get SR into a local buffer */
3562 regcache_raw_read (current_regcache
, sr_base_regnum
, temp_buffer
);
3563 /* Get value as an int. */
3564 sr_value
= extract_unsigned_integer (temp_buffer
, 4);
3565 /* Build the new value. */
3566 fpscr_c_part1_value
= fpscr_value
& 0x3fffd;
3567 fpscr_c_part2_value
= (sr_value
& 0x7000) << 6;
3568 fpscr_c_value
= fpscr_c_part1_value
| fpscr_c_part2_value
;
3569 /* Store that in out buffer!!! */
3570 store_unsigned_integer (buffer
, 4, fpscr_c_value
);
3571 /* FIXME There is surely an endianness gotcha here. */
3574 else if (reg_nr
== tdep
->FPUL_C_REGNUM
)
3576 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3578 /* FPUL_C register is floating point register 32,
3579 same size, same endianness. */
3580 regcache_raw_read (current_regcache
, base_regnum
, buffer
);
3585 sh64_register_read (struct gdbarch
*gdbarch
, int reg_nr
, char *buffer
)
3588 if (reg_nr
>= 0 && reg_nr
< gdbarch_tdep (current_gdbarch
)->DR0_REGNUM
)
3589 /* It is a regular register. */
3590 regcache_raw_read (current_regcache
, reg_nr
, buffer
);
3592 /* It is a pseudo register and we need to construct its value */
3593 sh64_pseudo_register_read (reg_nr
, buffer
);
3597 sh_pseudo_register_write (int reg_nr
, char *buffer
)
3599 int base_regnum
, portion
;
3600 char *temp_buffer
= (char*) alloca (MAX_REGISTER_RAW_SIZE
);
3601 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3603 if (reg_nr
>= tdep
->DR0_REGNUM
3604 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
3606 base_regnum
= dr_reg_base_num (reg_nr
);
3608 /* We must pay attention to the endiannes. */
3609 sh_sh4_register_convert_to_raw (REGISTER_VIRTUAL_TYPE (reg_nr
), reg_nr
,
3610 buffer
, temp_buffer
);
3612 /* Write the real regs for which this one is an alias. */
3613 for (portion
= 0; portion
< 2; portion
++)
3614 regcache_raw_write (current_regcache
, base_regnum
+ portion
,
3616 + REGISTER_RAW_SIZE (base_regnum
) * portion
));
3618 else if (reg_nr
>= tdep
->FV0_REGNUM
3619 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
3621 base_regnum
= fv_reg_base_num (reg_nr
);
3623 /* Write the real regs for which this one is an alias. */
3624 for (portion
= 0; portion
< 4; portion
++)
3625 regcache_raw_write (current_regcache
, base_regnum
+ portion
,
3627 + REGISTER_RAW_SIZE (base_regnum
) * portion
));
3632 sh4_register_write (struct gdbarch
*gdbarch
, int reg_nr
, char *buffer
)
3634 if (reg_nr
>= 0 && reg_nr
< gdbarch_tdep (current_gdbarch
)->DR0_REGNUM
)
3635 /* It is a regular register. */
3636 regcache_raw_write (current_regcache
, reg_nr
, buffer
);
3638 /* It is a pseudo register and we need to construct its value */
3639 sh_pseudo_register_write (reg_nr
, buffer
);
3643 sh64_pseudo_register_write (int reg_nr
, char *buffer
)
3645 int base_regnum
, portion
;
3647 char *temp_buffer
= (char*) alloca (MAX_REGISTER_RAW_SIZE
);
3648 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3650 if (reg_nr
>= tdep
->DR0_REGNUM
3651 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
3653 base_regnum
= dr_reg_base_num (reg_nr
);
3654 /* We must pay attention to the endiannes. */
3655 sh_sh64_register_convert_to_raw (REGISTER_VIRTUAL_TYPE (reg_nr
), reg_nr
,
3656 buffer
, temp_buffer
);
3659 /* Write the real regs for which this one is an alias. */
3660 for (portion
= 0; portion
< 2; portion
++)
3661 regcache_raw_write (current_regcache
, base_regnum
+ portion
,
3663 + REGISTER_RAW_SIZE (base_regnum
) * portion
));
3666 else if (reg_nr
>= tdep
->FPP0_REGNUM
3667 && reg_nr
<= tdep
->FPP_LAST_REGNUM
)
3669 base_regnum
= fpp_reg_base_num (reg_nr
);
3671 /* Write the real regs for which this one is an alias. */
3672 for (portion
= 0; portion
< 2; portion
++)
3673 regcache_raw_write (current_regcache
, base_regnum
+ portion
,
3675 + REGISTER_RAW_SIZE (base_regnum
) * portion
));
3678 else if (reg_nr
>= tdep
->FV0_REGNUM
3679 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
3681 base_regnum
= fv_reg_base_num (reg_nr
);
3683 /* Write the real regs for which this one is an alias. */
3684 for (portion
= 0; portion
< 4; portion
++)
3685 regcache_raw_write (current_regcache
, base_regnum
+ portion
,
3687 + REGISTER_RAW_SIZE (base_regnum
) * portion
));
3690 /* sh compact general pseudo registers. 1-to-1 with a shmedia
3691 register but only 4 bytes of it. */
3692 else if (reg_nr
>= tdep
->R0_C_REGNUM
3693 && reg_nr
<= tdep
->T_C_REGNUM
)
3695 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3696 /* reg_nr is 32 bit here, and base_regnum is 64 bits. */
3697 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3701 /* Let's read the value of the base register into a temporary
3702 buffer, so that overwriting the last four bytes with the new
3703 value of the pseudo will leave the upper 4 bytes unchanged. */
3704 regcache_raw_read (current_regcache
, base_regnum
, temp_buffer
);
3705 /* Write as an 8 byte quantity */
3706 memcpy (temp_buffer
+ offset
, buffer
, 4);
3707 regcache_raw_write (current_regcache
, base_regnum
, temp_buffer
);
3710 /* sh floating point compact pseudo registers. 1-to-1 with a shmedia
3711 registers. Both are 4 bytes. */
3712 else if (reg_nr
>= tdep
->FP0_C_REGNUM
3713 && reg_nr
<= tdep
->FP_LAST_C_REGNUM
)
3715 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3716 regcache_raw_write (current_regcache
, base_regnum
, buffer
);
3719 else if (reg_nr
>= tdep
->DR0_C_REGNUM
3720 && reg_nr
<= tdep
->DR_LAST_C_REGNUM
)
3722 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3723 for (portion
= 0; portion
< 2; portion
++)
3725 /* We must pay attention to the endiannes. */
3726 sh_sh64_register_convert_to_raw (REGISTER_VIRTUAL_TYPE (reg_nr
), reg_nr
,
3727 buffer
, temp_buffer
);
3729 regcache_raw_write (current_regcache
, base_regnum
+ portion
,
3731 + REGISTER_RAW_SIZE (base_regnum
) * portion
));
3735 else if (reg_nr
>= tdep
->FV0_C_REGNUM
3736 && reg_nr
<= tdep
->FV_LAST_C_REGNUM
)
3738 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3740 for (portion
= 0; portion
< 4; portion
++)
3742 regcache_raw_write (current_regcache
, base_regnum
+ portion
,
3744 + REGISTER_RAW_SIZE (base_regnum
) * portion
));
3748 else if (reg_nr
== tdep
->FPSCR_C_REGNUM
)
3750 int fpscr_base_regnum
;
3752 unsigned int fpscr_value
;
3753 unsigned int sr_value
;
3754 unsigned int old_fpscr_value
;
3755 unsigned int old_sr_value
;
3756 unsigned int fpscr_c_value
;
3757 unsigned int fpscr_mask
;
3758 unsigned int sr_mask
;
3760 fpscr_base_regnum
= tdep
->FPSCR_REGNUM
;
3761 sr_base_regnum
= tdep
->SR_REGNUM
;
3763 /* FPSCR_C is a very weird register that contains sparse bits
3764 from the FPSCR and the SR architectural registers.
3771 2-17 Bit 2-18 of FPSCR
3772 18-20 Bits 12,13,14 of SR
3776 /* Get value as an int. */
3777 fpscr_c_value
= extract_unsigned_integer (buffer
, 4);
3779 /* Build the new values. */
3780 fpscr_mask
= 0x0003fffd;
3781 sr_mask
= 0x001c0000;
3783 fpscr_value
= fpscr_c_value
& fpscr_mask
;
3784 sr_value
= (fpscr_value
& sr_mask
) >> 6;
3786 regcache_raw_read (current_regcache
, fpscr_base_regnum
, temp_buffer
);
3787 old_fpscr_value
= extract_unsigned_integer (temp_buffer
, 4);
3788 old_fpscr_value
&= 0xfffc0002;
3789 fpscr_value
|= old_fpscr_value
;
3790 store_unsigned_integer (temp_buffer
, 4, fpscr_value
);
3791 regcache_raw_write (current_regcache
, fpscr_base_regnum
, temp_buffer
);
3793 regcache_raw_read (current_regcache
, sr_base_regnum
, temp_buffer
);
3794 old_sr_value
= extract_unsigned_integer (temp_buffer
, 4);
3795 old_sr_value
&= 0xffff8fff;
3796 sr_value
|= old_sr_value
;
3797 store_unsigned_integer (temp_buffer
, 4, sr_value
);
3798 regcache_raw_write (current_regcache
, sr_base_regnum
, temp_buffer
);
3801 else if (reg_nr
== tdep
->FPUL_C_REGNUM
)
3803 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3804 regcache_raw_write (current_regcache
, base_regnum
, buffer
);
3809 sh64_register_write (struct gdbarch
*gdbarch
, int reg_nr
, char *buffer
)
3811 if (reg_nr
>= 0 && reg_nr
< gdbarch_tdep (current_gdbarch
)->DR0_REGNUM
)
3812 /* It is a regular register. */
3813 regcache_raw_write (current_regcache
, reg_nr
, buffer
);
3815 /* It is a pseudo register and we need to construct its value */
3816 sh64_pseudo_register_write (reg_nr
, buffer
);
3819 /* Floating point vector of 4 float registers. */
3821 do_fv_register_info (int fv_regnum
)
3823 int first_fp_reg_num
= fv_reg_base_num (fv_regnum
);
3824 printf_filtered ("fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
3825 fv_regnum
- gdbarch_tdep (current_gdbarch
)->FV0_REGNUM
,
3826 (int) read_register (first_fp_reg_num
),
3827 (int) read_register (first_fp_reg_num
+ 1),
3828 (int) read_register (first_fp_reg_num
+ 2),
3829 (int) read_register (first_fp_reg_num
+ 3));
3832 /* Floating point vector of 4 float registers, compact mode. */
3834 do_fv_c_register_info (int fv_regnum
)
3836 int first_fp_reg_num
= sh64_compact_reg_base_num (fv_regnum
);
3837 printf_filtered ("fv%d_c\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
3838 fv_regnum
- gdbarch_tdep (current_gdbarch
)->FV0_C_REGNUM
,
3839 (int) read_register (first_fp_reg_num
),
3840 (int) read_register (first_fp_reg_num
+ 1),
3841 (int) read_register (first_fp_reg_num
+ 2),
3842 (int) read_register (first_fp_reg_num
+ 3));
3845 /* Pairs of single regs. The DR are instead double precision
3848 do_fpp_register_info (int fpp_regnum
)
3850 int first_fp_reg_num
= fpp_reg_base_num (fpp_regnum
);
3852 printf_filtered ("fpp%d\t0x%08x\t0x%08x\n",
3853 fpp_regnum
- gdbarch_tdep (current_gdbarch
)->FPP0_REGNUM
,
3854 (int) read_register (first_fp_reg_num
),
3855 (int) read_register (first_fp_reg_num
+ 1));
3858 /* Double precision registers. */
3860 do_dr_register_info (int dr_regnum
)
3862 int first_fp_reg_num
= dr_reg_base_num (dr_regnum
);
3864 printf_filtered ("dr%d\t0x%08x%08x\n",
3865 dr_regnum
- gdbarch_tdep (current_gdbarch
)->DR0_REGNUM
,
3866 (int) read_register (first_fp_reg_num
),
3867 (int) read_register (first_fp_reg_num
+ 1));
3870 /* Double precision registers, compact mode. */
3872 do_dr_c_register_info (int dr_regnum
)
3874 int first_fp_reg_num
= sh64_compact_reg_base_num (dr_regnum
);
3876 printf_filtered ("dr%d_c\t0x%08x%08x\n",
3877 dr_regnum
- gdbarch_tdep (current_gdbarch
)->DR0_C_REGNUM
,
3878 (int) read_register (first_fp_reg_num
),
3879 (int) read_register (first_fp_reg_num
+1));
3882 /* General register in compact mode. */
3884 do_r_c_register_info (int r_c_regnum
)
3886 int regnum
= sh64_compact_reg_base_num (r_c_regnum
);
3888 printf_filtered ("r%d_c\t0x%08x\n",
3889 r_c_regnum
- gdbarch_tdep (current_gdbarch
)->R0_C_REGNUM
,
3890 /*FIXME!!!*/ (int) read_register (regnum
));
3893 /* FIXME:!! THIS SHOULD TAKE CARE OF GETTING THE RIGHT PORTION OF THE
3894 shmedia REGISTERS. */
3895 /* Control registers, compact mode. */
3897 do_cr_c_register_info (int cr_c_regnum
)
3899 switch (cr_c_regnum
)
3901 case 237: printf_filtered ("pc_c\t0x%08x\n", (int) read_register (cr_c_regnum
));
3903 case 238: printf_filtered ("gbr_c\t0x%08x\n", (int) read_register (cr_c_regnum
));
3905 case 239: printf_filtered ("mach_c\t0x%08x\n", (int) read_register (cr_c_regnum
));
3907 case 240: printf_filtered ("macl_c\t0x%08x\n", (int) read_register (cr_c_regnum
));
3909 case 241: printf_filtered ("pr_c\t0x%08x\n", (int) read_register (cr_c_regnum
));
3911 case 242: printf_filtered ("t_c\t0x%08x\n", (int) read_register (cr_c_regnum
));
3913 case 243: printf_filtered ("fpscr_c\t0x%08x\n", (int) read_register (cr_c_regnum
));
3915 case 244: printf_filtered ("fpul_c\t0x%08x\n", (int)read_register (cr_c_regnum
));
3921 sh_do_pseudo_register (int regnum
)
3923 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3925 if (regnum
< NUM_REGS
|| regnum
>= NUM_REGS
+ NUM_PSEUDO_REGS
)
3926 internal_error (__FILE__
, __LINE__
,
3927 "Invalid pseudo register number %d\n", regnum
);
3928 else if (regnum
>= tdep
->DR0_REGNUM
3929 && regnum
< tdep
->DR_LAST_REGNUM
)
3930 do_dr_register_info (regnum
);
3931 else if (regnum
>= tdep
->FV0_REGNUM
3932 && regnum
<= tdep
->FV_LAST_REGNUM
)
3933 do_fv_register_info (regnum
);
3937 sh_do_fp_register (int regnum
)
3938 { /* do values for FP (float) regs */
3940 double flt
; /* double extracted from raw hex data */
3944 /* Allocate space for the float. */
3945 raw_buffer
= (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM
));
3947 /* Get the data in raw format. */
3948 if (!frame_register_read (selected_frame
, regnum
, raw_buffer
))
3949 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
3951 /* Get the register as a number */
3952 flt
= unpack_double (builtin_type_float
, raw_buffer
, &inv
);
3954 /* Print the name and some spaces. */
3955 fputs_filtered (REGISTER_NAME (regnum
), gdb_stdout
);
3956 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum
)), gdb_stdout
);
3958 /* Print the value. */
3960 printf_filtered ("<invalid float>");
3962 printf_filtered ("%-10.9g", flt
);
3964 /* Print the fp register as hex. */
3965 printf_filtered ("\t(raw 0x");
3966 for (j
= 0; j
< REGISTER_RAW_SIZE (regnum
); j
++)
3968 register int idx
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? j
3969 : REGISTER_RAW_SIZE (regnum
) - 1 - j
;
3970 printf_filtered ("%02x", (unsigned char) raw_buffer
[idx
]);
3972 printf_filtered (")");
3973 printf_filtered ("\n");
3977 sh64_do_pseudo_register (int regnum
)
3979 /* All the sh64-compact mode registers are pseudo registers. */
3980 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3982 if (regnum
< NUM_REGS
3983 || regnum
>= NUM_REGS
+ NUM_PSEUDO_REGS_SH_MEDIA
+ NUM_PSEUDO_REGS_SH_COMPACT
)
3984 internal_error (__FILE__
, __LINE__
,
3985 "Invalid pseudo register number %d\n", regnum
);
3987 else if ((regnum
>= tdep
->DR0_REGNUM
3988 && regnum
<= tdep
->DR_LAST_REGNUM
))
3989 do_dr_register_info (regnum
);
3991 else if ((regnum
>= tdep
->DR0_C_REGNUM
3992 && regnum
<= tdep
->DR_LAST_C_REGNUM
))
3993 do_dr_c_register_info (regnum
);
3995 else if ((regnum
>= tdep
->FV0_REGNUM
3996 && regnum
<= tdep
->FV_LAST_REGNUM
))
3997 do_fv_register_info (regnum
);
3999 else if ((regnum
>= tdep
->FV0_C_REGNUM
4000 && regnum
<= tdep
->FV_LAST_C_REGNUM
))
4001 do_fv_c_register_info (regnum
);
4003 else if (regnum
>= tdep
->FPP0_REGNUM
4004 && regnum
<= tdep
->FPP_LAST_REGNUM
)
4005 do_fpp_register_info (regnum
);
4007 else if (regnum
>= tdep
->R0_C_REGNUM
4008 && regnum
<= tdep
->R_LAST_C_REGNUM
)
4009 do_r_c_register_info (regnum
); /* FIXME, this function will not print the right format */
4011 else if (regnum
>= tdep
->FP0_C_REGNUM
4012 && regnum
<= tdep
->FP_LAST_C_REGNUM
)
4013 sh_do_fp_register (regnum
); /* this should work also for pseudoregs */
4015 else if (regnum
>= tdep
->PC_C_REGNUM
4016 && regnum
<= tdep
->FPUL_C_REGNUM
)
4017 do_cr_c_register_info (regnum
);
4022 sh_do_register (int regnum
)
4024 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
4026 fputs_filtered (REGISTER_NAME (regnum
), gdb_stdout
);
4027 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum
)), gdb_stdout
);
4029 /* Get the data in raw format. */
4030 if (!frame_register_read (selected_frame
, regnum
, raw_buffer
))
4031 printf_filtered ("*value not available*\n");
4033 val_print (REGISTER_VIRTUAL_TYPE (regnum
), raw_buffer
, 0, 0,
4034 gdb_stdout
, 'x', 1, 0, Val_pretty_default
);
4035 printf_filtered ("\t");
4036 val_print (REGISTER_VIRTUAL_TYPE (regnum
), raw_buffer
, 0, 0,
4037 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
4038 printf_filtered ("\n");
4042 sh_print_register (int regnum
)
4044 if (regnum
< 0 || regnum
>= NUM_REGS
+ NUM_PSEUDO_REGS
)
4045 internal_error (__FILE__
, __LINE__
,
4046 "Invalid register number %d\n", regnum
);
4048 else if (regnum
>= 0 && regnum
< NUM_REGS
)
4050 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
4051 sh_do_fp_register (regnum
); /* FP regs */
4053 sh_do_register (regnum
); /* All other regs */
4056 else if (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
4057 do_pseudo_register (regnum
);
4061 sh_do_registers_info (int regnum
, int fpregs
)
4063 if (regnum
!= -1) /* do one specified register */
4065 if (*(REGISTER_NAME (regnum
)) == '\0')
4066 error ("Not a valid register for the current processor type");
4068 sh_print_register (regnum
);
4071 /* do all (or most) registers */
4074 while (regnum
< NUM_REGS
)
4076 /* If the register name is empty, it is undefined for this
4077 processor, so don't display anything. */
4078 if (REGISTER_NAME (regnum
) == NULL
4079 || *(REGISTER_NAME (regnum
)) == '\0')
4085 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
4089 /* true for "INFO ALL-REGISTERS" command */
4090 sh_do_fp_register (regnum
); /* FP regs */
4094 regnum
+= (gdbarch_tdep (current_gdbarch
)->FP_LAST_REGNUM
- FP0_REGNUM
); /* skip FP regs */
4098 sh_do_register (regnum
); /* All other regs */
4104 while (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
4106 do_pseudo_register (regnum
);
4113 sh_compact_do_registers_info (int regnum
, int fpregs
)
4115 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4116 if (regnum
!= -1) /* do one specified register */
4118 if (*(REGISTER_NAME (regnum
)) == '\0')
4119 error ("Not a valid register for the current processor type");
4121 if (regnum
>= 0 && regnum
< tdep
->R0_C_REGNUM
)
4122 error ("Not a valid register for the current processor mode.");
4124 sh_print_register (regnum
);
4127 /* do all compact registers */
4129 regnum
= tdep
->R0_C_REGNUM
;
4130 while (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
4132 do_pseudo_register (regnum
);
4139 sh64_do_registers_info (int regnum
, int fpregs
)
4141 if (pc_is_isa32 (selected_frame
->pc
))
4142 sh_do_registers_info (regnum
, fpregs
);
4144 sh_compact_do_registers_info (regnum
, fpregs
);
4147 #ifdef SVR4_SHARED_LIBS
4149 /* Fetch (and possibly build) an appropriate link_map_offsets structure
4150 for native i386 linux targets using the struct offsets defined in
4151 link.h (but without actual reference to that file).
4153 This makes it possible to access i386-linux shared libraries from
4154 a gdb that was not built on an i386-linux host (for cross debugging).
4157 struct link_map_offsets
*
4158 sh_linux_svr4_fetch_link_map_offsets (void)
4160 static struct link_map_offsets lmo
;
4161 static struct link_map_offsets
*lmp
= 0;
4167 lmo
.r_debug_size
= 8; /* 20 not actual size but all we need */
4169 lmo
.r_map_offset
= 4;
4172 lmo
.link_map_size
= 20; /* 552 not actual size but all we need */
4174 lmo
.l_addr_offset
= 0;
4175 lmo
.l_addr_size
= 4;
4177 lmo
.l_name_offset
= 4;
4178 lmo
.l_name_size
= 4;
4180 lmo
.l_next_offset
= 12;
4181 lmo
.l_next_size
= 4;
4183 lmo
.l_prev_offset
= 16;
4184 lmo
.l_prev_size
= 4;
4189 #endif /* SVR4_SHARED_LIBS */
4194 DSP_DSR_REGNUM
= 24,
4206 DSP_MOD_REGNUM
= 40,
4211 DSP_R0_BANK_REGNUM
= 51,
4212 DSP_R7_BANK_REGNUM
= DSP_R0_BANK_REGNUM
+ 7
4216 sh_dsp_register_sim_regno (int nr
)
4218 if (legacy_register_sim_regno (nr
) < 0)
4219 return legacy_register_sim_regno (nr
);
4220 if (nr
>= DSP_DSR_REGNUM
&& nr
< DSP_Y1_REGNUM
)
4221 return nr
- DSP_DSR_REGNUM
+ SIM_SH_DSR_REGNUM
;
4222 if (nr
== DSP_MOD_REGNUM
)
4223 return SIM_SH_MOD_REGNUM
;
4224 if (nr
== DSP_RS_REGNUM
)
4225 return SIM_SH_RS_REGNUM
;
4226 if (nr
== DSP_RE_REGNUM
)
4227 return SIM_SH_RE_REGNUM
;
4228 if (nr
>= DSP_R0_BANK_REGNUM
&& nr
<= DSP_R7_BANK_REGNUM
)
4229 return nr
- DSP_R0_BANK_REGNUM
+ SIM_SH_R0_BANK_REGNUM
;
4233 static gdbarch_init_ftype sh_gdbarch_init
;
4235 static struct gdbarch
*
4236 sh_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
4238 static LONGEST sh_call_dummy_words
[] = {0};
4239 struct gdbarch
*gdbarch
;
4240 struct gdbarch_tdep
*tdep
;
4241 gdbarch_register_name_ftype
*sh_register_name
;
4242 gdbarch_store_return_value_ftype
*sh_store_return_value
;
4243 gdbarch_register_virtual_type_ftype
*sh_register_virtual_type
;
4244 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
4246 /* Try to determine the ABI of the object we are loading. */
4248 if (info
.abfd
!= NULL
)
4250 osabi
= gdbarch_lookup_osabi (info
.abfd
);
4251 /* If we get "unknown" back, just leave it that way. */
4254 /* Find a candidate among the list of pre-declared architectures. */
4255 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
4257 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
4259 /* Make sure the ABI selection matches. */
4260 tdep
= gdbarch_tdep (arches
->gdbarch
);
4261 if (tdep
&& tdep
->osabi
== osabi
)
4262 return arches
->gdbarch
;
4265 /* None found, create a new architecture from the information
4267 tdep
= XMALLOC (struct gdbarch_tdep
);
4268 gdbarch
= gdbarch_alloc (&info
, tdep
);
4270 tdep
->osabi
= osabi
;
4272 /* Initialize the register numbers that are not common to all the
4273 variants to -1, if necessary thse will be overwritten in the case
4275 tdep
->FPUL_REGNUM
= -1;
4276 tdep
->FPSCR_REGNUM
= -1;
4277 tdep
->PR_REGNUM
= 17;
4278 tdep
->SR_REGNUM
= 22;
4279 tdep
->DSR_REGNUM
= -1;
4280 tdep
->FP_LAST_REGNUM
= -1;
4281 tdep
->A0G_REGNUM
= -1;
4282 tdep
->A0_REGNUM
= -1;
4283 tdep
->A1G_REGNUM
= -1;
4284 tdep
->A1_REGNUM
= -1;
4285 tdep
->M0_REGNUM
= -1;
4286 tdep
->M1_REGNUM
= -1;
4287 tdep
->X0_REGNUM
= -1;
4288 tdep
->X1_REGNUM
= -1;
4289 tdep
->Y0_REGNUM
= -1;
4290 tdep
->Y1_REGNUM
= -1;
4291 tdep
->MOD_REGNUM
= -1;
4292 tdep
->RS_REGNUM
= -1;
4293 tdep
->RE_REGNUM
= -1;
4294 tdep
->SSR_REGNUM
= -1;
4295 tdep
->SPC_REGNUM
= -1;
4296 tdep
->DR0_REGNUM
= -1;
4297 tdep
->DR_LAST_REGNUM
= -1;
4298 tdep
->FV0_REGNUM
= -1;
4299 tdep
->FV_LAST_REGNUM
= -1;
4300 tdep
->ARG0_REGNUM
= 4;
4301 tdep
->ARGLAST_REGNUM
= 7;
4302 tdep
->RETURN_REGNUM
= 0;
4303 tdep
->FLOAT_ARGLAST_REGNUM
= -1;
4305 tdep
->sh_abi
= SH_ABI_UNKNOWN
;
4307 set_gdbarch_fp0_regnum (gdbarch
, -1);
4308 set_gdbarch_num_pseudo_regs (gdbarch
, 0);
4309 set_gdbarch_max_register_raw_size (gdbarch
, 4);
4310 set_gdbarch_max_register_virtual_size (gdbarch
, 4);
4311 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
4312 set_gdbarch_ptr_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
4313 set_gdbarch_num_regs (gdbarch
, SH_DEFAULT_NUM_REGS
);
4314 set_gdbarch_sp_regnum (gdbarch
, 15);
4315 set_gdbarch_fp_regnum (gdbarch
, 14);
4316 set_gdbarch_pc_regnum (gdbarch
, 16);
4317 set_gdbarch_register_size (gdbarch
, 4);
4318 set_gdbarch_register_bytes (gdbarch
, SH_DEFAULT_NUM_REGS
* 4);
4319 set_gdbarch_do_registers_info (gdbarch
, sh_do_registers_info
);
4320 set_gdbarch_breakpoint_from_pc (gdbarch
, sh_breakpoint_from_pc
);
4321 set_gdbarch_frame_chain (gdbarch
, sh_frame_chain
);
4322 set_gdbarch_get_saved_register (gdbarch
, generic_get_saved_register
);
4323 set_gdbarch_init_extra_frame_info (gdbarch
, sh_init_extra_frame_info
);
4324 set_gdbarch_deprecated_extract_return_value (gdbarch
, sh_extract_return_value
);
4325 set_gdbarch_push_arguments (gdbarch
, sh_push_arguments
);
4326 set_gdbarch_store_struct_return (gdbarch
, sh_store_struct_return
);
4327 set_gdbarch_use_struct_convention (gdbarch
, sh_use_struct_convention
);
4328 set_gdbarch_deprecated_extract_struct_value_address (gdbarch
, sh_extract_struct_value_address
);
4329 set_gdbarch_pop_frame (gdbarch
, sh_pop_frame
);
4330 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_sh
);
4331 set_gdbarch_register_sim_regno (gdbarch
, legacy_register_sim_regno
);
4332 skip_prologue_hard_way
= sh_skip_prologue_hard_way
;
4333 do_pseudo_register
= sh_do_pseudo_register
;
4335 switch (info
.bfd_arch_info
->mach
)
4338 sh_register_name
= sh_sh_register_name
;
4339 sh_show_regs
= sh_generic_show_regs
;
4340 sh_store_return_value
= sh_default_store_return_value
;
4341 sh_register_virtual_type
= sh_default_register_virtual_type
;
4342 set_gdbarch_frame_init_saved_regs (gdbarch
, sh_nofp_frame_init_saved_regs
);
4343 set_gdbarch_register_raw_size (gdbarch
, sh_default_register_raw_size
);
4344 set_gdbarch_register_virtual_size (gdbarch
, sh_default_register_raw_size
);
4345 set_gdbarch_register_byte (gdbarch
, sh_default_register_byte
);
4348 sh_register_name
= sh_sh_register_name
;
4349 sh_show_regs
= sh_generic_show_regs
;
4350 sh_store_return_value
= sh_default_store_return_value
;
4351 sh_register_virtual_type
= sh_default_register_virtual_type
;
4352 set_gdbarch_frame_init_saved_regs (gdbarch
, sh_nofp_frame_init_saved_regs
);
4353 set_gdbarch_register_raw_size (gdbarch
, sh_default_register_raw_size
);
4354 set_gdbarch_register_virtual_size (gdbarch
, sh_default_register_raw_size
);
4355 set_gdbarch_register_byte (gdbarch
, sh_default_register_byte
);
4357 case bfd_mach_sh_dsp
:
4358 sh_register_name
= sh_sh_dsp_register_name
;
4359 sh_show_regs
= sh_dsp_show_regs
;
4360 sh_store_return_value
= sh_default_store_return_value
;
4361 sh_register_virtual_type
= sh_default_register_virtual_type
;
4362 set_gdbarch_frame_init_saved_regs (gdbarch
, sh_nofp_frame_init_saved_regs
);
4363 set_gdbarch_register_raw_size (gdbarch
, sh_default_register_raw_size
);
4364 set_gdbarch_register_virtual_size (gdbarch
, sh_default_register_raw_size
);
4365 set_gdbarch_register_byte (gdbarch
, sh_default_register_byte
);
4366 set_gdbarch_register_sim_regno (gdbarch
, sh_dsp_register_sim_regno
);
4367 tdep
->DSR_REGNUM
= 24;
4368 tdep
->A0G_REGNUM
= 25;
4369 tdep
->A0_REGNUM
= 26;
4370 tdep
->A1G_REGNUM
= 27;
4371 tdep
->A1_REGNUM
= 28;
4372 tdep
->M0_REGNUM
= 29;
4373 tdep
->M1_REGNUM
= 30;
4374 tdep
->X0_REGNUM
= 31;
4375 tdep
->X1_REGNUM
= 32;
4376 tdep
->Y0_REGNUM
= 33;
4377 tdep
->Y1_REGNUM
= 34;
4378 tdep
->MOD_REGNUM
= 40;
4379 tdep
->RS_REGNUM
= 43;
4380 tdep
->RE_REGNUM
= 44;
4383 sh_register_name
= sh_sh3_register_name
;
4384 sh_show_regs
= sh3_show_regs
;
4385 sh_store_return_value
= sh_default_store_return_value
;
4386 sh_register_virtual_type
= sh_default_register_virtual_type
;
4387 set_gdbarch_frame_init_saved_regs (gdbarch
, sh_nofp_frame_init_saved_regs
);
4388 set_gdbarch_register_raw_size (gdbarch
, sh_default_register_raw_size
);
4389 set_gdbarch_register_virtual_size (gdbarch
, sh_default_register_raw_size
);
4390 set_gdbarch_register_byte (gdbarch
, sh_default_register_byte
);
4391 tdep
->SSR_REGNUM
= 41;
4392 tdep
->SPC_REGNUM
= 42;
4395 sh_register_name
= sh_sh3e_register_name
;
4396 sh_show_regs
= sh3e_show_regs
;
4397 sh_store_return_value
= sh3e_sh4_store_return_value
;
4398 sh_register_virtual_type
= sh_sh3e_register_virtual_type
;
4399 set_gdbarch_frame_init_saved_regs (gdbarch
, sh_fp_frame_init_saved_regs
);
4400 set_gdbarch_register_raw_size (gdbarch
, sh_default_register_raw_size
);
4401 set_gdbarch_register_virtual_size (gdbarch
, sh_default_register_raw_size
);
4402 set_gdbarch_register_byte (gdbarch
, sh_default_register_byte
);
4403 set_gdbarch_deprecated_extract_return_value (gdbarch
, sh3e_sh4_extract_return_value
);
4404 set_gdbarch_fp0_regnum (gdbarch
, 25);
4405 tdep
->FPUL_REGNUM
= 23;
4406 tdep
->FPSCR_REGNUM
= 24;
4407 tdep
->FP_LAST_REGNUM
= 40;
4408 tdep
->SSR_REGNUM
= 41;
4409 tdep
->SPC_REGNUM
= 42;
4411 case bfd_mach_sh3_dsp
:
4412 sh_register_name
= sh_sh3_dsp_register_name
;
4413 sh_show_regs
= sh3_dsp_show_regs
;
4414 sh_store_return_value
= sh_default_store_return_value
;
4415 sh_register_virtual_type
= sh_default_register_virtual_type
;
4416 set_gdbarch_frame_init_saved_regs (gdbarch
, sh_nofp_frame_init_saved_regs
);
4417 set_gdbarch_register_raw_size (gdbarch
, sh_default_register_raw_size
);
4418 set_gdbarch_register_virtual_size (gdbarch
, sh_default_register_raw_size
);
4419 set_gdbarch_register_byte (gdbarch
, sh_default_register_byte
);
4420 tdep
->DSR_REGNUM
= 24;
4421 tdep
->A0G_REGNUM
= 25;
4422 tdep
->A0_REGNUM
= 26;
4423 tdep
->A1G_REGNUM
= 27;
4424 tdep
->A1_REGNUM
= 28;
4425 tdep
->M0_REGNUM
= 29;
4426 tdep
->M1_REGNUM
= 30;
4427 tdep
->X0_REGNUM
= 31;
4428 tdep
->X1_REGNUM
= 32;
4429 tdep
->Y0_REGNUM
= 33;
4430 tdep
->Y1_REGNUM
= 34;
4431 tdep
->MOD_REGNUM
= 40;
4432 tdep
->RS_REGNUM
= 43;
4433 tdep
->RE_REGNUM
= 44;
4434 tdep
->SSR_REGNUM
= 41;
4435 tdep
->SPC_REGNUM
= 42;
4438 sh_register_name
= sh_sh4_register_name
;
4439 sh_show_regs
= sh4_show_regs
;
4440 sh_store_return_value
= sh3e_sh4_store_return_value
;
4441 sh_register_virtual_type
= sh_sh4_register_virtual_type
;
4442 set_gdbarch_frame_init_saved_regs (gdbarch
, sh_fp_frame_init_saved_regs
);
4443 set_gdbarch_deprecated_extract_return_value (gdbarch
, sh3e_sh4_extract_return_value
);
4444 set_gdbarch_fp0_regnum (gdbarch
, 25);
4445 set_gdbarch_register_raw_size (gdbarch
, sh_sh4_register_raw_size
);
4446 set_gdbarch_register_virtual_size (gdbarch
, sh_sh4_register_raw_size
);
4447 set_gdbarch_register_byte (gdbarch
, sh_sh4_register_byte
);
4448 set_gdbarch_num_pseudo_regs (gdbarch
, 12);
4449 set_gdbarch_max_register_raw_size (gdbarch
, 4 * 4);
4450 set_gdbarch_max_register_virtual_size (gdbarch
, 4 * 4);
4451 set_gdbarch_register_read (gdbarch
, sh4_register_read
);
4452 set_gdbarch_register_write (gdbarch
, sh4_register_write
);
4453 tdep
->FPUL_REGNUM
= 23;
4454 tdep
->FPSCR_REGNUM
= 24;
4455 tdep
->FP_LAST_REGNUM
= 40;
4456 tdep
->SSR_REGNUM
= 41;
4457 tdep
->SPC_REGNUM
= 42;
4458 tdep
->DR0_REGNUM
= 59;
4459 tdep
->DR_LAST_REGNUM
= 66;
4460 tdep
->FV0_REGNUM
= 67;
4461 tdep
->FV_LAST_REGNUM
= 70;
4464 tdep
->PR_REGNUM
= 18;
4465 tdep
->SR_REGNUM
= 65;
4466 tdep
->FPSCR_REGNUM
= SIM_SH64_FPCSR_REGNUM
;
4467 tdep
->FP_LAST_REGNUM
= SIM_SH64_FR0_REGNUM
+ SIM_SH64_NR_FP_REGS
- 1;
4468 tdep
->SSR_REGNUM
= SIM_SH64_SSR_REGNUM
;
4469 tdep
->SPC_REGNUM
= SIM_SH64_SPC_REGNUM
;
4470 tdep
->TR7_REGNUM
= SIM_SH64_TR0_REGNUM
+ 7;
4471 tdep
->FPP0_REGNUM
= 173;
4472 tdep
->FPP_LAST_REGNUM
= 204;
4473 tdep
->DR0_REGNUM
= 141;
4474 tdep
->DR_LAST_REGNUM
= 172;
4475 tdep
->FV0_REGNUM
= 205;
4476 tdep
->FV_LAST_REGNUM
= 220;
4477 tdep
->R0_C_REGNUM
= 221;
4478 tdep
->R_LAST_C_REGNUM
= 236;
4479 tdep
->PC_C_REGNUM
= 237;
4480 tdep
->GBR_C_REGNUM
= 238;
4481 tdep
->MACH_C_REGNUM
= 239;
4482 tdep
->MACL_C_REGNUM
= 240;
4483 tdep
->PR_C_REGNUM
= 241;
4484 tdep
->T_C_REGNUM
= 242;
4485 tdep
->FPSCR_C_REGNUM
= 243;
4486 tdep
->FPUL_C_REGNUM
= 244;
4487 tdep
->FP0_C_REGNUM
= 245;
4488 tdep
->FP_LAST_C_REGNUM
= 260;
4489 tdep
->DR0_C_REGNUM
= 261;
4490 tdep
->DR_LAST_C_REGNUM
= 268;
4491 tdep
->FV0_C_REGNUM
= 269;
4492 tdep
->FV_LAST_C_REGNUM
= 272;
4493 tdep
->ARG0_REGNUM
= 2;
4494 tdep
->ARGLAST_REGNUM
= 9;
4495 tdep
->RETURN_REGNUM
= 2;
4496 tdep
->FLOAT_ARGLAST_REGNUM
= 11;
4498 set_gdbarch_num_pseudo_regs (gdbarch
, NUM_PSEUDO_REGS_SH_MEDIA
+ NUM_PSEUDO_REGS_SH_COMPACT
);
4499 set_gdbarch_fp0_regnum (gdbarch
, SIM_SH64_FR0_REGNUM
);
4500 set_gdbarch_pc_regnum (gdbarch
, 64);
4502 /* Determine the ABI */
4503 if (bfd_get_arch_size (info
.abfd
) == 64)
4505 /* If the ABI is the 64-bit one, it can only be sh-media. */
4506 tdep
->sh_abi
= SH_ABI_64
;
4507 set_gdbarch_ptr_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
4508 set_gdbarch_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
4512 /* If the ABI is the 32-bit one it could be either media or
4514 tdep
->sh_abi
= SH_ABI_32
;
4515 set_gdbarch_ptr_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
4516 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
4519 /* the number of real registers is the same whether we are in
4520 ISA16(compact) or ISA32(media). */
4521 set_gdbarch_num_regs (gdbarch
, SIM_SH64_NR_REGS
);
4522 set_gdbarch_register_size (gdbarch
, 8); /*????*/
4523 set_gdbarch_register_bytes (gdbarch
,
4524 ((SIM_SH64_NR_FP_REGS
+ 1) * 4)
4525 + (SIM_SH64_NR_REGS
- SIM_SH64_NR_FP_REGS
-1) * 8);
4527 sh_register_name
= sh_sh64_register_name
;
4528 sh_show_regs
= sh64_show_regs
;
4529 sh_register_virtual_type
= sh_sh64_register_virtual_type
;
4530 sh_store_return_value
= sh64_store_return_value
;
4531 skip_prologue_hard_way
= sh64_skip_prologue_hard_way
;
4532 do_pseudo_register
= sh64_do_pseudo_register
;
4533 set_gdbarch_register_raw_size (gdbarch
, sh_sh64_register_raw_size
);
4534 set_gdbarch_register_virtual_size (gdbarch
, sh_sh64_register_raw_size
);
4535 set_gdbarch_register_byte (gdbarch
, sh_sh64_register_byte
);
4536 /* This seems awfully wrong!*/
4537 /*set_gdbarch_max_register_raw_size (gdbarch, 8);*/
4538 /* should include the size of the pseudo regs. */
4539 set_gdbarch_max_register_raw_size (gdbarch
, 4 * 4);
4540 /* Or should that go in the virtual_size? */
4541 /*set_gdbarch_max_register_virtual_size (gdbarch, 8);*/
4542 set_gdbarch_max_register_virtual_size (gdbarch
, 4 * 4);
4543 set_gdbarch_register_read (gdbarch
, sh64_register_read
);
4544 set_gdbarch_register_write (gdbarch
, sh64_register_write
);
4546 set_gdbarch_do_registers_info (gdbarch
, sh64_do_registers_info
);
4547 set_gdbarch_frame_init_saved_regs (gdbarch
, sh64_nofp_frame_init_saved_regs
);
4548 set_gdbarch_breakpoint_from_pc (gdbarch
, sh_sh64_breakpoint_from_pc
);
4549 set_gdbarch_init_extra_frame_info (gdbarch
, sh64_init_extra_frame_info
);
4550 set_gdbarch_frame_chain (gdbarch
, sh64_frame_chain
);
4551 set_gdbarch_get_saved_register (gdbarch
, sh64_get_saved_register
);
4552 set_gdbarch_deprecated_extract_return_value (gdbarch
, sh64_extract_return_value
);
4553 set_gdbarch_push_arguments (gdbarch
, sh64_push_arguments
);
4554 /*set_gdbarch_store_struct_return (gdbarch, sh64_store_struct_return);*/
4555 set_gdbarch_deprecated_extract_struct_value_address (gdbarch
, sh64_extract_struct_value_address
);
4556 set_gdbarch_use_struct_convention (gdbarch
, sh64_use_struct_convention
);
4557 set_gdbarch_pop_frame (gdbarch
, sh64_pop_frame
);
4558 set_gdbarch_elf_make_msymbol_special (gdbarch
,
4559 sh64_elf_make_msymbol_special
);
4562 sh_register_name
= sh_generic_register_name
;
4563 sh_show_regs
= sh_generic_show_regs
;
4564 sh_store_return_value
= sh_default_store_return_value
;
4565 sh_register_virtual_type
= sh_default_register_virtual_type
;
4566 set_gdbarch_frame_init_saved_regs (gdbarch
, sh_nofp_frame_init_saved_regs
);
4567 set_gdbarch_register_raw_size (gdbarch
, sh_default_register_raw_size
);
4568 set_gdbarch_register_virtual_size (gdbarch
, sh_default_register_raw_size
);
4569 set_gdbarch_register_byte (gdbarch
, sh_default_register_byte
);
4573 set_gdbarch_read_pc (gdbarch
, generic_target_read_pc
);
4574 set_gdbarch_write_pc (gdbarch
, generic_target_write_pc
);
4575 set_gdbarch_read_fp (gdbarch
, generic_target_read_fp
);
4576 set_gdbarch_read_sp (gdbarch
, generic_target_read_sp
);
4577 set_gdbarch_write_sp (gdbarch
, generic_target_write_sp
);
4579 set_gdbarch_register_name (gdbarch
, sh_register_name
);
4580 set_gdbarch_register_virtual_type (gdbarch
, sh_register_virtual_type
);
4582 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
4583 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
4584 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
4585 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
4586 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
4587 set_gdbarch_long_double_bit (gdbarch
, 16 * TARGET_CHAR_BIT
);/*??should be 8?*/
4589 set_gdbarch_use_generic_dummy_frames (gdbarch
, 1);
4590 set_gdbarch_call_dummy_length (gdbarch
, 0);
4591 set_gdbarch_call_dummy_location (gdbarch
, AT_ENTRY_POINT
);
4592 set_gdbarch_call_dummy_address (gdbarch
, entry_point_address
);
4593 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch
, 1); /*???*/
4594 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0);
4595 set_gdbarch_call_dummy_start_offset (gdbarch
, 0);
4596 set_gdbarch_pc_in_call_dummy (gdbarch
, generic_pc_in_call_dummy
);
4597 set_gdbarch_call_dummy_words (gdbarch
, sh_call_dummy_words
);
4598 set_gdbarch_sizeof_call_dummy_words (gdbarch
, sizeof (sh_call_dummy_words
));
4599 set_gdbarch_call_dummy_p (gdbarch
, 1);
4600 set_gdbarch_call_dummy_stack_adjust_p (gdbarch
, 0);
4601 set_gdbarch_fix_call_dummy (gdbarch
, generic_fix_call_dummy
);
4602 set_gdbarch_coerce_float_to_double (gdbarch
,
4603 sh_coerce_float_to_double
);
4605 set_gdbarch_push_dummy_frame (gdbarch
, generic_push_dummy_frame
);
4606 set_gdbarch_push_return_address (gdbarch
, sh_push_return_address
);
4608 set_gdbarch_store_return_value (gdbarch
, sh_store_return_value
);
4609 set_gdbarch_skip_prologue (gdbarch
, sh_skip_prologue
);
4610 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
4611 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
4612 set_gdbarch_function_start_offset (gdbarch
, 0);
4614 set_gdbarch_frame_args_skip (gdbarch
, 0);
4615 set_gdbarch_frameless_function_invocation (gdbarch
, frameless_look_for_prologue
);
4616 set_gdbarch_frame_chain_valid (gdbarch
, generic_file_frame_chain_valid
);
4617 set_gdbarch_frame_saved_pc (gdbarch
, sh_frame_saved_pc
);
4618 set_gdbarch_frame_args_address (gdbarch
, default_frame_address
);
4619 set_gdbarch_frame_locals_address (gdbarch
, default_frame_address
);
4620 set_gdbarch_saved_pc_after_call (gdbarch
, sh_saved_pc_after_call
);
4621 set_gdbarch_frame_num_args (gdbarch
, frame_num_args_unknown
);
4622 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
4624 /* Hook in ABI-specific overrides, if they have been registered.
4626 FIXME: if the ABI is unknown, this is probably an embedded target,
4627 so we should not warn about this situation. */
4628 gdbarch_init_osabi (info
, gdbarch
, osabi
);
4634 sh_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
4636 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4641 fprintf_unfiltered (file
, "sh_dump_tdep: OS ABI = %s\n",
4642 gdbarch_osabi_name (tdep
->osabi
));
4646 _initialize_sh_tdep (void)
4648 struct cmd_list_element
*c
;
4650 gdbarch_register (bfd_arch_sh
, sh_gdbarch_init
, sh_dump_tdep
);
4652 add_com ("regs", class_vars
, sh_show_regs_command
, "Print all registers");