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* sh-tdep.c (sh_pseudo_register_read): Add PSEUDO_BANK_REGNUM handling.
[binutils-gdb.git] / gdb / sh-tdep.c
1 /* Target-dependent code for Renesas Super-H, for GDB.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004 Free Software Foundation, Inc.
4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
21
22 /*
23 Contributed by Steve Chamberlain
24 sac@cygnus.com
25 */
26
27 #include "defs.h"
28 #include "frame.h"
29 #include "frame-base.h"
30 #include "frame-unwind.h"
31 #include "dwarf2-frame.h"
32 #include "symtab.h"
33 #include "gdbtypes.h"
34 #include "gdbcmd.h"
35 #include "gdbcore.h"
36 #include "value.h"
37 #include "dis-asm.h"
38 #include "inferior.h"
39 #include "gdb_string.h"
40 #include "gdb_assert.h"
41 #include "arch-utils.h"
42 #include "floatformat.h"
43 #include "regcache.h"
44 #include "doublest.h"
45 #include "osabi.h"
46
47 #include "sh-tdep.h"
48
49 #include "elf-bfd.h"
50 #include "solib-svr4.h"
51
52 /* sh flags */
53 #include "elf/sh.h"
54 /* registers numbers shared with the simulator */
55 #include "gdb/sim-sh.h"
56
57 static void (*sh_show_regs) (void);
58
59 #define SH_NUM_REGS 67
60
61 struct sh_frame_cache
62 {
63 /* Base address. */
64 CORE_ADDR base;
65 LONGEST sp_offset;
66 CORE_ADDR pc;
67
68 /* Flag showing that a frame has been created in the prologue code. */
69 int uses_fp;
70
71 /* Saved registers. */
72 CORE_ADDR saved_regs[SH_NUM_REGS];
73 CORE_ADDR saved_sp;
74 };
75
76 static const char *
77 sh_sh_register_name (int reg_nr)
78 {
79 static char *register_names[] = {
80 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
81 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
82 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
83 "", "",
84 "", "", "", "", "", "", "", "",
85 "", "", "", "", "", "", "", "",
86 "", "",
87 "", "", "", "", "", "", "", "",
88 "", "", "", "", "", "", "", "",
89 "", "", "", "", "", "", "", "",
90 };
91 if (reg_nr < 0)
92 return NULL;
93 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
94 return NULL;
95 return register_names[reg_nr];
96 }
97
98 static const char *
99 sh_sh3_register_name (int reg_nr)
100 {
101 static char *register_names[] = {
102 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
103 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
104 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
105 "", "",
106 "", "", "", "", "", "", "", "",
107 "", "", "", "", "", "", "", "",
108 "ssr", "spc",
109 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
110 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
111 "", "", "", "", "", "", "", "",
112 };
113 if (reg_nr < 0)
114 return NULL;
115 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
116 return NULL;
117 return register_names[reg_nr];
118 }
119
120 static const char *
121 sh_sh3e_register_name (int reg_nr)
122 {
123 static char *register_names[] = {
124 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
125 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
126 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
127 "fpul", "fpscr",
128 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
129 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
130 "ssr", "spc",
131 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
132 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
133 "", "", "", "", "", "", "", "",
134 };
135 if (reg_nr < 0)
136 return NULL;
137 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
138 return NULL;
139 return register_names[reg_nr];
140 }
141
142 static const char *
143 sh_sh2e_register_name (int reg_nr)
144 {
145 static char *register_names[] = {
146 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
147 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
148 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
149 "fpul", "fpscr",
150 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
151 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
152 "", "",
153 "", "", "", "", "", "", "", "",
154 "", "", "", "", "", "", "", "",
155 "", "", "", "", "", "", "", "",
156 };
157 if (reg_nr < 0)
158 return NULL;
159 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
160 return NULL;
161 return register_names[reg_nr];
162 }
163
164 static const char *
165 sh_sh2a_register_name (int reg_nr)
166 {
167 static char *register_names[] = {
168 /* general registers 0-15 */
169 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
170 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
171 /* 16 - 22 */
172 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
173 /* 23, 24 */
174 "fpul", "fpscr",
175 /* floating point registers 25 - 40 */
176 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
177 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
178 /* 41, 42 */
179 "", "",
180 /* 43 - 62. Banked registers. The bank number used is determined by
181 the bank register (63). */
182 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
183 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
184 "machb", "ivnb", "prb", "gbrb", "maclb",
185 /* 63: register bank number, not a real register but used to
186 communicate the register bank currently get/set. This register
187 is hidden to the user, who manipulates it using the pseudo
188 register called "bank" (67). See below. */
189 "",
190 /* 64 - 66 */
191 "ibcr", "ibnr", "tbr",
192 /* 67: register bank number, the user visible pseudo register. */
193 "bank",
194 /* double precision (pseudo) 68 - 75 */
195 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
196 };
197 if (reg_nr < 0)
198 return NULL;
199 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
200 return NULL;
201 return register_names[reg_nr];
202 }
203
204 static const char *
205 sh_sh2a_nofpu_register_name (int reg_nr)
206 {
207 static char *register_names[] = {
208 /* general registers 0-15 */
209 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
210 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
211 /* 16 - 22 */
212 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
213 /* 23, 24 */
214 "", "",
215 /* floating point registers 25 - 40 */
216 "", "", "", "", "", "", "", "",
217 "", "", "", "", "", "", "", "",
218 /* 41, 42 */
219 "", "",
220 /* 43 - 62. Banked registers. The bank number used is determined by
221 the bank register (63). */
222 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
223 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
224 "machb", "ivnb", "prb", "gbrb", "maclb",
225 /* 63: register bank number, not a real register but used to
226 communicate the register bank currently get/set. This register
227 is hidden to the user, who manipulates it using the pseudo
228 register called "bank" (67). See below. */
229 "",
230 /* 64 - 66 */
231 "ibcr", "ibnr", "tbr",
232 /* 67: register bank number, the user visible pseudo register. */
233 "bank",
234 /* double precision (pseudo) 68 - 75 */
235 "", "", "", "", "", "", "", "",
236 };
237 if (reg_nr < 0)
238 return NULL;
239 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
240 return NULL;
241 return register_names[reg_nr];
242 }
243
244 static const char *
245 sh_sh_dsp_register_name (int reg_nr)
246 {
247 static char *register_names[] = {
248 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
249 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
250 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
251 "", "dsr",
252 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
253 "y0", "y1", "", "", "", "", "", "mod",
254 "", "",
255 "rs", "re", "", "", "", "", "", "",
256 "", "", "", "", "", "", "", "",
257 "", "", "", "", "", "", "", "",
258 };
259 if (reg_nr < 0)
260 return NULL;
261 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
262 return NULL;
263 return register_names[reg_nr];
264 }
265
266 static const char *
267 sh_sh3_dsp_register_name (int reg_nr)
268 {
269 static char *register_names[] = {
270 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
271 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
272 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
273 "", "dsr",
274 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
275 "y0", "y1", "", "", "", "", "", "mod",
276 "ssr", "spc",
277 "rs", "re", "", "", "", "", "", "",
278 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
279 "", "", "", "", "", "", "", "",
280 "", "", "", "", "", "", "", "",
281 };
282 if (reg_nr < 0)
283 return NULL;
284 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
285 return NULL;
286 return register_names[reg_nr];
287 }
288
289 static const char *
290 sh_sh4_register_name (int reg_nr)
291 {
292 static char *register_names[] = {
293 /* general registers 0-15 */
294 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
295 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
296 /* 16 - 22 */
297 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
298 /* 23, 24 */
299 "fpul", "fpscr",
300 /* floating point registers 25 - 40 */
301 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
302 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
303 /* 41, 42 */
304 "ssr", "spc",
305 /* bank 0 43 - 50 */
306 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
307 /* bank 1 51 - 58 */
308 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
309 "", "", "", "", "", "", "", "",
310 /* pseudo bank register. */
311 "",
312 /* double precision (pseudo) 59 - 66 */
313 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
314 /* vectors (pseudo) 67 - 70 */
315 "fv0", "fv4", "fv8", "fv12",
316 /* FIXME: missing XF 71 - 86 */
317 /* FIXME: missing XD 87 - 94 */
318 };
319 if (reg_nr < 0)
320 return NULL;
321 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
322 return NULL;
323 return register_names[reg_nr];
324 }
325
326 static const char *
327 sh_sh4_nofpu_register_name (int reg_nr)
328 {
329 static char *register_names[] = {
330 /* general registers 0-15 */
331 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
332 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
333 /* 16 - 22 */
334 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
335 /* 23, 24 */
336 "", "",
337 /* floating point registers 25 - 40 -- not for nofpu target */
338 "", "", "", "", "", "", "", "",
339 "", "", "", "", "", "", "", "",
340 /* 41, 42 */
341 "ssr", "spc",
342 /* bank 0 43 - 50 */
343 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
344 /* bank 1 51 - 58 */
345 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
346 "", "", "", "", "", "", "", "",
347 /* pseudo bank register. */
348 "",
349 /* double precision (pseudo) 59 - 66 -- not for nofpu target */
350 "", "", "", "", "", "", "", "",
351 /* vectors (pseudo) 67 - 70 -- not for nofpu target */
352 "", "", "", "",
353 };
354 if (reg_nr < 0)
355 return NULL;
356 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
357 return NULL;
358 return register_names[reg_nr];
359 }
360
361 static const char *
362 sh_sh4al_dsp_register_name (int reg_nr)
363 {
364 static char *register_names[] = {
365 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
366 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
367 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
368 "", "dsr",
369 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
370 "y0", "y1", "", "", "", "", "", "mod",
371 "ssr", "spc",
372 "rs", "re", "", "", "", "", "", "",
373 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
374 "", "", "", "", "", "", "", "",
375 "", "", "", "", "", "", "", "",
376 };
377 if (reg_nr < 0)
378 return NULL;
379 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
380 return NULL;
381 return register_names[reg_nr];
382 }
383
384 static const unsigned char *
385 sh_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
386 {
387 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */
388 static unsigned char breakpoint[] = { 0xc3, 0xc3 };
389
390 *lenptr = sizeof (breakpoint);
391 return breakpoint;
392 }
393
394 /* Prologue looks like
395 mov.l r14,@-r15
396 sts.l pr,@-r15
397 mov.l <regs>,@-r15
398 sub <room_for_loca_vars>,r15
399 mov r15,r14
400
401 Actually it can be more complicated than this but that's it, basically.
402 */
403
404 #define GET_SOURCE_REG(x) (((x) >> 4) & 0xf)
405 #define GET_TARGET_REG(x) (((x) >> 8) & 0xf)
406
407 /* JSR @Rm 0100mmmm00001011 */
408 #define IS_JSR(x) (((x) & 0xf0ff) == 0x400b)
409
410 /* STS.L PR,@-r15 0100111100100010
411 r15-4-->r15, PR-->(r15) */
412 #define IS_STS(x) ((x) == 0x4f22)
413
414 /* STS.L MACL,@-r15 0100111100010010
415 r15-4-->r15, MACL-->(r15) */
416 #define IS_MACL_STS(x) ((x) == 0x4f12)
417
418 /* MOV.L Rm,@-r15 00101111mmmm0110
419 r15-4-->r15, Rm-->(R15) */
420 #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
421
422 /* MOV r15,r14 0110111011110011
423 r15-->r14 */
424 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
425
426 /* ADD #imm,r15 01111111iiiiiiii
427 r15+imm-->r15 */
428 #define IS_ADD_IMM_SP(x) (((x) & 0xff00) == 0x7f00)
429
430 #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
431 #define IS_SHLL_R3(x) ((x) == 0x4300)
432
433 /* ADD r3,r15 0011111100111100
434 r15+r3-->r15 */
435 #define IS_ADD_R3SP(x) ((x) == 0x3f3c)
436
437 /* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
438 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
439 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
440 /* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to
441 make this entirely clear. */
442 /* #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b) */
443 #define IS_FPUSH(x) (((x) & 0xff0f) == 0xff0b)
444
445 /* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011 4 <= m <= 7 */
446 #define IS_MOV_ARG_TO_REG(x) \
447 (((x) & 0xf00f) == 0x6003 && \
448 ((x) & 0x00f0) >= 0x0040 && \
449 ((x) & 0x00f0) <= 0x0070)
450 /* MOV.L Rm,@Rn 0010nnnnmmmm0010 n = 14, 4 <= m <= 7 */
451 #define IS_MOV_ARG_TO_IND_R14(x) \
452 (((x) & 0xff0f) == 0x2e02 && \
453 ((x) & 0x00f0) >= 0x0040 && \
454 ((x) & 0x00f0) <= 0x0070)
455 /* MOV.L Rm,@(disp*4,Rn) 00011110mmmmdddd n = 14, 4 <= m <= 7 */
456 #define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \
457 (((x) & 0xff00) == 0x1e00 && \
458 ((x) & 0x00f0) >= 0x0040 && \
459 ((x) & 0x00f0) <= 0x0070)
460
461 /* MOV.W @(disp*2,PC),Rn 1001nnnndddddddd */
462 #define IS_MOVW_PCREL_TO_REG(x) (((x) & 0xf000) == 0x9000)
463 /* MOV.L @(disp*4,PC),Rn 1101nnnndddddddd */
464 #define IS_MOVL_PCREL_TO_REG(x) (((x) & 0xf000) == 0xd000)
465 /* MOVI20 #imm20,Rn 0000nnnniiii0000 */
466 #define IS_MOVI20(x) (((x) & 0xf00f) == 0x0000)
467 /* SUB Rn,R15 00111111nnnn1000 */
468 #define IS_SUB_REG_FROM_SP(x) (((x) & 0xff0f) == 0x3f08)
469
470 #define FPSCR_SZ (1 << 20)
471
472 /* The following instructions are used for epilogue testing. */
473 #define IS_RESTORE_FP(x) ((x) == 0x6ef6)
474 #define IS_RTS(x) ((x) == 0x000b)
475 #define IS_LDS(x) ((x) == 0x4f26)
476 #define IS_MACL_LDS(x) ((x) == 0x4f16)
477 #define IS_MOV_FP_SP(x) ((x) == 0x6fe3)
478 #define IS_ADD_REG_TO_FP(x) (((x) & 0xff0f) == 0x3e0c)
479 #define IS_ADD_IMM_FP(x) (((x) & 0xff00) == 0x7e00)
480
481 /* Disassemble an instruction. */
482 static int
483 gdb_print_insn_sh (bfd_vma memaddr, disassemble_info * info)
484 {
485 info->endian = TARGET_BYTE_ORDER;
486 return print_insn_sh (memaddr, info);
487 }
488
489 static CORE_ADDR
490 sh_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc,
491 struct sh_frame_cache *cache)
492 {
493 ULONGEST inst;
494 CORE_ADDR opc;
495 int offset;
496 int sav_offset = 0;
497 int r3_val = 0;
498 int reg, sav_reg = -1;
499
500 if (pc >= current_pc)
501 return current_pc;
502
503 cache->uses_fp = 0;
504 for (opc = pc + (2 * 28); pc < opc; pc += 2)
505 {
506 inst = read_memory_unsigned_integer (pc, 2);
507 /* See where the registers will be saved to */
508 if (IS_PUSH (inst))
509 {
510 cache->saved_regs[GET_SOURCE_REG (inst)] = cache->sp_offset;
511 cache->sp_offset += 4;
512 }
513 else if (IS_STS (inst))
514 {
515 cache->saved_regs[PR_REGNUM] = cache->sp_offset;
516 cache->sp_offset += 4;
517 }
518 else if (IS_MACL_STS (inst))
519 {
520 cache->saved_regs[MACL_REGNUM] = cache->sp_offset;
521 cache->sp_offset += 4;
522 }
523 else if (IS_MOV_R3 (inst))
524 {
525 r3_val = ((inst & 0xff) ^ 0x80) - 0x80;
526 }
527 else if (IS_SHLL_R3 (inst))
528 {
529 r3_val <<= 1;
530 }
531 else if (IS_ADD_R3SP (inst))
532 {
533 cache->sp_offset += -r3_val;
534 }
535 else if (IS_ADD_IMM_SP (inst))
536 {
537 offset = ((inst & 0xff) ^ 0x80) - 0x80;
538 cache->sp_offset -= offset;
539 }
540 else if (IS_MOVW_PCREL_TO_REG (inst))
541 {
542 if (sav_reg < 0)
543 {
544 reg = GET_TARGET_REG (inst);
545 if (reg < 14)
546 {
547 sav_reg = reg;
548 offset = (inst & 0xff) << 1;
549 sav_offset =
550 read_memory_integer ((pc + 4) + offset, 2);
551 }
552 }
553 }
554 else if (IS_MOVL_PCREL_TO_REG (inst))
555 {
556 if (sav_reg < 0)
557 {
558 reg = GET_TARGET_REG (inst);
559 if (reg < 14)
560 {
561 sav_reg = reg;
562 offset = (inst & 0xff) << 2;
563 sav_offset =
564 read_memory_integer (((pc & 0xfffffffc) + 4) + offset, 4);
565 }
566 }
567 }
568 else if (IS_MOVI20 (inst))
569 {
570 if (sav_reg < 0)
571 {
572 reg = GET_TARGET_REG (inst);
573 if (reg < 14)
574 {
575 sav_reg = reg;
576 sav_offset = GET_SOURCE_REG (inst) << 16;
577 /* MOVI20 is a 32 bit instruction! */
578 pc += 2;
579 sav_offset |= read_memory_unsigned_integer (pc, 2);
580 /* Now sav_offset contains an unsigned 20 bit value.
581 It must still get sign extended. */
582 if (sav_offset & 0x00080000)
583 sav_offset |= 0xfff00000;
584 }
585 }
586 }
587 else if (IS_SUB_REG_FROM_SP (inst))
588 {
589 reg = GET_SOURCE_REG (inst);
590 if (sav_reg > 0 && reg == sav_reg)
591 {
592 sav_reg = -1;
593 }
594 cache->sp_offset += sav_offset;
595 }
596 else if (IS_FPUSH (inst))
597 {
598 if (read_register (FPSCR_REGNUM) & FPSCR_SZ)
599 {
600 cache->sp_offset += 8;
601 }
602 else
603 {
604 cache->sp_offset += 4;
605 }
606 }
607 else if (IS_MOV_SP_FP (inst))
608 {
609 cache->uses_fp = 1;
610 /* At this point, only allow argument register moves to other
611 registers or argument register moves to @(X,fp) which are
612 moving the register arguments onto the stack area allocated
613 by a former add somenumber to SP call. Don't allow moving
614 to an fp indirect address above fp + cache->sp_offset. */
615 pc += 2;
616 for (opc = pc + 12; pc < opc; pc += 2)
617 {
618 inst = read_memory_integer (pc, 2);
619 if (IS_MOV_ARG_TO_IND_R14 (inst))
620 {
621 reg = GET_SOURCE_REG (inst);
622 if (cache->sp_offset > 0)
623 cache->saved_regs[reg] = cache->sp_offset;
624 }
625 else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst))
626 {
627 reg = GET_SOURCE_REG (inst);
628 offset = (inst & 0xf) * 4;
629 if (cache->sp_offset > offset)
630 cache->saved_regs[reg] = cache->sp_offset - offset;
631 }
632 else if (IS_MOV_ARG_TO_REG (inst))
633 continue;
634 else
635 break;
636 }
637 break;
638 }
639 else if (IS_JSR (inst))
640 {
641 /* We have found a jsr that has been scheduled into the prologue.
642 If we continue the scan and return a pc someplace after this,
643 then setting a breakpoint on this function will cause it to
644 appear to be called after the function it is calling via the
645 jsr, which will be very confusing. Most likely the next
646 instruction is going to be IS_MOV_SP_FP in the delay slot. If
647 so, note that before returning the current pc. */
648 inst = read_memory_integer (pc + 2, 2);
649 if (IS_MOV_SP_FP (inst))
650 cache->uses_fp = 1;
651 break;
652 }
653 #if 0 /* This used to just stop when it found an instruction that
654 was not considered part of the prologue. Now, we just
655 keep going looking for likely instructions. */
656 else
657 break;
658 #endif
659 }
660
661 return pc;
662 }
663
664 /* Skip any prologue before the guts of a function */
665
666 /* Skip the prologue using the debug information. If this fails we'll
667 fall back on the 'guess' method below. */
668 static CORE_ADDR
669 after_prologue (CORE_ADDR pc)
670 {
671 struct symtab_and_line sal;
672 CORE_ADDR func_addr, func_end;
673
674 /* If we can not find the symbol in the partial symbol table, then
675 there is no hope we can determine the function's start address
676 with this code. */
677 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
678 return 0;
679
680 /* Get the line associated with FUNC_ADDR. */
681 sal = find_pc_line (func_addr, 0);
682
683 /* There are only two cases to consider. First, the end of the source line
684 is within the function bounds. In that case we return the end of the
685 source line. Second is the end of the source line extends beyond the
686 bounds of the current function. We need to use the slow code to
687 examine instructions in that case. */
688 if (sal.end < func_end)
689 return sal.end;
690 else
691 return 0;
692 }
693
694 static CORE_ADDR
695 sh_skip_prologue (CORE_ADDR start_pc)
696 {
697 CORE_ADDR pc;
698 struct sh_frame_cache cache;
699
700 /* See if we can determine the end of the prologue via the symbol table.
701 If so, then return either PC, or the PC after the prologue, whichever
702 is greater. */
703 pc = after_prologue (start_pc);
704
705 /* If after_prologue returned a useful address, then use it. Else
706 fall back on the instruction skipping code. */
707 if (pc)
708 return max (pc, start_pc);
709
710 cache.sp_offset = -4;
711 pc = sh_analyze_prologue (start_pc, (CORE_ADDR) -1, &cache);
712 if (!cache.uses_fp)
713 return start_pc;
714
715 return pc;
716 }
717
718 /* The ABI says:
719
720 Aggregate types not bigger than 8 bytes that have the same size and
721 alignment as one of the integer scalar types are returned in the
722 same registers as the integer type they match.
723
724 For example, a 2-byte aligned structure with size 2 bytes has the
725 same size and alignment as a short int, and will be returned in R0.
726 A 4-byte aligned structure with size 8 bytes has the same size and
727 alignment as a long long int, and will be returned in R0 and R1.
728
729 When an aggregate type is returned in R0 and R1, R0 contains the
730 first four bytes of the aggregate, and R1 contains the
731 remainder. If the size of the aggregate type is not a multiple of 4
732 bytes, the aggregate is tail-padded up to a multiple of 4
733 bytes. The value of the padding is undefined. For little-endian
734 targets the padding will appear at the most significant end of the
735 last element, for big-endian targets the padding appears at the
736 least significant end of the last element.
737
738 All other aggregate types are returned by address. The caller
739 function passes the address of an area large enough to hold the
740 aggregate value in R2. The called function stores the result in
741 this location.
742
743 To reiterate, structs smaller than 8 bytes could also be returned
744 in memory, if they don't pass the "same size and alignment as an
745 integer type" rule.
746
747 For example, in
748
749 struct s { char c[3]; } wibble;
750 struct s foo(void) { return wibble; }
751
752 the return value from foo() will be in memory, not
753 in R0, because there is no 3-byte integer type.
754
755 Similarly, in
756
757 struct s { char c[2]; } wibble;
758 struct s foo(void) { return wibble; }
759
760 because a struct containing two chars has alignment 1, that matches
761 type char, but size 2, that matches type short. There's no integer
762 type that has alignment 1 and size 2, so the struct is returned in
763 memory.
764
765 */
766
767 static int
768 sh_use_struct_convention (int gcc_p, struct type *type)
769 {
770 int len = TYPE_LENGTH (type);
771 int nelem = TYPE_NFIELDS (type);
772
773 /* Non-power of 2 length types and types bigger than 8 bytes (which don't
774 fit in two registers anyway) use struct convention. */
775 if (len != 1 && len != 2 && len != 4 && len != 8)
776 return 1;
777
778 /* Scalar types and aggregate types with exactly one field are aligned
779 by definition. They are returned in registers. */
780 if (nelem <= 1)
781 return 0;
782
783 /* If the first field in the aggregate has the same length as the entire
784 aggregate type, the type is returned in registers. */
785 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == len)
786 return 0;
787
788 /* If the size of the aggregate is 8 bytes and the first field is
789 of size 4 bytes its alignment is equal to long long's alignment,
790 so it's returned in registers. */
791 if (len == 8 && TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == 4)
792 return 0;
793
794 /* Otherwise use struct convention. */
795 return 1;
796 }
797
798 /* Extract from an array REGBUF containing the (raw) register state
799 the address in which a function should return its structure value,
800 as a CORE_ADDR (or an expression that can be used as one). */
801 static CORE_ADDR
802 sh_extract_struct_value_address (struct regcache *regcache)
803 {
804 ULONGEST addr;
805
806 regcache_cooked_read_unsigned (regcache, STRUCT_RETURN_REGNUM, &addr);
807 return addr;
808 }
809
810 static CORE_ADDR
811 sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
812 {
813 return sp & ~3;
814 }
815
816 /* Function: push_dummy_call (formerly push_arguments)
817 Setup the function arguments for calling a function in the inferior.
818
819 On the Renesas SH architecture, there are four registers (R4 to R7)
820 which are dedicated for passing function arguments. Up to the first
821 four arguments (depending on size) may go into these registers.
822 The rest go on the stack.
823
824 MVS: Except on SH variants that have floating point registers.
825 In that case, float and double arguments are passed in the same
826 manner, but using FP registers instead of GP registers.
827
828 Arguments that are smaller than 4 bytes will still take up a whole
829 register or a whole 32-bit word on the stack, and will be
830 right-justified in the register or the stack word. This includes
831 chars, shorts, and small aggregate types.
832
833 Arguments that are larger than 4 bytes may be split between two or
834 more registers. If there are not enough registers free, an argument
835 may be passed partly in a register (or registers), and partly on the
836 stack. This includes doubles, long longs, and larger aggregates.
837 As far as I know, there is no upper limit to the size of aggregates
838 that will be passed in this way; in other words, the convention of
839 passing a pointer to a large aggregate instead of a copy is not used.
840
841 MVS: The above appears to be true for the SH variants that do not
842 have an FPU, however those that have an FPU appear to copy the
843 aggregate argument onto the stack (and not place it in registers)
844 if it is larger than 16 bytes (four GP registers).
845
846 An exceptional case exists for struct arguments (and possibly other
847 aggregates such as arrays) if the size is larger than 4 bytes but
848 not a multiple of 4 bytes. In this case the argument is never split
849 between the registers and the stack, but instead is copied in its
850 entirety onto the stack, AND also copied into as many registers as
851 there is room for. In other words, space in registers permitting,
852 two copies of the same argument are passed in. As far as I can tell,
853 only the one on the stack is used, although that may be a function
854 of the level of compiler optimization. I suspect this is a compiler
855 bug. Arguments of these odd sizes are left-justified within the
856 word (as opposed to arguments smaller than 4 bytes, which are
857 right-justified).
858
859 If the function is to return an aggregate type such as a struct, it
860 is either returned in the normal return value register R0 (if its
861 size is no greater than one byte), or else the caller must allocate
862 space into which the callee will copy the return value (if the size
863 is greater than one byte). In this case, a pointer to the return
864 value location is passed into the callee in register R2, which does
865 not displace any of the other arguments passed in via registers R4
866 to R7. */
867
868 /* Helper function to justify value in register according to endianess. */
869 static char *
870 sh_justify_value_in_reg (struct value *val, int len)
871 {
872 static char valbuf[4];
873
874 memset (valbuf, 0, sizeof (valbuf));
875 if (len < 4)
876 {
877 /* value gets right-justified in the register or stack word */
878 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
879 memcpy (valbuf + (4 - len), (char *) VALUE_CONTENTS (val), len);
880 else
881 memcpy (valbuf, (char *) VALUE_CONTENTS (val), len);
882 return valbuf;
883 }
884 return (char *) VALUE_CONTENTS (val);
885 }
886
887 /* Helper function to eval number of bytes to allocate on stack. */
888 static CORE_ADDR
889 sh_stack_allocsize (int nargs, struct value **args)
890 {
891 int stack_alloc = 0;
892 while (nargs-- > 0)
893 stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[nargs])) + 3) & ~3);
894 return stack_alloc;
895 }
896
897 /* Helper functions for getting the float arguments right. Registers usage
898 depends on the ABI and the endianess. The comments should enlighten how
899 it's intended to work. */
900
901 /* This array stores which of the float arg registers are already in use. */
902 static int flt_argreg_array[FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM + 1];
903
904 /* This function just resets the above array to "no reg used so far". */
905 static void
906 sh_init_flt_argreg (void)
907 {
908 memset (flt_argreg_array, 0, sizeof flt_argreg_array);
909 }
910
911 /* This function returns the next register to use for float arg passing.
912 It returns either a valid value between FLOAT_ARG0_REGNUM and
913 FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns
914 FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available.
915
916 Note that register number 0 in flt_argreg_array corresponds with the
917 real float register fr4. In contrast to FLOAT_ARG0_REGNUM (value is
918 29) the parity of the register number is preserved, which is important
919 for the double register passing test (see the "argreg & 1" test below). */
920 static int
921 sh_next_flt_argreg (int len)
922 {
923 int argreg;
924
925 /* First search for the next free register. */
926 for (argreg = 0; argreg <= FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM;
927 ++argreg)
928 if (!flt_argreg_array[argreg])
929 break;
930
931 /* No register left? */
932 if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
933 return FLOAT_ARGLAST_REGNUM + 1;
934
935 if (len == 8)
936 {
937 /* Doubles are always starting in a even register number. */
938 if (argreg & 1)
939 {
940 flt_argreg_array[argreg] = 1;
941
942 ++argreg;
943
944 /* No register left? */
945 if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
946 return FLOAT_ARGLAST_REGNUM + 1;
947 }
948 /* Also mark the next register as used. */
949 flt_argreg_array[argreg + 1] = 1;
950 }
951 else if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
952 {
953 /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */
954 if (!flt_argreg_array[argreg + 1])
955 ++argreg;
956 }
957 flt_argreg_array[argreg] = 1;
958 return FLOAT_ARG0_REGNUM + argreg;
959 }
960
961 /* Helper function which figures out, if a type is treated like a float type.
962
963 The FPU ABIs have a special way how to treat types as float types.
964 Structures with exactly one member, which is of type float or double, are
965 treated exactly as the base types float or double:
966
967 struct sf {
968 float f;
969 };
970
971 struct sd {
972 double d;
973 };
974
975 are handled the same way as just
976
977 float f;
978
979 double d;
980
981 As a result, arguments of these struct types are pushed into floating point
982 registers exactly as floats or doubles, using the same decision algorithm.
983
984 The same is valid if these types are used as function return types. The
985 above structs are returned in fr0 resp. fr0,fr1 instead of in r0, r0,r1
986 or even using struct convention as it is for other structs. */
987
988 static int
989 sh_treat_as_flt_p (struct type *type)
990 {
991 int len = TYPE_LENGTH (type);
992
993 /* Ordinary float types are obviously treated as float. */
994 if (TYPE_CODE (type) == TYPE_CODE_FLT)
995 return 1;
996 /* Otherwise non-struct types are not treated as float. */
997 if (TYPE_CODE (type) != TYPE_CODE_STRUCT)
998 return 0;
999 /* Otherwise structs with more than one memeber are not treated as float. */
1000 if (TYPE_NFIELDS (type) != 1)
1001 return 0;
1002 /* Otherwise if the type of that member is float, the whole type is
1003 treated as float. */
1004 if (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) == TYPE_CODE_FLT)
1005 return 1;
1006 /* Otherwise it's not treated as float. */
1007 return 0;
1008 }
1009
1010 static CORE_ADDR
1011 sh_push_dummy_call_fpu (struct gdbarch *gdbarch,
1012 struct value *function,
1013 struct regcache *regcache,
1014 CORE_ADDR bp_addr, int nargs,
1015 struct value **args,
1016 CORE_ADDR sp, int struct_return,
1017 CORE_ADDR struct_addr)
1018 {
1019 int stack_offset = 0;
1020 int argreg = ARG0_REGNUM;
1021 int flt_argreg = 0;
1022 int argnum;
1023 struct type *type;
1024 CORE_ADDR regval;
1025 char *val;
1026 int len, reg_size = 0;
1027 int pass_on_stack = 0;
1028 int treat_as_flt;
1029
1030 /* first force sp to a 4-byte alignment */
1031 sp = sh_frame_align (gdbarch, sp);
1032
1033 if (struct_return)
1034 regcache_cooked_write_unsigned (regcache,
1035 STRUCT_RETURN_REGNUM, struct_addr);
1036
1037 /* make room on stack for args */
1038 sp -= sh_stack_allocsize (nargs, args);
1039
1040 /* Initialize float argument mechanism. */
1041 sh_init_flt_argreg ();
1042
1043 /* Now load as many as possible of the first arguments into
1044 registers, and push the rest onto the stack. There are 16 bytes
1045 in four registers available. Loop thru args from first to last. */
1046 for (argnum = 0; argnum < nargs; argnum++)
1047 {
1048 type = VALUE_TYPE (args[argnum]);
1049 len = TYPE_LENGTH (type);
1050 val = sh_justify_value_in_reg (args[argnum], len);
1051
1052 /* Some decisions have to be made how various types are handled.
1053 This also differs in different ABIs. */
1054 pass_on_stack = 0;
1055
1056 /* Find out the next register to use for a floating point value. */
1057 treat_as_flt = sh_treat_as_flt_p (type);
1058 if (treat_as_flt)
1059 flt_argreg = sh_next_flt_argreg (len);
1060 /* In contrast to non-FPU CPUs, arguments are never split between
1061 registers and stack. If an argument doesn't fit in the remaining
1062 registers it's always pushed entirely on the stack. */
1063 else if (len > ((ARGLAST_REGNUM - argreg + 1) * 4))
1064 pass_on_stack = 1;
1065
1066 while (len > 0)
1067 {
1068 if ((treat_as_flt && flt_argreg > FLOAT_ARGLAST_REGNUM)
1069 || (!treat_as_flt && (argreg > ARGLAST_REGNUM
1070 || pass_on_stack)))
1071 {
1072 /* The data goes entirely on the stack, 4-byte aligned. */
1073 reg_size = (len + 3) & ~3;
1074 write_memory (sp + stack_offset, val, reg_size);
1075 stack_offset += reg_size;
1076 }
1077 else if (treat_as_flt && flt_argreg <= FLOAT_ARGLAST_REGNUM)
1078 {
1079 /* Argument goes in a float argument register. */
1080 reg_size = register_size (gdbarch, flt_argreg);
1081 regval = extract_unsigned_integer (val, reg_size);
1082 /* In little endian mode, float types taking two registers
1083 (doubles on sh4, long doubles on sh2e, sh3e and sh4) must
1084 be stored swapped in the argument registers. The below
1085 code first writes the first 32 bits in the next but one
1086 register, increments the val and len values accordingly
1087 and then proceeds as normal by writing the second 32 bits
1088 into the next register. */
1089 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE
1090 && TYPE_LENGTH (type) == 2 * reg_size)
1091 {
1092 regcache_cooked_write_unsigned (regcache, flt_argreg + 1,
1093 regval);
1094 val += reg_size;
1095 len -= reg_size;
1096 regval = extract_unsigned_integer (val, reg_size);
1097 }
1098 regcache_cooked_write_unsigned (regcache, flt_argreg++, regval);
1099 }
1100 else if (!treat_as_flt && argreg <= ARGLAST_REGNUM)
1101 {
1102 /* there's room in a register */
1103 reg_size = register_size (gdbarch, argreg);
1104 regval = extract_unsigned_integer (val, reg_size);
1105 regcache_cooked_write_unsigned (regcache, argreg++, regval);
1106 }
1107 /* Store the value one register at a time or in one step on stack. */
1108 len -= reg_size;
1109 val += reg_size;
1110 }
1111 }
1112
1113 /* Store return address. */
1114 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
1115
1116 /* Update stack pointer. */
1117 regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp);
1118
1119 return sp;
1120 }
1121
1122 static CORE_ADDR
1123 sh_push_dummy_call_nofpu (struct gdbarch *gdbarch,
1124 struct value *function,
1125 struct regcache *regcache,
1126 CORE_ADDR bp_addr,
1127 int nargs, struct value **args,
1128 CORE_ADDR sp, int struct_return,
1129 CORE_ADDR struct_addr)
1130 {
1131 int stack_offset = 0;
1132 int argreg = ARG0_REGNUM;
1133 int argnum;
1134 struct type *type;
1135 CORE_ADDR regval;
1136 char *val;
1137 int len, reg_size;
1138
1139 /* first force sp to a 4-byte alignment */
1140 sp = sh_frame_align (gdbarch, sp);
1141
1142 if (struct_return)
1143 regcache_cooked_write_unsigned (regcache,
1144 STRUCT_RETURN_REGNUM, struct_addr);
1145
1146 /* make room on stack for args */
1147 sp -= sh_stack_allocsize (nargs, args);
1148
1149 /* Now load as many as possible of the first arguments into
1150 registers, and push the rest onto the stack. There are 16 bytes
1151 in four registers available. Loop thru args from first to last. */
1152 for (argnum = 0; argnum < nargs; argnum++)
1153 {
1154 type = VALUE_TYPE (args[argnum]);
1155 len = TYPE_LENGTH (type);
1156 val = sh_justify_value_in_reg (args[argnum], len);
1157
1158 while (len > 0)
1159 {
1160 if (argreg > ARGLAST_REGNUM)
1161 {
1162 /* The remainder of the data goes entirely on the stack,
1163 4-byte aligned. */
1164 reg_size = (len + 3) & ~3;
1165 write_memory (sp + stack_offset, val, reg_size);
1166 stack_offset += reg_size;
1167 }
1168 else if (argreg <= ARGLAST_REGNUM)
1169 {
1170 /* there's room in a register */
1171 reg_size = register_size (gdbarch, argreg);
1172 regval = extract_unsigned_integer (val, reg_size);
1173 regcache_cooked_write_unsigned (regcache, argreg++, regval);
1174 }
1175 /* Store the value reg_size bytes at a time. This means that things
1176 larger than reg_size bytes may go partly in registers and partly
1177 on the stack. */
1178 len -= reg_size;
1179 val += reg_size;
1180 }
1181 }
1182
1183 /* Store return address. */
1184 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
1185
1186 /* Update stack pointer. */
1187 regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp);
1188
1189 return sp;
1190 }
1191
1192 /* Find a function's return value in the appropriate registers (in
1193 regbuf), and copy it into valbuf. Extract from an array REGBUF
1194 containing the (raw) register state a function return value of type
1195 TYPE, and copy that, in virtual format, into VALBUF. */
1196 static void
1197 sh_default_extract_return_value (struct type *type, struct regcache *regcache,
1198 void *valbuf)
1199 {
1200 int len = TYPE_LENGTH (type);
1201 int return_register = R0_REGNUM;
1202 int offset;
1203
1204 if (len <= 4)
1205 {
1206 ULONGEST c;
1207
1208 regcache_cooked_read_unsigned (regcache, R0_REGNUM, &c);
1209 store_unsigned_integer (valbuf, len, c);
1210 }
1211 else if (len == 8)
1212 {
1213 int i, regnum = R0_REGNUM;
1214 for (i = 0; i < len; i += 4)
1215 regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
1216 }
1217 else
1218 error ("bad size for return value");
1219 }
1220
1221 static void
1222 sh3e_sh4_extract_return_value (struct type *type, struct regcache *regcache,
1223 void *valbuf)
1224 {
1225 if (sh_treat_as_flt_p (type))
1226 {
1227 int len = TYPE_LENGTH (type);
1228 int i, regnum = FP0_REGNUM;
1229 for (i = 0; i < len; i += 4)
1230 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
1231 regcache_raw_read (regcache, regnum++, (char *) valbuf + len - 4 - i);
1232 else
1233 regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
1234 }
1235 else
1236 sh_default_extract_return_value (type, regcache, valbuf);
1237 }
1238
1239 /* Write into appropriate registers a function return value
1240 of type TYPE, given in virtual format.
1241 If the architecture is sh4 or sh3e, store a function's return value
1242 in the R0 general register or in the FP0 floating point register,
1243 depending on the type of the return value. In all the other cases
1244 the result is stored in r0, left-justified. */
1245 static void
1246 sh_default_store_return_value (struct type *type, struct regcache *regcache,
1247 const void *valbuf)
1248 {
1249 ULONGEST val;
1250 int len = TYPE_LENGTH (type);
1251
1252 if (len <= 4)
1253 {
1254 val = extract_unsigned_integer (valbuf, len);
1255 regcache_cooked_write_unsigned (regcache, R0_REGNUM, val);
1256 }
1257 else
1258 {
1259 int i, regnum = R0_REGNUM;
1260 for (i = 0; i < len; i += 4)
1261 regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
1262 }
1263 }
1264
1265 static void
1266 sh3e_sh4_store_return_value (struct type *type, struct regcache *regcache,
1267 const void *valbuf)
1268 {
1269 if (sh_treat_as_flt_p (type))
1270 {
1271 int len = TYPE_LENGTH (type);
1272 int i, regnum = FP0_REGNUM;
1273 for (i = 0; i < len; i += 4)
1274 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
1275 regcache_raw_write (regcache, regnum++,
1276 (char *) valbuf + len - 4 - i);
1277 else
1278 regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
1279 }
1280 else
1281 sh_default_store_return_value (type, regcache, valbuf);
1282 }
1283
1284 /* Print the registers in a form similar to the E7000 */
1285
1286 static void
1287 sh_generic_show_regs (void)
1288 {
1289 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1290 paddr (read_register (PC_REGNUM)),
1291 (long) read_register (SR_REGNUM),
1292 (long) read_register (PR_REGNUM),
1293 (long) read_register (MACH_REGNUM),
1294 (long) read_register (MACL_REGNUM));
1295
1296 printf_filtered ("GBR=%08lx VBR=%08lx",
1297 (long) read_register (GBR_REGNUM),
1298 (long) read_register (VBR_REGNUM));
1299
1300 printf_filtered
1301 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1302 (long) read_register (0), (long) read_register (1),
1303 (long) read_register (2), (long) read_register (3),
1304 (long) read_register (4), (long) read_register (5),
1305 (long) read_register (6), (long) read_register (7));
1306 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1307 (long) read_register (8), (long) read_register (9),
1308 (long) read_register (10), (long) read_register (11),
1309 (long) read_register (12), (long) read_register (13),
1310 (long) read_register (14), (long) read_register (15));
1311 }
1312
1313 static void
1314 sh3_show_regs (void)
1315 {
1316 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1317 paddr (read_register (PC_REGNUM)),
1318 (long) read_register (SR_REGNUM),
1319 (long) read_register (PR_REGNUM),
1320 (long) read_register (MACH_REGNUM),
1321 (long) read_register (MACL_REGNUM));
1322
1323 printf_filtered ("GBR=%08lx VBR=%08lx",
1324 (long) read_register (GBR_REGNUM),
1325 (long) read_register (VBR_REGNUM));
1326 printf_filtered (" SSR=%08lx SPC=%08lx",
1327 (long) read_register (SSR_REGNUM),
1328 (long) read_register (SPC_REGNUM));
1329
1330 printf_filtered
1331 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1332 (long) read_register (0), (long) read_register (1),
1333 (long) read_register (2), (long) read_register (3),
1334 (long) read_register (4), (long) read_register (5),
1335 (long) read_register (6), (long) read_register (7));
1336 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1337 (long) read_register (8), (long) read_register (9),
1338 (long) read_register (10), (long) read_register (11),
1339 (long) read_register (12), (long) read_register (13),
1340 (long) read_register (14), (long) read_register (15));
1341 }
1342
1343
1344 static void
1345 sh2e_show_regs (void)
1346 {
1347 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1348 paddr (read_register (PC_REGNUM)),
1349 (long) read_register (SR_REGNUM),
1350 (long) read_register (PR_REGNUM),
1351 (long) read_register (MACH_REGNUM),
1352 (long) read_register (MACL_REGNUM));
1353
1354 printf_filtered ("GBR=%08lx VBR=%08lx",
1355 (long) read_register (GBR_REGNUM),
1356 (long) read_register (VBR_REGNUM));
1357 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1358 (long) read_register (FPUL_REGNUM),
1359 (long) read_register (FPSCR_REGNUM));
1360
1361 printf_filtered
1362 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1363 (long) read_register (0), (long) read_register (1),
1364 (long) read_register (2), (long) read_register (3),
1365 (long) read_register (4), (long) read_register (5),
1366 (long) read_register (6), (long) read_register (7));
1367 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1368 (long) read_register (8), (long) read_register (9),
1369 (long) read_register (10), (long) read_register (11),
1370 (long) read_register (12), (long) read_register (13),
1371 (long) read_register (14), (long) read_register (15));
1372
1373 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 0), (long) read_register (FP0_REGNUM + 1), (long) read_register (FP0_REGNUM + 2), (long) read_register (FP0_REGNUM + 3), (long) read_register (FP0_REGNUM + 4), (long) read_register (FP0_REGNUM + 5), (long) read_register (FP0_REGNUM + 6), (long) read_register (FP0_REGNUM + 7));
1374 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 8), (long) read_register (FP0_REGNUM + 9), (long) read_register (FP0_REGNUM + 10), (long) read_register (FP0_REGNUM + 11), (long) read_register (FP0_REGNUM + 12), (long) read_register (FP0_REGNUM + 13), (long) read_register (FP0_REGNUM + 14), (long) read_register (FP0_REGNUM + 15));
1375 }
1376
1377 static void
1378 sh2a_show_regs (void)
1379 {
1380 int pr = read_register (FPSCR_REGNUM) & 0x80000;
1381 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1382 paddr (read_register (PC_REGNUM)),
1383 (long) read_register (SR_REGNUM),
1384 (long) read_register (PR_REGNUM),
1385 (long) read_register (MACH_REGNUM),
1386 (long) read_register (MACL_REGNUM));
1387
1388 printf_filtered ("GBR=%08lx VBR=%08lx TBR=%08lx",
1389 (long) read_register (GBR_REGNUM),
1390 (long) read_register (VBR_REGNUM),
1391 (long) read_register (TBR_REGNUM));
1392 printf_filtered (" FPUL=%08lx FPSCR=%08lx\n",
1393 (long) read_register (FPUL_REGNUM),
1394 (long) read_register (FPSCR_REGNUM));
1395
1396 printf_filtered ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1397 (long) read_register (0), (long) read_register (1),
1398 (long) read_register (2), (long) read_register (3),
1399 (long) read_register (4), (long) read_register (5),
1400 (long) read_register (6), (long) read_register (7));
1401 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1402 (long) read_register (8), (long) read_register (9),
1403 (long) read_register (10), (long) read_register (11),
1404 (long) read_register (12), (long) read_register (13),
1405 (long) read_register (14), (long) read_register (15));
1406
1407 printf_filtered ((pr
1408 ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1409 :
1410 "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1411 (long) read_register (FP0_REGNUM + 0),
1412 (long) read_register (FP0_REGNUM + 1),
1413 (long) read_register (FP0_REGNUM + 2),
1414 (long) read_register (FP0_REGNUM + 3),
1415 (long) read_register (FP0_REGNUM + 4),
1416 (long) read_register (FP0_REGNUM + 5),
1417 (long) read_register (FP0_REGNUM + 6),
1418 (long) read_register (FP0_REGNUM + 7));
1419 printf_filtered ((pr ?
1420 "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n" :
1421 "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1422 (long) read_register (FP0_REGNUM + 8),
1423 (long) read_register (FP0_REGNUM + 9),
1424 (long) read_register (FP0_REGNUM + 10),
1425 (long) read_register (FP0_REGNUM + 11),
1426 (long) read_register (FP0_REGNUM + 12),
1427 (long) read_register (FP0_REGNUM + 13),
1428 (long) read_register (FP0_REGNUM + 14),
1429 (long) read_register (FP0_REGNUM + 15));
1430 printf_filtered ("BANK=%-3d\n", (int) read_register (BANK_REGNUM));
1431 printf_filtered ("R0b - R7b %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1432 (long) read_register (R0_BANK0_REGNUM + 0),
1433 (long) read_register (R0_BANK0_REGNUM + 1),
1434 (long) read_register (R0_BANK0_REGNUM + 2),
1435 (long) read_register (R0_BANK0_REGNUM + 3),
1436 (long) read_register (R0_BANK0_REGNUM + 4),
1437 (long) read_register (R0_BANK0_REGNUM + 5),
1438 (long) read_register (R0_BANK0_REGNUM + 6),
1439 (long) read_register (R0_BANK0_REGNUM + 7));
1440 printf_filtered ("R8b - R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1441 (long) read_register (R0_BANK0_REGNUM + 8),
1442 (long) read_register (R0_BANK0_REGNUM + 9),
1443 (long) read_register (R0_BANK0_REGNUM + 10),
1444 (long) read_register (R0_BANK0_REGNUM + 11),
1445 (long) read_register (R0_BANK0_REGNUM + 12),
1446 (long) read_register (R0_BANK0_REGNUM + 13),
1447 (long) read_register (R0_BANK0_REGNUM + 14));
1448 printf_filtered ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n",
1449 (long) read_register (R0_BANK0_REGNUM + 15),
1450 (long) read_register (R0_BANK0_REGNUM + 16),
1451 (long) read_register (R0_BANK0_REGNUM + 17),
1452 (long) read_register (R0_BANK0_REGNUM + 18),
1453 (long) read_register (R0_BANK0_REGNUM + 19));
1454 }
1455
1456 static void
1457 sh2a_nofpu_show_regs (void)
1458 {
1459 int pr = read_register (FPSCR_REGNUM) & 0x80000;
1460 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1461 paddr (read_register (PC_REGNUM)),
1462 (long) read_register (SR_REGNUM),
1463 (long) read_register (PR_REGNUM),
1464 (long) read_register (MACH_REGNUM),
1465 (long) read_register (MACL_REGNUM));
1466
1467 printf_filtered ("GBR=%08lx VBR=%08lx TBR=%08lx",
1468 (long) read_register (GBR_REGNUM),
1469 (long) read_register (VBR_REGNUM),
1470 (long) read_register (TBR_REGNUM));
1471 printf_filtered (" FPUL=%08lx FPSCR=%08lx\n",
1472 (long) read_register (FPUL_REGNUM),
1473 (long) read_register (FPSCR_REGNUM));
1474
1475 printf_filtered ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1476 (long) read_register (0), (long) read_register (1),
1477 (long) read_register (2), (long) read_register (3),
1478 (long) read_register (4), (long) read_register (5),
1479 (long) read_register (6), (long) read_register (7));
1480 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1481 (long) read_register (8), (long) read_register (9),
1482 (long) read_register (10), (long) read_register (11),
1483 (long) read_register (12), (long) read_register (13),
1484 (long) read_register (14), (long) read_register (15));
1485
1486 printf_filtered ("BANK=%-3d\n", (int) read_register (BANK_REGNUM));
1487 printf_filtered ("R0b - R7b %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1488 (long) read_register (R0_BANK0_REGNUM + 0),
1489 (long) read_register (R0_BANK0_REGNUM + 1),
1490 (long) read_register (R0_BANK0_REGNUM + 2),
1491 (long) read_register (R0_BANK0_REGNUM + 3),
1492 (long) read_register (R0_BANK0_REGNUM + 4),
1493 (long) read_register (R0_BANK0_REGNUM + 5),
1494 (long) read_register (R0_BANK0_REGNUM + 6),
1495 (long) read_register (R0_BANK0_REGNUM + 7));
1496 printf_filtered ("R8b - R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1497 (long) read_register (R0_BANK0_REGNUM + 8),
1498 (long) read_register (R0_BANK0_REGNUM + 9),
1499 (long) read_register (R0_BANK0_REGNUM + 10),
1500 (long) read_register (R0_BANK0_REGNUM + 11),
1501 (long) read_register (R0_BANK0_REGNUM + 12),
1502 (long) read_register (R0_BANK0_REGNUM + 13),
1503 (long) read_register (R0_BANK0_REGNUM + 14));
1504 printf_filtered ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n",
1505 (long) read_register (R0_BANK0_REGNUM + 15),
1506 (long) read_register (R0_BANK0_REGNUM + 16),
1507 (long) read_register (R0_BANK0_REGNUM + 17),
1508 (long) read_register (R0_BANK0_REGNUM + 18),
1509 (long) read_register (R0_BANK0_REGNUM + 19));
1510 }
1511
1512 static void
1513 sh3e_show_regs (void)
1514 {
1515 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1516 paddr (read_register (PC_REGNUM)),
1517 (long) read_register (SR_REGNUM),
1518 (long) read_register (PR_REGNUM),
1519 (long) read_register (MACH_REGNUM),
1520 (long) read_register (MACL_REGNUM));
1521
1522 printf_filtered ("GBR=%08lx VBR=%08lx",
1523 (long) read_register (GBR_REGNUM),
1524 (long) read_register (VBR_REGNUM));
1525 printf_filtered (" SSR=%08lx SPC=%08lx",
1526 (long) read_register (SSR_REGNUM),
1527 (long) read_register (SPC_REGNUM));
1528 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1529 (long) read_register (FPUL_REGNUM),
1530 (long) read_register (FPSCR_REGNUM));
1531
1532 printf_filtered
1533 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1534 (long) read_register (0), (long) read_register (1),
1535 (long) read_register (2), (long) read_register (3),
1536 (long) read_register (4), (long) read_register (5),
1537 (long) read_register (6), (long) read_register (7));
1538 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1539 (long) read_register (8), (long) read_register (9),
1540 (long) read_register (10), (long) read_register (11),
1541 (long) read_register (12), (long) read_register (13),
1542 (long) read_register (14), (long) read_register (15));
1543
1544 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 0), (long) read_register (FP0_REGNUM + 1), (long) read_register (FP0_REGNUM + 2), (long) read_register (FP0_REGNUM + 3), (long) read_register (FP0_REGNUM + 4), (long) read_register (FP0_REGNUM + 5), (long) read_register (FP0_REGNUM + 6), (long) read_register (FP0_REGNUM + 7));
1545 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 8), (long) read_register (FP0_REGNUM + 9), (long) read_register (FP0_REGNUM + 10), (long) read_register (FP0_REGNUM + 11), (long) read_register (FP0_REGNUM + 12), (long) read_register (FP0_REGNUM + 13), (long) read_register (FP0_REGNUM + 14), (long) read_register (FP0_REGNUM + 15));
1546 }
1547
1548 static void
1549 sh3_dsp_show_regs (void)
1550 {
1551 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1552 paddr (read_register (PC_REGNUM)),
1553 (long) read_register (SR_REGNUM),
1554 (long) read_register (PR_REGNUM),
1555 (long) read_register (MACH_REGNUM),
1556 (long) read_register (MACL_REGNUM));
1557
1558 printf_filtered ("GBR=%08lx VBR=%08lx",
1559 (long) read_register (GBR_REGNUM),
1560 (long) read_register (VBR_REGNUM));
1561
1562 printf_filtered (" SSR=%08lx SPC=%08lx",
1563 (long) read_register (SSR_REGNUM),
1564 (long) read_register (SPC_REGNUM));
1565
1566 printf_filtered (" DSR=%08lx", (long) read_register (DSR_REGNUM));
1567
1568 printf_filtered
1569 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1570 (long) read_register (0), (long) read_register (1),
1571 (long) read_register (2), (long) read_register (3),
1572 (long) read_register (4), (long) read_register (5),
1573 (long) read_register (6), (long) read_register (7));
1574 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1575 (long) read_register (8), (long) read_register (9),
1576 (long) read_register (10), (long) read_register (11),
1577 (long) read_register (12), (long) read_register (13),
1578 (long) read_register (14), (long) read_register (15));
1579
1580 printf_filtered
1581 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1582 (long) read_register (A0G_REGNUM) & 0xff,
1583 (long) read_register (A0_REGNUM), (long) read_register (M0_REGNUM),
1584 (long) read_register (X0_REGNUM), (long) read_register (Y0_REGNUM),
1585 (long) read_register (RS_REGNUM), (long) read_register (MOD_REGNUM));
1586 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1587 (long) read_register (A1G_REGNUM) & 0xff,
1588 (long) read_register (A1_REGNUM),
1589 (long) read_register (M1_REGNUM),
1590 (long) read_register (X1_REGNUM),
1591 (long) read_register (Y1_REGNUM),
1592 (long) read_register (RE_REGNUM));
1593 }
1594
1595 static void
1596 sh4_show_regs (void)
1597 {
1598 int pr = read_register (FPSCR_REGNUM) & 0x80000;
1599 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1600 paddr (read_register (PC_REGNUM)),
1601 (long) read_register (SR_REGNUM),
1602 (long) read_register (PR_REGNUM),
1603 (long) read_register (MACH_REGNUM),
1604 (long) read_register (MACL_REGNUM));
1605
1606 printf_filtered ("GBR=%08lx VBR=%08lx",
1607 (long) read_register (GBR_REGNUM),
1608 (long) read_register (VBR_REGNUM));
1609 printf_filtered (" SSR=%08lx SPC=%08lx",
1610 (long) read_register (SSR_REGNUM),
1611 (long) read_register (SPC_REGNUM));
1612 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1613 (long) read_register (FPUL_REGNUM),
1614 (long) read_register (FPSCR_REGNUM));
1615
1616 printf_filtered
1617 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1618 (long) read_register (0), (long) read_register (1),
1619 (long) read_register (2), (long) read_register (3),
1620 (long) read_register (4), (long) read_register (5),
1621 (long) read_register (6), (long) read_register (7));
1622 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1623 (long) read_register (8), (long) read_register (9),
1624 (long) read_register (10), (long) read_register (11),
1625 (long) read_register (12), (long) read_register (13),
1626 (long) read_register (14), (long) read_register (15));
1627
1628 printf_filtered ((pr
1629 ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1630 :
1631 "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1632 (long) read_register (FP0_REGNUM + 0),
1633 (long) read_register (FP0_REGNUM + 1),
1634 (long) read_register (FP0_REGNUM + 2),
1635 (long) read_register (FP0_REGNUM + 3),
1636 (long) read_register (FP0_REGNUM + 4),
1637 (long) read_register (FP0_REGNUM + 5),
1638 (long) read_register (FP0_REGNUM + 6),
1639 (long) read_register (FP0_REGNUM + 7));
1640 printf_filtered ((pr ?
1641 "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n" :
1642 "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1643 (long) read_register (FP0_REGNUM + 8),
1644 (long) read_register (FP0_REGNUM + 9),
1645 (long) read_register (FP0_REGNUM + 10),
1646 (long) read_register (FP0_REGNUM + 11),
1647 (long) read_register (FP0_REGNUM + 12),
1648 (long) read_register (FP0_REGNUM + 13),
1649 (long) read_register (FP0_REGNUM + 14),
1650 (long) read_register (FP0_REGNUM + 15));
1651 }
1652
1653 static void
1654 sh4_nofpu_show_regs (void)
1655 {
1656 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1657 paddr (read_register (PC_REGNUM)),
1658 (long) read_register (SR_REGNUM),
1659 (long) read_register (PR_REGNUM),
1660 (long) read_register (MACH_REGNUM),
1661 (long) read_register (MACL_REGNUM));
1662
1663 printf_filtered ("GBR=%08lx VBR=%08lx",
1664 (long) read_register (GBR_REGNUM),
1665 (long) read_register (VBR_REGNUM));
1666 printf_filtered (" SSR=%08lx SPC=%08lx",
1667 (long) read_register (SSR_REGNUM),
1668 (long) read_register (SPC_REGNUM));
1669
1670 printf_filtered
1671 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1672 (long) read_register (0), (long) read_register (1),
1673 (long) read_register (2), (long) read_register (3),
1674 (long) read_register (4), (long) read_register (5),
1675 (long) read_register (6), (long) read_register (7));
1676 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1677 (long) read_register (8), (long) read_register (9),
1678 (long) read_register (10), (long) read_register (11),
1679 (long) read_register (12), (long) read_register (13),
1680 (long) read_register (14), (long) read_register (15));
1681 }
1682
1683 static void
1684 sh_dsp_show_regs (void)
1685 {
1686 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1687 paddr (read_register (PC_REGNUM)),
1688 (long) read_register (SR_REGNUM),
1689 (long) read_register (PR_REGNUM),
1690 (long) read_register (MACH_REGNUM),
1691 (long) read_register (MACL_REGNUM));
1692
1693 printf_filtered ("GBR=%08lx VBR=%08lx",
1694 (long) read_register (GBR_REGNUM),
1695 (long) read_register (VBR_REGNUM));
1696
1697 printf_filtered (" DSR=%08lx", (long) read_register (DSR_REGNUM));
1698
1699 printf_filtered
1700 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1701 (long) read_register (0), (long) read_register (1),
1702 (long) read_register (2), (long) read_register (3),
1703 (long) read_register (4), (long) read_register (5),
1704 (long) read_register (6), (long) read_register (7));
1705 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1706 (long) read_register (8), (long) read_register (9),
1707 (long) read_register (10), (long) read_register (11),
1708 (long) read_register (12), (long) read_register (13),
1709 (long) read_register (14), (long) read_register (15));
1710
1711 printf_filtered
1712 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1713 (long) read_register (A0G_REGNUM) & 0xff,
1714 (long) read_register (A0_REGNUM), (long) read_register (M0_REGNUM),
1715 (long) read_register (X0_REGNUM), (long) read_register (Y0_REGNUM),
1716 (long) read_register (RS_REGNUM), (long) read_register (MOD_REGNUM));
1717 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1718 (long) read_register (A1G_REGNUM) & 0xff,
1719 (long) read_register (A1_REGNUM),
1720 (long) read_register (M1_REGNUM),
1721 (long) read_register (X1_REGNUM),
1722 (long) read_register (Y1_REGNUM),
1723 (long) read_register (RE_REGNUM));
1724 }
1725
1726 static void
1727 sh_show_regs_command (char *args, int from_tty)
1728 {
1729 if (sh_show_regs)
1730 (*sh_show_regs) ();
1731 }
1732
1733 static struct type *
1734 sh_sh2a_register_type (struct gdbarch *gdbarch, int reg_nr)
1735 {
1736 if ((reg_nr >= FP0_REGNUM
1737 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
1738 return builtin_type_float;
1739 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
1740 return builtin_type_double;
1741 else
1742 return builtin_type_int;
1743 }
1744
1745 /* Return the GDB type object for the "standard" data type
1746 of data in register N. */
1747 static struct type *
1748 sh_sh3e_register_type (struct gdbarch *gdbarch, int reg_nr)
1749 {
1750 if ((reg_nr >= FP0_REGNUM
1751 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
1752 return builtin_type_float;
1753 else
1754 return builtin_type_int;
1755 }
1756
1757 static struct type *
1758 sh_sh4_build_float_register_type (int high)
1759 {
1760 struct type *temp;
1761
1762 temp = create_range_type (NULL, builtin_type_int, 0, high);
1763 return create_array_type (NULL, builtin_type_float, temp);
1764 }
1765
1766 static struct type *
1767 sh_sh4_register_type (struct gdbarch *gdbarch, int reg_nr)
1768 {
1769 if ((reg_nr >= FP0_REGNUM
1770 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
1771 return builtin_type_float;
1772 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
1773 return builtin_type_double;
1774 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
1775 return sh_sh4_build_float_register_type (3);
1776 else
1777 return builtin_type_int;
1778 }
1779
1780 static struct type *
1781 sh_default_register_type (struct gdbarch *gdbarch, int reg_nr)
1782 {
1783 return builtin_type_int;
1784 }
1785
1786 /* On the sh4, the DRi pseudo registers are problematic if the target
1787 is little endian. When the user writes one of those registers, for
1788 instance with 'ser var $dr0=1', we want the double to be stored
1789 like this:
1790 fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
1791 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1792
1793 This corresponds to little endian byte order & big endian word
1794 order. However if we let gdb write the register w/o conversion, it
1795 will write fr0 and fr1 this way:
1796 fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1797 fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
1798 because it will consider fr0 and fr1 as a single LE stretch of memory.
1799
1800 To achieve what we want we must force gdb to store things in
1801 floatformat_ieee_double_littlebyte_bigword (which is defined in
1802 include/floatformat.h and libiberty/floatformat.c.
1803
1804 In case the target is big endian, there is no problem, the
1805 raw bytes will look like:
1806 fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
1807 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1808
1809 The other pseudo registers (the FVs) also don't pose a problem
1810 because they are stored as 4 individual FP elements. */
1811
1812 static void
1813 sh_register_convert_to_virtual (int regnum, struct type *type,
1814 char *from, char *to)
1815 {
1816 if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
1817 {
1818 DOUBLEST val;
1819 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
1820 from, &val);
1821 store_typed_floating (to, type, val);
1822 }
1823 else
1824 error
1825 ("sh_register_convert_to_virtual called with non DR register number");
1826 }
1827
1828 static void
1829 sh_register_convert_to_raw (struct type *type, int regnum,
1830 const void *from, void *to)
1831 {
1832 if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
1833 {
1834 DOUBLEST val = extract_typed_floating (from, type);
1835 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword,
1836 &val, to);
1837 }
1838 else
1839 error ("sh_register_convert_to_raw called with non DR register number");
1840 }
1841
1842 /* For vectors of 4 floating point registers. */
1843 static int
1844 fv_reg_base_num (int fv_regnum)
1845 {
1846 int fp_regnum;
1847
1848 fp_regnum = FP0_REGNUM + (fv_regnum - FV0_REGNUM) * 4;
1849 return fp_regnum;
1850 }
1851
1852 /* For double precision floating point registers, i.e 2 fp regs.*/
1853 static int
1854 dr_reg_base_num (int dr_regnum)
1855 {
1856 int fp_regnum;
1857
1858 fp_regnum = FP0_REGNUM + (dr_regnum - DR0_REGNUM) * 2;
1859 return fp_regnum;
1860 }
1861
1862 static void
1863 sh_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
1864 int reg_nr, void *buffer)
1865 {
1866 int base_regnum, portion;
1867 char temp_buffer[MAX_REGISTER_SIZE];
1868
1869 if (reg_nr == PSEUDO_BANK_REGNUM)
1870 regcache_raw_read (regcache, BANK_REGNUM, buffer);
1871 else
1872 if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
1873 {
1874 base_regnum = dr_reg_base_num (reg_nr);
1875
1876 /* Build the value in the provided buffer. */
1877 /* Read the real regs for which this one is an alias. */
1878 for (portion = 0; portion < 2; portion++)
1879 regcache_raw_read (regcache, base_regnum + portion,
1880 (temp_buffer
1881 + register_size (gdbarch,
1882 base_regnum) * portion));
1883 /* We must pay attention to the endiannes. */
1884 sh_register_convert_to_virtual (reg_nr,
1885 gdbarch_register_type (gdbarch, reg_nr),
1886 temp_buffer, buffer);
1887 }
1888 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
1889 {
1890 base_regnum = fv_reg_base_num (reg_nr);
1891
1892 /* Read the real regs for which this one is an alias. */
1893 for (portion = 0; portion < 4; portion++)
1894 regcache_raw_read (regcache, base_regnum + portion,
1895 ((char *) buffer
1896 + register_size (gdbarch,
1897 base_regnum) * portion));
1898 }
1899 }
1900
1901 static void
1902 sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
1903 int reg_nr, const void *buffer)
1904 {
1905 int base_regnum, portion;
1906 char temp_buffer[MAX_REGISTER_SIZE];
1907
1908 if (reg_nr == PSEUDO_BANK_REGNUM)
1909 {
1910 /* When the bank register is written to, the whole register bank
1911 is switched and all values in the bank registers must be read
1912 from the target/sim again. We're just invalidating the regcache
1913 so that a re-read happens next time it's necessary. */
1914 int bregnum;
1915
1916 regcache_raw_write (regcache, BANK_REGNUM, buffer);
1917 for (bregnum = R0_BANK0_REGNUM; bregnum < MACLB_REGNUM; ++bregnum)
1918 set_register_cached (bregnum, 0);
1919 }
1920 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
1921 {
1922 base_regnum = dr_reg_base_num (reg_nr);
1923
1924 /* We must pay attention to the endiannes. */
1925 sh_register_convert_to_raw (gdbarch_register_type (gdbarch, reg_nr),
1926 reg_nr, buffer, temp_buffer);
1927
1928 /* Write the real regs for which this one is an alias. */
1929 for (portion = 0; portion < 2; portion++)
1930 regcache_raw_write (regcache, base_regnum + portion,
1931 (temp_buffer
1932 + register_size (gdbarch,
1933 base_regnum) * portion));
1934 }
1935 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
1936 {
1937 base_regnum = fv_reg_base_num (reg_nr);
1938
1939 /* Write the real regs for which this one is an alias. */
1940 for (portion = 0; portion < 4; portion++)
1941 regcache_raw_write (regcache, base_regnum + portion,
1942 ((char *) buffer
1943 + register_size (gdbarch,
1944 base_regnum) * portion));
1945 }
1946 }
1947
1948 /* Floating point vector of 4 float registers. */
1949 static void
1950 do_fv_register_info (struct gdbarch *gdbarch, struct ui_file *file,
1951 int fv_regnum)
1952 {
1953 int first_fp_reg_num = fv_reg_base_num (fv_regnum);
1954 fprintf_filtered (file, "fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
1955 fv_regnum - FV0_REGNUM,
1956 (int) read_register (first_fp_reg_num),
1957 (int) read_register (first_fp_reg_num + 1),
1958 (int) read_register (first_fp_reg_num + 2),
1959 (int) read_register (first_fp_reg_num + 3));
1960 }
1961
1962 /* Double precision registers. */
1963 static void
1964 do_dr_register_info (struct gdbarch *gdbarch, struct ui_file *file,
1965 int dr_regnum)
1966 {
1967 int first_fp_reg_num = dr_reg_base_num (dr_regnum);
1968
1969 fprintf_filtered (file, "dr%d\t0x%08x%08x\n",
1970 dr_regnum - DR0_REGNUM,
1971 (int) read_register (first_fp_reg_num),
1972 (int) read_register (first_fp_reg_num + 1));
1973 }
1974 static void
1975 do_bank_register_info (struct gdbarch *gdbarch, struct ui_file *file)
1976 {
1977 fprintf_filtered (file, "bank %d\n",
1978 (int) read_register (BANK_REGNUM));
1979 }
1980
1981 static void
1982 sh_print_pseudo_register (struct gdbarch *gdbarch, struct ui_file *file,
1983 int regnum)
1984 {
1985 if (regnum < NUM_REGS || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
1986 internal_error (__FILE__, __LINE__,
1987 "Invalid pseudo register number %d\n", regnum);
1988 else if (regnum == PSEUDO_BANK_REGNUM)
1989 do_bank_register_info (gdbarch, file);
1990 else if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
1991 do_dr_register_info (gdbarch, file, regnum);
1992 else if (regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM)
1993 do_fv_register_info (gdbarch, file, regnum);
1994 }
1995
1996 static void
1997 sh_do_fp_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
1998 { /* do values for FP (float) regs */
1999 char *raw_buffer;
2000 double flt; /* double extracted from raw hex data */
2001 int inv;
2002 int j;
2003
2004 /* Allocate space for the float. */
2005 raw_buffer = (char *) alloca (register_size (gdbarch, FP0_REGNUM));
2006
2007 /* Get the data in raw format. */
2008 if (!frame_register_read (get_selected_frame (), regnum, raw_buffer))
2009 error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum));
2010
2011 /* Get the register as a number */
2012 flt = unpack_double (builtin_type_float, raw_buffer, &inv);
2013
2014 /* Print the name and some spaces. */
2015 fputs_filtered (REGISTER_NAME (regnum), file);
2016 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file);
2017
2018 /* Print the value. */
2019 if (inv)
2020 fprintf_filtered (file, "<invalid float>");
2021 else
2022 fprintf_filtered (file, "%-10.9g", flt);
2023
2024 /* Print the fp register as hex. */
2025 fprintf_filtered (file, "\t(raw 0x");
2026 for (j = 0; j < register_size (gdbarch, regnum); j++)
2027 {
2028 int idx = (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
2029 ? j
2030 : register_size (gdbarch, regnum) - 1 - j);
2031 fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[idx]);
2032 }
2033 fprintf_filtered (file, ")");
2034 fprintf_filtered (file, "\n");
2035 }
2036
2037 static void
2038 sh_do_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
2039 {
2040 char raw_buffer[MAX_REGISTER_SIZE];
2041
2042 fputs_filtered (REGISTER_NAME (regnum), file);
2043 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file);
2044
2045 /* Get the data in raw format. */
2046 if (!frame_register_read (get_selected_frame (), regnum, raw_buffer))
2047 fprintf_filtered (file, "*value not available*\n");
2048
2049 val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0,
2050 file, 'x', 1, 0, Val_pretty_default);
2051 fprintf_filtered (file, "\t");
2052 val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0,
2053 file, 0, 1, 0, Val_pretty_default);
2054 fprintf_filtered (file, "\n");
2055 }
2056
2057 static void
2058 sh_print_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
2059 {
2060 if (regnum < 0 || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
2061 internal_error (__FILE__, __LINE__,
2062 "Invalid register number %d\n", regnum);
2063
2064 else if (regnum >= 0 && regnum < NUM_REGS)
2065 {
2066 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) ==
2067 TYPE_CODE_FLT)
2068 sh_do_fp_register (gdbarch, file, regnum); /* FP regs */
2069 else
2070 sh_do_register (gdbarch, file, regnum); /* All other regs */
2071 }
2072
2073 else if (regnum < NUM_REGS + NUM_PSEUDO_REGS)
2074 {
2075 sh_print_pseudo_register (gdbarch, file, regnum);
2076 }
2077 }
2078
2079 static void
2080 sh_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
2081 struct frame_info *frame, int regnum, int fpregs)
2082 {
2083 if (regnum != -1) /* do one specified register */
2084 {
2085 if (*(REGISTER_NAME (regnum)) == '\0')
2086 error ("Not a valid register for the current processor type");
2087
2088 sh_print_register (gdbarch, file, regnum);
2089 }
2090 else
2091 /* do all (or most) registers */
2092 {
2093 for (regnum = 0; regnum < NUM_REGS; ++regnum)
2094 {
2095 /* If the register name is empty, it is undefined for this
2096 processor, so don't display anything. */
2097 if (REGISTER_NAME (regnum) == NULL
2098 || *(REGISTER_NAME (regnum)) == '\0')
2099 continue;
2100
2101 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) ==
2102 TYPE_CODE_FLT)
2103 {
2104 /* true for "INFO ALL-REGISTERS" command */
2105 if (fpregs)
2106 sh_do_fp_register (gdbarch, file, regnum); /* FP regs */
2107 }
2108 else
2109 sh_do_register (gdbarch, file, regnum); /* All other regs */
2110 }
2111
2112 if (regnum == PSEUDO_BANK_REGNUM
2113 && REGISTER_NAME (regnum)
2114 && *REGISTER_NAME (regnum))
2115 sh_print_pseudo_register (gdbarch, file, regnum++);
2116
2117 if (fpregs)
2118 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
2119 {
2120 sh_print_pseudo_register (gdbarch, file, regnum);
2121 regnum++;
2122 }
2123 }
2124 }
2125
2126 /* Fetch (and possibly build) an appropriate link_map_offsets structure
2127 for native i386 linux targets using the struct offsets defined in
2128 link.h (but without actual reference to that file).
2129
2130 This makes it possible to access i386-linux shared libraries from
2131 a gdb that was not built on an i386-linux host (for cross debugging).
2132 */
2133
2134 struct link_map_offsets *
2135 sh_linux_svr4_fetch_link_map_offsets (void)
2136 {
2137 static struct link_map_offsets lmo;
2138 static struct link_map_offsets *lmp = 0;
2139
2140 if (lmp == 0)
2141 {
2142 lmp = &lmo;
2143
2144 lmo.r_debug_size = 8; /* 20 not actual size but all we need */
2145
2146 lmo.r_map_offset = 4;
2147 lmo.r_map_size = 4;
2148
2149 lmo.link_map_size = 20; /* 552 not actual size but all we need */
2150
2151 lmo.l_addr_offset = 0;
2152 lmo.l_addr_size = 4;
2153
2154 lmo.l_name_offset = 4;
2155 lmo.l_name_size = 4;
2156
2157 lmo.l_next_offset = 12;
2158 lmo.l_next_size = 4;
2159
2160 lmo.l_prev_offset = 16;
2161 lmo.l_prev_size = 4;
2162 }
2163
2164 return lmp;
2165 }
2166
2167 static int
2168 sh_dsp_register_sim_regno (int nr)
2169 {
2170 if (legacy_register_sim_regno (nr) < 0)
2171 return legacy_register_sim_regno (nr);
2172 if (nr >= DSR_REGNUM && nr <= Y1_REGNUM)
2173 return nr - DSR_REGNUM + SIM_SH_DSR_REGNUM;
2174 if (nr == MOD_REGNUM)
2175 return SIM_SH_MOD_REGNUM;
2176 if (nr == RS_REGNUM)
2177 return SIM_SH_RS_REGNUM;
2178 if (nr == RE_REGNUM)
2179 return SIM_SH_RE_REGNUM;
2180 if (nr >= DSP_R0_BANK_REGNUM && nr <= DSP_R7_BANK_REGNUM)
2181 return nr - DSP_R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM;
2182 return nr;
2183 }
2184
2185 static int
2186 sh_sh2a_register_sim_regno (int nr)
2187 {
2188 switch (nr)
2189 {
2190 case TBR_REGNUM:
2191 return SIM_SH_TBR_REGNUM;
2192 case IBNR_REGNUM:
2193 return SIM_SH_IBNR_REGNUM;
2194 case IBCR_REGNUM:
2195 return SIM_SH_IBCR_REGNUM;
2196 case BANK_REGNUM:
2197 return SIM_SH_BANK_REGNUM;
2198 case MACLB_REGNUM:
2199 return SIM_SH_BANK_MACL_REGNUM;
2200 case GBRB_REGNUM:
2201 return SIM_SH_BANK_GBR_REGNUM;
2202 case PRB_REGNUM:
2203 return SIM_SH_BANK_PR_REGNUM;
2204 case IVNB_REGNUM:
2205 return SIM_SH_BANK_IVN_REGNUM;
2206 case MACHB_REGNUM:
2207 return SIM_SH_BANK_MACH_REGNUM;
2208 default:
2209 break;
2210 }
2211 return legacy_register_sim_regno (nr);
2212 }
2213
2214 static struct sh_frame_cache *
2215 sh_alloc_frame_cache (void)
2216 {
2217 struct sh_frame_cache *cache;
2218 int i;
2219
2220 cache = FRAME_OBSTACK_ZALLOC (struct sh_frame_cache);
2221
2222 /* Base address. */
2223 cache->base = 0;
2224 cache->saved_sp = 0;
2225 cache->sp_offset = 0;
2226 cache->pc = 0;
2227
2228 /* Frameless until proven otherwise. */
2229 cache->uses_fp = 0;
2230
2231 /* Saved registers. We initialize these to -1 since zero is a valid
2232 offset (that's where fp is supposed to be stored). */
2233 for (i = 0; i < SH_NUM_REGS; i++)
2234 {
2235 cache->saved_regs[i] = -1;
2236 }
2237
2238 return cache;
2239 }
2240
2241 static struct sh_frame_cache *
2242 sh_frame_cache (struct frame_info *next_frame, void **this_cache)
2243 {
2244 struct sh_frame_cache *cache;
2245 CORE_ADDR current_pc;
2246 int i;
2247
2248 if (*this_cache)
2249 return *this_cache;
2250
2251 cache = sh_alloc_frame_cache ();
2252 *this_cache = cache;
2253
2254 /* In principle, for normal frames, fp holds the frame pointer,
2255 which holds the base address for the current stack frame.
2256 However, for functions that don't need it, the frame pointer is
2257 optional. For these "frameless" functions the frame pointer is
2258 actually the frame pointer of the calling frame. */
2259 cache->base = frame_unwind_register_unsigned (next_frame, FP_REGNUM);
2260 if (cache->base == 0)
2261 return cache;
2262
2263 cache->pc = frame_func_unwind (next_frame);
2264 current_pc = frame_pc_unwind (next_frame);
2265 if (cache->pc != 0)
2266 sh_analyze_prologue (cache->pc, current_pc, cache);
2267
2268 if (!cache->uses_fp)
2269 {
2270 /* We didn't find a valid frame, which means that CACHE->base
2271 currently holds the frame pointer for our calling frame. If
2272 we're at the start of a function, or somewhere half-way its
2273 prologue, the function's frame probably hasn't been fully
2274 setup yet. Try to reconstruct the base address for the stack
2275 frame by looking at the stack pointer. For truly "frameless"
2276 functions this might work too. */
2277 cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
2278 }
2279
2280 /* Now that we have the base address for the stack frame we can
2281 calculate the value of sp in the calling frame. */
2282 cache->saved_sp = cache->base + cache->sp_offset;
2283
2284 /* Adjust all the saved registers such that they contain addresses
2285 instead of offsets. */
2286 for (i = 0; i < SH_NUM_REGS; i++)
2287 if (cache->saved_regs[i] != -1)
2288 cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i] - 4;
2289
2290 return cache;
2291 }
2292
2293 static void
2294 sh_frame_prev_register (struct frame_info *next_frame, void **this_cache,
2295 int regnum, int *optimizedp,
2296 enum lval_type *lvalp, CORE_ADDR *addrp,
2297 int *realnump, void *valuep)
2298 {
2299 struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
2300
2301 gdb_assert (regnum >= 0);
2302
2303 if (regnum == SP_REGNUM && cache->saved_sp)
2304 {
2305 *optimizedp = 0;
2306 *lvalp = not_lval;
2307 *addrp = 0;
2308 *realnump = -1;
2309 if (valuep)
2310 {
2311 /* Store the value. */
2312 store_unsigned_integer (valuep, 4, cache->saved_sp);
2313 }
2314 return;
2315 }
2316
2317 /* The PC of the previous frame is stored in the PR register of
2318 the current frame. Frob regnum so that we pull the value from
2319 the correct place. */
2320 if (regnum == PC_REGNUM)
2321 regnum = PR_REGNUM;
2322
2323 if (regnum < SH_NUM_REGS && cache->saved_regs[regnum] != -1)
2324 {
2325 *optimizedp = 0;
2326 *lvalp = lval_memory;
2327 *addrp = cache->saved_regs[regnum];
2328 *realnump = -1;
2329 if (valuep)
2330 {
2331 /* Read the value in from memory. */
2332 read_memory (*addrp, valuep,
2333 register_size (current_gdbarch, regnum));
2334 }
2335 return;
2336 }
2337
2338 frame_register_unwind (next_frame, regnum,
2339 optimizedp, lvalp, addrp, realnump, valuep);
2340 }
2341
2342 static void
2343 sh_frame_this_id (struct frame_info *next_frame, void **this_cache,
2344 struct frame_id *this_id)
2345 {
2346 struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
2347
2348 /* This marks the outermost frame. */
2349 if (cache->base == 0)
2350 return;
2351
2352 *this_id = frame_id_build (cache->saved_sp, cache->pc);
2353 }
2354
2355 static const struct frame_unwind sh_frame_unwind = {
2356 NORMAL_FRAME,
2357 sh_frame_this_id,
2358 sh_frame_prev_register
2359 };
2360
2361 static const struct frame_unwind *
2362 sh_frame_sniffer (struct frame_info *next_frame)
2363 {
2364 return &sh_frame_unwind;
2365 }
2366
2367 static CORE_ADDR
2368 sh_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
2369 {
2370 return frame_unwind_register_unsigned (next_frame, SP_REGNUM);
2371 }
2372
2373 static CORE_ADDR
2374 sh_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2375 {
2376 return frame_unwind_register_unsigned (next_frame, PC_REGNUM);
2377 }
2378
2379 static struct frame_id
2380 sh_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
2381 {
2382 return frame_id_build (sh_unwind_sp (gdbarch, next_frame),
2383 frame_pc_unwind (next_frame));
2384 }
2385
2386 static CORE_ADDR
2387 sh_frame_base_address (struct frame_info *next_frame, void **this_cache)
2388 {
2389 struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
2390
2391 return cache->base;
2392 }
2393
2394 static const struct frame_base sh_frame_base = {
2395 &sh_frame_unwind,
2396 sh_frame_base_address,
2397 sh_frame_base_address,
2398 sh_frame_base_address
2399 };
2400
2401 /* The epilogue is defined here as the area at the end of a function,
2402 either on the `ret' instruction itself or after an instruction which
2403 destroys the function's stack frame. */
2404 static int
2405 sh_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
2406 {
2407 CORE_ADDR func_addr = 0, func_end = 0;
2408
2409 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
2410 {
2411 ULONGEST inst;
2412 /* The sh epilogue is max. 14 bytes long. Give another 14 bytes
2413 for a nop and some fixed data (e.g. big offsets) which are
2414 unfortunately also treated as part of the function (which
2415 means, they are below func_end. */
2416 CORE_ADDR addr = func_end - 28;
2417 if (addr < func_addr + 4)
2418 addr = func_addr + 4;
2419 if (pc < addr)
2420 return 0;
2421
2422 /* First search forward until hitting an rts. */
2423 while (addr < func_end
2424 && !IS_RTS (read_memory_unsigned_integer (addr, 2)))
2425 addr += 2;
2426 if (addr >= func_end)
2427 return 0;
2428
2429 /* At this point we should find a mov.l @r15+,r14 instruction,
2430 either before or after the rts. If not, then the function has
2431 probably no "normal" epilogue and we bail out here. */
2432 inst = read_memory_unsigned_integer (addr - 2, 2);
2433 if (IS_RESTORE_FP (read_memory_unsigned_integer (addr - 2, 2)))
2434 addr -= 2;
2435 else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr + 2, 2)))
2436 return 0;
2437
2438 inst = read_memory_unsigned_integer (addr - 2, 2);
2439
2440 /* Step over possible lds.l @r15+,macl. */
2441 if (IS_MACL_LDS (inst))
2442 {
2443 addr -= 2;
2444 inst = read_memory_unsigned_integer (addr - 2, 2);
2445 }
2446
2447 /* Step over possible lds.l @r15+,pr. */
2448 if (IS_LDS (inst))
2449 {
2450 addr -= 2;
2451 inst = read_memory_unsigned_integer (addr - 2, 2);
2452 }
2453
2454 /* Step over possible mov r14,r15. */
2455 if (IS_MOV_FP_SP (inst))
2456 {
2457 addr -= 2;
2458 inst = read_memory_unsigned_integer (addr - 2, 2);
2459 }
2460
2461 /* Now check for FP adjustments, using add #imm,r14 or add rX, r14
2462 instructions. */
2463 while (addr > func_addr + 4
2464 && (IS_ADD_REG_TO_FP (inst) || IS_ADD_IMM_FP (inst)))
2465 {
2466 addr -= 2;
2467 inst = read_memory_unsigned_integer (addr - 2, 2);
2468 }
2469
2470 /* On SH2a check if the previous instruction was perhaps a MOVI20.
2471 That's allowed for the epilogue. */
2472 if ((gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a
2473 || gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a_nofpu)
2474 && addr > func_addr + 6
2475 && IS_MOVI20 (read_memory_unsigned_integer (addr - 4, 2)))
2476 addr -= 4;
2477
2478 if (pc >= addr)
2479 return 1;
2480 }
2481 return 0;
2482 }
2483
2484 static gdbarch_init_ftype sh_gdbarch_init;
2485
2486 static struct gdbarch *
2487 sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2488 {
2489 struct gdbarch *gdbarch;
2490
2491 sh_show_regs = sh_generic_show_regs;
2492 switch (info.bfd_arch_info->mach)
2493 {
2494 case bfd_mach_sh2e:
2495 sh_show_regs = sh2e_show_regs;
2496 break;
2497 case bfd_mach_sh2a:
2498 sh_show_regs = sh2a_show_regs;
2499 break;
2500 case bfd_mach_sh2a_nofpu:
2501 sh_show_regs = sh2a_nofpu_show_regs;
2502 break;
2503 case bfd_mach_sh_dsp:
2504 sh_show_regs = sh_dsp_show_regs;
2505 break;
2506
2507 case bfd_mach_sh3:
2508 sh_show_regs = sh3_show_regs;
2509 break;
2510
2511 case bfd_mach_sh3e:
2512 sh_show_regs = sh3e_show_regs;
2513 break;
2514
2515 case bfd_mach_sh3_dsp:
2516 case bfd_mach_sh4al_dsp:
2517 sh_show_regs = sh3_dsp_show_regs;
2518 break;
2519
2520 case bfd_mach_sh4:
2521 case bfd_mach_sh4a:
2522 sh_show_regs = sh4_show_regs;
2523 break;
2524
2525 case bfd_mach_sh4_nofpu:
2526 case bfd_mach_sh4a_nofpu:
2527 sh_show_regs = sh4_nofpu_show_regs;
2528 break;
2529
2530 #if 0
2531 case bfd_mach_sh5:
2532 sh_show_regs = sh64_show_regs;
2533 /* SH5 is handled entirely in sh64-tdep.c */
2534 return sh64_gdbarch_init (info, arches);
2535 #endif
2536 }
2537
2538 /* If there is already a candidate, use it. */
2539 arches = gdbarch_list_lookup_by_info (arches, &info);
2540 if (arches != NULL)
2541 return arches->gdbarch;
2542
2543 /* None found, create a new architecture from the information
2544 provided. */
2545 gdbarch = gdbarch_alloc (&info, NULL);
2546
2547 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2548 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2549 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2550 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2551 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2552 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2553 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2554 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2555
2556 set_gdbarch_num_regs (gdbarch, SH_NUM_REGS);
2557 set_gdbarch_sp_regnum (gdbarch, 15);
2558 set_gdbarch_pc_regnum (gdbarch, 16);
2559 set_gdbarch_fp0_regnum (gdbarch, -1);
2560 set_gdbarch_num_pseudo_regs (gdbarch, 0);
2561
2562 set_gdbarch_register_type (gdbarch, sh_default_register_type);
2563
2564 set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info);
2565
2566 set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc);
2567 set_gdbarch_deprecated_use_struct_convention (gdbarch, sh_use_struct_convention);
2568
2569 set_gdbarch_print_insn (gdbarch, gdb_print_insn_sh);
2570 set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno);
2571
2572 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
2573
2574 set_gdbarch_store_return_value (gdbarch, sh_default_store_return_value);
2575 set_gdbarch_extract_return_value (gdbarch, sh_default_extract_return_value);
2576 set_gdbarch_deprecated_extract_struct_value_address (gdbarch, sh_extract_struct_value_address);
2577
2578 set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue);
2579 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2580
2581 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu);
2582
2583 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2584
2585 set_gdbarch_frame_align (gdbarch, sh_frame_align);
2586 set_gdbarch_unwind_sp (gdbarch, sh_unwind_sp);
2587 set_gdbarch_unwind_pc (gdbarch, sh_unwind_pc);
2588 set_gdbarch_unwind_dummy_id (gdbarch, sh_unwind_dummy_id);
2589 frame_base_set_default (gdbarch, &sh_frame_base);
2590
2591 set_gdbarch_in_function_epilogue_p (gdbarch, sh_in_function_epilogue_p);
2592
2593 switch (info.bfd_arch_info->mach)
2594 {
2595 case bfd_mach_sh:
2596 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
2597 break;
2598
2599 case bfd_mach_sh2:
2600 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
2601 break;
2602
2603 case bfd_mach_sh2e:
2604 /* doubles on sh2e and sh3e are actually 4 byte. */
2605 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2606
2607 set_gdbarch_register_name (gdbarch, sh_sh2e_register_name);
2608 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
2609 set_gdbarch_fp0_regnum (gdbarch, 25);
2610 set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value);
2611 set_gdbarch_extract_return_value (gdbarch,
2612 sh3e_sh4_extract_return_value);
2613 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2614 break;
2615
2616 case bfd_mach_sh2a:
2617 set_gdbarch_register_name (gdbarch, sh_sh2a_register_name);
2618 set_gdbarch_register_type (gdbarch, sh_sh2a_register_type);
2619 set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno);
2620
2621 set_gdbarch_fp0_regnum (gdbarch, 25);
2622 set_gdbarch_num_pseudo_regs (gdbarch, 9);
2623 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
2624 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
2625 set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value);
2626 set_gdbarch_extract_return_value (gdbarch, sh3e_sh4_extract_return_value);
2627 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2628 break;
2629
2630 case bfd_mach_sh2a_nofpu:
2631 set_gdbarch_register_name (gdbarch, sh_sh2a_nofpu_register_name);
2632 set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno);
2633
2634 set_gdbarch_num_pseudo_regs (gdbarch, 1);
2635 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
2636 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
2637 break;
2638
2639 case bfd_mach_sh_dsp:
2640 set_gdbarch_register_name (gdbarch, sh_sh_dsp_register_name);
2641 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
2642 break;
2643
2644 case bfd_mach_sh3:
2645 set_gdbarch_register_name (gdbarch, sh_sh3_register_name);
2646 break;
2647
2648 case bfd_mach_sh3e:
2649 /* doubles on sh2e and sh3e are actually 4 byte. */
2650 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2651
2652 set_gdbarch_register_name (gdbarch, sh_sh3e_register_name);
2653 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
2654 set_gdbarch_fp0_regnum (gdbarch, 25);
2655 set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value);
2656 set_gdbarch_extract_return_value (gdbarch,
2657 sh3e_sh4_extract_return_value);
2658 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2659 break;
2660
2661 case bfd_mach_sh3_dsp:
2662 set_gdbarch_register_name (gdbarch, sh_sh3_dsp_register_name);
2663 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
2664 break;
2665
2666 case bfd_mach_sh4:
2667 case bfd_mach_sh4a:
2668 set_gdbarch_register_name (gdbarch, sh_sh4_register_name);
2669 set_gdbarch_register_type (gdbarch, sh_sh4_register_type);
2670 set_gdbarch_fp0_regnum (gdbarch, 25);
2671 set_gdbarch_num_pseudo_regs (gdbarch, 13);
2672 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
2673 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
2674 set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value);
2675 set_gdbarch_extract_return_value (gdbarch,
2676 sh3e_sh4_extract_return_value);
2677 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2678 break;
2679
2680 case bfd_mach_sh4_nofpu:
2681 case bfd_mach_sh4a_nofpu:
2682 set_gdbarch_register_name (gdbarch, sh_sh4_nofpu_register_name);
2683 break;
2684
2685 case bfd_mach_sh4al_dsp:
2686 set_gdbarch_register_name (gdbarch, sh_sh4al_dsp_register_name);
2687 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
2688 break;
2689
2690 default:
2691 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
2692 break;
2693 }
2694
2695 /* Hook in ABI-specific overrides, if they have been registered. */
2696 gdbarch_init_osabi (info, gdbarch);
2697
2698 frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer);
2699 frame_unwind_append_sniffer (gdbarch, sh_frame_sniffer);
2700
2701 return gdbarch;
2702 }
2703
2704 extern initialize_file_ftype _initialize_sh_tdep; /* -Wmissing-prototypes */
2705
2706 void
2707 _initialize_sh_tdep (void)
2708 {
2709 struct cmd_list_element *c;
2710
2711 gdbarch_register (bfd_arch_sh, sh_gdbarch_init, NULL);
2712
2713 add_com ("regs", class_vars, sh_show_regs_command, "Print all registers");
2714 }