1 /* Target-dependent code for Hitachi Super-H, for GDB.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
3 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
23 Contributed by Steve Chamberlain
37 #include "inferior.h" /* for BEFORE_TEXT_END etc. */
38 #include "gdb_string.h"
39 #include "arch-utils.h"
40 #include "floatformat.h"
47 #include "solib-svr4.h"
51 /* registers numbers shared with the simulator */
52 #include "gdb/sim-sh.h"
54 void (*sh_show_regs
) (void);
55 CORE_ADDR (*skip_prologue_hard_way
) (CORE_ADDR
);
56 void (*do_pseudo_register
) (int);
58 #define SH_DEFAULT_NUM_REGS 59
60 /* Define other aspects of the stack frame.
61 we keep a copy of the worked out return pc lying around, since it
62 is a useful bit of info */
64 struct frame_extra_info
72 sh_generic_register_name (int reg_nr
)
74 static char *register_names
[] =
76 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
77 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
78 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
80 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
81 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
83 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
84 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
88 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
90 return register_names
[reg_nr
];
94 sh_sh_register_name (int reg_nr
)
96 static char *register_names
[] =
98 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
99 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
100 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
102 "", "", "", "", "", "", "", "",
103 "", "", "", "", "", "", "", "",
105 "", "", "", "", "", "", "", "",
106 "", "", "", "", "", "", "", "",
110 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
112 return register_names
[reg_nr
];
116 sh_sh3_register_name (int reg_nr
)
118 static char *register_names
[] =
120 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
121 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
122 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
124 "", "", "", "", "", "", "", "",
125 "", "", "", "", "", "", "", "",
127 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
128 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
132 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
134 return register_names
[reg_nr
];
138 sh_sh3e_register_name (int reg_nr
)
140 static char *register_names
[] =
142 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
143 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
144 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
146 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
147 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
149 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
150 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
154 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
156 return register_names
[reg_nr
];
160 sh_sh_dsp_register_name (int reg_nr
)
162 static char *register_names
[] =
164 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
165 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
166 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
168 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
169 "y0", "y1", "", "", "", "", "", "mod",
171 "rs", "re", "", "", "", "", "", "",
172 "", "", "", "", "", "", "", "",
176 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
178 return register_names
[reg_nr
];
182 sh_sh3_dsp_register_name (int reg_nr
)
184 static char *register_names
[] =
186 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
187 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
188 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
190 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
191 "y0", "y1", "", "", "", "", "", "mod",
193 "rs", "re", "", "", "", "", "", "",
194 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b"
195 "", "", "", "", "", "", "", "",
199 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
201 return register_names
[reg_nr
];
205 sh_sh4_register_name (int reg_nr
)
207 static char *register_names
[] =
209 /* general registers 0-15 */
210 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
211 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
213 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
216 /* floating point registers 25 - 40 */
217 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
218 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
222 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
224 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
225 /* double precision (pseudo) 59 - 66 */
226 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
227 /* vectors (pseudo) 67 - 70 */
228 "fv0", "fv4", "fv8", "fv12",
229 /* FIXME: missing XF 71 - 86 */
230 /* FIXME: missing XD 87 - 94 */
234 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
236 return register_names
[reg_nr
];
240 sh_sh64_register_name (int reg_nr
)
242 static char *register_names
[] =
244 /* SH MEDIA MODE (ISA 32) */
245 /* general registers (64-bit) 0-63 */
246 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
247 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
248 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
249 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
250 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
251 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
252 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
253 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
258 /* status reg., saved status reg., saved pc reg. (64-bit) 65-67 */
261 /* target registers (64-bit) 68-75*/
262 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7",
264 /* floating point state control register (32-bit) 76 */
267 /* single precision floating point registers (32-bit) 77-140*/
268 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
269 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
270 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23",
271 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31",
272 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39",
273 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47",
274 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55",
275 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63",
277 /* double precision registers (pseudo) 141-172 */
278 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
279 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30",
280 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46",
281 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62",
283 /* floating point pairs (pseudo) 173-204*/
284 "fp0", "fp2", "fp4", "fp6", "fp8", "fp10", "fp12", "fp14",
285 "fp16", "fp18", "fp20", "fp22", "fp24", "fp26", "fp28", "fp30",
286 "fp32", "fp34", "fp36", "fp38", "fp40", "fp42", "fp44", "fp46",
287 "fp48", "fp50", "fp52", "fp54", "fp56", "fp58", "fp60", "fp62",
289 /* floating point vectors (4 floating point regs) (pseudo) 205-220*/
290 "fv0", "fv4", "fv8", "fv12", "fv16", "fv20", "fv24", "fv28",
291 "fv32", "fv36", "fv40", "fv44", "fv48", "fv52", "fv56", "fv60",
293 /* SH COMPACT MODE (ISA 16) (all pseudo) 221-272*/
294 "r0_c", "r1_c", "r2_c", "r3_c", "r4_c", "r5_c", "r6_c", "r7_c",
295 "r8_c", "r9_c", "r10_c", "r11_c", "r12_c", "r13_c", "r14_c", "r15_c",
297 "gbr_c", "mach_c", "macl_c", "pr_c", "t_c",
299 "fr0_c", "fr1_c", "fr2_c", "fr3_c", "fr4_c", "fr5_c", "fr6_c", "fr7_c",
300 "fr8_c", "fr9_c", "fr10_c", "fr11_c", "fr12_c", "fr13_c", "fr14_c", "fr15_c",
301 "dr0_c", "dr2_c", "dr4_c", "dr6_c", "dr8_c", "dr10_c", "dr12_c", "dr14_c",
302 "fv0_c", "fv4_c", "fv8_c", "fv12_c",
303 /* FIXME!!!! XF0 XF15, XD0 XD14 ?????*/
308 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
310 return register_names
[reg_nr
];
313 #define NUM_PSEUDO_REGS_SH_MEDIA 80
314 #define NUM_PSEUDO_REGS_SH_COMPACT 51
316 static const unsigned char *
317 sh_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
319 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */
320 static unsigned char breakpoint
[] = {0xc3, 0xc3};
322 *lenptr
= sizeof (breakpoint
);
326 /* Macros and functions for setting and testing a bit in a minimal
327 symbol that marks it as 32-bit function. The MSB of the minimal
328 symbol's "info" field is used for this purpose. This field is
329 already being used to store the symbol size, so the assumption is
330 that the symbol size cannot exceed 2^31.
332 ELF_MAKE_MSYMBOL_SPECIAL
333 tests whether an ELF symbol is "special", i.e. refers
334 to a 32-bit function, and sets a "special" bit in a
335 minimal symbol to mark it as a 32-bit function
336 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol
337 MSYMBOL_SIZE returns the size of the minimal symbol, i.e.
338 the "info" field with the "special" bit masked out */
340 #define MSYMBOL_IS_SPECIAL(msym) \
341 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
344 sh64_elf_make_msymbol_special (asymbol
*sym
, struct minimal_symbol
*msym
)
349 if (((elf_symbol_type
*)(sym
))->internal_elf_sym
.st_other
== STO_SH5_ISA32
)
351 MSYMBOL_INFO (msym
) = (char *) (((long) MSYMBOL_INFO (msym
)) | 0x80000000);
352 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
356 /* ISA32 (shmedia) function addresses are odd (bit 0 is set). Here
357 are some macros to test, set, or clear bit 0 of addresses. */
358 #define IS_ISA32_ADDR(addr) ((addr) & 1)
359 #define MAKE_ISA32_ADDR(addr) ((addr) | 1)
360 #define UNMAKE_ISA32_ADDR(addr) ((addr) & ~1)
363 pc_is_isa32 (bfd_vma memaddr
)
365 struct minimal_symbol
*sym
;
367 /* If bit 0 of the address is set, assume this is a
368 ISA32 (shmedia) address. */
369 if (IS_ISA32_ADDR (memaddr
))
372 /* A flag indicating that this is a ISA32 function is stored by elfread.c in
373 the high bit of the info field. Use this to decide if the function is
375 sym
= lookup_minimal_symbol_by_pc (memaddr
);
377 return MSYMBOL_IS_SPECIAL (sym
);
382 static const unsigned char *
383 sh_sh64_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
385 /* The BRK instruction for shmedia is
386 01101111 11110101 11111111 11110000
387 which translates in big endian mode to 0x6f, 0xf5, 0xff, 0xf0
388 and in little endian mode to 0xf0, 0xff, 0xf5, 0x6f */
390 /* The BRK instruction for shcompact is
392 which translates in big endian mode to 0x0, 0x3b
393 and in little endian mode to 0x3b, 0x0*/
395 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
397 if (pc_is_isa32 (*pcptr
))
399 static unsigned char big_breakpoint_media
[] = {0x6f, 0xf5, 0xff, 0xf0};
400 *pcptr
= UNMAKE_ISA32_ADDR (*pcptr
);
401 *lenptr
= sizeof (big_breakpoint_media
);
402 return big_breakpoint_media
;
406 static unsigned char big_breakpoint_compact
[] = {0x0, 0x3b};
407 *lenptr
= sizeof (big_breakpoint_compact
);
408 return big_breakpoint_compact
;
413 if (pc_is_isa32 (*pcptr
))
415 static unsigned char little_breakpoint_media
[] = {0xf0, 0xff, 0xf5, 0x6f};
416 *pcptr
= UNMAKE_ISA32_ADDR (*pcptr
);
417 *lenptr
= sizeof (little_breakpoint_media
);
418 return little_breakpoint_media
;
422 static unsigned char little_breakpoint_compact
[] = {0x3b, 0x0};
423 *lenptr
= sizeof (little_breakpoint_compact
);
424 return little_breakpoint_compact
;
429 /* Prologue looks like
430 [mov.l <regs>,@-r15]...
435 Actually it can be more complicated than this. For instance, with
453 /* PTABS/L Rn, TRa 0110101111110001nnnnnnl00aaa0000
454 with l=1 and n = 18 0110101111110001010010100aaa0000 */
455 #define IS_PTABSL_R18(x) (((x) & 0xffffff8f) == 0x6bf14a00)
457 /* STS.L PR,@-r0 0100000000100010
458 r0-4-->r0, PR-->(r0) */
459 #define IS_STS_R0(x) ((x) == 0x4022)
461 /* STS PR, Rm 0000mmmm00101010
463 #define IS_STS_PR(x) (((x) & 0xf0ff) == 0x2a)
465 /* MOV.L Rm,@(disp,r15) 00011111mmmmdddd
467 #define IS_MOV_TO_R15(x) (((x) & 0xff00) == 0x1f00)
469 /* MOV.L R14,@(disp,r15) 000111111110dddd
470 R14-->(dispx4+r15) */
471 #define IS_MOV_R14(x) (((x) & 0xfff0) == 0x1fe0)
473 /* ST.Q R14, disp, R18 101011001110dddddddddd0100100000
474 R18-->(dispx8+R14) */
475 #define IS_STQ_R18_R14(x) (((x) & 0xfff003ff) == 0xace00120)
477 /* ST.Q R15, disp, R18 101011001111dddddddddd0100100000
478 R18-->(dispx8+R15) */
479 #define IS_STQ_R18_R15(x) (((x) & 0xfff003ff) == 0xacf00120)
481 /* ST.L R15, disp, R18 101010001111dddddddddd0100100000
482 R18-->(dispx4+R15) */
483 #define IS_STL_R18_R15(x) (((x) & 0xfff003ff) == 0xa8f00120)
485 /* ST.Q R15, disp, R14 1010 1100 1111 dddd dddd dd00 1110 0000
486 R14-->(dispx8+R15) */
487 #define IS_STQ_R14_R15(x) (((x) & 0xfff003ff) == 0xacf000e0)
489 /* ST.L R15, disp, R14 1010 1000 1111 dddd dddd dd00 1110 0000
490 R14-->(dispx4+R15) */
491 #define IS_STL_R14_R15(x) (((x) & 0xfff003ff) == 0xa8f000e0)
493 /* ADDI.L R15,imm,R15 1101 0100 1111 ssss ssss ss00 1111 0000
495 #define IS_ADDIL_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd4f000f0)
497 /* ADDI R15,imm,R15 1101 0000 1111 ssss ssss ss00 1111 0000
499 #define IS_ADDI_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd0f000f0)
501 /* ADD.L R15,R63,R14 0000 0000 1111 1000 1111 1100 1110 0000
503 #define IS_ADDL_SP_FP_MEDIA(x) ((x) == 0x00f8fce0)
505 /* ADD R15,R63,R14 0000 0000 1111 1001 1111 1100 1110 0000
507 #define IS_ADD_SP_FP_MEDIA(x) ((x) == 0x00f9fce0)
509 #define IS_MOV_SP_FP_MEDIA(x) (IS_ADDL_SP_FP_MEDIA(x) || IS_ADD_SP_FP_MEDIA(x))
511 /* MOV #imm, R0 1110 0000 ssss ssss
513 #define IS_MOV_R0(x) (((x) & 0xff00) == 0xe000)
515 /* MOV.L @(disp,PC), R0 1101 0000 iiii iiii */
516 #define IS_MOVL_R0(x) (((x) & 0xff00) == 0xd000)
518 /* ADD r15,r0 0011 0000 1111 1100
520 #define IS_ADD_SP_R0(x) ((x) == 0x30fc)
522 /* MOV.L R14 @-R0 0010 0000 1110 0110
523 R14-->(R0-4), R0-4-->R0 */
524 #define IS_MOV_R14_R0(x) ((x) == 0x20e6)
526 /* ADD Rm,R63,Rn Rm+R63-->Rn 0000 00mm mmmm 1001 1111 11nn nnnn 0000
527 where Rm is one of r2-r9 which are the argument registers. */
528 /* FIXME: Recognize the float and double register moves too! */
529 #define IS_MEDIA_IND_ARG_MOV(x) \
530 ((((x) & 0xfc0ffc0f) == 0x0009fc00) && (((x) & 0x03f00000) >= 0x00200000 && ((x) & 0x03f00000) <= 0x00900000))
532 /* ST.Q Rn,0,Rm Rm-->Rn+0 1010 11nn nnnn 0000 0000 00mm mmmm 0000
533 or ST.L Rn,0,Rm Rm-->Rn+0 1010 10nn nnnn 0000 0000 00mm mmmm 0000
534 where Rm is one of r2-r9 which are the argument registers. */
535 #define IS_MEDIA_ARG_MOV(x) \
536 (((((x) & 0xfc0ffc0f) == 0xac000000) || (((x) & 0xfc0ffc0f) == 0xa8000000)) \
537 && (((x) & 0x000003f0) >= 0x00000020 && ((x) & 0x000003f0) <= 0x00000090))
539 /* ST.B R14,0,Rn Rn-->(R14+0) 1010 0000 1110 0000 0000 00nn nnnn 0000*/
540 /* ST.W R14,0,Rn Rn-->(R14+0) 1010 0100 1110 0000 0000 00nn nnnn 0000*/
541 /* ST.L R14,0,Rn Rn-->(R14+0) 1010 1000 1110 0000 0000 00nn nnnn 0000*/
542 /* FST.S R14,0,FRn Rn-->(R14+0) 1011 0100 1110 0000 0000 00nn nnnn 0000*/
543 /* FST.D R14,0,DRn Rn-->(R14+0) 1011 1100 1110 0000 0000 00nn nnnn 0000*/
544 #define IS_MEDIA_MOV_TO_R14(x) \
545 ((((x) & 0xfffffc0f) == 0xa0e00000) \
546 || (((x) & 0xfffffc0f) == 0xa4e00000) \
547 || (((x) & 0xfffffc0f) == 0xa8e00000) \
548 || (((x) & 0xfffffc0f) == 0xb4e00000) \
549 || (((x) & 0xfffffc0f) == 0xbce00000))
551 /* MOV Rm, Rn Rm-->Rn 0110 nnnn mmmm 0011
553 #define IS_COMPACT_IND_ARG_MOV(x) \
554 ((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0020) && (((x) & 0x00f0) <= 0x0090))
556 /* compact direct arg move!
557 MOV.L Rn, @r14 0010 1110 mmmm 0010 */
558 #define IS_COMPACT_ARG_MOV(x) \
559 (((((x) & 0xff0f) == 0x2e02) && (((x) & 0x00f0) >= 0x0020) && ((x) & 0x00f0) <= 0x0090))
561 /* MOV.B Rm, @R14 0010 1110 mmmm 0000
562 MOV.W Rm, @R14 0010 1110 mmmm 0001 */
563 #define IS_COMPACT_MOV_TO_R14(x) \
564 ((((x) & 0xff0f) == 0x2e00) || (((x) & 0xff0f) == 0x2e01))
566 #define IS_JSR_R0(x) ((x) == 0x400b)
567 #define IS_NOP(x) ((x) == 0x0009)
570 /* STS.L PR,@-r15 0100111100100010
571 r15-4-->r15, PR-->(r15) */
572 #define IS_STS(x) ((x) == 0x4f22)
574 /* MOV.L Rm,@-r15 00101111mmmm0110
575 r15-4-->r15, Rm-->(R15) */
576 #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
578 #define GET_PUSHED_REG(x) (((x) >> 4) & 0xf)
580 /* MOV r15,r14 0110111011110011
582 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
584 /* ADD #imm,r15 01111111iiiiiiii
586 #define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00)
588 #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
589 #define IS_SHLL_R3(x) ((x) == 0x4300)
591 /* ADD r3,r15 0011111100111100
593 #define IS_ADD_R3SP(x) ((x) == 0x3f3c)
595 /* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
596 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
597 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
598 #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b)
600 /* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011
601 MOV.L Rm,@(disp,Rn) Rm-->(dispx4+Rn) 0001nnnnmmmmdddd
602 MOV.L Rm,@Rn Rm-->(Rn) 0010nnnnmmmm0010
603 where Rm is one of r4,r5,r6,r7 which are the argument registers. */
604 #define IS_ARG_MOV(x) \
605 (((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) \
606 || ((((x) & 0xf000) == 0x1000) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) \
607 || ((((x) & 0xf00f) == 0x2002) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)))
609 /* MOV.L Rm,@(disp,r14) 00011110mmmmdddd
610 Rm-->(dispx4+r14) where Rm is one of r4,r5,r6,r7 */
611 #define IS_MOV_TO_R14(x) \
612 ((((x) & 0xff00) == 0x1e) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070))
614 #define FPSCR_SZ (1 << 20)
616 /* Skip any prologue before the guts of a function */
618 /* Skip the prologue using the debug information. If this fails we'll
619 fall back on the 'guess' method below. */
621 after_prologue (CORE_ADDR pc
)
623 struct symtab_and_line sal
;
624 CORE_ADDR func_addr
, func_end
;
626 /* If we can not find the symbol in the partial symbol table, then
627 there is no hope we can determine the function's start address
629 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
632 /* Get the line associated with FUNC_ADDR. */
633 sal
= find_pc_line (func_addr
, 0);
635 /* There are only two cases to consider. First, the end of the source line
636 is within the function bounds. In that case we return the end of the
637 source line. Second is the end of the source line extends beyond the
638 bounds of the current function. We need to use the slow code to
639 examine instructions in that case. */
640 if (sal
.end
< func_end
)
646 /* Here we look at each instruction in the function, and try to guess
647 where the prologue ends. Unfortunately this is not always
650 sh_skip_prologue_hard_way (CORE_ADDR start_pc
)
658 for (here
= start_pc
, end
= start_pc
+ (2 * 28); here
< end
;)
660 int w
= read_memory_integer (here
, 2);
662 if (IS_FMOV (w
) || IS_PUSH (w
) || IS_STS (w
) || IS_MOV_R3 (w
)
663 || IS_ADD_R3SP (w
) || IS_ADD_SP (w
) || IS_SHLL_R3 (w
)
664 || IS_ARG_MOV (w
) || IS_MOV_TO_R14 (w
))
668 else if (IS_MOV_SP_FP (w
))
674 /* Don't bail out yet, if we are before the copy of sp. */
683 look_for_args_moves (CORE_ADDR start_pc
, int media_mode
)
687 int insn_size
= (media_mode
? 4 : 2);
689 for (here
= start_pc
, end
= start_pc
+ (insn_size
* 28); here
< end
;)
693 w
= read_memory_integer (UNMAKE_ISA32_ADDR (here
), insn_size
);
695 if (IS_MEDIA_IND_ARG_MOV (w
))
697 /* This must be followed by a store to r14, so the argument
698 is where the debug info says it is. This can happen after
699 the SP has been saved, unfortunately. */
701 int next_insn
= read_memory_integer (UNMAKE_ISA32_ADDR (here
),
704 if (IS_MEDIA_MOV_TO_R14 (next_insn
))
707 else if (IS_MEDIA_ARG_MOV (w
))
709 /* These instructions store directly the argument in r14. */
717 w
= read_memory_integer (here
, insn_size
);
720 if (IS_COMPACT_IND_ARG_MOV (w
))
722 /* This must be followed by a store to r14, so the argument
723 is where the debug info says it is. This can happen after
724 the SP has been saved, unfortunately. */
726 int next_insn
= 0xffff & read_memory_integer (here
, insn_size
);
728 if (IS_COMPACT_MOV_TO_R14 (next_insn
))
731 else if (IS_COMPACT_ARG_MOV (w
))
733 /* These instructions store directly the argument in r14. */
736 else if (IS_MOVL_R0 (w
))
738 /* There is a function that gcc calls to get the arguments
739 passed correctly to the function. Only after this
740 function call the arguments will be found at the place
741 where they are supposed to be. This happens in case the
742 argument has to be stored into a 64-bit register (for
743 instance doubles, long longs). SHcompact doesn't have
744 access to the full 64-bits, so we store the register in
745 stack slot and store the address of the stack slot in
746 the register, then do a call through a wrapper that
747 loads the memory value into the register. A SHcompact
748 callee calls an argument decoder
749 (GCC_shcompact_incoming_args) that stores the 64-bit
750 value in a stack slot and stores the address of the
751 stack slot in the register. GCC thinks the argument is
752 just passed by transparent reference, but this is only
753 true after the argument decoder is called. Such a call
754 needs to be considered part of the prologue. */
756 /* This must be followed by a JSR @r0 instruction and by
757 a NOP instruction. After these, the prologue is over! */
759 int next_insn
= 0xffff & read_memory_integer (here
, insn_size
);
761 if (IS_JSR_R0 (next_insn
))
763 next_insn
= 0xffff & read_memory_integer (here
, insn_size
);
766 if (IS_NOP (next_insn
))
779 sh64_skip_prologue_hard_way (CORE_ADDR start_pc
)
789 if (pc_is_isa32 (start_pc
) == 0)
795 for (here
= start_pc
, end
= start_pc
+ (insn_size
* 28); here
< end
;)
800 int w
= read_memory_integer (UNMAKE_ISA32_ADDR (here
), insn_size
);
802 if (IS_STQ_R18_R14 (w
) || IS_STQ_R18_R15 (w
) || IS_STQ_R14_R15 (w
)
803 || IS_STL_R14_R15 (w
) || IS_STL_R18_R15 (w
)
804 || IS_ADDIL_SP_MEDIA (w
) || IS_ADDI_SP_MEDIA (w
) || IS_PTABSL_R18 (w
))
808 else if (IS_MOV_SP_FP (w
) || IS_MOV_SP_FP_MEDIA(w
))
816 /* Don't bail out yet, we may have arguments stored in
817 registers here, according to the debug info, so that
818 gdb can print the frames correctly. */
819 start_pc
= look_for_args_moves (here
- insn_size
, media_mode
);
825 int w
= 0xffff & read_memory_integer (here
, insn_size
);
828 if (IS_STS_R0 (w
) || IS_STS_PR (w
)
829 || IS_MOV_TO_R15 (w
) || IS_MOV_R14 (w
)
830 || IS_MOV_R0 (w
) || IS_ADD_SP_R0 (w
) || IS_MOV_R14_R0 (w
))
834 else if (IS_MOV_SP_FP (w
))
842 /* Don't bail out yet, we may have arguments stored in
843 registers here, according to the debug info, so that
844 gdb can print the frames correctly. */
845 start_pc
= look_for_args_moves (here
- insn_size
, media_mode
);
855 sh_skip_prologue (CORE_ADDR pc
)
857 CORE_ADDR post_prologue_pc
;
859 /* See if we can determine the end of the prologue via the symbol table.
860 If so, then return either PC, or the PC after the prologue, whichever
862 post_prologue_pc
= after_prologue (pc
);
864 /* If after_prologue returned a useful address, then use it. Else
865 fall back on the instruction skipping code. */
866 if (post_prologue_pc
!= 0)
867 return max (pc
, post_prologue_pc
);
869 return (skip_prologue_hard_way (pc
));
872 /* Immediately after a function call, return the saved pc.
873 Can't always go through the frames for this because on some machines
874 the new frame is not set up until the new function executes
877 The return address is the value saved in the PR register + 4 */
879 sh_saved_pc_after_call (struct frame_info
*frame
)
881 return (ADDR_BITS_REMOVE (read_register (gdbarch_tdep (current_gdbarch
)->PR_REGNUM
)));
884 /* Should call_function allocate stack space for a struct return? */
886 sh_use_struct_convention (int gcc_p
, struct type
*type
)
888 return (TYPE_LENGTH (type
) > 1);
892 sh64_use_struct_convention (int gcc_p
, struct type
*type
)
894 return (TYPE_LENGTH (type
) > 8);
897 /* Store the address of the place in which to copy the structure the
898 subroutine will return. This is called from call_function.
900 We store structs through a pointer passed in R2 */
902 sh_store_struct_return (CORE_ADDR addr
, CORE_ADDR sp
)
904 write_register (STRUCT_RETURN_REGNUM
, (addr
));
907 /* Disassemble an instruction. */
909 gdb_print_insn_sh (bfd_vma memaddr
, disassemble_info
*info
)
911 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
912 return print_insn_sh (memaddr
, info
);
914 return print_insn_shl (memaddr
, info
);
917 /* Disassemble an instruction. */
919 gdb_print_insn_sh64 (bfd_vma memaddr
, disassemble_info
*info
)
921 if (pc_is_isa32 (memaddr
))
923 /* Round down the instruction address to the appropriate boundary
924 before disassembling it. */
925 return print_insn_sh64x_media (UNMAKE_ISA32_ADDR (memaddr
), info
);
929 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
930 return print_insn_sh (memaddr
, info
);
932 return print_insn_shl (memaddr
, info
);
936 /* Given a GDB frame, determine the address of the calling function's frame.
937 This will be used to create a new GDB frame struct, and then
938 INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame.
940 For us, the frame address is its stack pointer value, so we look up
941 the function prologue to determine the caller's sp value, and return it. */
943 sh_frame_chain (struct frame_info
*frame
)
945 if (PC_IN_CALL_DUMMY (frame
->pc
, frame
->frame
, frame
->frame
))
946 return frame
->frame
; /* dummy frame same as caller's frame */
947 if (frame
->pc
&& !inside_entry_file (frame
->pc
))
948 return read_memory_integer (FRAME_FP (frame
) + frame
->extra_info
->f_offset
, 4);
953 /* Given a register number RN as it appears in an assembly
954 instruction, find the corresponding register number in the GDB
957 translate_insn_rn (int rn
, int media_mode
)
959 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
961 /* FIXME: this assumes that the number rn is for a not pseudo
967 /* These registers don't have a corresponding compact one. */
968 /* FIXME: This is probably not enough. */
970 if ((rn
>= 16 && rn
<= 63) || (rn
>= 93 && rn
<= 140))
973 if (rn
>= 0 && rn
<= tdep
->R0_C_REGNUM
)
974 return tdep
->R0_C_REGNUM
+ rn
;
981 sh64_frame_chain (struct frame_info
*frame
)
983 if (PC_IN_CALL_DUMMY (frame
->pc
, frame
->frame
, frame
->frame
))
984 return frame
->frame
; /* dummy frame same as caller's frame */
985 if (frame
->pc
&& !inside_entry_file (frame
->pc
))
987 int media_mode
= pc_is_isa32 (frame
->pc
);
989 if (gdbarch_tdep (current_gdbarch
)->sh_abi
== SH_ABI_32
)
992 size
= REGISTER_RAW_SIZE (translate_insn_rn (FP_REGNUM
, media_mode
));
993 return read_memory_integer (FRAME_FP (frame
) + frame
->extra_info
->f_offset
, size
);
999 /* Find REGNUM on the stack. Otherwise, it's in an active register. One thing
1000 we might want to do here is to check REGNUM against the clobber mask, and
1001 somehow flag it as invalid if it isn't saved on the stack somewhere. This
1002 would provide a graceful failure mode when trying to get the value of
1003 caller-saves registers for an inner frame. */
1005 sh_find_callers_reg (struct frame_info
*fi
, int regnum
)
1007 for (; fi
; fi
= fi
->next
)
1008 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
1009 /* When the caller requests PR from the dummy frame, we return PC because
1010 that's where the previous routine appears to have done a call from. */
1011 return generic_read_register_dummy (fi
->pc
, fi
->frame
, regnum
);
1014 FRAME_INIT_SAVED_REGS (fi
);
1017 if (fi
->saved_regs
[regnum
] != 0)
1018 return read_memory_integer (fi
->saved_regs
[regnum
],
1019 REGISTER_RAW_SIZE (regnum
));
1021 return read_register (regnum
);
1025 sh64_get_saved_pr (struct frame_info
*fi
, int pr_regnum
)
1029 for (; fi
; fi
= fi
->next
)
1030 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
1031 /* When the caller requests PR from the dummy frame, we return PC because
1032 that's where the previous routine appears to have done a call from. */
1033 return generic_read_register_dummy (fi
->pc
, fi
->frame
, pr_regnum
);
1036 FRAME_INIT_SAVED_REGS (fi
);
1040 media_mode
= pc_is_isa32 (fi
->pc
);
1042 if (fi
->saved_regs
[pr_regnum
] != 0)
1044 int gdb_reg_num
= translate_insn_rn (pr_regnum
, media_mode
);
1045 int size
= ((gdbarch_tdep (current_gdbarch
)->sh_abi
== SH_ABI_32
)
1047 : REGISTER_RAW_SIZE (gdb_reg_num
));
1048 return read_memory_integer (fi
->saved_regs
[pr_regnum
], size
);
1051 return read_register (pr_regnum
);
1054 /* Put here the code to store, into a struct frame_saved_regs, the
1055 addresses of the saved registers of frame described by FRAME_INFO.
1056 This includes special registers such as pc and fp saved in special
1057 ways in the stack frame. sp is even more special: the address we
1058 return for it IS the sp for the next frame. */
1060 sh_nofp_frame_init_saved_regs (struct frame_info
*fi
)
1062 int *where
= (int *) alloca ((NUM_REGS
+ NUM_PSEUDO_REGS
) * sizeof(int));
1070 char *dummy_regs
= generic_find_dummy_frame (fi
->pc
, fi
->frame
);
1072 if (fi
->saved_regs
== NULL
)
1073 frame_saved_regs_zalloc (fi
);
1075 memset (fi
->saved_regs
, 0, SIZEOF_FRAME_SAVED_REGS
);
1079 /* DANGER! This is ONLY going to work if the char buffer format of
1080 the saved registers is byte-for-byte identical to the
1081 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
1082 memcpy (fi
->saved_regs
, dummy_regs
, sizeof (fi
->saved_regs
));
1086 fi
->extra_info
->leaf_function
= 1;
1087 fi
->extra_info
->f_offset
= 0;
1089 for (rn
= 0; rn
< NUM_REGS
+ NUM_PSEUDO_REGS
; rn
++)
1094 /* Loop around examining the prologue insns until we find something
1095 that does not appear to be part of the prologue. But give up
1096 after 20 of them, since we're getting silly then. */
1098 pc
= get_pc_function_start (fi
->pc
);
1105 for (opc
= pc
+ (2 * 28); pc
< opc
; pc
+= 2)
1107 insn
= read_memory_integer (pc
, 2);
1108 /* See where the registers will be saved to */
1111 rn
= GET_PUSHED_REG (insn
);
1115 else if (IS_STS (insn
))
1117 where
[gdbarch_tdep (current_gdbarch
)->PR_REGNUM
] = depth
;
1118 /* If we're storing the pr then this isn't a leaf */
1119 fi
->extra_info
->leaf_function
= 0;
1122 else if (IS_MOV_R3 (insn
))
1124 r3_val
= ((insn
& 0xff) ^ 0x80) - 0x80;
1126 else if (IS_SHLL_R3 (insn
))
1130 else if (IS_ADD_R3SP (insn
))
1134 else if (IS_ADD_SP (insn
))
1136 depth
-= ((insn
& 0xff) ^ 0x80) - 0x80;
1138 else if (IS_MOV_SP_FP (insn
))
1140 #if 0 /* This used to just stop when it found an instruction that
1141 was not considered part of the prologue. Now, we just
1142 keep going looking for likely instructions. */
1148 /* Now we know how deep things are, we can work out their addresses */
1150 for (rn
= 0; rn
< NUM_REGS
+ NUM_PSEUDO_REGS
; rn
++)
1154 if (rn
== FP_REGNUM
)
1157 fi
->saved_regs
[rn
] = fi
->frame
- where
[rn
] + depth
- 4;
1161 fi
->saved_regs
[rn
] = 0;
1167 fi
->saved_regs
[SP_REGNUM
] = read_memory_integer (fi
->saved_regs
[FP_REGNUM
], 4);
1171 fi
->saved_regs
[SP_REGNUM
] = fi
->frame
- 4;
1174 fi
->extra_info
->f_offset
= depth
- where
[FP_REGNUM
] - 4;
1175 /* Work out the return pc - either from the saved pr or the pr
1179 /* For vectors of 4 floating point registers. */
1181 fv_reg_base_num (int fv_regnum
)
1185 fp_regnum
= FP0_REGNUM
+
1186 (fv_regnum
- gdbarch_tdep (current_gdbarch
)->FV0_REGNUM
) * 4;
1190 /* For double precision floating point registers, i.e 2 fp regs.*/
1192 dr_reg_base_num (int dr_regnum
)
1196 fp_regnum
= FP0_REGNUM
+
1197 (dr_regnum
- gdbarch_tdep (current_gdbarch
)->DR0_REGNUM
) * 2;
1201 /* For pairs of floating point registers */
1203 fpp_reg_base_num (int fpp_regnum
)
1207 fp_regnum
= FP0_REGNUM
+
1208 (fpp_regnum
- gdbarch_tdep (current_gdbarch
)->FPP0_REGNUM
) * 2;
1213 is_media_pseudo (int rn
)
1215 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1217 return (rn
>= tdep
->DR0_REGNUM
1218 && rn
<= tdep
->FV_LAST_REGNUM
);
1222 sh64_get_gdb_regnum (int gcc_regnum
, CORE_ADDR pc
)
1224 return translate_insn_rn (gcc_regnum
, pc_is_isa32 (pc
));
1228 sh64_media_reg_base_num (int reg_nr
)
1230 int base_regnum
= -1;
1231 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1233 if (reg_nr
>= tdep
->DR0_REGNUM
1234 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
1235 base_regnum
= dr_reg_base_num (reg_nr
);
1237 else if (reg_nr
>= tdep
->FPP0_REGNUM
1238 && reg_nr
<= tdep
->FPP_LAST_REGNUM
)
1239 base_regnum
= fpp_reg_base_num (reg_nr
);
1241 else if (reg_nr
>= tdep
->FV0_REGNUM
1242 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
1243 base_regnum
= fv_reg_base_num (reg_nr
);
1250 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
1251 GDB_REGNUM BASE_REGNUM
1311 sh64_compact_reg_base_num (int reg_nr
)
1313 int base_regnum
= -1;
1314 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1316 /* general register N maps to general register N */
1317 if (reg_nr
>= tdep
->R0_C_REGNUM
1318 && reg_nr
<= tdep
->R_LAST_C_REGNUM
)
1319 base_regnum
= reg_nr
- tdep
->R0_C_REGNUM
;
1321 /* floating point register N maps to floating point register N */
1322 else if (reg_nr
>= tdep
->FP0_C_REGNUM
1323 && reg_nr
<= tdep
->FP_LAST_C_REGNUM
)
1324 base_regnum
= reg_nr
- tdep
->FP0_C_REGNUM
+ FP0_REGNUM
;
1326 /* double prec register N maps to base regnum for double prec register N */
1327 else if (reg_nr
>= tdep
->DR0_C_REGNUM
1328 && reg_nr
<= tdep
->DR_LAST_C_REGNUM
)
1329 base_regnum
= dr_reg_base_num (tdep
->DR0_REGNUM
1330 + reg_nr
- tdep
->DR0_C_REGNUM
);
1332 /* vector N maps to base regnum for vector register N */
1333 else if (reg_nr
>= tdep
->FV0_C_REGNUM
1334 && reg_nr
<= tdep
->FV_LAST_C_REGNUM
)
1335 base_regnum
= fv_reg_base_num (tdep
->FV0_REGNUM
1336 + reg_nr
- tdep
->FV0_C_REGNUM
);
1338 else if (reg_nr
== tdep
->PC_C_REGNUM
)
1339 base_regnum
= PC_REGNUM
;
1341 else if (reg_nr
== tdep
->GBR_C_REGNUM
)
1344 else if (reg_nr
== tdep
->MACH_C_REGNUM
1345 || reg_nr
== tdep
->MACL_C_REGNUM
)
1348 else if (reg_nr
== tdep
->PR_C_REGNUM
)
1351 else if (reg_nr
== tdep
->T_C_REGNUM
)
1354 else if (reg_nr
== tdep
->FPSCR_C_REGNUM
)
1355 base_regnum
= tdep
->FPSCR_REGNUM
; /*???? this register is a mess. */
1357 else if (reg_nr
== tdep
->FPUL_C_REGNUM
)
1358 base_regnum
= FP0_REGNUM
+ 32;
1363 /* Given a register number RN (according to the gdb scheme) , return
1364 its corresponding architectural register. In media mode, only a
1365 subset of the registers is pseudo registers. For compact mode, all
1366 the registers are pseudo. */
1368 translate_rn_to_arch_reg_num (int rn
, int media_mode
)
1373 if (!is_media_pseudo (rn
))
1376 return sh64_media_reg_base_num (rn
);
1379 /* All compact registers are pseudo. */
1380 return sh64_compact_reg_base_num (rn
);
1384 sign_extend (int value
, int bits
)
1386 value
= value
& ((1 << bits
) - 1);
1387 return (value
& (1 << (bits
- 1))
1388 ? value
| (~((1 << bits
) - 1))
1393 sh64_nofp_frame_init_saved_regs (struct frame_info
*fi
)
1395 int *where
= (int *) alloca ((NUM_REGS
+ NUM_PSEUDO_REGS
) * sizeof (int));
1407 int gdb_register_number
;
1408 int register_number
;
1409 char *dummy_regs
= generic_find_dummy_frame (fi
->pc
, fi
->frame
);
1410 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1412 if (fi
->saved_regs
== NULL
)
1413 frame_saved_regs_zalloc (fi
);
1415 memset (fi
->saved_regs
, 0, SIZEOF_FRAME_SAVED_REGS
);
1419 /* DANGER! This is ONLY going to work if the char buffer format of
1420 the saved registers is byte-for-byte identical to the
1421 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
1422 memcpy (fi
->saved_regs
, dummy_regs
, sizeof (fi
->saved_regs
));
1426 fi
->extra_info
->leaf_function
= 1;
1427 fi
->extra_info
->f_offset
= 0;
1429 for (rn
= 0; rn
< NUM_REGS
+ NUM_PSEUDO_REGS
; rn
++)
1434 /* Loop around examining the prologue insns until we find something
1435 that does not appear to be part of the prologue. But give up
1436 after 20 of them, since we're getting silly then. */
1438 pc
= get_pc_function_start (fi
->pc
);
1445 if (pc_is_isa32 (pc
))
1456 /* The frame pointer register is general register 14 in shmedia and
1457 shcompact modes. In sh compact it is a pseudo register. Same goes
1458 for the stack pointer register, which is register 15. */
1459 fp_regnum
= translate_insn_rn (FP_REGNUM
, media_mode
);
1460 sp_regnum
= translate_insn_rn (SP_REGNUM
, media_mode
);
1462 for (opc
= pc
+ (insn_size
* 28); pc
< opc
; pc
+= insn_size
)
1464 insn
= read_memory_integer (media_mode
? UNMAKE_ISA32_ADDR (pc
) : pc
,
1467 if (media_mode
== 0)
1469 if (IS_STS_PR (insn
))
1471 int next_insn
= read_memory_integer (pc
+ insn_size
, insn_size
);
1472 if (IS_MOV_TO_R15 (next_insn
))
1474 int reg_nr
= tdep
->PR_C_REGNUM
;
1476 where
[reg_nr
] = depth
- ((((next_insn
& 0xf) ^ 0x8) - 0x8) << 2);
1477 fi
->extra_info
->leaf_function
= 0;
1481 else if (IS_MOV_R14 (insn
))
1483 where
[fp_regnum
] = depth
- ((((insn
& 0xf) ^ 0x8) - 0x8) << 2);
1486 else if (IS_MOV_R0 (insn
))
1488 /* Put in R0 the offset from SP at which to store some
1489 registers. We are interested in this value, because it
1490 will tell us where the given registers are stored within
1492 r0_val
= ((insn
& 0xff) ^ 0x80) - 0x80;
1494 else if (IS_ADD_SP_R0 (insn
))
1496 /* This instruction still prepares r0, but we don't care.
1497 We already have the offset in r0_val. */
1499 else if (IS_STS_R0 (insn
))
1501 /* Store PR at r0_val-4 from SP. Decrement r0 by 4*/
1502 int reg_nr
= tdep
->PR_C_REGNUM
;
1503 where
[reg_nr
] = depth
- (r0_val
- 4);
1505 fi
->extra_info
->leaf_function
= 0;
1507 else if (IS_MOV_R14_R0 (insn
))
1509 /* Store R14 at r0_val-4 from SP. Decrement r0 by 4 */
1510 where
[fp_regnum
] = depth
- (r0_val
- 4);
1514 else if (IS_ADD_SP (insn
))
1516 depth
-= ((insn
& 0xff) ^ 0x80) - 0x80;
1518 else if (IS_MOV_SP_FP (insn
))
1523 if (IS_ADDIL_SP_MEDIA (insn
)
1524 || IS_ADDI_SP_MEDIA (insn
))
1526 depth
-= sign_extend ((((insn
& 0xffc00) ^ 0x80000) - 0x80000) >> 10, 9);
1529 else if (IS_STQ_R18_R15 (insn
))
1531 where
[tdep
->PR_REGNUM
] =
1532 depth
- (sign_extend ((insn
& 0xffc00) >> 10, 9) << 3);
1533 fi
->extra_info
->leaf_function
= 0;
1536 else if (IS_STL_R18_R15 (insn
))
1538 where
[tdep
->PR_REGNUM
] =
1539 depth
- (sign_extend ((insn
& 0xffc00) >> 10, 9) << 2);
1540 fi
->extra_info
->leaf_function
= 0;
1543 else if (IS_STQ_R14_R15 (insn
))
1545 where
[fp_regnum
] = depth
- (sign_extend ((insn
& 0xffc00) >> 10, 9) << 3);
1548 else if (IS_STL_R14_R15 (insn
))
1550 where
[fp_regnum
] = depth
- (sign_extend ((insn
& 0xffc00) >> 10, 9) << 2);
1553 else if (IS_MOV_SP_FP_MEDIA (insn
))
1558 /* Now we know how deep things are, we can work out their addresses. */
1559 for (rn
= 0; rn
< NUM_REGS
+ NUM_PSEUDO_REGS
; rn
++)
1561 register_number
= translate_rn_to_arch_reg_num (rn
, media_mode
);
1565 if (rn
== fp_regnum
)
1568 /* Watch out! saved_regs is only for the real registers, and
1569 doesn't include space for the pseudo registers. */
1570 fi
->saved_regs
[register_number
]= fi
->frame
- where
[rn
] + depth
;
1574 fi
->saved_regs
[register_number
] = 0;
1579 /* SP_REGNUM is 15. For shmedia 15 is the real register. For
1580 shcompact 15 is the arch register corresponding to the pseudo
1581 register r15 which still is the SP register. */
1582 /* The place on the stack where fp is stored contains the sp of
1584 /* Again, saved_registers contains only space for the real registers,
1585 so we store in FP_REGNUM position. */
1587 if (tdep
->sh_abi
== SH_ABI_32
)
1590 size
= REGISTER_RAW_SIZE (fp_regnum
);
1591 fi
->saved_regs
[sp_regnum
] = read_memory_integer (fi
->saved_regs
[fp_regnum
], size
);
1594 fi
->saved_regs
[sp_regnum
] = fi
->frame
;
1596 fi
->extra_info
->f_offset
= depth
- where
[fp_regnum
];
1600 sh_fp_frame_init_saved_regs (struct frame_info
*fi
)
1602 int *where
= (int *) alloca ((NUM_REGS
+ NUM_PSEUDO_REGS
) * sizeof (int));
1610 char *dummy_regs
= generic_find_dummy_frame (fi
->pc
, fi
->frame
);
1611 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1613 if (fi
->saved_regs
== NULL
)
1614 frame_saved_regs_zalloc (fi
);
1616 memset (fi
->saved_regs
, 0, SIZEOF_FRAME_SAVED_REGS
);
1620 /* DANGER! This is ONLY going to work if the char buffer format of
1621 the saved registers is byte-for-byte identical to the
1622 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
1623 memcpy (fi
->saved_regs
, dummy_regs
, sizeof (fi
->saved_regs
));
1627 fi
->extra_info
->leaf_function
= 1;
1628 fi
->extra_info
->f_offset
= 0;
1630 for (rn
= 0; rn
< NUM_REGS
+ NUM_PSEUDO_REGS
; rn
++)
1635 /* Loop around examining the prologue insns until we find something
1636 that does not appear to be part of the prologue. But give up
1637 after 20 of them, since we're getting silly then. */
1639 pc
= get_pc_function_start (fi
->pc
);
1646 for (opc
= pc
+ (2 * 28); pc
< opc
; pc
+= 2)
1648 insn
= read_memory_integer (pc
, 2);
1649 /* See where the registers will be saved to */
1652 rn
= GET_PUSHED_REG (insn
);
1656 else if (IS_STS (insn
))
1658 where
[tdep
->PR_REGNUM
] = depth
;
1659 /* If we're storing the pr then this isn't a leaf */
1660 fi
->extra_info
->leaf_function
= 0;
1663 else if (IS_MOV_R3 (insn
))
1665 r3_val
= ((insn
& 0xff) ^ 0x80) - 0x80;
1667 else if (IS_SHLL_R3 (insn
))
1671 else if (IS_ADD_R3SP (insn
))
1675 else if (IS_ADD_SP (insn
))
1677 depth
-= ((insn
& 0xff) ^ 0x80) - 0x80;
1679 else if (IS_FMOV (insn
))
1681 if (read_register (tdep
->FPSCR_REGNUM
) & FPSCR_SZ
)
1690 else if (IS_MOV_SP_FP (insn
))
1692 #if 0 /* This used to just stop when it found an instruction that
1693 was not considered part of the prologue. Now, we just
1694 keep going looking for likely instructions. */
1700 /* Now we know how deep things are, we can work out their addresses */
1702 for (rn
= 0; rn
< NUM_REGS
+ NUM_PSEUDO_REGS
; rn
++)
1706 if (rn
== FP_REGNUM
)
1709 fi
->saved_regs
[rn
] = fi
->frame
- where
[rn
] + depth
- 4;
1713 fi
->saved_regs
[rn
] = 0;
1719 fi
->saved_regs
[SP_REGNUM
] =
1720 read_memory_integer (fi
->saved_regs
[FP_REGNUM
], 4);
1724 fi
->saved_regs
[SP_REGNUM
] = fi
->frame
- 4;
1727 fi
->extra_info
->f_offset
= depth
- where
[FP_REGNUM
] - 4;
1728 /* Work out the return pc - either from the saved pr or the pr
1732 /* Initialize the extra info saved in a FRAME */
1734 sh_init_extra_frame_info (int fromleaf
, struct frame_info
*fi
)
1737 fi
->extra_info
= (struct frame_extra_info
*)
1738 frame_obstack_alloc (sizeof (struct frame_extra_info
));
1741 fi
->pc
= FRAME_SAVED_PC (fi
->next
);
1743 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
1745 /* We need to setup fi->frame here because run_stack_dummy gets it wrong
1746 by assuming it's always FP. */
1747 fi
->frame
= generic_read_register_dummy (fi
->pc
, fi
->frame
,
1749 fi
->extra_info
->return_pc
= generic_read_register_dummy (fi
->pc
,
1752 fi
->extra_info
->f_offset
= -(CALL_DUMMY_LENGTH
+ 4);
1753 fi
->extra_info
->leaf_function
= 0;
1758 FRAME_INIT_SAVED_REGS (fi
);
1759 fi
->extra_info
->return_pc
=
1760 sh_find_callers_reg (fi
, gdbarch_tdep (current_gdbarch
)->PR_REGNUM
);
1765 sh64_init_extra_frame_info (int fromleaf
, struct frame_info
*fi
)
1767 int media_mode
= pc_is_isa32 (fi
->pc
);
1769 fi
->extra_info
= (struct frame_extra_info
*)
1770 frame_obstack_alloc (sizeof (struct frame_extra_info
));
1773 fi
->pc
= FRAME_SAVED_PC (fi
->next
);
1775 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
1777 /* We need to setup fi->frame here because run_stack_dummy gets it wrong
1778 by assuming it's always FP. */
1779 fi
->frame
= generic_read_register_dummy (fi
->pc
, fi
->frame
,
1781 fi
->extra_info
->return_pc
=
1782 generic_read_register_dummy (fi
->pc
, fi
->frame
, PC_REGNUM
);
1783 fi
->extra_info
->f_offset
= -(CALL_DUMMY_LENGTH
+ 4);
1784 fi
->extra_info
->leaf_function
= 0;
1789 FRAME_INIT_SAVED_REGS (fi
);
1790 fi
->extra_info
->return_pc
=
1791 sh64_get_saved_pr (fi
, gdbarch_tdep (current_gdbarch
)->PR_REGNUM
);
1796 sh64_get_saved_register (char *raw_buffer
, int *optimized
, CORE_ADDR
*addrp
,
1797 struct frame_info
*frame
, int regnum
,
1798 enum lval_type
*lval
)
1801 int live_regnum
= regnum
;
1802 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1804 if (!target_has_registers
)
1805 error ("No registers.");
1807 /* Normal systems don't optimize out things with register numbers. */
1808 if (optimized
!= NULL
)
1811 if (addrp
) /* default assumption: not found in memory */
1815 memset (raw_buffer
, 0, sizeof (raw_buffer
));
1817 /* We must do this here, before the following while loop changes
1818 frame, and makes it NULL. If this is a media register number,
1819 but we are in compact mode, it will become the corresponding
1820 compact pseudo register. If there is no corresponding compact
1821 pseudo-register what do we do?*/
1822 media_mode
= pc_is_isa32 (frame
->pc
);
1823 live_regnum
= translate_insn_rn (regnum
, media_mode
);
1825 /* Note: since the current frame's registers could only have been
1826 saved by frames INTERIOR TO the current frame, we skip examining
1827 the current frame itself: otherwise, we would be getting the
1828 previous frame's registers which were saved by the current frame. */
1830 while (frame
&& ((frame
= frame
->next
) != NULL
))
1832 if (PC_IN_CALL_DUMMY (frame
->pc
, frame
->frame
, frame
->frame
))
1834 if (lval
) /* found it in a CALL_DUMMY frame */
1838 generic_find_dummy_frame (frame
->pc
, frame
->frame
) +
1839 REGISTER_BYTE (regnum
),
1840 REGISTER_RAW_SIZE (regnum
));
1844 FRAME_INIT_SAVED_REGS (frame
);
1845 if (frame
->saved_regs
!= NULL
1846 && frame
->saved_regs
[regnum
] != 0)
1848 if (lval
) /* found it saved on the stack */
1849 *lval
= lval_memory
;
1850 if (regnum
== SP_REGNUM
)
1852 if (raw_buffer
) /* SP register treated specially */
1853 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
),
1854 frame
->saved_regs
[regnum
]);
1857 { /* any other register */
1860 *addrp
= frame
->saved_regs
[regnum
];
1864 if (tdep
->sh_abi
== SH_ABI_32
1865 && (live_regnum
== FP_REGNUM
1866 || live_regnum
== tdep
->PR_REGNUM
))
1869 size
= REGISTER_RAW_SIZE (live_regnum
);
1870 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
1871 read_memory (frame
->saved_regs
[regnum
], raw_buffer
, size
);
1873 read_memory (frame
->saved_regs
[regnum
],
1875 + REGISTER_RAW_SIZE (live_regnum
)
1884 /* If we get thru the loop to this point, it means the register was
1885 not saved in any frame. Return the actual live-register value. */
1887 if (lval
) /* found it in a live register */
1888 *lval
= lval_register
;
1890 *addrp
= REGISTER_BYTE (live_regnum
);
1892 read_register_gen (live_regnum
, raw_buffer
);
1895 /* Extract from an array REGBUF containing the (raw) register state
1896 the address in which a function should return its structure value,
1897 as a CORE_ADDR (or an expression that can be used as one). */
1899 sh_extract_struct_value_address (char *regbuf
)
1901 return (extract_address ((regbuf
), REGISTER_RAW_SIZE (0)));
1905 sh64_extract_struct_value_address (char *regbuf
)
1907 return (extract_address ((regbuf
+ REGISTER_BYTE (STRUCT_RETURN_REGNUM
)),
1908 REGISTER_RAW_SIZE (STRUCT_RETURN_REGNUM
)));
1912 sh_frame_saved_pc (struct frame_info
*frame
)
1914 return ((frame
)->extra_info
->return_pc
);
1917 /* Discard from the stack the innermost frame,
1918 restoring all saved registers. */
1922 register struct frame_info
*frame
= get_current_frame ();
1923 register CORE_ADDR fp
;
1924 register int regnum
;
1926 if (PC_IN_CALL_DUMMY (frame
->pc
, frame
->frame
, frame
->frame
))
1927 generic_pop_dummy_frame ();
1930 fp
= FRAME_FP (frame
);
1931 FRAME_INIT_SAVED_REGS (frame
);
1933 /* Copy regs from where they were saved in the frame */
1934 for (regnum
= 0; regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
1935 if (frame
->saved_regs
[regnum
])
1936 write_register (regnum
,
1937 read_memory_integer (frame
->saved_regs
[regnum
], 4));
1939 write_register (PC_REGNUM
, frame
->extra_info
->return_pc
);
1940 write_register (SP_REGNUM
, fp
+ 4);
1942 flush_cached_frames ();
1945 /* Used in the 'return' command. */
1947 sh64_pop_frame (void)
1949 register struct frame_info
*frame
= get_current_frame ();
1950 register CORE_ADDR fp
;
1951 register int regnum
;
1952 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1954 int media_mode
= pc_is_isa32 (frame
->pc
);
1956 if (PC_IN_CALL_DUMMY (frame
->pc
, frame
->frame
, frame
->frame
))
1957 generic_pop_dummy_frame ();
1960 fp
= FRAME_FP (frame
);
1961 FRAME_INIT_SAVED_REGS (frame
);
1963 /* Copy regs from where they were saved in the frame */
1964 for (regnum
= 0; regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
1965 if (frame
->saved_regs
[regnum
])
1968 if (tdep
->sh_abi
== SH_ABI_32
1969 && (regnum
== FP_REGNUM
1970 || regnum
== tdep
->PR_REGNUM
))
1973 size
= REGISTER_RAW_SIZE (translate_insn_rn (regnum
,
1975 write_register (regnum
,
1976 read_memory_integer (frame
->saved_regs
[regnum
],
1980 write_register (PC_REGNUM
, frame
->extra_info
->return_pc
);
1981 write_register (SP_REGNUM
, fp
+ 8);
1983 flush_cached_frames ();
1986 /* Function: push_arguments
1987 Setup the function arguments for calling a function in the inferior.
1989 On the Hitachi SH architecture, there are four registers (R4 to R7)
1990 which are dedicated for passing function arguments. Up to the first
1991 four arguments (depending on size) may go into these registers.
1992 The rest go on the stack.
1994 Arguments that are smaller than 4 bytes will still take up a whole
1995 register or a whole 32-bit word on the stack, and will be
1996 right-justified in the register or the stack word. This includes
1997 chars, shorts, and small aggregate types.
1999 Arguments that are larger than 4 bytes may be split between two or
2000 more registers. If there are not enough registers free, an argument
2001 may be passed partly in a register (or registers), and partly on the
2002 stack. This includes doubles, long longs, and larger aggregates.
2003 As far as I know, there is no upper limit to the size of aggregates
2004 that will be passed in this way; in other words, the convention of
2005 passing a pointer to a large aggregate instead of a copy is not used.
2007 An exceptional case exists for struct arguments (and possibly other
2008 aggregates such as arrays) if the size is larger than 4 bytes but
2009 not a multiple of 4 bytes. In this case the argument is never split
2010 between the registers and the stack, but instead is copied in its
2011 entirety onto the stack, AND also copied into as many registers as
2012 there is room for. In other words, space in registers permitting,
2013 two copies of the same argument are passed in. As far as I can tell,
2014 only the one on the stack is used, although that may be a function
2015 of the level of compiler optimization. I suspect this is a compiler
2016 bug. Arguments of these odd sizes are left-justified within the
2017 word (as opposed to arguments smaller than 4 bytes, which are
2020 If the function is to return an aggregate type such as a struct, it
2021 is either returned in the normal return value register R0 (if its
2022 size is no greater than one byte), or else the caller must allocate
2023 space into which the callee will copy the return value (if the size
2024 is greater than one byte). In this case, a pointer to the return
2025 value location is passed into the callee in register R2, which does
2026 not displace any of the other arguments passed in via registers R4
2030 sh_push_arguments (int nargs
, struct value
**args
, CORE_ADDR sp
,
2031 int struct_return
, CORE_ADDR struct_addr
)
2033 int stack_offset
, stack_alloc
;
2041 int odd_sized_struct
;
2042 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2044 /* first force sp to a 4-byte alignment */
2047 /* The "struct return pointer" pseudo-argument has its own dedicated
2050 write_register (STRUCT_RETURN_REGNUM
, struct_addr
);
2052 /* Now make sure there's space on the stack */
2053 for (argnum
= 0, stack_alloc
= 0; argnum
< nargs
; argnum
++)
2054 stack_alloc
+= ((TYPE_LENGTH (VALUE_TYPE (args
[argnum
])) + 3) & ~3);
2055 sp
-= stack_alloc
; /* make room on stack for args */
2057 /* Now load as many as possible of the first arguments into
2058 registers, and push the rest onto the stack. There are 16 bytes
2059 in four registers available. Loop thru args from first to last. */
2061 argreg
= tdep
->ARG0_REGNUM
;
2062 for (argnum
= 0, stack_offset
= 0; argnum
< nargs
; argnum
++)
2064 type
= VALUE_TYPE (args
[argnum
]);
2065 len
= TYPE_LENGTH (type
);
2066 memset (valbuf
, 0, sizeof (valbuf
));
2069 /* value gets right-justified in the register or stack word */
2070 memcpy (valbuf
+ (4 - len
),
2071 (char *) VALUE_CONTENTS (args
[argnum
]), len
);
2075 val
= (char *) VALUE_CONTENTS (args
[argnum
]);
2077 if (len
> 4 && (len
& 3) != 0)
2078 odd_sized_struct
= 1; /* such structs go entirely on stack */
2080 odd_sized_struct
= 0;
2083 if (argreg
> tdep
->ARGLAST_REGNUM
2084 || odd_sized_struct
)
2086 /* must go on the stack */
2087 write_memory (sp
+ stack_offset
, val
, 4);
2090 /* NOTE WELL!!!!! This is not an "else if" clause!!!
2091 That's because some *&^%$ things get passed on the stack
2092 AND in the registers! */
2093 if (argreg
<= tdep
->ARGLAST_REGNUM
)
2095 /* there's room in a register */
2096 regval
= extract_address (val
, REGISTER_RAW_SIZE (argreg
));
2097 write_register (argreg
++, regval
);
2099 /* Store the value 4 bytes at a time. This means that things
2100 larger than 4 bytes may go partly in registers and partly
2102 len
-= REGISTER_RAW_SIZE (argreg
);
2103 val
+= REGISTER_RAW_SIZE (argreg
);
2109 /* R2-R9 for integer types and integer equivalent (char, pointers) and
2110 non-scalar (struct, union) elements (even if the elements are
2112 FR0-FR11 for single precision floating point (float)
2113 DR0-DR10 for double precision floating point (double)
2115 If a float is argument number 3 (for instance) and arguments number
2116 1,2, and 4 are integer, the mapping will be:
2117 arg1 -->R2, arg2 --> R3, arg3 -->FR0, arg4 --> R5. I.e. R4 is not used.
2119 If a float is argument number 10 (for instance) and arguments number
2120 1 through 10 are integer, the mapping will be:
2121 arg1->R2, arg2->R3, arg3->R4, arg4->R5, arg5->R6, arg6->R7, arg7->R8,
2122 arg8->R9, arg9->(0,SP)stack(8-byte aligned), arg10->FR0, arg11->stack(16,SP).
2123 I.e. there is hole in the stack.
2125 Different rules apply for variable arguments functions, and for functions
2126 for which the prototype is not known. */
2129 sh64_push_arguments (int nargs
, struct value
**args
, CORE_ADDR sp
,
2130 int struct_return
, CORE_ADDR struct_addr
)
2132 int stack_offset
, stack_alloc
;
2136 int float_arg_index
= 0;
2137 int double_arg_index
= 0;
2147 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2149 memset (fp_args
, 0, sizeof (fp_args
));
2151 /* first force sp to a 8-byte alignment */
2154 /* The "struct return pointer" pseudo-argument has its own dedicated
2158 write_register (STRUCT_RETURN_REGNUM
, struct_addr
);
2160 /* Now make sure there's space on the stack */
2161 for (argnum
= 0, stack_alloc
= 0; argnum
< nargs
; argnum
++)
2162 stack_alloc
+= ((TYPE_LENGTH (VALUE_TYPE (args
[argnum
])) + 7) & ~7);
2163 sp
-= stack_alloc
; /* make room on stack for args */
2165 /* Now load as many as possible of the first arguments into
2166 registers, and push the rest onto the stack. There are 64 bytes
2167 in eight registers available. Loop thru args from first to last. */
2169 int_argreg
= tdep
->ARG0_REGNUM
;
2170 float_argreg
= FP0_REGNUM
;
2171 double_argreg
= tdep
->DR0_REGNUM
;
2173 for (argnum
= 0, stack_offset
= 0; argnum
< nargs
; argnum
++)
2175 type
= VALUE_TYPE (args
[argnum
]);
2176 len
= TYPE_LENGTH (type
);
2177 memset (valbuf
, 0, sizeof (valbuf
));
2179 if (TYPE_CODE (type
) != TYPE_CODE_FLT
)
2181 argreg_size
= REGISTER_RAW_SIZE (int_argreg
);
2183 if (len
< argreg_size
)
2185 /* value gets right-justified in the register or stack word */
2186 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2187 memcpy (valbuf
+ argreg_size
- len
,
2188 (char *) VALUE_CONTENTS (args
[argnum
]), len
);
2190 memcpy (valbuf
, (char *) VALUE_CONTENTS (args
[argnum
]), len
);
2195 val
= (char *) VALUE_CONTENTS (args
[argnum
]);
2199 if (int_argreg
> tdep
->ARGLAST_REGNUM
)
2201 /* must go on the stack */
2202 write_memory (sp
+ stack_offset
, val
, argreg_size
);
2203 stack_offset
+= 8;/*argreg_size;*/
2205 /* NOTE WELL!!!!! This is not an "else if" clause!!!
2206 That's because some *&^%$ things get passed on the stack
2207 AND in the registers! */
2208 if (int_argreg
<= tdep
->ARGLAST_REGNUM
)
2210 /* there's room in a register */
2211 regval
= extract_address (val
, argreg_size
);
2212 write_register (int_argreg
, regval
);
2214 /* Store the value 8 bytes at a time. This means that
2215 things larger than 8 bytes may go partly in registers
2216 and partly on the stack. FIXME: argreg is incremented
2217 before we use its size. */
2225 val
= (char *) VALUE_CONTENTS (args
[argnum
]);
2228 /* Where is it going to be stored? */
2229 while (fp_args
[float_arg_index
])
2232 /* Now float_argreg points to the register where it
2233 should be stored. Are we still within the allowed
2235 if (float_arg_index
<= tdep
->FLOAT_ARGLAST_REGNUM
)
2237 /* Goes in FR0...FR11 */
2238 write_register_gen (FP0_REGNUM
+ float_arg_index
, val
);
2239 fp_args
[float_arg_index
] = 1;
2240 /* Skip the corresponding general argument register. */
2245 /* Store it as the integers, 8 bytes at the time, if
2246 necessary spilling on the stack. */
2251 /* Where is it going to be stored? */
2252 while (fp_args
[double_arg_index
])
2253 double_arg_index
+= 2;
2254 /* Now double_argreg points to the register
2255 where it should be stored.
2256 Are we still within the allowed register set? */
2257 if (double_arg_index
< tdep
->FLOAT_ARGLAST_REGNUM
)
2259 /* Goes in DR0...DR10 */
2260 /* The numbering of the DRi registers is consecutive,
2261 i.e. includes odd numbers. */
2262 int double_register_offset
= double_arg_index
/ 2;
2263 int regnum
= tdep
->DR0_REGNUM
+
2264 double_register_offset
;
2266 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
2268 memset (valbuf_tmp
, 0, sizeof (valbuf_tmp
));
2269 REGISTER_CONVERT_TO_VIRTUAL (regnum
,
2270 type
, val
, valbuf_tmp
);
2274 /* Note: must use write_register_gen here instead
2275 of regcache_write, because regcache_write works
2276 only for real registers, not pseudo.
2277 write_register_gen will call the gdbarch
2278 function to do register writes, and that will
2279 properly know how to deal with pseudoregs. */
2280 write_register_gen (regnum
, val
);
2281 fp_args
[double_arg_index
] = 1;
2282 fp_args
[double_arg_index
+ 1] = 1;
2283 /* Skip the corresponding general argument register. */
2288 /* Store it as the integers, 8 bytes at the time, if
2289 necessary spilling on the stack. */
2296 /* Function: push_return_address (pc)
2297 Set up the return address for the inferior function call.
2298 Needed for targets where we don't actually execute a JSR/BSR instruction */
2301 sh_push_return_address (CORE_ADDR pc
, CORE_ADDR sp
)
2303 write_register (gdbarch_tdep (current_gdbarch
)->PR_REGNUM
,
2304 CALL_DUMMY_ADDRESS ());
2308 /* Function: fix_call_dummy
2309 Poke the callee function's address into the destination part of
2310 the CALL_DUMMY. The address is actually stored in a data word
2311 following the actualy CALL_DUMMY instructions, which will load
2312 it into a register using PC-relative addressing. This function
2313 expects the CALL_DUMMY to look like this:
2324 sh_fix_call_dummy (char *dummy
, CORE_ADDR pc
, CORE_ADDR fun
, int nargs
,
2325 struct value
**args
, struct type
*type
, int gcc_p
)
2327 *(unsigned long *) (dummy
+ 8) = fun
;
2332 sh_coerce_float_to_double (struct type
*formal
, struct type
*actual
)
2337 /* Find a function's return value in the appropriate registers (in
2338 regbuf), and copy it into valbuf. Extract from an array REGBUF
2339 containing the (raw) register state a function return value of type
2340 TYPE, and copy that, in virtual format, into VALBUF. */
2342 sh_extract_return_value (struct type
*type
, char *regbuf
, char *valbuf
)
2344 int len
= TYPE_LENGTH (type
);
2345 int return_register
= R0_REGNUM
;
2350 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2351 offset
= REGISTER_BYTE (return_register
) + 4 - len
;
2353 offset
= REGISTER_BYTE (return_register
);
2354 memcpy (valbuf
, regbuf
+ offset
, len
);
2358 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2359 offset
= REGISTER_BYTE (return_register
) + 8 - len
;
2361 offset
= REGISTER_BYTE (return_register
);
2362 memcpy (valbuf
, regbuf
+ offset
, len
);
2365 error ("bad size for return value");
2369 sh3e_sh4_extract_return_value (struct type
*type
, char *regbuf
, char *valbuf
)
2371 int return_register
;
2373 int len
= TYPE_LENGTH (type
);
2375 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2376 return_register
= FP0_REGNUM
;
2378 return_register
= R0_REGNUM
;
2380 if (len
== 8 && TYPE_CODE (type
) == TYPE_CODE_FLT
)
2383 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
2384 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword
,
2385 (char *) regbuf
+ REGISTER_BYTE (return_register
),
2388 floatformat_to_doublest (&floatformat_ieee_double_big
,
2389 (char *) regbuf
+ REGISTER_BYTE (return_register
),
2391 store_floating (valbuf
, len
, val
);
2395 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2396 offset
= REGISTER_BYTE (return_register
) + 4 - len
;
2398 offset
= REGISTER_BYTE (return_register
);
2399 memcpy (valbuf
, regbuf
+ offset
, len
);
2403 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2404 offset
= REGISTER_BYTE (return_register
) + 8 - len
;
2406 offset
= REGISTER_BYTE (return_register
);
2407 memcpy (valbuf
, regbuf
+ offset
, len
);
2410 error ("bad size for return value");
2414 sh64_extract_return_value (struct type
*type
, char *regbuf
, char *valbuf
)
2417 int return_register
;
2418 int len
= TYPE_LENGTH (type
);
2419 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2421 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2425 /* Return value stored in FP0_REGNUM */
2426 return_register
= FP0_REGNUM
;
2427 offset
= REGISTER_BYTE (return_register
);
2428 memcpy (valbuf
, (char *) regbuf
+ offset
, len
);
2432 /* return value stored in DR0_REGNUM */
2435 return_register
= tdep
->DR0_REGNUM
;
2436 offset
= REGISTER_BYTE (return_register
);
2438 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
2439 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword
,
2440 (char *) regbuf
+ offset
, &val
);
2442 floatformat_to_doublest (&floatformat_ieee_double_big
,
2443 (char *) regbuf
+ offset
, &val
);
2444 store_floating (valbuf
, len
, val
);
2451 /* Result is in register 2. If smaller than 8 bytes, it is padded
2452 at the most significant end. */
2453 return_register
= tdep
->RETURN_REGNUM
;
2454 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2455 offset
= REGISTER_BYTE (return_register
) +
2456 REGISTER_RAW_SIZE (return_register
) - len
;
2458 offset
= REGISTER_BYTE (return_register
);
2459 memcpy (valbuf
, (char *) regbuf
+ offset
, len
);
2462 error ("bad size for return value");
2466 /* Write into appropriate registers a function return value
2467 of type TYPE, given in virtual format.
2468 If the architecture is sh4 or sh3e, store a function's return value
2469 in the R0 general register or in the FP0 floating point register,
2470 depending on the type of the return value. In all the other cases
2471 the result is stored in r0, left-justified. */
2473 sh_default_store_return_value (struct type
*type
, char *valbuf
)
2475 char buf
[32]; /* more than enough... */
2477 if (TYPE_LENGTH (type
) < REGISTER_RAW_SIZE (R0_REGNUM
))
2479 /* Add leading zeros to the value. */
2480 memset (buf
, 0, REGISTER_RAW_SIZE (R0_REGNUM
));
2481 memcpy (buf
+ REGISTER_RAW_SIZE (R0_REGNUM
) - TYPE_LENGTH (type
),
2482 valbuf
, TYPE_LENGTH (type
));
2483 write_register_bytes (REGISTER_BYTE (R0_REGNUM
), buf
,
2484 REGISTER_RAW_SIZE (R0_REGNUM
));
2487 write_register_bytes (REGISTER_BYTE (R0_REGNUM
), valbuf
,
2488 TYPE_LENGTH (type
));
2492 sh3e_sh4_store_return_value (struct type
*type
, char *valbuf
)
2494 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2495 write_register_bytes (REGISTER_BYTE (FP0_REGNUM
),
2496 valbuf
, TYPE_LENGTH (type
));
2498 sh_default_store_return_value (type
, valbuf
);
2502 sh64_store_return_value (struct type
*type
, char *valbuf
)
2504 char buf
[64]; /* more than enough... */
2505 int len
= TYPE_LENGTH (type
);
2507 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2511 /* Return value stored in FP0_REGNUM */
2512 write_register_gen (FP0_REGNUM
, valbuf
);
2516 /* return value stored in DR0_REGNUM */
2517 /* FIXME: Implement */
2522 int return_register
= gdbarch_tdep (current_gdbarch
)->RETURN_REGNUM
;
2525 if (len
<= REGISTER_RAW_SIZE (return_register
))
2527 /* Pad with zeros. */
2528 memset (buf
, 0, REGISTER_RAW_SIZE (return_register
));
2529 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
2530 offset
= 0; /*REGISTER_RAW_SIZE (return_register) - len;*/
2532 offset
= REGISTER_RAW_SIZE (return_register
) - len
;
2534 memcpy (buf
+ offset
, valbuf
, len
);
2535 write_register_gen (return_register
, buf
);
2538 write_register_gen (return_register
, valbuf
);
2542 /* Print the registers in a form similar to the E7000 */
2545 sh_generic_show_regs (void)
2547 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2549 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2550 paddr (read_register (PC_REGNUM
)),
2551 (long) read_register (tdep
->SR_REGNUM
),
2552 (long) read_register (tdep
->PR_REGNUM
),
2553 (long) read_register (MACH_REGNUM
),
2554 (long) read_register (MACL_REGNUM
));
2556 printf_filtered ("GBR=%08lx VBR=%08lx",
2557 (long) read_register (GBR_REGNUM
),
2558 (long) read_register (VBR_REGNUM
));
2560 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2561 (long) read_register (0),
2562 (long) read_register (1),
2563 (long) read_register (2),
2564 (long) read_register (3),
2565 (long) read_register (4),
2566 (long) read_register (5),
2567 (long) read_register (6),
2568 (long) read_register (7));
2569 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2570 (long) read_register (8),
2571 (long) read_register (9),
2572 (long) read_register (10),
2573 (long) read_register (11),
2574 (long) read_register (12),
2575 (long) read_register (13),
2576 (long) read_register (14),
2577 (long) read_register (15));
2581 sh3_show_regs (void)
2583 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2585 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2586 paddr (read_register (PC_REGNUM
)),
2587 (long) read_register (tdep
->SR_REGNUM
),
2588 (long) read_register (tdep
->PR_REGNUM
),
2589 (long) read_register (MACH_REGNUM
),
2590 (long) read_register (MACL_REGNUM
));
2592 printf_filtered ("GBR=%08lx VBR=%08lx",
2593 (long) read_register (GBR_REGNUM
),
2594 (long) read_register (VBR_REGNUM
));
2595 printf_filtered (" SSR=%08lx SPC=%08lx",
2596 (long) read_register (tdep
->SSR_REGNUM
),
2597 (long) read_register (tdep
->SPC_REGNUM
));
2599 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2600 (long) read_register (0),
2601 (long) read_register (1),
2602 (long) read_register (2),
2603 (long) read_register (3),
2604 (long) read_register (4),
2605 (long) read_register (5),
2606 (long) read_register (6),
2607 (long) read_register (7));
2608 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2609 (long) read_register (8),
2610 (long) read_register (9),
2611 (long) read_register (10),
2612 (long) read_register (11),
2613 (long) read_register (12),
2614 (long) read_register (13),
2615 (long) read_register (14),
2616 (long) read_register (15));
2621 sh3e_show_regs (void)
2623 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2625 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2626 paddr (read_register (PC_REGNUM
)),
2627 (long) read_register (tdep
->SR_REGNUM
),
2628 (long) read_register (tdep
->PR_REGNUM
),
2629 (long) read_register (MACH_REGNUM
),
2630 (long) read_register (MACL_REGNUM
));
2632 printf_filtered ("GBR=%08lx VBR=%08lx",
2633 (long) read_register (GBR_REGNUM
),
2634 (long) read_register (VBR_REGNUM
));
2635 printf_filtered (" SSR=%08lx SPC=%08lx",
2636 (long) read_register (tdep
->SSR_REGNUM
),
2637 (long) read_register (tdep
->SPC_REGNUM
));
2638 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
2639 (long) read_register (tdep
->FPUL_REGNUM
),
2640 (long) read_register (tdep
->FPSCR_REGNUM
));
2642 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2643 (long) read_register (0),
2644 (long) read_register (1),
2645 (long) read_register (2),
2646 (long) read_register (3),
2647 (long) read_register (4),
2648 (long) read_register (5),
2649 (long) read_register (6),
2650 (long) read_register (7));
2651 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2652 (long) read_register (8),
2653 (long) read_register (9),
2654 (long) read_register (10),
2655 (long) read_register (11),
2656 (long) read_register (12),
2657 (long) read_register (13),
2658 (long) read_register (14),
2659 (long) read_register (15));
2661 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2662 (long) read_register (FP0_REGNUM
+ 0),
2663 (long) read_register (FP0_REGNUM
+ 1),
2664 (long) read_register (FP0_REGNUM
+ 2),
2665 (long) read_register (FP0_REGNUM
+ 3),
2666 (long) read_register (FP0_REGNUM
+ 4),
2667 (long) read_register (FP0_REGNUM
+ 5),
2668 (long) read_register (FP0_REGNUM
+ 6),
2669 (long) read_register (FP0_REGNUM
+ 7));
2670 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2671 (long) read_register (FP0_REGNUM
+ 8),
2672 (long) read_register (FP0_REGNUM
+ 9),
2673 (long) read_register (FP0_REGNUM
+ 10),
2674 (long) read_register (FP0_REGNUM
+ 11),
2675 (long) read_register (FP0_REGNUM
+ 12),
2676 (long) read_register (FP0_REGNUM
+ 13),
2677 (long) read_register (FP0_REGNUM
+ 14),
2678 (long) read_register (FP0_REGNUM
+ 15));
2682 sh3_dsp_show_regs (void)
2684 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2686 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2687 paddr (read_register (PC_REGNUM
)),
2688 (long) read_register (tdep
->SR_REGNUM
),
2689 (long) read_register (tdep
->PR_REGNUM
),
2690 (long) read_register (MACH_REGNUM
),
2691 (long) read_register (MACL_REGNUM
));
2693 printf_filtered ("GBR=%08lx VBR=%08lx",
2694 (long) read_register (GBR_REGNUM
),
2695 (long) read_register (VBR_REGNUM
));
2697 printf_filtered (" SSR=%08lx SPC=%08lx",
2698 (long) read_register (tdep
->SSR_REGNUM
),
2699 (long) read_register (tdep
->SPC_REGNUM
));
2701 printf_filtered (" DSR=%08lx",
2702 (long) read_register (tdep
->DSR_REGNUM
));
2704 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2705 (long) read_register (0),
2706 (long) read_register (1),
2707 (long) read_register (2),
2708 (long) read_register (3),
2709 (long) read_register (4),
2710 (long) read_register (5),
2711 (long) read_register (6),
2712 (long) read_register (7));
2713 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2714 (long) read_register (8),
2715 (long) read_register (9),
2716 (long) read_register (10),
2717 (long) read_register (11),
2718 (long) read_register (12),
2719 (long) read_register (13),
2720 (long) read_register (14),
2721 (long) read_register (15));
2723 printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
2724 (long) read_register (tdep
->A0G_REGNUM
) & 0xff,
2725 (long) read_register (tdep
->A0_REGNUM
),
2726 (long) read_register (tdep
->M0_REGNUM
),
2727 (long) read_register (tdep
->X0_REGNUM
),
2728 (long) read_register (tdep
->Y0_REGNUM
),
2729 (long) read_register (tdep
->RS_REGNUM
),
2730 (long) read_register (tdep
->MOD_REGNUM
));
2731 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
2732 (long) read_register (tdep
->A1G_REGNUM
) & 0xff,
2733 (long) read_register (tdep
->A1_REGNUM
),
2734 (long) read_register (tdep
->M1_REGNUM
),
2735 (long) read_register (tdep
->X1_REGNUM
),
2736 (long) read_register (tdep
->Y1_REGNUM
),
2737 (long) read_register (tdep
->RE_REGNUM
));
2741 sh4_show_regs (void)
2743 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2745 int pr
= read_register (tdep
->FPSCR_REGNUM
) & 0x80000;
2746 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2747 paddr (read_register (PC_REGNUM
)),
2748 (long) read_register (tdep
->SR_REGNUM
),
2749 (long) read_register (tdep
->PR_REGNUM
),
2750 (long) read_register (MACH_REGNUM
),
2751 (long) read_register (MACL_REGNUM
));
2753 printf_filtered ("GBR=%08lx VBR=%08lx",
2754 (long) read_register (GBR_REGNUM
),
2755 (long) read_register (VBR_REGNUM
));
2756 printf_filtered (" SSR=%08lx SPC=%08lx",
2757 (long) read_register (tdep
->SSR_REGNUM
),
2758 (long) read_register (tdep
->SPC_REGNUM
));
2759 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
2760 (long) read_register (tdep
->FPUL_REGNUM
),
2761 (long) read_register (tdep
->FPSCR_REGNUM
));
2763 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2764 (long) read_register (0),
2765 (long) read_register (1),
2766 (long) read_register (2),
2767 (long) read_register (3),
2768 (long) read_register (4),
2769 (long) read_register (5),
2770 (long) read_register (6),
2771 (long) read_register (7));
2772 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2773 (long) read_register (8),
2774 (long) read_register (9),
2775 (long) read_register (10),
2776 (long) read_register (11),
2777 (long) read_register (12),
2778 (long) read_register (13),
2779 (long) read_register (14),
2780 (long) read_register (15));
2782 printf_filtered ((pr
2783 ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
2784 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2785 (long) read_register (FP0_REGNUM
+ 0),
2786 (long) read_register (FP0_REGNUM
+ 1),
2787 (long) read_register (FP0_REGNUM
+ 2),
2788 (long) read_register (FP0_REGNUM
+ 3),
2789 (long) read_register (FP0_REGNUM
+ 4),
2790 (long) read_register (FP0_REGNUM
+ 5),
2791 (long) read_register (FP0_REGNUM
+ 6),
2792 (long) read_register (FP0_REGNUM
+ 7));
2793 printf_filtered ((pr
2794 ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
2795 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2796 (long) read_register (FP0_REGNUM
+ 8),
2797 (long) read_register (FP0_REGNUM
+ 9),
2798 (long) read_register (FP0_REGNUM
+ 10),
2799 (long) read_register (FP0_REGNUM
+ 11),
2800 (long) read_register (FP0_REGNUM
+ 12),
2801 (long) read_register (FP0_REGNUM
+ 13),
2802 (long) read_register (FP0_REGNUM
+ 14),
2803 (long) read_register (FP0_REGNUM
+ 15));
2807 sh_dsp_show_regs (void)
2809 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2811 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2812 paddr (read_register (PC_REGNUM
)),
2813 (long) read_register (tdep
->SR_REGNUM
),
2814 (long) read_register (tdep
->PR_REGNUM
),
2815 (long) read_register (MACH_REGNUM
),
2816 (long) read_register (MACL_REGNUM
));
2818 printf_filtered ("GBR=%08lx VBR=%08lx",
2819 (long) read_register (GBR_REGNUM
),
2820 (long) read_register (VBR_REGNUM
));
2822 printf_filtered (" DSR=%08lx",
2823 (long) read_register (tdep
->DSR_REGNUM
));
2825 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2826 (long) read_register (0),
2827 (long) read_register (1),
2828 (long) read_register (2),
2829 (long) read_register (3),
2830 (long) read_register (4),
2831 (long) read_register (5),
2832 (long) read_register (6),
2833 (long) read_register (7));
2834 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2835 (long) read_register (8),
2836 (long) read_register (9),
2837 (long) read_register (10),
2838 (long) read_register (11),
2839 (long) read_register (12),
2840 (long) read_register (13),
2841 (long) read_register (14),
2842 (long) read_register (15));
2844 printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
2845 (long) read_register (tdep
->A0G_REGNUM
) & 0xff,
2846 (long) read_register (tdep
->A0_REGNUM
),
2847 (long) read_register (tdep
->M0_REGNUM
),
2848 (long) read_register (tdep
->X0_REGNUM
),
2849 (long) read_register (tdep
->Y0_REGNUM
),
2850 (long) read_register (tdep
->RS_REGNUM
),
2851 (long) read_register (tdep
->MOD_REGNUM
));
2852 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
2853 (long) read_register (tdep
->A1G_REGNUM
) & 0xff,
2854 (long) read_register (tdep
->A1_REGNUM
),
2855 (long) read_register (tdep
->M1_REGNUM
),
2856 (long) read_register (tdep
->X1_REGNUM
),
2857 (long) read_register (tdep
->Y1_REGNUM
),
2858 (long) read_register (tdep
->RE_REGNUM
));
2862 sh64_show_media_regs (void)
2865 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2867 printf_filtered ("PC=%s SR=%016llx \n",
2868 paddr (read_register (PC_REGNUM
)),
2869 (long long) read_register (tdep
->SR_REGNUM
));
2871 printf_filtered ("SSR=%016llx SPC=%016llx \n",
2872 (long long) read_register (tdep
->SSR_REGNUM
),
2873 (long long) read_register (tdep
->SPC_REGNUM
));
2874 printf_filtered ("FPSCR=%016lx\n ",
2875 (long) read_register (tdep
->FPSCR_REGNUM
));
2877 for (i
= 0; i
< 64; i
= i
+ 4)
2878 printf_filtered ("\nR%d-R%d %016llx %016llx %016llx %016llx\n",
2880 (long long) read_register (i
+ 0),
2881 (long long) read_register (i
+ 1),
2882 (long long) read_register (i
+ 2),
2883 (long long) read_register (i
+ 3));
2885 printf_filtered ("\n");
2887 for (i
= 0; i
< 64; i
= i
+ 8)
2888 printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2890 (long) read_register (FP0_REGNUM
+ i
+ 0),
2891 (long) read_register (FP0_REGNUM
+ i
+ 1),
2892 (long) read_register (FP0_REGNUM
+ i
+ 2),
2893 (long) read_register (FP0_REGNUM
+ i
+ 3),
2894 (long) read_register (FP0_REGNUM
+ i
+ 4),
2895 (long) read_register (FP0_REGNUM
+ i
+ 5),
2896 (long) read_register (FP0_REGNUM
+ i
+ 6),
2897 (long) read_register (FP0_REGNUM
+ i
+ 7));
2901 sh64_show_compact_regs (void)
2904 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2906 printf_filtered ("PC=%s \n",
2907 paddr (read_register (tdep
->PC_C_REGNUM
)));
2909 printf_filtered ("GBR=%08lx MACH=%08lx MACL=%08lx PR=%08lx T=%08lx\n",
2910 (long) read_register (tdep
->GBR_C_REGNUM
),
2911 (long) read_register (tdep
->MACH_C_REGNUM
),
2912 (long) read_register (tdep
->MACL_C_REGNUM
),
2913 (long) read_register (tdep
->PR_C_REGNUM
),
2914 (long) read_register (tdep
->T_C_REGNUM
));
2915 printf_filtered ("FPSCR=%08lx FPUL=%08lx\n",
2916 (long) read_register (tdep
->FPSCR_REGNUM
),
2917 (long) read_register (tdep
->FPUL_REGNUM
));
2919 for (i
= 0; i
< 16; i
= i
+ 4)
2920 printf_filtered ("\nR%d-R%d %08lx %08lx %08lx %08lx\n",
2922 (long) read_register (i
+ 0),
2923 (long) read_register (i
+ 1),
2924 (long) read_register (i
+ 2),
2925 (long) read_register (i
+ 3));
2927 printf_filtered ("\n");
2929 for (i
= 0; i
< 16; i
= i
+ 8)
2930 printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2932 (long) read_register (FP0_REGNUM
+ i
+ 0),
2933 (long) read_register (FP0_REGNUM
+ i
+ 1),
2934 (long) read_register (FP0_REGNUM
+ i
+ 2),
2935 (long) read_register (FP0_REGNUM
+ i
+ 3),
2936 (long) read_register (FP0_REGNUM
+ i
+ 4),
2937 (long) read_register (FP0_REGNUM
+ i
+ 5),
2938 (long) read_register (FP0_REGNUM
+ i
+ 6),
2939 (long) read_register (FP0_REGNUM
+ i
+ 7));
2942 /*FIXME!!! This only shows the registers for shmedia, excluding the
2943 pseudo registers. */
2945 sh64_show_regs (void)
2947 if (pc_is_isa32 (selected_frame
->pc
))
2948 sh64_show_media_regs ();
2950 sh64_show_compact_regs ();
2953 void sh_show_regs_command (char *args
, int from_tty
)
2959 /* Index within `registers' of the first byte of the space for
2962 sh_default_register_byte (int reg_nr
)
2964 return (reg_nr
* 4);
2968 sh_sh4_register_byte (int reg_nr
)
2970 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2972 if (reg_nr
>= tdep
->DR0_REGNUM
2973 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
2974 return (dr_reg_base_num (reg_nr
) * 4);
2975 else if (reg_nr
>= tdep
->FV0_REGNUM
2976 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
2977 return (fv_reg_base_num (reg_nr
) * 4);
2979 return (reg_nr
* 4);
2984 SH MEDIA MODE (ISA 32)
2985 general registers (64-bit) 0-63
2986 0 r0, r1, r2, r3, r4, r5, r6, r7,
2987 64 r8, r9, r10, r11, r12, r13, r14, r15,
2988 128 r16, r17, r18, r19, r20, r21, r22, r23,
2989 192 r24, r25, r26, r27, r28, r29, r30, r31,
2990 256 r32, r33, r34, r35, r36, r37, r38, r39,
2991 320 r40, r41, r42, r43, r44, r45, r46, r47,
2992 384 r48, r49, r50, r51, r52, r53, r54, r55,
2993 448 r56, r57, r58, r59, r60, r61, r62, r63,
2998 status reg., saved status reg., saved pc reg. (64-bit) 65-67
3001 target registers (64-bit) 68-75
3002 544 tr0, tr1, tr2, tr3, tr4, tr5, tr6, tr7,
3004 floating point state control register (32-bit) 76
3007 single precision floating point registers (32-bit) 77-140
3008 612 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7,
3009 644 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15,
3010 676 fr16, fr17, fr18, fr19, fr20, fr21, fr22, fr23,
3011 708 fr24, fr25, fr26, fr27, fr28, fr29, fr30, fr31,
3012 740 fr32, fr33, fr34, fr35, fr36, fr37, fr38, fr39,
3013 772 fr40, fr41, fr42, fr43, fr44, fr45, fr46, fr47,
3014 804 fr48, fr49, fr50, fr51, fr52, fr53, fr54, fr55,
3015 836 fr56, fr57, fr58, fr59, fr60, fr61, fr62, fr63,
3017 TOTAL SPACE FOR REGISTERS: 868 bytes
3019 From here on they are all pseudo registers: no memory allocated.
3020 REGISTER_BYTE returns the register byte for the base register.
3022 double precision registers (pseudo) 141-172
3023 dr0, dr2, dr4, dr6, dr8, dr10, dr12, dr14,
3024 dr16, dr18, dr20, dr22, dr24, dr26, dr28, dr30,
3025 dr32, dr34, dr36, dr38, dr40, dr42, dr44, dr46,
3026 dr48, dr50, dr52, dr54, dr56, dr58, dr60, dr62,
3028 floating point pairs (pseudo) 173-204
3029 fp0, fp2, fp4, fp6, fp8, fp10, fp12, fp14,
3030 fp16, fp18, fp20, fp22, fp24, fp26, fp28, fp30,
3031 fp32, fp34, fp36, fp38, fp40, fp42, fp44, fp46,
3032 fp48, fp50, fp52, fp54, fp56, fp58, fp60, fp62,
3034 floating point vectors (4 floating point regs) (pseudo) 205-220
3035 fv0, fv4, fv8, fv12, fv16, fv20, fv24, fv28,
3036 fv32, fv36, fv40, fv44, fv48, fv52, fv56, fv60,
3038 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
3039 r0_c, r1_c, r2_c, r3_c, r4_c, r5_c, r6_c, r7_c,
3040 r8_c, r9_c, r10_c, r11_c, r12_c, r13_c, r14_c, r15_c,
3042 gbr_c, mach_c, macl_c, pr_c, t_c,
3044 fr0_c, fr1_c, fr2_c, fr3_c, fr4_c, fr5_c, fr6_c, fr7_c,
3045 fr8_c, fr9_c, fr10_c, fr11_c, fr12_c, fr13_c, fr14_c, fr15_c
3046 dr0_c, dr2_c, dr4_c, dr6_c, dr8_c, dr10_c, dr12_c, dr14_c
3047 fv0_c, fv4_c, fv8_c, fv12_c
3051 sh_sh64_register_byte (int reg_nr
)
3053 int base_regnum
= -1;
3054 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3056 /* If it is a pseudo register, get the number of the first floating
3057 point register that is part of it. */
3058 if (reg_nr
>= tdep
->DR0_REGNUM
3059 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
3060 base_regnum
= dr_reg_base_num (reg_nr
);
3062 else if (reg_nr
>= tdep
->FPP0_REGNUM
3063 && reg_nr
<= tdep
->FPP_LAST_REGNUM
)
3064 base_regnum
= fpp_reg_base_num (reg_nr
);
3066 else if (reg_nr
>= tdep
->FV0_REGNUM
3067 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
3068 base_regnum
= fv_reg_base_num (reg_nr
);
3070 /* sh compact pseudo register. FPSCR is a pathological case, need to
3071 treat it as special. */
3072 else if ((reg_nr
>= tdep
->R0_C_REGNUM
3073 && reg_nr
<= tdep
->FV_LAST_C_REGNUM
)
3074 && reg_nr
!= tdep
->FPSCR_C_REGNUM
)
3075 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3077 /* Now return the offset in bytes within the register cache. */
3078 /* sh media pseudo register, i.e. any of DR, FFP, FV registers. */
3079 if (reg_nr
>= tdep
->DR0_REGNUM
3080 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
3081 return (base_regnum
- FP0_REGNUM
+ 1) * 4
3082 + (tdep
->TR7_REGNUM
+ 1) * 8;
3084 /* sh compact pseudo register: general register */
3085 if ((reg_nr
>= tdep
->R0_C_REGNUM
3086 && reg_nr
<= tdep
->R_LAST_C_REGNUM
))
3087 return (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3088 ? base_regnum
* 8 + 4
3091 /* sh compact pseudo register: */
3092 if (reg_nr
== tdep
->PC_C_REGNUM
3093 || reg_nr
== tdep
->GBR_C_REGNUM
3094 || reg_nr
== tdep
->MACL_C_REGNUM
3095 || reg_nr
== tdep
->PR_C_REGNUM
)
3096 return (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3097 ? base_regnum
* 8 + 4
3100 if (reg_nr
== tdep
->MACH_C_REGNUM
)
3101 return base_regnum
* 8;
3103 if (reg_nr
== tdep
->T_C_REGNUM
)
3104 return base_regnum
* 8; /* FIXME??? how do we get bit 0? Do we have to? */
3106 /* sh compact pseudo register: floating point register */
3107 else if (reg_nr
>=tdep
->FP0_C_REGNUM
3108 && reg_nr
<= tdep
->FV_LAST_C_REGNUM
)
3109 return (base_regnum
- FP0_REGNUM
) * 4
3110 + (tdep
->TR7_REGNUM
+ 1) * 8 + 4;
3112 else if (reg_nr
== tdep
->FPSCR_C_REGNUM
)
3113 /* This is complicated, for now return the beginning of the
3114 architectural FPSCR register. */
3115 return (tdep
->TR7_REGNUM
+ 1) * 8;
3117 else if (reg_nr
== tdep
->FPUL_C_REGNUM
)
3118 return ((base_regnum
- FP0_REGNUM
) * 4 +
3119 (tdep
->TR7_REGNUM
+ 1) * 8 + 4);
3121 /* It is not a pseudo register. */
3122 /* It is a 64 bit register. */
3123 else if (reg_nr
<= tdep
->TR7_REGNUM
)
3126 /* It is a 32 bit register. */
3128 if (reg_nr
== tdep
->FPSCR_REGNUM
)
3129 return (tdep
->FPSCR_REGNUM
* 8);
3131 /* It is floating point 32-bit register */
3133 return ((tdep
->TR7_REGNUM
+ 1) * 8
3134 + (reg_nr
- FP0_REGNUM
+ 1) * 4);
3137 /* Number of bytes of storage in the actual machine representation for
3140 sh_default_register_raw_size (int reg_nr
)
3146 sh_sh4_register_raw_size (int reg_nr
)
3148 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3150 if (reg_nr
>= tdep
->DR0_REGNUM
3151 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
3153 else if (reg_nr
>= tdep
->FV0_REGNUM
3154 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
3161 sh_sh64_register_raw_size (int reg_nr
)
3163 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3165 if ((reg_nr
>= tdep
->DR0_REGNUM
3166 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
3167 || (reg_nr
>= tdep
->FPP0_REGNUM
3168 && reg_nr
<= tdep
->FPP_LAST_REGNUM
)
3169 || (reg_nr
>= tdep
->DR0_C_REGNUM
3170 && reg_nr
<= tdep
->DR_LAST_C_REGNUM
)
3171 || (reg_nr
<= tdep
->TR7_REGNUM
))
3174 else if ((reg_nr
>= tdep
->FV0_REGNUM
3175 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
3176 || (reg_nr
>= tdep
->FV0_C_REGNUM
3177 && reg_nr
<= tdep
->FV_LAST_C_REGNUM
))
3180 else /* this covers also the 32-bit SH compact registers. */
3184 /* Number of bytes of storage in the program's representation
3187 sh_register_virtual_size (int reg_nr
)
3194 sh_sh64_register_virtual_size (int reg_nr
)
3196 if (reg_nr
>= FP0_REGNUM
3197 && reg_nr
<= gdbarch_tdep (current_gdbarch
)->FP_LAST_REGNUM
)
3203 /* Return the GDB type object for the "standard" data type
3204 of data in register N. */
3205 static struct type
*
3206 sh_sh3e_register_virtual_type (int reg_nr
)
3208 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3210 if ((reg_nr
>= FP0_REGNUM
3211 && (reg_nr
<= tdep
->FP_LAST_REGNUM
))
3212 || (reg_nr
== tdep
->FPUL_REGNUM
))
3213 return builtin_type_float
;
3215 return builtin_type_int
;
3218 static struct type
*
3219 sh_sh4_build_float_register_type (int high
)
3223 temp
= create_range_type (NULL
, builtin_type_int
, 0, high
);
3224 return create_array_type (NULL
, builtin_type_float
, temp
);
3227 static struct type
*
3228 sh_sh4_register_virtual_type (int reg_nr
)
3230 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3232 if ((reg_nr
>= FP0_REGNUM
3233 && (reg_nr
<= tdep
->FP_LAST_REGNUM
))
3234 || (reg_nr
== tdep
->FPUL_REGNUM
))
3235 return builtin_type_float
;
3236 else if (reg_nr
>= tdep
->DR0_REGNUM
3237 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
3238 return builtin_type_double
;
3239 else if (reg_nr
>= tdep
->FV0_REGNUM
3240 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
3241 return sh_sh4_build_float_register_type (3);
3243 return builtin_type_int
;
3246 static struct type
*
3247 sh_sh64_register_virtual_type (int reg_nr
)
3249 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3251 if ((reg_nr
>= FP0_REGNUM
3252 && reg_nr
<= tdep
->FP_LAST_REGNUM
)
3253 || (reg_nr
>= tdep
->FP0_C_REGNUM
3254 && reg_nr
<= tdep
->FP_LAST_C_REGNUM
))
3255 return builtin_type_float
;
3256 else if ((reg_nr
>= tdep
->DR0_REGNUM
3257 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
3258 || (reg_nr
>= tdep
->DR0_C_REGNUM
3259 && reg_nr
<= tdep
->DR_LAST_C_REGNUM
))
3260 return builtin_type_double
;
3261 else if (reg_nr
>= tdep
->FPP0_REGNUM
3262 && reg_nr
<= tdep
->FPP_LAST_REGNUM
)
3263 return sh_sh4_build_float_register_type (1);
3264 else if ((reg_nr
>= tdep
->FV0_REGNUM
3265 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
3266 ||(reg_nr
>= tdep
->FV0_C_REGNUM
3267 && reg_nr
<= tdep
->FV_LAST_C_REGNUM
))
3268 return sh_sh4_build_float_register_type (3);
3269 else if (reg_nr
== tdep
->FPSCR_REGNUM
)
3270 return builtin_type_int
;
3271 else if (reg_nr
>= tdep
->R0_C_REGNUM
3272 && reg_nr
< tdep
->FP0_C_REGNUM
)
3273 return builtin_type_int
;
3275 return builtin_type_long_long
;
3278 static struct type
*
3279 sh_default_register_virtual_type (int reg_nr
)
3281 return builtin_type_int
;
3284 /* On the sh4, the DRi pseudo registers are problematic if the target
3285 is little endian. When the user writes one of those registers, for
3286 instance with 'ser var $dr0=1', we want the double to be stored
3288 fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
3289 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
3291 This corresponds to little endian byte order & big endian word
3292 order. However if we let gdb write the register w/o conversion, it
3293 will write fr0 and fr1 this way:
3294 fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
3295 fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
3296 because it will consider fr0 and fr1 as a single LE stretch of memory.
3298 To achieve what we want we must force gdb to store things in
3299 floatformat_ieee_double_littlebyte_bigword (which is defined in
3300 include/floatformat.h and libiberty/floatformat.c.
3302 In case the target is big endian, there is no problem, the
3303 raw bytes will look like:
3304 fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
3305 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
3307 The other pseudo registers (the FVs) also don't pose a problem
3308 because they are stored as 4 individual FP elements. */
3311 sh_sh4_register_convert_to_virtual (int regnum
, struct type
*type
,
3312 char *from
, char *to
)
3314 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3316 if (regnum
>= tdep
->DR0_REGNUM
3317 && regnum
<= tdep
->DR_LAST_REGNUM
)
3320 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword
, from
, &val
);
3321 store_floating (to
, TYPE_LENGTH (type
), val
);
3324 error ("sh_register_convert_to_virtual called with non DR register number");
3328 sh_sh64_register_convert_to_virtual (int regnum
, struct type
*type
,
3329 char *from
, char *to
)
3331 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3333 if (TARGET_BYTE_ORDER
!= BFD_ENDIAN_LITTLE
)
3335 /* It is a no-op. */
3336 memcpy (to
, from
, REGISTER_RAW_SIZE (regnum
));
3340 if ((regnum
>= tdep
->DR0_REGNUM
3341 && regnum
<= tdep
->DR_LAST_REGNUM
)
3342 || (regnum
>= tdep
->DR0_C_REGNUM
3343 && regnum
<= tdep
->DR_LAST_C_REGNUM
))
3346 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword
, from
, &val
);
3347 store_floating(to
, TYPE_LENGTH(type
), val
);
3350 error("sh_register_convert_to_virtual called with non DR register number");
3354 sh_sh4_register_convert_to_raw (struct type
*type
, int regnum
,
3355 char *from
, char *to
)
3357 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3359 if (regnum
>= tdep
->DR0_REGNUM
3360 && regnum
<= tdep
->DR_LAST_REGNUM
)
3362 DOUBLEST val
= extract_floating (from
, TYPE_LENGTH(type
));
3363 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword
, &val
, to
);
3366 error("sh_register_convert_to_raw called with non DR register number");
3370 sh_sh64_register_convert_to_raw (struct type
*type
, int regnum
,
3371 char *from
, char *to
)
3373 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3375 if (TARGET_BYTE_ORDER
!= BFD_ENDIAN_LITTLE
)
3377 /* It is a no-op. */
3378 memcpy (to
, from
, REGISTER_RAW_SIZE (regnum
));
3382 if ((regnum
>= tdep
->DR0_REGNUM
3383 && regnum
<= tdep
->DR_LAST_REGNUM
)
3384 || (regnum
>= tdep
->DR0_C_REGNUM
3385 && regnum
<= tdep
->DR_LAST_C_REGNUM
))
3387 DOUBLEST val
= extract_floating (from
, TYPE_LENGTH(type
));
3388 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword
, &val
, to
);
3391 error("sh_register_convert_to_raw called with non DR register number");
3395 sh_pseudo_register_read (int reg_nr
, char *buffer
)
3397 int base_regnum
, portion
;
3398 char *temp_buffer
= (char*) alloca (MAX_REGISTER_RAW_SIZE
);
3399 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3401 if (reg_nr
>= tdep
->DR0_REGNUM
3402 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
3404 base_regnum
= dr_reg_base_num (reg_nr
);
3406 /* Build the value in the provided buffer. */
3407 /* Read the real regs for which this one is an alias. */
3408 for (portion
= 0; portion
< 2; portion
++)
3409 regcache_read (base_regnum
+ portion
,
3411 + REGISTER_RAW_SIZE (base_regnum
) * portion
);
3412 /* We must pay attention to the endiannes. */
3413 sh_sh4_register_convert_to_virtual (reg_nr
,
3414 REGISTER_VIRTUAL_TYPE (reg_nr
),
3415 temp_buffer
, buffer
);
3417 else if (reg_nr
>= tdep
->FV0_REGNUM
3418 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
3420 base_regnum
= fv_reg_base_num (reg_nr
);
3422 /* Read the real regs for which this one is an alias. */
3423 for (portion
= 0; portion
< 4; portion
++)
3424 regcache_read (base_regnum
+ portion
,
3425 buffer
+ REGISTER_RAW_SIZE (base_regnum
) * portion
);
3430 sh4_register_read (struct gdbarch
*gdbarch
, int reg_nr
, char *buffer
)
3432 if (reg_nr
>= 0 && reg_nr
< gdbarch_tdep (current_gdbarch
)->DR0_REGNUM
)
3433 /* It is a regular register. */
3434 regcache_read (reg_nr
, buffer
);
3436 /* It is a pseudo register and we need to construct its value */
3437 sh_pseudo_register_read (reg_nr
, buffer
);
3441 sh64_pseudo_register_read (int reg_nr
, char *buffer
)
3446 char *temp_buffer
= (char*) alloca (MAX_REGISTER_RAW_SIZE
);
3447 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3449 if (reg_nr
>= tdep
->DR0_REGNUM
3450 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
3452 base_regnum
= dr_reg_base_num (reg_nr
);
3454 /* Build the value in the provided buffer. */
3455 /* DR regs are double precision registers obtained by
3456 concatenating 2 single precision floating point registers. */
3457 for (portion
= 0; portion
< 2; portion
++)
3458 regcache_read (base_regnum
+ portion
,
3460 + REGISTER_RAW_SIZE (base_regnum
) * portion
);
3462 /* We must pay attention to the endiannes. */
3463 sh_sh64_register_convert_to_virtual (reg_nr
, REGISTER_VIRTUAL_TYPE (reg_nr
),
3464 temp_buffer
, buffer
);
3468 else if (reg_nr
>= tdep
->FPP0_REGNUM
3469 && reg_nr
<= tdep
->FPP_LAST_REGNUM
)
3471 base_regnum
= fpp_reg_base_num (reg_nr
);
3473 /* Build the value in the provided buffer. */
3474 /* FPP regs are pairs of single precision registers obtained by
3475 concatenating 2 single precision floating point registers. */
3476 for (portion
= 0; portion
< 2; portion
++)
3477 regcache_read (base_regnum
+ portion
,
3478 buffer
+ REGISTER_RAW_SIZE (base_regnum
) * portion
);
3481 else if (reg_nr
>= tdep
->FV0_REGNUM
3482 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
3484 base_regnum
= fv_reg_base_num (reg_nr
);
3486 /* Build the value in the provided buffer. */
3487 /* FV regs are vectors of single precision registers obtained by
3488 concatenating 4 single precision floating point registers. */
3489 for (portion
= 0; portion
< 4; portion
++)
3490 regcache_read (base_regnum
+ portion
,
3491 buffer
+ REGISTER_RAW_SIZE (base_regnum
) * portion
);
3494 /* sh compact pseudo registers. 1-to-1 with a shmedia register */
3495 else if (reg_nr
>= tdep
->R0_C_REGNUM
3496 && reg_nr
<= tdep
->T_C_REGNUM
)
3498 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3500 /* Build the value in the provided buffer. */
3501 regcache_read (base_regnum
, temp_buffer
);
3502 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3504 memcpy (buffer
, temp_buffer
+ offset
, 4); /* get LOWER 32 bits only????*/
3507 else if (reg_nr
>= tdep
->FP0_C_REGNUM
3508 && reg_nr
<= tdep
->FP_LAST_C_REGNUM
)
3510 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3512 /* Build the value in the provided buffer. */
3513 /* Floating point registers map 1-1 to the media fp regs,
3514 they have the same size and endienness. */
3515 regcache_read (base_regnum
, buffer
);
3518 else if (reg_nr
>= tdep
->DR0_C_REGNUM
3519 && reg_nr
<= tdep
->DR_LAST_C_REGNUM
)
3521 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3523 /* DR_C regs are double precision registers obtained by
3524 concatenating 2 single precision floating point registers. */
3525 for (portion
= 0; portion
< 2; portion
++)
3526 regcache_read (base_regnum
+ portion
,
3528 + REGISTER_RAW_SIZE (base_regnum
) * portion
);
3530 /* We must pay attention to the endiannes. */
3531 sh_sh64_register_convert_to_virtual (reg_nr
, REGISTER_VIRTUAL_TYPE (reg_nr
),
3532 temp_buffer
, buffer
);
3535 else if (reg_nr
>= tdep
->FV0_C_REGNUM
3536 && reg_nr
<= tdep
->FV_LAST_C_REGNUM
)
3538 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3540 /* Build the value in the provided buffer. */
3541 /* FV_C regs are vectors of single precision registers obtained by
3542 concatenating 4 single precision floating point registers. */
3543 for (portion
= 0; portion
< 4; portion
++)
3544 regcache_read (base_regnum
+ portion
,
3545 buffer
+ REGISTER_RAW_SIZE (base_regnum
) * portion
);
3548 else if (reg_nr
== tdep
->FPSCR_C_REGNUM
)
3550 int fpscr_base_regnum
;
3552 unsigned int fpscr_value
;
3553 unsigned int sr_value
;
3554 unsigned int fpscr_c_value
;
3555 unsigned int fpscr_c_part1_value
;
3556 unsigned int fpscr_c_part2_value
;
3558 fpscr_base_regnum
= tdep
->FPSCR_REGNUM
;
3559 sr_base_regnum
= tdep
->SR_REGNUM
;
3561 /* Build the value in the provided buffer. */
3562 /* FPSCR_C is a very weird register that contains sparse bits
3563 from the FPSCR and the SR architectural registers.
3570 2-17 Bit 2-18 of FPSCR
3571 18-20 Bits 12,13,14 of SR
3575 /* Get FPSCR into a local buffer */
3576 regcache_read (fpscr_base_regnum
, temp_buffer
);
3577 /* Get value as an int. */
3578 fpscr_value
= extract_unsigned_integer (temp_buffer
, 4);
3579 /* Get SR into a local buffer */
3580 regcache_read (sr_base_regnum
, temp_buffer
);
3581 /* Get value as an int. */
3582 sr_value
= extract_unsigned_integer (temp_buffer
, 4);
3583 /* Build the new value. */
3584 fpscr_c_part1_value
= fpscr_value
& 0x3fffd;
3585 fpscr_c_part2_value
= (sr_value
& 0x7000) << 6;
3586 fpscr_c_value
= fpscr_c_part1_value
| fpscr_c_part2_value
;
3587 /* Store that in out buffer!!! */
3588 store_unsigned_integer (buffer
, 4, fpscr_c_value
);
3589 /* FIXME There is surely an endianness gotcha here. */
3592 else if (reg_nr
== tdep
->FPUL_C_REGNUM
)
3594 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3596 /* FPUL_C register is floating point register 32,
3597 same size, same endianness. */
3598 regcache_read (base_regnum
, buffer
);
3603 sh64_register_read (struct gdbarch
*gdbarch
, int reg_nr
, char *buffer
)
3606 if (reg_nr
>= 0 && reg_nr
< gdbarch_tdep (current_gdbarch
)->DR0_REGNUM
)
3607 /* It is a regular register. */
3608 regcache_read (reg_nr
, buffer
);
3610 /* It is a pseudo register and we need to construct its value */
3611 sh64_pseudo_register_read (reg_nr
, buffer
);
3615 sh_pseudo_register_write (int reg_nr
, char *buffer
)
3617 int base_regnum
, portion
;
3618 char *temp_buffer
= (char*) alloca (MAX_REGISTER_RAW_SIZE
);
3619 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3621 if (reg_nr
>= tdep
->DR0_REGNUM
3622 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
3624 base_regnum
= dr_reg_base_num (reg_nr
);
3626 /* We must pay attention to the endiannes. */
3627 sh_sh4_register_convert_to_raw (REGISTER_VIRTUAL_TYPE (reg_nr
), reg_nr
,
3628 buffer
, temp_buffer
);
3630 /* Write the real regs for which this one is an alias. */
3631 for (portion
= 0; portion
< 2; portion
++)
3632 regcache_write (base_regnum
+ portion
,
3633 temp_buffer
+ REGISTER_RAW_SIZE (base_regnum
) * portion
);
3635 else if (reg_nr
>= tdep
->FV0_REGNUM
3636 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
3638 base_regnum
= fv_reg_base_num (reg_nr
);
3640 /* Write the real regs for which this one is an alias. */
3641 for (portion
= 0; portion
< 4; portion
++)
3642 regcache_write (base_regnum
+ portion
,
3643 buffer
+ REGISTER_RAW_SIZE (base_regnum
) * portion
);
3648 sh4_register_write (struct gdbarch
*gdbarch
, int reg_nr
, char *buffer
)
3650 if (reg_nr
>= 0 && reg_nr
< gdbarch_tdep (current_gdbarch
)->DR0_REGNUM
)
3651 /* It is a regular register. */
3652 regcache_write (reg_nr
, buffer
);
3654 /* It is a pseudo register and we need to construct its value */
3655 sh_pseudo_register_write (reg_nr
, buffer
);
3659 sh64_pseudo_register_write (int reg_nr
, char *buffer
)
3661 int base_regnum
, portion
;
3663 char *temp_buffer
= (char*) alloca (MAX_REGISTER_RAW_SIZE
);
3664 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3666 if (reg_nr
>= tdep
->DR0_REGNUM
3667 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
3669 base_regnum
= dr_reg_base_num (reg_nr
);
3670 /* We must pay attention to the endiannes. */
3671 sh_sh64_register_convert_to_raw (REGISTER_VIRTUAL_TYPE (reg_nr
), reg_nr
,
3672 buffer
, temp_buffer
);
3675 /* Write the real regs for which this one is an alias. */
3676 for (portion
= 0; portion
< 2; portion
++)
3677 regcache_write (base_regnum
+ portion
,
3678 temp_buffer
+ REGISTER_RAW_SIZE (base_regnum
) * portion
);
3681 else if (reg_nr
>= tdep
->FPP0_REGNUM
3682 && reg_nr
<= tdep
->FPP_LAST_REGNUM
)
3684 base_regnum
= fpp_reg_base_num (reg_nr
);
3686 /* Write the real regs for which this one is an alias. */
3687 for (portion
= 0; portion
< 2; portion
++)
3688 regcache_write (base_regnum
+ portion
,
3689 buffer
+ REGISTER_RAW_SIZE (base_regnum
) * portion
);
3692 else if (reg_nr
>= tdep
->FV0_REGNUM
3693 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
3695 base_regnum
= fv_reg_base_num (reg_nr
);
3697 /* Write the real regs for which this one is an alias. */
3698 for (portion
= 0; portion
< 4; portion
++)
3699 regcache_write (base_regnum
+ portion
,
3700 buffer
+ REGISTER_RAW_SIZE (base_regnum
) * portion
);
3703 /* sh compact general pseudo registers. 1-to-1 with a shmedia
3704 register but only 4 bytes of it. */
3705 else if (reg_nr
>= tdep
->R0_C_REGNUM
3706 && reg_nr
<= tdep
->T_C_REGNUM
)
3708 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3709 /* reg_nr is 32 bit here, and base_regnum is 64 bits. */
3710 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3714 /* Let's read the value of the base register into a temporary
3715 buffer, so that overwriting the last four bytes with the new
3716 value of the pseudo will leave the upper 4 bytes unchanged. */
3717 regcache_read (base_regnum
, temp_buffer
);
3718 /* Write as an 8 byte quantity */
3719 memcpy (temp_buffer
+ offset
, buffer
, 4);
3720 regcache_write (base_regnum
, temp_buffer
);
3723 /* sh floating point compact pseudo registers. 1-to-1 with a shmedia
3724 registers. Both are 4 bytes. */
3725 else if (reg_nr
>= tdep
->FP0_C_REGNUM
3726 && reg_nr
<= tdep
->FP_LAST_C_REGNUM
)
3728 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3729 regcache_write (base_regnum
, buffer
);
3732 else if (reg_nr
>= tdep
->DR0_C_REGNUM
3733 && reg_nr
<= tdep
->DR_LAST_C_REGNUM
)
3735 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3736 for (portion
= 0; portion
< 2; portion
++)
3738 /* We must pay attention to the endiannes. */
3739 sh_sh64_register_convert_to_raw (REGISTER_VIRTUAL_TYPE (reg_nr
), reg_nr
,
3740 buffer
, temp_buffer
);
3742 regcache_write (base_regnum
+ portion
,
3743 temp_buffer
+ REGISTER_RAW_SIZE (base_regnum
) * portion
);
3747 else if (reg_nr
>= tdep
->FV0_C_REGNUM
3748 && reg_nr
<= tdep
->FV_LAST_C_REGNUM
)
3750 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3752 for (portion
= 0; portion
< 4; portion
++)
3754 regcache_write (base_regnum
+ portion
,
3755 buffer
+ REGISTER_RAW_SIZE (base_regnum
) * portion
);
3759 else if (reg_nr
== tdep
->FPSCR_C_REGNUM
)
3761 int fpscr_base_regnum
;
3763 unsigned int fpscr_value
;
3764 unsigned int sr_value
;
3765 unsigned int old_fpscr_value
;
3766 unsigned int old_sr_value
;
3767 unsigned int fpscr_c_value
;
3768 unsigned int fpscr_mask
;
3769 unsigned int sr_mask
;
3771 fpscr_base_regnum
= tdep
->FPSCR_REGNUM
;
3772 sr_base_regnum
= tdep
->SR_REGNUM
;
3774 /* FPSCR_C is a very weird register that contains sparse bits
3775 from the FPSCR and the SR architectural registers.
3782 2-17 Bit 2-18 of FPSCR
3783 18-20 Bits 12,13,14 of SR
3787 /* Get value as an int. */
3788 fpscr_c_value
= extract_unsigned_integer (buffer
, 4);
3790 /* Build the new values. */
3791 fpscr_mask
= 0x0003fffd;
3792 sr_mask
= 0x001c0000;
3794 fpscr_value
= fpscr_c_value
& fpscr_mask
;
3795 sr_value
= (fpscr_value
& sr_mask
) >> 6;
3797 regcache_read (fpscr_base_regnum
, temp_buffer
);
3798 old_fpscr_value
= extract_unsigned_integer (temp_buffer
, 4);
3799 old_fpscr_value
&= 0xfffc0002;
3800 fpscr_value
|= old_fpscr_value
;
3801 store_unsigned_integer (temp_buffer
, 4, fpscr_value
);
3802 regcache_write (fpscr_base_regnum
, temp_buffer
);
3804 regcache_read (sr_base_regnum
, temp_buffer
);
3805 old_sr_value
= extract_unsigned_integer (temp_buffer
, 4);
3806 old_sr_value
&= 0xffff8fff;
3807 sr_value
|= old_sr_value
;
3808 store_unsigned_integer (temp_buffer
, 4, sr_value
);
3809 regcache_write (sr_base_regnum
, temp_buffer
);
3812 else if (reg_nr
== tdep
->FPUL_C_REGNUM
)
3814 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3815 regcache_write (base_regnum
, buffer
);
3820 sh64_register_write (struct gdbarch
*gdbarch
, int reg_nr
, char *buffer
)
3822 if (reg_nr
>= 0 && reg_nr
< gdbarch_tdep (current_gdbarch
)->DR0_REGNUM
)
3823 /* It is a regular register. */
3824 regcache_write (reg_nr
, buffer
);
3826 /* It is a pseudo register and we need to construct its value */
3827 sh64_pseudo_register_write (reg_nr
, buffer
);
3830 /* Floating point vector of 4 float registers. */
3832 do_fv_register_info (int fv_regnum
)
3834 int first_fp_reg_num
= fv_reg_base_num (fv_regnum
);
3835 printf_filtered ("fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
3836 fv_regnum
- gdbarch_tdep (current_gdbarch
)->FV0_REGNUM
,
3837 (int) read_register (first_fp_reg_num
),
3838 (int) read_register (first_fp_reg_num
+ 1),
3839 (int) read_register (first_fp_reg_num
+ 2),
3840 (int) read_register (first_fp_reg_num
+ 3));
3843 /* Floating point vector of 4 float registers, compact mode. */
3845 do_fv_c_register_info (int fv_regnum
)
3847 int first_fp_reg_num
= sh64_compact_reg_base_num (fv_regnum
);
3848 printf_filtered ("fv%d_c\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
3849 fv_regnum
- gdbarch_tdep (current_gdbarch
)->FV0_C_REGNUM
,
3850 (int) read_register (first_fp_reg_num
),
3851 (int) read_register (first_fp_reg_num
+ 1),
3852 (int) read_register (first_fp_reg_num
+ 2),
3853 (int) read_register (first_fp_reg_num
+ 3));
3856 /* Pairs of single regs. The DR are instead double precision
3859 do_fpp_register_info (int fpp_regnum
)
3861 int first_fp_reg_num
= fpp_reg_base_num (fpp_regnum
);
3863 printf_filtered ("fpp%d\t0x%08x\t0x%08x\n",
3864 fpp_regnum
- gdbarch_tdep (current_gdbarch
)->FPP0_REGNUM
,
3865 (int) read_register (first_fp_reg_num
),
3866 (int) read_register (first_fp_reg_num
+ 1));
3869 /* Double precision registers. */
3871 do_dr_register_info (int dr_regnum
)
3873 int first_fp_reg_num
= dr_reg_base_num (dr_regnum
);
3875 printf_filtered ("dr%d\t0x%08x%08x\n",
3876 dr_regnum
- gdbarch_tdep (current_gdbarch
)->DR0_REGNUM
,
3877 (int) read_register (first_fp_reg_num
),
3878 (int) read_register (first_fp_reg_num
+ 1));
3881 /* Double precision registers, compact mode. */
3883 do_dr_c_register_info (int dr_regnum
)
3885 int first_fp_reg_num
= sh64_compact_reg_base_num (dr_regnum
);
3887 printf_filtered ("dr%d_c\t0x%08x%08x\n",
3888 dr_regnum
- gdbarch_tdep (current_gdbarch
)->DR0_C_REGNUM
,
3889 (int) read_register (first_fp_reg_num
),
3890 (int) read_register (first_fp_reg_num
+1));
3893 /* General register in compact mode. */
3895 do_r_c_register_info (int r_c_regnum
)
3897 int regnum
= sh64_compact_reg_base_num (r_c_regnum
);
3899 printf_filtered ("r%d_c\t0x%08x\n",
3900 r_c_regnum
- gdbarch_tdep (current_gdbarch
)->R0_C_REGNUM
,
3901 /*FIXME!!!*/ (int) read_register (regnum
));
3904 /* FIXME:!! THIS SHOULD TAKE CARE OF GETTING THE RIGHT PORTION OF THE
3905 shmedia REGISTERS. */
3906 /* Control registers, compact mode. */
3908 do_cr_c_register_info (int cr_c_regnum
)
3910 switch (cr_c_regnum
)
3912 case 237: printf_filtered ("pc_c\t0x%08x\n", (int) read_register (cr_c_regnum
));
3914 case 238: printf_filtered ("gbr_c\t0x%08x\n", (int) read_register (cr_c_regnum
));
3916 case 239: printf_filtered ("mach_c\t0x%08x\n", (int) read_register (cr_c_regnum
));
3918 case 240: printf_filtered ("macl_c\t0x%08x\n", (int) read_register (cr_c_regnum
));
3920 case 241: printf_filtered ("pr_c\t0x%08x\n", (int) read_register (cr_c_regnum
));
3922 case 242: printf_filtered ("t_c\t0x%08x\n", (int) read_register (cr_c_regnum
));
3924 case 243: printf_filtered ("fpscr_c\t0x%08x\n", (int) read_register (cr_c_regnum
));
3926 case 244: printf_filtered ("fpul_c\t0x%08x\n", (int)read_register (cr_c_regnum
));
3932 sh_do_pseudo_register (int regnum
)
3934 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3936 if (regnum
< NUM_REGS
|| regnum
>= NUM_REGS
+ NUM_PSEUDO_REGS
)
3937 internal_error (__FILE__
, __LINE__
,
3938 "Invalid pseudo register number %d\n", regnum
);
3939 else if (regnum
>= tdep
->DR0_REGNUM
3940 && regnum
< tdep
->DR_LAST_REGNUM
)
3941 do_dr_register_info (regnum
);
3942 else if (regnum
>= tdep
->FV0_REGNUM
3943 && regnum
<= tdep
->FV_LAST_REGNUM
)
3944 do_fv_register_info (regnum
);
3948 sh_do_fp_register (int regnum
)
3949 { /* do values for FP (float) regs */
3951 double flt
; /* double extracted from raw hex data */
3955 /* Allocate space for the float. */
3956 raw_buffer
= (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM
));
3958 /* Get the data in raw format. */
3959 if (!frame_register_read (selected_frame
, regnum
, raw_buffer
))
3960 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
3962 /* Get the register as a number */
3963 flt
= unpack_double (builtin_type_float
, raw_buffer
, &inv
);
3965 /* Print the name and some spaces. */
3966 fputs_filtered (REGISTER_NAME (regnum
), gdb_stdout
);
3967 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum
)), gdb_stdout
);
3969 /* Print the value. */
3971 printf_filtered ("<invalid float>");
3973 printf_filtered ("%-10.9g", flt
);
3975 /* Print the fp register as hex. */
3976 printf_filtered ("\t(raw 0x");
3977 for (j
= 0; j
< REGISTER_RAW_SIZE (regnum
); j
++)
3979 register int idx
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? j
3980 : REGISTER_RAW_SIZE (regnum
) - 1 - j
;
3981 printf_filtered ("%02x", (unsigned char) raw_buffer
[idx
]);
3983 printf_filtered (")");
3984 printf_filtered ("\n");
3988 sh64_do_pseudo_register (int regnum
)
3990 /* All the sh64-compact mode registers are pseudo registers. */
3991 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3993 if (regnum
< NUM_REGS
3994 || regnum
>= NUM_REGS
+ NUM_PSEUDO_REGS_SH_MEDIA
+ NUM_PSEUDO_REGS_SH_COMPACT
)
3995 internal_error (__FILE__
, __LINE__
,
3996 "Invalid pseudo register number %d\n", regnum
);
3998 else if ((regnum
>= tdep
->DR0_REGNUM
3999 && regnum
<= tdep
->DR_LAST_REGNUM
))
4000 do_dr_register_info (regnum
);
4002 else if ((regnum
>= tdep
->DR0_C_REGNUM
4003 && regnum
<= tdep
->DR_LAST_C_REGNUM
))
4004 do_dr_c_register_info (regnum
);
4006 else if ((regnum
>= tdep
->FV0_REGNUM
4007 && regnum
<= tdep
->FV_LAST_REGNUM
))
4008 do_fv_register_info (regnum
);
4010 else if ((regnum
>= tdep
->FV0_C_REGNUM
4011 && regnum
<= tdep
->FV_LAST_C_REGNUM
))
4012 do_fv_c_register_info (regnum
);
4014 else if (regnum
>= tdep
->FPP0_REGNUM
4015 && regnum
<= tdep
->FPP_LAST_REGNUM
)
4016 do_fpp_register_info (regnum
);
4018 else if (regnum
>= tdep
->R0_C_REGNUM
4019 && regnum
<= tdep
->R_LAST_C_REGNUM
)
4020 do_r_c_register_info (regnum
); /* FIXME, this function will not print the right format */
4022 else if (regnum
>= tdep
->FP0_C_REGNUM
4023 && regnum
<= tdep
->FP_LAST_C_REGNUM
)
4024 sh_do_fp_register (regnum
); /* this should work also for pseudoregs */
4026 else if (regnum
>= tdep
->PC_C_REGNUM
4027 && regnum
<= tdep
->FPUL_C_REGNUM
)
4028 do_cr_c_register_info (regnum
);
4033 sh_do_register (int regnum
)
4035 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
4037 fputs_filtered (REGISTER_NAME (regnum
), gdb_stdout
);
4038 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum
)), gdb_stdout
);
4040 /* Get the data in raw format. */
4041 if (!frame_register_read (selected_frame
, regnum
, raw_buffer
))
4042 printf_filtered ("*value not available*\n");
4044 val_print (REGISTER_VIRTUAL_TYPE (regnum
), raw_buffer
, 0, 0,
4045 gdb_stdout
, 'x', 1, 0, Val_pretty_default
);
4046 printf_filtered ("\t");
4047 val_print (REGISTER_VIRTUAL_TYPE (regnum
), raw_buffer
, 0, 0,
4048 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
4049 printf_filtered ("\n");
4053 sh_print_register (int regnum
)
4055 if (regnum
< 0 || regnum
>= NUM_REGS
+ NUM_PSEUDO_REGS
)
4056 internal_error (__FILE__
, __LINE__
,
4057 "Invalid register number %d\n", regnum
);
4059 else if (regnum
>= 0 && regnum
< NUM_REGS
)
4061 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
4062 sh_do_fp_register (regnum
); /* FP regs */
4064 sh_do_register (regnum
); /* All other regs */
4067 else if (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
4068 do_pseudo_register (regnum
);
4072 sh_do_registers_info (int regnum
, int fpregs
)
4074 if (regnum
!= -1) /* do one specified register */
4076 if (*(REGISTER_NAME (regnum
)) == '\0')
4077 error ("Not a valid register for the current processor type");
4079 sh_print_register (regnum
);
4082 /* do all (or most) registers */
4085 while (regnum
< NUM_REGS
)
4087 /* If the register name is empty, it is undefined for this
4088 processor, so don't display anything. */
4089 if (REGISTER_NAME (regnum
) == NULL
4090 || *(REGISTER_NAME (regnum
)) == '\0')
4096 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
4100 /* true for "INFO ALL-REGISTERS" command */
4101 sh_do_fp_register (regnum
); /* FP regs */
4105 regnum
+= (gdbarch_tdep (current_gdbarch
)->FP_LAST_REGNUM
- FP0_REGNUM
); /* skip FP regs */
4109 sh_do_register (regnum
); /* All other regs */
4115 while (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
4117 do_pseudo_register (regnum
);
4124 sh_compact_do_registers_info (int regnum
, int fpregs
)
4126 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4127 if (regnum
!= -1) /* do one specified register */
4129 if (*(REGISTER_NAME (regnum
)) == '\0')
4130 error ("Not a valid register for the current processor type");
4132 if (regnum
>= 0 && regnum
< tdep
->R0_C_REGNUM
)
4133 error ("Not a valid register for the current processor mode.");
4135 sh_print_register (regnum
);
4138 /* do all compact registers */
4140 regnum
= tdep
->R0_C_REGNUM
;
4141 while (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
4143 do_pseudo_register (regnum
);
4150 sh64_do_registers_info (int regnum
, int fpregs
)
4152 if (pc_is_isa32 (selected_frame
->pc
))
4153 sh_do_registers_info (regnum
, fpregs
);
4155 sh_compact_do_registers_info (regnum
, fpregs
);
4158 #ifdef SVR4_SHARED_LIBS
4160 /* Fetch (and possibly build) an appropriate link_map_offsets structure
4161 for native i386 linux targets using the struct offsets defined in
4162 link.h (but without actual reference to that file).
4164 This makes it possible to access i386-linux shared libraries from
4165 a gdb that was not built on an i386-linux host (for cross debugging).
4168 struct link_map_offsets
*
4169 sh_linux_svr4_fetch_link_map_offsets (void)
4171 static struct link_map_offsets lmo
;
4172 static struct link_map_offsets
*lmp
= 0;
4178 lmo
.r_debug_size
= 8; /* 20 not actual size but all we need */
4180 lmo
.r_map_offset
= 4;
4183 lmo
.link_map_size
= 20; /* 552 not actual size but all we need */
4185 lmo
.l_addr_offset
= 0;
4186 lmo
.l_addr_size
= 4;
4188 lmo
.l_name_offset
= 4;
4189 lmo
.l_name_size
= 4;
4191 lmo
.l_next_offset
= 12;
4192 lmo
.l_next_size
= 4;
4194 lmo
.l_prev_offset
= 16;
4195 lmo
.l_prev_size
= 4;
4200 #endif /* SVR4_SHARED_LIBS */
4203 /* This table matches the indices assigned to enum sh_osabi. Keep
4205 static const char * const sh_osabi_names
[] =
4214 process_note_abi_tag_sections (bfd
*abfd
, asection
*sect
, void *obj
)
4216 enum sh_osabi
*os_ident_ptr
= obj
;
4218 unsigned int sectsize
;
4220 name
= bfd_get_section_name (abfd
, sect
);
4221 sectsize
= bfd_section_size (abfd
, sect
);
4223 if (strcmp (name
, ".note.ABI-tag") == 0 && sectsize
> 0)
4225 unsigned int name_length
, data_length
, note_type
;
4228 /* If the section is larger than this, it's probably not what we are
4233 note
= alloca (sectsize
);
4235 bfd_get_section_contents (abfd
, sect
, note
,
4236 (file_ptr
) 0, (bfd_size_type
) sectsize
);
4238 name_length
= bfd_h_get_32 (abfd
, note
);
4239 data_length
= bfd_h_get_32 (abfd
, note
+ 4);
4240 note_type
= bfd_h_get_32 (abfd
, note
+ 8);
4242 if (name_length
== 4 && data_length
== 16 && note_type
== NT_GNU_ABI_TAG
4243 && strcmp (note
+ 12, "GNU") == 0)
4245 int os_number
= bfd_h_get_32 (abfd
, note
+ 16);
4247 /* The case numbers are from abi-tags in glibc. */
4250 case GNU_ABI_TAG_LINUX
:
4251 *os_ident_ptr
= SH_OSABI_LINUX
;
4254 case GNU_ABI_TAG_HURD
:
4256 (__FILE__
, __LINE__
,
4257 "process_note_abi_sections: Hurd objects not supported");
4260 case GNU_ABI_TAG_SOLARIS
:
4262 (__FILE__
, __LINE__
,
4263 "process_note_abi_sections: Solaris objects not supported");
4268 (__FILE__
, __LINE__
,
4269 "process_note_abi_sections: unknown OS number %d",
4274 /* NetBSD uses a similar trick. */
4275 else if (strcmp (name
, ".note.netbsd.ident") == 0 && sectsize
> 0)
4277 unsigned int name_length
, desc_length
, note_type
;
4280 /* If the section is larger than this, it's probably not what we are
4285 note
= alloca (sectsize
);
4287 bfd_get_section_contents (abfd
, sect
, note
,
4288 (file_ptr
) 0, (bfd_size_type
) sectsize
);
4290 name_length
= bfd_h_get_32 (abfd
, note
);
4291 desc_length
= bfd_h_get_32 (abfd
, note
+ 4);
4292 note_type
= bfd_h_get_32 (abfd
, note
+ 8);
4294 if (name_length
== 7 && desc_length
== 4 && note_type
== NT_NETBSD_IDENT
4295 && strcmp (note
+ 12, "NetBSD") == 0)
4296 /* XXX Should we check the version here?
4297 Probably not necessary yet. */
4298 *os_ident_ptr
= SH_OSABI_NETBSD_ELF
;
4303 get_elfosabi (bfd
*abfd
)
4306 enum sh_osabi sh_osabi
= SH_OSABI_UNKNOWN
;
4308 elfosabi
= elf_elfheader (abfd
)->e_ident
[EI_OSABI
];
4313 /* When elfosabi is 0 (ELFOSABI_NONE), this is supposed to indicate
4314 that we're on a SYSV system. However, some systems use note sections
4315 to record OS/ABI info, but leave e_ident[EI_OSABI] zero. So we
4316 have to check the note sections too. */
4317 bfd_map_over_sections (abfd
,
4318 process_note_abi_tag_sections
,
4322 case ELFOSABI_NETBSD
:
4323 sh_osabi
= SH_OSABI_NETBSD_ELF
;
4326 case ELFOSABI_LINUX
:
4327 sh_osabi
= SH_OSABI_LINUX
;
4334 struct sh_osabi_handler
4336 struct sh_osabi_handler
*next
;
4338 void (*init_osabi
)(struct gdbarch_info
, struct gdbarch
*);
4341 struct sh_osabi_handler
*sh_osabi_handler_list
= NULL
;
4344 sh_gdbarch_register_os_abi (enum sh_osabi abi
,
4345 void (*init_osabi
)(struct gdbarch_info
,
4348 struct sh_osabi_handler
**handler_p
;
4350 for (handler_p
= &sh_osabi_handler_list
; *handler_p
!= NULL
;
4351 handler_p
= &(*handler_p
)->next
)
4353 if ((*handler_p
)->abi
== abi
)
4356 (__FILE__
, __LINE__
,
4357 "sh_gdbarch_register_os_abi: A handler for this ABI variant "
4358 "(%d) has already been registered", (int) abi
);
4359 /* If user wants to continue, override previous definition. */
4360 (*handler_p
)->init_osabi
= init_osabi
;
4366 = (struct sh_osabi_handler
*) xmalloc (sizeof (struct sh_osabi_handler
));
4367 (*handler_p
)->next
= NULL
;
4368 (*handler_p
)->abi
= abi
;
4369 (*handler_p
)->init_osabi
= init_osabi
;
4372 static gdbarch_init_ftype sh_gdbarch_init
;
4374 static struct gdbarch
*
4375 sh_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
4377 static LONGEST sh_call_dummy_words
[] = {0};
4378 struct gdbarch
*gdbarch
;
4379 struct gdbarch_tdep
*tdep
;
4380 gdbarch_register_name_ftype
*sh_register_name
;
4381 gdbarch_store_return_value_ftype
*sh_store_return_value
;
4382 gdbarch_register_virtual_type_ftype
*sh_register_virtual_type
;
4383 enum sh_osabi sh_osabi
= SH_OSABI_UNKNOWN
;
4384 struct sh_osabi_handler
*osabi_handler
;
4386 /* Try to determine the ABI of the object we are loading. */
4388 if (info
.abfd
!= NULL
)
4390 switch (bfd_get_flavour (info
.abfd
))
4392 case bfd_target_elf_flavour
:
4393 sh_osabi
= get_elfosabi (info
.abfd
);
4397 /* Just leave it as "unkown". */
4402 /* Find a candidate among the list of pre-declared architectures. */
4403 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
4405 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
4407 /* Make sure the ABI selection matches. */
4408 tdep
= gdbarch_tdep (arches
->gdbarch
);
4409 if (tdep
&& tdep
->sh_osabi
== sh_osabi
)
4410 return arches
->gdbarch
;
4413 /* None found, create a new architecture from the information
4415 tdep
= XMALLOC (struct gdbarch_tdep
);
4416 gdbarch
= gdbarch_alloc (&info
, tdep
);
4418 tdep
->sh_osabi
= sh_osabi
;
4419 if (sh_osabi
< SH_OSABI_INVALID
)
4420 tdep
->osabi_name
= sh_osabi_names
[sh_osabi
];
4423 internal_error (__FILE__
, __LINE__
, "Invalid setting of sh_osabi %d",
4425 tdep
->osabi_name
= "<invalid>";
4428 /* Initialize the register numbers that are not common to all the
4429 variants to -1, if necessary thse will be overwritten in the case
4431 tdep
->FPUL_REGNUM
= -1;
4432 tdep
->FPSCR_REGNUM
= -1;
4433 tdep
->PR_REGNUM
= 17;
4434 tdep
->SR_REGNUM
= 22;
4435 tdep
->DSR_REGNUM
= -1;
4436 tdep
->FP_LAST_REGNUM
= -1;
4437 tdep
->A0G_REGNUM
= -1;
4438 tdep
->A0_REGNUM
= -1;
4439 tdep
->A1G_REGNUM
= -1;
4440 tdep
->A1_REGNUM
= -1;
4441 tdep
->M0_REGNUM
= -1;
4442 tdep
->M1_REGNUM
= -1;
4443 tdep
->X0_REGNUM
= -1;
4444 tdep
->X1_REGNUM
= -1;
4445 tdep
->Y0_REGNUM
= -1;
4446 tdep
->Y1_REGNUM
= -1;
4447 tdep
->MOD_REGNUM
= -1;
4448 tdep
->RS_REGNUM
= -1;
4449 tdep
->RE_REGNUM
= -1;
4450 tdep
->SSR_REGNUM
= -1;
4451 tdep
->SPC_REGNUM
= -1;
4452 tdep
->DR0_REGNUM
= -1;
4453 tdep
->DR_LAST_REGNUM
= -1;
4454 tdep
->FV0_REGNUM
= -1;
4455 tdep
->FV_LAST_REGNUM
= -1;
4456 tdep
->ARG0_REGNUM
= 4;
4457 tdep
->ARGLAST_REGNUM
= 7;
4458 tdep
->RETURN_REGNUM
= 0;
4459 tdep
->FLOAT_ARGLAST_REGNUM
= -1;
4461 tdep
->sh_abi
= SH_ABI_UNKNOWN
;
4463 set_gdbarch_fp0_regnum (gdbarch
, -1);
4464 set_gdbarch_num_pseudo_regs (gdbarch
, 0);
4465 set_gdbarch_max_register_raw_size (gdbarch
, 4);
4466 set_gdbarch_max_register_virtual_size (gdbarch
, 4);
4467 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
4468 set_gdbarch_ptr_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
4469 set_gdbarch_num_regs (gdbarch
, SH_DEFAULT_NUM_REGS
);
4470 set_gdbarch_sp_regnum (gdbarch
, 15);
4471 set_gdbarch_fp_regnum (gdbarch
, 14);
4472 set_gdbarch_pc_regnum (gdbarch
, 16);
4473 set_gdbarch_register_size (gdbarch
, 4);
4474 set_gdbarch_register_bytes (gdbarch
, SH_DEFAULT_NUM_REGS
* 4);
4475 set_gdbarch_do_registers_info (gdbarch
, sh_do_registers_info
);
4476 set_gdbarch_breakpoint_from_pc (gdbarch
, sh_breakpoint_from_pc
);
4477 set_gdbarch_frame_chain (gdbarch
, sh_frame_chain
);
4478 set_gdbarch_get_saved_register (gdbarch
, generic_get_saved_register
);
4479 set_gdbarch_init_extra_frame_info (gdbarch
, sh_init_extra_frame_info
);
4480 set_gdbarch_extract_return_value (gdbarch
, sh_extract_return_value
);
4481 set_gdbarch_push_arguments (gdbarch
, sh_push_arguments
);
4482 set_gdbarch_store_struct_return (gdbarch
, sh_store_struct_return
);
4483 set_gdbarch_use_struct_convention (gdbarch
, sh_use_struct_convention
);
4484 set_gdbarch_extract_struct_value_address (gdbarch
, sh_extract_struct_value_address
);
4485 set_gdbarch_pop_frame (gdbarch
, sh_pop_frame
);
4486 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_sh
);
4487 skip_prologue_hard_way
= sh_skip_prologue_hard_way
;
4488 do_pseudo_register
= sh_do_pseudo_register
;
4490 switch (info
.bfd_arch_info
->mach
)
4493 sh_register_name
= sh_sh_register_name
;
4494 sh_show_regs
= sh_generic_show_regs
;
4495 sh_store_return_value
= sh_default_store_return_value
;
4496 sh_register_virtual_type
= sh_default_register_virtual_type
;
4497 set_gdbarch_frame_init_saved_regs (gdbarch
, sh_nofp_frame_init_saved_regs
);
4498 set_gdbarch_register_raw_size (gdbarch
, sh_default_register_raw_size
);
4499 set_gdbarch_register_virtual_size (gdbarch
, sh_default_register_raw_size
);
4500 set_gdbarch_register_byte (gdbarch
, sh_default_register_byte
);
4503 sh_register_name
= sh_sh_register_name
;
4504 sh_show_regs
= sh_generic_show_regs
;
4505 sh_store_return_value
= sh_default_store_return_value
;
4506 sh_register_virtual_type
= sh_default_register_virtual_type
;
4507 set_gdbarch_frame_init_saved_regs (gdbarch
, sh_nofp_frame_init_saved_regs
);
4508 set_gdbarch_register_raw_size (gdbarch
, sh_default_register_raw_size
);
4509 set_gdbarch_register_virtual_size (gdbarch
, sh_default_register_raw_size
);
4510 set_gdbarch_register_byte (gdbarch
, sh_default_register_byte
);
4512 case bfd_mach_sh_dsp
:
4513 sh_register_name
= sh_sh_dsp_register_name
;
4514 sh_show_regs
= sh_dsp_show_regs
;
4515 sh_store_return_value
= sh_default_store_return_value
;
4516 sh_register_virtual_type
= sh_default_register_virtual_type
;
4517 set_gdbarch_frame_init_saved_regs (gdbarch
, sh_nofp_frame_init_saved_regs
);
4518 set_gdbarch_register_raw_size (gdbarch
, sh_default_register_raw_size
);
4519 set_gdbarch_register_virtual_size (gdbarch
, sh_default_register_raw_size
);
4520 set_gdbarch_register_byte (gdbarch
, sh_default_register_byte
);
4521 tdep
->DSR_REGNUM
= 24;
4522 tdep
->A0G_REGNUM
= 25;
4523 tdep
->A0_REGNUM
= 26;
4524 tdep
->A1G_REGNUM
= 27;
4525 tdep
->A1_REGNUM
= 28;
4526 tdep
->M0_REGNUM
= 29;
4527 tdep
->M1_REGNUM
= 30;
4528 tdep
->X0_REGNUM
= 31;
4529 tdep
->X1_REGNUM
= 32;
4530 tdep
->Y0_REGNUM
= 33;
4531 tdep
->Y1_REGNUM
= 34;
4532 tdep
->MOD_REGNUM
= 40;
4533 tdep
->RS_REGNUM
= 43;
4534 tdep
->RE_REGNUM
= 44;
4537 sh_register_name
= sh_sh3_register_name
;
4538 sh_show_regs
= sh3_show_regs
;
4539 sh_store_return_value
= sh_default_store_return_value
;
4540 sh_register_virtual_type
= sh_default_register_virtual_type
;
4541 set_gdbarch_frame_init_saved_regs (gdbarch
, sh_nofp_frame_init_saved_regs
);
4542 set_gdbarch_register_raw_size (gdbarch
, sh_default_register_raw_size
);
4543 set_gdbarch_register_virtual_size (gdbarch
, sh_default_register_raw_size
);
4544 set_gdbarch_register_byte (gdbarch
, sh_default_register_byte
);
4545 tdep
->SSR_REGNUM
= 41;
4546 tdep
->SPC_REGNUM
= 42;
4549 sh_register_name
= sh_sh3e_register_name
;
4550 sh_show_regs
= sh3e_show_regs
;
4551 sh_store_return_value
= sh3e_sh4_store_return_value
;
4552 sh_register_virtual_type
= sh_sh3e_register_virtual_type
;
4553 set_gdbarch_frame_init_saved_regs (gdbarch
, sh_fp_frame_init_saved_regs
);
4554 set_gdbarch_register_raw_size (gdbarch
, sh_default_register_raw_size
);
4555 set_gdbarch_register_virtual_size (gdbarch
, sh_default_register_raw_size
);
4556 set_gdbarch_register_byte (gdbarch
, sh_default_register_byte
);
4557 set_gdbarch_extract_return_value (gdbarch
, sh3e_sh4_extract_return_value
);
4558 set_gdbarch_fp0_regnum (gdbarch
, 25);
4559 tdep
->FPUL_REGNUM
= 23;
4560 tdep
->FPSCR_REGNUM
= 24;
4561 tdep
->FP_LAST_REGNUM
= 40;
4562 tdep
->SSR_REGNUM
= 41;
4563 tdep
->SPC_REGNUM
= 42;
4565 case bfd_mach_sh3_dsp
:
4566 sh_register_name
= sh_sh3_dsp_register_name
;
4567 sh_show_regs
= sh3_dsp_show_regs
;
4568 sh_store_return_value
= sh_default_store_return_value
;
4569 sh_register_virtual_type
= sh_default_register_virtual_type
;
4570 set_gdbarch_frame_init_saved_regs (gdbarch
, sh_nofp_frame_init_saved_regs
);
4571 set_gdbarch_register_raw_size (gdbarch
, sh_default_register_raw_size
);
4572 set_gdbarch_register_virtual_size (gdbarch
, sh_default_register_raw_size
);
4573 set_gdbarch_register_byte (gdbarch
, sh_default_register_byte
);
4574 tdep
->DSR_REGNUM
= 24;
4575 tdep
->A0G_REGNUM
= 25;
4576 tdep
->A0_REGNUM
= 26;
4577 tdep
->A1G_REGNUM
= 27;
4578 tdep
->A1_REGNUM
= 28;
4579 tdep
->M0_REGNUM
= 29;
4580 tdep
->M1_REGNUM
= 30;
4581 tdep
->X0_REGNUM
= 31;
4582 tdep
->X1_REGNUM
= 32;
4583 tdep
->Y0_REGNUM
= 33;
4584 tdep
->Y1_REGNUM
= 34;
4585 tdep
->MOD_REGNUM
= 40;
4586 tdep
->RS_REGNUM
= 43;
4587 tdep
->RE_REGNUM
= 44;
4588 tdep
->SSR_REGNUM
= 41;
4589 tdep
->SPC_REGNUM
= 42;
4592 sh_register_name
= sh_sh4_register_name
;
4593 sh_show_regs
= sh4_show_regs
;
4594 sh_store_return_value
= sh3e_sh4_store_return_value
;
4595 sh_register_virtual_type
= sh_sh4_register_virtual_type
;
4596 set_gdbarch_frame_init_saved_regs (gdbarch
, sh_fp_frame_init_saved_regs
);
4597 set_gdbarch_extract_return_value (gdbarch
, sh3e_sh4_extract_return_value
);
4598 set_gdbarch_fp0_regnum (gdbarch
, 25);
4599 set_gdbarch_register_raw_size (gdbarch
, sh_sh4_register_raw_size
);
4600 set_gdbarch_register_virtual_size (gdbarch
, sh_sh4_register_raw_size
);
4601 set_gdbarch_register_byte (gdbarch
, sh_sh4_register_byte
);
4602 set_gdbarch_num_pseudo_regs (gdbarch
, 12);
4603 set_gdbarch_max_register_raw_size (gdbarch
, 4 * 4);
4604 set_gdbarch_max_register_virtual_size (gdbarch
, 4 * 4);
4605 set_gdbarch_register_read (gdbarch
, sh4_register_read
);
4606 set_gdbarch_register_write (gdbarch
, sh4_register_write
);
4607 tdep
->FPUL_REGNUM
= 23;
4608 tdep
->FPSCR_REGNUM
= 24;
4609 tdep
->FP_LAST_REGNUM
= 40;
4610 tdep
->SSR_REGNUM
= 41;
4611 tdep
->SPC_REGNUM
= 42;
4612 tdep
->DR0_REGNUM
= 59;
4613 tdep
->DR_LAST_REGNUM
= 66;
4614 tdep
->FV0_REGNUM
= 67;
4615 tdep
->FV_LAST_REGNUM
= 70;
4618 tdep
->PR_REGNUM
= 18;
4619 tdep
->SR_REGNUM
= 65;
4620 tdep
->FPSCR_REGNUM
= SIM_SH64_FPCSR_REGNUM
;
4621 tdep
->FP_LAST_REGNUM
= SIM_SH64_FR0_REGNUM
+ SIM_SH64_NR_FP_REGS
- 1;
4622 tdep
->SSR_REGNUM
= SIM_SH64_SSR_REGNUM
;
4623 tdep
->SPC_REGNUM
= SIM_SH64_SPC_REGNUM
;
4624 tdep
->TR7_REGNUM
= SIM_SH64_TR0_REGNUM
+ 7;
4625 tdep
->FPP0_REGNUM
= 173;
4626 tdep
->FPP_LAST_REGNUM
= 204;
4627 tdep
->DR0_REGNUM
= 141;
4628 tdep
->DR_LAST_REGNUM
= 172;
4629 tdep
->FV0_REGNUM
= 205;
4630 tdep
->FV_LAST_REGNUM
= 220;
4631 tdep
->R0_C_REGNUM
= 221;
4632 tdep
->R_LAST_C_REGNUM
= 236;
4633 tdep
->PC_C_REGNUM
= 237;
4634 tdep
->GBR_C_REGNUM
= 238;
4635 tdep
->MACH_C_REGNUM
= 239;
4636 tdep
->MACL_C_REGNUM
= 240;
4637 tdep
->PR_C_REGNUM
= 241;
4638 tdep
->T_C_REGNUM
= 242;
4639 tdep
->FPSCR_C_REGNUM
= 243;
4640 tdep
->FPUL_C_REGNUM
= 244;
4641 tdep
->FP0_C_REGNUM
= 245;
4642 tdep
->FP_LAST_C_REGNUM
= 260;
4643 tdep
->DR0_C_REGNUM
= 261;
4644 tdep
->DR_LAST_C_REGNUM
= 268;
4645 tdep
->FV0_C_REGNUM
= 269;
4646 tdep
->FV_LAST_C_REGNUM
= 272;
4647 tdep
->ARG0_REGNUM
= 2;
4648 tdep
->ARGLAST_REGNUM
= 9;
4649 tdep
->RETURN_REGNUM
= 2;
4650 tdep
->FLOAT_ARGLAST_REGNUM
= 11;
4652 set_gdbarch_num_pseudo_regs (gdbarch
, NUM_PSEUDO_REGS_SH_MEDIA
+ NUM_PSEUDO_REGS_SH_COMPACT
);
4653 set_gdbarch_fp0_regnum (gdbarch
, SIM_SH64_FR0_REGNUM
);
4654 set_gdbarch_pc_regnum (gdbarch
, 64);
4656 /* Determine the ABI */
4657 if (bfd_get_arch_size (info
.abfd
) == 64)
4659 /* If the ABI is the 64-bit one, it can only be sh-media. */
4660 tdep
->sh_abi
= SH_ABI_64
;
4661 set_gdbarch_ptr_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
4662 set_gdbarch_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
4666 /* If the ABI is the 32-bit one it could be either media or
4668 tdep
->sh_abi
= SH_ABI_32
;
4669 set_gdbarch_ptr_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
4670 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
4673 /* the number of real registers is the same whether we are in
4674 ISA16(compact) or ISA32(media). */
4675 set_gdbarch_num_regs (gdbarch
, SIM_SH64_NR_REGS
);
4676 set_gdbarch_register_size (gdbarch
, 8); /*????*/
4677 set_gdbarch_register_bytes (gdbarch
,
4678 ((SIM_SH64_NR_FP_REGS
+ 1) * 4)
4679 + (SIM_SH64_NR_REGS
- SIM_SH64_NR_FP_REGS
-1) * 8);
4681 sh_register_name
= sh_sh64_register_name
;
4682 sh_show_regs
= sh64_show_regs
;
4683 sh_register_virtual_type
= sh_sh64_register_virtual_type
;
4684 sh_store_return_value
= sh64_store_return_value
;
4685 skip_prologue_hard_way
= sh64_skip_prologue_hard_way
;
4686 do_pseudo_register
= sh64_do_pseudo_register
;
4687 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_sh64
);
4688 set_gdbarch_register_raw_size (gdbarch
, sh_sh64_register_raw_size
);
4689 set_gdbarch_register_virtual_size (gdbarch
, sh_sh64_register_raw_size
);
4690 set_gdbarch_register_byte (gdbarch
, sh_sh64_register_byte
);
4691 /* This seems awfully wrong!*/
4692 /*set_gdbarch_max_register_raw_size (gdbarch, 8);*/
4693 /* should include the size of the pseudo regs. */
4694 set_gdbarch_max_register_raw_size (gdbarch
, 4 * 4);
4695 /* Or should that go in the virtual_size? */
4696 /*set_gdbarch_max_register_virtual_size (gdbarch, 8);*/
4697 set_gdbarch_max_register_virtual_size (gdbarch
, 4 * 4);
4698 set_gdbarch_register_read (gdbarch
, sh64_register_read
);
4699 set_gdbarch_register_write (gdbarch
, sh64_register_write
);
4701 set_gdbarch_do_registers_info (gdbarch
, sh64_do_registers_info
);
4702 set_gdbarch_frame_init_saved_regs (gdbarch
, sh64_nofp_frame_init_saved_regs
);
4703 set_gdbarch_breakpoint_from_pc (gdbarch
, sh_sh64_breakpoint_from_pc
);
4704 set_gdbarch_init_extra_frame_info (gdbarch
, sh64_init_extra_frame_info
);
4705 set_gdbarch_frame_chain (gdbarch
, sh64_frame_chain
);
4706 set_gdbarch_get_saved_register (gdbarch
, sh64_get_saved_register
);
4707 set_gdbarch_extract_return_value (gdbarch
, sh64_extract_return_value
);
4708 set_gdbarch_push_arguments (gdbarch
, sh64_push_arguments
);
4709 /*set_gdbarch_store_struct_return (gdbarch, sh64_store_struct_return);*/
4710 set_gdbarch_extract_struct_value_address (gdbarch
, sh64_extract_struct_value_address
);
4711 set_gdbarch_use_struct_convention (gdbarch
, sh64_use_struct_convention
);
4712 set_gdbarch_pop_frame (gdbarch
, sh64_pop_frame
);
4713 set_gdbarch_elf_make_msymbol_special (gdbarch
,
4714 sh64_elf_make_msymbol_special
);
4717 sh_register_name
= sh_generic_register_name
;
4718 sh_show_regs
= sh_generic_show_regs
;
4719 sh_store_return_value
= sh_default_store_return_value
;
4720 sh_register_virtual_type
= sh_default_register_virtual_type
;
4721 set_gdbarch_frame_init_saved_regs (gdbarch
, sh_nofp_frame_init_saved_regs
);
4722 set_gdbarch_register_raw_size (gdbarch
, sh_default_register_raw_size
);
4723 set_gdbarch_register_virtual_size (gdbarch
, sh_default_register_raw_size
);
4724 set_gdbarch_register_byte (gdbarch
, sh_default_register_byte
);
4728 set_gdbarch_read_pc (gdbarch
, generic_target_read_pc
);
4729 set_gdbarch_write_pc (gdbarch
, generic_target_write_pc
);
4730 set_gdbarch_read_fp (gdbarch
, generic_target_read_fp
);
4731 set_gdbarch_read_sp (gdbarch
, generic_target_read_sp
);
4732 set_gdbarch_write_sp (gdbarch
, generic_target_write_sp
);
4734 set_gdbarch_register_name (gdbarch
, sh_register_name
);
4735 set_gdbarch_register_virtual_type (gdbarch
, sh_register_virtual_type
);
4737 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
4738 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
4739 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
4740 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
4741 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
4742 set_gdbarch_long_double_bit (gdbarch
, 16 * TARGET_CHAR_BIT
);/*??should be 8?*/
4744 set_gdbarch_use_generic_dummy_frames (gdbarch
, 1);
4745 set_gdbarch_call_dummy_length (gdbarch
, 0);
4746 set_gdbarch_call_dummy_location (gdbarch
, AT_ENTRY_POINT
);
4747 set_gdbarch_call_dummy_address (gdbarch
, entry_point_address
);
4748 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch
, 1); /*???*/
4749 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0);
4750 set_gdbarch_call_dummy_start_offset (gdbarch
, 0);
4751 set_gdbarch_pc_in_call_dummy (gdbarch
, generic_pc_in_call_dummy
);
4752 set_gdbarch_call_dummy_words (gdbarch
, sh_call_dummy_words
);
4753 set_gdbarch_sizeof_call_dummy_words (gdbarch
, sizeof (sh_call_dummy_words
));
4754 set_gdbarch_call_dummy_p (gdbarch
, 1);
4755 set_gdbarch_call_dummy_stack_adjust_p (gdbarch
, 0);
4756 set_gdbarch_fix_call_dummy (gdbarch
, generic_fix_call_dummy
);
4757 set_gdbarch_coerce_float_to_double (gdbarch
,
4758 sh_coerce_float_to_double
);
4760 set_gdbarch_push_dummy_frame (gdbarch
, generic_push_dummy_frame
);
4761 set_gdbarch_push_return_address (gdbarch
, sh_push_return_address
);
4763 set_gdbarch_store_return_value (gdbarch
, sh_store_return_value
);
4764 set_gdbarch_skip_prologue (gdbarch
, sh_skip_prologue
);
4765 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
4766 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
4767 set_gdbarch_function_start_offset (gdbarch
, 0);
4769 set_gdbarch_frame_args_skip (gdbarch
, 0);
4770 set_gdbarch_frameless_function_invocation (gdbarch
, frameless_look_for_prologue
);
4771 set_gdbarch_frame_chain_valid (gdbarch
, generic_file_frame_chain_valid
);
4772 set_gdbarch_frame_saved_pc (gdbarch
, sh_frame_saved_pc
);
4773 set_gdbarch_frame_args_address (gdbarch
, default_frame_address
);
4774 set_gdbarch_frame_locals_address (gdbarch
, default_frame_address
);
4775 set_gdbarch_saved_pc_after_call (gdbarch
, sh_saved_pc_after_call
);
4776 set_gdbarch_frame_num_args (gdbarch
, frame_num_args_unknown
);
4777 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
4779 /* Hook in ABI-specific overrides, if they have been registered. If
4780 the ABI is unknown, this is probably an embedded target, so we
4781 should not warn about this situation. */
4782 if (sh_osabi
!= SH_OSABI_UNKNOWN
)
4784 for (osabi_handler
= sh_osabi_handler_list
; osabi_handler
!= NULL
;
4785 osabi_handler
= osabi_handler
->next
)
4786 if (osabi_handler
->abi
== sh_osabi
)
4790 osabi_handler
->init_osabi (info
, gdbarch
);
4793 /* We assume that if GDB_MULTI_ARCH is less than
4794 GDB_MULTI_ARCH_TM that an ABI variant can be supported by
4795 overriding definitions in this file. */
4796 if (GDB_MULTI_ARCH
> GDB_MULTI_ARCH_PARTIAL
)
4799 "A handler for the ABI variant \"%s\" is not built into this "
4800 "configuration of GDB. "
4801 "Attempting to continue with the default SuperH settings",
4802 sh_osabi_names
[sh_osabi
]);
4810 sh_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
4812 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4817 if (tdep
->osabi_name
!= NULL
)
4818 fprintf_unfiltered (file
, "sh_dump_tdep: OS ABI = %s\n", tdep
->osabi_name
);
4820 internal_error (__FILE__
, __LINE__
,
4821 "sh_dump_tdep: illegal setting of tdep->sh_osabi (%d)",
4822 (int) tdep
->sh_osabi
);
4826 _initialize_sh_tdep (void)
4828 struct cmd_list_element
*c
;
4830 gdbarch_register (bfd_arch_sh
, sh_gdbarch_init
, sh_dump_tdep
);
4832 add_com ("regs", class_vars
, sh_show_regs_command
, "Print all registers");