projects / binutils-gdb.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
* sh-tdep.c (SH_NUM_REGS): Define as 67.
[binutils-gdb.git] / gdb / sh-tdep.c
1 /* Target-dependent code for Renesas Super-H, for GDB.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004 Free Software Foundation, Inc.
4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
21
22 /*
23 Contributed by Steve Chamberlain
24 sac@cygnus.com
25 */
26
27 #include "defs.h"
28 #include "frame.h"
29 #include "frame-base.h"
30 #include "frame-unwind.h"
31 #include "dwarf2-frame.h"
32 #include "symtab.h"
33 #include "gdbtypes.h"
34 #include "gdbcmd.h"
35 #include "gdbcore.h"
36 #include "value.h"
37 #include "dis-asm.h"
38 #include "inferior.h"
39 #include "gdb_string.h"
40 #include "gdb_assert.h"
41 #include "arch-utils.h"
42 #include "floatformat.h"
43 #include "regcache.h"
44 #include "doublest.h"
45 #include "osabi.h"
46
47 #include "sh-tdep.h"
48
49 #include "elf-bfd.h"
50 #include "solib-svr4.h"
51
52 /* sh flags */
53 #include "elf/sh.h"
54 /* registers numbers shared with the simulator */
55 #include "gdb/sim-sh.h"
56
57 static void (*sh_show_regs) (void);
58
59 #define SH_NUM_REGS 67
60
61 struct sh_frame_cache
62 {
63 /* Base address. */
64 CORE_ADDR base;
65 LONGEST sp_offset;
66 CORE_ADDR pc;
67
68 /* Flag showing that a frame has been created in the prologue code. */
69 int uses_fp;
70
71 /* Saved registers. */
72 CORE_ADDR saved_regs[SH_NUM_REGS];
73 CORE_ADDR saved_sp;
74 };
75
76 static const char *
77 sh_sh_register_name (int reg_nr)
78 {
79 static char *register_names[] = {
80 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
81 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
82 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
83 "", "",
84 "", "", "", "", "", "", "", "",
85 "", "", "", "", "", "", "", "",
86 "", "",
87 "", "", "", "", "", "", "", "",
88 "", "", "", "", "", "", "", "",
89 "", "", "", "", "", "", "", "",
90 };
91 if (reg_nr < 0)
92 return NULL;
93 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
94 return NULL;
95 return register_names[reg_nr];
96 }
97
98 static const char *
99 sh_sh3_register_name (int reg_nr)
100 {
101 static char *register_names[] = {
102 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
103 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
104 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
105 "", "",
106 "", "", "", "", "", "", "", "",
107 "", "", "", "", "", "", "", "",
108 "ssr", "spc",
109 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
110 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
111 "", "", "", "", "", "", "", "",
112 };
113 if (reg_nr < 0)
114 return NULL;
115 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
116 return NULL;
117 return register_names[reg_nr];
118 }
119
120 static const char *
121 sh_sh3e_register_name (int reg_nr)
122 {
123 static char *register_names[] = {
124 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
125 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
126 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
127 "fpul", "fpscr",
128 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
129 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
130 "ssr", "spc",
131 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
132 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
133 "", "", "", "", "", "", "", "",
134 };
135 if (reg_nr < 0)
136 return NULL;
137 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
138 return NULL;
139 return register_names[reg_nr];
140 }
141
142 static const char *
143 sh_sh2e_register_name (int reg_nr)
144 {
145 static char *register_names[] = {
146 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
147 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
148 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
149 "fpul", "fpscr",
150 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
151 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
152 "", "",
153 "", "", "", "", "", "", "", "",
154 "", "", "", "", "", "", "", "",
155 "", "", "", "", "", "", "", "",
156 };
157 if (reg_nr < 0)
158 return NULL;
159 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
160 return NULL;
161 return register_names[reg_nr];
162 }
163
164 static const char *
165 sh_sh2a_register_name (int reg_nr)
166 {
167 static char *register_names[] = {
168 /* general registers 0-15 */
169 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
170 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
171 /* 16 - 22 */
172 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
173 /* 23, 24 */
174 "fpul", "fpscr",
175 /* floating point registers 25 - 40 */
176 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
177 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
178 /* 41, 42 */
179 "", "",
180 /* 43 - 62. Banked registers. The bank number used is determined by
181 the bank register (63). */
182 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
183 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
184 "machb", "ivnb", "prb", "gbrb", "maclb",
185 /* 63: register bank number, not a real register but used to
186 communicate the register bank currently get/set. This register
187 is hidden to the user, who manipulates it using the pseudo
188 register called "bank" (67). See below. */
189 "",
190 /* 64 - 66 */
191 "ibcr", "ibnr", "tbr",
192 /* 67: register bank number, the user visible pseudo register. */
193 "bank",
194 /* double precision (pseudo) 68 - 75 */
195 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
196 };
197 if (reg_nr < 0)
198 return NULL;
199 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
200 return NULL;
201 return register_names[reg_nr];
202 }
203
204 static const char *
205 sh_sh2a_nofpu_register_name (int reg_nr)
206 {
207 static char *register_names[] = {
208 /* general registers 0-15 */
209 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
210 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
211 /* 16 - 22 */
212 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
213 /* 23, 24 */
214 "", "",
215 /* floating point registers 25 - 40 */
216 "", "", "", "", "", "", "", "",
217 "", "", "", "", "", "", "", "",
218 /* 41, 42 */
219 "", "",
220 /* 43 - 62. Banked registers. The bank number used is determined by
221 the bank register (63). */
222 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
223 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
224 "machb", "ivnb", "prb", "gbrb", "maclb",
225 /* 63: register bank number, not a real register but used to
226 communicate the register bank currently get/set. This register
227 is hidden to the user, who manipulates it using the pseudo
228 register called "bank" (67). See below. */
229 "",
230 /* 64 - 66 */
231 "ibcr", "ibnr", "tbr",
232 /* 67: register bank number, the user visible pseudo register. */
233 "bank",
234 /* double precision (pseudo) 68 - 75 */
235 "", "", "", "", "", "", "", "",
236 };
237 if (reg_nr < 0)
238 return NULL;
239 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
240 return NULL;
241 return register_names[reg_nr];
242 }
243
244 static const char *
245 sh_sh_dsp_register_name (int reg_nr)
246 {
247 static char *register_names[] = {
248 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
249 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
250 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
251 "", "dsr",
252 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
253 "y0", "y1", "", "", "", "", "", "mod",
254 "", "",
255 "rs", "re", "", "", "", "", "", "",
256 "", "", "", "", "", "", "", "",
257 "", "", "", "", "", "", "", "",
258 };
259 if (reg_nr < 0)
260 return NULL;
261 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
262 return NULL;
263 return register_names[reg_nr];
264 }
265
266 static const char *
267 sh_sh3_dsp_register_name (int reg_nr)
268 {
269 static char *register_names[] = {
270 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
271 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
272 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
273 "", "dsr",
274 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
275 "y0", "y1", "", "", "", "", "", "mod",
276 "ssr", "spc",
277 "rs", "re", "", "", "", "", "", "",
278 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
279 "", "", "", "", "", "", "", "",
280 "", "", "", "", "", "", "", "",
281 };
282 if (reg_nr < 0)
283 return NULL;
284 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
285 return NULL;
286 return register_names[reg_nr];
287 }
288
289 static const char *
290 sh_sh4_register_name (int reg_nr)
291 {
292 static char *register_names[] = {
293 /* general registers 0-15 */
294 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
295 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
296 /* 16 - 22 */
297 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
298 /* 23, 24 */
299 "fpul", "fpscr",
300 /* floating point registers 25 - 40 */
301 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
302 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
303 /* 41, 42 */
304 "ssr", "spc",
305 /* bank 0 43 - 50 */
306 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
307 /* bank 1 51 - 58 */
308 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
309 "", "", "", "", "", "", "", "",
310 /* pseudo bank register. */
311 "",
312 /* double precision (pseudo) 59 - 66 */
313 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
314 /* vectors (pseudo) 67 - 70 */
315 "fv0", "fv4", "fv8", "fv12",
316 /* FIXME: missing XF 71 - 86 */
317 /* FIXME: missing XD 87 - 94 */
318 };
319 if (reg_nr < 0)
320 return NULL;
321 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
322 return NULL;
323 return register_names[reg_nr];
324 }
325
326 static const char *
327 sh_sh4_nofpu_register_name (int reg_nr)
328 {
329 static char *register_names[] = {
330 /* general registers 0-15 */
331 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
332 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
333 /* 16 - 22 */
334 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
335 /* 23, 24 */
336 "", "",
337 /* floating point registers 25 - 40 -- not for nofpu target */
338 "", "", "", "", "", "", "", "",
339 "", "", "", "", "", "", "", "",
340 /* 41, 42 */
341 "ssr", "spc",
342 /* bank 0 43 - 50 */
343 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
344 /* bank 1 51 - 58 */
345 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
346 "", "", "", "", "", "", "", "",
347 /* pseudo bank register. */
348 "",
349 /* double precision (pseudo) 59 - 66 -- not for nofpu target */
350 "", "", "", "", "", "", "", "",
351 /* vectors (pseudo) 67 - 70 -- not for nofpu target */
352 "", "", "", "",
353 };
354 if (reg_nr < 0)
355 return NULL;
356 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
357 return NULL;
358 return register_names[reg_nr];
359 }
360
361 static const char *
362 sh_sh4al_dsp_register_name (int reg_nr)
363 {
364 static char *register_names[] = {
365 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
366 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
367 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
368 "", "dsr",
369 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
370 "y0", "y1", "", "", "", "", "", "mod",
371 "ssr", "spc",
372 "rs", "re", "", "", "", "", "", "",
373 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
374 "", "", "", "", "", "", "", "",
375 "", "", "", "", "", "", "", "",
376 };
377 if (reg_nr < 0)
378 return NULL;
379 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
380 return NULL;
381 return register_names[reg_nr];
382 }
383
384 static const unsigned char *
385 sh_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
386 {
387 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */
388 static unsigned char breakpoint[] = { 0xc3, 0xc3 };
389
390 *lenptr = sizeof (breakpoint);
391 return breakpoint;
392 }
393
394 /* Prologue looks like
395 mov.l r14,@-r15
396 sts.l pr,@-r15
397 mov.l <regs>,@-r15
398 sub <room_for_loca_vars>,r15
399 mov r15,r14
400
401 Actually it can be more complicated than this but that's it, basically.
402 */
403
404 #define GET_SOURCE_REG(x) (((x) >> 4) & 0xf)
405 #define GET_TARGET_REG(x) (((x) >> 8) & 0xf)
406
407 /* JSR @Rm 0100mmmm00001011 */
408 #define IS_JSR(x) (((x) & 0xf0ff) == 0x400b)
409
410 /* STS.L PR,@-r15 0100111100100010
411 r15-4-->r15, PR-->(r15) */
412 #define IS_STS(x) ((x) == 0x4f22)
413
414 /* MOV.L Rm,@-r15 00101111mmmm0110
415 r15-4-->r15, Rm-->(R15) */
416 #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
417
418 /* MOV r15,r14 0110111011110011
419 r15-->r14 */
420 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
421
422 /* ADD #imm,r15 01111111iiiiiiii
423 r15+imm-->r15 */
424 #define IS_ADD_IMM_SP(x) (((x) & 0xff00) == 0x7f00)
425
426 #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
427 #define IS_SHLL_R3(x) ((x) == 0x4300)
428
429 /* ADD r3,r15 0011111100111100
430 r15+r3-->r15 */
431 #define IS_ADD_R3SP(x) ((x) == 0x3f3c)
432
433 /* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
434 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
435 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
436 /* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to
437 make this entirely clear. */
438 /* #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b) */
439 #define IS_FPUSH(x) (((x) & 0xff0f) == 0xff0b)
440
441 /* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011 4 <= m <= 7 */
442 #define IS_MOV_ARG_TO_REG(x) \
443 (((x) & 0xf00f) == 0x6003 && \
444 ((x) & 0x00f0) >= 0x0040 && \
445 ((x) & 0x00f0) <= 0x0070)
446 /* MOV.L Rm,@Rn 0010nnnnmmmm0010 n = 14, 4 <= m <= 7 */
447 #define IS_MOV_ARG_TO_IND_R14(x) \
448 (((x) & 0xff0f) == 0x2e02 && \
449 ((x) & 0x00f0) >= 0x0040 && \
450 ((x) & 0x00f0) <= 0x0070)
451 /* MOV.L Rm,@(disp*4,Rn) 00011110mmmmdddd n = 14, 4 <= m <= 7 */
452 #define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \
453 (((x) & 0xff00) == 0x1e00 && \
454 ((x) & 0x00f0) >= 0x0040 && \
455 ((x) & 0x00f0) <= 0x0070)
456
457 /* MOV.W @(disp*2,PC),Rn 1001nnnndddddddd */
458 #define IS_MOVW_PCREL_TO_REG(x) (((x) & 0xf000) == 0x9000)
459 /* MOV.L @(disp*4,PC),Rn 1101nnnndddddddd */
460 #define IS_MOVL_PCREL_TO_REG(x) (((x) & 0xf000) == 0xd000)
461 /* SUB Rn,R15 00111111nnnn1000 */
462 #define IS_SUB_REG_FROM_SP(x) (((x) & 0xff0f) == 0x3f08)
463
464 #define FPSCR_SZ (1 << 20)
465
466 /* The following instructions are used for epilogue testing. */
467 #define IS_RESTORE_FP(x) ((x) == 0x6ef6)
468 #define IS_RTS(x) ((x) == 0x000b)
469 #define IS_LDS(x) ((x) == 0x4f26)
470 #define IS_MOV_FP_SP(x) ((x) == 0x6fe3)
471 #define IS_ADD_REG_TO_FP(x) (((x) & 0xff0f) == 0x3e0c)
472 #define IS_ADD_IMM_FP(x) (((x) & 0xff00) == 0x7e00)
473
474 /* Disassemble an instruction. */
475 static int
476 gdb_print_insn_sh (bfd_vma memaddr, disassemble_info * info)
477 {
478 info->endian = TARGET_BYTE_ORDER;
479 return print_insn_sh (memaddr, info);
480 }
481
482 static CORE_ADDR
483 sh_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc,
484 struct sh_frame_cache *cache)
485 {
486 ULONGEST inst;
487 CORE_ADDR opc;
488 int offset;
489 int sav_offset = 0;
490 int r3_val = 0;
491 int reg, sav_reg = -1;
492
493 if (pc >= current_pc)
494 return current_pc;
495
496 cache->uses_fp = 0;
497 for (opc = pc + (2 * 28); pc < opc; pc += 2)
498 {
499 inst = read_memory_unsigned_integer (pc, 2);
500 /* See where the registers will be saved to */
501 if (IS_PUSH (inst))
502 {
503 cache->saved_regs[GET_SOURCE_REG (inst)] = cache->sp_offset;
504 cache->sp_offset += 4;
505 }
506 else if (IS_STS (inst))
507 {
508 cache->saved_regs[PR_REGNUM] = cache->sp_offset;
509 cache->sp_offset += 4;
510 }
511 else if (IS_MOV_R3 (inst))
512 {
513 r3_val = ((inst & 0xff) ^ 0x80) - 0x80;
514 }
515 else if (IS_SHLL_R3 (inst))
516 {
517 r3_val <<= 1;
518 }
519 else if (IS_ADD_R3SP (inst))
520 {
521 cache->sp_offset += -r3_val;
522 }
523 else if (IS_ADD_IMM_SP (inst))
524 {
525 offset = ((inst & 0xff) ^ 0x80) - 0x80;
526 cache->sp_offset -= offset;
527 }
528 else if (IS_MOVW_PCREL_TO_REG (inst))
529 {
530 if (sav_reg < 0)
531 {
532 reg = GET_TARGET_REG (inst);
533 if (reg < 14)
534 {
535 sav_reg = reg;
536 offset = (inst & 0xff) << 1;
537 sav_offset =
538 read_memory_integer ((pc + 4) + offset, 2);
539 }
540 }
541 }
542 else if (IS_MOVL_PCREL_TO_REG (inst))
543 {
544 if (sav_reg < 0)
545 {
546 reg = GET_TARGET_REG (inst);
547 if (reg < 14)
548 {
549 sav_reg = reg;
550 offset = (inst & 0xff) << 2;
551 sav_offset =
552 read_memory_integer (((pc & 0xfffffffc) + 4) + offset, 4);
553 }
554 }
555 }
556 else if (IS_SUB_REG_FROM_SP (inst))
557 {
558 reg = GET_SOURCE_REG (inst);
559 if (sav_reg > 0 && reg == sav_reg)
560 {
561 sav_reg = -1;
562 }
563 cache->sp_offset += sav_offset;
564 }
565 else if (IS_FPUSH (inst))
566 {
567 if (read_register (FPSCR_REGNUM) & FPSCR_SZ)
568 {
569 cache->sp_offset += 8;
570 }
571 else
572 {
573 cache->sp_offset += 4;
574 }
575 }
576 else if (IS_MOV_SP_FP (inst))
577 {
578 cache->uses_fp = 1;
579 /* At this point, only allow argument register moves to other
580 registers or argument register moves to @(X,fp) which are
581 moving the register arguments onto the stack area allocated
582 by a former add somenumber to SP call. Don't allow moving
583 to an fp indirect address above fp + cache->sp_offset. */
584 pc += 2;
585 for (opc = pc + 12; pc < opc; pc += 2)
586 {
587 inst = read_memory_integer (pc, 2);
588 if (IS_MOV_ARG_TO_IND_R14 (inst))
589 {
590 reg = GET_SOURCE_REG (inst);
591 if (cache->sp_offset > 0)
592 cache->saved_regs[reg] = cache->sp_offset;
593 }
594 else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst))
595 {
596 reg = GET_SOURCE_REG (inst);
597 offset = (inst & 0xf) * 4;
598 if (cache->sp_offset > offset)
599 cache->saved_regs[reg] = cache->sp_offset - offset;
600 }
601 else if (IS_MOV_ARG_TO_REG (inst))
602 continue;
603 else
604 break;
605 }
606 break;
607 }
608 else if (IS_JSR (inst))
609 {
610 /* We have found a jsr that has been scheduled into the prologue.
611 If we continue the scan and return a pc someplace after this,
612 then setting a breakpoint on this function will cause it to
613 appear to be called after the function it is calling via the
614 jsr, which will be very confusing. Most likely the next
615 instruction is going to be IS_MOV_SP_FP in the delay slot. If
616 so, note that before returning the current pc. */
617 inst = read_memory_integer (pc + 2, 2);
618 if (IS_MOV_SP_FP (inst))
619 cache->uses_fp = 1;
620 break;
621 }
622 #if 0 /* This used to just stop when it found an instruction that
623 was not considered part of the prologue. Now, we just
624 keep going looking for likely instructions. */
625 else
626 break;
627 #endif
628 }
629
630 return pc;
631 }
632
633 /* Skip any prologue before the guts of a function */
634
635 /* Skip the prologue using the debug information. If this fails we'll
636 fall back on the 'guess' method below. */
637 static CORE_ADDR
638 after_prologue (CORE_ADDR pc)
639 {
640 struct symtab_and_line sal;
641 CORE_ADDR func_addr, func_end;
642
643 /* If we can not find the symbol in the partial symbol table, then
644 there is no hope we can determine the function's start address
645 with this code. */
646 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
647 return 0;
648
649 /* Get the line associated with FUNC_ADDR. */
650 sal = find_pc_line (func_addr, 0);
651
652 /* There are only two cases to consider. First, the end of the source line
653 is within the function bounds. In that case we return the end of the
654 source line. Second is the end of the source line extends beyond the
655 bounds of the current function. We need to use the slow code to
656 examine instructions in that case. */
657 if (sal.end < func_end)
658 return sal.end;
659 else
660 return 0;
661 }
662
663 static CORE_ADDR
664 sh_skip_prologue (CORE_ADDR start_pc)
665 {
666 CORE_ADDR pc;
667 struct sh_frame_cache cache;
668
669 /* See if we can determine the end of the prologue via the symbol table.
670 If so, then return either PC, or the PC after the prologue, whichever
671 is greater. */
672 pc = after_prologue (start_pc);
673
674 /* If after_prologue returned a useful address, then use it. Else
675 fall back on the instruction skipping code. */
676 if (pc)
677 return max (pc, start_pc);
678
679 cache.sp_offset = -4;
680 pc = sh_analyze_prologue (start_pc, (CORE_ADDR) -1, &cache);
681 if (!cache.uses_fp)
682 return start_pc;
683
684 return pc;
685 }
686
687 /* The ABI says:
688
689 Aggregate types not bigger than 8 bytes that have the same size and
690 alignment as one of the integer scalar types are returned in the
691 same registers as the integer type they match.
692
693 For example, a 2-byte aligned structure with size 2 bytes has the
694 same size and alignment as a short int, and will be returned in R0.
695 A 4-byte aligned structure with size 8 bytes has the same size and
696 alignment as a long long int, and will be returned in R0 and R1.
697
698 When an aggregate type is returned in R0 and R1, R0 contains the
699 first four bytes of the aggregate, and R1 contains the
700 remainder. If the size of the aggregate type is not a multiple of 4
701 bytes, the aggregate is tail-padded up to a multiple of 4
702 bytes. The value of the padding is undefined. For little-endian
703 targets the padding will appear at the most significant end of the
704 last element, for big-endian targets the padding appears at the
705 least significant end of the last element.
706
707 All other aggregate types are returned by address. The caller
708 function passes the address of an area large enough to hold the
709 aggregate value in R2. The called function stores the result in
710 this location.
711
712 To reiterate, structs smaller than 8 bytes could also be returned
713 in memory, if they don't pass the "same size and alignment as an
714 integer type" rule.
715
716 For example, in
717
718 struct s { char c[3]; } wibble;
719 struct s foo(void) { return wibble; }
720
721 the return value from foo() will be in memory, not
722 in R0, because there is no 3-byte integer type.
723
724 Similarly, in
725
726 struct s { char c[2]; } wibble;
727 struct s foo(void) { return wibble; }
728
729 because a struct containing two chars has alignment 1, that matches
730 type char, but size 2, that matches type short. There's no integer
731 type that has alignment 1 and size 2, so the struct is returned in
732 memory.
733
734 */
735
736 static int
737 sh_use_struct_convention (int gcc_p, struct type *type)
738 {
739 int len = TYPE_LENGTH (type);
740 int nelem = TYPE_NFIELDS (type);
741
742 /* Non-power of 2 length types and types bigger than 8 bytes (which don't
743 fit in two registers anyway) use struct convention. */
744 if (len != 1 && len != 2 && len != 4 && len != 8)
745 return 1;
746
747 /* Scalar types and aggregate types with exactly one field are aligned
748 by definition. They are returned in registers. */
749 if (nelem <= 1)
750 return 0;
751
752 /* If the first field in the aggregate has the same length as the entire
753 aggregate type, the type is returned in registers. */
754 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == len)
755 return 0;
756
757 /* If the size of the aggregate is 8 bytes and the first field is
758 of size 4 bytes its alignment is equal to long long's alignment,
759 so it's returned in registers. */
760 if (len == 8 && TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == 4)
761 return 0;
762
763 /* Otherwise use struct convention. */
764 return 1;
765 }
766
767 /* Extract from an array REGBUF containing the (raw) register state
768 the address in which a function should return its structure value,
769 as a CORE_ADDR (or an expression that can be used as one). */
770 static CORE_ADDR
771 sh_extract_struct_value_address (struct regcache *regcache)
772 {
773 ULONGEST addr;
774
775 regcache_cooked_read_unsigned (regcache, STRUCT_RETURN_REGNUM, &addr);
776 return addr;
777 }
778
779 static CORE_ADDR
780 sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
781 {
782 return sp & ~3;
783 }
784
785 /* Function: push_dummy_call (formerly push_arguments)
786 Setup the function arguments for calling a function in the inferior.
787
788 On the Renesas SH architecture, there are four registers (R4 to R7)
789 which are dedicated for passing function arguments. Up to the first
790 four arguments (depending on size) may go into these registers.
791 The rest go on the stack.
792
793 MVS: Except on SH variants that have floating point registers.
794 In that case, float and double arguments are passed in the same
795 manner, but using FP registers instead of GP registers.
796
797 Arguments that are smaller than 4 bytes will still take up a whole
798 register or a whole 32-bit word on the stack, and will be
799 right-justified in the register or the stack word. This includes
800 chars, shorts, and small aggregate types.
801
802 Arguments that are larger than 4 bytes may be split between two or
803 more registers. If there are not enough registers free, an argument
804 may be passed partly in a register (or registers), and partly on the
805 stack. This includes doubles, long longs, and larger aggregates.
806 As far as I know, there is no upper limit to the size of aggregates
807 that will be passed in this way; in other words, the convention of
808 passing a pointer to a large aggregate instead of a copy is not used.
809
810 MVS: The above appears to be true for the SH variants that do not
811 have an FPU, however those that have an FPU appear to copy the
812 aggregate argument onto the stack (and not place it in registers)
813 if it is larger than 16 bytes (four GP registers).
814
815 An exceptional case exists for struct arguments (and possibly other
816 aggregates such as arrays) if the size is larger than 4 bytes but
817 not a multiple of 4 bytes. In this case the argument is never split
818 between the registers and the stack, but instead is copied in its
819 entirety onto the stack, AND also copied into as many registers as
820 there is room for. In other words, space in registers permitting,
821 two copies of the same argument are passed in. As far as I can tell,
822 only the one on the stack is used, although that may be a function
823 of the level of compiler optimization. I suspect this is a compiler
824 bug. Arguments of these odd sizes are left-justified within the
825 word (as opposed to arguments smaller than 4 bytes, which are
826 right-justified).
827
828 If the function is to return an aggregate type such as a struct, it
829 is either returned in the normal return value register R0 (if its
830 size is no greater than one byte), or else the caller must allocate
831 space into which the callee will copy the return value (if the size
832 is greater than one byte). In this case, a pointer to the return
833 value location is passed into the callee in register R2, which does
834 not displace any of the other arguments passed in via registers R4
835 to R7. */
836
837 /* Helper function to justify value in register according to endianess. */
838 static char *
839 sh_justify_value_in_reg (struct value *val, int len)
840 {
841 static char valbuf[4];
842
843 memset (valbuf, 0, sizeof (valbuf));
844 if (len < 4)
845 {
846 /* value gets right-justified in the register or stack word */
847 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
848 memcpy (valbuf + (4 - len), (char *) VALUE_CONTENTS (val), len);
849 else
850 memcpy (valbuf, (char *) VALUE_CONTENTS (val), len);
851 return valbuf;
852 }
853 return (char *) VALUE_CONTENTS (val);
854 }
855
856 /* Helper function to eval number of bytes to allocate on stack. */
857 static CORE_ADDR
858 sh_stack_allocsize (int nargs, struct value **args)
859 {
860 int stack_alloc = 0;
861 while (nargs-- > 0)
862 stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[nargs])) + 3) & ~3);
863 return stack_alloc;
864 }
865
866 /* Helper functions for getting the float arguments right. Registers usage
867 depends on the ABI and the endianess. The comments should enlighten how
868 it's intended to work. */
869
870 /* This array stores which of the float arg registers are already in use. */
871 static int flt_argreg_array[FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM + 1];
872
873 /* This function just resets the above array to "no reg used so far". */
874 static void
875 sh_init_flt_argreg (void)
876 {
877 memset (flt_argreg_array, 0, sizeof flt_argreg_array);
878 }
879
880 /* This function returns the next register to use for float arg passing.
881 It returns either a valid value between FLOAT_ARG0_REGNUM and
882 FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns
883 FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available.
884
885 Note that register number 0 in flt_argreg_array corresponds with the
886 real float register fr4. In contrast to FLOAT_ARG0_REGNUM (value is
887 29) the parity of the register number is preserved, which is important
888 for the double register passing test (see the "argreg & 1" test below). */
889 static int
890 sh_next_flt_argreg (int len)
891 {
892 int argreg;
893
894 /* First search for the next free register. */
895 for (argreg = 0; argreg <= FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM;
896 ++argreg)
897 if (!flt_argreg_array[argreg])
898 break;
899
900 /* No register left? */
901 if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
902 return FLOAT_ARGLAST_REGNUM + 1;
903
904 if (len == 8)
905 {
906 /* Doubles are always starting in a even register number. */
907 if (argreg & 1)
908 {
909 flt_argreg_array[argreg] = 1;
910
911 ++argreg;
912
913 /* No register left? */
914 if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
915 return FLOAT_ARGLAST_REGNUM + 1;
916 }
917 /* Also mark the next register as used. */
918 flt_argreg_array[argreg + 1] = 1;
919 }
920 else if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
921 {
922 /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */
923 if (!flt_argreg_array[argreg + 1])
924 ++argreg;
925 }
926 flt_argreg_array[argreg] = 1;
927 return FLOAT_ARG0_REGNUM + argreg;
928 }
929
930 /* Helper function which figures out, if a type is treated like a float type.
931
932 The FPU ABIs have a special way how to treat types as float types.
933 Structures with exactly one member, which is of type float or double, are
934 treated exactly as the base types float or double:
935
936 struct sf {
937 float f;
938 };
939
940 struct sd {
941 double d;
942 };
943
944 are handled the same way as just
945
946 float f;
947
948 double d;
949
950 As a result, arguments of these struct types are pushed into floating point
951 registers exactly as floats or doubles, using the same decision algorithm.
952
953 The same is valid if these types are used as function return types. The
954 above structs are returned in fr0 resp. fr0,fr1 instead of in r0, r0,r1
955 or even using struct convention as it is for other structs. */
956
957 static int
958 sh_treat_as_flt_p (struct type *type)
959 {
960 int len = TYPE_LENGTH (type);
961
962 /* Ordinary float types are obviously treated as float. */
963 if (TYPE_CODE (type) == TYPE_CODE_FLT)
964 return 1;
965 /* Otherwise non-struct types are not treated as float. */
966 if (TYPE_CODE (type) != TYPE_CODE_STRUCT)
967 return 0;
968 /* Otherwise structs with more than one memeber are not treated as float. */
969 if (TYPE_NFIELDS (type) != 1)
970 return 0;
971 /* Otherwise if the type of that member is float, the whole type is
972 treated as float. */
973 if (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) == TYPE_CODE_FLT)
974 return 1;
975 /* Otherwise it's not treated as float. */
976 return 0;
977 }
978
979 static CORE_ADDR
980 sh_push_dummy_call_fpu (struct gdbarch *gdbarch,
981 struct value *function,
982 struct regcache *regcache,
983 CORE_ADDR bp_addr, int nargs,
984 struct value **args,
985 CORE_ADDR sp, int struct_return,
986 CORE_ADDR struct_addr)
987 {
988 int stack_offset = 0;
989 int argreg = ARG0_REGNUM;
990 int flt_argreg = 0;
991 int argnum;
992 struct type *type;
993 CORE_ADDR regval;
994 char *val;
995 int len, reg_size = 0;
996 int pass_on_stack = 0;
997 int treat_as_flt;
998
999 /* first force sp to a 4-byte alignment */
1000 sp = sh_frame_align (gdbarch, sp);
1001
1002 if (struct_return)
1003 regcache_cooked_write_unsigned (regcache,
1004 STRUCT_RETURN_REGNUM, struct_addr);
1005
1006 /* make room on stack for args */
1007 sp -= sh_stack_allocsize (nargs, args);
1008
1009 /* Initialize float argument mechanism. */
1010 sh_init_flt_argreg ();
1011
1012 /* Now load as many as possible of the first arguments into
1013 registers, and push the rest onto the stack. There are 16 bytes
1014 in four registers available. Loop thru args from first to last. */
1015 for (argnum = 0; argnum < nargs; argnum++)
1016 {
1017 type = VALUE_TYPE (args[argnum]);
1018 len = TYPE_LENGTH (type);
1019 val = sh_justify_value_in_reg (args[argnum], len);
1020
1021 /* Some decisions have to be made how various types are handled.
1022 This also differs in different ABIs. */
1023 pass_on_stack = 0;
1024
1025 /* Find out the next register to use for a floating point value. */
1026 treat_as_flt = sh_treat_as_flt_p (type);
1027 if (treat_as_flt)
1028 flt_argreg = sh_next_flt_argreg (len);
1029 /* In contrast to non-FPU CPUs, arguments are never split between
1030 registers and stack. If an argument doesn't fit in the remaining
1031 registers it's always pushed entirely on the stack. */
1032 else if (len > ((ARGLAST_REGNUM - argreg + 1) * 4))
1033 pass_on_stack = 1;
1034
1035 while (len > 0)
1036 {
1037 if ((treat_as_flt && flt_argreg > FLOAT_ARGLAST_REGNUM)
1038 || (!treat_as_flt && (argreg > ARGLAST_REGNUM
1039 || pass_on_stack)))
1040 {
1041 /* The data goes entirely on the stack, 4-byte aligned. */
1042 reg_size = (len + 3) & ~3;
1043 write_memory (sp + stack_offset, val, reg_size);
1044 stack_offset += reg_size;
1045 }
1046 else if (treat_as_flt && flt_argreg <= FLOAT_ARGLAST_REGNUM)
1047 {
1048 /* Argument goes in a float argument register. */
1049 reg_size = register_size (gdbarch, flt_argreg);
1050 regval = extract_unsigned_integer (val, reg_size);
1051 /* In little endian mode, float types taking two registers
1052 (doubles on sh4, long doubles on sh2e, sh3e and sh4) must
1053 be stored swapped in the argument registers. The below
1054 code first writes the first 32 bits in the next but one
1055 register, increments the val and len values accordingly
1056 and then proceeds as normal by writing the second 32 bits
1057 into the next register. */
1058 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE
1059 && TYPE_LENGTH (type) == 2 * reg_size)
1060 {
1061 regcache_cooked_write_unsigned (regcache, flt_argreg + 1,
1062 regval);
1063 val += reg_size;
1064 len -= reg_size;
1065 regval = extract_unsigned_integer (val, reg_size);
1066 }
1067 regcache_cooked_write_unsigned (regcache, flt_argreg++, regval);
1068 }
1069 else if (!treat_as_flt && argreg <= ARGLAST_REGNUM)
1070 {
1071 /* there's room in a register */
1072 reg_size = register_size (gdbarch, argreg);
1073 regval = extract_unsigned_integer (val, reg_size);
1074 regcache_cooked_write_unsigned (regcache, argreg++, regval);
1075 }
1076 /* Store the value one register at a time or in one step on stack. */
1077 len -= reg_size;
1078 val += reg_size;
1079 }
1080 }
1081
1082 /* Store return address. */
1083 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
1084
1085 /* Update stack pointer. */
1086 regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp);
1087
1088 return sp;
1089 }
1090
1091 static CORE_ADDR
1092 sh_push_dummy_call_nofpu (struct gdbarch *gdbarch,
1093 struct value *function,
1094 struct regcache *regcache,
1095 CORE_ADDR bp_addr,
1096 int nargs, struct value **args,
1097 CORE_ADDR sp, int struct_return,
1098 CORE_ADDR struct_addr)
1099 {
1100 int stack_offset = 0;
1101 int argreg = ARG0_REGNUM;
1102 int argnum;
1103 struct type *type;
1104 CORE_ADDR regval;
1105 char *val;
1106 int len, reg_size;
1107
1108 /* first force sp to a 4-byte alignment */
1109 sp = sh_frame_align (gdbarch, sp);
1110
1111 if (struct_return)
1112 regcache_cooked_write_unsigned (regcache,
1113 STRUCT_RETURN_REGNUM, struct_addr);
1114
1115 /* make room on stack for args */
1116 sp -= sh_stack_allocsize (nargs, args);
1117
1118 /* Now load as many as possible of the first arguments into
1119 registers, and push the rest onto the stack. There are 16 bytes
1120 in four registers available. Loop thru args from first to last. */
1121 for (argnum = 0; argnum < nargs; argnum++)
1122 {
1123 type = VALUE_TYPE (args[argnum]);
1124 len = TYPE_LENGTH (type);
1125 val = sh_justify_value_in_reg (args[argnum], len);
1126
1127 while (len > 0)
1128 {
1129 if (argreg > ARGLAST_REGNUM)
1130 {
1131 /* The remainder of the data goes entirely on the stack,
1132 4-byte aligned. */
1133 reg_size = (len + 3) & ~3;
1134 write_memory (sp + stack_offset, val, reg_size);
1135 stack_offset += reg_size;
1136 }
1137 else if (argreg <= ARGLAST_REGNUM)
1138 {
1139 /* there's room in a register */
1140 reg_size = register_size (gdbarch, argreg);
1141 regval = extract_unsigned_integer (val, reg_size);
1142 regcache_cooked_write_unsigned (regcache, argreg++, regval);
1143 }
1144 /* Store the value reg_size bytes at a time. This means that things
1145 larger than reg_size bytes may go partly in registers and partly
1146 on the stack. */
1147 len -= reg_size;
1148 val += reg_size;
1149 }
1150 }
1151
1152 /* Store return address. */
1153 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
1154
1155 /* Update stack pointer. */
1156 regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp);
1157
1158 return sp;
1159 }
1160
1161 /* Find a function's return value in the appropriate registers (in
1162 regbuf), and copy it into valbuf. Extract from an array REGBUF
1163 containing the (raw) register state a function return value of type
1164 TYPE, and copy that, in virtual format, into VALBUF. */
1165 static void
1166 sh_default_extract_return_value (struct type *type, struct regcache *regcache,
1167 void *valbuf)
1168 {
1169 int len = TYPE_LENGTH (type);
1170 int return_register = R0_REGNUM;
1171 int offset;
1172
1173 if (len <= 4)
1174 {
1175 ULONGEST c;
1176
1177 regcache_cooked_read_unsigned (regcache, R0_REGNUM, &c);
1178 store_unsigned_integer (valbuf, len, c);
1179 }
1180 else if (len == 8)
1181 {
1182 int i, regnum = R0_REGNUM;
1183 for (i = 0; i < len; i += 4)
1184 regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
1185 }
1186 else
1187 error ("bad size for return value");
1188 }
1189
1190 static void
1191 sh3e_sh4_extract_return_value (struct type *type, struct regcache *regcache,
1192 void *valbuf)
1193 {
1194 if (sh_treat_as_flt_p (type))
1195 {
1196 int len = TYPE_LENGTH (type);
1197 int i, regnum = FP0_REGNUM;
1198 for (i = 0; i < len; i += 4)
1199 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
1200 regcache_raw_read (regcache, regnum++, (char *) valbuf + len - 4 - i);
1201 else
1202 regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
1203 }
1204 else
1205 sh_default_extract_return_value (type, regcache, valbuf);
1206 }
1207
1208 /* Write into appropriate registers a function return value
1209 of type TYPE, given in virtual format.
1210 If the architecture is sh4 or sh3e, store a function's return value
1211 in the R0 general register or in the FP0 floating point register,
1212 depending on the type of the return value. In all the other cases
1213 the result is stored in r0, left-justified. */
1214 static void
1215 sh_default_store_return_value (struct type *type, struct regcache *regcache,
1216 const void *valbuf)
1217 {
1218 ULONGEST val;
1219 int len = TYPE_LENGTH (type);
1220
1221 if (len <= 4)
1222 {
1223 val = extract_unsigned_integer (valbuf, len);
1224 regcache_cooked_write_unsigned (regcache, R0_REGNUM, val);
1225 }
1226 else
1227 {
1228 int i, regnum = R0_REGNUM;
1229 for (i = 0; i < len; i += 4)
1230 regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
1231 }
1232 }
1233
1234 static void
1235 sh3e_sh4_store_return_value (struct type *type, struct regcache *regcache,
1236 const void *valbuf)
1237 {
1238 if (sh_treat_as_flt_p (type))
1239 {
1240 int len = TYPE_LENGTH (type);
1241 int i, regnum = FP0_REGNUM;
1242 for (i = 0; i < len; i += 4)
1243 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
1244 regcache_raw_write (regcache, regnum++,
1245 (char *) valbuf + len - 4 - i);
1246 else
1247 regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
1248 }
1249 else
1250 sh_default_store_return_value (type, regcache, valbuf);
1251 }
1252
1253 /* Print the registers in a form similar to the E7000 */
1254
1255 static void
1256 sh_generic_show_regs (void)
1257 {
1258 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1259 paddr (read_register (PC_REGNUM)),
1260 (long) read_register (SR_REGNUM),
1261 (long) read_register (PR_REGNUM),
1262 (long) read_register (MACH_REGNUM),
1263 (long) read_register (MACL_REGNUM));
1264
1265 printf_filtered ("GBR=%08lx VBR=%08lx",
1266 (long) read_register (GBR_REGNUM),
1267 (long) read_register (VBR_REGNUM));
1268
1269 printf_filtered
1270 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1271 (long) read_register (0), (long) read_register (1),
1272 (long) read_register (2), (long) read_register (3),
1273 (long) read_register (4), (long) read_register (5),
1274 (long) read_register (6), (long) read_register (7));
1275 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1276 (long) read_register (8), (long) read_register (9),
1277 (long) read_register (10), (long) read_register (11),
1278 (long) read_register (12), (long) read_register (13),
1279 (long) read_register (14), (long) read_register (15));
1280 }
1281
1282 static void
1283 sh3_show_regs (void)
1284 {
1285 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1286 paddr (read_register (PC_REGNUM)),
1287 (long) read_register (SR_REGNUM),
1288 (long) read_register (PR_REGNUM),
1289 (long) read_register (MACH_REGNUM),
1290 (long) read_register (MACL_REGNUM));
1291
1292 printf_filtered ("GBR=%08lx VBR=%08lx",
1293 (long) read_register (GBR_REGNUM),
1294 (long) read_register (VBR_REGNUM));
1295 printf_filtered (" SSR=%08lx SPC=%08lx",
1296 (long) read_register (SSR_REGNUM),
1297 (long) read_register (SPC_REGNUM));
1298
1299 printf_filtered
1300 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1301 (long) read_register (0), (long) read_register (1),
1302 (long) read_register (2), (long) read_register (3),
1303 (long) read_register (4), (long) read_register (5),
1304 (long) read_register (6), (long) read_register (7));
1305 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1306 (long) read_register (8), (long) read_register (9),
1307 (long) read_register (10), (long) read_register (11),
1308 (long) read_register (12), (long) read_register (13),
1309 (long) read_register (14), (long) read_register (15));
1310 }
1311
1312
1313 static void
1314 sh2e_show_regs (void)
1315 {
1316 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1317 paddr (read_register (PC_REGNUM)),
1318 (long) read_register (SR_REGNUM),
1319 (long) read_register (PR_REGNUM),
1320 (long) read_register (MACH_REGNUM),
1321 (long) read_register (MACL_REGNUM));
1322
1323 printf_filtered ("GBR=%08lx VBR=%08lx",
1324 (long) read_register (GBR_REGNUM),
1325 (long) read_register (VBR_REGNUM));
1326 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1327 (long) read_register (FPUL_REGNUM),
1328 (long) read_register (FPSCR_REGNUM));
1329
1330 printf_filtered
1331 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1332 (long) read_register (0), (long) read_register (1),
1333 (long) read_register (2), (long) read_register (3),
1334 (long) read_register (4), (long) read_register (5),
1335 (long) read_register (6), (long) read_register (7));
1336 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1337 (long) read_register (8), (long) read_register (9),
1338 (long) read_register (10), (long) read_register (11),
1339 (long) read_register (12), (long) read_register (13),
1340 (long) read_register (14), (long) read_register (15));
1341
1342 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 0), (long) read_register (FP0_REGNUM + 1), (long) read_register (FP0_REGNUM + 2), (long) read_register (FP0_REGNUM + 3), (long) read_register (FP0_REGNUM + 4), (long) read_register (FP0_REGNUM + 5), (long) read_register (FP0_REGNUM + 6), (long) read_register (FP0_REGNUM + 7));
1343 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 8), (long) read_register (FP0_REGNUM + 9), (long) read_register (FP0_REGNUM + 10), (long) read_register (FP0_REGNUM + 11), (long) read_register (FP0_REGNUM + 12), (long) read_register (FP0_REGNUM + 13), (long) read_register (FP0_REGNUM + 14), (long) read_register (FP0_REGNUM + 15));
1344 }
1345
1346 static void
1347 sh2a_show_regs (void)
1348 {
1349 int pr = read_register (FPSCR_REGNUM) & 0x80000;
1350 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1351 paddr (read_register (PC_REGNUM)),
1352 (long) read_register (SR_REGNUM),
1353 (long) read_register (PR_REGNUM),
1354 (long) read_register (MACH_REGNUM),
1355 (long) read_register (MACL_REGNUM));
1356
1357 printf_filtered ("GBR=%08lx VBR=%08lx TBR=%08lx",
1358 (long) read_register (GBR_REGNUM),
1359 (long) read_register (VBR_REGNUM),
1360 (long) read_register (TBR_REGNUM));
1361 printf_filtered (" FPUL=%08lx FPSCR=%08lx\n",
1362 (long) read_register (FPUL_REGNUM),
1363 (long) read_register (FPSCR_REGNUM));
1364
1365 printf_filtered ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1366 (long) read_register (0), (long) read_register (1),
1367 (long) read_register (2), (long) read_register (3),
1368 (long) read_register (4), (long) read_register (5),
1369 (long) read_register (6), (long) read_register (7));
1370 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1371 (long) read_register (8), (long) read_register (9),
1372 (long) read_register (10), (long) read_register (11),
1373 (long) read_register (12), (long) read_register (13),
1374 (long) read_register (14), (long) read_register (15));
1375
1376 printf_filtered ((pr
1377 ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1378 :
1379 "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1380 (long) read_register (FP0_REGNUM + 0),
1381 (long) read_register (FP0_REGNUM + 1),
1382 (long) read_register (FP0_REGNUM + 2),
1383 (long) read_register (FP0_REGNUM + 3),
1384 (long) read_register (FP0_REGNUM + 4),
1385 (long) read_register (FP0_REGNUM + 5),
1386 (long) read_register (FP0_REGNUM + 6),
1387 (long) read_register (FP0_REGNUM + 7));
1388 printf_filtered ((pr ?
1389 "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n" :
1390 "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1391 (long) read_register (FP0_REGNUM + 8),
1392 (long) read_register (FP0_REGNUM + 9),
1393 (long) read_register (FP0_REGNUM + 10),
1394 (long) read_register (FP0_REGNUM + 11),
1395 (long) read_register (FP0_REGNUM + 12),
1396 (long) read_register (FP0_REGNUM + 13),
1397 (long) read_register (FP0_REGNUM + 14),
1398 (long) read_register (FP0_REGNUM + 15));
1399 printf_filtered ("BANK=%-3d\n", (int) read_register (BANK_REGNUM));
1400 printf_filtered ("R0b - R7b %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1401 (long) read_register (R0_BANK0_REGNUM + 0),
1402 (long) read_register (R0_BANK0_REGNUM + 1),
1403 (long) read_register (R0_BANK0_REGNUM + 2),
1404 (long) read_register (R0_BANK0_REGNUM + 3),
1405 (long) read_register (R0_BANK0_REGNUM + 4),
1406 (long) read_register (R0_BANK0_REGNUM + 5),
1407 (long) read_register (R0_BANK0_REGNUM + 6),
1408 (long) read_register (R0_BANK0_REGNUM + 7));
1409 printf_filtered ("R8b - R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1410 (long) read_register (R0_BANK0_REGNUM + 8),
1411 (long) read_register (R0_BANK0_REGNUM + 9),
1412 (long) read_register (R0_BANK0_REGNUM + 10),
1413 (long) read_register (R0_BANK0_REGNUM + 11),
1414 (long) read_register (R0_BANK0_REGNUM + 12),
1415 (long) read_register (R0_BANK0_REGNUM + 13),
1416 (long) read_register (R0_BANK0_REGNUM + 14));
1417 printf_filtered ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n",
1418 (long) read_register (R0_BANK0_REGNUM + 15),
1419 (long) read_register (R0_BANK0_REGNUM + 16),
1420 (long) read_register (R0_BANK0_REGNUM + 17),
1421 (long) read_register (R0_BANK0_REGNUM + 18),
1422 (long) read_register (R0_BANK0_REGNUM + 19));
1423 }
1424
1425 static void
1426 sh2a_nofpu_show_regs (void)
1427 {
1428 int pr = read_register (FPSCR_REGNUM) & 0x80000;
1429 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1430 paddr (read_register (PC_REGNUM)),
1431 (long) read_register (SR_REGNUM),
1432 (long) read_register (PR_REGNUM),
1433 (long) read_register (MACH_REGNUM),
1434 (long) read_register (MACL_REGNUM));
1435
1436 printf_filtered ("GBR=%08lx VBR=%08lx TBR=%08lx",
1437 (long) read_register (GBR_REGNUM),
1438 (long) read_register (VBR_REGNUM),
1439 (long) read_register (TBR_REGNUM));
1440 printf_filtered (" FPUL=%08lx FPSCR=%08lx\n",
1441 (long) read_register (FPUL_REGNUM),
1442 (long) read_register (FPSCR_REGNUM));
1443
1444 printf_filtered ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1445 (long) read_register (0), (long) read_register (1),
1446 (long) read_register (2), (long) read_register (3),
1447 (long) read_register (4), (long) read_register (5),
1448 (long) read_register (6), (long) read_register (7));
1449 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1450 (long) read_register (8), (long) read_register (9),
1451 (long) read_register (10), (long) read_register (11),
1452 (long) read_register (12), (long) read_register (13),
1453 (long) read_register (14), (long) read_register (15));
1454
1455 printf_filtered ("BANK=%-3d\n", (int) read_register (BANK_REGNUM));
1456 printf_filtered ("R0b - R7b %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1457 (long) read_register (R0_BANK0_REGNUM + 0),
1458 (long) read_register (R0_BANK0_REGNUM + 1),
1459 (long) read_register (R0_BANK0_REGNUM + 2),
1460 (long) read_register (R0_BANK0_REGNUM + 3),
1461 (long) read_register (R0_BANK0_REGNUM + 4),
1462 (long) read_register (R0_BANK0_REGNUM + 5),
1463 (long) read_register (R0_BANK0_REGNUM + 6),
1464 (long) read_register (R0_BANK0_REGNUM + 7));
1465 printf_filtered ("R8b - R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1466 (long) read_register (R0_BANK0_REGNUM + 8),
1467 (long) read_register (R0_BANK0_REGNUM + 9),
1468 (long) read_register (R0_BANK0_REGNUM + 10),
1469 (long) read_register (R0_BANK0_REGNUM + 11),
1470 (long) read_register (R0_BANK0_REGNUM + 12),
1471 (long) read_register (R0_BANK0_REGNUM + 13),
1472 (long) read_register (R0_BANK0_REGNUM + 14));
1473 printf_filtered ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n",
1474 (long) read_register (R0_BANK0_REGNUM + 15),
1475 (long) read_register (R0_BANK0_REGNUM + 16),
1476 (long) read_register (R0_BANK0_REGNUM + 17),
1477 (long) read_register (R0_BANK0_REGNUM + 18),
1478 (long) read_register (R0_BANK0_REGNUM + 19));
1479 }
1480
1481 static void
1482 sh3e_show_regs (void)
1483 {
1484 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1485 paddr (read_register (PC_REGNUM)),
1486 (long) read_register (SR_REGNUM),
1487 (long) read_register (PR_REGNUM),
1488 (long) read_register (MACH_REGNUM),
1489 (long) read_register (MACL_REGNUM));
1490
1491 printf_filtered ("GBR=%08lx VBR=%08lx",
1492 (long) read_register (GBR_REGNUM),
1493 (long) read_register (VBR_REGNUM));
1494 printf_filtered (" SSR=%08lx SPC=%08lx",
1495 (long) read_register (SSR_REGNUM),
1496 (long) read_register (SPC_REGNUM));
1497 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1498 (long) read_register (FPUL_REGNUM),
1499 (long) read_register (FPSCR_REGNUM));
1500
1501 printf_filtered
1502 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1503 (long) read_register (0), (long) read_register (1),
1504 (long) read_register (2), (long) read_register (3),
1505 (long) read_register (4), (long) read_register (5),
1506 (long) read_register (6), (long) read_register (7));
1507 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1508 (long) read_register (8), (long) read_register (9),
1509 (long) read_register (10), (long) read_register (11),
1510 (long) read_register (12), (long) read_register (13),
1511 (long) read_register (14), (long) read_register (15));
1512
1513 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 0), (long) read_register (FP0_REGNUM + 1), (long) read_register (FP0_REGNUM + 2), (long) read_register (FP0_REGNUM + 3), (long) read_register (FP0_REGNUM + 4), (long) read_register (FP0_REGNUM + 5), (long) read_register (FP0_REGNUM + 6), (long) read_register (FP0_REGNUM + 7));
1514 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 8), (long) read_register (FP0_REGNUM + 9), (long) read_register (FP0_REGNUM + 10), (long) read_register (FP0_REGNUM + 11), (long) read_register (FP0_REGNUM + 12), (long) read_register (FP0_REGNUM + 13), (long) read_register (FP0_REGNUM + 14), (long) read_register (FP0_REGNUM + 15));
1515 }
1516
1517 static void
1518 sh3_dsp_show_regs (void)
1519 {
1520 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1521 paddr (read_register (PC_REGNUM)),
1522 (long) read_register (SR_REGNUM),
1523 (long) read_register (PR_REGNUM),
1524 (long) read_register (MACH_REGNUM),
1525 (long) read_register (MACL_REGNUM));
1526
1527 printf_filtered ("GBR=%08lx VBR=%08lx",
1528 (long) read_register (GBR_REGNUM),
1529 (long) read_register (VBR_REGNUM));
1530
1531 printf_filtered (" SSR=%08lx SPC=%08lx",
1532 (long) read_register (SSR_REGNUM),
1533 (long) read_register (SPC_REGNUM));
1534
1535 printf_filtered (" DSR=%08lx", (long) read_register (DSR_REGNUM));
1536
1537 printf_filtered
1538 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1539 (long) read_register (0), (long) read_register (1),
1540 (long) read_register (2), (long) read_register (3),
1541 (long) read_register (4), (long) read_register (5),
1542 (long) read_register (6), (long) read_register (7));
1543 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1544 (long) read_register (8), (long) read_register (9),
1545 (long) read_register (10), (long) read_register (11),
1546 (long) read_register (12), (long) read_register (13),
1547 (long) read_register (14), (long) read_register (15));
1548
1549 printf_filtered
1550 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1551 (long) read_register (A0G_REGNUM) & 0xff,
1552 (long) read_register (A0_REGNUM), (long) read_register (M0_REGNUM),
1553 (long) read_register (X0_REGNUM), (long) read_register (Y0_REGNUM),
1554 (long) read_register (RS_REGNUM), (long) read_register (MOD_REGNUM));
1555 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1556 (long) read_register (A1G_REGNUM) & 0xff,
1557 (long) read_register (A1_REGNUM),
1558 (long) read_register (M1_REGNUM),
1559 (long) read_register (X1_REGNUM),
1560 (long) read_register (Y1_REGNUM),
1561 (long) read_register (RE_REGNUM));
1562 }
1563
1564 static void
1565 sh4_show_regs (void)
1566 {
1567 int pr = read_register (FPSCR_REGNUM) & 0x80000;
1568 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1569 paddr (read_register (PC_REGNUM)),
1570 (long) read_register (SR_REGNUM),
1571 (long) read_register (PR_REGNUM),
1572 (long) read_register (MACH_REGNUM),
1573 (long) read_register (MACL_REGNUM));
1574
1575 printf_filtered ("GBR=%08lx VBR=%08lx",
1576 (long) read_register (GBR_REGNUM),
1577 (long) read_register (VBR_REGNUM));
1578 printf_filtered (" SSR=%08lx SPC=%08lx",
1579 (long) read_register (SSR_REGNUM),
1580 (long) read_register (SPC_REGNUM));
1581 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1582 (long) read_register (FPUL_REGNUM),
1583 (long) read_register (FPSCR_REGNUM));
1584
1585 printf_filtered
1586 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1587 (long) read_register (0), (long) read_register (1),
1588 (long) read_register (2), (long) read_register (3),
1589 (long) read_register (4), (long) read_register (5),
1590 (long) read_register (6), (long) read_register (7));
1591 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1592 (long) read_register (8), (long) read_register (9),
1593 (long) read_register (10), (long) read_register (11),
1594 (long) read_register (12), (long) read_register (13),
1595 (long) read_register (14), (long) read_register (15));
1596
1597 printf_filtered ((pr
1598 ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1599 :
1600 "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1601 (long) read_register (FP0_REGNUM + 0),
1602 (long) read_register (FP0_REGNUM + 1),
1603 (long) read_register (FP0_REGNUM + 2),
1604 (long) read_register (FP0_REGNUM + 3),
1605 (long) read_register (FP0_REGNUM + 4),
1606 (long) read_register (FP0_REGNUM + 5),
1607 (long) read_register (FP0_REGNUM + 6),
1608 (long) read_register (FP0_REGNUM + 7));
1609 printf_filtered ((pr ?
1610 "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n" :
1611 "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1612 (long) read_register (FP0_REGNUM + 8),
1613 (long) read_register (FP0_REGNUM + 9),
1614 (long) read_register (FP0_REGNUM + 10),
1615 (long) read_register (FP0_REGNUM + 11),
1616 (long) read_register (FP0_REGNUM + 12),
1617 (long) read_register (FP0_REGNUM + 13),
1618 (long) read_register (FP0_REGNUM + 14),
1619 (long) read_register (FP0_REGNUM + 15));
1620 }
1621
1622 static void
1623 sh4_nofpu_show_regs (void)
1624 {
1625 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1626 paddr (read_register (PC_REGNUM)),
1627 (long) read_register (SR_REGNUM),
1628 (long) read_register (PR_REGNUM),
1629 (long) read_register (MACH_REGNUM),
1630 (long) read_register (MACL_REGNUM));
1631
1632 printf_filtered ("GBR=%08lx VBR=%08lx",
1633 (long) read_register (GBR_REGNUM),
1634 (long) read_register (VBR_REGNUM));
1635 printf_filtered (" SSR=%08lx SPC=%08lx",
1636 (long) read_register (SSR_REGNUM),
1637 (long) read_register (SPC_REGNUM));
1638
1639 printf_filtered
1640 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1641 (long) read_register (0), (long) read_register (1),
1642 (long) read_register (2), (long) read_register (3),
1643 (long) read_register (4), (long) read_register (5),
1644 (long) read_register (6), (long) read_register (7));
1645 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1646 (long) read_register (8), (long) read_register (9),
1647 (long) read_register (10), (long) read_register (11),
1648 (long) read_register (12), (long) read_register (13),
1649 (long) read_register (14), (long) read_register (15));
1650 }
1651
1652 static void
1653 sh_dsp_show_regs (void)
1654 {
1655 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1656 paddr (read_register (PC_REGNUM)),
1657 (long) read_register (SR_REGNUM),
1658 (long) read_register (PR_REGNUM),
1659 (long) read_register (MACH_REGNUM),
1660 (long) read_register (MACL_REGNUM));
1661
1662 printf_filtered ("GBR=%08lx VBR=%08lx",
1663 (long) read_register (GBR_REGNUM),
1664 (long) read_register (VBR_REGNUM));
1665
1666 printf_filtered (" DSR=%08lx", (long) read_register (DSR_REGNUM));
1667
1668 printf_filtered
1669 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1670 (long) read_register (0), (long) read_register (1),
1671 (long) read_register (2), (long) read_register (3),
1672 (long) read_register (4), (long) read_register (5),
1673 (long) read_register (6), (long) read_register (7));
1674 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1675 (long) read_register (8), (long) read_register (9),
1676 (long) read_register (10), (long) read_register (11),
1677 (long) read_register (12), (long) read_register (13),
1678 (long) read_register (14), (long) read_register (15));
1679
1680 printf_filtered
1681 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1682 (long) read_register (A0G_REGNUM) & 0xff,
1683 (long) read_register (A0_REGNUM), (long) read_register (M0_REGNUM),
1684 (long) read_register (X0_REGNUM), (long) read_register (Y0_REGNUM),
1685 (long) read_register (RS_REGNUM), (long) read_register (MOD_REGNUM));
1686 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1687 (long) read_register (A1G_REGNUM) & 0xff,
1688 (long) read_register (A1_REGNUM),
1689 (long) read_register (M1_REGNUM),
1690 (long) read_register (X1_REGNUM),
1691 (long) read_register (Y1_REGNUM),
1692 (long) read_register (RE_REGNUM));
1693 }
1694
1695 static void
1696 sh_show_regs_command (char *args, int from_tty)
1697 {
1698 if (sh_show_regs)
1699 (*sh_show_regs) ();
1700 }
1701
1702 static struct type *
1703 sh_sh2a_register_type (struct gdbarch *gdbarch, int reg_nr)
1704 {
1705 if ((reg_nr >= FP0_REGNUM
1706 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
1707 return builtin_type_float;
1708 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
1709 return builtin_type_double;
1710 else
1711 return builtin_type_int;
1712 }
1713
1714 /* Return the GDB type object for the "standard" data type
1715 of data in register N. */
1716 static struct type *
1717 sh_sh3e_register_type (struct gdbarch *gdbarch, int reg_nr)
1718 {
1719 if ((reg_nr >= FP0_REGNUM
1720 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
1721 return builtin_type_float;
1722 else
1723 return builtin_type_int;
1724 }
1725
1726 static struct type *
1727 sh_sh4_build_float_register_type (int high)
1728 {
1729 struct type *temp;
1730
1731 temp = create_range_type (NULL, builtin_type_int, 0, high);
1732 return create_array_type (NULL, builtin_type_float, temp);
1733 }
1734
1735 static struct type *
1736 sh_sh4_register_type (struct gdbarch *gdbarch, int reg_nr)
1737 {
1738 if ((reg_nr >= FP0_REGNUM
1739 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
1740 return builtin_type_float;
1741 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
1742 return builtin_type_double;
1743 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
1744 return sh_sh4_build_float_register_type (3);
1745 else
1746 return builtin_type_int;
1747 }
1748
1749 static struct type *
1750 sh_default_register_type (struct gdbarch *gdbarch, int reg_nr)
1751 {
1752 return builtin_type_int;
1753 }
1754
1755 /* On the sh4, the DRi pseudo registers are problematic if the target
1756 is little endian. When the user writes one of those registers, for
1757 instance with 'ser var $dr0=1', we want the double to be stored
1758 like this:
1759 fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
1760 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1761
1762 This corresponds to little endian byte order & big endian word
1763 order. However if we let gdb write the register w/o conversion, it
1764 will write fr0 and fr1 this way:
1765 fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1766 fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
1767 because it will consider fr0 and fr1 as a single LE stretch of memory.
1768
1769 To achieve what we want we must force gdb to store things in
1770 floatformat_ieee_double_littlebyte_bigword (which is defined in
1771 include/floatformat.h and libiberty/floatformat.c.
1772
1773 In case the target is big endian, there is no problem, the
1774 raw bytes will look like:
1775 fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
1776 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1777
1778 The other pseudo registers (the FVs) also don't pose a problem
1779 because they are stored as 4 individual FP elements. */
1780
1781 static void
1782 sh_register_convert_to_virtual (int regnum, struct type *type,
1783 char *from, char *to)
1784 {
1785 if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
1786 {
1787 DOUBLEST val;
1788 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
1789 from, &val);
1790 store_typed_floating (to, type, val);
1791 }
1792 else
1793 error
1794 ("sh_register_convert_to_virtual called with non DR register number");
1795 }
1796
1797 static void
1798 sh_register_convert_to_raw (struct type *type, int regnum,
1799 const void *from, void *to)
1800 {
1801 if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
1802 {
1803 DOUBLEST val = extract_typed_floating (from, type);
1804 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword,
1805 &val, to);
1806 }
1807 else
1808 error ("sh_register_convert_to_raw called with non DR register number");
1809 }
1810
1811 /* For vectors of 4 floating point registers. */
1812 static int
1813 fv_reg_base_num (int fv_regnum)
1814 {
1815 int fp_regnum;
1816
1817 fp_regnum = FP0_REGNUM + (fv_regnum - FV0_REGNUM) * 4;
1818 return fp_regnum;
1819 }
1820
1821 /* For double precision floating point registers, i.e 2 fp regs.*/
1822 static int
1823 dr_reg_base_num (int dr_regnum)
1824 {
1825 int fp_regnum;
1826
1827 fp_regnum = FP0_REGNUM + (dr_regnum - DR0_REGNUM) * 2;
1828 return fp_regnum;
1829 }
1830
1831 static void
1832 sh_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
1833 int reg_nr, void *buffer)
1834 {
1835 int base_regnum, portion;
1836 char temp_buffer[MAX_REGISTER_SIZE];
1837
1838 if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
1839 {
1840 base_regnum = dr_reg_base_num (reg_nr);
1841
1842 /* Build the value in the provided buffer. */
1843 /* Read the real regs for which this one is an alias. */
1844 for (portion = 0; portion < 2; portion++)
1845 regcache_raw_read (regcache, base_regnum + portion,
1846 (temp_buffer
1847 + register_size (gdbarch,
1848 base_regnum) * portion));
1849 /* We must pay attention to the endiannes. */
1850 sh_register_convert_to_virtual (reg_nr,
1851 gdbarch_register_type (gdbarch, reg_nr),
1852 temp_buffer, buffer);
1853 }
1854 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
1855 {
1856 base_regnum = fv_reg_base_num (reg_nr);
1857
1858 /* Read the real regs for which this one is an alias. */
1859 for (portion = 0; portion < 4; portion++)
1860 regcache_raw_read (regcache, base_regnum + portion,
1861 ((char *) buffer
1862 + register_size (gdbarch,
1863 base_regnum) * portion));
1864 }
1865 }
1866
1867 static void
1868 sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
1869 int reg_nr, const void *buffer)
1870 {
1871 int base_regnum, portion;
1872 char temp_buffer[MAX_REGISTER_SIZE];
1873
1874 if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
1875 {
1876 base_regnum = dr_reg_base_num (reg_nr);
1877
1878 /* We must pay attention to the endiannes. */
1879 sh_register_convert_to_raw (gdbarch_register_type (gdbarch, reg_nr),
1880 reg_nr, buffer, temp_buffer);
1881
1882 /* Write the real regs for which this one is an alias. */
1883 for (portion = 0; portion < 2; portion++)
1884 regcache_raw_write (regcache, base_regnum + portion,
1885 (temp_buffer
1886 + register_size (gdbarch,
1887 base_regnum) * portion));
1888 }
1889 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
1890 {
1891 base_regnum = fv_reg_base_num (reg_nr);
1892
1893 /* Write the real regs for which this one is an alias. */
1894 for (portion = 0; portion < 4; portion++)
1895 regcache_raw_write (regcache, base_regnum + portion,
1896 ((char *) buffer
1897 + register_size (gdbarch,
1898 base_regnum) * portion));
1899 }
1900 }
1901
1902 /* Floating point vector of 4 float registers. */
1903 static void
1904 do_fv_register_info (struct gdbarch *gdbarch, struct ui_file *file,
1905 int fv_regnum)
1906 {
1907 int first_fp_reg_num = fv_reg_base_num (fv_regnum);
1908 fprintf_filtered (file, "fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
1909 fv_regnum - FV0_REGNUM,
1910 (int) read_register (first_fp_reg_num),
1911 (int) read_register (first_fp_reg_num + 1),
1912 (int) read_register (first_fp_reg_num + 2),
1913 (int) read_register (first_fp_reg_num + 3));
1914 }
1915
1916 /* Double precision registers. */
1917 static void
1918 do_dr_register_info (struct gdbarch *gdbarch, struct ui_file *file,
1919 int dr_regnum)
1920 {
1921 int first_fp_reg_num = dr_reg_base_num (dr_regnum);
1922
1923 fprintf_filtered (file, "dr%d\t0x%08x%08x\n",
1924 dr_regnum - DR0_REGNUM,
1925 (int) read_register (first_fp_reg_num),
1926 (int) read_register (first_fp_reg_num + 1));
1927 }
1928 static void
1929 do_bank_register_info (struct gdbarch *gdbarch, struct ui_file *file)
1930 {
1931 fprintf_filtered (file, "bank %d\n",
1932 (int) read_register (BANK_REGNUM));
1933 }
1934
1935 static void
1936 sh_print_pseudo_register (struct gdbarch *gdbarch, struct ui_file *file,
1937 int regnum)
1938 {
1939 if (regnum < NUM_REGS || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
1940 internal_error (__FILE__, __LINE__,
1941 "Invalid pseudo register number %d\n", regnum);
1942 else if (regnum == PSEUDO_BANK_REGNUM)
1943 do_bank_register_info (gdbarch, file);
1944 else if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
1945 do_dr_register_info (gdbarch, file, regnum);
1946 else if (regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM)
1947 do_fv_register_info (gdbarch, file, regnum);
1948 }
1949
1950 static void
1951 sh_do_fp_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
1952 { /* do values for FP (float) regs */
1953 char *raw_buffer;
1954 double flt; /* double extracted from raw hex data */
1955 int inv;
1956 int j;
1957
1958 /* Allocate space for the float. */
1959 raw_buffer = (char *) alloca (register_size (gdbarch, FP0_REGNUM));
1960
1961 /* Get the data in raw format. */
1962 if (!frame_register_read (get_selected_frame (), regnum, raw_buffer))
1963 error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum));
1964
1965 /* Get the register as a number */
1966 flt = unpack_double (builtin_type_float, raw_buffer, &inv);
1967
1968 /* Print the name and some spaces. */
1969 fputs_filtered (REGISTER_NAME (regnum), file);
1970 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file);
1971
1972 /* Print the value. */
1973 if (inv)
1974 fprintf_filtered (file, "<invalid float>");
1975 else
1976 fprintf_filtered (file, "%-10.9g", flt);
1977
1978 /* Print the fp register as hex. */
1979 fprintf_filtered (file, "\t(raw 0x");
1980 for (j = 0; j < register_size (gdbarch, regnum); j++)
1981 {
1982 int idx = (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
1983 ? j
1984 : register_size (gdbarch, regnum) - 1 - j);
1985 fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[idx]);
1986 }
1987 fprintf_filtered (file, ")");
1988 fprintf_filtered (file, "\n");
1989 }
1990
1991 static void
1992 sh_do_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
1993 {
1994 char raw_buffer[MAX_REGISTER_SIZE];
1995
1996 fputs_filtered (REGISTER_NAME (regnum), file);
1997 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file);
1998
1999 /* Get the data in raw format. */
2000 if (!frame_register_read (get_selected_frame (), regnum, raw_buffer))
2001 fprintf_filtered (file, "*value not available*\n");
2002
2003 val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0,
2004 file, 'x', 1, 0, Val_pretty_default);
2005 fprintf_filtered (file, "\t");
2006 val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0,
2007 file, 0, 1, 0, Val_pretty_default);
2008 fprintf_filtered (file, "\n");
2009 }
2010
2011 static void
2012 sh_print_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
2013 {
2014 if (regnum < 0 || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
2015 internal_error (__FILE__, __LINE__,
2016 "Invalid register number %d\n", regnum);
2017
2018 else if (regnum >= 0 && regnum < NUM_REGS)
2019 {
2020 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) ==
2021 TYPE_CODE_FLT)
2022 sh_do_fp_register (gdbarch, file, regnum); /* FP regs */
2023 else
2024 sh_do_register (gdbarch, file, regnum); /* All other regs */
2025 }
2026
2027 else if (regnum < NUM_REGS + NUM_PSEUDO_REGS)
2028 {
2029 sh_print_pseudo_register (gdbarch, file, regnum);
2030 }
2031 }
2032
2033 static void
2034 sh_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
2035 struct frame_info *frame, int regnum, int fpregs)
2036 {
2037 if (regnum != -1) /* do one specified register */
2038 {
2039 if (*(REGISTER_NAME (regnum)) == '\0')
2040 error ("Not a valid register for the current processor type");
2041
2042 sh_print_register (gdbarch, file, regnum);
2043 }
2044 else
2045 /* do all (or most) registers */
2046 {
2047 for (regnum = 0; regnum < NUM_REGS; ++regnum)
2048 {
2049 /* If the register name is empty, it is undefined for this
2050 processor, so don't display anything. */
2051 if (REGISTER_NAME (regnum) == NULL
2052 || *(REGISTER_NAME (regnum)) == '\0')
2053 continue;
2054
2055 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) ==
2056 TYPE_CODE_FLT)
2057 {
2058 /* true for "INFO ALL-REGISTERS" command */
2059 if (fpregs)
2060 sh_do_fp_register (gdbarch, file, regnum); /* FP regs */
2061 }
2062 else
2063 sh_do_register (gdbarch, file, regnum); /* All other regs */
2064 }
2065
2066 if (regnum == PSEUDO_BANK_REGNUM
2067 && REGISTER_NAME (regnum)
2068 && *REGISTER_NAME (regnum))
2069 sh_print_pseudo_register (gdbarch, file, regnum++);
2070
2071 if (fpregs)
2072 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
2073 {
2074 sh_print_pseudo_register (gdbarch, file, regnum);
2075 regnum++;
2076 }
2077 }
2078 }
2079
2080 /* Fetch (and possibly build) an appropriate link_map_offsets structure
2081 for native i386 linux targets using the struct offsets defined in
2082 link.h (but without actual reference to that file).
2083
2084 This makes it possible to access i386-linux shared libraries from
2085 a gdb that was not built on an i386-linux host (for cross debugging).
2086 */
2087
2088 struct link_map_offsets *
2089 sh_linux_svr4_fetch_link_map_offsets (void)
2090 {
2091 static struct link_map_offsets lmo;
2092 static struct link_map_offsets *lmp = 0;
2093
2094 if (lmp == 0)
2095 {
2096 lmp = &lmo;
2097
2098 lmo.r_debug_size = 8; /* 20 not actual size but all we need */
2099
2100 lmo.r_map_offset = 4;
2101 lmo.r_map_size = 4;
2102
2103 lmo.link_map_size = 20; /* 552 not actual size but all we need */
2104
2105 lmo.l_addr_offset = 0;
2106 lmo.l_addr_size = 4;
2107
2108 lmo.l_name_offset = 4;
2109 lmo.l_name_size = 4;
2110
2111 lmo.l_next_offset = 12;
2112 lmo.l_next_size = 4;
2113
2114 lmo.l_prev_offset = 16;
2115 lmo.l_prev_size = 4;
2116 }
2117
2118 return lmp;
2119 }
2120
2121 static int
2122 sh_dsp_register_sim_regno (int nr)
2123 {
2124 if (legacy_register_sim_regno (nr) < 0)
2125 return legacy_register_sim_regno (nr);
2126 if (nr >= DSR_REGNUM && nr <= Y1_REGNUM)
2127 return nr - DSR_REGNUM + SIM_SH_DSR_REGNUM;
2128 if (nr == MOD_REGNUM)
2129 return SIM_SH_MOD_REGNUM;
2130 if (nr == RS_REGNUM)
2131 return SIM_SH_RS_REGNUM;
2132 if (nr == RE_REGNUM)
2133 return SIM_SH_RE_REGNUM;
2134 if (nr >= DSP_R0_BANK_REGNUM && nr <= DSP_R7_BANK_REGNUM)
2135 return nr - DSP_R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM;
2136 return nr;
2137 }
2138
2139 static int
2140 sh_sh2a_register_sim_regno (int nr)
2141 {
2142 switch (nr)
2143 {
2144 case TBR_REGNUM:
2145 return SIM_SH_TBR_REGNUM;
2146 case IBNR_REGNUM:
2147 return SIM_SH_IBNR_REGNUM;
2148 case IBCR_REGNUM:
2149 return SIM_SH_IBCR_REGNUM;
2150 case BANK_REGNUM:
2151 return SIM_SH_BANK_REGNUM;
2152 case MACLB_REGNUM:
2153 return SIM_SH_BANK_MACL_REGNUM;
2154 case GBRB_REGNUM:
2155 return SIM_SH_BANK_GBR_REGNUM;
2156 case PRB_REGNUM:
2157 return SIM_SH_BANK_PR_REGNUM;
2158 case IVNB_REGNUM:
2159 return SIM_SH_BANK_IVN_REGNUM;
2160 case MACHB_REGNUM:
2161 return SIM_SH_BANK_MACH_REGNUM;
2162 default:
2163 break;
2164 }
2165 return legacy_register_sim_regno (nr);
2166 }
2167
2168 static struct sh_frame_cache *
2169 sh_alloc_frame_cache (void)
2170 {
2171 struct sh_frame_cache *cache;
2172 int i;
2173
2174 cache = FRAME_OBSTACK_ZALLOC (struct sh_frame_cache);
2175
2176 /* Base address. */
2177 cache->base = 0;
2178 cache->saved_sp = 0;
2179 cache->sp_offset = 0;
2180 cache->pc = 0;
2181
2182 /* Frameless until proven otherwise. */
2183 cache->uses_fp = 0;
2184
2185 /* Saved registers. We initialize these to -1 since zero is a valid
2186 offset (that's where fp is supposed to be stored). */
2187 for (i = 0; i < SH_NUM_REGS; i++)
2188 {
2189 cache->saved_regs[i] = -1;
2190 }
2191
2192 return cache;
2193 }
2194
2195 static struct sh_frame_cache *
2196 sh_frame_cache (struct frame_info *next_frame, void **this_cache)
2197 {
2198 struct sh_frame_cache *cache;
2199 CORE_ADDR current_pc;
2200 int i;
2201
2202 if (*this_cache)
2203 return *this_cache;
2204
2205 cache = sh_alloc_frame_cache ();
2206 *this_cache = cache;
2207
2208 /* In principle, for normal frames, fp holds the frame pointer,
2209 which holds the base address for the current stack frame.
2210 However, for functions that don't need it, the frame pointer is
2211 optional. For these "frameless" functions the frame pointer is
2212 actually the frame pointer of the calling frame. */
2213 cache->base = frame_unwind_register_unsigned (next_frame, FP_REGNUM);
2214 if (cache->base == 0)
2215 return cache;
2216
2217 cache->pc = frame_func_unwind (next_frame);
2218 current_pc = frame_pc_unwind (next_frame);
2219 if (cache->pc != 0)
2220 sh_analyze_prologue (cache->pc, current_pc, cache);
2221
2222 if (!cache->uses_fp)
2223 {
2224 /* We didn't find a valid frame, which means that CACHE->base
2225 currently holds the frame pointer for our calling frame. If
2226 we're at the start of a function, or somewhere half-way its
2227 prologue, the function's frame probably hasn't been fully
2228 setup yet. Try to reconstruct the base address for the stack
2229 frame by looking at the stack pointer. For truly "frameless"
2230 functions this might work too. */
2231 cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
2232 }
2233
2234 /* Now that we have the base address for the stack frame we can
2235 calculate the value of sp in the calling frame. */
2236 cache->saved_sp = cache->base + cache->sp_offset;
2237
2238 /* Adjust all the saved registers such that they contain addresses
2239 instead of offsets. */
2240 for (i = 0; i < SH_NUM_REGS; i++)
2241 if (cache->saved_regs[i] != -1)
2242 cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i] - 4;
2243
2244 return cache;
2245 }
2246
2247 static void
2248 sh_frame_prev_register (struct frame_info *next_frame, void **this_cache,
2249 int regnum, int *optimizedp,
2250 enum lval_type *lvalp, CORE_ADDR *addrp,
2251 int *realnump, void *valuep)
2252 {
2253 struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
2254
2255 gdb_assert (regnum >= 0);
2256
2257 if (regnum == SP_REGNUM && cache->saved_sp)
2258 {
2259 *optimizedp = 0;
2260 *lvalp = not_lval;
2261 *addrp = 0;
2262 *realnump = -1;
2263 if (valuep)
2264 {
2265 /* Store the value. */
2266 store_unsigned_integer (valuep, 4, cache->saved_sp);
2267 }
2268 return;
2269 }
2270
2271 /* The PC of the previous frame is stored in the PR register of
2272 the current frame. Frob regnum so that we pull the value from
2273 the correct place. */
2274 if (regnum == PC_REGNUM)
2275 regnum = PR_REGNUM;
2276
2277 if (regnum < SH_NUM_REGS && cache->saved_regs[regnum] != -1)
2278 {
2279 *optimizedp = 0;
2280 *lvalp = lval_memory;
2281 *addrp = cache->saved_regs[regnum];
2282 *realnump = -1;
2283 if (valuep)
2284 {
2285 /* Read the value in from memory. */
2286 read_memory (*addrp, valuep,
2287 register_size (current_gdbarch, regnum));
2288 }
2289 return;
2290 }
2291
2292 frame_register_unwind (next_frame, regnum,
2293 optimizedp, lvalp, addrp, realnump, valuep);
2294 }
2295
2296 static void
2297 sh_frame_this_id (struct frame_info *next_frame, void **this_cache,
2298 struct frame_id *this_id)
2299 {
2300 struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
2301
2302 /* This marks the outermost frame. */
2303 if (cache->base == 0)
2304 return;
2305
2306 *this_id = frame_id_build (cache->saved_sp, cache->pc);
2307 }
2308
2309 static const struct frame_unwind sh_frame_unwind = {
2310 NORMAL_FRAME,
2311 sh_frame_this_id,
2312 sh_frame_prev_register
2313 };
2314
2315 static const struct frame_unwind *
2316 sh_frame_sniffer (struct frame_info *next_frame)
2317 {
2318 return &sh_frame_unwind;
2319 }
2320
2321 static CORE_ADDR
2322 sh_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
2323 {
2324 return frame_unwind_register_unsigned (next_frame, SP_REGNUM);
2325 }
2326
2327 static CORE_ADDR
2328 sh_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2329 {
2330 return frame_unwind_register_unsigned (next_frame, PC_REGNUM);
2331 }
2332
2333 static struct frame_id
2334 sh_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
2335 {
2336 return frame_id_build (sh_unwind_sp (gdbarch, next_frame),
2337 frame_pc_unwind (next_frame));
2338 }
2339
2340 static CORE_ADDR
2341 sh_frame_base_address (struct frame_info *next_frame, void **this_cache)
2342 {
2343 struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
2344
2345 return cache->base;
2346 }
2347
2348 static const struct frame_base sh_frame_base = {
2349 &sh_frame_unwind,
2350 sh_frame_base_address,
2351 sh_frame_base_address,
2352 sh_frame_base_address
2353 };
2354
2355 /* The epilogue is defined here as the area at the end of a function,
2356 either on the `ret' instruction itself or after an instruction which
2357 destroys the function's stack frame. */
2358 static int
2359 sh_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
2360 {
2361 CORE_ADDR func_addr = 0, func_end = 0;
2362
2363 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
2364 {
2365 ULONGEST inst;
2366 /* The sh epilogue is max. 14 bytes long. Give another 14 bytes
2367 for a nop and some fixed data (e.g. big offsets) which are
2368 unfortunately also treated as part of the function (which
2369 means, they are below func_end. */
2370 CORE_ADDR addr = func_end - 28;
2371 if (addr < func_addr + 4)
2372 addr = func_addr + 4;
2373 if (pc < addr)
2374 return 0;
2375
2376 /* First search forward until hitting an rts. */
2377 while (addr < func_end
2378 && !IS_RTS (read_memory_unsigned_integer (addr, 2)))
2379 addr += 2;
2380 if (addr >= func_end)
2381 return 0;
2382
2383 /* At this point we should find a mov.l @r15+,r14 instruction,
2384 either before or after the rts. If not, then the function has
2385 probably no "normal" epilogue and we bail out here. */
2386 inst = read_memory_unsigned_integer (addr - 2, 2);
2387 if (IS_RESTORE_FP (read_memory_unsigned_integer (addr - 2, 2)))
2388 addr -= 2;
2389 else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr + 2, 2)))
2390 return 0;
2391
2392 /* Step over possible lds.l @r15+,pr. */
2393 inst = read_memory_unsigned_integer (addr - 2, 2);
2394 if (IS_LDS (inst))
2395 {
2396 addr -= 2;
2397 inst = read_memory_unsigned_integer (addr - 2, 2);
2398 }
2399
2400 /* Step over possible mov r14,r15. */
2401 if (IS_MOV_FP_SP (inst))
2402 {
2403 addr -= 2;
2404 inst = read_memory_unsigned_integer (addr - 2, 2);
2405 }
2406
2407 /* Now check for FP adjustments, using add #imm,r14 or add rX, r14
2408 instructions. */
2409 while (addr > func_addr + 4
2410 && (IS_ADD_REG_TO_FP (inst) || IS_ADD_IMM_FP (inst)))
2411 {
2412 addr -= 2;
2413 inst = read_memory_unsigned_integer (addr - 2, 2);
2414 }
2415
2416 if (pc >= addr)
2417 return 1;
2418 }
2419 return 0;
2420 }
2421
2422 static gdbarch_init_ftype sh_gdbarch_init;
2423
2424 static struct gdbarch *
2425 sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2426 {
2427 struct gdbarch *gdbarch;
2428
2429 sh_show_regs = sh_generic_show_regs;
2430 switch (info.bfd_arch_info->mach)
2431 {
2432 case bfd_mach_sh2e:
2433 sh_show_regs = sh2e_show_regs;
2434 break;
2435 case bfd_mach_sh2a:
2436 sh_show_regs = sh2a_show_regs;
2437 break;
2438 case bfd_mach_sh2a_nofpu:
2439 sh_show_regs = sh2a_nofpu_show_regs;
2440 break;
2441 case bfd_mach_sh_dsp:
2442 sh_show_regs = sh_dsp_show_regs;
2443 break;
2444
2445 case bfd_mach_sh3:
2446 sh_show_regs = sh3_show_regs;
2447 break;
2448
2449 case bfd_mach_sh3e:
2450 sh_show_regs = sh3e_show_regs;
2451 break;
2452
2453 case bfd_mach_sh3_dsp:
2454 case bfd_mach_sh4al_dsp:
2455 sh_show_regs = sh3_dsp_show_regs;
2456 break;
2457
2458 case bfd_mach_sh4:
2459 case bfd_mach_sh4a:
2460 sh_show_regs = sh4_show_regs;
2461 break;
2462
2463 case bfd_mach_sh4_nofpu:
2464 case bfd_mach_sh4a_nofpu:
2465 sh_show_regs = sh4_nofpu_show_regs;
2466 break;
2467
2468 #if 0
2469 case bfd_mach_sh5:
2470 sh_show_regs = sh64_show_regs;
2471 /* SH5 is handled entirely in sh64-tdep.c */
2472 return sh64_gdbarch_init (info, arches);
2473 #endif
2474 }
2475
2476 /* If there is already a candidate, use it. */
2477 arches = gdbarch_list_lookup_by_info (arches, &info);
2478 if (arches != NULL)
2479 return arches->gdbarch;
2480
2481 /* None found, create a new architecture from the information
2482 provided. */
2483 gdbarch = gdbarch_alloc (&info, NULL);
2484
2485 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2486 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2487 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2488 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2489 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2490 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2491 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2492 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2493
2494 set_gdbarch_num_regs (gdbarch, SH_NUM_REGS);
2495 set_gdbarch_sp_regnum (gdbarch, 15);
2496 set_gdbarch_pc_regnum (gdbarch, 16);
2497 set_gdbarch_fp0_regnum (gdbarch, -1);
2498 set_gdbarch_num_pseudo_regs (gdbarch, 0);
2499
2500 set_gdbarch_register_type (gdbarch, sh_default_register_type);
2501
2502 set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info);
2503
2504 set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc);
2505 set_gdbarch_deprecated_use_struct_convention (gdbarch, sh_use_struct_convention);
2506
2507 set_gdbarch_print_insn (gdbarch, gdb_print_insn_sh);
2508 set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno);
2509
2510 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
2511
2512 set_gdbarch_store_return_value (gdbarch, sh_default_store_return_value);
2513 set_gdbarch_extract_return_value (gdbarch, sh_default_extract_return_value);
2514 set_gdbarch_deprecated_extract_struct_value_address (gdbarch, sh_extract_struct_value_address);
2515
2516 set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue);
2517 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2518
2519 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu);
2520
2521 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2522
2523 set_gdbarch_frame_align (gdbarch, sh_frame_align);
2524 set_gdbarch_unwind_sp (gdbarch, sh_unwind_sp);
2525 set_gdbarch_unwind_pc (gdbarch, sh_unwind_pc);
2526 set_gdbarch_unwind_dummy_id (gdbarch, sh_unwind_dummy_id);
2527 frame_base_set_default (gdbarch, &sh_frame_base);
2528
2529 set_gdbarch_in_function_epilogue_p (gdbarch, sh_in_function_epilogue_p);
2530
2531 switch (info.bfd_arch_info->mach)
2532 {
2533 case bfd_mach_sh:
2534 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
2535 break;
2536
2537 case bfd_mach_sh2:
2538 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
2539 break;
2540
2541 case bfd_mach_sh2e:
2542 /* doubles on sh2e and sh3e are actually 4 byte. */
2543 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2544
2545 set_gdbarch_register_name (gdbarch, sh_sh2e_register_name);
2546 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
2547 set_gdbarch_fp0_regnum (gdbarch, 25);
2548 set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value);
2549 set_gdbarch_extract_return_value (gdbarch,
2550 sh3e_sh4_extract_return_value);
2551 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2552 break;
2553
2554 case bfd_mach_sh2a:
2555 set_gdbarch_register_name (gdbarch, sh_sh2a_register_name);
2556 set_gdbarch_register_type (gdbarch, sh_sh2a_register_type);
2557 set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno);
2558
2559 set_gdbarch_fp0_regnum (gdbarch, 25);
2560 set_gdbarch_num_pseudo_regs (gdbarch, 9);
2561 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
2562 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
2563 set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value);
2564 set_gdbarch_extract_return_value (gdbarch, sh3e_sh4_extract_return_value);
2565 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2566 break;
2567
2568 case bfd_mach_sh2a_nofpu:
2569 set_gdbarch_register_name (gdbarch, sh_sh2a_nofpu_register_name);
2570 set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno);
2571
2572 set_gdbarch_num_pseudo_regs (gdbarch, 1);
2573 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
2574 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
2575 break;
2576
2577 case bfd_mach_sh_dsp:
2578 set_gdbarch_register_name (gdbarch, sh_sh_dsp_register_name);
2579 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
2580 break;
2581
2582 case bfd_mach_sh3:
2583 set_gdbarch_register_name (gdbarch, sh_sh3_register_name);
2584 break;
2585
2586 case bfd_mach_sh3e:
2587 /* doubles on sh2e and sh3e are actually 4 byte. */
2588 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2589
2590 set_gdbarch_register_name (gdbarch, sh_sh3e_register_name);
2591 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
2592 set_gdbarch_fp0_regnum (gdbarch, 25);
2593 set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value);
2594 set_gdbarch_extract_return_value (gdbarch,
2595 sh3e_sh4_extract_return_value);
2596 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2597 break;
2598
2599 case bfd_mach_sh3_dsp:
2600 set_gdbarch_register_name (gdbarch, sh_sh3_dsp_register_name);
2601 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
2602 break;
2603
2604 case bfd_mach_sh4:
2605 case bfd_mach_sh4a:
2606 set_gdbarch_register_name (gdbarch, sh_sh4_register_name);
2607 set_gdbarch_register_type (gdbarch, sh_sh4_register_type);
2608 set_gdbarch_fp0_regnum (gdbarch, 25);
2609 set_gdbarch_num_pseudo_regs (gdbarch, 13);
2610 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
2611 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
2612 set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value);
2613 set_gdbarch_extract_return_value (gdbarch,
2614 sh3e_sh4_extract_return_value);
2615 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2616 break;
2617
2618 case bfd_mach_sh4_nofpu:
2619 case bfd_mach_sh4a_nofpu:
2620 set_gdbarch_register_name (gdbarch, sh_sh4_nofpu_register_name);
2621 break;
2622
2623 case bfd_mach_sh4al_dsp:
2624 set_gdbarch_register_name (gdbarch, sh_sh4al_dsp_register_name);
2625 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
2626 break;
2627
2628 default:
2629 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
2630 break;
2631 }
2632
2633 /* Hook in ABI-specific overrides, if they have been registered. */
2634 gdbarch_init_osabi (info, gdbarch);
2635
2636 frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer);
2637 frame_unwind_append_sniffer (gdbarch, sh_frame_sniffer);
2638
2639 return gdbarch;
2640 }
2641
2642 extern initialize_file_ftype _initialize_sh_tdep; /* -Wmissing-prototypes */
2643
2644 void
2645 _initialize_sh_tdep (void)
2646 {
2647 struct cmd_list_element *c;
2648
2649 gdbarch_register (bfd_arch_sh, sh_gdbarch_init, NULL);
2650
2651 add_com ("regs", class_vars, sh_show_regs_command, "Print all registers");
2652 }