1 /* Target-dependent code for Renesas Super-H, for GDB.
3 Copyright (C) 1993-2016 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20 /* Contributed by Steve Chamberlain
25 #include "frame-base.h"
26 #include "frame-unwind.h"
27 #include "dwarf2-frame.h"
35 #include "arch-utils.h"
44 /* Register numbers shared with the simulator. */
45 #include "gdb/sim-sh.h"
47 #include "sh64-tdep.h"
49 /* Information that is dependent on the processor variant. */
62 struct sh64_frame_cache
69 /* Flag showing that a frame has been created in the prologue code. */
74 /* Saved registers. */
75 CORE_ADDR saved_regs
[SIM_SH64_NR_REGS
];
79 /* Registers of SH5 */
83 DEFAULT_RETURN_REGNUM
= 2,
84 STRUCT_RETURN_REGNUM
= 2,
87 FLOAT_ARGLAST_REGNUM
= 11,
93 /* FPP stands for Floating Point Pair, to avoid confusion with
94 GDB's gdbarch_fp0_regnum, which is the number of the first Floating
95 point register. Unfortunately on the sh5, the floating point
96 registers are called FR, and the floating point pairs are called FP. */
98 FPP_LAST_REGNUM
= 204,
100 FV_LAST_REGNUM
= 220,
102 R_LAST_C_REGNUM
= 236,
109 FPSCR_C_REGNUM
= 243,
112 FP_LAST_C_REGNUM
= 260,
114 DR_LAST_C_REGNUM
= 268,
116 FV_LAST_C_REGNUM
= 272,
117 FPSCR_REGNUM
= SIM_SH64_FPCSR_REGNUM
,
118 SSR_REGNUM
= SIM_SH64_SSR_REGNUM
,
119 SPC_REGNUM
= SIM_SH64_SPC_REGNUM
,
120 TR7_REGNUM
= SIM_SH64_TR0_REGNUM
+ 7,
121 FP_LAST_REGNUM
= SIM_SH64_FR0_REGNUM
+ SIM_SH64_NR_FP_REGS
- 1
125 sh64_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
127 static char *register_names
[] =
129 /* SH MEDIA MODE (ISA 32) */
130 /* general registers (64-bit) 0-63 */
131 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
132 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
133 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
134 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
135 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
136 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
137 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
138 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
143 /* status reg., saved status reg., saved pc reg. (64-bit) 65-67 */
146 /* target registers (64-bit) 68-75 */
147 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7",
149 /* floating point state control register (32-bit) 76 */
152 /* single precision floating point registers (32-bit) 77-140 */
153 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
154 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
155 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23",
156 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31",
157 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39",
158 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47",
159 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55",
160 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63",
162 /* double precision registers (pseudo) 141-172 */
163 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
164 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30",
165 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46",
166 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62",
168 /* floating point pairs (pseudo) 173-204 */
169 "fp0", "fp2", "fp4", "fp6", "fp8", "fp10", "fp12", "fp14",
170 "fp16", "fp18", "fp20", "fp22", "fp24", "fp26", "fp28", "fp30",
171 "fp32", "fp34", "fp36", "fp38", "fp40", "fp42", "fp44", "fp46",
172 "fp48", "fp50", "fp52", "fp54", "fp56", "fp58", "fp60", "fp62",
174 /* floating point vectors (4 floating point regs) (pseudo) 205-220 */
175 "fv0", "fv4", "fv8", "fv12", "fv16", "fv20", "fv24", "fv28",
176 "fv32", "fv36", "fv40", "fv44", "fv48", "fv52", "fv56", "fv60",
178 /* SH COMPACT MODE (ISA 16) (all pseudo) 221-272 */
179 "r0_c", "r1_c", "r2_c", "r3_c", "r4_c", "r5_c", "r6_c", "r7_c",
180 "r8_c", "r9_c", "r10_c", "r11_c", "r12_c", "r13_c", "r14_c", "r15_c",
182 "gbr_c", "mach_c", "macl_c", "pr_c", "t_c",
184 "fr0_c", "fr1_c", "fr2_c", "fr3_c",
185 "fr4_c", "fr5_c", "fr6_c", "fr7_c",
186 "fr8_c", "fr9_c", "fr10_c", "fr11_c",
187 "fr12_c", "fr13_c", "fr14_c", "fr15_c",
188 "dr0_c", "dr2_c", "dr4_c", "dr6_c",
189 "dr8_c", "dr10_c", "dr12_c", "dr14_c",
190 "fv0_c", "fv4_c", "fv8_c", "fv12_c",
191 /* FIXME!!!! XF0 XF15, XD0 XD14 ????? */
196 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
198 return register_names
[reg_nr
];
201 #define NUM_PSEUDO_REGS_SH_MEDIA 80
202 #define NUM_PSEUDO_REGS_SH_COMPACT 51
204 /* Macros and functions for setting and testing a bit in a minimal
205 symbol that marks it as 32-bit function. The MSB of the minimal
206 symbol's "info" field is used for this purpose.
208 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special",
209 i.e. refers to a 32-bit function, and sets a "special" bit in a
210 minimal symbol to mark it as a 32-bit function
211 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
213 #define MSYMBOL_IS_SPECIAL(msym) \
214 MSYMBOL_TARGET_FLAG_1 (msym)
217 sh64_elf_make_msymbol_special (asymbol
*sym
, struct minimal_symbol
*msym
)
222 if (((elf_symbol_type
*)(sym
))->internal_elf_sym
.st_other
== STO_SH5_ISA32
)
224 MSYMBOL_TARGET_FLAG_1 (msym
) = 1;
225 SET_MSYMBOL_VALUE_ADDRESS (msym
, MSYMBOL_VALUE_RAW_ADDRESS (msym
) | 1);
229 /* ISA32 (shmedia) function addresses are odd (bit 0 is set). Here
230 are some macros to test, set, or clear bit 0 of addresses. */
231 #define IS_ISA32_ADDR(addr) ((addr) & 1)
232 #define MAKE_ISA32_ADDR(addr) ((addr) | 1)
233 #define UNMAKE_ISA32_ADDR(addr) ((addr) & ~1)
236 pc_is_isa32 (bfd_vma memaddr
)
238 struct bound_minimal_symbol sym
;
240 /* If bit 0 of the address is set, assume this is a
241 ISA32 (shmedia) address. */
242 if (IS_ISA32_ADDR (memaddr
))
245 /* A flag indicating that this is a ISA32 function is stored by elfread.c in
246 the high bit of the info field. Use this to decide if the function is
248 sym
= lookup_minimal_symbol_by_pc (memaddr
);
250 return MSYMBOL_IS_SPECIAL (sym
.minsym
);
255 static const unsigned char *
256 sh64_breakpoint_from_pc (struct gdbarch
*gdbarch
,
257 CORE_ADDR
*pcptr
, int *lenptr
)
259 /* The BRK instruction for shmedia is
260 01101111 11110101 11111111 11110000
261 which translates in big endian mode to 0x6f, 0xf5, 0xff, 0xf0
262 and in little endian mode to 0xf0, 0xff, 0xf5, 0x6f */
264 /* The BRK instruction for shcompact is
266 which translates in big endian mode to 0x0, 0x3b
267 and in little endian mode to 0x3b, 0x0 */
269 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
271 if (pc_is_isa32 (*pcptr
))
273 static unsigned char big_breakpoint_media
[] = {
274 0x6f, 0xf5, 0xff, 0xf0
276 *pcptr
= UNMAKE_ISA32_ADDR (*pcptr
);
277 *lenptr
= sizeof (big_breakpoint_media
);
278 return big_breakpoint_media
;
282 static unsigned char big_breakpoint_compact
[] = {0x0, 0x3b};
283 *lenptr
= sizeof (big_breakpoint_compact
);
284 return big_breakpoint_compact
;
289 if (pc_is_isa32 (*pcptr
))
291 static unsigned char little_breakpoint_media
[] = {
292 0xf0, 0xff, 0xf5, 0x6f
294 *pcptr
= UNMAKE_ISA32_ADDR (*pcptr
);
295 *lenptr
= sizeof (little_breakpoint_media
);
296 return little_breakpoint_media
;
300 static unsigned char little_breakpoint_compact
[] = {0x3b, 0x0};
301 *lenptr
= sizeof (little_breakpoint_compact
);
302 return little_breakpoint_compact
;
307 /* Prologue looks like
308 [mov.l <regs>,@-r15]...
313 Actually it can be more complicated than this. For instance, with
331 /* PTABS/L Rn, TRa 0110101111110001nnnnnnl00aaa0000
332 with l=1 and n = 18 0110101111110001010010100aaa0000 */
333 #define IS_PTABSL_R18(x) (((x) & 0xffffff8f) == 0x6bf14a00)
335 /* STS.L PR,@-r0 0100000000100010
336 r0-4-->r0, PR-->(r0) */
337 #define IS_STS_R0(x) ((x) == 0x4022)
339 /* STS PR, Rm 0000mmmm00101010
341 #define IS_STS_PR(x) (((x) & 0xf0ff) == 0x2a)
343 /* MOV.L Rm,@(disp,r15) 00011111mmmmdddd
345 #define IS_MOV_TO_R15(x) (((x) & 0xff00) == 0x1f00)
347 /* MOV.L R14,@(disp,r15) 000111111110dddd
348 R14-->(dispx4+r15) */
349 #define IS_MOV_R14(x) (((x) & 0xfff0) == 0x1fe0)
351 /* ST.Q R14, disp, R18 101011001110dddddddddd0100100000
352 R18-->(dispx8+R14) */
353 #define IS_STQ_R18_R14(x) (((x) & 0xfff003ff) == 0xace00120)
355 /* ST.Q R15, disp, R18 101011001111dddddddddd0100100000
356 R18-->(dispx8+R15) */
357 #define IS_STQ_R18_R15(x) (((x) & 0xfff003ff) == 0xacf00120)
359 /* ST.L R15, disp, R18 101010001111dddddddddd0100100000
360 R18-->(dispx4+R15) */
361 #define IS_STL_R18_R15(x) (((x) & 0xfff003ff) == 0xa8f00120)
363 /* ST.Q R15, disp, R14 1010 1100 1111 dddd dddd dd00 1110 0000
364 R14-->(dispx8+R15) */
365 #define IS_STQ_R14_R15(x) (((x) & 0xfff003ff) == 0xacf000e0)
367 /* ST.L R15, disp, R14 1010 1000 1111 dddd dddd dd00 1110 0000
368 R14-->(dispx4+R15) */
369 #define IS_STL_R14_R15(x) (((x) & 0xfff003ff) == 0xa8f000e0)
371 /* ADDI.L R15,imm,R15 1101 0100 1111 ssss ssss ss00 1111 0000
373 #define IS_ADDIL_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd4f000f0)
375 /* ADDI R15,imm,R15 1101 0000 1111 ssss ssss ss00 1111 0000
377 #define IS_ADDI_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd0f000f0)
379 /* ADD.L R15,R63,R14 0000 0000 1111 1000 1111 1100 1110 0000
381 #define IS_ADDL_SP_FP_MEDIA(x) ((x) == 0x00f8fce0)
383 /* ADD R15,R63,R14 0000 0000 1111 1001 1111 1100 1110 0000
385 #define IS_ADD_SP_FP_MEDIA(x) ((x) == 0x00f9fce0)
387 #define IS_MOV_SP_FP_MEDIA(x) \
388 (IS_ADDL_SP_FP_MEDIA(x) || IS_ADD_SP_FP_MEDIA(x))
390 /* MOV #imm, R0 1110 0000 ssss ssss
392 #define IS_MOV_R0(x) (((x) & 0xff00) == 0xe000)
394 /* MOV.L @(disp,PC), R0 1101 0000 iiii iiii */
395 #define IS_MOVL_R0(x) (((x) & 0xff00) == 0xd000)
397 /* ADD r15,r0 0011 0000 1111 1100
399 #define IS_ADD_SP_R0(x) ((x) == 0x30fc)
401 /* MOV.L R14 @-R0 0010 0000 1110 0110
402 R14-->(R0-4), R0-4-->R0 */
403 #define IS_MOV_R14_R0(x) ((x) == 0x20e6)
405 /* ADD Rm,R63,Rn Rm+R63-->Rn 0000 00mm mmmm 1001 1111 11nn nnnn 0000
406 where Rm is one of r2-r9 which are the argument registers. */
407 /* FIXME: Recognize the float and double register moves too! */
408 #define IS_MEDIA_IND_ARG_MOV(x) \
409 ((((x) & 0xfc0ffc0f) == 0x0009fc00) \
410 && (((x) & 0x03f00000) >= 0x00200000 \
411 && ((x) & 0x03f00000) <= 0x00900000))
413 /* ST.Q Rn,0,Rm Rm-->Rn+0 1010 11nn nnnn 0000 0000 00mm mmmm 0000
414 or ST.L Rn,0,Rm Rm-->Rn+0 1010 10nn nnnn 0000 0000 00mm mmmm 0000
415 where Rm is one of r2-r9 which are the argument registers. */
416 #define IS_MEDIA_ARG_MOV(x) \
417 (((((x) & 0xfc0ffc0f) == 0xac000000) || (((x) & 0xfc0ffc0f) == 0xa8000000)) \
418 && (((x) & 0x000003f0) >= 0x00000020 && ((x) & 0x000003f0) <= 0x00000090))
420 /* ST.B R14,0,Rn Rn-->(R14+0) 1010 0000 1110 0000 0000 00nn nnnn 0000 */
421 /* ST.W R14,0,Rn Rn-->(R14+0) 1010 0100 1110 0000 0000 00nn nnnn 0000 */
422 /* ST.L R14,0,Rn Rn-->(R14+0) 1010 1000 1110 0000 0000 00nn nnnn 0000 */
423 /* FST.S R14,0,FRn Rn-->(R14+0) 1011 0100 1110 0000 0000 00nn nnnn 0000 */
424 /* FST.D R14,0,DRn Rn-->(R14+0) 1011 1100 1110 0000 0000 00nn nnnn 0000 */
425 #define IS_MEDIA_MOV_TO_R14(x) \
426 ((((x) & 0xfffffc0f) == 0xa0e00000) \
427 || (((x) & 0xfffffc0f) == 0xa4e00000) \
428 || (((x) & 0xfffffc0f) == 0xa8e00000) \
429 || (((x) & 0xfffffc0f) == 0xb4e00000) \
430 || (((x) & 0xfffffc0f) == 0xbce00000))
432 /* MOV Rm, Rn Rm-->Rn 0110 nnnn mmmm 0011
434 #define IS_COMPACT_IND_ARG_MOV(x) \
435 ((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0020) \
436 && (((x) & 0x00f0) <= 0x0090))
438 /* compact direct arg move!
439 MOV.L Rn, @r14 0010 1110 mmmm 0010 */
440 #define IS_COMPACT_ARG_MOV(x) \
441 (((((x) & 0xff0f) == 0x2e02) && (((x) & 0x00f0) >= 0x0020) \
442 && ((x) & 0x00f0) <= 0x0090))
444 /* MOV.B Rm, @R14 0010 1110 mmmm 0000
445 MOV.W Rm, @R14 0010 1110 mmmm 0001 */
446 #define IS_COMPACT_MOV_TO_R14(x) \
447 ((((x) & 0xff0f) == 0x2e00) || (((x) & 0xff0f) == 0x2e01))
449 #define IS_JSR_R0(x) ((x) == 0x400b)
450 #define IS_NOP(x) ((x) == 0x0009)
453 /* MOV r15,r14 0110111011110011
455 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
457 /* ADD #imm,r15 01111111iiiiiiii
459 #define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00)
461 /* Skip any prologue before the guts of a function. */
463 /* Skip the prologue using the debug information. If this fails we'll
464 fall back on the 'guess' method below. */
466 after_prologue (CORE_ADDR pc
)
468 struct symtab_and_line sal
;
469 CORE_ADDR func_addr
, func_end
;
471 /* If we can not find the symbol in the partial symbol table, then
472 there is no hope we can determine the function's start address
474 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
478 /* Get the line associated with FUNC_ADDR. */
479 sal
= find_pc_line (func_addr
, 0);
481 /* There are only two cases to consider. First, the end of the source line
482 is within the function bounds. In that case we return the end of the
483 source line. Second is the end of the source line extends beyond the
484 bounds of the current function. We need to use the slow code to
485 examine instructions in that case. */
486 if (sal
.end
< func_end
)
493 look_for_args_moves (struct gdbarch
*gdbarch
,
494 CORE_ADDR start_pc
, int media_mode
)
496 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
499 int insn_size
= (media_mode
? 4 : 2);
501 for (here
= start_pc
, end
= start_pc
+ (insn_size
* 28); here
< end
;)
505 w
= read_memory_integer (UNMAKE_ISA32_ADDR (here
),
506 insn_size
, byte_order
);
508 if (IS_MEDIA_IND_ARG_MOV (w
))
510 /* This must be followed by a store to r14, so the argument
511 is where the debug info says it is. This can happen after
512 the SP has been saved, unfortunately. */
514 int next_insn
= read_memory_integer (UNMAKE_ISA32_ADDR (here
),
515 insn_size
, byte_order
);
517 if (IS_MEDIA_MOV_TO_R14 (next_insn
))
520 else if (IS_MEDIA_ARG_MOV (w
))
522 /* These instructions store directly the argument in r14. */
530 w
= read_memory_integer (here
, insn_size
, byte_order
);
533 if (IS_COMPACT_IND_ARG_MOV (w
))
535 /* This must be followed by a store to r14, so the argument
536 is where the debug info says it is. This can happen after
537 the SP has been saved, unfortunately. */
539 int next_insn
= 0xffff & read_memory_integer (here
, insn_size
,
542 if (IS_COMPACT_MOV_TO_R14 (next_insn
))
545 else if (IS_COMPACT_ARG_MOV (w
))
547 /* These instructions store directly the argument in r14. */
550 else if (IS_MOVL_R0 (w
))
552 /* There is a function that gcc calls to get the arguments
553 passed correctly to the function. Only after this
554 function call the arguments will be found at the place
555 where they are supposed to be. This happens in case the
556 argument has to be stored into a 64-bit register (for
557 instance doubles, long longs). SHcompact doesn't have
558 access to the full 64-bits, so we store the register in
559 stack slot and store the address of the stack slot in
560 the register, then do a call through a wrapper that
561 loads the memory value into the register. A SHcompact
562 callee calls an argument decoder
563 (GCC_shcompact_incoming_args) that stores the 64-bit
564 value in a stack slot and stores the address of the
565 stack slot in the register. GCC thinks the argument is
566 just passed by transparent reference, but this is only
567 true after the argument decoder is called. Such a call
568 needs to be considered part of the prologue. */
570 /* This must be followed by a JSR @r0 instruction and by
571 a NOP instruction. After these, the prologue is over! */
573 int next_insn
= 0xffff & read_memory_integer (here
, insn_size
,
576 if (IS_JSR_R0 (next_insn
))
578 next_insn
= 0xffff & read_memory_integer (here
, insn_size
,
582 if (IS_NOP (next_insn
))
595 sh64_skip_prologue_hard_way (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
597 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
606 if (pc_is_isa32 (start_pc
) == 0)
612 for (here
= start_pc
, end
= start_pc
+ (insn_size
* 28); here
< end
;)
617 int w
= read_memory_integer (UNMAKE_ISA32_ADDR (here
),
618 insn_size
, byte_order
);
620 if (IS_STQ_R18_R14 (w
) || IS_STQ_R18_R15 (w
) || IS_STQ_R14_R15 (w
)
621 || IS_STL_R14_R15 (w
) || IS_STL_R18_R15 (w
)
622 || IS_ADDIL_SP_MEDIA (w
) || IS_ADDI_SP_MEDIA (w
)
623 || IS_PTABSL_R18 (w
))
627 else if (IS_MOV_SP_FP (w
) || IS_MOV_SP_FP_MEDIA(w
))
635 /* Don't bail out yet, we may have arguments stored in
636 registers here, according to the debug info, so that
637 gdb can print the frames correctly. */
638 start_pc
= look_for_args_moves (gdbarch
,
639 here
- insn_size
, media_mode
);
645 int w
= 0xffff & read_memory_integer (here
, insn_size
, byte_order
);
648 if (IS_STS_R0 (w
) || IS_STS_PR (w
)
649 || IS_MOV_TO_R15 (w
) || IS_MOV_R14 (w
)
650 || IS_MOV_R0 (w
) || IS_ADD_SP_R0 (w
) || IS_MOV_R14_R0 (w
))
654 else if (IS_MOV_SP_FP (w
))
662 /* Don't bail out yet, we may have arguments stored in
663 registers here, according to the debug info, so that
664 gdb can print the frames correctly. */
665 start_pc
= look_for_args_moves (gdbarch
,
666 here
- insn_size
, media_mode
);
676 sh64_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
678 CORE_ADDR post_prologue_pc
;
680 /* See if we can determine the end of the prologue via the symbol table.
681 If so, then return either PC, or the PC after the prologue, whichever
683 post_prologue_pc
= after_prologue (pc
);
685 /* If after_prologue returned a useful address, then use it. Else
686 fall back on the instruction skipping code. */
687 if (post_prologue_pc
!= 0)
688 return max (pc
, post_prologue_pc
);
690 return sh64_skip_prologue_hard_way (gdbarch
, pc
);
693 /* Should call_function allocate stack space for a struct return? */
695 sh64_use_struct_convention (struct type
*type
)
697 return (TYPE_LENGTH (type
) > 8);
700 /* For vectors of 4 floating point registers. */
702 sh64_fv_reg_base_num (struct gdbarch
*gdbarch
, int fv_regnum
)
706 fp_regnum
= gdbarch_fp0_regnum (gdbarch
) + (fv_regnum
- FV0_REGNUM
) * 4;
710 /* For double precision floating point registers, i.e 2 fp regs. */
712 sh64_dr_reg_base_num (struct gdbarch
*gdbarch
, int dr_regnum
)
716 fp_regnum
= gdbarch_fp0_regnum (gdbarch
) + (dr_regnum
- DR0_REGNUM
) * 2;
720 /* For pairs of floating point registers. */
722 sh64_fpp_reg_base_num (struct gdbarch
*gdbarch
, int fpp_regnum
)
726 fp_regnum
= gdbarch_fp0_regnum (gdbarch
) + (fpp_regnum
- FPP0_REGNUM
) * 2;
732 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
733 GDB_REGNUM BASE_REGNUM
793 sh64_compact_reg_base_num (struct gdbarch
*gdbarch
, int reg_nr
)
795 int base_regnum
= reg_nr
;
797 /* general register N maps to general register N */
798 if (reg_nr
>= R0_C_REGNUM
799 && reg_nr
<= R_LAST_C_REGNUM
)
800 base_regnum
= reg_nr
- R0_C_REGNUM
;
802 /* floating point register N maps to floating point register N */
803 else if (reg_nr
>= FP0_C_REGNUM
804 && reg_nr
<= FP_LAST_C_REGNUM
)
805 base_regnum
= reg_nr
- FP0_C_REGNUM
+ gdbarch_fp0_regnum (gdbarch
);
807 /* double prec register N maps to base regnum for double prec register N */
808 else if (reg_nr
>= DR0_C_REGNUM
809 && reg_nr
<= DR_LAST_C_REGNUM
)
810 base_regnum
= sh64_dr_reg_base_num (gdbarch
,
811 DR0_REGNUM
+ reg_nr
- DR0_C_REGNUM
);
813 /* vector N maps to base regnum for vector register N */
814 else if (reg_nr
>= FV0_C_REGNUM
815 && reg_nr
<= FV_LAST_C_REGNUM
)
816 base_regnum
= sh64_fv_reg_base_num (gdbarch
,
817 FV0_REGNUM
+ reg_nr
- FV0_C_REGNUM
);
819 else if (reg_nr
== PC_C_REGNUM
)
820 base_regnum
= gdbarch_pc_regnum (gdbarch
);
822 else if (reg_nr
== GBR_C_REGNUM
)
825 else if (reg_nr
== MACH_C_REGNUM
826 || reg_nr
== MACL_C_REGNUM
)
829 else if (reg_nr
== PR_C_REGNUM
)
830 base_regnum
= PR_REGNUM
;
832 else if (reg_nr
== T_C_REGNUM
)
835 else if (reg_nr
== FPSCR_C_REGNUM
)
836 base_regnum
= FPSCR_REGNUM
; /*???? this register is a mess. */
838 else if (reg_nr
== FPUL_C_REGNUM
)
839 base_regnum
= gdbarch_fp0_regnum (gdbarch
) + 32;
845 sign_extend (int value
, int bits
)
847 value
= value
& ((1 << bits
) - 1);
848 return (value
& (1 << (bits
- 1))
849 ? value
| (~((1 << bits
) - 1))
854 sh64_analyze_prologue (struct gdbarch
*gdbarch
,
855 struct sh64_frame_cache
*cache
,
857 CORE_ADDR current_pc
)
864 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
866 cache
->sp_offset
= 0;
868 /* Loop around examining the prologue insns until we find something
869 that does not appear to be part of the prologue. But give up
870 after 20 of them, since we're getting silly then. */
874 if (cache
->media_mode
)
879 opc
= pc
+ (insn_size
* 28);
880 if (opc
> current_pc
)
882 for ( ; pc
<= opc
; pc
+= insn_size
)
884 insn
= read_memory_integer (cache
->media_mode
? UNMAKE_ISA32_ADDR (pc
)
886 insn_size
, byte_order
);
888 if (!cache
->media_mode
)
890 if (IS_STS_PR (insn
))
892 int next_insn
= read_memory_integer (pc
+ insn_size
,
893 insn_size
, byte_order
);
894 if (IS_MOV_TO_R15 (next_insn
))
896 cache
->saved_regs
[PR_REGNUM
]
897 = cache
->sp_offset
- ((((next_insn
& 0xf) ^ 0x8)
903 else if (IS_MOV_R14 (insn
))
905 cache
->saved_regs
[MEDIA_FP_REGNUM
] =
906 cache
->sp_offset
- ((((insn
& 0xf) ^ 0x8) - 0x8) << 2);
910 else if (IS_MOV_R0 (insn
))
912 /* Put in R0 the offset from SP at which to store some
913 registers. We are interested in this value, because it
914 will tell us where the given registers are stored within
916 r0_val
= ((insn
& 0xff) ^ 0x80) - 0x80;
919 else if (IS_ADD_SP_R0 (insn
))
921 /* This instruction still prepares r0, but we don't care.
922 We already have the offset in r0_val. */
925 else if (IS_STS_R0 (insn
))
927 /* Store PR at r0_val-4 from SP. Decrement r0 by 4. */
928 cache
->saved_regs
[PR_REGNUM
] = cache
->sp_offset
- (r0_val
- 4);
932 else if (IS_MOV_R14_R0 (insn
))
934 /* Store R14 at r0_val-4 from SP. Decrement r0 by 4. */
935 cache
->saved_regs
[MEDIA_FP_REGNUM
] = cache
->sp_offset
941 else if (IS_ADD_SP (insn
))
942 cache
->sp_offset
-= ((insn
& 0xff) ^ 0x80) - 0x80;
944 else if (IS_MOV_SP_FP (insn
))
949 if (IS_ADDIL_SP_MEDIA (insn
) || IS_ADDI_SP_MEDIA (insn
))
951 sign_extend ((((insn
& 0xffc00) ^ 0x80000) - 0x80000) >> 10, 9);
953 else if (IS_STQ_R18_R15 (insn
))
954 cache
->saved_regs
[PR_REGNUM
]
955 = cache
->sp_offset
- (sign_extend ((insn
& 0xffc00) >> 10,
958 else if (IS_STL_R18_R15 (insn
))
959 cache
->saved_regs
[PR_REGNUM
]
960 = cache
->sp_offset
- (sign_extend ((insn
& 0xffc00) >> 10,
963 else if (IS_STQ_R14_R15 (insn
))
965 cache
->saved_regs
[MEDIA_FP_REGNUM
]
966 = cache
->sp_offset
- (sign_extend ((insn
& 0xffc00) >> 10,
971 else if (IS_STL_R14_R15 (insn
))
973 cache
->saved_regs
[MEDIA_FP_REGNUM
]
974 = cache
->sp_offset
- (sign_extend ((insn
& 0xffc00) >> 10,
979 else if (IS_MOV_SP_FP_MEDIA (insn
))
986 sh64_frame_align (struct gdbarch
*ignore
, CORE_ADDR sp
)
991 /* Function: push_dummy_call
992 Setup the function arguments for calling a function in the inferior.
994 On the Renesas SH architecture, there are four registers (R4 to R7)
995 which are dedicated for passing function arguments. Up to the first
996 four arguments (depending on size) may go into these registers.
997 The rest go on the stack.
999 Arguments that are smaller than 4 bytes will still take up a whole
1000 register or a whole 32-bit word on the stack, and will be
1001 right-justified in the register or the stack word. This includes
1002 chars, shorts, and small aggregate types.
1004 Arguments that are larger than 4 bytes may be split between two or
1005 more registers. If there are not enough registers free, an argument
1006 may be passed partly in a register (or registers), and partly on the
1007 stack. This includes doubles, long longs, and larger aggregates.
1008 As far as I know, there is no upper limit to the size of aggregates
1009 that will be passed in this way; in other words, the convention of
1010 passing a pointer to a large aggregate instead of a copy is not used.
1012 An exceptional case exists for struct arguments (and possibly other
1013 aggregates such as arrays) if the size is larger than 4 bytes but
1014 not a multiple of 4 bytes. In this case the argument is never split
1015 between the registers and the stack, but instead is copied in its
1016 entirety onto the stack, AND also copied into as many registers as
1017 there is room for. In other words, space in registers permitting,
1018 two copies of the same argument are passed in. As far as I can tell,
1019 only the one on the stack is used, although that may be a function
1020 of the level of compiler optimization. I suspect this is a compiler
1021 bug. Arguments of these odd sizes are left-justified within the
1022 word (as opposed to arguments smaller than 4 bytes, which are
1025 If the function is to return an aggregate type such as a struct, it
1026 is either returned in the normal return value register R0 (if its
1027 size is no greater than one byte), or else the caller must allocate
1028 space into which the callee will copy the return value (if the size
1029 is greater than one byte). In this case, a pointer to the return
1030 value location is passed into the callee in register R2, which does
1031 not displace any of the other arguments passed in via registers R4
1034 /* R2-R9 for integer types and integer equivalent (char, pointers) and
1035 non-scalar (struct, union) elements (even if the elements are
1037 FR0-FR11 for single precision floating point (float)
1038 DR0-DR10 for double precision floating point (double)
1040 If a float is argument number 3 (for instance) and arguments number
1041 1,2, and 4 are integer, the mapping will be:
1042 arg1 -->R2, arg2 --> R3, arg3 -->FR0, arg4 --> R5. I.e. R4 is not used.
1044 If a float is argument number 10 (for instance) and arguments number
1045 1 through 10 are integer, the mapping will be:
1046 arg1->R2, arg2->R3, arg3->R4, arg4->R5, arg5->R6, arg6->R7, arg7->R8,
1047 arg8->R9, arg9->(0,SP)stack(8-byte aligned), arg10->FR0,
1048 arg11->stack(16,SP). I.e. there is hole in the stack.
1050 Different rules apply for variable arguments functions, and for functions
1051 for which the prototype is not known. */
1054 sh64_push_dummy_call (struct gdbarch
*gdbarch
,
1055 struct value
*function
,
1056 struct regcache
*regcache
,
1058 int nargs
, struct value
**args
,
1059 CORE_ADDR sp
, int struct_return
,
1060 CORE_ADDR struct_addr
)
1062 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1063 int stack_offset
, stack_alloc
;
1065 int float_arg_index
= 0;
1066 int double_arg_index
= 0;
1070 const gdb_byte
*val
;
1076 memset (fp_args
, 0, sizeof (fp_args
));
1078 /* First force sp to a 8-byte alignment. */
1079 sp
= sh64_frame_align (gdbarch
, sp
);
1081 /* The "struct return pointer" pseudo-argument has its own dedicated
1085 regcache_cooked_write_unsigned (regcache
,
1086 STRUCT_RETURN_REGNUM
, struct_addr
);
1088 /* Now make sure there's space on the stack. */
1089 for (argnum
= 0, stack_alloc
= 0; argnum
< nargs
; argnum
++)
1090 stack_alloc
+= ((TYPE_LENGTH (value_type (args
[argnum
])) + 7) & ~7);
1091 sp
-= stack_alloc
; /* Make room on stack for args. */
1093 /* Now load as many as possible of the first arguments into
1094 registers, and push the rest onto the stack. There are 64 bytes
1095 in eight registers available. Loop thru args from first to last. */
1097 int_argreg
= ARG0_REGNUM
;
1099 for (argnum
= 0, stack_offset
= 0; argnum
< nargs
; argnum
++)
1101 type
= value_type (args
[argnum
]);
1102 len
= TYPE_LENGTH (type
);
1103 memset (valbuf
, 0, sizeof (valbuf
));
1105 if (TYPE_CODE (type
) != TYPE_CODE_FLT
)
1107 argreg_size
= register_size (gdbarch
, int_argreg
);
1109 if (len
< argreg_size
)
1111 /* value gets right-justified in the register or stack word. */
1112 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1113 memcpy (valbuf
+ argreg_size
- len
,
1114 value_contents (args
[argnum
]), len
);
1116 memcpy (valbuf
, value_contents (args
[argnum
]), len
);
1121 val
= value_contents (args
[argnum
]);
1125 if (int_argreg
> ARGLAST_REGNUM
)
1127 /* Must go on the stack. */
1128 write_memory (sp
+ stack_offset
, val
, argreg_size
);
1129 stack_offset
+= 8;/*argreg_size;*/
1131 /* NOTE WELL!!!!! This is not an "else if" clause!!!
1132 That's because some *&^%$ things get passed on the stack
1133 AND in the registers! */
1134 if (int_argreg
<= ARGLAST_REGNUM
)
1136 /* There's room in a register. */
1137 regval
= extract_unsigned_integer (val
, argreg_size
,
1139 regcache_cooked_write_unsigned (regcache
,
1140 int_argreg
, regval
);
1142 /* Store the value 8 bytes at a time. This means that
1143 things larger than 8 bytes may go partly in registers
1144 and partly on the stack. FIXME: argreg is incremented
1145 before we use its size. */
1153 val
= value_contents (args
[argnum
]);
1156 /* Where is it going to be stored? */
1157 while (fp_args
[float_arg_index
])
1160 /* Now float_argreg points to the register where it
1161 should be stored. Are we still within the allowed
1163 if (float_arg_index
<= FLOAT_ARGLAST_REGNUM
)
1165 /* Goes in FR0...FR11 */
1166 regcache_cooked_write (regcache
,
1167 gdbarch_fp0_regnum (gdbarch
)
1170 fp_args
[float_arg_index
] = 1;
1171 /* Skip the corresponding general argument register. */
1176 /* Store it as the integers, 8 bytes at the time, if
1177 necessary spilling on the stack. */
1182 /* Where is it going to be stored? */
1183 while (fp_args
[double_arg_index
])
1184 double_arg_index
+= 2;
1185 /* Now double_argreg points to the register
1186 where it should be stored.
1187 Are we still within the allowed register set? */
1188 if (double_arg_index
< FLOAT_ARGLAST_REGNUM
)
1190 /* Goes in DR0...DR10 */
1191 /* The numbering of the DRi registers is consecutive,
1192 i.e. includes odd numbers. */
1193 int double_register_offset
= double_arg_index
/ 2;
1194 int regnum
= DR0_REGNUM
+ double_register_offset
;
1195 regcache_cooked_write (regcache
, regnum
, val
);
1196 fp_args
[double_arg_index
] = 1;
1197 fp_args
[double_arg_index
+ 1] = 1;
1198 /* Skip the corresponding general argument register. */
1203 /* Store it as the integers, 8 bytes at the time, if
1204 necessary spilling on the stack. */
1209 /* Store return address. */
1210 regcache_cooked_write_unsigned (regcache
, PR_REGNUM
, bp_addr
);
1212 /* Update stack pointer. */
1213 regcache_cooked_write_unsigned (regcache
,
1214 gdbarch_sp_regnum (gdbarch
), sp
);
1219 /* Find a function's return value in the appropriate registers (in
1220 regbuf), and copy it into valbuf. Extract from an array REGBUF
1221 containing the (raw) register state a function return value of type
1222 TYPE, and copy that, in virtual format, into VALBUF. */
1224 sh64_extract_return_value (struct type
*type
, struct regcache
*regcache
,
1227 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1228 int len
= TYPE_LENGTH (type
);
1230 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
1234 /* Return value stored in gdbarch_fp0_regnum. */
1235 regcache_raw_read (regcache
,
1236 gdbarch_fp0_regnum (gdbarch
), valbuf
);
1240 /* return value stored in DR0_REGNUM. */
1244 regcache_cooked_read (regcache
, DR0_REGNUM
, buf
);
1246 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
1247 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword
,
1250 floatformat_to_doublest (&floatformat_ieee_double_big
,
1252 store_typed_floating (valbuf
, type
, val
);
1261 /* Result is in register 2. If smaller than 8 bytes, it is padded
1262 at the most significant end. */
1263 regcache_raw_read (regcache
, DEFAULT_RETURN_REGNUM
, buf
);
1265 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1266 offset
= register_size (gdbarch
, DEFAULT_RETURN_REGNUM
)
1270 memcpy (valbuf
, buf
+ offset
, len
);
1273 error (_("bad size for return value"));
1277 /* Write into appropriate registers a function return value
1278 of type TYPE, given in virtual format.
1279 If the architecture is sh4 or sh3e, store a function's return value
1280 in the R0 general register or in the FP0 floating point register,
1281 depending on the type of the return value. In all the other cases
1282 the result is stored in r0, left-justified. */
1285 sh64_store_return_value (struct type
*type
, struct regcache
*regcache
,
1286 const gdb_byte
*valbuf
)
1288 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1289 gdb_byte buf
[64]; /* more than enough... */
1290 int len
= TYPE_LENGTH (type
);
1292 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
1294 int i
, regnum
= gdbarch_fp0_regnum (gdbarch
);
1295 for (i
= 0; i
< len
; i
+= 4)
1296 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
1297 regcache_raw_write (regcache
, regnum
++,
1298 valbuf
+ len
- 4 - i
);
1300 regcache_raw_write (regcache
, regnum
++, valbuf
+ i
);
1304 int return_register
= DEFAULT_RETURN_REGNUM
;
1307 if (len
<= register_size (gdbarch
, return_register
))
1309 /* Pad with zeros. */
1310 memset (buf
, 0, register_size (gdbarch
, return_register
));
1311 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
1312 offset
= 0; /*register_size (gdbarch,
1313 return_register) - len;*/
1315 offset
= register_size (gdbarch
, return_register
) - len
;
1317 memcpy (buf
+ offset
, valbuf
, len
);
1318 regcache_raw_write (regcache
, return_register
, buf
);
1321 regcache_raw_write (regcache
, return_register
, valbuf
);
1325 static enum return_value_convention
1326 sh64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
1327 struct type
*type
, struct regcache
*regcache
,
1328 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
1330 if (sh64_use_struct_convention (type
))
1331 return RETURN_VALUE_STRUCT_CONVENTION
;
1333 sh64_store_return_value (type
, regcache
, writebuf
);
1335 sh64_extract_return_value (type
, regcache
, readbuf
);
1336 return RETURN_VALUE_REGISTER_CONVENTION
;
1341 SH MEDIA MODE (ISA 32)
1342 general registers (64-bit) 0-63
1343 0 r0, r1, r2, r3, r4, r5, r6, r7,
1344 64 r8, r9, r10, r11, r12, r13, r14, r15,
1345 128 r16, r17, r18, r19, r20, r21, r22, r23,
1346 192 r24, r25, r26, r27, r28, r29, r30, r31,
1347 256 r32, r33, r34, r35, r36, r37, r38, r39,
1348 320 r40, r41, r42, r43, r44, r45, r46, r47,
1349 384 r48, r49, r50, r51, r52, r53, r54, r55,
1350 448 r56, r57, r58, r59, r60, r61, r62, r63,
1355 status reg., saved status reg., saved pc reg. (64-bit) 65-67
1358 target registers (64-bit) 68-75
1359 544 tr0, tr1, tr2, tr3, tr4, tr5, tr6, tr7,
1361 floating point state control register (32-bit) 76
1364 single precision floating point registers (32-bit) 77-140
1365 612 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7,
1366 644 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15,
1367 676 fr16, fr17, fr18, fr19, fr20, fr21, fr22, fr23,
1368 708 fr24, fr25, fr26, fr27, fr28, fr29, fr30, fr31,
1369 740 fr32, fr33, fr34, fr35, fr36, fr37, fr38, fr39,
1370 772 fr40, fr41, fr42, fr43, fr44, fr45, fr46, fr47,
1371 804 fr48, fr49, fr50, fr51, fr52, fr53, fr54, fr55,
1372 836 fr56, fr57, fr58, fr59, fr60, fr61, fr62, fr63,
1374 TOTAL SPACE FOR REGISTERS: 868 bytes
1376 From here on they are all pseudo registers: no memory allocated.
1377 REGISTER_BYTE returns the register byte for the base register.
1379 double precision registers (pseudo) 141-172
1380 dr0, dr2, dr4, dr6, dr8, dr10, dr12, dr14,
1381 dr16, dr18, dr20, dr22, dr24, dr26, dr28, dr30,
1382 dr32, dr34, dr36, dr38, dr40, dr42, dr44, dr46,
1383 dr48, dr50, dr52, dr54, dr56, dr58, dr60, dr62,
1385 floating point pairs (pseudo) 173-204
1386 fp0, fp2, fp4, fp6, fp8, fp10, fp12, fp14,
1387 fp16, fp18, fp20, fp22, fp24, fp26, fp28, fp30,
1388 fp32, fp34, fp36, fp38, fp40, fp42, fp44, fp46,
1389 fp48, fp50, fp52, fp54, fp56, fp58, fp60, fp62,
1391 floating point vectors (4 floating point regs) (pseudo) 205-220
1392 fv0, fv4, fv8, fv12, fv16, fv20, fv24, fv28,
1393 fv32, fv36, fv40, fv44, fv48, fv52, fv56, fv60,
1395 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
1396 r0_c, r1_c, r2_c, r3_c, r4_c, r5_c, r6_c, r7_c,
1397 r8_c, r9_c, r10_c, r11_c, r12_c, r13_c, r14_c, r15_c,
1399 gbr_c, mach_c, macl_c, pr_c, t_c,
1401 fr0_c, fr1_c, fr2_c, fr3_c, fr4_c, fr5_c, fr6_c, fr7_c,
1402 fr8_c, fr9_c, fr10_c, fr11_c, fr12_c, fr13_c, fr14_c, fr15_c
1403 dr0_c, dr2_c, dr4_c, dr6_c, dr8_c, dr10_c, dr12_c, dr14_c
1404 fv0_c, fv4_c, fv8_c, fv12_c
1407 static struct type
*
1408 sh64_build_float_register_type (struct gdbarch
*gdbarch
, int high
)
1410 return lookup_array_range_type (builtin_type (gdbarch
)->builtin_float
,
1414 /* Return the GDB type object for the "standard" data type
1415 of data in register REG_NR. */
1416 static struct type
*
1417 sh64_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
1419 if ((reg_nr
>= gdbarch_fp0_regnum (gdbarch
)
1420 && reg_nr
<= FP_LAST_REGNUM
)
1421 || (reg_nr
>= FP0_C_REGNUM
1422 && reg_nr
<= FP_LAST_C_REGNUM
))
1423 return builtin_type (gdbarch
)->builtin_float
;
1424 else if ((reg_nr
>= DR0_REGNUM
1425 && reg_nr
<= DR_LAST_REGNUM
)
1426 || (reg_nr
>= DR0_C_REGNUM
1427 && reg_nr
<= DR_LAST_C_REGNUM
))
1428 return builtin_type (gdbarch
)->builtin_double
;
1429 else if (reg_nr
>= FPP0_REGNUM
1430 && reg_nr
<= FPP_LAST_REGNUM
)
1431 return sh64_build_float_register_type (gdbarch
, 1);
1432 else if ((reg_nr
>= FV0_REGNUM
1433 && reg_nr
<= FV_LAST_REGNUM
)
1434 ||(reg_nr
>= FV0_C_REGNUM
1435 && reg_nr
<= FV_LAST_C_REGNUM
))
1436 return sh64_build_float_register_type (gdbarch
, 3);
1437 else if (reg_nr
== FPSCR_REGNUM
)
1438 return builtin_type (gdbarch
)->builtin_int
;
1439 else if (reg_nr
>= R0_C_REGNUM
1440 && reg_nr
< FP0_C_REGNUM
)
1441 return builtin_type (gdbarch
)->builtin_int
;
1443 return builtin_type (gdbarch
)->builtin_long_long
;
1447 sh64_register_convert_to_virtual (struct gdbarch
*gdbarch
, int regnum
,
1448 struct type
*type
, gdb_byte
*from
, gdb_byte
*to
)
1450 if (gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_LITTLE
)
1452 /* It is a no-op. */
1453 memcpy (to
, from
, register_size (gdbarch
, regnum
));
1457 if ((regnum
>= DR0_REGNUM
1458 && regnum
<= DR_LAST_REGNUM
)
1459 || (regnum
>= DR0_C_REGNUM
1460 && regnum
<= DR_LAST_C_REGNUM
))
1463 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword
,
1465 store_typed_floating (to
, type
, val
);
1468 error (_("sh64_register_convert_to_virtual "
1469 "called with non DR register number"));
1473 sh64_register_convert_to_raw (struct gdbarch
*gdbarch
, struct type
*type
,
1474 int regnum
, const void *from
, void *to
)
1476 if (gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_LITTLE
)
1478 /* It is a no-op. */
1479 memcpy (to
, from
, register_size (gdbarch
, regnum
));
1483 if ((regnum
>= DR0_REGNUM
1484 && regnum
<= DR_LAST_REGNUM
)
1485 || (regnum
>= DR0_C_REGNUM
1486 && regnum
<= DR_LAST_C_REGNUM
))
1488 DOUBLEST val
= extract_typed_floating (from
, type
);
1489 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword
,
1493 error (_("sh64_register_convert_to_raw called "
1494 "with non DR register number"));
1497 /* Concatenate PORTIONS contiguous raw registers starting at
1498 BASE_REGNUM into BUFFER. */
1500 static enum register_status
1501 pseudo_register_read_portions (struct gdbarch
*gdbarch
,
1502 struct regcache
*regcache
,
1504 int base_regnum
, gdb_byte
*buffer
)
1508 for (portion
= 0; portion
< portions
; portion
++)
1510 enum register_status status
;
1513 b
= buffer
+ register_size (gdbarch
, base_regnum
) * portion
;
1514 status
= regcache_raw_read (regcache
, base_regnum
+ portion
, b
);
1515 if (status
!= REG_VALID
)
1522 static enum register_status
1523 sh64_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1524 int reg_nr
, gdb_byte
*buffer
)
1526 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1529 gdb_byte temp_buffer
[MAX_REGISTER_SIZE
];
1530 enum register_status status
;
1532 if (reg_nr
>= DR0_REGNUM
1533 && reg_nr
<= DR_LAST_REGNUM
)
1535 base_regnum
= sh64_dr_reg_base_num (gdbarch
, reg_nr
);
1537 /* Build the value in the provided buffer. */
1538 /* DR regs are double precision registers obtained by
1539 concatenating 2 single precision floating point registers. */
1540 status
= pseudo_register_read_portions (gdbarch
, regcache
,
1541 2, base_regnum
, temp_buffer
);
1542 if (status
== REG_VALID
)
1544 /* We must pay attention to the endianness. */
1545 sh64_register_convert_to_virtual (gdbarch
, reg_nr
,
1546 register_type (gdbarch
, reg_nr
),
1547 temp_buffer
, buffer
);
1553 else if (reg_nr
>= FPP0_REGNUM
1554 && reg_nr
<= FPP_LAST_REGNUM
)
1556 base_regnum
= sh64_fpp_reg_base_num (gdbarch
, reg_nr
);
1558 /* Build the value in the provided buffer. */
1559 /* FPP regs are pairs of single precision registers obtained by
1560 concatenating 2 single precision floating point registers. */
1561 return pseudo_register_read_portions (gdbarch
, regcache
,
1562 2, base_regnum
, buffer
);
1565 else if (reg_nr
>= FV0_REGNUM
1566 && reg_nr
<= FV_LAST_REGNUM
)
1568 base_regnum
= sh64_fv_reg_base_num (gdbarch
, reg_nr
);
1570 /* Build the value in the provided buffer. */
1571 /* FV regs are vectors of single precision registers obtained by
1572 concatenating 4 single precision floating point registers. */
1573 return pseudo_register_read_portions (gdbarch
, regcache
,
1574 4, base_regnum
, buffer
);
1577 /* sh compact pseudo registers. 1-to-1 with a shmedia register. */
1578 else if (reg_nr
>= R0_C_REGNUM
1579 && reg_nr
<= T_C_REGNUM
)
1581 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1583 /* Build the value in the provided buffer. */
1584 status
= regcache_raw_read (regcache
, base_regnum
, temp_buffer
);
1585 if (status
!= REG_VALID
)
1587 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1590 temp_buffer
+ offset
, 4); /* get LOWER 32 bits only???? */
1594 else if (reg_nr
>= FP0_C_REGNUM
1595 && reg_nr
<= FP_LAST_C_REGNUM
)
1597 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1599 /* Build the value in the provided buffer. */
1600 /* Floating point registers map 1-1 to the media fp regs,
1601 they have the same size and endianness. */
1602 return regcache_raw_read (regcache
, base_regnum
, buffer
);
1605 else if (reg_nr
>= DR0_C_REGNUM
1606 && reg_nr
<= DR_LAST_C_REGNUM
)
1608 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1610 /* DR_C regs are double precision registers obtained by
1611 concatenating 2 single precision floating point registers. */
1612 status
= pseudo_register_read_portions (gdbarch
, regcache
,
1613 2, base_regnum
, temp_buffer
);
1614 if (status
== REG_VALID
)
1616 /* We must pay attention to the endianness. */
1617 sh64_register_convert_to_virtual (gdbarch
, reg_nr
,
1618 register_type (gdbarch
, reg_nr
),
1619 temp_buffer
, buffer
);
1624 else if (reg_nr
>= FV0_C_REGNUM
1625 && reg_nr
<= FV_LAST_C_REGNUM
)
1627 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1629 /* Build the value in the provided buffer. */
1630 /* FV_C regs are vectors of single precision registers obtained by
1631 concatenating 4 single precision floating point registers. */
1632 return pseudo_register_read_portions (gdbarch
, regcache
,
1633 4, base_regnum
, buffer
);
1636 else if (reg_nr
== FPSCR_C_REGNUM
)
1638 int fpscr_base_regnum
;
1640 unsigned int fpscr_value
;
1641 unsigned int sr_value
;
1642 unsigned int fpscr_c_value
;
1643 unsigned int fpscr_c_part1_value
;
1644 unsigned int fpscr_c_part2_value
;
1646 fpscr_base_regnum
= FPSCR_REGNUM
;
1647 sr_base_regnum
= SR_REGNUM
;
1649 /* Build the value in the provided buffer. */
1650 /* FPSCR_C is a very weird register that contains sparse bits
1651 from the FPSCR and the SR architectural registers.
1658 2-17 Bit 2-18 of FPSCR
1659 18-20 Bits 12,13,14 of SR
1663 /* Get FPSCR into a local buffer. */
1664 status
= regcache_raw_read (regcache
, fpscr_base_regnum
, temp_buffer
);
1665 if (status
!= REG_VALID
)
1667 /* Get value as an int. */
1668 fpscr_value
= extract_unsigned_integer (temp_buffer
, 4, byte_order
);
1669 /* Get SR into a local buffer */
1670 status
= regcache_raw_read (regcache
, sr_base_regnum
, temp_buffer
);
1671 if (status
!= REG_VALID
)
1673 /* Get value as an int. */
1674 sr_value
= extract_unsigned_integer (temp_buffer
, 4, byte_order
);
1675 /* Build the new value. */
1676 fpscr_c_part1_value
= fpscr_value
& 0x3fffd;
1677 fpscr_c_part2_value
= (sr_value
& 0x7000) << 6;
1678 fpscr_c_value
= fpscr_c_part1_value
| fpscr_c_part2_value
;
1679 /* Store that in out buffer!!! */
1680 store_unsigned_integer (buffer
, 4, byte_order
, fpscr_c_value
);
1681 /* FIXME There is surely an endianness gotcha here. */
1686 else if (reg_nr
== FPUL_C_REGNUM
)
1688 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1690 /* FPUL_C register is floating point register 32,
1691 same size, same endianness. */
1692 return regcache_raw_read (regcache
, base_regnum
, buffer
);
1695 gdb_assert_not_reached ("invalid pseudo register number");
1699 sh64_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1700 int reg_nr
, const gdb_byte
*buffer
)
1702 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1703 int base_regnum
, portion
;
1705 gdb_byte temp_buffer
[MAX_REGISTER_SIZE
];
1707 if (reg_nr
>= DR0_REGNUM
1708 && reg_nr
<= DR_LAST_REGNUM
)
1710 base_regnum
= sh64_dr_reg_base_num (gdbarch
, reg_nr
);
1711 /* We must pay attention to the endianness. */
1712 sh64_register_convert_to_raw (gdbarch
, register_type (gdbarch
, reg_nr
),
1714 buffer
, temp_buffer
);
1716 /* Write the real regs for which this one is an alias. */
1717 for (portion
= 0; portion
< 2; portion
++)
1718 regcache_raw_write (regcache
, base_regnum
+ portion
,
1720 + register_size (gdbarch
,
1721 base_regnum
) * portion
));
1724 else if (reg_nr
>= FPP0_REGNUM
1725 && reg_nr
<= FPP_LAST_REGNUM
)
1727 base_regnum
= sh64_fpp_reg_base_num (gdbarch
, reg_nr
);
1729 /* Write the real regs for which this one is an alias. */
1730 for (portion
= 0; portion
< 2; portion
++)
1731 regcache_raw_write (regcache
, base_regnum
+ portion
,
1732 (buffer
+ register_size (gdbarch
,
1733 base_regnum
) * portion
));
1736 else if (reg_nr
>= FV0_REGNUM
1737 && reg_nr
<= FV_LAST_REGNUM
)
1739 base_regnum
= sh64_fv_reg_base_num (gdbarch
, reg_nr
);
1741 /* Write the real regs for which this one is an alias. */
1742 for (portion
= 0; portion
< 4; portion
++)
1743 regcache_raw_write (regcache
, base_regnum
+ portion
,
1744 (buffer
+ register_size (gdbarch
,
1745 base_regnum
) * portion
));
1748 /* sh compact general pseudo registers. 1-to-1 with a shmedia
1749 register but only 4 bytes of it. */
1750 else if (reg_nr
>= R0_C_REGNUM
1751 && reg_nr
<= T_C_REGNUM
)
1753 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1754 /* reg_nr is 32 bit here, and base_regnum is 64 bits. */
1755 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1759 /* Let's read the value of the base register into a temporary
1760 buffer, so that overwriting the last four bytes with the new
1761 value of the pseudo will leave the upper 4 bytes unchanged. */
1762 regcache_raw_read (regcache
, base_regnum
, temp_buffer
);
1763 /* Write as an 8 byte quantity. */
1764 memcpy (temp_buffer
+ offset
, buffer
, 4);
1765 regcache_raw_write (regcache
, base_regnum
, temp_buffer
);
1768 /* sh floating point compact pseudo registers. 1-to-1 with a shmedia
1769 registers. Both are 4 bytes. */
1770 else if (reg_nr
>= FP0_C_REGNUM
1771 && reg_nr
<= FP_LAST_C_REGNUM
)
1773 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1774 regcache_raw_write (regcache
, base_regnum
, buffer
);
1777 else if (reg_nr
>= DR0_C_REGNUM
1778 && reg_nr
<= DR_LAST_C_REGNUM
)
1780 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1781 for (portion
= 0; portion
< 2; portion
++)
1783 /* We must pay attention to the endianness. */
1784 sh64_register_convert_to_raw (gdbarch
,
1785 register_type (gdbarch
, reg_nr
),
1787 buffer
, temp_buffer
);
1789 regcache_raw_write (regcache
, base_regnum
+ portion
,
1791 + register_size (gdbarch
,
1792 base_regnum
) * portion
));
1796 else if (reg_nr
>= FV0_C_REGNUM
1797 && reg_nr
<= FV_LAST_C_REGNUM
)
1799 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1801 for (portion
= 0; portion
< 4; portion
++)
1803 regcache_raw_write (regcache
, base_regnum
+ portion
,
1805 + register_size (gdbarch
,
1806 base_regnum
) * portion
));
1810 else if (reg_nr
== FPSCR_C_REGNUM
)
1812 int fpscr_base_regnum
;
1814 unsigned int fpscr_value
;
1815 unsigned int sr_value
;
1816 unsigned int old_fpscr_value
;
1817 unsigned int old_sr_value
;
1818 unsigned int fpscr_c_value
;
1819 unsigned int fpscr_mask
;
1820 unsigned int sr_mask
;
1822 fpscr_base_regnum
= FPSCR_REGNUM
;
1823 sr_base_regnum
= SR_REGNUM
;
1825 /* FPSCR_C is a very weird register that contains sparse bits
1826 from the FPSCR and the SR architectural registers.
1833 2-17 Bit 2-18 of FPSCR
1834 18-20 Bits 12,13,14 of SR
1838 /* Get value as an int. */
1839 fpscr_c_value
= extract_unsigned_integer (buffer
, 4, byte_order
);
1841 /* Build the new values. */
1842 fpscr_mask
= 0x0003fffd;
1843 sr_mask
= 0x001c0000;
1845 fpscr_value
= fpscr_c_value
& fpscr_mask
;
1846 sr_value
= (fpscr_value
& sr_mask
) >> 6;
1848 regcache_raw_read (regcache
, fpscr_base_regnum
, temp_buffer
);
1849 old_fpscr_value
= extract_unsigned_integer (temp_buffer
, 4, byte_order
);
1850 old_fpscr_value
&= 0xfffc0002;
1851 fpscr_value
|= old_fpscr_value
;
1852 store_unsigned_integer (temp_buffer
, 4, byte_order
, fpscr_value
);
1853 regcache_raw_write (regcache
, fpscr_base_regnum
, temp_buffer
);
1855 regcache_raw_read (regcache
, sr_base_regnum
, temp_buffer
);
1856 old_sr_value
= extract_unsigned_integer (temp_buffer
, 4, byte_order
);
1857 old_sr_value
&= 0xffff8fff;
1858 sr_value
|= old_sr_value
;
1859 store_unsigned_integer (temp_buffer
, 4, byte_order
, sr_value
);
1860 regcache_raw_write (regcache
, sr_base_regnum
, temp_buffer
);
1863 else if (reg_nr
== FPUL_C_REGNUM
)
1865 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1866 regcache_raw_write (regcache
, base_regnum
, buffer
);
1870 /* FIXME:!! THIS SHOULD TAKE CARE OF GETTING THE RIGHT PORTION OF THE
1871 shmedia REGISTERS. */
1872 /* Control registers, compact mode. */
1874 sh64_do_cr_c_register_info (struct ui_file
*file
, struct frame_info
*frame
,
1877 switch (cr_c_regnum
)
1880 fprintf_filtered (file
, "pc_c\t0x%08x\n",
1881 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
1884 fprintf_filtered (file
, "gbr_c\t0x%08x\n",
1885 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
1888 fprintf_filtered (file
, "mach_c\t0x%08x\n",
1889 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
1892 fprintf_filtered (file
, "macl_c\t0x%08x\n",
1893 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
1896 fprintf_filtered (file
, "pr_c\t0x%08x\n",
1897 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
1900 fprintf_filtered (file
, "t_c\t0x%08x\n",
1901 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
1903 case FPSCR_C_REGNUM
:
1904 fprintf_filtered (file
, "fpscr_c\t0x%08x\n",
1905 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
1908 fprintf_filtered (file
, "fpul_c\t0x%08x\n",
1909 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
1915 sh64_do_fp_register (struct gdbarch
*gdbarch
, struct ui_file
*file
,
1916 struct frame_info
*frame
, int regnum
)
1917 { /* Do values for FP (float) regs. */
1918 unsigned char *raw_buffer
;
1919 double flt
; /* Double extracted from raw hex data. */
1922 /* Allocate space for the float. */
1923 raw_buffer
= (unsigned char *)
1924 alloca (register_size (gdbarch
, gdbarch_fp0_regnum (gdbarch
)));
1926 /* Get the data in raw format. */
1927 if (!deprecated_frame_register_read (frame
, regnum
, raw_buffer
))
1928 error (_("can't read register %d (%s)"),
1929 regnum
, gdbarch_register_name (gdbarch
, regnum
));
1931 /* Get the register as a number. */
1932 flt
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
1935 /* Print the name and some spaces. */
1936 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
1937 print_spaces_filtered (15 - strlen (gdbarch_register_name
1938 (gdbarch
, regnum
)), file
);
1940 /* Print the value. */
1942 fprintf_filtered (file
, "<invalid float>");
1944 fprintf_filtered (file
, "%-10.9g", flt
);
1946 /* Print the fp register as hex. */
1947 fprintf_filtered (file
, "\t(raw ");
1948 print_hex_chars (file
, raw_buffer
,
1949 register_size (gdbarch
, regnum
),
1950 gdbarch_byte_order (gdbarch
));
1951 fprintf_filtered (file
, ")");
1952 fprintf_filtered (file
, "\n");
1956 sh64_do_pseudo_register (struct gdbarch
*gdbarch
, struct ui_file
*file
,
1957 struct frame_info
*frame
, int regnum
)
1959 /* All the sh64-compact mode registers are pseudo registers. */
1961 if (regnum
< gdbarch_num_regs (gdbarch
)
1962 || regnum
>= gdbarch_num_regs (gdbarch
)
1963 + NUM_PSEUDO_REGS_SH_MEDIA
1964 + NUM_PSEUDO_REGS_SH_COMPACT
)
1965 internal_error (__FILE__
, __LINE__
,
1966 _("Invalid pseudo register number %d\n"), regnum
);
1968 else if ((regnum
>= DR0_REGNUM
&& regnum
<= DR_LAST_REGNUM
))
1970 int fp_regnum
= sh64_dr_reg_base_num (gdbarch
, regnum
);
1971 fprintf_filtered (file
, "dr%d\t0x%08x%08x\n", regnum
- DR0_REGNUM
,
1972 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
),
1973 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 1));
1976 else if ((regnum
>= DR0_C_REGNUM
&& regnum
<= DR_LAST_C_REGNUM
))
1978 int fp_regnum
= sh64_compact_reg_base_num (gdbarch
, regnum
);
1979 fprintf_filtered (file
, "dr%d_c\t0x%08x%08x\n", regnum
- DR0_C_REGNUM
,
1980 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
),
1981 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 1));
1984 else if ((regnum
>= FV0_REGNUM
&& regnum
<= FV_LAST_REGNUM
))
1986 int fp_regnum
= sh64_fv_reg_base_num (gdbarch
, regnum
);
1987 fprintf_filtered (file
, "fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
1988 regnum
- FV0_REGNUM
,
1989 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
),
1990 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 1),
1991 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 2),
1992 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 3));
1995 else if ((regnum
>= FV0_C_REGNUM
&& regnum
<= FV_LAST_C_REGNUM
))
1997 int fp_regnum
= sh64_compact_reg_base_num (gdbarch
, regnum
);
1998 fprintf_filtered (file
, "fv%d_c\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
1999 regnum
- FV0_C_REGNUM
,
2000 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
),
2001 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 1),
2002 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 2),
2003 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 3));
2006 else if (regnum
>= FPP0_REGNUM
&& regnum
<= FPP_LAST_REGNUM
)
2008 int fp_regnum
= sh64_fpp_reg_base_num (gdbarch
, regnum
);
2009 fprintf_filtered (file
, "fpp%d\t0x%08x\t0x%08x\n", regnum
- FPP0_REGNUM
,
2010 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
),
2011 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 1));
2014 else if (regnum
>= R0_C_REGNUM
&& regnum
<= R_LAST_C_REGNUM
)
2016 int c_regnum
= sh64_compact_reg_base_num (gdbarch
, regnum
);
2017 fprintf_filtered (file
, "r%d_c\t0x%08x\n", regnum
- R0_C_REGNUM
,
2018 (unsigned) get_frame_register_unsigned (frame
, c_regnum
));
2020 else if (regnum
>= FP0_C_REGNUM
&& regnum
<= FP_LAST_C_REGNUM
)
2021 /* This should work also for pseudoregs. */
2022 sh64_do_fp_register (gdbarch
, file
, frame
, regnum
);
2023 else if (regnum
>= PC_C_REGNUM
&& regnum
<= FPUL_C_REGNUM
)
2024 sh64_do_cr_c_register_info (file
, frame
, regnum
);
2028 sh64_do_register (struct gdbarch
*gdbarch
, struct ui_file
*file
,
2029 struct frame_info
*frame
, int regnum
)
2031 unsigned char raw_buffer
[MAX_REGISTER_SIZE
];
2032 struct value_print_options opts
;
2034 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
2035 print_spaces_filtered (15 - strlen (gdbarch_register_name
2036 (gdbarch
, regnum
)), file
);
2038 /* Get the data in raw format. */
2039 if (!deprecated_frame_register_read (frame
, regnum
, raw_buffer
))
2041 fprintf_filtered (file
, "*value not available*\n");
2045 get_formatted_print_options (&opts
, 'x');
2047 val_print (register_type (gdbarch
, regnum
), raw_buffer
, 0, 0,
2048 file
, 0, NULL
, &opts
, current_language
);
2049 fprintf_filtered (file
, "\t");
2050 get_formatted_print_options (&opts
, 0);
2052 val_print (register_type (gdbarch
, regnum
), raw_buffer
, 0, 0,
2053 file
, 0, NULL
, &opts
, current_language
);
2054 fprintf_filtered (file
, "\n");
2058 sh64_print_register (struct gdbarch
*gdbarch
, struct ui_file
*file
,
2059 struct frame_info
*frame
, int regnum
)
2061 if (regnum
< 0 || regnum
>= gdbarch_num_regs (gdbarch
)
2062 + gdbarch_num_pseudo_regs (gdbarch
))
2063 internal_error (__FILE__
, __LINE__
,
2064 _("Invalid register number %d\n"), regnum
);
2066 else if (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
))
2068 if (TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
2069 sh64_do_fp_register (gdbarch
, file
, frame
, regnum
); /* FP regs */
2071 sh64_do_register (gdbarch
, file
, frame
, regnum
);
2074 else if (regnum
< gdbarch_num_regs (gdbarch
)
2075 + gdbarch_num_pseudo_regs (gdbarch
))
2076 sh64_do_pseudo_register (gdbarch
, file
, frame
, regnum
);
2080 sh64_media_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
2081 struct frame_info
*frame
, int regnum
,
2084 if (regnum
!= -1) /* Do one specified register. */
2086 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
2087 error (_("Not a valid register for the current processor type"));
2089 sh64_print_register (gdbarch
, file
, frame
, regnum
);
2092 /* Do all (or most) registers. */
2095 while (regnum
< gdbarch_num_regs (gdbarch
))
2097 /* If the register name is empty, it is undefined for this
2098 processor, so don't display anything. */
2099 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
2100 || *(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
2106 if (TYPE_CODE (register_type (gdbarch
, regnum
))
2111 /* true for "INFO ALL-REGISTERS" command. */
2112 sh64_do_fp_register (gdbarch
, file
, frame
, regnum
);
2116 regnum
+= FP_LAST_REGNUM
- gdbarch_fp0_regnum (gdbarch
);
2121 sh64_do_register (gdbarch
, file
, frame
, regnum
);
2127 while (regnum
< gdbarch_num_regs (gdbarch
)
2128 + gdbarch_num_pseudo_regs (gdbarch
))
2130 sh64_do_pseudo_register (gdbarch
, file
, frame
, regnum
);
2137 sh64_compact_print_registers_info (struct gdbarch
*gdbarch
,
2138 struct ui_file
*file
,
2139 struct frame_info
*frame
, int regnum
,
2142 if (regnum
!= -1) /* Do one specified register. */
2144 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
2145 error (_("Not a valid register for the current processor type"));
2147 if (regnum
>= 0 && regnum
< R0_C_REGNUM
)
2148 error (_("Not a valid register for the current processor mode."));
2150 sh64_print_register (gdbarch
, file
, frame
, regnum
);
2153 /* Do all compact registers. */
2155 regnum
= R0_C_REGNUM
;
2156 while (regnum
< gdbarch_num_regs (gdbarch
)
2157 + gdbarch_num_pseudo_regs (gdbarch
))
2159 sh64_do_pseudo_register (gdbarch
, file
, frame
, regnum
);
2166 sh64_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
2167 struct frame_info
*frame
, int regnum
, int fpregs
)
2169 if (pc_is_isa32 (get_frame_pc (frame
)))
2170 sh64_media_print_registers_info (gdbarch
, file
, frame
, regnum
, fpregs
);
2172 sh64_compact_print_registers_info (gdbarch
, file
, frame
, regnum
, fpregs
);
2175 static struct sh64_frame_cache
*
2176 sh64_alloc_frame_cache (void)
2178 struct sh64_frame_cache
*cache
;
2181 cache
= FRAME_OBSTACK_ZALLOC (struct sh64_frame_cache
);
2185 cache
->saved_sp
= 0;
2186 cache
->sp_offset
= 0;
2189 /* Frameless until proven otherwise. */
2192 /* Saved registers. We initialize these to -1 since zero is a valid
2193 offset (that's where fp is supposed to be stored). */
2194 for (i
= 0; i
< SIM_SH64_NR_REGS
; i
++)
2196 cache
->saved_regs
[i
] = -1;
2202 static struct sh64_frame_cache
*
2203 sh64_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2205 struct gdbarch
*gdbarch
;
2206 struct sh64_frame_cache
*cache
;
2207 CORE_ADDR current_pc
;
2211 return (struct sh64_frame_cache
*) *this_cache
;
2213 gdbarch
= get_frame_arch (this_frame
);
2214 cache
= sh64_alloc_frame_cache ();
2215 *this_cache
= cache
;
2217 current_pc
= get_frame_pc (this_frame
);
2218 cache
->media_mode
= pc_is_isa32 (current_pc
);
2220 /* In principle, for normal frames, fp holds the frame pointer,
2221 which holds the base address for the current stack frame.
2222 However, for functions that don't need it, the frame pointer is
2223 optional. For these "frameless" functions the frame pointer is
2224 actually the frame pointer of the calling frame. */
2225 cache
->base
= get_frame_register_unsigned (this_frame
, MEDIA_FP_REGNUM
);
2226 if (cache
->base
== 0)
2229 cache
->pc
= get_frame_func (this_frame
);
2231 sh64_analyze_prologue (gdbarch
, cache
, cache
->pc
, current_pc
);
2233 if (!cache
->uses_fp
)
2235 /* We didn't find a valid frame, which means that CACHE->base
2236 currently holds the frame pointer for our calling frame. If
2237 we're at the start of a function, or somewhere half-way its
2238 prologue, the function's frame probably hasn't been fully
2239 setup yet. Try to reconstruct the base address for the stack
2240 frame by looking at the stack pointer. For truly "frameless"
2241 functions this might work too. */
2242 cache
->base
= get_frame_register_unsigned
2243 (this_frame
, gdbarch_sp_regnum (gdbarch
));
2246 /* Now that we have the base address for the stack frame we can
2247 calculate the value of sp in the calling frame. */
2248 cache
->saved_sp
= cache
->base
+ cache
->sp_offset
;
2250 /* Adjust all the saved registers such that they contain addresses
2251 instead of offsets. */
2252 for (i
= 0; i
< SIM_SH64_NR_REGS
; i
++)
2253 if (cache
->saved_regs
[i
] != -1)
2254 cache
->saved_regs
[i
] = cache
->saved_sp
- cache
->saved_regs
[i
];
2259 static struct value
*
2260 sh64_frame_prev_register (struct frame_info
*this_frame
,
2261 void **this_cache
, int regnum
)
2263 struct sh64_frame_cache
*cache
= sh64_frame_cache (this_frame
, this_cache
);
2264 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2265 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2267 gdb_assert (regnum
>= 0);
2269 if (regnum
== gdbarch_sp_regnum (gdbarch
) && cache
->saved_sp
)
2270 frame_unwind_got_constant (this_frame
, regnum
, cache
->saved_sp
);
2272 /* The PC of the previous frame is stored in the PR register of
2273 the current frame. Frob regnum so that we pull the value from
2274 the correct place. */
2275 if (regnum
== gdbarch_pc_regnum (gdbarch
))
2278 if (regnum
< SIM_SH64_NR_REGS
&& cache
->saved_regs
[regnum
] != -1)
2280 if (gdbarch_tdep (gdbarch
)->sh_abi
== SH_ABI_32
2281 && (regnum
== MEDIA_FP_REGNUM
|| regnum
== PR_REGNUM
))
2284 val
= read_memory_unsigned_integer (cache
->saved_regs
[regnum
],
2286 return frame_unwind_got_constant (this_frame
, regnum
, val
);
2289 return frame_unwind_got_memory (this_frame
, regnum
,
2290 cache
->saved_regs
[regnum
]);
2293 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
2297 sh64_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2298 struct frame_id
*this_id
)
2300 struct sh64_frame_cache
*cache
= sh64_frame_cache (this_frame
, this_cache
);
2302 /* This marks the outermost frame. */
2303 if (cache
->base
== 0)
2306 *this_id
= frame_id_build (cache
->saved_sp
, cache
->pc
);
2309 static const struct frame_unwind sh64_frame_unwind
= {
2311 default_frame_unwind_stop_reason
,
2313 sh64_frame_prev_register
,
2315 default_frame_sniffer
2319 sh64_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2321 return frame_unwind_register_unsigned (next_frame
,
2322 gdbarch_sp_regnum (gdbarch
));
2326 sh64_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2328 return frame_unwind_register_unsigned (next_frame
,
2329 gdbarch_pc_regnum (gdbarch
));
2332 static struct frame_id
2333 sh64_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2335 CORE_ADDR sp
= get_frame_register_unsigned (this_frame
,
2336 gdbarch_sp_regnum (gdbarch
));
2337 return frame_id_build (sp
, get_frame_pc (this_frame
));
2341 sh64_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
2343 struct sh64_frame_cache
*cache
= sh64_frame_cache (this_frame
, this_cache
);
2348 static const struct frame_base sh64_frame_base
= {
2350 sh64_frame_base_address
,
2351 sh64_frame_base_address
,
2352 sh64_frame_base_address
2357 sh64_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2359 struct gdbarch
*gdbarch
;
2360 struct gdbarch_tdep
*tdep
;
2362 /* If there is already a candidate, use it. */
2363 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
2365 return arches
->gdbarch
;
2367 /* None found, create a new architecture from the information
2369 tdep
= XNEW (struct gdbarch_tdep
);
2370 gdbarch
= gdbarch_alloc (&info
, tdep
);
2372 /* Determine the ABI */
2373 if (info
.abfd
&& bfd_get_arch_size (info
.abfd
) == 64)
2375 /* If the ABI is the 64-bit one, it can only be sh-media. */
2376 tdep
->sh_abi
= SH_ABI_64
;
2377 set_gdbarch_ptr_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2378 set_gdbarch_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2382 /* If the ABI is the 32-bit one it could be either media or
2384 tdep
->sh_abi
= SH_ABI_32
;
2385 set_gdbarch_ptr_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2386 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2389 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
2390 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2391 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2392 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2393 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2394 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2395 set_gdbarch_long_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2397 /* The number of real registers is the same whether we are in
2398 ISA16(compact) or ISA32(media). */
2399 set_gdbarch_num_regs (gdbarch
, SIM_SH64_NR_REGS
);
2400 set_gdbarch_sp_regnum (gdbarch
, 15);
2401 set_gdbarch_pc_regnum (gdbarch
, 64);
2402 set_gdbarch_fp0_regnum (gdbarch
, SIM_SH64_FR0_REGNUM
);
2403 set_gdbarch_num_pseudo_regs (gdbarch
, NUM_PSEUDO_REGS_SH_MEDIA
2404 + NUM_PSEUDO_REGS_SH_COMPACT
);
2406 set_gdbarch_register_name (gdbarch
, sh64_register_name
);
2407 set_gdbarch_register_type (gdbarch
, sh64_register_type
);
2409 set_gdbarch_pseudo_register_read (gdbarch
, sh64_pseudo_register_read
);
2410 set_gdbarch_pseudo_register_write (gdbarch
, sh64_pseudo_register_write
);
2412 set_gdbarch_breakpoint_from_pc (gdbarch
, sh64_breakpoint_from_pc
);
2414 set_gdbarch_print_insn (gdbarch
, print_insn_sh
);
2415 set_gdbarch_register_sim_regno (gdbarch
, legacy_register_sim_regno
);
2417 set_gdbarch_return_value (gdbarch
, sh64_return_value
);
2419 set_gdbarch_skip_prologue (gdbarch
, sh64_skip_prologue
);
2420 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2422 set_gdbarch_push_dummy_call (gdbarch
, sh64_push_dummy_call
);
2424 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
2426 set_gdbarch_frame_align (gdbarch
, sh64_frame_align
);
2427 set_gdbarch_unwind_sp (gdbarch
, sh64_unwind_sp
);
2428 set_gdbarch_unwind_pc (gdbarch
, sh64_unwind_pc
);
2429 set_gdbarch_dummy_id (gdbarch
, sh64_dummy_id
);
2430 frame_base_set_default (gdbarch
, &sh64_frame_base
);
2432 set_gdbarch_print_registers_info (gdbarch
, sh64_print_registers_info
);
2434 set_gdbarch_elf_make_msymbol_special (gdbarch
,
2435 sh64_elf_make_msymbol_special
);
2437 /* Hook in ABI-specific overrides, if they have been registered. */
2438 gdbarch_init_osabi (info
, gdbarch
);
2440 dwarf2_append_unwinders (gdbarch
);
2441 frame_unwind_append_unwinder (gdbarch
, &sh64_frame_unwind
);