1 /* Target-dependent code for SPARC.
3 Copyright (C) 2003-2021 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "arch-utils.h"
24 #include "dwarf2/frame.h"
26 #include "frame-base.h"
27 #include "frame-unwind.h"
36 #include "target-descriptions.h"
39 #include "sparc-tdep.h"
40 #include "sparc-ravenscar-thread.h"
45 /* This file implements the SPARC 32-bit ABI as defined by the section
46 "Low-Level System Information" of the SPARC Compliance Definition
47 (SCD) 2.4.1, which is the 32-bit System V psABI for SPARC. The SCD
48 lists changes with respect to the original 32-bit psABI as defined
49 in the "System V ABI, SPARC Processor Supplement".
51 Note that if we talk about SunOS, we mean SunOS 4.x, which was
52 BSD-based, which is sometimes (retroactively?) referred to as
53 Solaris 1.x. If we talk about Solaris we mean Solaris 2.x and
54 above (Solaris 7, 8 and 9 are nothing but Solaris 2.7, 2.8 and 2.9
55 suffering from severe version number inflation). Solaris 2.x is
56 also known as SunOS 5.x, since that's what uname(1) says. Solaris
59 /* Please use the sparc32_-prefix for 32-bit specific code, the
60 sparc64_-prefix for 64-bit specific code and the sparc_-prefix for
61 code that can handle both. The 64-bit specific code lives in
62 sparc64-tdep.c; don't add any here. */
64 /* The SPARC Floating-Point Quad-Precision format is similar to
65 big-endian IA-64 Quad-Precision format. */
66 #define floatformats_sparc_quad floatformats_ia64_quad
68 /* The stack pointer is offset from the stack frame by a BIAS of 2047
69 (0x7ff) for 64-bit code. BIAS is likely to be defined on SPARC
70 hosts, so undefine it first. */
74 /* Macros to extract fields from SPARC instructions. */
75 #define X_OP(i) (((i) >> 30) & 0x3)
76 #define X_RD(i) (((i) >> 25) & 0x1f)
77 #define X_A(i) (((i) >> 29) & 1)
78 #define X_COND(i) (((i) >> 25) & 0xf)
79 #define X_OP2(i) (((i) >> 22) & 0x7)
80 #define X_IMM22(i) ((i) & 0x3fffff)
81 #define X_OP3(i) (((i) >> 19) & 0x3f)
82 #define X_RS1(i) (((i) >> 14) & 0x1f)
83 #define X_RS2(i) ((i) & 0x1f)
84 #define X_I(i) (((i) >> 13) & 1)
85 /* Sign extension macros. */
86 #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000)
87 #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000)
88 #define X_DISP10(i) ((((((i) >> 11) && 0x300) | (((i) >> 5) & 0xff)) ^ 0x200) - 0x200)
89 #define X_SIMM13(i) ((((i) & 0x1fff) ^ 0x1000) - 0x1000)
90 /* Macros to identify some instructions. */
91 /* RETURN (RETT in V8) */
92 #define X_RETTURN(i) ((X_OP (i) == 0x2) && (X_OP3 (i) == 0x39))
94 /* Fetch the instruction at PC. Instructions are always big-endian
95 even if the processor operates in little-endian mode. */
98 sparc_fetch_instruction (CORE_ADDR pc
)
104 /* If we can't read the instruction at PC, return zero. */
105 if (target_read_memory (pc
, buf
, sizeof (buf
)))
109 for (i
= 0; i
< sizeof (buf
); i
++)
110 insn
= (insn
<< 8) | buf
[i
];
115 /* Return non-zero if the instruction corresponding to PC is an "unimp"
119 sparc_is_unimp_insn (CORE_ADDR pc
)
121 const unsigned long insn
= sparc_fetch_instruction (pc
);
123 return ((insn
& 0xc1c00000) == 0);
126 /* Return non-zero if the instruction corresponding to PC is an
127 "annulled" branch, i.e. the annul bit is set. */
130 sparc_is_annulled_branch_insn (CORE_ADDR pc
)
132 /* The branch instructions featuring an annul bit can be identified
133 by the following bit patterns:
136 OP2=1: Branch on Integer Condition Codes with Prediction (BPcc).
137 OP2=2: Branch on Integer Condition Codes (Bcc).
138 OP2=5: Branch on FP Condition Codes with Prediction (FBfcc).
139 OP2=6: Branch on FP Condition Codes (FBcc).
141 Branch on Integer Register with Prediction (BPr).
143 This leaves out ILLTRAP (OP2=0), SETHI/NOP (OP2=4) and the V8
144 coprocessor branch instructions (Op2=7). */
146 const unsigned long insn
= sparc_fetch_instruction (pc
);
147 const unsigned op2
= X_OP2 (insn
);
149 if ((X_OP (insn
) == 0)
150 && ((op2
== 1) || (op2
== 2) || (op2
== 5) || (op2
== 6)
151 || ((op2
== 3) && ((insn
& 0x10000000) == 0))))
157 /* OpenBSD/sparc includes StackGhost, which according to the author's
158 website http://stackghost.cerias.purdue.edu "... transparently and
159 automatically protects applications' stack frames; more
160 specifically, it guards the return pointers. The protection
161 mechanisms require no application source or binary modification and
162 imposes only a negligible performance penalty."
164 The same website provides the following description of how
167 "StackGhost interfaces with the kernel trap handler that would
168 normally write out registers to the stack and the handler that
169 would read them back in. By XORing a cookie into the
170 return-address saved in the user stack when it is actually written
171 to the stack, and then XOR it out when the return-address is pulled
172 from the stack, StackGhost can cause attacker corrupted return
173 pointers to behave in a manner the attacker cannot predict.
174 StackGhost can also use several unused bits in the return pointer
175 to detect a smashed return pointer and abort the process."
177 For GDB this means that whenever we're reading %i7 from a stack
178 frame's window save area, we'll have to XOR the cookie.
180 More information on StackGuard can be found on in:
182 Mike Frantzen and Mike Shuey. "StackGhost: Hardware Facilitated
183 Stack Protection." 2001. Published in USENIX Security Symposium
186 /* Fetch StackGhost Per-Process XOR cookie. */
189 sparc_fetch_wcookie (struct gdbarch
*gdbarch
)
191 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
192 struct target_ops
*ops
= current_inferior ()->top_target ();
196 len
= target_read (ops
, TARGET_OBJECT_WCOOKIE
, NULL
, buf
, 0, 8);
200 /* We should have either an 32-bit or an 64-bit cookie. */
201 gdb_assert (len
== 4 || len
== 8);
203 return extract_unsigned_integer (buf
, len
, byte_order
);
207 /* The functions on this page are intended to be used to classify
208 function arguments. */
210 /* Check whether TYPE is "Integral or Pointer". */
213 sparc_integral_or_pointer_p (const struct type
*type
)
215 int len
= TYPE_LENGTH (type
);
217 switch (type
->code ())
223 case TYPE_CODE_RANGE
:
224 /* We have byte, half-word, word and extended-word/doubleword
225 integral types. The doubleword is an extension to the
226 original 32-bit ABI by the SCD 2.4.x. */
227 return (len
== 1 || len
== 2 || len
== 4 || len
== 8);
230 case TYPE_CODE_RVALUE_REF
:
231 /* Allow either 32-bit or 64-bit pointers. */
232 return (len
== 4 || len
== 8);
240 /* Check whether TYPE is "Floating". */
243 sparc_floating_p (const struct type
*type
)
245 switch (type
->code ())
249 int len
= TYPE_LENGTH (type
);
250 return (len
== 4 || len
== 8 || len
== 16);
259 /* Check whether TYPE is "Complex Floating". */
262 sparc_complex_floating_p (const struct type
*type
)
264 switch (type
->code ())
266 case TYPE_CODE_COMPLEX
:
268 int len
= TYPE_LENGTH (type
);
269 return (len
== 8 || len
== 16 || len
== 32);
278 /* Check whether TYPE is "Structure or Union".
280 In terms of Ada subprogram calls, arrays are treated the same as
281 struct and union types. So this function also returns non-zero
285 sparc_structure_or_union_p (const struct type
*type
)
287 switch (type
->code ())
289 case TYPE_CODE_STRUCT
:
290 case TYPE_CODE_UNION
:
291 case TYPE_CODE_ARRAY
:
300 /* Return true if TYPE is returned by memory, false if returned by
304 sparc_structure_return_p (const struct type
*type
)
306 if (type
->code () == TYPE_CODE_ARRAY
&& type
->is_vector ())
308 /* Float vectors are always returned by memory. */
309 if (sparc_floating_p (check_typedef (TYPE_TARGET_TYPE (type
))))
311 /* Integer vectors are returned by memory if the vector size
312 is greater than 8 bytes long. */
313 return (TYPE_LENGTH (type
) > 8);
316 if (sparc_floating_p (type
))
318 /* Floating point types are passed by register for size 4 and
319 8 bytes, and by memory for size 16 bytes. */
320 return (TYPE_LENGTH (type
) == 16);
323 /* Other than that, only aggregates of all sizes get returned by
325 return sparc_structure_or_union_p (type
);
328 /* Return true if arguments of the given TYPE are passed by
329 memory; false if returned by register. */
332 sparc_arg_by_memory_p (const struct type
*type
)
334 if (type
->code () == TYPE_CODE_ARRAY
&& type
->is_vector ())
336 /* Float vectors are always passed by memory. */
337 if (sparc_floating_p (check_typedef (TYPE_TARGET_TYPE (type
))))
339 /* Integer vectors are passed by memory if the vector size
340 is greater than 8 bytes long. */
341 return (TYPE_LENGTH (type
) > 8);
344 /* Floats are passed by register for size 4 and 8 bytes, and by memory
345 for size 16 bytes. */
346 if (sparc_floating_p (type
))
347 return (TYPE_LENGTH (type
) == 16);
349 /* Complex floats and aggregates of all sizes are passed by memory. */
350 if (sparc_complex_floating_p (type
) || sparc_structure_or_union_p (type
))
353 /* Everything else gets passed by register. */
357 /* Register information. */
358 #define SPARC32_FPU_REGISTERS \
359 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
360 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \
361 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", \
362 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
363 #define SPARC32_CP0_REGISTERS \
364 "y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr"
366 static const char * const sparc_core_register_names
[] = {
369 static const char * const sparc32_fpu_register_names
[] = {
370 SPARC32_FPU_REGISTERS
372 static const char * const sparc32_cp0_register_names
[] = {
373 SPARC32_CP0_REGISTERS
376 static const char * const sparc32_register_names
[] =
378 SPARC_CORE_REGISTERS
,
379 SPARC32_FPU_REGISTERS
,
380 SPARC32_CP0_REGISTERS
383 /* Total number of registers. */
384 #define SPARC32_NUM_REGS ARRAY_SIZE (sparc32_register_names)
386 /* We provide the aliases %d0..%d30 for the floating registers as
387 "psuedo" registers. */
389 static const char * const sparc32_pseudo_register_names
[] =
391 "d0", "d2", "d4", "d6", "d8", "d10", "d12", "d14",
392 "d16", "d18", "d20", "d22", "d24", "d26", "d28", "d30"
395 /* Total number of pseudo registers. */
396 #define SPARC32_NUM_PSEUDO_REGS ARRAY_SIZE (sparc32_pseudo_register_names)
398 /* Return the name of pseudo register REGNUM. */
401 sparc32_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
403 regnum
-= gdbarch_num_regs (gdbarch
);
405 if (regnum
< SPARC32_NUM_PSEUDO_REGS
)
406 return sparc32_pseudo_register_names
[regnum
];
408 internal_error (__FILE__
, __LINE__
,
409 _("sparc32_pseudo_register_name: bad register number %d"),
413 /* Return the name of register REGNUM. */
416 sparc32_register_name (struct gdbarch
*gdbarch
, int regnum
)
418 if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
419 return tdesc_register_name (gdbarch
, regnum
);
421 if (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
))
422 return sparc32_register_names
[regnum
];
424 return sparc32_pseudo_register_name (gdbarch
, regnum
);
427 /* Construct types for ISA-specific registers. */
430 sparc_psr_type (struct gdbarch
*gdbarch
)
432 sparc_gdbarch_tdep
*tdep
= (sparc_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
434 if (!tdep
->sparc_psr_type
)
438 type
= arch_flags_type (gdbarch
, "builtin_type_sparc_psr", 32);
439 append_flags_type_flag (type
, 5, "ET");
440 append_flags_type_flag (type
, 6, "PS");
441 append_flags_type_flag (type
, 7, "S");
442 append_flags_type_flag (type
, 12, "EF");
443 append_flags_type_flag (type
, 13, "EC");
445 tdep
->sparc_psr_type
= type
;
448 return tdep
->sparc_psr_type
;
452 sparc_fsr_type (struct gdbarch
*gdbarch
)
454 sparc_gdbarch_tdep
*tdep
= (sparc_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
456 if (!tdep
->sparc_fsr_type
)
460 type
= arch_flags_type (gdbarch
, "builtin_type_sparc_fsr", 32);
461 append_flags_type_flag (type
, 0, "NXA");
462 append_flags_type_flag (type
, 1, "DZA");
463 append_flags_type_flag (type
, 2, "UFA");
464 append_flags_type_flag (type
, 3, "OFA");
465 append_flags_type_flag (type
, 4, "NVA");
466 append_flags_type_flag (type
, 5, "NXC");
467 append_flags_type_flag (type
, 6, "DZC");
468 append_flags_type_flag (type
, 7, "UFC");
469 append_flags_type_flag (type
, 8, "OFC");
470 append_flags_type_flag (type
, 9, "NVC");
471 append_flags_type_flag (type
, 22, "NS");
472 append_flags_type_flag (type
, 23, "NXM");
473 append_flags_type_flag (type
, 24, "DZM");
474 append_flags_type_flag (type
, 25, "UFM");
475 append_flags_type_flag (type
, 26, "OFM");
476 append_flags_type_flag (type
, 27, "NVM");
478 tdep
->sparc_fsr_type
= type
;
481 return tdep
->sparc_fsr_type
;
484 /* Return the GDB type object for the "standard" data type of data in
485 pseudo register REGNUM. */
488 sparc32_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
490 regnum
-= gdbarch_num_regs (gdbarch
);
492 if (regnum
>= SPARC32_D0_REGNUM
&& regnum
<= SPARC32_D30_REGNUM
)
493 return builtin_type (gdbarch
)->builtin_double
;
495 internal_error (__FILE__
, __LINE__
,
496 _("sparc32_pseudo_register_type: bad register number %d"),
500 /* Return the GDB type object for the "standard" data type of data in
504 sparc32_register_type (struct gdbarch
*gdbarch
, int regnum
)
506 if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
507 return tdesc_register_type (gdbarch
, regnum
);
509 if (regnum
>= SPARC_F0_REGNUM
&& regnum
<= SPARC_F31_REGNUM
)
510 return builtin_type (gdbarch
)->builtin_float
;
512 if (regnum
== SPARC_SP_REGNUM
|| regnum
== SPARC_FP_REGNUM
)
513 return builtin_type (gdbarch
)->builtin_data_ptr
;
515 if (regnum
== SPARC32_PC_REGNUM
|| regnum
== SPARC32_NPC_REGNUM
)
516 return builtin_type (gdbarch
)->builtin_func_ptr
;
518 if (regnum
== SPARC32_PSR_REGNUM
)
519 return sparc_psr_type (gdbarch
);
521 if (regnum
== SPARC32_FSR_REGNUM
)
522 return sparc_fsr_type (gdbarch
);
524 if (regnum
>= gdbarch_num_regs (gdbarch
))
525 return sparc32_pseudo_register_type (gdbarch
, regnum
);
527 return builtin_type (gdbarch
)->builtin_int32
;
530 static enum register_status
531 sparc32_pseudo_register_read (struct gdbarch
*gdbarch
,
532 readable_regcache
*regcache
,
533 int regnum
, gdb_byte
*buf
)
535 enum register_status status
;
537 regnum
-= gdbarch_num_regs (gdbarch
);
538 gdb_assert (regnum
>= SPARC32_D0_REGNUM
&& regnum
<= SPARC32_D30_REGNUM
);
540 regnum
= SPARC_F0_REGNUM
+ 2 * (regnum
- SPARC32_D0_REGNUM
);
541 status
= regcache
->raw_read (regnum
, buf
);
542 if (status
== REG_VALID
)
543 status
= regcache
->raw_read (regnum
+ 1, buf
+ 4);
548 sparc32_pseudo_register_write (struct gdbarch
*gdbarch
,
549 struct regcache
*regcache
,
550 int regnum
, const gdb_byte
*buf
)
552 regnum
-= gdbarch_num_regs (gdbarch
);
553 gdb_assert (regnum
>= SPARC32_D0_REGNUM
&& regnum
<= SPARC32_D30_REGNUM
);
555 regnum
= SPARC_F0_REGNUM
+ 2 * (regnum
- SPARC32_D0_REGNUM
);
556 regcache
->raw_write (regnum
, buf
);
557 regcache
->raw_write (regnum
+ 1, buf
+ 4);
560 /* Implement the stack_frame_destroyed_p gdbarch method. */
563 sparc_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
565 /* This function must return true if we are one instruction after an
566 instruction that destroyed the stack frame of the current
567 function. The SPARC instructions used to restore the callers
568 stack frame are RESTORE and RETURN/RETT.
570 Of these RETURN/RETT is a branch instruction and thus we return
571 true if we are in its delay slot.
573 RESTORE is almost always found in the delay slot of a branch
574 instruction that transfers control to the caller, such as JMPL.
575 Thus the next instruction is in the caller frame and we don't
576 need to do anything about it. */
578 unsigned int insn
= sparc_fetch_instruction (pc
- 4);
580 return X_RETTURN (insn
);
585 sparc32_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR address
)
587 /* The ABI requires double-word alignment. */
588 return address
& ~0x7;
592 sparc32_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
594 struct value
**args
, int nargs
,
595 struct type
*value_type
,
596 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
597 struct regcache
*regcache
)
599 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
604 if (using_struct_return (gdbarch
, NULL
, value_type
))
608 /* This is an UNIMP instruction. */
609 store_unsigned_integer (buf
, 4, byte_order
,
610 TYPE_LENGTH (value_type
) & 0x1fff);
611 write_memory (sp
- 8, buf
, 4);
619 sparc32_store_arguments (struct regcache
*regcache
, int nargs
,
620 struct value
**args
, CORE_ADDR sp
,
621 function_call_return_method return_method
,
622 CORE_ADDR struct_addr
)
624 struct gdbarch
*gdbarch
= regcache
->arch ();
625 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
626 /* Number of words in the "parameter array". */
627 int num_elements
= 0;
631 for (i
= 0; i
< nargs
; i
++)
633 struct type
*type
= value_type (args
[i
]);
634 int len
= TYPE_LENGTH (type
);
636 if (sparc_arg_by_memory_p (type
))
638 /* Structure, Union and Quad-Precision Arguments. */
641 /* Use doubleword alignment for these values. That's always
642 correct, and wasting a few bytes shouldn't be a problem. */
645 write_memory (sp
, value_contents (args
[i
]).data (), len
);
646 args
[i
] = value_from_pointer (lookup_pointer_type (type
), sp
);
649 else if (sparc_floating_p (type
))
651 /* Floating arguments. */
652 gdb_assert (len
== 4 || len
== 8);
653 num_elements
+= (len
/ 4);
657 /* Arguments passed via the General Purpose Registers. */
658 num_elements
+= ((len
+ 3) / 4);
662 /* Always allocate at least six words. */
663 sp
-= std::max (6, num_elements
) * 4;
665 /* The psABI says that "Software convention requires space for the
666 struct/union return value pointer, even if the word is unused." */
669 /* The psABI says that "Although software convention and the
670 operating system require every stack frame to be doubleword
674 for (i
= 0; i
< nargs
; i
++)
676 const bfd_byte
*valbuf
= value_contents (args
[i
]).data ();
677 struct type
*type
= value_type (args
[i
]);
678 int len
= TYPE_LENGTH (type
);
683 memset (buf
, 0, 4 - len
);
684 memcpy (buf
+ 4 - len
, valbuf
, len
);
689 gdb_assert (len
== 4 || len
== 8);
693 int regnum
= SPARC_O0_REGNUM
+ element
;
695 regcache
->cooked_write (regnum
, valbuf
);
696 if (len
> 4 && element
< 5)
697 regcache
->cooked_write (regnum
+ 1, valbuf
+ 4);
700 /* Always store the argument in memory. */
701 write_memory (sp
+ 4 + element
* 4, valbuf
, len
);
705 gdb_assert (element
== num_elements
);
707 if (return_method
== return_method_struct
)
711 store_unsigned_integer (buf
, 4, byte_order
, struct_addr
);
712 write_memory (sp
, buf
, 4);
719 sparc32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
720 struct regcache
*regcache
, CORE_ADDR bp_addr
,
721 int nargs
, struct value
**args
, CORE_ADDR sp
,
722 function_call_return_method return_method
,
723 CORE_ADDR struct_addr
)
725 CORE_ADDR call_pc
= (return_method
== return_method_struct
726 ? (bp_addr
- 12) : (bp_addr
- 8));
728 /* Set return address. */
729 regcache_cooked_write_unsigned (regcache
, SPARC_O7_REGNUM
, call_pc
);
731 /* Set up function arguments. */
732 sp
= sparc32_store_arguments (regcache
, nargs
, args
, sp
, return_method
,
735 /* Allocate the 16-word window save area. */
738 /* Stack should be doubleword aligned at this point. */
739 gdb_assert (sp
% 8 == 0);
741 /* Finally, update the stack pointer. */
742 regcache_cooked_write_unsigned (regcache
, SPARC_SP_REGNUM
, sp
);
748 /* Use the program counter to determine the contents and size of a
749 breakpoint instruction. Return a pointer to a string of bytes that
750 encode a breakpoint instruction, store the length of the string in
751 *LEN and optionally adjust *PC to point to the correct memory
752 location for inserting the breakpoint. */
753 constexpr gdb_byte sparc_break_insn
[] = { 0x91, 0xd0, 0x20, 0x01 };
755 typedef BP_MANIPULATION (sparc_break_insn
) sparc_breakpoint
;
758 /* Allocate and initialize a frame cache. */
760 static struct sparc_frame_cache
*
761 sparc_alloc_frame_cache (void)
763 struct sparc_frame_cache
*cache
;
765 cache
= FRAME_OBSTACK_ZALLOC (struct sparc_frame_cache
);
771 /* Frameless until proven otherwise. */
772 cache
->frameless_p
= 1;
773 cache
->frame_offset
= 0;
774 cache
->saved_regs_mask
= 0;
775 cache
->copied_regs_mask
= 0;
776 cache
->struct_return_p
= 0;
781 /* GCC generates several well-known sequences of instructions at the begining
782 of each function prologue when compiling with -fstack-check. If one of
783 such sequences starts at START_PC, then return the address of the
784 instruction immediately past this sequence. Otherwise, return START_PC. */
787 sparc_skip_stack_check (const CORE_ADDR start_pc
)
789 CORE_ADDR pc
= start_pc
;
791 int probing_loop
= 0;
793 /* With GCC, all stack checking sequences begin with the same two
794 instructions, plus an optional one in the case of a probing loop:
796 sethi <some immediate>, %g1
801 sethi <some immediate>, %g1
802 sethi <some immediate>, %g4
807 sethi <some immediate>, %g1
809 sethi <some immediate>, %g4
811 If the optional instruction is found (setting g4), assume that a
812 probing loop will follow. */
814 /* sethi <some immediate>, %g1 */
815 insn
= sparc_fetch_instruction (pc
);
817 if (!(X_OP (insn
) == 0 && X_OP2 (insn
) == 0x4 && X_RD (insn
) == 1))
820 /* optional: sethi <some immediate>, %g4 */
821 insn
= sparc_fetch_instruction (pc
);
823 if (X_OP (insn
) == 0 && X_OP2 (insn
) == 0x4 && X_RD (insn
) == 4)
826 insn
= sparc_fetch_instruction (pc
);
830 /* sub %sp, %g1, %g1 */
831 if (!(X_OP (insn
) == 2 && X_OP3 (insn
) == 0x4 && !X_I(insn
)
832 && X_RD (insn
) == 1 && X_RS1 (insn
) == 14 && X_RS2 (insn
) == 1))
835 insn
= sparc_fetch_instruction (pc
);
838 /* optional: sethi <some immediate>, %g4 */
839 if (X_OP (insn
) == 0 && X_OP2 (insn
) == 0x4 && X_RD (insn
) == 4)
842 insn
= sparc_fetch_instruction (pc
);
846 /* First possible sequence:
847 [first two instructions above]
848 clr [%g1 - some immediate] */
850 /* clr [%g1 - some immediate] */
851 if (X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && X_I(insn
)
852 && X_RS1 (insn
) == 1 && X_RD (insn
) == 0)
854 /* Valid stack-check sequence, return the new PC. */
858 /* Second possible sequence: A small number of probes.
859 [first two instructions above]
861 add %g1, -<some immediate>, %g1
863 [repeat the two instructions above any (small) number of times]
864 clr [%g1 - some immediate] */
867 else if (X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && !X_I(insn
)
868 && X_RS1 (insn
) == 1 && X_RD (insn
) == 0)
872 /* add %g1, -<some immediate>, %g1 */
873 insn
= sparc_fetch_instruction (pc
);
875 if (!(X_OP (insn
) == 2 && X_OP3(insn
) == 0 && X_I(insn
)
876 && X_RS1 (insn
) == 1 && X_RD (insn
) == 1))
880 insn
= sparc_fetch_instruction (pc
);
882 if (!(X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && !X_I(insn
)
883 && X_RD (insn
) == 0 && X_RS1 (insn
) == 1))
887 /* clr [%g1 - some immediate] */
888 if (!(X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && X_I(insn
)
889 && X_RS1 (insn
) == 1 && X_RD (insn
) == 0))
892 /* We found a valid stack-check sequence, return the new PC. */
896 /* Third sequence: A probing loop.
897 [first three instructions above]
901 add %g1, -<some immediate>, %g1
905 And an optional last probe for the remainder:
907 clr [%g4 - some immediate] */
911 /* sub %g1, %g4, %g4 */
912 if (!(X_OP (insn
) == 2 && X_OP3 (insn
) == 0x4 && !X_I(insn
)
913 && X_RD (insn
) == 4 && X_RS1 (insn
) == 1 && X_RS2 (insn
) == 4))
917 insn
= sparc_fetch_instruction (pc
);
919 if (!(X_OP (insn
) == 2 && X_OP3 (insn
) == 0x14 && !X_I(insn
)
920 && X_RD (insn
) == 0 && X_RS1 (insn
) == 1 && X_RS2 (insn
) == 4))
924 insn
= sparc_fetch_instruction (pc
);
926 if (!(X_OP (insn
) == 0 && X_COND (insn
) == 0x1))
929 /* add %g1, -<some immediate>, %g1 */
930 insn
= sparc_fetch_instruction (pc
);
932 if (!(X_OP (insn
) == 2 && X_OP3(insn
) == 0 && X_I(insn
)
933 && X_RS1 (insn
) == 1 && X_RD (insn
) == 1))
937 insn
= sparc_fetch_instruction (pc
);
939 if (!(X_OP (insn
) == 0 && X_COND (insn
) == 0x8))
942 /* clr [%g1] (st %g0, [%g1] or st %g0, [%g1+0]) */
943 insn
= sparc_fetch_instruction (pc
);
945 if (!(X_OP (insn
) == 3 && X_OP3(insn
) == 0x4
946 && X_RD (insn
) == 0 && X_RS1 (insn
) == 1
947 && (!X_I(insn
) || X_SIMM13 (insn
) == 0)))
950 /* We found a valid stack-check sequence, return the new PC. */
952 /* optional: clr [%g4 - some immediate] */
953 insn
= sparc_fetch_instruction (pc
);
955 if (!(X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && X_I(insn
)
956 && X_RS1 (insn
) == 4 && X_RD (insn
) == 0))
962 /* No stack check code in our prologue, return the start_pc. */
966 /* Record the effect of a SAVE instruction on CACHE. */
969 sparc_record_save_insn (struct sparc_frame_cache
*cache
)
971 /* The frame is set up. */
972 cache
->frameless_p
= 0;
974 /* The frame pointer contains the CFA. */
975 cache
->frame_offset
= 0;
977 /* The `local' and `in' registers are all saved. */
978 cache
->saved_regs_mask
= 0xffff;
980 /* The `out' registers are all renamed. */
981 cache
->copied_regs_mask
= 0xff;
984 /* Do a full analysis of the prologue at PC and update CACHE accordingly.
985 Bail out early if CURRENT_PC is reached. Return the address where
986 the analysis stopped.
988 We handle both the traditional register window model and the single
989 register window (aka flat) model. */
992 sparc_analyze_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
993 CORE_ADDR current_pc
, struct sparc_frame_cache
*cache
)
995 sparc_gdbarch_tdep
*tdep
= (sparc_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
1000 pc
= sparc_skip_stack_check (pc
);
1002 if (current_pc
<= pc
)
1005 /* We have to handle to "Procedure Linkage Table" (PLT) special. On
1006 SPARC the linker usually defines a symbol (typically
1007 _PROCEDURE_LINKAGE_TABLE_) at the start of the .plt section.
1008 This symbol makes us end up here with PC pointing at the start of
1009 the PLT and CURRENT_PC probably pointing at a PLT entry. If we
1010 would do our normal prologue analysis, we would probably conclude
1011 that we've got a frame when in reality we don't, since the
1012 dynamic linker patches up the first PLT with some code that
1013 starts with a SAVE instruction. Patch up PC such that it points
1014 at the start of our PLT entry. */
1015 if (tdep
->plt_entry_size
> 0 && in_plt_section (current_pc
))
1016 pc
= current_pc
- ((current_pc
- pc
) % tdep
->plt_entry_size
);
1018 insn
= sparc_fetch_instruction (pc
);
1020 /* Recognize store insns and record their sources. */
1021 while (X_OP (insn
) == 3
1022 && (X_OP3 (insn
) == 0x4 /* stw */
1023 || X_OP3 (insn
) == 0x7 /* std */
1024 || X_OP3 (insn
) == 0xe) /* stx */
1025 && X_RS1 (insn
) == SPARC_SP_REGNUM
)
1027 int regnum
= X_RD (insn
);
1029 /* Recognize stores into the corresponding stack slots. */
1030 if (regnum
>= SPARC_L0_REGNUM
&& regnum
<= SPARC_I7_REGNUM
1032 && X_SIMM13 (insn
) == (X_OP3 (insn
) == 0xe
1033 ? (regnum
- SPARC_L0_REGNUM
) * 8 + BIAS
1034 : (regnum
- SPARC_L0_REGNUM
) * 4))
1035 || (!X_I (insn
) && regnum
== SPARC_L0_REGNUM
)))
1037 cache
->saved_regs_mask
|= (1 << (regnum
- SPARC_L0_REGNUM
));
1038 if (X_OP3 (insn
) == 0x7)
1039 cache
->saved_regs_mask
|= (1 << (regnum
+ 1 - SPARC_L0_REGNUM
));
1044 insn
= sparc_fetch_instruction (pc
+ offset
);
1047 /* Recognize a SETHI insn and record its destination. */
1048 if (X_OP (insn
) == 0 && X_OP2 (insn
) == 0x04)
1053 insn
= sparc_fetch_instruction (pc
+ offset
);
1056 /* Allow for an arithmetic operation on DEST or %g1. */
1057 if (X_OP (insn
) == 2 && X_I (insn
)
1058 && (X_RD (insn
) == 1 || X_RD (insn
) == dest
))
1062 insn
= sparc_fetch_instruction (pc
+ offset
);
1065 /* Check for the SAVE instruction that sets up the frame. */
1066 if (X_OP (insn
) == 2 && X_OP3 (insn
) == 0x3c)
1068 sparc_record_save_insn (cache
);
1073 /* Check for an arithmetic operation on %sp. */
1074 if (X_OP (insn
) == 2
1075 && (X_OP3 (insn
) == 0 || X_OP3 (insn
) == 0x4)
1076 && X_RS1 (insn
) == SPARC_SP_REGNUM
1077 && X_RD (insn
) == SPARC_SP_REGNUM
)
1081 cache
->frame_offset
= X_SIMM13 (insn
);
1082 if (X_OP3 (insn
) == 0)
1083 cache
->frame_offset
= -cache
->frame_offset
;
1087 insn
= sparc_fetch_instruction (pc
+ offset
);
1089 /* Check for an arithmetic operation that sets up the frame. */
1090 if (X_OP (insn
) == 2
1091 && (X_OP3 (insn
) == 0 || X_OP3 (insn
) == 0x4)
1092 && X_RS1 (insn
) == SPARC_SP_REGNUM
1093 && X_RD (insn
) == SPARC_FP_REGNUM
)
1095 cache
->frameless_p
= 0;
1096 cache
->frame_offset
= 0;
1097 /* We could check that the amount subtracted to %sp above is the
1098 same as the one added here, but this seems superfluous. */
1099 cache
->copied_regs_mask
|= 0x40;
1102 insn
= sparc_fetch_instruction (pc
+ offset
);
1105 /* Check for a move (or) operation that copies the return register. */
1106 if (X_OP (insn
) == 2
1107 && X_OP3 (insn
) == 0x2
1109 && X_RS1 (insn
) == SPARC_G0_REGNUM
1110 && X_RS2 (insn
) == SPARC_O7_REGNUM
1111 && X_RD (insn
) == SPARC_I7_REGNUM
)
1113 cache
->copied_regs_mask
|= 0x80;
1123 /* Return PC of first real instruction of the function starting at
1127 sparc32_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
1129 struct symtab_and_line sal
;
1130 CORE_ADDR func_addr
;
1131 struct sparc_frame_cache cache
;
1133 /* This is the preferred method, find the end of the prologue by
1134 using the debugging information. */
1136 if (find_pc_partial_function (start_pc
, NULL
, &func_addr
, NULL
))
1138 CORE_ADDR post_prologue_pc
1139 = skip_prologue_using_sal (gdbarch
, func_addr
);
1141 if (post_prologue_pc
!= 0)
1142 return std::max (start_pc
, post_prologue_pc
);
1145 start_pc
= sparc_analyze_prologue (gdbarch
, start_pc
, 0xffffffffUL
, &cache
);
1147 /* The psABI says that "Although the first 6 words of arguments
1148 reside in registers, the standard stack frame reserves space for
1149 them.". It also suggests that a function may use that space to
1150 "write incoming arguments 0 to 5" into that space, and that's
1151 indeed what GCC seems to be doing. In that case GCC will
1152 generate debug information that points to the stack slots instead
1153 of the registers, so we should consider the instructions that
1154 write out these incoming arguments onto the stack. */
1158 unsigned long insn
= sparc_fetch_instruction (start_pc
);
1160 /* Recognize instructions that store incoming arguments into the
1161 corresponding stack slots. */
1162 if (X_OP (insn
) == 3 && (X_OP3 (insn
) & 0x3c) == 0x04
1163 && X_I (insn
) && X_RS1 (insn
) == SPARC_FP_REGNUM
)
1165 int regnum
= X_RD (insn
);
1167 /* Case of arguments still in %o[0..5]. */
1168 if (regnum
>= SPARC_O0_REGNUM
&& regnum
<= SPARC_O5_REGNUM
1169 && !(cache
.copied_regs_mask
& (1 << (regnum
- SPARC_O0_REGNUM
)))
1170 && X_SIMM13 (insn
) == 68 + (regnum
- SPARC_O0_REGNUM
) * 4)
1176 /* Case of arguments copied into %i[0..5]. */
1177 if (regnum
>= SPARC_I0_REGNUM
&& regnum
<= SPARC_I5_REGNUM
1178 && (cache
.copied_regs_mask
& (1 << (regnum
- SPARC_I0_REGNUM
)))
1179 && X_SIMM13 (insn
) == 68 + (regnum
- SPARC_I0_REGNUM
) * 4)
1192 /* Normal frames. */
1194 struct sparc_frame_cache
*
1195 sparc_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1197 struct sparc_frame_cache
*cache
;
1200 return (struct sparc_frame_cache
*) *this_cache
;
1202 cache
= sparc_alloc_frame_cache ();
1203 *this_cache
= cache
;
1205 cache
->pc
= get_frame_func (this_frame
);
1207 sparc_analyze_prologue (get_frame_arch (this_frame
), cache
->pc
,
1208 get_frame_pc (this_frame
), cache
);
1210 if (cache
->frameless_p
)
1212 /* This function is frameless, so %fp (%i6) holds the frame
1213 pointer for our calling frame. Use %sp (%o6) as this frame's
1216 get_frame_register_unsigned (this_frame
, SPARC_SP_REGNUM
);
1220 /* For normal frames, %fp (%i6) holds the frame pointer, the
1221 base address for the current stack frame. */
1223 get_frame_register_unsigned (this_frame
, SPARC_FP_REGNUM
);
1226 cache
->base
+= cache
->frame_offset
;
1228 if (cache
->base
& 1)
1229 cache
->base
+= BIAS
;
1235 sparc32_struct_return_from_sym (struct symbol
*sym
)
1237 struct type
*type
= check_typedef (SYMBOL_TYPE (sym
));
1238 enum type_code code
= type
->code ();
1240 if (code
== TYPE_CODE_FUNC
|| code
== TYPE_CODE_METHOD
)
1242 type
= check_typedef (TYPE_TARGET_TYPE (type
));
1243 if (sparc_structure_or_union_p (type
)
1244 || (sparc_floating_p (type
) && TYPE_LENGTH (type
) == 16))
1251 struct sparc_frame_cache
*
1252 sparc32_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1254 struct sparc_frame_cache
*cache
;
1258 return (struct sparc_frame_cache
*) *this_cache
;
1260 cache
= sparc_frame_cache (this_frame
, this_cache
);
1262 sym
= find_pc_function (cache
->pc
);
1265 cache
->struct_return_p
= sparc32_struct_return_from_sym (sym
);
1269 /* There is no debugging information for this function to
1270 help us determine whether this function returns a struct
1271 or not. So we rely on another heuristic which is to check
1272 the instruction at the return address and see if this is
1273 an "unimp" instruction. If it is, then it is a struct-return
1277 (cache
->copied_regs_mask
& 0x80) ? SPARC_I7_REGNUM
: SPARC_O7_REGNUM
;
1279 pc
= get_frame_register_unsigned (this_frame
, regnum
) + 8;
1280 if (sparc_is_unimp_insn (pc
))
1281 cache
->struct_return_p
= 1;
1288 sparc32_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1289 struct frame_id
*this_id
)
1291 struct sparc_frame_cache
*cache
=
1292 sparc32_frame_cache (this_frame
, this_cache
);
1294 /* This marks the outermost frame. */
1295 if (cache
->base
== 0)
1298 (*this_id
) = frame_id_build (cache
->base
, cache
->pc
);
1301 static struct value
*
1302 sparc32_frame_prev_register (struct frame_info
*this_frame
,
1303 void **this_cache
, int regnum
)
1305 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1306 struct sparc_frame_cache
*cache
=
1307 sparc32_frame_cache (this_frame
, this_cache
);
1309 if (regnum
== SPARC32_PC_REGNUM
|| regnum
== SPARC32_NPC_REGNUM
)
1311 CORE_ADDR pc
= (regnum
== SPARC32_NPC_REGNUM
) ? 4 : 0;
1313 /* If this functions has a Structure, Union or Quad-Precision
1314 return value, we have to skip the UNIMP instruction that encodes
1315 the size of the structure. */
1316 if (cache
->struct_return_p
)
1320 (cache
->copied_regs_mask
& 0x80) ? SPARC_I7_REGNUM
: SPARC_O7_REGNUM
;
1321 pc
+= get_frame_register_unsigned (this_frame
, regnum
) + 8;
1322 return frame_unwind_got_constant (this_frame
, regnum
, pc
);
1325 /* Handle StackGhost. */
1327 ULONGEST wcookie
= sparc_fetch_wcookie (gdbarch
);
1329 if (wcookie
!= 0 && !cache
->frameless_p
&& regnum
== SPARC_I7_REGNUM
)
1331 CORE_ADDR addr
= cache
->base
+ (regnum
- SPARC_L0_REGNUM
) * 4;
1334 /* Read the value in from memory. */
1335 i7
= get_frame_memory_unsigned (this_frame
, addr
, 4);
1336 return frame_unwind_got_constant (this_frame
, regnum
, i7
^ wcookie
);
1340 /* The previous frame's `local' and `in' registers may have been saved
1341 in the register save area. */
1342 if (regnum
>= SPARC_L0_REGNUM
&& regnum
<= SPARC_I7_REGNUM
1343 && (cache
->saved_regs_mask
& (1 << (regnum
- SPARC_L0_REGNUM
))))
1345 CORE_ADDR addr
= cache
->base
+ (regnum
- SPARC_L0_REGNUM
) * 4;
1347 return frame_unwind_got_memory (this_frame
, regnum
, addr
);
1350 /* The previous frame's `out' registers may be accessible as the current
1351 frame's `in' registers. */
1352 if (regnum
>= SPARC_O0_REGNUM
&& regnum
<= SPARC_O7_REGNUM
1353 && (cache
->copied_regs_mask
& (1 << (regnum
- SPARC_O0_REGNUM
))))
1354 regnum
+= (SPARC_I0_REGNUM
- SPARC_O0_REGNUM
);
1356 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
1359 static const struct frame_unwind sparc32_frame_unwind
=
1363 default_frame_unwind_stop_reason
,
1364 sparc32_frame_this_id
,
1365 sparc32_frame_prev_register
,
1367 default_frame_sniffer
1372 sparc32_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
1374 struct sparc_frame_cache
*cache
=
1375 sparc32_frame_cache (this_frame
, this_cache
);
1380 static const struct frame_base sparc32_frame_base
=
1382 &sparc32_frame_unwind
,
1383 sparc32_frame_base_address
,
1384 sparc32_frame_base_address
,
1385 sparc32_frame_base_address
1388 static struct frame_id
1389 sparc_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1393 sp
= get_frame_register_unsigned (this_frame
, SPARC_SP_REGNUM
);
1396 return frame_id_build (sp
, get_frame_pc (this_frame
));
1400 /* Extract a function return value of TYPE from REGCACHE, and copy
1401 that into VALBUF. */
1404 sparc32_extract_return_value (struct type
*type
, struct regcache
*regcache
,
1407 int len
= TYPE_LENGTH (type
);
1410 gdb_assert (!sparc_structure_return_p (type
));
1412 if (sparc_floating_p (type
) || sparc_complex_floating_p (type
)
1413 || type
->code () == TYPE_CODE_ARRAY
)
1415 /* Floating return values. */
1416 regcache
->cooked_read (SPARC_F0_REGNUM
, buf
);
1418 regcache
->cooked_read (SPARC_F1_REGNUM
, buf
+ 4);
1421 regcache
->cooked_read (SPARC_F2_REGNUM
, buf
+ 8);
1422 regcache
->cooked_read (SPARC_F3_REGNUM
, buf
+ 12);
1426 regcache
->cooked_read (SPARC_F4_REGNUM
, buf
+ 16);
1427 regcache
->cooked_read (SPARC_F5_REGNUM
, buf
+ 20);
1428 regcache
->cooked_read (SPARC_F6_REGNUM
, buf
+ 24);
1429 regcache
->cooked_read (SPARC_F7_REGNUM
, buf
+ 28);
1431 memcpy (valbuf
, buf
, len
);
1435 /* Integral and pointer return values. */
1436 gdb_assert (sparc_integral_or_pointer_p (type
));
1438 regcache
->cooked_read (SPARC_O0_REGNUM
, buf
);
1441 regcache
->cooked_read (SPARC_O1_REGNUM
, buf
+ 4);
1442 gdb_assert (len
== 8);
1443 memcpy (valbuf
, buf
, 8);
1447 /* Just stripping off any unused bytes should preserve the
1448 signed-ness just fine. */
1449 memcpy (valbuf
, buf
+ 4 - len
, len
);
1454 /* Store the function return value of type TYPE from VALBUF into
1458 sparc32_store_return_value (struct type
*type
, struct regcache
*regcache
,
1459 const gdb_byte
*valbuf
)
1461 int len
= TYPE_LENGTH (type
);
1464 gdb_assert (!sparc_structure_return_p (type
));
1466 if (sparc_floating_p (type
) || sparc_complex_floating_p (type
))
1468 /* Floating return values. */
1469 memcpy (buf
, valbuf
, len
);
1470 regcache
->cooked_write (SPARC_F0_REGNUM
, buf
);
1472 regcache
->cooked_write (SPARC_F1_REGNUM
, buf
+ 4);
1475 regcache
->cooked_write (SPARC_F2_REGNUM
, buf
+ 8);
1476 regcache
->cooked_write (SPARC_F3_REGNUM
, buf
+ 12);
1480 regcache
->cooked_write (SPARC_F4_REGNUM
, buf
+ 16);
1481 regcache
->cooked_write (SPARC_F5_REGNUM
, buf
+ 20);
1482 regcache
->cooked_write (SPARC_F6_REGNUM
, buf
+ 24);
1483 regcache
->cooked_write (SPARC_F7_REGNUM
, buf
+ 28);
1488 /* Integral and pointer return values. */
1489 gdb_assert (sparc_integral_or_pointer_p (type
));
1493 gdb_assert (len
== 8);
1494 memcpy (buf
, valbuf
, 8);
1495 regcache
->cooked_write (SPARC_O1_REGNUM
, buf
+ 4);
1499 /* ??? Do we need to do any sign-extension here? */
1500 memcpy (buf
+ 4 - len
, valbuf
, len
);
1502 regcache
->cooked_write (SPARC_O0_REGNUM
, buf
);
1506 static enum return_value_convention
1507 sparc32_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
1508 struct type
*type
, struct regcache
*regcache
,
1509 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
1511 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1513 /* The psABI says that "...every stack frame reserves the word at
1514 %fp+64. If a function returns a structure, union, or
1515 quad-precision value, this word should hold the address of the
1516 object into which the return value should be copied." This
1517 guarantees that we can always find the return value, not just
1518 before the function returns. */
1520 if (sparc_structure_return_p (type
))
1527 regcache_cooked_read_unsigned (regcache
, SPARC_SP_REGNUM
, &sp
);
1528 addr
= read_memory_unsigned_integer (sp
+ 64, 4, byte_order
);
1529 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
1533 regcache_cooked_read_unsigned (regcache
, SPARC_SP_REGNUM
, &sp
);
1534 addr
= read_memory_unsigned_integer (sp
+ 64, 4, byte_order
);
1535 write_memory (addr
, writebuf
, TYPE_LENGTH (type
));
1538 return RETURN_VALUE_ABI_PRESERVES_ADDRESS
;
1542 sparc32_extract_return_value (type
, regcache
, readbuf
);
1544 sparc32_store_return_value (type
, regcache
, writebuf
);
1546 return RETURN_VALUE_REGISTER_CONVENTION
;
1550 sparc32_stabs_argument_has_addr (struct gdbarch
*gdbarch
, struct type
*type
)
1552 return (sparc_structure_or_union_p (type
)
1553 || (sparc_floating_p (type
) && TYPE_LENGTH (type
) == 16)
1554 || sparc_complex_floating_p (type
));
1558 sparc32_dwarf2_struct_return_p (struct frame_info
*this_frame
)
1560 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
1561 struct symbol
*sym
= find_pc_function (pc
);
1564 return sparc32_struct_return_from_sym (sym
);
1569 sparc32_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
1570 struct dwarf2_frame_state_reg
*reg
,
1571 struct frame_info
*this_frame
)
1577 case SPARC_G0_REGNUM
:
1578 /* Since %g0 is always zero, there is no point in saving it, and
1579 people will be inclined omit it from the CFI. Make sure we
1580 don't warn about that. */
1581 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
1583 case SPARC_SP_REGNUM
:
1584 reg
->how
= DWARF2_FRAME_REG_CFA
;
1586 case SPARC32_PC_REGNUM
:
1587 case SPARC32_NPC_REGNUM
:
1588 reg
->how
= DWARF2_FRAME_REG_RA_OFFSET
;
1590 if (sparc32_dwarf2_struct_return_p (this_frame
))
1592 if (regnum
== SPARC32_NPC_REGNUM
)
1594 reg
->loc
.offset
= off
;
1599 /* Implement the execute_dwarf_cfa_vendor_op method. */
1602 sparc_execute_dwarf_cfa_vendor_op (struct gdbarch
*gdbarch
, gdb_byte op
,
1603 struct dwarf2_frame_state
*fs
)
1605 /* Only DW_CFA_GNU_window_save is expected on SPARC. */
1606 if (op
!= DW_CFA_GNU_window_save
)
1610 int size
= register_size (gdbarch
, 0);
1612 fs
->regs
.alloc_regs (32);
1613 for (reg
= 8; reg
< 16; reg
++)
1615 fs
->regs
.reg
[reg
].how
= DWARF2_FRAME_REG_SAVED_REG
;
1616 fs
->regs
.reg
[reg
].loc
.reg
= reg
+ 16;
1618 for (reg
= 16; reg
< 32; reg
++)
1620 fs
->regs
.reg
[reg
].how
= DWARF2_FRAME_REG_SAVED_OFFSET
;
1621 fs
->regs
.reg
[reg
].loc
.offset
= (reg
- 16) * size
;
1628 /* The SPARC Architecture doesn't have hardware single-step support,
1629 and most operating systems don't implement it either, so we provide
1630 software single-step mechanism. */
1633 sparc_analyze_control_transfer (struct regcache
*regcache
,
1634 CORE_ADDR pc
, CORE_ADDR
*npc
)
1636 unsigned long insn
= sparc_fetch_instruction (pc
);
1637 int conditional_p
= X_COND (insn
) & 0x7;
1638 int branch_p
= 0, fused_p
= 0;
1639 long offset
= 0; /* Must be signed for sign-extend. */
1641 if (X_OP (insn
) == 0 && X_OP2 (insn
) == 3)
1643 if ((insn
& 0x10000000) == 0)
1645 /* Branch on Integer Register with Prediction (BPr). */
1651 /* Compare and Branch */
1654 offset
= 4 * X_DISP10 (insn
);
1657 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 6)
1659 /* Branch on Floating-Point Condition Codes (FBfcc). */
1661 offset
= 4 * X_DISP22 (insn
);
1663 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 5)
1665 /* Branch on Floating-Point Condition Codes with Prediction
1668 offset
= 4 * X_DISP19 (insn
);
1670 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 2)
1672 /* Branch on Integer Condition Codes (Bicc). */
1674 offset
= 4 * X_DISP22 (insn
);
1676 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 1)
1678 /* Branch on Integer Condition Codes with Prediction (BPcc). */
1680 offset
= 4 * X_DISP19 (insn
);
1682 else if (X_OP (insn
) == 2 && X_OP3 (insn
) == 0x3a)
1684 struct frame_info
*frame
= get_current_frame ();
1686 /* Trap instruction (TRAP). */
1687 gdbarch
*arch
= regcache
->arch ();
1688 sparc_gdbarch_tdep
*tdep
= (sparc_gdbarch_tdep
*) gdbarch_tdep (arch
);
1689 return tdep
->step_trap (frame
, insn
);
1692 /* FIXME: Handle DONE and RETRY instructions. */
1698 /* Fused compare-and-branch instructions are non-delayed,
1699 and do not have an annulling capability. So we need to
1700 always set a breakpoint on both the NPC and the branch
1702 gdb_assert (offset
!= 0);
1705 else if (conditional_p
)
1707 /* For conditional branches, return nPC + 4 iff the annul
1709 return (X_A (insn
) ? *npc
+ 4 : 0);
1713 /* For unconditional branches, return the target if its
1714 specified condition is "always" and return nPC + 4 if the
1715 condition is "never". If the annul bit is 1, set *NPC to
1717 if (X_COND (insn
) == 0x0)
1718 pc
= *npc
, offset
= 4;
1730 sparc_step_trap (struct frame_info
*frame
, unsigned long insn
)
1735 static std::vector
<CORE_ADDR
>
1736 sparc_software_single_step (struct regcache
*regcache
)
1738 struct gdbarch
*arch
= regcache
->arch ();
1739 sparc_gdbarch_tdep
*tdep
= (sparc_gdbarch_tdep
*) gdbarch_tdep (arch
);
1740 CORE_ADDR npc
, nnpc
;
1742 CORE_ADDR pc
, orig_npc
;
1743 std::vector
<CORE_ADDR
> next_pcs
;
1745 pc
= regcache_raw_get_unsigned (regcache
, tdep
->pc_regnum
);
1746 orig_npc
= npc
= regcache_raw_get_unsigned (regcache
, tdep
->npc_regnum
);
1748 /* Analyze the instruction at PC. */
1749 nnpc
= sparc_analyze_control_transfer (regcache
, pc
, &npc
);
1751 next_pcs
.push_back (npc
);
1754 next_pcs
.push_back (nnpc
);
1756 /* Assert that we have set at least one breakpoint, and that
1757 they're not set at the same spot - unless we're going
1758 from here straight to NULL, i.e. a call or jump to 0. */
1759 gdb_assert (npc
!= 0 || nnpc
!= 0 || orig_npc
== 0);
1760 gdb_assert (nnpc
!= npc
|| orig_npc
== 0);
1766 sparc_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1768 gdbarch
*arch
= regcache
->arch ();
1769 sparc_gdbarch_tdep
*tdep
= (sparc_gdbarch_tdep
*) gdbarch_tdep (arch
);
1771 regcache_cooked_write_unsigned (regcache
, tdep
->pc_regnum
, pc
);
1772 regcache_cooked_write_unsigned (regcache
, tdep
->npc_regnum
, pc
+ 4);
1776 /* Iterate over core file register note sections. */
1779 sparc_iterate_over_regset_sections (struct gdbarch
*gdbarch
,
1780 iterate_over_regset_sections_cb
*cb
,
1782 const struct regcache
*regcache
)
1784 sparc_gdbarch_tdep
*tdep
= (sparc_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
1786 cb (".reg", tdep
->sizeof_gregset
, tdep
->sizeof_gregset
, tdep
->gregset
, NULL
,
1788 cb (".reg2", tdep
->sizeof_fpregset
, tdep
->sizeof_fpregset
, tdep
->fpregset
,
1794 validate_tdesc_registers (const struct target_desc
*tdesc
,
1795 struct tdesc_arch_data
*tdesc_data
,
1796 const char *feature_name
,
1797 const char * const register_names
[],
1798 unsigned int registers_num
,
1799 unsigned int reg_start
)
1802 const struct tdesc_feature
*feature
;
1804 feature
= tdesc_find_feature (tdesc
, feature_name
);
1805 if (feature
== NULL
)
1808 for (unsigned int i
= 0; i
< registers_num
; i
++)
1809 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
1816 static struct gdbarch
*
1817 sparc32_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
1819 const struct target_desc
*tdesc
= info
.target_desc
;
1820 struct gdbarch
*gdbarch
;
1823 /* If there is already a candidate, use it. */
1824 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
1826 return arches
->gdbarch
;
1828 /* Allocate space for the new architecture. */
1829 sparc_gdbarch_tdep
*tdep
= new sparc_gdbarch_tdep
;
1830 gdbarch
= gdbarch_alloc (&info
, tdep
);
1832 tdep
->pc_regnum
= SPARC32_PC_REGNUM
;
1833 tdep
->npc_regnum
= SPARC32_NPC_REGNUM
;
1834 tdep
->step_trap
= sparc_step_trap
;
1835 tdep
->fpu_register_names
= sparc32_fpu_register_names
;
1836 tdep
->fpu_registers_num
= ARRAY_SIZE (sparc32_fpu_register_names
);
1837 tdep
->cp0_register_names
= sparc32_cp0_register_names
;
1838 tdep
->cp0_registers_num
= ARRAY_SIZE (sparc32_cp0_register_names
);
1840 set_gdbarch_long_double_bit (gdbarch
, 128);
1841 set_gdbarch_long_double_format (gdbarch
, floatformats_sparc_quad
);
1843 set_gdbarch_wchar_bit (gdbarch
, 16);
1844 set_gdbarch_wchar_signed (gdbarch
, 1);
1846 set_gdbarch_num_regs (gdbarch
, SPARC32_NUM_REGS
);
1847 set_gdbarch_register_name (gdbarch
, sparc32_register_name
);
1848 set_gdbarch_register_type (gdbarch
, sparc32_register_type
);
1849 set_gdbarch_num_pseudo_regs (gdbarch
, SPARC32_NUM_PSEUDO_REGS
);
1850 set_tdesc_pseudo_register_name (gdbarch
, sparc32_pseudo_register_name
);
1851 set_tdesc_pseudo_register_type (gdbarch
, sparc32_pseudo_register_type
);
1852 set_gdbarch_pseudo_register_read (gdbarch
, sparc32_pseudo_register_read
);
1853 set_gdbarch_pseudo_register_write (gdbarch
, sparc32_pseudo_register_write
);
1855 /* Register numbers of various important registers. */
1856 set_gdbarch_sp_regnum (gdbarch
, SPARC_SP_REGNUM
); /* %sp */
1857 set_gdbarch_pc_regnum (gdbarch
, SPARC32_PC_REGNUM
); /* %pc */
1858 set_gdbarch_fp0_regnum (gdbarch
, SPARC_F0_REGNUM
); /* %f0 */
1860 /* Call dummy code. */
1861 set_gdbarch_frame_align (gdbarch
, sparc32_frame_align
);
1862 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
1863 set_gdbarch_push_dummy_code (gdbarch
, sparc32_push_dummy_code
);
1864 set_gdbarch_push_dummy_call (gdbarch
, sparc32_push_dummy_call
);
1866 set_gdbarch_return_value (gdbarch
, sparc32_return_value
);
1867 set_gdbarch_stabs_argument_has_addr
1868 (gdbarch
, sparc32_stabs_argument_has_addr
);
1870 set_gdbarch_skip_prologue (gdbarch
, sparc32_skip_prologue
);
1872 /* Stack grows downward. */
1873 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
1875 set_gdbarch_breakpoint_kind_from_pc (gdbarch
,
1876 sparc_breakpoint::kind_from_pc
);
1877 set_gdbarch_sw_breakpoint_from_kind (gdbarch
,
1878 sparc_breakpoint::bp_from_kind
);
1880 set_gdbarch_frame_args_skip (gdbarch
, 8);
1882 set_gdbarch_software_single_step (gdbarch
, sparc_software_single_step
);
1883 set_gdbarch_write_pc (gdbarch
, sparc_write_pc
);
1885 set_gdbarch_dummy_id (gdbarch
, sparc_dummy_id
);
1887 frame_base_set_default (gdbarch
, &sparc32_frame_base
);
1889 /* Hook in the DWARF CFI frame unwinder. */
1890 dwarf2_frame_set_init_reg (gdbarch
, sparc32_dwarf2_frame_init_reg
);
1891 /* Register DWARF vendor CFI handler. */
1892 set_gdbarch_execute_dwarf_cfa_vendor_op (gdbarch
,
1893 sparc_execute_dwarf_cfa_vendor_op
);
1894 /* FIXME: kettenis/20050423: Don't enable the unwinder until the
1895 StackGhost issues have been resolved. */
1897 /* Hook in ABI-specific overrides, if they have been registered. */
1898 gdbarch_init_osabi (info
, gdbarch
);
1900 frame_unwind_append_unwinder (gdbarch
, &sparc32_frame_unwind
);
1902 if (tdesc_has_registers (tdesc
))
1904 tdesc_arch_data_up tdesc_data
= tdesc_data_alloc ();
1906 /* Validate that the descriptor provides the mandatory registers
1907 and allocate their numbers. */
1908 valid_p
&= validate_tdesc_registers (tdesc
, tdesc_data
.get (),
1909 "org.gnu.gdb.sparc.cpu",
1910 sparc_core_register_names
,
1911 ARRAY_SIZE (sparc_core_register_names
),
1913 valid_p
&= validate_tdesc_registers (tdesc
, tdesc_data
.get (),
1914 "org.gnu.gdb.sparc.fpu",
1915 tdep
->fpu_register_names
,
1916 tdep
->fpu_registers_num
,
1918 valid_p
&= validate_tdesc_registers (tdesc
, tdesc_data
.get (),
1919 "org.gnu.gdb.sparc.cp0",
1920 tdep
->cp0_register_names
,
1921 tdep
->cp0_registers_num
,
1923 + tdep
->fpu_registers_num
);
1927 /* Target description may have changed. */
1928 info
.tdesc_data
= tdesc_data
.get ();
1929 tdesc_use_registers (gdbarch
, tdesc
, std::move (tdesc_data
));
1932 /* If we have register sets, enable the generic core file support. */
1934 set_gdbarch_iterate_over_regset_sections
1935 (gdbarch
, sparc_iterate_over_regset_sections
);
1937 register_sparc_ravenscar_ops (gdbarch
);
1942 /* Helper functions for dealing with register windows. */
1945 sparc_supply_rwindow (struct regcache
*regcache
, CORE_ADDR sp
, int regnum
)
1947 struct gdbarch
*gdbarch
= regcache
->arch ();
1948 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1953 /* This function calls functions that depend on the global current thread. */
1954 gdb_assert (regcache
->ptid () == inferior_ptid
);
1958 /* Registers are 64-bit. */
1961 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1963 if (regnum
== i
|| regnum
== -1)
1965 target_read_memory (sp
+ ((i
- SPARC_L0_REGNUM
) * 8), buf
, 8);
1967 /* Handle StackGhost. */
1968 if (i
== SPARC_I7_REGNUM
)
1970 ULONGEST wcookie
= sparc_fetch_wcookie (gdbarch
);
1973 i7
= extract_unsigned_integer (buf
+ offset
, 8, byte_order
);
1974 store_unsigned_integer (buf
+ offset
, 8, byte_order
,
1978 regcache
->raw_supply (i
, buf
);
1984 /* Registers are 32-bit. Toss any sign-extension of the stack
1988 /* Clear out the top half of the temporary buffer, and put the
1989 register value in the bottom half if we're in 64-bit mode. */
1990 if (gdbarch_ptr_bit (regcache
->arch ()) == 64)
1996 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1998 if (regnum
== i
|| regnum
== -1)
2000 target_read_memory (sp
+ ((i
- SPARC_L0_REGNUM
) * 4),
2003 /* Handle StackGhost. */
2004 if (i
== SPARC_I7_REGNUM
)
2006 ULONGEST wcookie
= sparc_fetch_wcookie (gdbarch
);
2009 i7
= extract_unsigned_integer (buf
+ offset
, 4, byte_order
);
2010 store_unsigned_integer (buf
+ offset
, 4, byte_order
,
2014 regcache
->raw_supply (i
, buf
);
2021 sparc_collect_rwindow (const struct regcache
*regcache
,
2022 CORE_ADDR sp
, int regnum
)
2024 struct gdbarch
*gdbarch
= regcache
->arch ();
2025 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2030 /* This function calls functions that depend on the global current thread. */
2031 gdb_assert (regcache
->ptid () == inferior_ptid
);
2035 /* Registers are 64-bit. */
2038 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
2040 if (regnum
== -1 || regnum
== SPARC_SP_REGNUM
|| regnum
== i
)
2042 regcache
->raw_collect (i
, buf
);
2044 /* Handle StackGhost. */
2045 if (i
== SPARC_I7_REGNUM
)
2047 ULONGEST wcookie
= sparc_fetch_wcookie (gdbarch
);
2050 i7
= extract_unsigned_integer (buf
+ offset
, 8, byte_order
);
2051 store_unsigned_integer (buf
, 8, byte_order
, i7
^ wcookie
);
2054 target_write_memory (sp
+ ((i
- SPARC_L0_REGNUM
) * 8), buf
, 8);
2060 /* Registers are 32-bit. Toss any sign-extension of the stack
2064 /* Only use the bottom half if we're in 64-bit mode. */
2065 if (gdbarch_ptr_bit (regcache
->arch ()) == 64)
2068 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
2070 if (regnum
== -1 || regnum
== SPARC_SP_REGNUM
|| regnum
== i
)
2072 regcache
->raw_collect (i
, buf
);
2074 /* Handle StackGhost. */
2075 if (i
== SPARC_I7_REGNUM
)
2077 ULONGEST wcookie
= sparc_fetch_wcookie (gdbarch
);
2080 i7
= extract_unsigned_integer (buf
+ offset
, 4, byte_order
);
2081 store_unsigned_integer (buf
+ offset
, 4, byte_order
,
2085 target_write_memory (sp
+ ((i
- SPARC_L0_REGNUM
) * 4),
2092 /* Helper functions for dealing with register sets. */
2095 sparc32_supply_gregset (const struct sparc_gregmap
*gregmap
,
2096 struct regcache
*regcache
,
2097 int regnum
, const void *gregs
)
2099 const gdb_byte
*regs
= (const gdb_byte
*) gregs
;
2100 gdb_byte zero
[4] = { 0 };
2103 if (regnum
== SPARC32_PSR_REGNUM
|| regnum
== -1)
2104 regcache
->raw_supply (SPARC32_PSR_REGNUM
, regs
+ gregmap
->r_psr_offset
);
2106 if (regnum
== SPARC32_PC_REGNUM
|| regnum
== -1)
2107 regcache
->raw_supply (SPARC32_PC_REGNUM
, regs
+ gregmap
->r_pc_offset
);
2109 if (regnum
== SPARC32_NPC_REGNUM
|| regnum
== -1)
2110 regcache
->raw_supply (SPARC32_NPC_REGNUM
, regs
+ gregmap
->r_npc_offset
);
2112 if (regnum
== SPARC32_Y_REGNUM
|| regnum
== -1)
2113 regcache
->raw_supply (SPARC32_Y_REGNUM
, regs
+ gregmap
->r_y_offset
);
2115 if (regnum
== SPARC_G0_REGNUM
|| regnum
== -1)
2116 regcache
->raw_supply (SPARC_G0_REGNUM
, &zero
);
2118 if ((regnum
>= SPARC_G1_REGNUM
&& regnum
<= SPARC_O7_REGNUM
) || regnum
== -1)
2120 int offset
= gregmap
->r_g1_offset
;
2122 for (i
= SPARC_G1_REGNUM
; i
<= SPARC_O7_REGNUM
; i
++)
2124 if (regnum
== i
|| regnum
== -1)
2125 regcache
->raw_supply (i
, regs
+ offset
);
2130 if ((regnum
>= SPARC_L0_REGNUM
&& regnum
<= SPARC_I7_REGNUM
) || regnum
== -1)
2132 /* Not all of the register set variants include Locals and
2133 Inputs. For those that don't, we read them off the stack. */
2134 if (gregmap
->r_l0_offset
== -1)
2138 regcache_cooked_read_unsigned (regcache
, SPARC_SP_REGNUM
, &sp
);
2139 sparc_supply_rwindow (regcache
, sp
, regnum
);
2143 int offset
= gregmap
->r_l0_offset
;
2145 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
2147 if (regnum
== i
|| regnum
== -1)
2148 regcache
->raw_supply (i
, regs
+ offset
);
2156 sparc32_collect_gregset (const struct sparc_gregmap
*gregmap
,
2157 const struct regcache
*regcache
,
2158 int regnum
, void *gregs
)
2160 gdb_byte
*regs
= (gdb_byte
*) gregs
;
2163 if (regnum
== SPARC32_PSR_REGNUM
|| regnum
== -1)
2164 regcache
->raw_collect (SPARC32_PSR_REGNUM
, regs
+ gregmap
->r_psr_offset
);
2166 if (regnum
== SPARC32_PC_REGNUM
|| regnum
== -1)
2167 regcache
->raw_collect (SPARC32_PC_REGNUM
, regs
+ gregmap
->r_pc_offset
);
2169 if (regnum
== SPARC32_NPC_REGNUM
|| regnum
== -1)
2170 regcache
->raw_collect (SPARC32_NPC_REGNUM
, regs
+ gregmap
->r_npc_offset
);
2172 if (regnum
== SPARC32_Y_REGNUM
|| regnum
== -1)
2173 regcache
->raw_collect (SPARC32_Y_REGNUM
, regs
+ gregmap
->r_y_offset
);
2175 if ((regnum
>= SPARC_G1_REGNUM
&& regnum
<= SPARC_O7_REGNUM
) || regnum
== -1)
2177 int offset
= gregmap
->r_g1_offset
;
2179 /* %g0 is always zero. */
2180 for (i
= SPARC_G1_REGNUM
; i
<= SPARC_O7_REGNUM
; i
++)
2182 if (regnum
== i
|| regnum
== -1)
2183 regcache
->raw_collect (i
, regs
+ offset
);
2188 if ((regnum
>= SPARC_L0_REGNUM
&& regnum
<= SPARC_I7_REGNUM
) || regnum
== -1)
2190 /* Not all of the register set variants include Locals and
2191 Inputs. For those that don't, we read them off the stack. */
2192 if (gregmap
->r_l0_offset
!= -1)
2194 int offset
= gregmap
->r_l0_offset
;
2196 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
2198 if (regnum
== i
|| regnum
== -1)
2199 regcache
->raw_collect (i
, regs
+ offset
);
2207 sparc32_supply_fpregset (const struct sparc_fpregmap
*fpregmap
,
2208 struct regcache
*regcache
,
2209 int regnum
, const void *fpregs
)
2211 const gdb_byte
*regs
= (const gdb_byte
*) fpregs
;
2214 for (i
= 0; i
< 32; i
++)
2216 if (regnum
== (SPARC_F0_REGNUM
+ i
) || regnum
== -1)
2217 regcache
->raw_supply (SPARC_F0_REGNUM
+ i
,
2218 regs
+ fpregmap
->r_f0_offset
+ (i
* 4));
2221 if (regnum
== SPARC32_FSR_REGNUM
|| regnum
== -1)
2222 regcache
->raw_supply (SPARC32_FSR_REGNUM
, regs
+ fpregmap
->r_fsr_offset
);
2226 sparc32_collect_fpregset (const struct sparc_fpregmap
*fpregmap
,
2227 const struct regcache
*regcache
,
2228 int regnum
, void *fpregs
)
2230 gdb_byte
*regs
= (gdb_byte
*) fpregs
;
2233 for (i
= 0; i
< 32; i
++)
2235 if (regnum
== (SPARC_F0_REGNUM
+ i
) || regnum
== -1)
2236 regcache
->raw_collect (SPARC_F0_REGNUM
+ i
,
2237 regs
+ fpregmap
->r_f0_offset
+ (i
* 4));
2240 if (regnum
== SPARC32_FSR_REGNUM
|| regnum
== -1)
2241 regcache
->raw_collect (SPARC32_FSR_REGNUM
,
2242 regs
+ fpregmap
->r_fsr_offset
);
2248 /* From <machine/reg.h>. */
2249 const struct sparc_gregmap sparc32_sunos4_gregmap
=
2261 const struct sparc_fpregmap sparc32_sunos4_fpregmap
=
2267 const struct sparc_fpregmap sparc32_bsd_fpregmap
=
2273 void _initialize_sparc_tdep ();
2275 _initialize_sparc_tdep ()
2277 register_gdbarch_init (bfd_arch_sparc
, sparc32_gdbarch_init
);