gdb/sparc-tdep.c

   1 /* Machine-dependent code which would otherwise be in inflow.c and core.c,
   2    for GDB, the GNU debugger.
   3    Copyright (C) 1986, 1987, 1989 Free Software Foundation, Inc.
   4    This code is for the sparc cpu.
   5
   6 This file is part of GDB.
   7
   8 GDB is free software; you can redistribute it and/or modify
   9 it under the terms of the GNU General Public License as published by
  10 the Free Software Foundation; either version 1, or (at your option)
  11 any later version.
  12
  13 GDB is distributed in the hope that it will be useful,
  14 but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 GNU General Public License for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with GDB; see the file COPYING.  If not, write to
  20 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
  21
  22 #include <stdio.h>
  23 #include "defs.h"
  24 #include "param.h"
  25 #include "frame.h"
  26 #include "inferior.h"
  27 #include "obstack.h"
  28 #include "signame.h"
  29 #include "target.h"
  30 #include "ieee-float.h"
  31
  32 #include <sys/param.h>
  33 #include <sys/dir.h>
  34 #include <sys/user.h>
  35 #include <signal.h>
  36 #include <sys/ioctl.h>
  37 #include <fcntl.h>
  38
  39 #include <sys/ptrace.h>
  40 #include <machine/reg.h>
  41
  42 #include <sys/file.h>
  43 #include <sys/stat.h>
  44 #include <sys/core.h>
  45
  46 #include "gdbcore.h"
  47
  48 /* From infrun.c */
  49 extern int stop_after_trap;
  50
  51 typedef enum
  52 {
  53   Error, not_branch, bicc, bicca, ba, baa, ticc, ta,
  54 } branch_type;
  55
  56 /* Simulate single-step ptrace call for sun4.  Code written by Gary
  57    Beihl (beihl@mcc.com).  */
  58
  59 /* npc4 and next_pc describe the situation at the time that the
  60    step-breakpoint was set, not necessary the current value of NPC_REGNUM.  */
  61 static CORE_ADDR next_pc, npc4, target;
  62 static int brknpc4, brktrg;
  63 typedef char binsn_quantum[BREAKPOINT_MAX];
  64 static binsn_quantum break_mem[3];
  65
  66 /* Non-zero if we just simulated a single-step ptrace call.  This is
  67    needed because we cannot remove the breakpoints in the inferior
  68    process until after the `wait' in `wait_for_inferior'.  Used for
  69    sun4. */
  70
  71 int one_stepped;
  72
  73 void
  74 single_step (signal)
  75      int signal;
  76 {
  77   branch_type br, isannulled();
  78   CORE_ADDR pc;
  79   long pc_instruction;
  80
  81   if (!one_stepped)
  82     {
  83       /* Always set breakpoint for NPC.  */
  84       next_pc = read_register (NPC_REGNUM);
  85       npc4 = next_pc + 4; /* branch not taken */
  86
  87       target_insert_breakpoint (next_pc, break_mem[0]);
  88       /* printf ("set break at %x\n",next_pc); */
  89
  90       pc = read_register (PC_REGNUM);
  91       pc_instruction = read_memory_integer (pc, sizeof(pc_instruction));
  92       br = isannulled (pc_instruction, pc, &target);
  93       brknpc4 = brktrg = 0;
  94
  95       if (br == bicca)
  96         {
  97           /* Conditional annulled branch will either end up at
  98              npc (if taken) or at npc+4 (if not taken).
  99              Trap npc+4.  */
 100           brknpc4 = 1;
 101           target_insert_breakpoint (npc4, break_mem[1]);
 102         }
 103       else if (br == baa && target != next_pc)
 104         {
 105           /* Unconditional annulled branch will always end up at
 106              the target.  */
 107           brktrg = 1;
 108           target_insert_breakpoint (target, break_mem[2]);
 109         }
 110
 111       /* Let it go */
 112       ptrace (7, inferior_pid, 1, signal);
 113       one_stepped = 1;
 114       return;
 115     }
 116   else
 117     {
 118       /* Remove breakpoints */
 119       target_remove_breakpoint (next_pc, break_mem[0]);
 120
 121       if (brknpc4)
 122         target_remove_breakpoint (npc4, break_mem[1]);
 123
 124       if (brktrg)
 125         target_remove_breakpoint (target, break_mem[2]);
 126
 127       one_stepped = 0;
 128     }
 129 }
 130 \f
 131 /*
 132  * Find the pc saved in frame FRAME.
 133  */
 134 CORE_ADDR
 135 frame_saved_pc (frame)
 136      FRAME frame;
 137 {
 138   CORE_ADDR prev_pc;
 139
 140   /* If it's at the bottom, the return value's stored in i7/rp */
 141   if (get_current_frame () == frame)
 142     prev_pc = GET_RWINDOW_REG (read_register (SP_REGNUM), rw_in[7]);
 143   else
 144     /* Wouldn't this always work?  This would allow this routine to
 145        be completely a macro.  */
 146     prev_pc = GET_RWINDOW_REG (frame->bottom, rw_in[7]);
 147
 148   return PC_ADJUST (prev_pc);
 149 }
 150
 151 /*
 152  * Since an individual frame in the frame cache is defined by two
 153  * arguments (a frame pointer and a stack pointer), we need two
 154  * arguments to get info for an arbitrary stack frame.  This routine
 155  * takes two arguments and makes the cached frames look as if these
 156  * two arguments defined a frame on the cache.  This allows the rest
 157  * of info frame to extract the important arguments without
 158  * difficulty.
 159  */
 160 FRAME
 161 setup_arbitrary_frame (frame, stack)
 162      FRAME_ADDR frame, stack;
 163 {
 164   FRAME fid = create_new_frame (frame, 0);
 165
 166   if (!fid)
 167     fatal ("internal: create_new_frame returned invalid frame id");
 168
 169   fid->bottom = stack;
 170
 171   return fid;
 172 }
 173
 174 /* This code was written by Gary Beihl (beihl@mcc.com).
 175    It was modified by Michael Tiemann (tiemann@corto.inria.fr).  */
 176
 177 /*
 178  * This routine appears to be passed a size by which to increase the
 179  * stack.  It then executes a save instruction in the inferior to
 180  * increase the stack by this amount.  Only the register window system
 181  * should be affected by this; the program counter & etc. will not be.
 182  *
 183  * This instructions used for this purpose are:
 184  *
 185  *      sethi %hi(0x0),g1                    *
 186  *      add g1,0x1ee0,g1                     *
 187  *      save sp,g1,sp
 188  *      sethi %hi(0x0),g1                    *
 189  *      add g1,0x1ee0,g1                     *
 190  *      t g0,0x1,o0
 191  *      sethi %hi(0x0),g0                    (nop)
 192  *
 193  *  I presume that these set g1 to be the negative of the size, do a
 194  * save (putting the stack pointer at sp - size) and restore the
 195  * original contents of g1.  A * indicates that the actual value of
 196  * the instruction is modified below.
 197  */
 198 static int save_insn_opcodes[] = {
 199   0x03000000, 0x82007ee0, 0x9de38001, 0x03000000,
 200   0x82007ee0, 0x91d02001, 0x01000000 };
 201
 202 /* Neither do_save_insn or do_restore_insn save stack configuration
 203    (current_frame, etc),
 204    since the stack is in an indeterminate state through the call to
 205    each of them.  That responsibility of the routine which calls them.  */
 206
 207 static void
 208 do_save_insn (size)
 209      int size;
 210 {
 211   int g1 = read_register (G1_REGNUM);
 212   CORE_ADDR sp = read_register (SP_REGNUM);
 213   CORE_ADDR pc = read_register (PC_REGNUM);
 214   CORE_ADDR npc = read_register (NPC_REGNUM);
 215   CORE_ADDR fake_pc = sp - sizeof (save_insn_opcodes);
 216   struct inferior_status inf_status;
 217
 218   save_inferior_status (&inf_status, 0); /* Don't restore stack info */
 219   /*
 220    * See above.
 221    */
 222   save_insn_opcodes[0] = 0x03000000 | ((-size >> 10) & 0x3fffff);
 223   save_insn_opcodes[1] = 0x82006000 | (-size & 0x3ff);
 224   save_insn_opcodes[3] = 0x03000000 | ((g1 >> 10) & 0x3fffff);
 225   save_insn_opcodes[4] = 0x82006000 | (g1 & 0x3ff);
 226   write_memory (fake_pc, (char *)save_insn_opcodes, sizeof (save_insn_opcodes));
 227
 228   clear_proceed_status ();
 229   stop_after_trap = 1;
 230   proceed (fake_pc, 0, 0);
 231
 232   write_register (PC_REGNUM, pc);
 233   write_register (NPC_REGNUM, npc);
 234   restore_inferior_status (&inf_status);
 235 }
 236
 237 /*
 238  * This routine takes a program counter value.  It restores the
 239  * register window system to the frame above the current one.
 240  * THIS ROUTINE CLOBBERS PC AND NPC IN THE TARGET!
 241  */
 242
 243 /*    The following insns translate to:
 244
 245         restore %g0,%g0,%g0
 246         t %g0,1
 247         sethi %hi(0),%g0        */
 248
 249 static int restore_insn_opcodes[] = { 0x81e80000, 0x91d02001, 0x01000000 };
 250
 251 static void
 252 do_restore_insn ()
 253 {
 254   CORE_ADDR sp = read_register (SP_REGNUM);
 255   CORE_ADDR fake_pc = sp - sizeof (restore_insn_opcodes);
 256   struct inferior_status inf_status;
 257
 258   save_inferior_status (&inf_status, 0); /* Don't restore stack info */
 259
 260   write_memory (fake_pc, (char *)restore_insn_opcodes,
 261                 sizeof (restore_insn_opcodes));
 262
 263   clear_proceed_status ();
 264   stop_after_trap = 1;
 265   proceed (fake_pc, 0, 0);
 266
 267   restore_inferior_status (&inf_status);
 268 }
 269
 270 /* This routine should be more specific in it's actions; making sure
 271    that it uses the same register in the initial prologue section.  */
 272 CORE_ADDR
 273 skip_prologue (start_pc)
 274      CORE_ADDR start_pc;
 275 {
 276   union
 277     {
 278       unsigned long int code;
 279       struct
 280         {
 281           unsigned int op:2;
 282           unsigned int rd:5;
 283           unsigned int op2:3;
 284           unsigned int imm22:22;
 285         } sethi;
 286       struct
 287         {
 288           unsigned int op:2;
 289           unsigned int rd:5;
 290           unsigned int op3:6;
 291           unsigned int rs1:5;
 292           unsigned int i:1;
 293           unsigned int simm13:13;
 294         } add;
 295       int i;
 296     } x;
 297   int dest = -1;
 298   CORE_ADDR pc = start_pc;
 299   /* Have we found a save instruction?  */
 300   int found_save = 0;
 301
 302   x.i = read_memory_integer (pc, 4);
 303
 304   /* Recognize the `sethi' insn and record its destination.  */
 305   if (x.sethi.op == 0 && x.sethi.op2 == 4)
 306     {
 307       dest = x.sethi.rd;
 308       pc += 4;
 309       x.i = read_memory_integer (pc, 4);
 310     }
 311
 312   /* Recognize an add immediate value to register to either %g1 or
 313      the destination register recorded above.  Actually, this might
 314      well recognize several different arithmetic operations.
 315      It doesn't check that rs1 == rd because in theory "sub %g0, 5, %g1"
 316      followed by "save %sp, %g1, %sp" is a valid prologue (Not that
 317      I imagine any compiler really does that, however).  */
 318   if (x.add.op == 2 && x.add.i && (x.add.rd == 1 || x.add.rd == dest))
 319     {
 320       pc += 4;
 321       x.i = read_memory_integer (pc, 4);
 322     }
 323
 324   /* This recognizes any SAVE insn.  But why do the XOR and then
 325      the compare?  That's identical to comparing against 60 (as long
 326      as there isn't any sign extension).  */
 327   if (x.add.op == 2 && (x.add.op3 ^ 32) == 28)
 328     {
 329       found_save = 1;
 330       pc += 4;
 331       x.i = read_memory_integer (pc, 4);
 332     }
 333
 334   /* Now we need to recognize stores into the frame from the input
 335      registers.  This recognizes all non alternate stores of input
 336      register, into a location offset from the frame pointer.  */
 337   while (x.add.op == 3
 338          && (x.add.op3 & 0x3c) == 4 /* Store, non-alternate.  */
 339          && (x.add.rd & 0x18) == 0x18 /* Input register.  */
 340          && x.add.i             /* Immediate mode.  */
 341          && x.add.rs1 == 30     /* Off of frame pointer.  */
 342          /* Into reserved stack space.  */
 343          && x.add.simm13 >= 0x44
 344          && x.add.simm13 < 0x5b)
 345     {
 346       pc += 4;
 347       x.i = read_memory_integer (pc, 4);
 348     }
 349   if (found_save)
 350     return pc;
 351   else
 352     /* Without a save instruction, it's not a prologue.  */
 353     return start_pc;
 354 }
 355
 356 /* Check instruction at ADDR to see if it is an annulled branch.
 357    All other instructions will go to NPC or will trap.
 358    Set *TARGET if we find a canidate branch; set to zero if not. */
 359
 360 branch_type
 361 isannulled (instruction, addr, target)
 362      long instruction;
 363      CORE_ADDR addr, *target;
 364 {
 365   branch_type val = not_branch;
 366   long int offset;              /* Must be signed for sign-extend.  */
 367   union
 368     {
 369       unsigned long int code;
 370       struct
 371         {
 372           unsigned int op:2;
 373           unsigned int a:1;
 374           unsigned int cond:4;
 375           unsigned int op2:3;
 376           unsigned int disp22:22;
 377         } b;
 378     } insn;
 379
 380   *target = 0;
 381   insn.code = instruction;
 382
 383   if (insn.b.op == 0
 384       && (insn.b.op2 == 2 || insn.b.op2 == 6 || insn.b.op2 == 7))
 385     {
 386       if (insn.b.cond == 8)
 387         val = insn.b.a ? baa : ba;
 388       else
 389         val = insn.b.a ? bicca : bicc;
 390       offset = 4 * ((int) (insn.b.disp22 << 10) >> 10);
 391       *target = addr + offset;
 392     }
 393
 394   return val;
 395 }
 396
 397 /* sparc_frame_find_saved_regs ()
 398
 399    Stores, into a struct frame_saved_regs,
 400    the addresses of the saved registers of frame described by FRAME_INFO.
 401    This includes special registers such as pc and fp saved in special
 402    ways in the stack frame.  sp is even more special:
 403    the address we return for it IS the sp for the next frame.
 404
 405    Note that on register window machines, we are currently making the
 406    assumption that window registers are being saved somewhere in the
 407    frame in which they are being used.  If they are stored in an
 408    inferior frame, find_saved_register will break.
 409
 410    On the Sun 4, the only time all registers are saved is when
 411    a dummy frame is involved.  Otherwise, the only saved registers
 412    are the LOCAL and IN registers which are saved as a result
 413    of the "save/restore" opcodes.  This condition is determined
 414    by address rather than by value.
 415
 416    The "pc" is not stored in a frame on the SPARC.  (What is stored
 417    is a return address minus 8.)  sparc_pop_frame knows how to
 418    deal with that.  Other routines might or might not.
 419
 420    See tm-sparc.h (PUSH_FRAME and friends) for CRITICAL information
 421    about how this works.  */
 422
 423 void
 424 sparc_frame_find_saved_regs (fi, saved_regs_addr)
 425      struct frame_info *fi;
 426      struct frame_saved_regs *saved_regs_addr;
 427 {
 428   register int regnum;
 429   FRAME_ADDR frame = read_register (FP_REGNUM);
 430   FRAME fid = FRAME_INFO_ID (fi);
 431
 432   if (!fid)
 433     fatal ("Bad frame info struct in FRAME_FIND_SAVED_REGS");
 434
 435   bzero (saved_regs_addr, sizeof (*saved_regs_addr));
 436
 437   /* Old test.
 438   if (fi->pc >= frame - CALL_DUMMY_LENGTH - 0x140
 439       && fi->pc <= frame) */
 440
 441   if (fi->pc >= (fi->bottom ? fi->bottom :
 442                    read_register (SP_REGNUM))
 443       && fi->pc <= FRAME_FP(fi))
 444     {
 445       /* Dummy frame.  All but the window regs are in there somewhere. */
 446       for (regnum = G1_REGNUM; regnum < G1_REGNUM+7; regnum++)
 447         saved_regs_addr->regs[regnum] =
 448           frame + (regnum - G0_REGNUM) * 4 - 0xa0;
 449       for (regnum = I0_REGNUM; regnum < I0_REGNUM+8; regnum++)
 450         saved_regs_addr->regs[regnum] =
 451           frame + (regnum - I0_REGNUM) * 4 - 0xc0;
 452       for (regnum = FP0_REGNUM; regnum < FP0_REGNUM + 32; regnum++)
 453         saved_regs_addr->regs[regnum] =
 454           frame + (regnum - FP0_REGNUM) * 4 - 0x80;
 455       for (regnum = Y_REGNUM; regnum < NUM_REGS; regnum++)
 456         saved_regs_addr->regs[regnum] =
 457           frame + (regnum - Y_REGNUM) * 4 - 0xe0;
 458       frame = fi->bottom ?
 459         fi->bottom : read_register (SP_REGNUM);
 460     }
 461   else
 462     {
 463       /* Normal frame.  Just Local and In registers */
 464       frame = fi->bottom ?
 465         fi->bottom : read_register (SP_REGNUM);
 466       for (regnum = L0_REGNUM; regnum < L0_REGNUM+16; regnum++)
 467         saved_regs_addr->regs[regnum] = frame + (regnum-L0_REGNUM) * 4;
 468     }
 469   if (fi->next)
 470     {
 471       /* Pull off either the next frame pointer or the stack pointer */
 472       FRAME_ADDR next_next_frame =
 473         (fi->next->bottom ?
 474          fi->next->bottom :
 475          read_register (SP_REGNUM));
 476       for (regnum = O0_REGNUM; regnum < O0_REGNUM+8; regnum++)
 477         saved_regs_addr->regs[regnum] = next_next_frame + regnum * 4;
 478     }
 479   /* Otherwise, whatever we would get from ptrace(GETREGS) is accurate */
 480   saved_regs_addr->regs[SP_REGNUM] = FRAME_FP (fi);
 481 }
 482
 483 /* Push an empty stack frame, and record in it the current PC, regs, etc.
 484
 485    Note that the write's are of registers in the context of the newly
 486    pushed frame.  Thus the the fp*'s, the g*'s, the i*'s, and
 487    the randoms, of the new frame, are being saved.  The locals and outs
 488    are new; they don't need to be saved. The i's and l's of
 489    the last frame were saved by the do_save_insn in the register
 490    file (now on the stack, since a context switch happended imm after).
 491
 492    The return pointer register %i7 does not have
 493    the pc saved into it (return from this frame will be accomplished
 494    by a POP_FRAME).  In fact, we must leave it unclobbered, since we
 495    must preserve it in the calling routine except across call instructions.  */
 496
 497 /* Definitely see tm-sparc.h for more doc of the frame format here.  */
 498
 499 void
 500 sparc_push_dummy_frame ()
 501 {
 502   CORE_ADDR fp;
 503   char register_temp[REGISTER_BYTES];
 504
 505   do_save_insn (0x140); /* FIXME where does this value come from? */
 506   fp = read_register (FP_REGNUM);
 507
 508   read_register_bytes (REGISTER_BYTE (FP0_REGNUM), register_temp, 32 * 4);
 509   write_memory (fp - 0x80, register_temp, 32 * 4);
 510
 511   read_register_bytes (REGISTER_BYTE (G0_REGNUM), register_temp, 8 * 4);
 512   write_memory (fp - 0xa0, register_temp, 8 * 4);
 513
 514   read_register_bytes (REGISTER_BYTE (I0_REGNUM), register_temp, 8 * 4);
 515   write_memory (fp - 0xc0, register_temp, 8 * 4);
 516
 517   /* Y, PS, WIM, TBR, PC, NPC, FPS, CPS regs */
 518   read_register_bytes (REGISTER_BYTE (Y_REGNUM), register_temp, 8 * 4);
 519   write_memory (fp - 0xe0, register_temp, 8 * 4);
 520 }
 521
 522 /* Discard from the stack the innermost frame, restoring all saved registers.
 523
 524    Note that the values stored in fsr by get_frame_saved_regs are *in
 525    the context of the called frame*.  What this means is that the i
 526    regs of fsr must be restored into the o regs of the (calling) frame that
 527    we pop into.  We don't care about the output regs of the calling frame,
 528    since unless it's a dummy frame, it won't have any output regs in it.
 529
 530    We never have to bother with %l (local) regs, since the called routine's
 531    locals get tossed, and the calling routine's locals are already saved
 532    on its stack.  */
 533
 534 /* Definitely see tm-sparc.h for more doc of the frame format here.  */
 535
 536 void
 537 sparc_pop_frame ()
 538 {
 539   register FRAME frame = get_current_frame ();
 540   register CORE_ADDR pc;
 541   struct frame_saved_regs fsr;
 542   struct frame_info *fi;
 543   char raw_buffer[REGISTER_BYTES];
 544
 545   fi = get_frame_info (frame);
 546   get_frame_saved_regs (fi, &fsr);
 547   do_restore_insn ();
 548   if (fsr.regs[FP0_REGNUM])
 549     {
 550       read_memory (fsr.regs[FP0_REGNUM], raw_buffer, 32 * 4);
 551       write_register_bytes (REGISTER_BYTE (FP0_REGNUM), raw_buffer, 32 * 4);
 552     }
 553   if (fsr.regs[G1_REGNUM])
 554     {
 555       read_memory (fsr.regs[G1_REGNUM], raw_buffer, 7 * 4);
 556       write_register_bytes (REGISTER_BYTE (G1_REGNUM), raw_buffer, 7 * 4);
 557     }
 558   if (fsr.regs[I0_REGNUM])
 559     {
 560       read_memory (fsr.regs[I0_REGNUM], raw_buffer, 8 * 4);
 561       write_register_bytes (REGISTER_BYTE (O0_REGNUM), raw_buffer, 8 * 4);
 562     }
 563   if (fsr.regs[PS_REGNUM])
 564     write_register (PS_REGNUM, read_memory_integer (fsr.regs[PS_REGNUM], 4));
 565   if (fsr.regs[Y_REGNUM])
 566     write_register (Y_REGNUM, read_memory_integer (fsr.regs[Y_REGNUM], 4));
 567   if (fsr.regs[PC_REGNUM])
 568     {
 569       /* Explicitly specified PC (and maybe NPC) -- just restore them. */
 570       write_register (PC_REGNUM, read_memory_integer (fsr.regs[PC_REGNUM], 4));
 571       if (fsr.regs[NPC_REGNUM])
 572         write_register (NPC_REGNUM,
 573                         read_memory_integer (fsr.regs[NPC_REGNUM], 4));
 574     }
 575   else if (fsr.regs[I7_REGNUM])
 576     {
 577       /* Return address in %i7 -- adjust it, then restore PC and NPC from it */
 578       pc = PC_ADJUST (read_memory_integer (fsr.regs[I7_REGNUM], 4));
 579       write_register (PC_REGNUM,  pc);
 580       write_register (NPC_REGNUM, pc + 4);
 581     }
 582   flush_cached_frames ();
 583   set_current_frame ( create_new_frame (read_register (FP_REGNUM),
 584                                         read_pc ()));
 585 }
 586
 587 /* Structure of SPARC extended floating point numbers.
 588    This information is not currently used by GDB, since no current SPARC
 589    implementations support extended float.  */
 590
 591 const struct ext_format ext_format_sparc[] = {
 592 /* tot sbyte smask expbyte manbyte */
 593  { 16, 0,    0x80, 0,1,    4,8  },              /* sparc */
 594 };