1 /* Target-dependent code for the SPARC for GDB, the GNU debugger.
3 Copyright 1986, 1987, 1989, 1990, 1991, 1992, 1993, 1994, 1995,
4 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation,
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
24 /* ??? Support for calling functions from gdb in sparc64 is unfinished. */
27 #include "arch-utils.h"
34 #include "gdb_string.h"
38 #include <sys/procfs.h>
39 /* Prototypes for supply_gregset etc. */
45 #include "symfile.h" /* for 'entry_point_address' */
48 * Some local macros that have multi-arch and non-multi-arch versions:
51 #if (GDB_MULTI_ARCH > 0)
53 /* Does the target have Floating Point registers? */
54 #define SPARC_HAS_FPU (gdbarch_tdep (current_gdbarch)->has_fpu)
55 /* Number of bytes devoted to Floating Point registers: */
56 #define FP_REGISTER_BYTES (gdbarch_tdep (current_gdbarch)->fp_register_bytes)
57 /* Highest numbered Floating Point register. */
58 #define FP_MAX_REGNUM (gdbarch_tdep (current_gdbarch)->fp_max_regnum)
59 /* Size of a general (integer) register: */
60 #define SPARC_INTREG_SIZE (gdbarch_tdep (current_gdbarch)->intreg_size)
61 /* Offset within the call dummy stack of the saved registers. */
62 #define DUMMY_REG_SAVE_OFFSET (gdbarch_tdep (current_gdbarch)->reg_save_offset)
64 #else /* non-multi-arch */
67 /* Does the target have Floating Point registers? */
68 #if defined(TARGET_SPARCLET) || defined(TARGET_SPARCLITE)
69 #define SPARC_HAS_FPU 0
71 #define SPARC_HAS_FPU 1
74 /* Number of bytes devoted to Floating Point registers: */
75 #if (GDB_TARGET_IS_SPARC64)
76 #define FP_REGISTER_BYTES (64 * 4)
79 #define FP_REGISTER_BYTES (32 * 4)
81 #define FP_REGISTER_BYTES 0
85 /* Highest numbered Floating Point register. */
86 #if (GDB_TARGET_IS_SPARC64)
87 #define FP_MAX_REGNUM (FP0_REGNUM + 48)
89 #define FP_MAX_REGNUM (FP0_REGNUM + 32)
92 /* Size of a general (integer) register: */
93 #define SPARC_INTREG_SIZE (REGISTER_RAW_SIZE (G0_REGNUM))
95 /* Offset within the call dummy stack of the saved registers. */
96 #if (GDB_TARGET_IS_SPARC64)
97 #define DUMMY_REG_SAVE_OFFSET (128 + 16)
99 #define DUMMY_REG_SAVE_OFFSET 0x60
102 #endif /* GDB_MULTI_ARCH */
107 int fp_register_bytes
;
112 int call_dummy_call_offset
;
116 /* Now make GDB_TARGET_IS_SPARC64 a runtime test. */
117 /* FIXME MVS: or try testing bfd_arch_info.arch and bfd_arch_info.mach ...
118 * define GDB_TARGET_IS_SPARC64 \
119 * (TARGET_ARCHITECTURE->arch == bfd_arch_sparc && \
120 * (TARGET_ARCHITECTURE->mach == bfd_mach_sparc_v9 || \
121 * TARGET_ARCHITECTURE->mach == bfd_mach_sparc_v9a))
125 extern int stop_after_trap
;
127 /* We don't store all registers immediately when requested, since they
128 get sent over in large chunks anyway. Instead, we accumulate most
129 of the changes and send them over once. "deferred_stores" keeps
130 track of which sets of registers we have locally-changed copies of,
131 so we only need send the groups that have changed. */
133 int deferred_stores
= 0; /* Accumulated stores we want to do eventually. */
136 /* Some machines, such as Fujitsu SPARClite 86x, have a bi-endian mode
137 where instructions are big-endian and data are little-endian.
138 This flag is set when we detect that the target is of this type. */
143 /* Fetch a single instruction. Even on bi-endian machines
144 such as sparc86x, instructions are always big-endian. */
147 fetch_instruction (CORE_ADDR pc
)
149 unsigned long retval
;
151 unsigned char buf
[4];
153 read_memory (pc
, buf
, sizeof (buf
));
155 /* Start at the most significant end of the integer, and work towards
156 the least significant. */
158 for (i
= 0; i
< sizeof (buf
); ++i
)
159 retval
= (retval
<< 8) | buf
[i
];
164 /* Branches with prediction are treated like their non-predicting cousins. */
165 /* FIXME: What about floating point branches? */
167 /* Macros to extract fields from sparc instructions. */
168 #define X_OP(i) (((i) >> 30) & 0x3)
169 #define X_RD(i) (((i) >> 25) & 0x1f)
170 #define X_A(i) (((i) >> 29) & 1)
171 #define X_COND(i) (((i) >> 25) & 0xf)
172 #define X_OP2(i) (((i) >> 22) & 0x7)
173 #define X_IMM22(i) ((i) & 0x3fffff)
174 #define X_OP3(i) (((i) >> 19) & 0x3f)
175 #define X_RS1(i) (((i) >> 14) & 0x1f)
176 #define X_I(i) (((i) >> 13) & 1)
177 #define X_IMM13(i) ((i) & 0x1fff)
178 /* Sign extension macros. */
179 #define X_SIMM13(i) ((X_IMM13 (i) ^ 0x1000) - 0x1000)
180 #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000)
181 #define X_CC(i) (((i) >> 20) & 3)
182 #define X_P(i) (((i) >> 19) & 1)
183 #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000)
184 #define X_RCOND(i) (((i) >> 25) & 7)
185 #define X_DISP16(i) ((((((i) >> 6) && 0xc000) | ((i) & 0x3fff)) ^ 0x8000) - 0x8000)
186 #define X_FCN(i) (((i) >> 25) & 31)
190 Error
, not_branch
, bicc
, bicca
, ba
, baa
, ticc
, ta
, done_retry
193 /* Simulate single-step ptrace call for sun4. Code written by Gary
194 Beihl (beihl@mcc.com). */
196 /* npc4 and next_pc describe the situation at the time that the
197 step-breakpoint was set, not necessary the current value of NPC_REGNUM. */
198 static CORE_ADDR next_pc
, npc4
, target
;
199 static int brknpc4
, brktrg
;
200 typedef char binsn_quantum
[BREAKPOINT_MAX
];
201 static binsn_quantum break_mem
[3];
203 static branch_type
isbranch (long, CORE_ADDR
, CORE_ADDR
*);
205 /* single_step() is called just before we want to resume the inferior,
206 if we want to single-step it but there is no hardware or kernel single-step
207 support (as on all SPARCs). We find all the possible targets of the
208 coming instruction and breakpoint them.
210 single_step is also called just after the inferior stops. If we had
211 set up a simulated single-step, we undo our damage. */
214 sparc_software_single_step (enum target_signal ignore
, /* pid, but we don't need it */
215 int insert_breakpoints_p
)
221 if (insert_breakpoints_p
)
223 /* Always set breakpoint for NPC. */
224 next_pc
= read_register (NPC_REGNUM
);
225 npc4
= next_pc
+ 4; /* branch not taken */
227 target_insert_breakpoint (next_pc
, break_mem
[0]);
228 /* printf_unfiltered ("set break at %x\n",next_pc); */
230 pc
= read_register (PC_REGNUM
);
231 pc_instruction
= fetch_instruction (pc
);
232 br
= isbranch (pc_instruction
, pc
, &target
);
233 brknpc4
= brktrg
= 0;
237 /* Conditional annulled branch will either end up at
238 npc (if taken) or at npc+4 (if not taken).
241 target_insert_breakpoint (npc4
, break_mem
[1]);
243 else if (br
== baa
&& target
!= next_pc
)
245 /* Unconditional annulled branch will always end up at
248 target_insert_breakpoint (target
, break_mem
[2]);
250 else if (GDB_TARGET_IS_SPARC64
&& br
== done_retry
)
253 target_insert_breakpoint (target
, break_mem
[2]);
258 /* Remove breakpoints */
259 target_remove_breakpoint (next_pc
, break_mem
[0]);
262 target_remove_breakpoint (npc4
, break_mem
[1]);
265 target_remove_breakpoint (target
, break_mem
[2]);
269 struct frame_extra_info
274 /* Following fields only relevant for flat frames. */
277 /* Add this to ->frame to get the value of the stack pointer at the
278 time of the register saves. */
282 /* Call this for each newly created frame. For SPARC, we need to
283 calculate the bottom of the frame, and do some extra work if the
284 prologue has been generated via the -mflat option to GCC. In
285 particular, we need to know where the previous fp and the pc have
286 been stashed, since their exact position within the frame may vary. */
289 sparc_init_extra_frame_info (int fromleaf
, struct frame_info
*fi
)
292 CORE_ADDR prologue_start
, prologue_end
;
295 fi
->extra_info
= (struct frame_extra_info
*)
296 frame_obstack_alloc (sizeof (struct frame_extra_info
));
297 frame_saved_regs_zalloc (fi
);
299 fi
->extra_info
->bottom
=
301 (fi
->frame
== fi
->next
->frame
? fi
->next
->extra_info
->bottom
:
302 fi
->next
->frame
) : read_sp ());
304 /* If fi->next is NULL, then we already set ->frame by passing read_fp()
305 to create_new_frame. */
310 buf
= alloca (MAX_REGISTER_RAW_SIZE
);
312 /* Compute ->frame as if not flat. If it is flat, we'll change
314 if (fi
->next
->next
!= NULL
315 && (fi
->next
->next
->signal_handler_caller
316 || frame_in_dummy (fi
->next
->next
))
317 && frameless_look_for_prologue (fi
->next
))
319 /* A frameless function interrupted by a signal did not change
320 the frame pointer, fix up frame pointer accordingly. */
321 fi
->frame
= FRAME_FP (fi
->next
);
322 fi
->extra_info
->bottom
= fi
->next
->extra_info
->bottom
;
326 /* Should we adjust for stack bias here? */
327 get_saved_register (buf
, 0, 0, fi
, FP_REGNUM
, 0);
328 fi
->frame
= extract_address (buf
, REGISTER_RAW_SIZE (FP_REGNUM
));
330 if (GDB_TARGET_IS_SPARC64
&& (fi
->frame
& 1))
335 /* Decide whether this is a function with a ``flat register window''
336 frame. For such functions, the frame pointer is actually in %i7. */
337 fi
->extra_info
->flat
= 0;
338 fi
->extra_info
->in_prologue
= 0;
339 if (find_pc_partial_function (fi
->pc
, &name
, &prologue_start
, &prologue_end
))
341 /* See if the function starts with an add (which will be of a
342 negative number if a flat frame) to the sp. FIXME: Does not
343 handle large frames which will need more than one instruction
345 insn
= fetch_instruction (prologue_start
);
346 if (X_OP (insn
) == 2 && X_RD (insn
) == 14 && X_OP3 (insn
) == 0
347 && X_I (insn
) && X_SIMM13 (insn
) < 0)
349 int offset
= X_SIMM13 (insn
);
351 /* Then look for a save of %i7 into the frame. */
352 insn
= fetch_instruction (prologue_start
+ 4);
356 && X_RS1 (insn
) == 14)
360 buf
= alloca (MAX_REGISTER_RAW_SIZE
);
362 /* We definitely have a flat frame now. */
363 fi
->extra_info
->flat
= 1;
365 fi
->extra_info
->sp_offset
= offset
;
367 /* Overwrite the frame's address with the value in %i7. */
368 get_saved_register (buf
, 0, 0, fi
, I7_REGNUM
, 0);
369 fi
->frame
= extract_address (buf
, REGISTER_RAW_SIZE (I7_REGNUM
));
371 if (GDB_TARGET_IS_SPARC64
&& (fi
->frame
& 1))
374 /* Record where the fp got saved. */
375 fi
->extra_info
->fp_addr
=
376 fi
->frame
+ fi
->extra_info
->sp_offset
+ X_SIMM13 (insn
);
378 /* Also try to collect where the pc got saved to. */
379 fi
->extra_info
->pc_addr
= 0;
380 insn
= fetch_instruction (prologue_start
+ 12);
384 && X_RS1 (insn
) == 14)
385 fi
->extra_info
->pc_addr
=
386 fi
->frame
+ fi
->extra_info
->sp_offset
+ X_SIMM13 (insn
);
391 /* Check if the PC is in the function prologue before a SAVE
392 instruction has been executed yet. If so, set the frame
393 to the current value of the stack pointer and set
394 the in_prologue flag. */
396 struct symtab_and_line sal
;
398 sal
= find_pc_line (prologue_start
, 0);
399 if (sal
.line
== 0) /* no line info, use PC */
400 prologue_end
= fi
->pc
;
401 else if (sal
.end
< prologue_end
)
402 prologue_end
= sal
.end
;
403 if (fi
->pc
< prologue_end
)
405 for (addr
= prologue_start
; addr
< fi
->pc
; addr
+= 4)
407 insn
= read_memory_integer (addr
, 4);
408 if (X_OP (insn
) == 2 && X_OP3 (insn
) == 0x3c)
409 break; /* SAVE seen, stop searching */
413 fi
->extra_info
->in_prologue
= 1;
414 fi
->frame
= read_register (SP_REGNUM
);
419 if (fi
->next
&& fi
->frame
== 0)
421 /* Kludge to cause init_prev_frame_info to destroy the new frame. */
422 fi
->frame
= fi
->next
->frame
;
423 fi
->pc
= fi
->next
->pc
;
428 sparc_frame_chain (struct frame_info
*frame
)
430 /* Value that will cause FRAME_CHAIN_VALID to not worry about the chain
431 value. If it really is zero, we detect it later in
432 sparc_init_prev_frame. */
433 return (CORE_ADDR
) 1;
437 sparc_extract_struct_value_address (char *regbuf
)
439 return extract_address (regbuf
+ REGISTER_BYTE (O0_REGNUM
),
440 REGISTER_RAW_SIZE (O0_REGNUM
));
443 /* Find the pc saved in frame FRAME. */
446 sparc_frame_saved_pc (struct frame_info
*frame
)
451 buf
= alloca (MAX_REGISTER_RAW_SIZE
);
452 if (frame
->signal_handler_caller
)
454 /* This is the signal trampoline frame.
455 Get the saved PC from the sigcontext structure. */
457 #ifndef SIGCONTEXT_PC_OFFSET
458 #define SIGCONTEXT_PC_OFFSET 12
461 CORE_ADDR sigcontext_addr
;
463 int saved_pc_offset
= SIGCONTEXT_PC_OFFSET
;
466 scbuf
= alloca (TARGET_PTR_BIT
/ HOST_CHAR_BIT
);
468 /* Solaris2 ucbsigvechandler passes a pointer to a sigcontext
469 as the third parameter. The offset to the saved pc is 12. */
470 find_pc_partial_function (frame
->pc
, &name
,
471 (CORE_ADDR
*) NULL
, (CORE_ADDR
*) NULL
);
472 if (name
&& STREQ (name
, "ucbsigvechandler"))
473 saved_pc_offset
= 12;
475 /* The sigcontext address is contained in register O2. */
476 get_saved_register (buf
, (int *) NULL
, (CORE_ADDR
*) NULL
,
477 frame
, O0_REGNUM
+ 2, (enum lval_type
*) NULL
);
478 sigcontext_addr
= extract_address (buf
, REGISTER_RAW_SIZE (O0_REGNUM
+ 2));
480 /* Don't cause a memory_error when accessing sigcontext in case the
481 stack layout has changed or the stack is corrupt. */
482 target_read_memory (sigcontext_addr
+ saved_pc_offset
,
483 scbuf
, sizeof (scbuf
));
484 return extract_address (scbuf
, sizeof (scbuf
));
486 else if (frame
->extra_info
->in_prologue
||
487 (frame
->next
!= NULL
&&
488 (frame
->next
->signal_handler_caller
||
489 frame_in_dummy (frame
->next
)) &&
490 frameless_look_for_prologue (frame
)))
492 /* A frameless function interrupted by a signal did not save
493 the PC, it is still in %o7. */
494 get_saved_register (buf
, (int *) NULL
, (CORE_ADDR
*) NULL
,
495 frame
, O7_REGNUM
, (enum lval_type
*) NULL
);
496 return PC_ADJUST (extract_address (buf
, SPARC_INTREG_SIZE
));
498 if (frame
->extra_info
->flat
)
499 addr
= frame
->extra_info
->pc_addr
;
501 addr
= frame
->extra_info
->bottom
+ FRAME_SAVED_I0
+
502 SPARC_INTREG_SIZE
* (I7_REGNUM
- I0_REGNUM
);
505 /* A flat frame leaf function might not save the PC anywhere,
506 just leave it in %o7. */
507 return PC_ADJUST (read_register (O7_REGNUM
));
509 read_memory (addr
, buf
, SPARC_INTREG_SIZE
);
510 return PC_ADJUST (extract_address (buf
, SPARC_INTREG_SIZE
));
513 /* Since an individual frame in the frame cache is defined by two
514 arguments (a frame pointer and a stack pointer), we need two
515 arguments to get info for an arbitrary stack frame. This routine
516 takes two arguments and makes the cached frames look as if these
517 two arguments defined a frame on the cache. This allows the rest
518 of info frame to extract the important arguments without
522 setup_arbitrary_frame (int argc
, CORE_ADDR
*argv
)
524 struct frame_info
*frame
;
527 error ("Sparc frame specifications require two arguments: fp and sp");
529 frame
= create_new_frame (argv
[0], 0);
532 internal_error (__FILE__
, __LINE__
,
533 "create_new_frame returned invalid frame");
535 frame
->extra_info
->bottom
= argv
[1];
536 frame
->pc
= FRAME_SAVED_PC (frame
);
540 /* Given a pc value, skip it forward past the function prologue by
541 disassembling instructions that appear to be a prologue.
543 If FRAMELESS_P is set, we are only testing to see if the function
544 is frameless. This allows a quicker answer.
546 This routine should be more specific in its actions; making sure
547 that it uses the same register in the initial prologue section. */
549 static CORE_ADDR
examine_prologue (CORE_ADDR
, int, struct frame_info
*,
553 examine_prologue (CORE_ADDR start_pc
, int frameless_p
, struct frame_info
*fi
,
554 CORE_ADDR
*saved_regs
)
558 CORE_ADDR pc
= start_pc
;
561 insn
= fetch_instruction (pc
);
563 /* Recognize the `sethi' insn and record its destination. */
564 if (X_OP (insn
) == 0 && X_OP2 (insn
) == 4)
568 insn
= fetch_instruction (pc
);
571 /* Recognize an add immediate value to register to either %g1 or
572 the destination register recorded above. Actually, this might
573 well recognize several different arithmetic operations.
574 It doesn't check that rs1 == rd because in theory "sub %g0, 5, %g1"
575 followed by "save %sp, %g1, %sp" is a valid prologue (Not that
576 I imagine any compiler really does that, however). */
579 && (X_RD (insn
) == 1 || X_RD (insn
) == dest
))
582 insn
= fetch_instruction (pc
);
585 /* Recognize any SAVE insn. */
586 if (X_OP (insn
) == 2 && X_OP3 (insn
) == 60)
589 if (frameless_p
) /* If the save is all we care about, */
590 return pc
; /* return before doing more work */
591 insn
= fetch_instruction (pc
);
593 /* Recognize add to %sp. */
594 else if (X_OP (insn
) == 2 && X_RD (insn
) == 14 && X_OP3 (insn
) == 0)
597 if (frameless_p
) /* If the add is all we care about, */
598 return pc
; /* return before doing more work */
600 insn
= fetch_instruction (pc
);
601 /* Recognize store of frame pointer (i7). */
605 && X_RS1 (insn
) == 14)
608 insn
= fetch_instruction (pc
);
610 /* Recognize sub %sp, <anything>, %i7. */
613 && X_RS1 (insn
) == 14
614 && X_RD (insn
) == 31)
617 insn
= fetch_instruction (pc
);
626 /* Without a save or add instruction, it's not a prologue. */
631 /* Recognize stores into the frame from the input registers.
632 This recognizes all non alternate stores of an input register,
633 into a location offset from the frame pointer between
636 /* The above will fail for arguments that are promoted
637 (eg. shorts to ints or floats to doubles), because the compiler
638 will pass them in positive-offset frame space, but the prologue
639 will save them (after conversion) in negative frame space at an
640 unpredictable offset. Therefore I am going to remove the
641 restriction on the target-address of the save, on the theory
642 that any unbroken sequence of saves from input registers must
643 be part of the prologue. In un-optimized code (at least), I'm
644 fairly sure that the compiler would emit SOME other instruction
645 (eg. a move or add) before emitting another save that is actually
646 a part of the function body.
648 Besides, the reserved stack space is different for SPARC64 anyway.
653 && (X_OP3 (insn
) & 0x3c) == 4 /* Store, non-alternate. */
654 && (X_RD (insn
) & 0x18) == 0x18 /* Input register. */
655 && X_I (insn
) /* Immediate mode. */
656 && X_RS1 (insn
) == 30) /* Off of frame pointer. */
657 ; /* empty statement -- fall thru to end of loop */
658 else if (GDB_TARGET_IS_SPARC64
660 && (X_OP3 (insn
) & 0x3c) == 12 /* store, extended (64-bit) */
661 && (X_RD (insn
) & 0x18) == 0x18 /* input register */
662 && X_I (insn
) /* immediate mode */
663 && X_RS1 (insn
) == 30) /* off of frame pointer */
664 ; /* empty statement -- fall thru to end of loop */
665 else if (X_OP (insn
) == 3
666 && (X_OP3 (insn
) & 0x3c) == 36 /* store, floating-point */
667 && X_I (insn
) /* immediate mode */
668 && X_RS1 (insn
) == 30) /* off of frame pointer */
669 ; /* empty statement -- fall thru to end of loop */
672 && X_OP3 (insn
) == 4 /* store? */
673 && X_RS1 (insn
) == 14) /* off of frame pointer */
675 if (saved_regs
&& X_I (insn
))
676 saved_regs
[X_RD (insn
)] =
677 fi
->frame
+ fi
->extra_info
->sp_offset
+ X_SIMM13 (insn
);
682 insn
= fetch_instruction (pc
);
688 /* Advance PC across any function entry prologue instructions to reach
692 sparc_skip_prologue (CORE_ADDR start_pc
)
694 struct symtab_and_line sal
;
695 CORE_ADDR func_start
, func_end
;
697 /* This is the preferred method, find the end of the prologue by
698 using the debugging information. */
699 if (find_pc_partial_function (start_pc
, NULL
, &func_start
, &func_end
))
701 sal
= find_pc_line (func_start
, 0);
703 if (sal
.end
< func_end
704 && start_pc
<= sal
.end
)
708 /* Oh well, examine the code by hand. */
709 return examine_prologue (start_pc
, 0, NULL
, NULL
);
712 /* Is the prologue at IP frameless? */
715 sparc_prologue_frameless_p (CORE_ADDR ip
)
717 return ip
== examine_prologue (ip
, 1, NULL
, NULL
);
720 /* Check instruction at ADDR to see if it is a branch.
721 All non-annulled instructions will go to NPC or will trap.
722 Set *TARGET if we find a candidate branch; set to zero if not.
724 This isn't static as it's used by remote-sa.sparc.c. */
727 isbranch (long instruction
, CORE_ADDR addr
, CORE_ADDR
*target
)
729 branch_type val
= not_branch
;
730 long int offset
= 0; /* Must be signed for sign-extend. */
734 if (X_OP (instruction
) == 0
735 && (X_OP2 (instruction
) == 2
736 || X_OP2 (instruction
) == 6
737 || X_OP2 (instruction
) == 1
738 || X_OP2 (instruction
) == 3
739 || X_OP2 (instruction
) == 5
740 || (GDB_TARGET_IS_SPARC64
&& X_OP2 (instruction
) == 7)))
742 if (X_COND (instruction
) == 8)
743 val
= X_A (instruction
) ? baa
: ba
;
745 val
= X_A (instruction
) ? bicca
: bicc
;
746 switch (X_OP2 (instruction
))
749 if (!GDB_TARGET_IS_SPARC64
)
754 offset
= 4 * X_DISP22 (instruction
);
758 offset
= 4 * X_DISP19 (instruction
);
761 offset
= 4 * X_DISP16 (instruction
);
764 *target
= addr
+ offset
;
766 else if (GDB_TARGET_IS_SPARC64
767 && X_OP (instruction
) == 2
768 && X_OP3 (instruction
) == 62)
770 if (X_FCN (instruction
) == 0)
773 *target
= read_register (TNPC_REGNUM
);
776 else if (X_FCN (instruction
) == 1)
779 *target
= read_register (TPC_REGNUM
);
787 /* Find register number REGNUM relative to FRAME and put its
788 (raw) contents in *RAW_BUFFER. Set *OPTIMIZED if the variable
789 was optimized out (and thus can't be fetched). If the variable
790 was fetched from memory, set *ADDRP to where it was fetched from,
791 otherwise it was fetched from a register.
793 The argument RAW_BUFFER must point to aligned memory. */
796 sparc_get_saved_register (char *raw_buffer
, int *optimized
, CORE_ADDR
*addrp
,
797 struct frame_info
*frame
, int regnum
,
798 enum lval_type
*lval
)
800 struct frame_info
*frame1
;
803 if (!target_has_registers
)
804 error ("No registers.");
811 /* FIXME This code extracted from infcmd.c; should put elsewhere! */
814 /* error ("No selected frame."); */
815 if (!target_has_registers
)
816 error ("The program has no registers now.");
817 if (selected_frame
== NULL
)
818 error ("No selected frame.");
819 /* Try to use selected frame */
820 frame
= get_prev_frame (selected_frame
);
822 error ("Cmd not meaningful in the outermost frame.");
826 frame1
= frame
->next
;
828 /* Get saved PC from the frame info if not in innermost frame. */
829 if (regnum
== PC_REGNUM
&& frame1
!= NULL
)
833 if (raw_buffer
!= NULL
)
835 /* Put it back in target format. */
836 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
), frame
->pc
);
843 while (frame1
!= NULL
)
845 /* FIXME MVS: wrong test for dummy frame at entry. */
847 if (frame1
->pc
>= (frame1
->extra_info
->bottom
?
848 frame1
->extra_info
->bottom
: read_sp ())
849 && frame1
->pc
<= FRAME_FP (frame1
))
851 /* Dummy frame. All but the window regs are in there somewhere.
852 The window registers are saved on the stack, just like in a
854 if (regnum
>= G1_REGNUM
&& regnum
< G1_REGNUM
+ 7)
855 addr
= frame1
->frame
+ (regnum
- G0_REGNUM
) * SPARC_INTREG_SIZE
856 - (FP_REGISTER_BYTES
+ 8 * SPARC_INTREG_SIZE
);
857 else if (regnum
>= I0_REGNUM
&& regnum
< I0_REGNUM
+ 8)
858 addr
= (get_prev_frame (frame1
)->extra_info
->bottom
859 + (regnum
- I0_REGNUM
) * SPARC_INTREG_SIZE
861 else if (regnum
>= L0_REGNUM
&& regnum
< L0_REGNUM
+ 8)
862 addr
= (get_prev_frame (frame1
)->extra_info
->bottom
863 + (regnum
- L0_REGNUM
) * SPARC_INTREG_SIZE
865 else if (regnum
>= O0_REGNUM
&& regnum
< O0_REGNUM
+ 8)
866 addr
= frame1
->frame
+ (regnum
- O0_REGNUM
) * SPARC_INTREG_SIZE
867 - (FP_REGISTER_BYTES
+ 16 * SPARC_INTREG_SIZE
);
868 else if (SPARC_HAS_FPU
&&
869 regnum
>= FP0_REGNUM
&& regnum
< FP0_REGNUM
+ 32)
870 addr
= frame1
->frame
+ (regnum
- FP0_REGNUM
) * 4
871 - (FP_REGISTER_BYTES
);
872 else if (GDB_TARGET_IS_SPARC64
&& SPARC_HAS_FPU
&&
873 regnum
>= FP0_REGNUM
+ 32 && regnum
< FP_MAX_REGNUM
)
874 addr
= frame1
->frame
+ 32 * 4 + (regnum
- FP0_REGNUM
- 32) * 8
875 - (FP_REGISTER_BYTES
);
876 else if (regnum
>= Y_REGNUM
&& regnum
< NUM_REGS
)
877 addr
= frame1
->frame
+ (regnum
- Y_REGNUM
) * SPARC_INTREG_SIZE
878 - (FP_REGISTER_BYTES
+ 24 * SPARC_INTREG_SIZE
);
880 else if (frame1
->extra_info
->flat
)
883 if (regnum
== RP_REGNUM
)
884 addr
= frame1
->extra_info
->pc_addr
;
885 else if (regnum
== I7_REGNUM
)
886 addr
= frame1
->extra_info
->fp_addr
;
889 CORE_ADDR func_start
;
892 regs
= alloca (NUM_REGS
* sizeof (CORE_ADDR
));
893 memset (regs
, 0, NUM_REGS
* sizeof (CORE_ADDR
));
895 find_pc_partial_function (frame1
->pc
, NULL
, &func_start
, NULL
);
896 examine_prologue (func_start
, 0, frame1
, regs
);
902 /* Normal frame. Local and In registers are saved on stack. */
903 if (regnum
>= I0_REGNUM
&& regnum
< I0_REGNUM
+ 8)
904 addr
= (get_prev_frame (frame1
)->extra_info
->bottom
905 + (regnum
- I0_REGNUM
) * SPARC_INTREG_SIZE
907 else if (regnum
>= L0_REGNUM
&& regnum
< L0_REGNUM
+ 8)
908 addr
= (get_prev_frame (frame1
)->extra_info
->bottom
909 + (regnum
- L0_REGNUM
) * SPARC_INTREG_SIZE
911 else if (regnum
>= O0_REGNUM
&& regnum
< O0_REGNUM
+ 8)
913 /* Outs become ins. */
914 get_saved_register (raw_buffer
, optimized
, addrp
, frame1
,
915 (regnum
- O0_REGNUM
+ I0_REGNUM
), lval
);
921 frame1
= frame1
->next
;
927 if (regnum
== SP_REGNUM
)
929 if (raw_buffer
!= NULL
)
931 /* Put it back in target format. */
932 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
), addr
);
938 if (raw_buffer
!= NULL
)
939 read_memory (addr
, raw_buffer
, REGISTER_RAW_SIZE (regnum
));
944 *lval
= lval_register
;
945 addr
= REGISTER_BYTE (regnum
);
946 if (raw_buffer
!= NULL
)
947 read_register_gen (regnum
, raw_buffer
);
953 /* Push an empty stack frame, and record in it the current PC, regs, etc.
955 We save the non-windowed registers and the ins. The locals and outs
956 are new; they don't need to be saved. The i's and l's of
957 the last frame were already saved on the stack. */
959 /* Definitely see tm-sparc.h for more doc of the frame format here. */
961 /* See tm-sparc.h for how this is calculated. */
963 #define DUMMY_STACK_REG_BUF_SIZE \
964 (((8+8+8) * SPARC_INTREG_SIZE) + FP_REGISTER_BYTES)
965 #define DUMMY_STACK_SIZE \
966 (DUMMY_STACK_REG_BUF_SIZE + DUMMY_REG_SAVE_OFFSET)
969 sparc_push_dummy_frame (void)
971 CORE_ADDR sp
, old_sp
;
974 register_temp
= alloca (DUMMY_STACK_SIZE
);
976 old_sp
= sp
= read_sp ();
978 if (GDB_TARGET_IS_SPARC64
)
980 /* PC, NPC, CCR, FSR, FPRS, Y, ASI */
981 read_register_bytes (REGISTER_BYTE (PC_REGNUM
), ®ister_temp
[0],
982 REGISTER_RAW_SIZE (PC_REGNUM
) * 7);
983 read_register_bytes (REGISTER_BYTE (PSTATE_REGNUM
),
984 ®ister_temp
[7 * SPARC_INTREG_SIZE
],
985 REGISTER_RAW_SIZE (PSTATE_REGNUM
));
986 /* FIXME: not sure what needs to be saved here. */
990 /* Y, PS, WIM, TBR, PC, NPC, FPS, CPS regs */
991 read_register_bytes (REGISTER_BYTE (Y_REGNUM
), ®ister_temp
[0],
992 REGISTER_RAW_SIZE (Y_REGNUM
) * 8);
995 read_register_bytes (REGISTER_BYTE (O0_REGNUM
),
996 ®ister_temp
[8 * SPARC_INTREG_SIZE
],
997 SPARC_INTREG_SIZE
* 8);
999 read_register_bytes (REGISTER_BYTE (G0_REGNUM
),
1000 ®ister_temp
[16 * SPARC_INTREG_SIZE
],
1001 SPARC_INTREG_SIZE
* 8);
1004 read_register_bytes (REGISTER_BYTE (FP0_REGNUM
),
1005 ®ister_temp
[24 * SPARC_INTREG_SIZE
],
1008 sp
-= DUMMY_STACK_SIZE
;
1012 write_memory (sp
+ DUMMY_REG_SAVE_OFFSET
, ®ister_temp
[0],
1013 DUMMY_STACK_REG_BUF_SIZE
);
1015 if (strcmp (target_shortname
, "sim") != 0)
1017 /* NOTE: cagney/2002-04-04: The code below originally contained
1018 GDB's _only_ call to write_fp(). That call was eliminated by
1019 inlining the corresponding code. For the 64 bit case, the
1020 old function (sparc64_write_fp) did the below although I'm
1021 not clear why. The same goes for why this is only done when
1022 the underlying target is a simulator. */
1023 if (GDB_TARGET_IS_SPARC64
)
1025 /* Target is a 64 bit SPARC. */
1026 CORE_ADDR oldfp
= read_register (FP_REGNUM
);
1028 write_register (FP_REGNUM
, old_sp
- 2047);
1030 write_register (FP_REGNUM
, old_sp
);
1034 /* Target is a 32 bit SPARC. */
1035 write_register (FP_REGNUM
, old_sp
);
1037 /* Set return address register for the call dummy to the current PC. */
1038 write_register (I7_REGNUM
, read_pc () - 8);
1042 /* The call dummy will write this value to FP before executing
1043 the 'save'. This ensures that register window flushes work
1044 correctly in the simulator. */
1045 write_register (G0_REGNUM
+ 1, read_register (FP_REGNUM
));
1047 /* The call dummy will write this value to FP after executing
1049 write_register (G0_REGNUM
+ 2, old_sp
);
1051 /* The call dummy will write this value to the return address (%i7) after
1052 executing the 'save'. */
1053 write_register (G0_REGNUM
+ 3, read_pc () - 8);
1055 /* Set the FP that the call dummy will be using after the 'save'.
1056 This makes backtraces from an inferior function call work properly. */
1057 write_register (FP_REGNUM
, old_sp
);
1061 /* sparc_frame_find_saved_regs (). This function is here only because
1062 pop_frame uses it. Note there is an interesting corner case which
1063 I think few ports of GDB get right--if you are popping a frame
1064 which does not save some register that *is* saved by a more inner
1065 frame (such a frame will never be a dummy frame because dummy
1066 frames save all registers). Rewriting pop_frame to use
1067 get_saved_register would solve this problem and also get rid of the
1068 ugly duplication between sparc_frame_find_saved_regs and
1071 Stores, into an array of CORE_ADDR,
1072 the addresses of the saved registers of frame described by FRAME_INFO.
1073 This includes special registers such as pc and fp saved in special
1074 ways in the stack frame. sp is even more special:
1075 the address we return for it IS the sp for the next frame.
1077 Note that on register window machines, we are currently making the
1078 assumption that window registers are being saved somewhere in the
1079 frame in which they are being used. If they are stored in an
1080 inferior frame, find_saved_register will break.
1082 On the Sun 4, the only time all registers are saved is when
1083 a dummy frame is involved. Otherwise, the only saved registers
1084 are the LOCAL and IN registers which are saved as a result
1085 of the "save/restore" opcodes. This condition is determined
1086 by address rather than by value.
1088 The "pc" is not stored in a frame on the SPARC. (What is stored
1089 is a return address minus 8.) sparc_pop_frame knows how to
1090 deal with that. Other routines might or might not.
1092 See tm-sparc.h (PUSH_DUMMY_FRAME and friends) for CRITICAL information
1093 about how this works. */
1095 static void sparc_frame_find_saved_regs (struct frame_info
*, CORE_ADDR
*);
1098 sparc_frame_find_saved_regs (struct frame_info
*fi
, CORE_ADDR
*saved_regs_addr
)
1100 register int regnum
;
1101 CORE_ADDR frame_addr
= FRAME_FP (fi
);
1104 internal_error (__FILE__
, __LINE__
,
1105 "Bad frame info struct in FRAME_FIND_SAVED_REGS");
1107 memset (saved_regs_addr
, 0, NUM_REGS
* sizeof (CORE_ADDR
));
1109 if (fi
->pc
>= (fi
->extra_info
->bottom
?
1110 fi
->extra_info
->bottom
: read_sp ())
1111 && fi
->pc
<= FRAME_FP (fi
))
1113 /* Dummy frame. All but the window regs are in there somewhere. */
1114 for (regnum
= G1_REGNUM
; regnum
< G1_REGNUM
+ 7; regnum
++)
1115 saved_regs_addr
[regnum
] =
1116 frame_addr
+ (regnum
- G0_REGNUM
) * SPARC_INTREG_SIZE
1117 - DUMMY_STACK_REG_BUF_SIZE
+ 16 * SPARC_INTREG_SIZE
;
1119 for (regnum
= I0_REGNUM
; regnum
< I0_REGNUM
+ 8; regnum
++)
1120 saved_regs_addr
[regnum
] =
1121 frame_addr
+ (regnum
- I0_REGNUM
) * SPARC_INTREG_SIZE
1122 - DUMMY_STACK_REG_BUF_SIZE
+ 8 * SPARC_INTREG_SIZE
;
1125 for (regnum
= FP0_REGNUM
; regnum
< FP_MAX_REGNUM
; regnum
++)
1126 saved_regs_addr
[regnum
] = frame_addr
+ (regnum
- FP0_REGNUM
) * 4
1127 - DUMMY_STACK_REG_BUF_SIZE
+ 24 * SPARC_INTREG_SIZE
;
1129 if (GDB_TARGET_IS_SPARC64
)
1131 for (regnum
= PC_REGNUM
; regnum
< PC_REGNUM
+ 7; regnum
++)
1133 saved_regs_addr
[regnum
] =
1134 frame_addr
+ (regnum
- PC_REGNUM
) * SPARC_INTREG_SIZE
1135 - DUMMY_STACK_REG_BUF_SIZE
;
1137 saved_regs_addr
[PSTATE_REGNUM
] =
1138 frame_addr
+ 8 * SPARC_INTREG_SIZE
- DUMMY_STACK_REG_BUF_SIZE
;
1141 for (regnum
= Y_REGNUM
; regnum
< NUM_REGS
; regnum
++)
1142 saved_regs_addr
[regnum
] =
1143 frame_addr
+ (regnum
- Y_REGNUM
) * SPARC_INTREG_SIZE
1144 - DUMMY_STACK_REG_BUF_SIZE
;
1146 frame_addr
= fi
->extra_info
->bottom
?
1147 fi
->extra_info
->bottom
: read_sp ();
1149 else if (fi
->extra_info
->flat
)
1151 CORE_ADDR func_start
;
1152 find_pc_partial_function (fi
->pc
, NULL
, &func_start
, NULL
);
1153 examine_prologue (func_start
, 0, fi
, saved_regs_addr
);
1155 /* Flat register window frame. */
1156 saved_regs_addr
[RP_REGNUM
] = fi
->extra_info
->pc_addr
;
1157 saved_regs_addr
[I7_REGNUM
] = fi
->extra_info
->fp_addr
;
1161 /* Normal frame. Just Local and In registers */
1162 frame_addr
= fi
->extra_info
->bottom
?
1163 fi
->extra_info
->bottom
: read_sp ();
1164 for (regnum
= L0_REGNUM
; regnum
< L0_REGNUM
+ 8; regnum
++)
1165 saved_regs_addr
[regnum
] =
1166 (frame_addr
+ (regnum
- L0_REGNUM
) * SPARC_INTREG_SIZE
1168 for (regnum
= I0_REGNUM
; regnum
< I0_REGNUM
+ 8; regnum
++)
1169 saved_regs_addr
[regnum
] =
1170 (frame_addr
+ (regnum
- I0_REGNUM
) * SPARC_INTREG_SIZE
1175 if (fi
->extra_info
->flat
)
1177 saved_regs_addr
[O7_REGNUM
] = fi
->extra_info
->pc_addr
;
1181 /* Pull off either the next frame pointer or the stack pointer */
1182 CORE_ADDR next_next_frame_addr
=
1183 (fi
->next
->extra_info
->bottom
?
1184 fi
->next
->extra_info
->bottom
: read_sp ());
1185 for (regnum
= O0_REGNUM
; regnum
< O0_REGNUM
+ 8; regnum
++)
1186 saved_regs_addr
[regnum
] =
1187 (next_next_frame_addr
1188 + (regnum
- O0_REGNUM
) * SPARC_INTREG_SIZE
1192 /* Otherwise, whatever we would get from ptrace(GETREGS) is accurate */
1193 /* FIXME -- should this adjust for the sparc64 offset? */
1194 saved_regs_addr
[SP_REGNUM
] = FRAME_FP (fi
);
1197 /* Discard from the stack the innermost frame, restoring all saved registers.
1199 Note that the values stored in fsr by get_frame_saved_regs are *in
1200 the context of the called frame*. What this means is that the i
1201 regs of fsr must be restored into the o regs of the (calling) frame that
1202 we pop into. We don't care about the output regs of the calling frame,
1203 since unless it's a dummy frame, it won't have any output regs in it.
1205 We never have to bother with %l (local) regs, since the called routine's
1206 locals get tossed, and the calling routine's locals are already saved
1209 /* Definitely see tm-sparc.h for more doc of the frame format here. */
1212 sparc_pop_frame (void)
1214 register struct frame_info
*frame
= get_current_frame ();
1215 register CORE_ADDR pc
;
1220 fsr
= alloca (NUM_REGS
* sizeof (CORE_ADDR
));
1221 raw_buffer
= alloca (REGISTER_BYTES
);
1222 sparc_frame_find_saved_regs (frame
, &fsr
[0]);
1225 if (fsr
[FP0_REGNUM
])
1227 read_memory (fsr
[FP0_REGNUM
], raw_buffer
, FP_REGISTER_BYTES
);
1228 write_register_bytes (REGISTER_BYTE (FP0_REGNUM
),
1229 raw_buffer
, FP_REGISTER_BYTES
);
1231 if (!(GDB_TARGET_IS_SPARC64
))
1233 if (fsr
[FPS_REGNUM
])
1235 read_memory (fsr
[FPS_REGNUM
], raw_buffer
, SPARC_INTREG_SIZE
);
1236 write_register_gen (FPS_REGNUM
, raw_buffer
);
1238 if (fsr
[CPS_REGNUM
])
1240 read_memory (fsr
[CPS_REGNUM
], raw_buffer
, SPARC_INTREG_SIZE
);
1241 write_register_gen (CPS_REGNUM
, raw_buffer
);
1247 read_memory (fsr
[G1_REGNUM
], raw_buffer
, 7 * SPARC_INTREG_SIZE
);
1248 write_register_bytes (REGISTER_BYTE (G1_REGNUM
), raw_buffer
,
1249 7 * SPARC_INTREG_SIZE
);
1252 if (frame
->extra_info
->flat
)
1254 /* Each register might or might not have been saved, need to test
1256 for (regnum
= L0_REGNUM
; regnum
< L0_REGNUM
+ 8; ++regnum
)
1258 write_register (regnum
, read_memory_integer (fsr
[regnum
],
1259 SPARC_INTREG_SIZE
));
1260 for (regnum
= I0_REGNUM
; regnum
< I0_REGNUM
+ 8; ++regnum
)
1262 write_register (regnum
, read_memory_integer (fsr
[regnum
],
1263 SPARC_INTREG_SIZE
));
1265 /* Handle all outs except stack pointer (o0-o5; o7). */
1266 for (regnum
= O0_REGNUM
; regnum
< O0_REGNUM
+ 6; ++regnum
)
1268 write_register (regnum
, read_memory_integer (fsr
[regnum
],
1269 SPARC_INTREG_SIZE
));
1270 if (fsr
[O0_REGNUM
+ 7])
1271 write_register (O0_REGNUM
+ 7,
1272 read_memory_integer (fsr
[O0_REGNUM
+ 7],
1273 SPARC_INTREG_SIZE
));
1275 write_sp (frame
->frame
);
1277 else if (fsr
[I0_REGNUM
])
1283 reg_temp
= alloca (SPARC_INTREG_SIZE
* 16);
1285 read_memory (fsr
[I0_REGNUM
], raw_buffer
, 8 * SPARC_INTREG_SIZE
);
1287 /* Get the ins and locals which we are about to restore. Just
1288 moving the stack pointer is all that is really needed, except
1289 store_inferior_registers is then going to write the ins and
1290 locals from the registers array, so we need to muck with the
1292 sp
= fsr
[SP_REGNUM
];
1294 if (GDB_TARGET_IS_SPARC64
&& (sp
& 1))
1297 read_memory (sp
, reg_temp
, SPARC_INTREG_SIZE
* 16);
1299 /* Restore the out registers.
1300 Among other things this writes the new stack pointer. */
1301 write_register_bytes (REGISTER_BYTE (O0_REGNUM
), raw_buffer
,
1302 SPARC_INTREG_SIZE
* 8);
1304 write_register_bytes (REGISTER_BYTE (L0_REGNUM
), reg_temp
,
1305 SPARC_INTREG_SIZE
* 16);
1308 if (!(GDB_TARGET_IS_SPARC64
))
1310 write_register (PS_REGNUM
,
1311 read_memory_integer (fsr
[PS_REGNUM
],
1312 REGISTER_RAW_SIZE (PS_REGNUM
)));
1315 write_register (Y_REGNUM
,
1316 read_memory_integer (fsr
[Y_REGNUM
],
1317 REGISTER_RAW_SIZE (Y_REGNUM
)));
1320 /* Explicitly specified PC (and maybe NPC) -- just restore them. */
1321 write_register (PC_REGNUM
,
1322 read_memory_integer (fsr
[PC_REGNUM
],
1323 REGISTER_RAW_SIZE (PC_REGNUM
)));
1324 if (fsr
[NPC_REGNUM
])
1325 write_register (NPC_REGNUM
,
1326 read_memory_integer (fsr
[NPC_REGNUM
],
1327 REGISTER_RAW_SIZE (NPC_REGNUM
)));
1329 else if (frame
->extra_info
->flat
)
1331 if (frame
->extra_info
->pc_addr
)
1332 pc
= PC_ADJUST ((CORE_ADDR
)
1333 read_memory_integer (frame
->extra_info
->pc_addr
,
1334 REGISTER_RAW_SIZE (PC_REGNUM
)));
1337 /* I think this happens only in the innermost frame, if so then
1338 it is a complicated way of saying
1339 "pc = read_register (O7_REGNUM);". */
1342 buf
= alloca (MAX_REGISTER_RAW_SIZE
);
1343 get_saved_register (buf
, 0, 0, frame
, O7_REGNUM
, 0);
1344 pc
= PC_ADJUST (extract_address
1345 (buf
, REGISTER_RAW_SIZE (O7_REGNUM
)));
1348 write_register (PC_REGNUM
, pc
);
1349 write_register (NPC_REGNUM
, pc
+ 4);
1351 else if (fsr
[I7_REGNUM
])
1353 /* Return address in %i7 -- adjust it, then restore PC and NPC from it */
1354 pc
= PC_ADJUST ((CORE_ADDR
) read_memory_integer (fsr
[I7_REGNUM
],
1355 SPARC_INTREG_SIZE
));
1356 write_register (PC_REGNUM
, pc
);
1357 write_register (NPC_REGNUM
, pc
+ 4);
1359 flush_cached_frames ();
1362 /* On the Sun 4 under SunOS, the compile will leave a fake insn which
1363 encodes the structure size being returned. If we detect such
1364 a fake insn, step past it. */
1367 sparc_pc_adjust (CORE_ADDR pc
)
1373 err
= target_read_memory (pc
+ 8, buf
, 4);
1374 insn
= extract_unsigned_integer (buf
, 4);
1375 if ((err
== 0) && (insn
& 0xffc00000) == 0)
1381 /* If pc is in a shared library trampoline, return its target.
1382 The SunOs 4.x linker rewrites the jump table entries for PIC
1383 compiled modules in the main executable to bypass the dynamic linker
1384 with jumps of the form
1387 and removes the corresponding jump table relocation entry in the
1388 dynamic relocations.
1389 find_solib_trampoline_target relies on the presence of the jump
1390 table relocation entry, so we have to detect these jump instructions
1394 sunos4_skip_trampoline_code (CORE_ADDR pc
)
1396 unsigned long insn1
;
1400 err
= target_read_memory (pc
, buf
, 4);
1401 insn1
= extract_unsigned_integer (buf
, 4);
1402 if (err
== 0 && (insn1
& 0xffc00000) == 0x03000000)
1404 unsigned long insn2
;
1406 err
= target_read_memory (pc
+ 4, buf
, 4);
1407 insn2
= extract_unsigned_integer (buf
, 4);
1408 if (err
== 0 && (insn2
& 0xffffe000) == 0x81c06000)
1410 CORE_ADDR target_pc
= (insn1
& 0x3fffff) << 10;
1411 int delta
= insn2
& 0x1fff;
1413 /* Sign extend the displacement. */
1416 return target_pc
+ delta
;
1419 return find_solib_trampoline_target (pc
);
1422 #ifdef USE_PROC_FS /* Target dependent support for /proc */
1424 /* The /proc interface divides the target machine's register set up into
1425 two different sets, the general register set (gregset) and the floating
1426 point register set (fpregset). For each set, there is an ioctl to get
1427 the current register set and another ioctl to set the current values.
1429 The actual structure passed through the ioctl interface is, of course,
1430 naturally machine dependent, and is different for each set of registers.
1431 For the sparc for example, the general register set is typically defined
1434 typedef int gregset_t[38];
1440 and the floating point set by:
1442 typedef struct prfpregset {
1445 double pr_dregs[16];
1450 u_char pr_q_entrysize;
1455 These routines provide the packing and unpacking of gregset_t and
1456 fpregset_t formatted data.
1461 /* Given a pointer to a general register set in /proc format (gregset_t *),
1462 unpack the register contents and supply them as gdb's idea of the current
1466 supply_gregset (gdb_gregset_t
*gregsetp
)
1468 prgreg_t
*regp
= (prgreg_t
*) gregsetp
;
1469 int regi
, offset
= 0;
1471 /* If the host is 64-bit sparc, but the target is 32-bit sparc,
1472 then the gregset may contain 64-bit ints while supply_register
1473 is expecting 32-bit ints. Compensate. */
1474 if (sizeof (regp
[0]) == 8 && SPARC_INTREG_SIZE
== 4)
1477 /* GDB register numbers for Gn, On, Ln, In all match /proc reg numbers. */
1478 /* FIXME MVS: assumes the order of the first 32 elements... */
1479 for (regi
= G0_REGNUM
; regi
<= I7_REGNUM
; regi
++)
1481 supply_register (regi
, ((char *) (regp
+ regi
)) + offset
);
1484 /* These require a bit more care. */
1485 supply_register (PC_REGNUM
, ((char *) (regp
+ R_PC
)) + offset
);
1486 supply_register (NPC_REGNUM
, ((char *) (regp
+ R_nPC
)) + offset
);
1487 supply_register (Y_REGNUM
, ((char *) (regp
+ R_Y
)) + offset
);
1489 if (GDB_TARGET_IS_SPARC64
)
1492 supply_register (CCR_REGNUM
, ((char *) (regp
+ R_CCR
)) + offset
);
1494 supply_register (CCR_REGNUM
, NULL
);
1497 supply_register (FPRS_REGNUM
, ((char *) (regp
+ R_FPRS
)) + offset
);
1499 supply_register (FPRS_REGNUM
, NULL
);
1502 supply_register (ASI_REGNUM
, ((char *) (regp
+ R_ASI
)) + offset
);
1504 supply_register (ASI_REGNUM
, NULL
);
1510 supply_register (PS_REGNUM
, ((char *) (regp
+ R_PS
)) + offset
);
1512 supply_register (PS_REGNUM
, NULL
);
1515 /* For 64-bit hosts, R_WIM and R_TBR may not be defined.
1516 Steal R_ASI and R_FPRS, and hope for the best! */
1518 #if !defined (R_WIM) && defined (R_ASI)
1522 #if !defined (R_TBR) && defined (R_FPRS)
1523 #define R_TBR R_FPRS
1527 supply_register (WIM_REGNUM
, ((char *) (regp
+ R_WIM
)) + offset
);
1529 supply_register (WIM_REGNUM
, NULL
);
1533 supply_register (TBR_REGNUM
, ((char *) (regp
+ R_TBR
)) + offset
);
1535 supply_register (TBR_REGNUM
, NULL
);
1539 /* Fill inaccessible registers with zero. */
1540 if (GDB_TARGET_IS_SPARC64
)
1543 * don't know how to get value of any of the following:
1545 supply_register (VER_REGNUM
, NULL
);
1546 supply_register (TICK_REGNUM
, NULL
);
1547 supply_register (PIL_REGNUM
, NULL
);
1548 supply_register (PSTATE_REGNUM
, NULL
);
1549 supply_register (TSTATE_REGNUM
, NULL
);
1550 supply_register (TBA_REGNUM
, NULL
);
1551 supply_register (TL_REGNUM
, NULL
);
1552 supply_register (TT_REGNUM
, NULL
);
1553 supply_register (TPC_REGNUM
, NULL
);
1554 supply_register (TNPC_REGNUM
, NULL
);
1555 supply_register (WSTATE_REGNUM
, NULL
);
1556 supply_register (CWP_REGNUM
, NULL
);
1557 supply_register (CANSAVE_REGNUM
, NULL
);
1558 supply_register (CANRESTORE_REGNUM
, NULL
);
1559 supply_register (CLEANWIN_REGNUM
, NULL
);
1560 supply_register (OTHERWIN_REGNUM
, NULL
);
1561 supply_register (ASR16_REGNUM
, NULL
);
1562 supply_register (ASR17_REGNUM
, NULL
);
1563 supply_register (ASR18_REGNUM
, NULL
);
1564 supply_register (ASR19_REGNUM
, NULL
);
1565 supply_register (ASR20_REGNUM
, NULL
);
1566 supply_register (ASR21_REGNUM
, NULL
);
1567 supply_register (ASR22_REGNUM
, NULL
);
1568 supply_register (ASR23_REGNUM
, NULL
);
1569 supply_register (ASR24_REGNUM
, NULL
);
1570 supply_register (ASR25_REGNUM
, NULL
);
1571 supply_register (ASR26_REGNUM
, NULL
);
1572 supply_register (ASR27_REGNUM
, NULL
);
1573 supply_register (ASR28_REGNUM
, NULL
);
1574 supply_register (ASR29_REGNUM
, NULL
);
1575 supply_register (ASR30_REGNUM
, NULL
);
1576 supply_register (ASR31_REGNUM
, NULL
);
1577 supply_register (ICC_REGNUM
, NULL
);
1578 supply_register (XCC_REGNUM
, NULL
);
1582 supply_register (CPS_REGNUM
, NULL
);
1587 fill_gregset (gdb_gregset_t
*gregsetp
, int regno
)
1589 prgreg_t
*regp
= (prgreg_t
*) gregsetp
;
1590 int regi
, offset
= 0;
1592 /* If the host is 64-bit sparc, but the target is 32-bit sparc,
1593 then the gregset may contain 64-bit ints while supply_register
1594 is expecting 32-bit ints. Compensate. */
1595 if (sizeof (regp
[0]) == 8 && SPARC_INTREG_SIZE
== 4)
1598 for (regi
= 0; regi
<= R_I7
; regi
++)
1599 if ((regno
== -1) || (regno
== regi
))
1600 read_register_gen (regi
, (char *) (regp
+ regi
) + offset
);
1602 if ((regno
== -1) || (regno
== PC_REGNUM
))
1603 read_register_gen (PC_REGNUM
, (char *) (regp
+ R_PC
) + offset
);
1605 if ((regno
== -1) || (regno
== NPC_REGNUM
))
1606 read_register_gen (NPC_REGNUM
, (char *) (regp
+ R_nPC
) + offset
);
1608 if ((regno
== -1) || (regno
== Y_REGNUM
))
1609 read_register_gen (Y_REGNUM
, (char *) (regp
+ R_Y
) + offset
);
1611 if (GDB_TARGET_IS_SPARC64
)
1614 if (regno
== -1 || regno
== CCR_REGNUM
)
1615 read_register_gen (CCR_REGNUM
, ((char *) (regp
+ R_CCR
)) + offset
);
1618 if (regno
== -1 || regno
== FPRS_REGNUM
)
1619 read_register_gen (FPRS_REGNUM
, ((char *) (regp
+ R_FPRS
)) + offset
);
1622 if (regno
== -1 || regno
== ASI_REGNUM
)
1623 read_register_gen (ASI_REGNUM
, ((char *) (regp
+ R_ASI
)) + offset
);
1629 if (regno
== -1 || regno
== PS_REGNUM
)
1630 read_register_gen (PS_REGNUM
, ((char *) (regp
+ R_PS
)) + offset
);
1633 /* For 64-bit hosts, R_WIM and R_TBR may not be defined.
1634 Steal R_ASI and R_FPRS, and hope for the best! */
1636 #if !defined (R_WIM) && defined (R_ASI)
1640 #if !defined (R_TBR) && defined (R_FPRS)
1641 #define R_TBR R_FPRS
1645 if (regno
== -1 || regno
== WIM_REGNUM
)
1646 read_register_gen (WIM_REGNUM
, ((char *) (regp
+ R_WIM
)) + offset
);
1648 if (regno
== -1 || regno
== WIM_REGNUM
)
1649 read_register_gen (WIM_REGNUM
, NULL
);
1653 if (regno
== -1 || regno
== TBR_REGNUM
)
1654 read_register_gen (TBR_REGNUM
, ((char *) (regp
+ R_TBR
)) + offset
);
1656 if (regno
== -1 || regno
== TBR_REGNUM
)
1657 read_register_gen (TBR_REGNUM
, NULL
);
1662 /* Given a pointer to a floating point register set in /proc format
1663 (fpregset_t *), unpack the register contents and supply them as gdb's
1664 idea of the current floating point register values. */
1667 supply_fpregset (gdb_fpregset_t
*fpregsetp
)
1675 for (regi
= FP0_REGNUM
; regi
< FP_MAX_REGNUM
; regi
++)
1677 from
= (char *) &fpregsetp
->pr_fr
.pr_regs
[regi
- FP0_REGNUM
];
1678 supply_register (regi
, from
);
1681 if (GDB_TARGET_IS_SPARC64
)
1684 * don't know how to get value of the following.
1686 supply_register (FSR_REGNUM
, NULL
); /* zero it out for now */
1687 supply_register (FCC0_REGNUM
, NULL
);
1688 supply_register (FCC1_REGNUM
, NULL
); /* don't know how to get value */
1689 supply_register (FCC2_REGNUM
, NULL
); /* don't know how to get value */
1690 supply_register (FCC3_REGNUM
, NULL
); /* don't know how to get value */
1694 supply_register (FPS_REGNUM
, (char *) &(fpregsetp
->pr_fsr
));
1698 /* Given a pointer to a floating point register set in /proc format
1699 (fpregset_t *), update the register specified by REGNO from gdb's idea
1700 of the current floating point register set. If REGNO is -1, update
1702 /* This will probably need some changes for sparc64. */
1705 fill_fpregset (gdb_fpregset_t
*fpregsetp
, int regno
)
1714 for (regi
= FP0_REGNUM
; regi
< FP_MAX_REGNUM
; regi
++)
1716 if ((regno
== -1) || (regno
== regi
))
1718 from
= (char *) ®isters
[REGISTER_BYTE (regi
)];
1719 to
= (char *) &fpregsetp
->pr_fr
.pr_regs
[regi
- FP0_REGNUM
];
1720 memcpy (to
, from
, REGISTER_RAW_SIZE (regi
));
1724 if (!(GDB_TARGET_IS_SPARC64
)) /* FIXME: does Sparc64 have this register? */
1725 if ((regno
== -1) || (regno
== FPS_REGNUM
))
1727 from
= (char *)®isters
[REGISTER_BYTE (FPS_REGNUM
)];
1728 to
= (char *) &fpregsetp
->pr_fsr
;
1729 memcpy (to
, from
, REGISTER_RAW_SIZE (FPS_REGNUM
));
1733 #endif /* USE_PROC_FS */
1735 /* Because of Multi-arch, GET_LONGJMP_TARGET is always defined. So test
1736 for a definition of JB_PC. */
1739 /* Figure out where the longjmp will land. We expect that we have just entered
1740 longjmp and haven't yet setup the stack frame, so the args are still in the
1741 output regs. %o0 (O0_REGNUM) points at the jmp_buf structure from which we
1742 extract the pc (JB_PC) that we will land at. The pc is copied into ADDR.
1743 This routine returns true on success */
1746 get_longjmp_target (CORE_ADDR
*pc
)
1749 #define LONGJMP_TARGET_SIZE 4
1750 char buf
[LONGJMP_TARGET_SIZE
];
1752 jb_addr
= read_register (O0_REGNUM
);
1754 if (target_read_memory (jb_addr
+ JB_PC
* JB_ELEMENT_SIZE
, buf
,
1755 LONGJMP_TARGET_SIZE
))
1758 *pc
= extract_address (buf
, LONGJMP_TARGET_SIZE
);
1762 #endif /* GET_LONGJMP_TARGET */
1764 #ifdef STATIC_TRANSFORM_NAME
1765 /* SunPRO (3.0 at least), encodes the static variables. This is not
1766 related to C++ mangling, it is done for C too. */
1769 sunpro_static_transform_name (char *name
)
1774 /* For file-local statics there will be a dollar sign, a bunch
1775 of junk (the contents of which match a string given in the
1776 N_OPT), a period and the name. For function-local statics
1777 there will be a bunch of junk (which seems to change the
1778 second character from 'A' to 'B'), a period, the name of the
1779 function, and the name. So just skip everything before the
1781 p
= strrchr (name
, '.');
1787 #endif /* STATIC_TRANSFORM_NAME */
1790 /* Utilities for printing registers.
1791 Page numbers refer to the SPARC Architecture Manual. */
1793 static void dump_ccreg (char *, int);
1796 dump_ccreg (char *reg
, int val
)
1799 printf_unfiltered ("%s:%s,%s,%s,%s", reg
,
1800 val
& 8 ? "N" : "NN",
1801 val
& 4 ? "Z" : "NZ",
1802 val
& 2 ? "O" : "NO",
1803 val
& 1 ? "C" : "NC");
1807 decode_asi (int val
)
1813 return "ASI_NUCLEUS";
1815 return "ASI_NUCLEUS_LITTLE";
1817 return "ASI_AS_IF_USER_PRIMARY";
1819 return "ASI_AS_IF_USER_SECONDARY";
1821 return "ASI_AS_IF_USER_PRIMARY_LITTLE";
1823 return "ASI_AS_IF_USER_SECONDARY_LITTLE";
1825 return "ASI_PRIMARY";
1827 return "ASI_SECONDARY";
1829 return "ASI_PRIMARY_NOFAULT";
1831 return "ASI_SECONDARY_NOFAULT";
1833 return "ASI_PRIMARY_LITTLE";
1835 return "ASI_SECONDARY_LITTLE";
1837 return "ASI_PRIMARY_NOFAULT_LITTLE";
1839 return "ASI_SECONDARY_NOFAULT_LITTLE";
1845 /* PRINT_REGISTER_HOOK routine.
1846 Pretty print various registers. */
1847 /* FIXME: Would be nice if this did some fancy things for 32 bit sparc. */
1850 sparc_print_register_hook (int regno
)
1854 /* Handle double/quad versions of lower 32 fp regs. */
1855 if (regno
>= FP0_REGNUM
&& regno
< FP0_REGNUM
+ 32
1856 && (regno
& 1) == 0)
1860 if (frame_register_read (selected_frame
, regno
, value
)
1861 && frame_register_read (selected_frame
, regno
+ 1, value
+ 4))
1863 printf_unfiltered ("\t");
1864 print_floating (value
, builtin_type_double
, gdb_stdout
);
1866 #if 0 /* FIXME: gdb doesn't handle long doubles */
1867 if ((regno
& 3) == 0)
1869 if (frame_register_read (selected_frame
, regno
+ 2, value
+ 8)
1870 && frame_register_read (selected_frame
, regno
+ 3, value
+ 12))
1872 printf_unfiltered ("\t");
1873 print_floating (value
, builtin_type_long_double
, gdb_stdout
);
1880 #if 0 /* FIXME: gdb doesn't handle long doubles */
1881 /* Print upper fp regs as long double if appropriate. */
1882 if (regno
>= FP0_REGNUM
+ 32 && regno
< FP_MAX_REGNUM
1883 /* We test for even numbered regs and not a multiple of 4 because
1884 the upper fp regs are recorded as doubles. */
1885 && (regno
& 1) == 0)
1889 if (frame_register_read (selected_frame
, regno
, value
)
1890 && frame_register_read (selected_frame
, regno
+ 1, value
+ 8))
1892 printf_unfiltered ("\t");
1893 print_floating (value
, builtin_type_long_double
, gdb_stdout
);
1899 /* FIXME: Some of these are priviledged registers.
1900 Not sure how they should be handled. */
1902 #define BITS(n, mask) ((int) (((val) >> (n)) & (mask)))
1904 val
= read_register (regno
);
1907 if (GDB_TARGET_IS_SPARC64
)
1911 printf_unfiltered ("\t");
1912 dump_ccreg ("xcc", val
>> 4);
1913 printf_unfiltered (", ");
1914 dump_ccreg ("icc", val
& 15);
1917 printf ("\tfef:%d, du:%d, dl:%d",
1918 BITS (2, 1), BITS (1, 1), BITS (0, 1));
1922 static char *fcc
[4] =
1923 {"=", "<", ">", "?"};
1924 static char *rd
[4] =
1925 {"N", "0", "+", "-"};
1926 /* Long, but I'd rather leave it as is and use a wide screen. */
1927 printf_filtered ("\t0:%s, 1:%s, 2:%s, 3:%s, rd:%s, tem:%d, ",
1928 fcc
[BITS (10, 3)], fcc
[BITS (32, 3)],
1929 fcc
[BITS (34, 3)], fcc
[BITS (36, 3)],
1930 rd
[BITS (30, 3)], BITS (23, 31));
1931 printf_filtered ("ns:%d, ver:%d, ftt:%d, qne:%d, aexc:%d, cexc:%d",
1932 BITS (22, 1), BITS (17, 7), BITS (14, 7),
1933 BITS (13, 1), BITS (5, 31), BITS (0, 31));
1938 char *asi
= decode_asi (val
);
1940 printf ("\t%s", asi
);
1944 printf ("\tmanuf:%d, impl:%d, mask:%d, maxtl:%d, maxwin:%d",
1945 BITS (48, 0xffff), BITS (32, 0xffff),
1946 BITS (24, 0xff), BITS (8, 0xff), BITS (0, 31));
1950 static char *mm
[4] =
1951 {"tso", "pso", "rso", "?"};
1952 printf_filtered ("\tcle:%d, tle:%d, mm:%s, red:%d, ",
1953 BITS (9, 1), BITS (8, 1),
1954 mm
[BITS (6, 3)], BITS (5, 1));
1955 printf_filtered ("pef:%d, am:%d, priv:%d, ie:%d, ag:%d",
1956 BITS (4, 1), BITS (3, 1), BITS (2, 1),
1957 BITS (1, 1), BITS (0, 1));
1961 /* FIXME: print all 4? */
1964 /* FIXME: print all 4? */
1967 /* FIXME: print all 4? */
1970 /* FIXME: print all 4? */
1973 printf ("\tother:%d, normal:%d", BITS (3, 7), BITS (0, 7));
1976 printf ("\t%d", BITS (0, 31));
1978 case CANSAVE_REGNUM
:
1979 printf ("\t%-2d before spill", BITS (0, 31));
1981 case CANRESTORE_REGNUM
:
1982 printf ("\t%-2d before fill", BITS (0, 31));
1984 case CLEANWIN_REGNUM
:
1985 printf ("\t%-2d before clean", BITS (0, 31));
1987 case OTHERWIN_REGNUM
:
1988 printf ("\t%d", BITS (0, 31));
1995 printf ("\ticc:%c%c%c%c, pil:%d, s:%d, ps:%d, et:%d, cwp:%d",
1996 BITS (23, 1) ? 'N' : '-', BITS (22, 1) ? 'Z' : '-',
1997 BITS (21, 1) ? 'V' : '-', BITS (20, 1) ? 'C' : '-',
1998 BITS (8, 15), BITS (7, 1), BITS (6, 1), BITS (5, 1),
2003 static char *fcc
[4] =
2004 {"=", "<", ">", "?"};
2005 static char *rd
[4] =
2006 {"N", "0", "+", "-"};
2007 /* Long, but I'd rather leave it as is and use a wide screen. */
2008 printf ("\trd:%s, tem:%d, ns:%d, ver:%d, ftt:%d, qne:%d, "
2009 "fcc:%s, aexc:%d, cexc:%d",
2010 rd
[BITS (30, 3)], BITS (23, 31), BITS (22, 1), BITS (17, 7),
2011 BITS (14, 7), BITS (13, 1), fcc
[BITS (10, 3)], BITS (5, 31),
2021 gdb_print_insn_sparc (bfd_vma memaddr
, disassemble_info
*info
)
2023 /* It's necessary to override mach again because print_insn messes it up. */
2024 info
->mach
= TARGET_ARCHITECTURE
->mach
;
2025 return print_insn_sparc (memaddr
, info
);
2028 /* The SPARC passes the arguments on the stack; arguments smaller
2029 than an int are promoted to an int. The first 6 words worth of
2030 args are also passed in registers o0 - o5. */
2033 sparc32_push_arguments (int nargs
, struct value
**args
, CORE_ADDR sp
,
2034 int struct_return
, CORE_ADDR struct_addr
)
2037 int accumulate_size
= 0;
2044 struct sparc_arg
*sparc_args
=
2045 (struct sparc_arg
*) alloca (nargs
* sizeof (struct sparc_arg
));
2046 struct sparc_arg
*m_arg
;
2048 /* Promote arguments if necessary, and calculate their stack offsets
2050 for (i
= 0, m_arg
= sparc_args
; i
< nargs
; i
++, m_arg
++)
2052 struct value
*arg
= args
[i
];
2053 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
2054 /* Cast argument to long if necessary as the compiler does it too. */
2055 switch (TYPE_CODE (arg_type
))
2058 case TYPE_CODE_BOOL
:
2059 case TYPE_CODE_CHAR
:
2060 case TYPE_CODE_RANGE
:
2061 case TYPE_CODE_ENUM
:
2062 if (TYPE_LENGTH (arg_type
) < TYPE_LENGTH (builtin_type_long
))
2064 arg_type
= builtin_type_long
;
2065 arg
= value_cast (arg_type
, arg
);
2071 m_arg
->len
= TYPE_LENGTH (arg_type
);
2072 m_arg
->offset
= accumulate_size
;
2073 accumulate_size
= (accumulate_size
+ m_arg
->len
+ 3) & ~3;
2074 m_arg
->contents
= VALUE_CONTENTS (arg
);
2077 /* Make room for the arguments on the stack. */
2078 accumulate_size
+= CALL_DUMMY_STACK_ADJUST
;
2079 sp
= ((sp
- accumulate_size
) & ~7) + CALL_DUMMY_STACK_ADJUST
;
2081 /* `Push' arguments on the stack. */
2082 for (i
= 0, oregnum
= 0, m_arg
= sparc_args
;
2086 write_memory (sp
+ m_arg
->offset
, m_arg
->contents
, m_arg
->len
);
2088 j
< m_arg
->len
&& oregnum
< 6;
2089 j
+= SPARC_INTREG_SIZE
, oregnum
++)
2090 write_register_gen (O0_REGNUM
+ oregnum
, m_arg
->contents
+ j
);
2097 /* Extract from an array REGBUF containing the (raw) register state
2098 a function return value of type TYPE, and copy that, in virtual format,
2102 sparc32_extract_return_value (struct type
*type
, char *regbuf
, char *valbuf
)
2104 int typelen
= TYPE_LENGTH (type
);
2105 int regsize
= REGISTER_RAW_SIZE (O0_REGNUM
);
2107 if (TYPE_CODE (type
) == TYPE_CODE_FLT
&& SPARC_HAS_FPU
)
2108 memcpy (valbuf
, ®buf
[REGISTER_BYTE (FP0_REGNUM
)], typelen
);
2111 ®buf
[O0_REGNUM
* regsize
+
2113 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
? 0
2114 : regsize
- typelen
)],
2119 /* Write into appropriate registers a function return value
2120 of type TYPE, given in virtual format. On SPARCs with FPUs,
2121 float values are returned in %f0 (and %f1). In all other cases,
2122 values are returned in register %o0. */
2125 sparc_store_return_value (struct type
*type
, char *valbuf
)
2130 buffer
= alloca (MAX_REGISTER_RAW_SIZE
);
2132 if (TYPE_CODE (type
) == TYPE_CODE_FLT
&& SPARC_HAS_FPU
)
2133 /* Floating-point values are returned in the register pair */
2134 /* formed by %f0 and %f1 (doubles are, anyway). */
2137 /* Other values are returned in register %o0. */
2140 /* Add leading zeros to the value. */
2141 if (TYPE_LENGTH (type
) < REGISTER_RAW_SIZE (regno
))
2143 memset (buffer
, 0, REGISTER_RAW_SIZE (regno
));
2144 memcpy (buffer
+ REGISTER_RAW_SIZE (regno
) - TYPE_LENGTH (type
), valbuf
,
2145 TYPE_LENGTH (type
));
2146 write_register_gen (regno
, buffer
);
2149 write_register_bytes (REGISTER_BYTE (regno
), valbuf
, TYPE_LENGTH (type
));
2153 sparclet_store_return_value (struct type
*type
, char *valbuf
)
2155 /* Other values are returned in register %o0. */
2156 write_register_bytes (REGISTER_BYTE (O0_REGNUM
), valbuf
,
2157 TYPE_LENGTH (type
));
2161 #ifndef CALL_DUMMY_CALL_OFFSET
2162 #define CALL_DUMMY_CALL_OFFSET \
2163 (gdbarch_tdep (current_gdbarch)->call_dummy_call_offset)
2164 #endif /* CALL_DUMMY_CALL_OFFSET */
2166 /* Insert the function address into a call dummy instruction sequence
2169 For structs and unions, if the function was compiled with Sun cc,
2170 it expects 'unimp' after the call. But gcc doesn't use that
2171 (twisted) convention. So leave a nop there for gcc (FIX_CALL_DUMMY
2172 can assume it is operating on a pristine CALL_DUMMY, not one that
2173 has already been customized for a different function). */
2176 sparc_fix_call_dummy (char *dummy
, CORE_ADDR pc
, CORE_ADDR fun
,
2177 struct type
*value_type
, int using_gcc
)
2181 /* Store the relative adddress of the target function into the
2182 'call' instruction. */
2183 store_unsigned_integer (dummy
+ CALL_DUMMY_CALL_OFFSET
, 4,
2185 | (((fun
- (pc
+ CALL_DUMMY_CALL_OFFSET
)) >> 2)
2188 /* If the called function returns an aggregate value, fill in the UNIMP
2189 instruction containing the size of the returned aggregate return value,
2190 which follows the call instruction.
2191 For details see the SPARC Architecture Manual Version 8, Appendix D.3.
2193 Adjust the call_dummy_breakpoint_offset for the bp_call_dummy breakpoint
2194 to the proper address in the call dummy, so that `finish' after a stop
2195 in a call dummy works.
2196 Tweeking current_gdbarch is not an optimal solution, but the call to
2197 sparc_fix_call_dummy is immediately followed by a call to run_stack_dummy,
2198 which is the only function where dummy_breakpoint_offset is actually
2199 used, if it is non-zero. */
2200 if (TYPE_CODE (value_type
) == TYPE_CODE_STRUCT
2201 || TYPE_CODE (value_type
) == TYPE_CODE_UNION
)
2203 store_unsigned_integer (dummy
+ CALL_DUMMY_CALL_OFFSET
+ 8, 4,
2204 TYPE_LENGTH (value_type
) & 0x1fff);
2205 set_gdbarch_call_dummy_breakpoint_offset (current_gdbarch
, 0x30);
2208 set_gdbarch_call_dummy_breakpoint_offset (current_gdbarch
, 0x2c);
2210 if (!(GDB_TARGET_IS_SPARC64
))
2212 /* If this is not a simulator target, change the first four
2213 instructions of the call dummy to NOPs. Those instructions
2214 include a 'save' instruction and are designed to work around
2215 problems with register window flushing in the simulator. */
2217 if (strcmp (target_shortname
, "sim") != 0)
2219 for (i
= 0; i
< 4; i
++)
2220 store_unsigned_integer (dummy
+ (i
* 4), 4, 0x01000000);
2224 /* If this is a bi-endian target, GDB has written the call dummy
2225 in little-endian order. We must byte-swap it back to big-endian. */
2228 for (i
= 0; i
< CALL_DUMMY_LENGTH
; i
+= 4)
2230 char tmp
= dummy
[i
];
2231 dummy
[i
] = dummy
[i
+ 3];
2234 dummy
[i
+ 1] = dummy
[i
+ 2];
2241 /* Set target byte order based on machine type. */
2244 sparc_target_architecture_hook (const bfd_arch_info_type
*ap
)
2248 if (ap
->mach
== bfd_mach_sparc_sparclite_le
)
2250 target_byte_order
= BFD_ENDIAN_LITTLE
;
2260 * Module "constructor" function.
2263 static struct gdbarch
* sparc_gdbarch_init (struct gdbarch_info info
,
2264 struct gdbarch_list
*arches
);
2267 _initialize_sparc_tdep (void)
2269 /* Hook us into the gdbarch mechanism. */
2270 register_gdbarch_init (bfd_arch_sparc
, sparc_gdbarch_init
);
2272 tm_print_insn
= gdb_print_insn_sparc
;
2273 tm_print_insn_info
.mach
= TM_PRINT_INSN_MACH
; /* Selects sparc/sparclite */
2274 target_architecture_hook
= sparc_target_architecture_hook
;
2277 /* Compensate for stack bias. Note that we currently don't handle
2278 mixed 32/64 bit code. */
2281 sparc64_read_sp (void)
2283 CORE_ADDR sp
= read_register (SP_REGNUM
);
2291 sparc64_read_fp (void)
2293 CORE_ADDR fp
= read_register (FP_REGNUM
);
2301 sparc64_write_sp (CORE_ADDR val
)
2303 CORE_ADDR oldsp
= read_register (SP_REGNUM
);
2305 write_register (SP_REGNUM
, val
- 2047);
2307 write_register (SP_REGNUM
, val
);
2310 /* The SPARC 64 ABI passes floating-point arguments in FP0 to FP31,
2311 and all other arguments in O0 to O5. They are also copied onto
2312 the stack in the correct places. Apparently (empirically),
2313 structs of less than 16 bytes are passed member-by-member in
2314 separate registers, but I am unable to figure out the algorithm.
2315 Some members go in floating point regs, but I don't know which.
2317 FIXME: Handle small structs (less than 16 bytes containing floats).
2319 The counting regimen for using both integer and FP registers
2320 for argument passing is rather odd -- a single counter is used
2321 for both; this means that if the arguments alternate between
2322 int and float, we will waste every other register of both types. */
2325 sparc64_push_arguments (int nargs
, struct value
**args
, CORE_ADDR sp
,
2326 int struct_return
, CORE_ADDR struct_retaddr
)
2328 int i
, j
, register_counter
= 0;
2330 struct type
*sparc_intreg_type
=
2331 TYPE_LENGTH (builtin_type_long
) == SPARC_INTREG_SIZE
?
2332 builtin_type_long
: builtin_type_long_long
;
2334 sp
= (sp
& ~(((unsigned long) SPARC_INTREG_SIZE
) - 1UL));
2336 /* Figure out how much space we'll need. */
2337 for (i
= nargs
- 1; i
>= 0; i
--)
2339 int len
= TYPE_LENGTH (check_typedef (VALUE_TYPE (args
[i
])));
2340 struct value
*copyarg
= args
[i
];
2343 if (copylen
< SPARC_INTREG_SIZE
)
2345 copyarg
= value_cast (sparc_intreg_type
, copyarg
);
2346 copylen
= SPARC_INTREG_SIZE
;
2355 /* if STRUCT_RETURN, then first argument is the struct return location. */
2357 write_register (O0_REGNUM
+ register_counter
++, struct_retaddr
);
2359 /* Now write the arguments onto the stack, while writing FP
2360 arguments into the FP registers, and other arguments into the
2361 first six 'O' registers. */
2363 for (i
= 0; i
< nargs
; i
++)
2365 int len
= TYPE_LENGTH (check_typedef (VALUE_TYPE (args
[i
])));
2366 struct value
*copyarg
= args
[i
];
2367 enum type_code typecode
= TYPE_CODE (VALUE_TYPE (args
[i
]));
2370 if (typecode
== TYPE_CODE_INT
||
2371 typecode
== TYPE_CODE_BOOL
||
2372 typecode
== TYPE_CODE_CHAR
||
2373 typecode
== TYPE_CODE_RANGE
||
2374 typecode
== TYPE_CODE_ENUM
)
2375 if (len
< SPARC_INTREG_SIZE
)
2377 /* Small ints will all take up the size of one intreg on
2379 copyarg
= value_cast (sparc_intreg_type
, copyarg
);
2380 copylen
= SPARC_INTREG_SIZE
;
2383 write_memory (tempsp
, VALUE_CONTENTS (copyarg
), copylen
);
2386 /* Corner case: Structs consisting of a single float member are floats.
2387 * FIXME! I don't know about structs containing multiple floats!
2388 * Structs containing mixed floats and ints are even more weird.
2393 /* Separate float args from all other args. */
2394 if (typecode
== TYPE_CODE_FLT
&& SPARC_HAS_FPU
)
2396 if (register_counter
< 16)
2398 /* This arg gets copied into a FP register. */
2402 case 4: /* Single-precision (float) */
2403 fpreg
= FP0_REGNUM
+ 2 * register_counter
+ 1;
2404 register_counter
+= 1;
2406 case 8: /* Double-precision (double) */
2407 fpreg
= FP0_REGNUM
+ 2 * register_counter
;
2408 register_counter
+= 1;
2410 case 16: /* Quad-precision (long double) */
2411 fpreg
= FP0_REGNUM
+ 2 * register_counter
;
2412 register_counter
+= 2;
2415 internal_error (__FILE__
, __LINE__
, "bad switch");
2417 write_register_bytes (REGISTER_BYTE (fpreg
),
2418 VALUE_CONTENTS (args
[i
]),
2422 else /* all other args go into the first six 'o' registers */
2425 j
< len
&& register_counter
< 6;
2426 j
+= SPARC_INTREG_SIZE
)
2428 int oreg
= O0_REGNUM
+ register_counter
;
2430 write_register_gen (oreg
, VALUE_CONTENTS (copyarg
) + j
);
2431 register_counter
+= 1;
2438 /* Values <= 32 bytes are returned in o0-o3 (floating-point values are
2439 returned in f0-f3). */
2442 sp64_extract_return_value (struct type
*type
, char *regbuf
, char *valbuf
,
2445 int typelen
= TYPE_LENGTH (type
);
2446 int regsize
= REGISTER_RAW_SIZE (O0_REGNUM
);
2448 if (TYPE_CODE (type
) == TYPE_CODE_FLT
&& SPARC_HAS_FPU
)
2450 memcpy (valbuf
, ®buf
[REGISTER_BYTE (FP0_REGNUM
)], typelen
);
2454 if (TYPE_CODE (type
) != TYPE_CODE_STRUCT
2455 || (TYPE_LENGTH (type
) > 32))
2458 ®buf
[O0_REGNUM
* regsize
+
2459 (typelen
>= regsize
? 0 : regsize
- typelen
)],
2465 char *o0
= ®buf
[O0_REGNUM
* regsize
];
2466 char *f0
= ®buf
[FP0_REGNUM
* regsize
];
2469 for (x
= 0; x
< TYPE_NFIELDS (type
); x
++)
2471 struct field
*f
= &TYPE_FIELDS (type
)[x
];
2472 /* FIXME: We may need to handle static fields here. */
2473 int whichreg
= (f
->loc
.bitpos
+ bitoffset
) / 32;
2474 int remainder
= ((f
->loc
.bitpos
+ bitoffset
) % 32) / 8;
2475 int where
= (f
->loc
.bitpos
+ bitoffset
) / 8;
2476 int size
= TYPE_LENGTH (f
->type
);
2477 int typecode
= TYPE_CODE (f
->type
);
2479 if (typecode
== TYPE_CODE_STRUCT
)
2481 sp64_extract_return_value (f
->type
,
2484 bitoffset
+ f
->loc
.bitpos
);
2486 else if (typecode
== TYPE_CODE_FLT
&& SPARC_HAS_FPU
)
2488 memcpy (valbuf
+ where
, &f0
[whichreg
* 4] + remainder
, size
);
2492 memcpy (valbuf
+ where
, &o0
[whichreg
* 4] + remainder
, size
);
2499 sparc64_extract_return_value (struct type
*type
, char *regbuf
, char *valbuf
)
2501 sp64_extract_return_value (type
, regbuf
, valbuf
, 0);
2505 sparclet_extract_return_value (struct type
*type
,
2509 regbuf
+= REGISTER_RAW_SIZE (O0_REGNUM
) * 8;
2510 if (TYPE_LENGTH (type
) < REGISTER_RAW_SIZE (O0_REGNUM
))
2511 regbuf
+= REGISTER_RAW_SIZE (O0_REGNUM
) - TYPE_LENGTH (type
);
2513 memcpy ((void *) valbuf
, regbuf
, TYPE_LENGTH (type
));
2518 sparc32_stack_align (CORE_ADDR addr
)
2520 return ((addr
+ 7) & -8);
2524 sparc64_stack_align (CORE_ADDR addr
)
2526 return ((addr
+ 15) & -16);
2530 sparc_print_extra_frame_info (struct frame_info
*fi
)
2532 if (fi
&& fi
->extra_info
&& fi
->extra_info
->flat
)
2533 printf_filtered (" flat, pc saved at 0x%s, fp saved at 0x%s\n",
2534 paddr_nz (fi
->extra_info
->pc_addr
),
2535 paddr_nz (fi
->extra_info
->fp_addr
));
2538 /* MULTI_ARCH support */
2541 sparc32_register_name (int regno
)
2543 static char *register_names
[] =
2544 { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
2545 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
2546 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
2547 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
2549 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
2550 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
2551 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
2552 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
2554 "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr"
2558 regno
>= (sizeof (register_names
) / sizeof (register_names
[0])))
2561 return register_names
[regno
];
2565 sparc64_register_name (int regno
)
2567 static char *register_names
[] =
2568 { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
2569 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
2570 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
2571 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
2573 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
2574 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
2575 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
2576 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
2577 "f32", "f34", "f36", "f38", "f40", "f42", "f44", "f46",
2578 "f48", "f50", "f52", "f54", "f56", "f58", "f60", "f62",
2580 "pc", "npc", "ccr", "fsr", "fprs", "y", "asi", "ver",
2581 "tick", "pil", "pstate", "tstate", "tba", "tl", "tt", "tpc",
2582 "tnpc", "wstate", "cwp", "cansave", "canrestore", "cleanwin", "otherwin",
2583 "asr16", "asr17", "asr18", "asr19", "asr20", "asr21", "asr22", "asr23",
2584 "asr24", "asr25", "asr26", "asr27", "asr28", "asr29", "asr30", "asr31",
2585 /* These are here at the end to simplify removing them if we have to. */
2586 "icc", "xcc", "fcc0", "fcc1", "fcc2", "fcc3"
2590 regno
>= (sizeof (register_names
) / sizeof (register_names
[0])))
2593 return register_names
[regno
];
2597 sparclite_register_name (int regno
)
2599 static char *register_names
[] =
2600 { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
2601 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
2602 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
2603 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
2605 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
2606 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
2607 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
2608 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
2610 "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr",
2611 "dia1", "dia2", "dda1", "dda2", "ddv1", "ddv2", "dcr", "dsr"
2615 regno
>= (sizeof (register_names
) / sizeof (register_names
[0])))
2618 return register_names
[regno
];
2622 sparclet_register_name (int regno
)
2624 static char *register_names
[] =
2625 { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
2626 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
2627 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
2628 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
2630 "", "", "", "", "", "", "", "", /* no floating point registers */
2631 "", "", "", "", "", "", "", "",
2632 "", "", "", "", "", "", "", "",
2633 "", "", "", "", "", "", "", "",
2635 "y", "psr", "wim", "tbr", "pc", "npc", "", "", /* no FPSR or CPSR */
2636 "ccsr", "ccpr", "cccrcr", "ccor", "ccobr", "ccibr", "ccir", "",
2638 /* ASR15 ASR19 (don't display them) */
2639 "asr1", "", "asr17", "asr18", "", "asr20", "asr21", "asr22"
2640 /* None of the rest get displayed */
2642 "awr0", "awr1", "awr2", "awr3", "awr4", "awr5", "awr6", "awr7",
2643 "awr8", "awr9", "awr10", "awr11", "awr12", "awr13", "awr14", "awr15",
2644 "awr16", "awr17", "awr18", "awr19", "awr20", "awr21", "awr22", "awr23",
2645 "awr24", "awr25", "awr26", "awr27", "awr28", "awr29", "awr30", "awr31",
2651 regno
>= (sizeof (register_names
) / sizeof (register_names
[0])))
2654 return register_names
[regno
];
2658 sparc_push_return_address (CORE_ADDR pc_unused
, CORE_ADDR sp
)
2660 if (CALL_DUMMY_LOCATION
== AT_ENTRY_POINT
)
2662 /* The return PC of the dummy_frame is the former 'current' PC
2663 (where we were before we made the target function call).
2664 This is saved in %i7 by push_dummy_frame.
2666 We will save the 'call dummy location' (ie. the address
2667 to which the target function will return) in %o7.
2668 This address will actually be the program's entry point.
2669 There will be a special call_dummy breakpoint there. */
2671 write_register (O7_REGNUM
,
2672 CALL_DUMMY_ADDRESS () - 8);
2678 /* Should call_function allocate stack space for a struct return? */
2681 sparc64_use_struct_convention (int gcc_p
, struct type
*type
)
2683 return (TYPE_LENGTH (type
) > 32);
2686 /* Store the address of the place in which to copy the structure the
2687 subroutine will return. This is called from call_function_by_hand.
2688 The ultimate mystery is, tho, what is the value "16"?
2690 MVS: That's the offset from where the sp is now, to where the
2691 subroutine is gonna expect to find the struct return address. */
2694 sparc32_store_struct_return (CORE_ADDR addr
, CORE_ADDR sp
)
2699 val
= alloca (SPARC_INTREG_SIZE
);
2700 store_unsigned_integer (val
, SPARC_INTREG_SIZE
, addr
);
2701 write_memory (sp
+ (16 * SPARC_INTREG_SIZE
), val
, SPARC_INTREG_SIZE
);
2703 if (CALL_DUMMY_LOCATION
== AT_ENTRY_POINT
)
2705 /* Now adjust the value of the link register, which was previously
2706 stored by push_return_address. Functions that return structs are
2707 peculiar in that they return to link register + 12, rather than
2708 link register + 8. */
2710 o7
= read_register (O7_REGNUM
);
2711 write_register (O7_REGNUM
, o7
- 4);
2716 sparc64_store_struct_return (CORE_ADDR addr
, CORE_ADDR sp
)
2718 /* FIXME: V9 uses %o0 for this. */
2719 /* FIXME MVS: Only for small enough structs!!! */
2721 target_write_memory (sp
+ (16 * SPARC_INTREG_SIZE
),
2722 (char *) &addr
, SPARC_INTREG_SIZE
);
2724 if (CALL_DUMMY_LOCATION
== AT_ENTRY_POINT
)
2726 /* Now adjust the value of the link register, which was previously
2727 stored by push_return_address. Functions that return structs are
2728 peculiar in that they return to link register + 12, rather than
2729 link register + 8. */
2731 write_register (O7_REGNUM
, read_register (O7_REGNUM
) - 4);
2736 /* Default target data type for register REGNO. */
2738 static struct type
*
2739 sparc32_register_virtual_type (int regno
)
2741 if (regno
== PC_REGNUM
||
2742 regno
== FP_REGNUM
||
2744 return builtin_type_unsigned_int
;
2746 return builtin_type_int
;
2748 return builtin_type_float
;
2749 return builtin_type_int
;
2752 static struct type
*
2753 sparc64_register_virtual_type (int regno
)
2755 if (regno
== PC_REGNUM
||
2756 regno
== FP_REGNUM
||
2758 return builtin_type_unsigned_long_long
;
2760 return builtin_type_long_long
;
2762 return builtin_type_float
;
2764 return builtin_type_double
;
2765 return builtin_type_long_long
;
2768 /* Number of bytes of storage in the actual machine representation for
2772 sparc32_register_size (int regno
)
2778 sparc64_register_size (int regno
)
2780 return (regno
< 32 ? 8 : regno
< 64 ? 4 : 8);
2783 /* Index within the `registers' buffer of the first byte of the space
2784 for register REGNO. */
2787 sparc32_register_byte (int regno
)
2793 sparc64_register_byte (int regno
)
2797 else if (regno
< 64)
2798 return 32 * 8 + (regno
- 32) * 4;
2799 else if (regno
< 80)
2800 return 32 * 8 + 32 * 4 + (regno
- 64) * 8;
2802 return 64 * 8 + (regno
- 80) * 8;
2805 /* Immediately after a function call, return the saved pc.
2806 Can't go through the frames for this because on some machines
2807 the new frame is not set up until the new function executes
2808 some instructions. */
2811 sparc_saved_pc_after_call (struct frame_info
*fi
)
2813 return sparc_pc_adjust (read_register (RP_REGNUM
));
2816 /* Convert registers between 'raw' and 'virtual' formats.
2817 They are the same on sparc, so there's nothing to do. */
2820 sparc_convert_to_virtual (int regnum
, struct type
*type
, char *from
, char *to
)
2821 { /* do nothing (should never be called) */
2825 sparc_convert_to_raw (struct type
*type
, int regnum
, char *from
, char *to
)
2826 { /* do nothing (should never be called) */
2829 /* Init saved regs: nothing to do, just a place-holder function. */
2832 sparc_frame_init_saved_regs (struct frame_info
*fi_ignored
)
2836 /* gdbarch fix call dummy:
2837 All this function does is rearrange the arguments before calling
2838 sparc_fix_call_dummy (which does the real work). */
2841 sparc_gdbarch_fix_call_dummy (char *dummy
,
2845 struct value
**args
,
2849 if (CALL_DUMMY_LOCATION
== ON_STACK
)
2850 sparc_fix_call_dummy (dummy
, pc
, fun
, type
, gcc_p
);
2853 /* Coerce float to double: a no-op. */
2856 sparc_coerce_float_to_double (struct type
*formal
, struct type
*actual
)
2861 /* CALL_DUMMY_ADDRESS: fetch the breakpoint address for a call dummy. */
2864 sparc_call_dummy_address (void)
2866 return (CALL_DUMMY_START_OFFSET
) + CALL_DUMMY_BREAKPOINT_OFFSET
;
2869 /* Supply the Y register number to those that need it. */
2872 sparc_y_regnum (void)
2874 return gdbarch_tdep (current_gdbarch
)->y_regnum
;
2878 sparc_reg_struct_has_addr (int gcc_p
, struct type
*type
)
2880 if (GDB_TARGET_IS_SPARC64
)
2881 return (TYPE_LENGTH (type
) > 32);
2883 return (gcc_p
!= 1);
2887 sparc_intreg_size (void)
2889 return SPARC_INTREG_SIZE
;
2893 sparc_return_value_on_stack (struct type
*type
)
2895 if (TYPE_CODE (type
) == TYPE_CODE_FLT
&&
2896 TYPE_LENGTH (type
) > 8)
2903 * Gdbarch "constructor" function.
2906 #define SPARC32_CALL_DUMMY_ON_STACK
2908 #define SPARC_SP_REGNUM 14
2909 #define SPARC_FP_REGNUM 30
2910 #define SPARC_FP0_REGNUM 32
2911 #define SPARC32_NPC_REGNUM 69
2912 #define SPARC32_PC_REGNUM 68
2913 #define SPARC32_Y_REGNUM 64
2914 #define SPARC64_PC_REGNUM 80
2915 #define SPARC64_NPC_REGNUM 81
2916 #define SPARC64_Y_REGNUM 85
2918 static struct gdbarch
*
2919 sparc_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2921 struct gdbarch
*gdbarch
;
2922 struct gdbarch_tdep
*tdep
;
2924 static LONGEST call_dummy_32
[] =
2925 { 0xbc100001, 0x9de38000, 0xbc100002, 0xbe100003,
2926 0xda03a058, 0xd803a054, 0xd603a050, 0xd403a04c,
2927 0xd203a048, 0x40000000, 0xd003a044, 0x01000000,
2928 0x91d02001, 0x01000000
2930 static LONGEST call_dummy_64
[] =
2931 { 0x9de3bec0fd3fa7f7LL
, 0xf93fa7eff53fa7e7LL
,
2932 0xf13fa7dfed3fa7d7LL
, 0xe93fa7cfe53fa7c7LL
,
2933 0xe13fa7bfdd3fa7b7LL
, 0xd93fa7afd53fa7a7LL
,
2934 0xd13fa79fcd3fa797LL
, 0xc93fa78fc53fa787LL
,
2935 0xc13fa77fcc3fa777LL
, 0xc83fa76fc43fa767LL
,
2936 0xc03fa75ffc3fa757LL
, 0xf83fa74ff43fa747LL
,
2937 0xf03fa73f01000000LL
, 0x0100000001000000LL
,
2938 0x0100000091580000LL
, 0xd027a72b93500000LL
,
2939 0xd027a72791480000LL
, 0xd027a72391400000LL
,
2940 0xd027a71fda5ba8a7LL
, 0xd85ba89fd65ba897LL
,
2941 0xd45ba88fd25ba887LL
, 0x9fc02000d05ba87fLL
,
2942 0x0100000091d02001LL
, 0x0100000001000000LL
2944 static LONGEST call_dummy_nil
[] = {0};
2946 /* First see if there is already a gdbarch that can satisfy the request. */
2947 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
2949 return arches
->gdbarch
;
2951 /* None found: is the request for a sparc architecture? */
2952 if (info
.bfd_arch_info
->arch
!= bfd_arch_sparc
)
2953 return NULL
; /* No; then it's not for us. */
2955 /* Yes: create a new gdbarch for the specified machine type. */
2956 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
2957 gdbarch
= gdbarch_alloc (&info
, tdep
);
2959 /* First set settings that are common for all sparc architectures. */
2960 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
2961 set_gdbarch_breakpoint_from_pc (gdbarch
, memory_breakpoint_from_pc
);
2962 set_gdbarch_coerce_float_to_double (gdbarch
,
2963 sparc_coerce_float_to_double
);
2964 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch
, 1);
2965 set_gdbarch_call_dummy_p (gdbarch
, 1);
2966 set_gdbarch_call_dummy_stack_adjust_p (gdbarch
, 1);
2967 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
2968 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2969 set_gdbarch_extract_struct_value_address (gdbarch
,
2970 sparc_extract_struct_value_address
);
2971 set_gdbarch_fix_call_dummy (gdbarch
, sparc_gdbarch_fix_call_dummy
);
2972 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2973 set_gdbarch_fp_regnum (gdbarch
, SPARC_FP_REGNUM
);
2974 set_gdbarch_fp0_regnum (gdbarch
, SPARC_FP0_REGNUM
);
2975 set_gdbarch_frame_args_address (gdbarch
, default_frame_address
);
2976 set_gdbarch_frame_chain (gdbarch
, sparc_frame_chain
);
2977 set_gdbarch_frame_init_saved_regs (gdbarch
, sparc_frame_init_saved_regs
);
2978 set_gdbarch_frame_locals_address (gdbarch
, default_frame_address
);
2979 set_gdbarch_frame_num_args (gdbarch
, frame_num_args_unknown
);
2980 set_gdbarch_frame_saved_pc (gdbarch
, sparc_frame_saved_pc
);
2981 set_gdbarch_frameless_function_invocation (gdbarch
,
2982 frameless_look_for_prologue
);
2983 set_gdbarch_get_saved_register (gdbarch
, sparc_get_saved_register
);
2984 set_gdbarch_init_extra_frame_info (gdbarch
, sparc_init_extra_frame_info
);
2985 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2986 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2987 set_gdbarch_long_double_bit (gdbarch
, 16 * TARGET_CHAR_BIT
);
2988 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2989 set_gdbarch_max_register_raw_size (gdbarch
, 8);
2990 set_gdbarch_max_register_virtual_size (gdbarch
, 8);
2991 set_gdbarch_pop_frame (gdbarch
, sparc_pop_frame
);
2992 set_gdbarch_push_return_address (gdbarch
, sparc_push_return_address
);
2993 set_gdbarch_push_dummy_frame (gdbarch
, sparc_push_dummy_frame
);
2994 set_gdbarch_read_pc (gdbarch
, generic_target_read_pc
);
2995 set_gdbarch_register_convert_to_raw (gdbarch
, sparc_convert_to_raw
);
2996 set_gdbarch_register_convert_to_virtual (gdbarch
,
2997 sparc_convert_to_virtual
);
2998 set_gdbarch_register_convertible (gdbarch
,
2999 generic_register_convertible_not
);
3000 set_gdbarch_reg_struct_has_addr (gdbarch
, sparc_reg_struct_has_addr
);
3001 set_gdbarch_return_value_on_stack (gdbarch
, sparc_return_value_on_stack
);
3002 set_gdbarch_saved_pc_after_call (gdbarch
, sparc_saved_pc_after_call
);
3003 set_gdbarch_prologue_frameless_p (gdbarch
, sparc_prologue_frameless_p
);
3004 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
3005 set_gdbarch_skip_prologue (gdbarch
, sparc_skip_prologue
);
3006 set_gdbarch_sp_regnum (gdbarch
, SPARC_SP_REGNUM
);
3007 set_gdbarch_use_generic_dummy_frames (gdbarch
, 0);
3008 set_gdbarch_write_pc (gdbarch
, generic_target_write_pc
);
3011 * Settings that depend only on 32/64 bit word size
3014 switch (info
.bfd_arch_info
->mach
)
3016 case bfd_mach_sparc
:
3017 case bfd_mach_sparc_sparclet
:
3018 case bfd_mach_sparc_sparclite
:
3019 case bfd_mach_sparc_v8plus
:
3020 case bfd_mach_sparc_v8plusa
:
3021 case bfd_mach_sparc_sparclite_le
:
3022 /* 32-bit machine types: */
3024 #ifdef SPARC32_CALL_DUMMY_ON_STACK
3025 set_gdbarch_pc_in_call_dummy (gdbarch
, pc_in_call_dummy_on_stack
);
3026 set_gdbarch_call_dummy_address (gdbarch
, sparc_call_dummy_address
);
3027 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0x30);
3028 set_gdbarch_call_dummy_length (gdbarch
, 0x38);
3030 /* NOTE: cagney/2002-04-26: Based from info posted by Peter
3031 Schauer around Oct '99. Briefly, due to aspects of the SPARC
3032 ABI, it isn't possible to use ON_STACK with a strictly
3035 Peter Schauer writes ...
3037 No, any call from GDB to a user function returning a
3038 struct/union will fail miserably. Try this:
3057 for (i = 0; i < 4; i++)
3063 Set a breakpoint at the gx = sret () statement, run to it and
3064 issue a `print sret()'. It will not succed with your
3065 approach, and I doubt that continuing the program will work
3068 For details of the ABI see the Sparc Architecture Manual. I
3069 have Version 8 (Prentice Hall ISBN 0-13-825001-4) and the
3070 calling conventions for functions returning aggregate values
3071 are explained in Appendix D.3. */
3073 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
3074 set_gdbarch_call_dummy_words (gdbarch
, call_dummy_32
);
3076 set_gdbarch_pc_in_call_dummy (gdbarch
, pc_in_call_dummy_at_entry_point
);
3077 set_gdbarch_call_dummy_address (gdbarch
, entry_point_address
);
3078 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0);
3079 set_gdbarch_call_dummy_length (gdbarch
, 0);
3080 set_gdbarch_call_dummy_location (gdbarch
, AT_ENTRY_POINT
);
3081 set_gdbarch_call_dummy_words (gdbarch
, call_dummy_nil
);
3083 set_gdbarch_call_dummy_stack_adjust (gdbarch
, 68);
3084 set_gdbarch_call_dummy_start_offset (gdbarch
, 0);
3085 set_gdbarch_frame_args_skip (gdbarch
, 68);
3086 set_gdbarch_function_start_offset (gdbarch
, 0);
3087 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
3088 set_gdbarch_npc_regnum (gdbarch
, SPARC32_NPC_REGNUM
);
3089 set_gdbarch_pc_regnum (gdbarch
, SPARC32_PC_REGNUM
);
3090 set_gdbarch_ptr_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
3091 set_gdbarch_push_arguments (gdbarch
, sparc32_push_arguments
);
3092 set_gdbarch_read_fp (gdbarch
, generic_target_read_fp
);
3093 set_gdbarch_read_sp (gdbarch
, generic_target_read_sp
);
3095 set_gdbarch_register_byte (gdbarch
, sparc32_register_byte
);
3096 set_gdbarch_register_raw_size (gdbarch
, sparc32_register_size
);
3097 set_gdbarch_register_size (gdbarch
, 4);
3098 set_gdbarch_register_virtual_size (gdbarch
, sparc32_register_size
);
3099 set_gdbarch_register_virtual_type (gdbarch
,
3100 sparc32_register_virtual_type
);
3101 #ifdef SPARC32_CALL_DUMMY_ON_STACK
3102 set_gdbarch_sizeof_call_dummy_words (gdbarch
, sizeof (call_dummy_32
));
3104 set_gdbarch_sizeof_call_dummy_words (gdbarch
, 0);
3106 set_gdbarch_stack_align (gdbarch
, sparc32_stack_align
);
3107 set_gdbarch_store_struct_return (gdbarch
, sparc32_store_struct_return
);
3108 set_gdbarch_use_struct_convention (gdbarch
,
3109 generic_use_struct_convention
);
3110 set_gdbarch_write_sp (gdbarch
, generic_target_write_sp
);
3111 tdep
->y_regnum
= SPARC32_Y_REGNUM
;
3112 tdep
->fp_max_regnum
= SPARC_FP0_REGNUM
+ 32;
3113 tdep
->intreg_size
= 4;
3114 tdep
->reg_save_offset
= 0x60;
3115 tdep
->call_dummy_call_offset
= 0x24;
3118 case bfd_mach_sparc_v9
:
3119 case bfd_mach_sparc_v9a
:
3120 /* 64-bit machine types: */
3121 default: /* Any new machine type is likely to be 64-bit. */
3123 #ifdef SPARC64_CALL_DUMMY_ON_STACK
3124 set_gdbarch_pc_in_call_dummy (gdbarch
, pc_in_call_dummy_on_stack
);
3125 set_gdbarch_call_dummy_address (gdbarch
, sparc_call_dummy_address
);
3126 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 8 * 4);
3127 set_gdbarch_call_dummy_length (gdbarch
, 192);
3128 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
3129 set_gdbarch_call_dummy_start_offset (gdbarch
, 148);
3130 set_gdbarch_call_dummy_words (gdbarch
, call_dummy_64
);
3132 set_gdbarch_pc_in_call_dummy (gdbarch
, pc_in_call_dummy_at_entry_point
);
3133 set_gdbarch_call_dummy_address (gdbarch
, entry_point_address
);
3134 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0);
3135 set_gdbarch_call_dummy_length (gdbarch
, 0);
3136 set_gdbarch_call_dummy_location (gdbarch
, AT_ENTRY_POINT
);
3137 set_gdbarch_call_dummy_start_offset (gdbarch
, 0);
3138 set_gdbarch_call_dummy_words (gdbarch
, call_dummy_nil
);
3140 set_gdbarch_call_dummy_stack_adjust (gdbarch
, 128);
3141 set_gdbarch_frame_args_skip (gdbarch
, 136);
3142 set_gdbarch_function_start_offset (gdbarch
, 0);
3143 set_gdbarch_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
3144 set_gdbarch_npc_regnum (gdbarch
, SPARC64_NPC_REGNUM
);
3145 set_gdbarch_pc_regnum (gdbarch
, SPARC64_PC_REGNUM
);
3146 set_gdbarch_ptr_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
3147 set_gdbarch_push_arguments (gdbarch
, sparc64_push_arguments
);
3148 /* NOTE different for at_entry */
3149 set_gdbarch_read_fp (gdbarch
, sparc64_read_fp
);
3150 set_gdbarch_read_sp (gdbarch
, sparc64_read_sp
);
3151 /* Some of the registers aren't 64 bits, but it's a lot simpler just
3152 to assume they all are (since most of them are). */
3153 set_gdbarch_register_byte (gdbarch
, sparc64_register_byte
);
3154 set_gdbarch_register_raw_size (gdbarch
, sparc64_register_size
);
3155 set_gdbarch_register_size (gdbarch
, 8);
3156 set_gdbarch_register_virtual_size (gdbarch
, sparc64_register_size
);
3157 set_gdbarch_register_virtual_type (gdbarch
,
3158 sparc64_register_virtual_type
);
3159 #ifdef SPARC64_CALL_DUMMY_ON_STACK
3160 set_gdbarch_sizeof_call_dummy_words (gdbarch
, sizeof (call_dummy_64
));
3162 set_gdbarch_sizeof_call_dummy_words (gdbarch
, 0);
3164 set_gdbarch_stack_align (gdbarch
, sparc64_stack_align
);
3165 set_gdbarch_store_struct_return (gdbarch
, sparc64_store_struct_return
);
3166 set_gdbarch_use_struct_convention (gdbarch
,
3167 sparc64_use_struct_convention
);
3168 set_gdbarch_write_sp (gdbarch
, sparc64_write_sp
);
3169 tdep
->y_regnum
= SPARC64_Y_REGNUM
;
3170 tdep
->fp_max_regnum
= SPARC_FP0_REGNUM
+ 48;
3171 tdep
->intreg_size
= 8;
3172 tdep
->reg_save_offset
= 0x90;
3173 tdep
->call_dummy_call_offset
= 148 + 4 * 5;
3178 * Settings that vary per-architecture:
3181 switch (info
.bfd_arch_info
->mach
)
3183 case bfd_mach_sparc
:
3184 set_gdbarch_extract_return_value (gdbarch
, sparc32_extract_return_value
);
3185 set_gdbarch_frame_chain_valid (gdbarch
, file_frame_chain_valid
);
3186 set_gdbarch_num_regs (gdbarch
, 72);
3187 set_gdbarch_register_bytes (gdbarch
, 32*4 + 32*4 + 8*4);
3188 set_gdbarch_register_name (gdbarch
, sparc32_register_name
);
3189 set_gdbarch_store_return_value (gdbarch
, sparc_store_return_value
);
3190 tdep
->has_fpu
= 1; /* (all but sparclet and sparclite) */
3191 tdep
->fp_register_bytes
= 32 * 4;
3192 tdep
->print_insn_mach
= bfd_mach_sparc
;
3194 case bfd_mach_sparc_sparclet
:
3195 set_gdbarch_extract_return_value (gdbarch
,
3196 sparclet_extract_return_value
);
3197 set_gdbarch_frame_chain_valid (gdbarch
, file_frame_chain_valid
);
3198 set_gdbarch_num_regs (gdbarch
, 32 + 32 + 8 + 8 + 8);
3199 set_gdbarch_register_bytes (gdbarch
, 32*4 + 32*4 + 8*4 + 8*4 + 8*4);
3200 set_gdbarch_register_name (gdbarch
, sparclet_register_name
);
3201 set_gdbarch_store_return_value (gdbarch
, sparclet_store_return_value
);
3202 tdep
->has_fpu
= 0; /* (all but sparclet and sparclite) */
3203 tdep
->fp_register_bytes
= 0;
3204 tdep
->print_insn_mach
= bfd_mach_sparc_sparclet
;
3206 case bfd_mach_sparc_sparclite
:
3207 set_gdbarch_extract_return_value (gdbarch
, sparc32_extract_return_value
);
3208 set_gdbarch_frame_chain_valid (gdbarch
, func_frame_chain_valid
);
3209 set_gdbarch_num_regs (gdbarch
, 80);
3210 set_gdbarch_register_bytes (gdbarch
, 32*4 + 32*4 + 8*4 + 8*4);
3211 set_gdbarch_register_name (gdbarch
, sparclite_register_name
);
3212 set_gdbarch_store_return_value (gdbarch
, sparc_store_return_value
);
3213 tdep
->has_fpu
= 0; /* (all but sparclet and sparclite) */
3214 tdep
->fp_register_bytes
= 0;
3215 tdep
->print_insn_mach
= bfd_mach_sparc_sparclite
;
3217 case bfd_mach_sparc_v8plus
:
3218 set_gdbarch_extract_return_value (gdbarch
, sparc32_extract_return_value
);
3219 set_gdbarch_frame_chain_valid (gdbarch
, file_frame_chain_valid
);
3220 set_gdbarch_num_regs (gdbarch
, 72);
3221 set_gdbarch_register_bytes (gdbarch
, 32*4 + 32*4 + 8*4);
3222 set_gdbarch_register_name (gdbarch
, sparc32_register_name
);
3223 set_gdbarch_store_return_value (gdbarch
, sparc_store_return_value
);
3224 tdep
->print_insn_mach
= bfd_mach_sparc
;
3225 tdep
->fp_register_bytes
= 32 * 4;
3226 tdep
->has_fpu
= 1; /* (all but sparclet and sparclite) */
3228 case bfd_mach_sparc_v8plusa
:
3229 set_gdbarch_extract_return_value (gdbarch
, sparc32_extract_return_value
);
3230 set_gdbarch_frame_chain_valid (gdbarch
, file_frame_chain_valid
);
3231 set_gdbarch_num_regs (gdbarch
, 72);
3232 set_gdbarch_register_bytes (gdbarch
, 32*4 + 32*4 + 8*4);
3233 set_gdbarch_register_name (gdbarch
, sparc32_register_name
);
3234 set_gdbarch_store_return_value (gdbarch
, sparc_store_return_value
);
3235 tdep
->has_fpu
= 1; /* (all but sparclet and sparclite) */
3236 tdep
->fp_register_bytes
= 32 * 4;
3237 tdep
->print_insn_mach
= bfd_mach_sparc
;
3239 case bfd_mach_sparc_sparclite_le
:
3240 set_gdbarch_extract_return_value (gdbarch
, sparc32_extract_return_value
);
3241 set_gdbarch_frame_chain_valid (gdbarch
, func_frame_chain_valid
);
3242 set_gdbarch_num_regs (gdbarch
, 80);
3243 set_gdbarch_register_bytes (gdbarch
, 32*4 + 32*4 + 8*4 + 8*4);
3244 set_gdbarch_register_name (gdbarch
, sparclite_register_name
);
3245 set_gdbarch_store_return_value (gdbarch
, sparc_store_return_value
);
3246 tdep
->has_fpu
= 0; /* (all but sparclet and sparclite) */
3247 tdep
->fp_register_bytes
= 0;
3248 tdep
->print_insn_mach
= bfd_mach_sparc_sparclite
;
3250 case bfd_mach_sparc_v9
:
3251 set_gdbarch_extract_return_value (gdbarch
, sparc64_extract_return_value
);
3252 set_gdbarch_frame_chain_valid (gdbarch
, file_frame_chain_valid
);
3253 set_gdbarch_num_regs (gdbarch
, 125);
3254 set_gdbarch_register_bytes (gdbarch
, 32*8 + 32*8 + 45*8);
3255 set_gdbarch_register_name (gdbarch
, sparc64_register_name
);
3256 set_gdbarch_store_return_value (gdbarch
, sparc_store_return_value
);
3257 tdep
->has_fpu
= 1; /* (all but sparclet and sparclite) */
3258 tdep
->fp_register_bytes
= 64 * 4;
3259 tdep
->print_insn_mach
= bfd_mach_sparc_v9a
;
3261 case bfd_mach_sparc_v9a
:
3262 set_gdbarch_extract_return_value (gdbarch
, sparc64_extract_return_value
);
3263 set_gdbarch_frame_chain_valid (gdbarch
, file_frame_chain_valid
);
3264 set_gdbarch_num_regs (gdbarch
, 125);
3265 set_gdbarch_register_bytes (gdbarch
, 32*8 + 32*8 + 45*8);
3266 set_gdbarch_register_name (gdbarch
, sparc64_register_name
);
3267 set_gdbarch_store_return_value (gdbarch
, sparc_store_return_value
);
3268 tdep
->has_fpu
= 1; /* (all but sparclet and sparclite) */
3269 tdep
->fp_register_bytes
= 64 * 4;
3270 tdep
->print_insn_mach
= bfd_mach_sparc_v9a
;