1 /* Target-dependent code for the SPARC for GDB, the GNU debugger.
2 Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
3 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 /* ??? Support for calling functions from gdb in sparc64 is unfinished. */
25 #include "arch-utils.h"
32 #include "gdb_string.h"
35 #include <sys/procfs.h>
36 /* Prototypes for supply_gregset etc. */
42 #include "symfile.h" /* for 'entry_point_address' */
45 * Some local macros that have multi-arch and non-multi-arch versions:
48 #if (GDB_MULTI_ARCH > 0)
50 /* Does the target have Floating Point registers? */
51 #define SPARC_HAS_FPU (gdbarch_tdep (current_gdbarch)->has_fpu)
52 /* Number of bytes devoted to Floating Point registers: */
53 #define FP_REGISTER_BYTES (gdbarch_tdep (current_gdbarch)->fp_register_bytes)
54 /* Highest numbered Floating Point register. */
55 #define FP_MAX_REGNUM (gdbarch_tdep (current_gdbarch)->fp_max_regnum)
56 /* Size of a general (integer) register: */
57 #define SPARC_INTREG_SIZE (gdbarch_tdep (current_gdbarch)->intreg_size)
58 /* Offset within the call dummy stack of the saved registers. */
59 #define DUMMY_REG_SAVE_OFFSET (gdbarch_tdep (current_gdbarch)->reg_save_offset)
61 #else /* non-multi-arch */
64 /* Does the target have Floating Point registers? */
65 #if defined(TARGET_SPARCLET) || defined(TARGET_SPARCLITE)
66 #define SPARC_HAS_FPU 0
68 #define SPARC_HAS_FPU 1
71 /* Number of bytes devoted to Floating Point registers: */
72 #if (GDB_TARGET_IS_SPARC64)
73 #define FP_REGISTER_BYTES (64 * 4)
76 #define FP_REGISTER_BYTES (32 * 4)
78 #define FP_REGISTER_BYTES 0
82 /* Highest numbered Floating Point register. */
83 #if (GDB_TARGET_IS_SPARC64)
84 #define FP_MAX_REGNUM (FP0_REGNUM + 48)
86 #define FP_MAX_REGNUM (FP0_REGNUM + 32)
89 /* Size of a general (integer) register: */
90 #define SPARC_INTREG_SIZE (REGISTER_RAW_SIZE (G0_REGNUM))
92 /* Offset within the call dummy stack of the saved registers. */
93 #if (GDB_TARGET_IS_SPARC64)
94 #define DUMMY_REG_SAVE_OFFSET (128 + 16)
96 #define DUMMY_REG_SAVE_OFFSET 0x60
99 #endif /* GDB_MULTI_ARCH */
104 int fp_register_bytes
;
109 int call_dummy_call_offset
;
113 /* Now make GDB_TARGET_IS_SPARC64 a runtime test. */
114 /* FIXME MVS: or try testing bfd_arch_info.arch and bfd_arch_info.mach ...
115 * define GDB_TARGET_IS_SPARC64 \
116 * (TARGET_ARCHITECTURE->arch == bfd_arch_sparc && \
117 * (TARGET_ARCHITECTURE->mach == bfd_mach_sparc_v9 || \
118 * TARGET_ARCHITECTURE->mach == bfd_mach_sparc_v9a))
122 extern int stop_after_trap
;
124 /* We don't store all registers immediately when requested, since they
125 get sent over in large chunks anyway. Instead, we accumulate most
126 of the changes and send them over once. "deferred_stores" keeps
127 track of which sets of registers we have locally-changed copies of,
128 so we only need send the groups that have changed. */
130 int deferred_stores
= 0; /* Accumulated stores we want to do eventually. */
133 /* Some machines, such as Fujitsu SPARClite 86x, have a bi-endian mode
134 where instructions are big-endian and data are little-endian.
135 This flag is set when we detect that the target is of this type. */
140 /* Fetch a single instruction. Even on bi-endian machines
141 such as sparc86x, instructions are always big-endian. */
144 fetch_instruction (CORE_ADDR pc
)
146 unsigned long retval
;
148 unsigned char buf
[4];
150 read_memory (pc
, buf
, sizeof (buf
));
152 /* Start at the most significant end of the integer, and work towards
153 the least significant. */
155 for (i
= 0; i
< sizeof (buf
); ++i
)
156 retval
= (retval
<< 8) | buf
[i
];
161 /* Branches with prediction are treated like their non-predicting cousins. */
162 /* FIXME: What about floating point branches? */
164 /* Macros to extract fields from sparc instructions. */
165 #define X_OP(i) (((i) >> 30) & 0x3)
166 #define X_RD(i) (((i) >> 25) & 0x1f)
167 #define X_A(i) (((i) >> 29) & 1)
168 #define X_COND(i) (((i) >> 25) & 0xf)
169 #define X_OP2(i) (((i) >> 22) & 0x7)
170 #define X_IMM22(i) ((i) & 0x3fffff)
171 #define X_OP3(i) (((i) >> 19) & 0x3f)
172 #define X_RS1(i) (((i) >> 14) & 0x1f)
173 #define X_I(i) (((i) >> 13) & 1)
174 #define X_IMM13(i) ((i) & 0x1fff)
175 /* Sign extension macros. */
176 #define X_SIMM13(i) ((X_IMM13 (i) ^ 0x1000) - 0x1000)
177 #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000)
178 #define X_CC(i) (((i) >> 20) & 3)
179 #define X_P(i) (((i) >> 19) & 1)
180 #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000)
181 #define X_RCOND(i) (((i) >> 25) & 7)
182 #define X_DISP16(i) ((((((i) >> 6) && 0xc000) | ((i) & 0x3fff)) ^ 0x8000) - 0x8000)
183 #define X_FCN(i) (((i) >> 25) & 31)
187 Error
, not_branch
, bicc
, bicca
, ba
, baa
, ticc
, ta
, done_retry
190 /* Simulate single-step ptrace call for sun4. Code written by Gary
191 Beihl (beihl@mcc.com). */
193 /* npc4 and next_pc describe the situation at the time that the
194 step-breakpoint was set, not necessary the current value of NPC_REGNUM. */
195 static CORE_ADDR next_pc
, npc4
, target
;
196 static int brknpc4
, brktrg
;
197 typedef char binsn_quantum
[BREAKPOINT_MAX
];
198 static binsn_quantum break_mem
[3];
200 static branch_type
isbranch (long, CORE_ADDR
, CORE_ADDR
*);
202 /* single_step() is called just before we want to resume the inferior,
203 if we want to single-step it but there is no hardware or kernel single-step
204 support (as on all SPARCs). We find all the possible targets of the
205 coming instruction and breakpoint them.
207 single_step is also called just after the inferior stops. If we had
208 set up a simulated single-step, we undo our damage. */
211 sparc_software_single_step (enum target_signal ignore
, /* pid, but we don't need it */
212 int insert_breakpoints_p
)
218 if (insert_breakpoints_p
)
220 /* Always set breakpoint for NPC. */
221 next_pc
= read_register (NPC_REGNUM
);
222 npc4
= next_pc
+ 4; /* branch not taken */
224 target_insert_breakpoint (next_pc
, break_mem
[0]);
225 /* printf_unfiltered ("set break at %x\n",next_pc); */
227 pc
= read_register (PC_REGNUM
);
228 pc_instruction
= fetch_instruction (pc
);
229 br
= isbranch (pc_instruction
, pc
, &target
);
230 brknpc4
= brktrg
= 0;
234 /* Conditional annulled branch will either end up at
235 npc (if taken) or at npc+4 (if not taken).
238 target_insert_breakpoint (npc4
, break_mem
[1]);
240 else if (br
== baa
&& target
!= next_pc
)
242 /* Unconditional annulled branch will always end up at
245 target_insert_breakpoint (target
, break_mem
[2]);
247 else if (GDB_TARGET_IS_SPARC64
&& br
== done_retry
)
250 target_insert_breakpoint (target
, break_mem
[2]);
255 /* Remove breakpoints */
256 target_remove_breakpoint (next_pc
, break_mem
[0]);
259 target_remove_breakpoint (npc4
, break_mem
[1]);
262 target_remove_breakpoint (target
, break_mem
[2]);
266 struct frame_extra_info
271 /* Following fields only relevant for flat frames. */
274 /* Add this to ->frame to get the value of the stack pointer at the
275 time of the register saves. */
279 /* Call this for each newly created frame. For SPARC, we need to
280 calculate the bottom of the frame, and do some extra work if the
281 prologue has been generated via the -mflat option to GCC. In
282 particular, we need to know where the previous fp and the pc have
283 been stashed, since their exact position within the frame may vary. */
286 sparc_init_extra_frame_info (int fromleaf
, struct frame_info
*fi
)
289 CORE_ADDR prologue_start
, prologue_end
;
292 fi
->extra_info
= (struct frame_extra_info
*)
293 frame_obstack_alloc (sizeof (struct frame_extra_info
));
294 frame_saved_regs_zalloc (fi
);
296 fi
->extra_info
->bottom
=
298 (fi
->frame
== fi
->next
->frame
? fi
->next
->extra_info
->bottom
:
299 fi
->next
->frame
) : read_sp ());
301 /* If fi->next is NULL, then we already set ->frame by passing read_fp()
302 to create_new_frame. */
307 buf
= alloca (MAX_REGISTER_RAW_SIZE
);
309 /* Compute ->frame as if not flat. If it is flat, we'll change
311 if (fi
->next
->next
!= NULL
312 && (fi
->next
->next
->signal_handler_caller
313 || frame_in_dummy (fi
->next
->next
))
314 && frameless_look_for_prologue (fi
->next
))
316 /* A frameless function interrupted by a signal did not change
317 the frame pointer, fix up frame pointer accordingly. */
318 fi
->frame
= FRAME_FP (fi
->next
);
319 fi
->extra_info
->bottom
= fi
->next
->extra_info
->bottom
;
323 /* Should we adjust for stack bias here? */
324 get_saved_register (buf
, 0, 0, fi
, FP_REGNUM
, 0);
325 fi
->frame
= extract_address (buf
, REGISTER_RAW_SIZE (FP_REGNUM
));
327 if (GDB_TARGET_IS_SPARC64
&& (fi
->frame
& 1))
332 /* Decide whether this is a function with a ``flat register window''
333 frame. For such functions, the frame pointer is actually in %i7. */
334 fi
->extra_info
->flat
= 0;
335 fi
->extra_info
->in_prologue
= 0;
336 if (find_pc_partial_function (fi
->pc
, &name
, &prologue_start
, &prologue_end
))
338 /* See if the function starts with an add (which will be of a
339 negative number if a flat frame) to the sp. FIXME: Does not
340 handle large frames which will need more than one instruction
342 insn
= fetch_instruction (prologue_start
);
343 if (X_OP (insn
) == 2 && X_RD (insn
) == 14 && X_OP3 (insn
) == 0
344 && X_I (insn
) && X_SIMM13 (insn
) < 0)
346 int offset
= X_SIMM13 (insn
);
348 /* Then look for a save of %i7 into the frame. */
349 insn
= fetch_instruction (prologue_start
+ 4);
353 && X_RS1 (insn
) == 14)
357 buf
= alloca (MAX_REGISTER_RAW_SIZE
);
359 /* We definitely have a flat frame now. */
360 fi
->extra_info
->flat
= 1;
362 fi
->extra_info
->sp_offset
= offset
;
364 /* Overwrite the frame's address with the value in %i7. */
365 get_saved_register (buf
, 0, 0, fi
, I7_REGNUM
, 0);
366 fi
->frame
= extract_address (buf
, REGISTER_RAW_SIZE (I7_REGNUM
));
368 if (GDB_TARGET_IS_SPARC64
&& (fi
->frame
& 1))
371 /* Record where the fp got saved. */
372 fi
->extra_info
->fp_addr
=
373 fi
->frame
+ fi
->extra_info
->sp_offset
+ X_SIMM13 (insn
);
375 /* Also try to collect where the pc got saved to. */
376 fi
->extra_info
->pc_addr
= 0;
377 insn
= fetch_instruction (prologue_start
+ 12);
381 && X_RS1 (insn
) == 14)
382 fi
->extra_info
->pc_addr
=
383 fi
->frame
+ fi
->extra_info
->sp_offset
+ X_SIMM13 (insn
);
388 /* Check if the PC is in the function prologue before a SAVE
389 instruction has been executed yet. If so, set the frame
390 to the current value of the stack pointer and set
391 the in_prologue flag. */
393 struct symtab_and_line sal
;
395 sal
= find_pc_line (prologue_start
, 0);
396 if (sal
.line
== 0) /* no line info, use PC */
397 prologue_end
= fi
->pc
;
398 else if (sal
.end
< prologue_end
)
399 prologue_end
= sal
.end
;
400 if (fi
->pc
< prologue_end
)
402 for (addr
= prologue_start
; addr
< fi
->pc
; addr
+= 4)
404 insn
= read_memory_integer (addr
, 4);
405 if (X_OP (insn
) == 2 && X_OP3 (insn
) == 0x3c)
406 break; /* SAVE seen, stop searching */
410 fi
->extra_info
->in_prologue
= 1;
411 fi
->frame
= read_register (SP_REGNUM
);
416 if (fi
->next
&& fi
->frame
== 0)
418 /* Kludge to cause init_prev_frame_info to destroy the new frame. */
419 fi
->frame
= fi
->next
->frame
;
420 fi
->pc
= fi
->next
->pc
;
425 sparc_frame_chain (struct frame_info
*frame
)
427 /* Value that will cause FRAME_CHAIN_VALID to not worry about the chain
428 value. If it really is zero, we detect it later in
429 sparc_init_prev_frame. */
430 return (CORE_ADDR
) 1;
434 sparc_extract_struct_value_address (char *regbuf
)
436 return extract_address (regbuf
+ REGISTER_BYTE (O0_REGNUM
),
437 REGISTER_RAW_SIZE (O0_REGNUM
));
440 /* Find the pc saved in frame FRAME. */
443 sparc_frame_saved_pc (struct frame_info
*frame
)
448 buf
= alloca (MAX_REGISTER_RAW_SIZE
);
449 if (frame
->signal_handler_caller
)
451 /* This is the signal trampoline frame.
452 Get the saved PC from the sigcontext structure. */
454 #ifndef SIGCONTEXT_PC_OFFSET
455 #define SIGCONTEXT_PC_OFFSET 12
458 CORE_ADDR sigcontext_addr
;
460 int saved_pc_offset
= SIGCONTEXT_PC_OFFSET
;
463 scbuf
= alloca (TARGET_PTR_BIT
/ HOST_CHAR_BIT
);
465 /* Solaris2 ucbsigvechandler passes a pointer to a sigcontext
466 as the third parameter. The offset to the saved pc is 12. */
467 find_pc_partial_function (frame
->pc
, &name
,
468 (CORE_ADDR
*) NULL
, (CORE_ADDR
*) NULL
);
469 if (name
&& STREQ (name
, "ucbsigvechandler"))
470 saved_pc_offset
= 12;
472 /* The sigcontext address is contained in register O2. */
473 get_saved_register (buf
, (int *) NULL
, (CORE_ADDR
*) NULL
,
474 frame
, O0_REGNUM
+ 2, (enum lval_type
*) NULL
);
475 sigcontext_addr
= extract_address (buf
, REGISTER_RAW_SIZE (O0_REGNUM
+ 2));
477 /* Don't cause a memory_error when accessing sigcontext in case the
478 stack layout has changed or the stack is corrupt. */
479 target_read_memory (sigcontext_addr
+ saved_pc_offset
,
480 scbuf
, sizeof (scbuf
));
481 return extract_address (scbuf
, sizeof (scbuf
));
483 else if (frame
->extra_info
->in_prologue
||
484 (frame
->next
!= NULL
&&
485 (frame
->next
->signal_handler_caller
||
486 frame_in_dummy (frame
->next
)) &&
487 frameless_look_for_prologue (frame
)))
489 /* A frameless function interrupted by a signal did not save
490 the PC, it is still in %o7. */
491 get_saved_register (buf
, (int *) NULL
, (CORE_ADDR
*) NULL
,
492 frame
, O7_REGNUM
, (enum lval_type
*) NULL
);
493 return PC_ADJUST (extract_address (buf
, SPARC_INTREG_SIZE
));
495 if (frame
->extra_info
->flat
)
496 addr
= frame
->extra_info
->pc_addr
;
498 addr
= frame
->extra_info
->bottom
+ FRAME_SAVED_I0
+
499 SPARC_INTREG_SIZE
* (I7_REGNUM
- I0_REGNUM
);
502 /* A flat frame leaf function might not save the PC anywhere,
503 just leave it in %o7. */
504 return PC_ADJUST (read_register (O7_REGNUM
));
506 read_memory (addr
, buf
, SPARC_INTREG_SIZE
);
507 return PC_ADJUST (extract_address (buf
, SPARC_INTREG_SIZE
));
510 /* Since an individual frame in the frame cache is defined by two
511 arguments (a frame pointer and a stack pointer), we need two
512 arguments to get info for an arbitrary stack frame. This routine
513 takes two arguments and makes the cached frames look as if these
514 two arguments defined a frame on the cache. This allows the rest
515 of info frame to extract the important arguments without
519 setup_arbitrary_frame (int argc
, CORE_ADDR
*argv
)
521 struct frame_info
*frame
;
524 error ("Sparc frame specifications require two arguments: fp and sp");
526 frame
= create_new_frame (argv
[0], 0);
529 internal_error (__FILE__
, __LINE__
,
530 "create_new_frame returned invalid frame");
532 frame
->extra_info
->bottom
= argv
[1];
533 frame
->pc
= FRAME_SAVED_PC (frame
);
537 /* Given a pc value, skip it forward past the function prologue by
538 disassembling instructions that appear to be a prologue.
540 If FRAMELESS_P is set, we are only testing to see if the function
541 is frameless. This allows a quicker answer.
543 This routine should be more specific in its actions; making sure
544 that it uses the same register in the initial prologue section. */
546 static CORE_ADDR
examine_prologue (CORE_ADDR
, int, struct frame_info
*,
550 examine_prologue (CORE_ADDR start_pc
, int frameless_p
, struct frame_info
*fi
,
551 CORE_ADDR
*saved_regs
)
555 CORE_ADDR pc
= start_pc
;
558 insn
= fetch_instruction (pc
);
560 /* Recognize the `sethi' insn and record its destination. */
561 if (X_OP (insn
) == 0 && X_OP2 (insn
) == 4)
565 insn
= fetch_instruction (pc
);
568 /* Recognize an add immediate value to register to either %g1 or
569 the destination register recorded above. Actually, this might
570 well recognize several different arithmetic operations.
571 It doesn't check that rs1 == rd because in theory "sub %g0, 5, %g1"
572 followed by "save %sp, %g1, %sp" is a valid prologue (Not that
573 I imagine any compiler really does that, however). */
576 && (X_RD (insn
) == 1 || X_RD (insn
) == dest
))
579 insn
= fetch_instruction (pc
);
582 /* Recognize any SAVE insn. */
583 if (X_OP (insn
) == 2 && X_OP3 (insn
) == 60)
586 if (frameless_p
) /* If the save is all we care about, */
587 return pc
; /* return before doing more work */
588 insn
= fetch_instruction (pc
);
590 /* Recognize add to %sp. */
591 else if (X_OP (insn
) == 2 && X_RD (insn
) == 14 && X_OP3 (insn
) == 0)
594 if (frameless_p
) /* If the add is all we care about, */
595 return pc
; /* return before doing more work */
597 insn
= fetch_instruction (pc
);
598 /* Recognize store of frame pointer (i7). */
602 && X_RS1 (insn
) == 14)
605 insn
= fetch_instruction (pc
);
607 /* Recognize sub %sp, <anything>, %i7. */
610 && X_RS1 (insn
) == 14
611 && X_RD (insn
) == 31)
614 insn
= fetch_instruction (pc
);
623 /* Without a save or add instruction, it's not a prologue. */
628 /* Recognize stores into the frame from the input registers.
629 This recognizes all non alternate stores of an input register,
630 into a location offset from the frame pointer between
633 /* The above will fail for arguments that are promoted
634 (eg. shorts to ints or floats to doubles), because the compiler
635 will pass them in positive-offset frame space, but the prologue
636 will save them (after conversion) in negative frame space at an
637 unpredictable offset. Therefore I am going to remove the
638 restriction on the target-address of the save, on the theory
639 that any unbroken sequence of saves from input registers must
640 be part of the prologue. In un-optimized code (at least), I'm
641 fairly sure that the compiler would emit SOME other instruction
642 (eg. a move or add) before emitting another save that is actually
643 a part of the function body.
645 Besides, the reserved stack space is different for SPARC64 anyway.
650 && (X_OP3 (insn
) & 0x3c) == 4 /* Store, non-alternate. */
651 && (X_RD (insn
) & 0x18) == 0x18 /* Input register. */
652 && X_I (insn
) /* Immediate mode. */
653 && X_RS1 (insn
) == 30) /* Off of frame pointer. */
654 ; /* empty statement -- fall thru to end of loop */
655 else if (GDB_TARGET_IS_SPARC64
657 && (X_OP3 (insn
) & 0x3c) == 12 /* store, extended (64-bit) */
658 && (X_RD (insn
) & 0x18) == 0x18 /* input register */
659 && X_I (insn
) /* immediate mode */
660 && X_RS1 (insn
) == 30) /* off of frame pointer */
661 ; /* empty statement -- fall thru to end of loop */
662 else if (X_OP (insn
) == 3
663 && (X_OP3 (insn
) & 0x3c) == 36 /* store, floating-point */
664 && X_I (insn
) /* immediate mode */
665 && X_RS1 (insn
) == 30) /* off of frame pointer */
666 ; /* empty statement -- fall thru to end of loop */
669 && X_OP3 (insn
) == 4 /* store? */
670 && X_RS1 (insn
) == 14) /* off of frame pointer */
672 if (saved_regs
&& X_I (insn
))
673 saved_regs
[X_RD (insn
)] =
674 fi
->frame
+ fi
->extra_info
->sp_offset
+ X_SIMM13 (insn
);
679 insn
= fetch_instruction (pc
);
686 sparc_skip_prologue (CORE_ADDR start_pc
, int frameless_p
)
688 return examine_prologue (start_pc
, frameless_p
, NULL
, NULL
);
691 /* Check instruction at ADDR to see if it is a branch.
692 All non-annulled instructions will go to NPC or will trap.
693 Set *TARGET if we find a candidate branch; set to zero if not.
695 This isn't static as it's used by remote-sa.sparc.c. */
698 isbranch (long instruction
, CORE_ADDR addr
, CORE_ADDR
*target
)
700 branch_type val
= not_branch
;
701 long int offset
= 0; /* Must be signed for sign-extend. */
705 if (X_OP (instruction
) == 0
706 && (X_OP2 (instruction
) == 2
707 || X_OP2 (instruction
) == 6
708 || X_OP2 (instruction
) == 1
709 || X_OP2 (instruction
) == 3
710 || X_OP2 (instruction
) == 5
711 || (GDB_TARGET_IS_SPARC64
&& X_OP2 (instruction
) == 7)))
713 if (X_COND (instruction
) == 8)
714 val
= X_A (instruction
) ? baa
: ba
;
716 val
= X_A (instruction
) ? bicca
: bicc
;
717 switch (X_OP2 (instruction
))
720 if (!GDB_TARGET_IS_SPARC64
)
725 offset
= 4 * X_DISP22 (instruction
);
729 offset
= 4 * X_DISP19 (instruction
);
732 offset
= 4 * X_DISP16 (instruction
);
735 *target
= addr
+ offset
;
737 else if (GDB_TARGET_IS_SPARC64
738 && X_OP (instruction
) == 2
739 && X_OP3 (instruction
) == 62)
741 if (X_FCN (instruction
) == 0)
744 *target
= read_register (TNPC_REGNUM
);
747 else if (X_FCN (instruction
) == 1)
750 *target
= read_register (TPC_REGNUM
);
758 /* Find register number REGNUM relative to FRAME and put its
759 (raw) contents in *RAW_BUFFER. Set *OPTIMIZED if the variable
760 was optimized out (and thus can't be fetched). If the variable
761 was fetched from memory, set *ADDRP to where it was fetched from,
762 otherwise it was fetched from a register.
764 The argument RAW_BUFFER must point to aligned memory. */
767 sparc_get_saved_register (char *raw_buffer
, int *optimized
, CORE_ADDR
*addrp
,
768 struct frame_info
*frame
, int regnum
,
769 enum lval_type
*lval
)
771 struct frame_info
*frame1
;
774 if (!target_has_registers
)
775 error ("No registers.");
782 /* FIXME This code extracted from infcmd.c; should put elsewhere! */
785 /* error ("No selected frame."); */
786 if (!target_has_registers
)
787 error ("The program has no registers now.");
788 if (selected_frame
== NULL
)
789 error ("No selected frame.");
790 /* Try to use selected frame */
791 frame
= get_prev_frame (selected_frame
);
793 error ("Cmd not meaningful in the outermost frame.");
797 frame1
= frame
->next
;
799 /* Get saved PC from the frame info if not in innermost frame. */
800 if (regnum
== PC_REGNUM
&& frame1
!= NULL
)
804 if (raw_buffer
!= NULL
)
806 /* Put it back in target format. */
807 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
), frame
->pc
);
814 while (frame1
!= NULL
)
816 /* FIXME MVS: wrong test for dummy frame at entry. */
818 if (frame1
->pc
>= (frame1
->extra_info
->bottom
?
819 frame1
->extra_info
->bottom
: read_sp ())
820 && frame1
->pc
<= FRAME_FP (frame1
))
822 /* Dummy frame. All but the window regs are in there somewhere.
823 The window registers are saved on the stack, just like in a
825 if (regnum
>= G1_REGNUM
&& regnum
< G1_REGNUM
+ 7)
826 addr
= frame1
->frame
+ (regnum
- G0_REGNUM
) * SPARC_INTREG_SIZE
827 - (FP_REGISTER_BYTES
+ 8 * SPARC_INTREG_SIZE
);
828 else if (regnum
>= I0_REGNUM
&& regnum
< I0_REGNUM
+ 8)
829 addr
= (frame1
->prev
->extra_info
->bottom
830 + (regnum
- I0_REGNUM
) * SPARC_INTREG_SIZE
832 else if (regnum
>= L0_REGNUM
&& regnum
< L0_REGNUM
+ 8)
833 addr
= (frame1
->prev
->extra_info
->bottom
834 + (regnum
- L0_REGNUM
) * SPARC_INTREG_SIZE
836 else if (regnum
>= O0_REGNUM
&& regnum
< O0_REGNUM
+ 8)
837 addr
= frame1
->frame
+ (regnum
- O0_REGNUM
) * SPARC_INTREG_SIZE
838 - (FP_REGISTER_BYTES
+ 16 * SPARC_INTREG_SIZE
);
839 else if (SPARC_HAS_FPU
&&
840 regnum
>= FP0_REGNUM
&& regnum
< FP0_REGNUM
+ 32)
841 addr
= frame1
->frame
+ (regnum
- FP0_REGNUM
) * 4
842 - (FP_REGISTER_BYTES
);
843 else if (GDB_TARGET_IS_SPARC64
&& SPARC_HAS_FPU
&&
844 regnum
>= FP0_REGNUM
+ 32 && regnum
< FP_MAX_REGNUM
)
845 addr
= frame1
->frame
+ 32 * 4 + (regnum
- FP0_REGNUM
- 32) * 8
846 - (FP_REGISTER_BYTES
);
847 else if (regnum
>= Y_REGNUM
&& regnum
< NUM_REGS
)
848 addr
= frame1
->frame
+ (regnum
- Y_REGNUM
) * SPARC_INTREG_SIZE
849 - (FP_REGISTER_BYTES
+ 24 * SPARC_INTREG_SIZE
);
851 else if (frame1
->extra_info
->flat
)
854 if (regnum
== RP_REGNUM
)
855 addr
= frame1
->extra_info
->pc_addr
;
856 else if (regnum
== I7_REGNUM
)
857 addr
= frame1
->extra_info
->fp_addr
;
860 CORE_ADDR func_start
;
863 regs
= alloca (NUM_REGS
* sizeof (CORE_ADDR
));
864 memset (regs
, 0, NUM_REGS
* sizeof (CORE_ADDR
));
866 find_pc_partial_function (frame1
->pc
, NULL
, &func_start
, NULL
);
867 examine_prologue (func_start
, 0, frame1
, regs
);
873 /* Normal frame. Local and In registers are saved on stack. */
874 if (regnum
>= I0_REGNUM
&& regnum
< I0_REGNUM
+ 8)
875 addr
= (frame1
->prev
->extra_info
->bottom
876 + (regnum
- I0_REGNUM
) * SPARC_INTREG_SIZE
878 else if (regnum
>= L0_REGNUM
&& regnum
< L0_REGNUM
+ 8)
879 addr
= (frame1
->prev
->extra_info
->bottom
880 + (regnum
- L0_REGNUM
) * SPARC_INTREG_SIZE
882 else if (regnum
>= O0_REGNUM
&& regnum
< O0_REGNUM
+ 8)
884 /* Outs become ins. */
885 get_saved_register (raw_buffer
, optimized
, addrp
, frame1
,
886 (regnum
- O0_REGNUM
+ I0_REGNUM
), lval
);
892 frame1
= frame1
->next
;
898 if (regnum
== SP_REGNUM
)
900 if (raw_buffer
!= NULL
)
902 /* Put it back in target format. */
903 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
), addr
);
909 if (raw_buffer
!= NULL
)
910 read_memory (addr
, raw_buffer
, REGISTER_RAW_SIZE (regnum
));
915 *lval
= lval_register
;
916 addr
= REGISTER_BYTE (regnum
);
917 if (raw_buffer
!= NULL
)
918 read_register_gen (regnum
, raw_buffer
);
924 /* Push an empty stack frame, and record in it the current PC, regs, etc.
926 We save the non-windowed registers and the ins. The locals and outs
927 are new; they don't need to be saved. The i's and l's of
928 the last frame were already saved on the stack. */
930 /* Definitely see tm-sparc.h for more doc of the frame format here. */
932 /* See tm-sparc.h for how this is calculated. */
934 #define DUMMY_STACK_REG_BUF_SIZE \
935 (((8+8+8) * SPARC_INTREG_SIZE) + FP_REGISTER_BYTES)
936 #define DUMMY_STACK_SIZE \
937 (DUMMY_STACK_REG_BUF_SIZE + DUMMY_REG_SAVE_OFFSET)
940 sparc_push_dummy_frame (void)
942 CORE_ADDR sp
, old_sp
;
945 register_temp
= alloca (DUMMY_STACK_SIZE
);
947 old_sp
= sp
= read_sp ();
949 if (GDB_TARGET_IS_SPARC64
)
951 /* PC, NPC, CCR, FSR, FPRS, Y, ASI */
952 read_register_bytes (REGISTER_BYTE (PC_REGNUM
), ®ister_temp
[0],
953 REGISTER_RAW_SIZE (PC_REGNUM
) * 7);
954 read_register_bytes (REGISTER_BYTE (PSTATE_REGNUM
),
955 ®ister_temp
[7 * SPARC_INTREG_SIZE
],
956 REGISTER_RAW_SIZE (PSTATE_REGNUM
));
957 /* FIXME: not sure what needs to be saved here. */
961 /* Y, PS, WIM, TBR, PC, NPC, FPS, CPS regs */
962 read_register_bytes (REGISTER_BYTE (Y_REGNUM
), ®ister_temp
[0],
963 REGISTER_RAW_SIZE (Y_REGNUM
) * 8);
966 read_register_bytes (REGISTER_BYTE (O0_REGNUM
),
967 ®ister_temp
[8 * SPARC_INTREG_SIZE
],
968 SPARC_INTREG_SIZE
* 8);
970 read_register_bytes (REGISTER_BYTE (G0_REGNUM
),
971 ®ister_temp
[16 * SPARC_INTREG_SIZE
],
972 SPARC_INTREG_SIZE
* 8);
975 read_register_bytes (REGISTER_BYTE (FP0_REGNUM
),
976 ®ister_temp
[24 * SPARC_INTREG_SIZE
],
979 sp
-= DUMMY_STACK_SIZE
;
983 write_memory (sp
+ DUMMY_REG_SAVE_OFFSET
, ®ister_temp
[0],
984 DUMMY_STACK_REG_BUF_SIZE
);
986 if (strcmp (target_shortname
, "sim") != 0)
990 /* Set return address register for the call dummy to the current PC. */
991 write_register (I7_REGNUM
, read_pc () - 8);
995 /* The call dummy will write this value to FP before executing
996 the 'save'. This ensures that register window flushes work
997 correctly in the simulator. */
998 write_register (G0_REGNUM
+ 1, read_register (FP_REGNUM
));
1000 /* The call dummy will write this value to FP after executing
1002 write_register (G0_REGNUM
+ 2, old_sp
);
1004 /* The call dummy will write this value to the return address (%i7) after
1005 executing the 'save'. */
1006 write_register (G0_REGNUM
+ 3, read_pc () - 8);
1008 /* Set the FP that the call dummy will be using after the 'save'.
1009 This makes backtraces from an inferior function call work properly. */
1010 write_register (FP_REGNUM
, old_sp
);
1014 /* sparc_frame_find_saved_regs (). This function is here only because
1015 pop_frame uses it. Note there is an interesting corner case which
1016 I think few ports of GDB get right--if you are popping a frame
1017 which does not save some register that *is* saved by a more inner
1018 frame (such a frame will never be a dummy frame because dummy
1019 frames save all registers). Rewriting pop_frame to use
1020 get_saved_register would solve this problem and also get rid of the
1021 ugly duplication between sparc_frame_find_saved_regs and
1024 Stores, into an array of CORE_ADDR,
1025 the addresses of the saved registers of frame described by FRAME_INFO.
1026 This includes special registers such as pc and fp saved in special
1027 ways in the stack frame. sp is even more special:
1028 the address we return for it IS the sp for the next frame.
1030 Note that on register window machines, we are currently making the
1031 assumption that window registers are being saved somewhere in the
1032 frame in which they are being used. If they are stored in an
1033 inferior frame, find_saved_register will break.
1035 On the Sun 4, the only time all registers are saved is when
1036 a dummy frame is involved. Otherwise, the only saved registers
1037 are the LOCAL and IN registers which are saved as a result
1038 of the "save/restore" opcodes. This condition is determined
1039 by address rather than by value.
1041 The "pc" is not stored in a frame on the SPARC. (What is stored
1042 is a return address minus 8.) sparc_pop_frame knows how to
1043 deal with that. Other routines might or might not.
1045 See tm-sparc.h (PUSH_DUMMY_FRAME and friends) for CRITICAL information
1046 about how this works. */
1048 static void sparc_frame_find_saved_regs (struct frame_info
*, CORE_ADDR
*);
1051 sparc_frame_find_saved_regs (struct frame_info
*fi
, CORE_ADDR
*saved_regs_addr
)
1053 register int regnum
;
1054 CORE_ADDR frame_addr
= FRAME_FP (fi
);
1057 internal_error (__FILE__
, __LINE__
,
1058 "Bad frame info struct in FRAME_FIND_SAVED_REGS");
1060 memset (saved_regs_addr
, 0, NUM_REGS
* sizeof (CORE_ADDR
));
1062 if (fi
->pc
>= (fi
->extra_info
->bottom
?
1063 fi
->extra_info
->bottom
: read_sp ())
1064 && fi
->pc
<= FRAME_FP (fi
))
1066 /* Dummy frame. All but the window regs are in there somewhere. */
1067 for (regnum
= G1_REGNUM
; regnum
< G1_REGNUM
+ 7; regnum
++)
1068 saved_regs_addr
[regnum
] =
1069 frame_addr
+ (regnum
- G0_REGNUM
) * SPARC_INTREG_SIZE
1070 - DUMMY_STACK_REG_BUF_SIZE
+ 16 * SPARC_INTREG_SIZE
;
1072 for (regnum
= I0_REGNUM
; regnum
< I0_REGNUM
+ 8; regnum
++)
1073 saved_regs_addr
[regnum
] =
1074 frame_addr
+ (regnum
- I0_REGNUM
) * SPARC_INTREG_SIZE
1075 - DUMMY_STACK_REG_BUF_SIZE
+ 8 * SPARC_INTREG_SIZE
;
1078 for (regnum
= FP0_REGNUM
; regnum
< FP_MAX_REGNUM
; regnum
++)
1079 saved_regs_addr
[regnum
] = frame_addr
+ (regnum
- FP0_REGNUM
) * 4
1080 - DUMMY_STACK_REG_BUF_SIZE
+ 24 * SPARC_INTREG_SIZE
;
1082 if (GDB_TARGET_IS_SPARC64
)
1084 for (regnum
= PC_REGNUM
; regnum
< PC_REGNUM
+ 7; regnum
++)
1086 saved_regs_addr
[regnum
] =
1087 frame_addr
+ (regnum
- PC_REGNUM
) * SPARC_INTREG_SIZE
1088 - DUMMY_STACK_REG_BUF_SIZE
;
1090 saved_regs_addr
[PSTATE_REGNUM
] =
1091 frame_addr
+ 8 * SPARC_INTREG_SIZE
- DUMMY_STACK_REG_BUF_SIZE
;
1094 for (regnum
= Y_REGNUM
; regnum
< NUM_REGS
; regnum
++)
1095 saved_regs_addr
[regnum
] =
1096 frame_addr
+ (regnum
- Y_REGNUM
) * SPARC_INTREG_SIZE
1097 - DUMMY_STACK_REG_BUF_SIZE
;
1099 frame_addr
= fi
->extra_info
->bottom
?
1100 fi
->extra_info
->bottom
: read_sp ();
1102 else if (fi
->extra_info
->flat
)
1104 CORE_ADDR func_start
;
1105 find_pc_partial_function (fi
->pc
, NULL
, &func_start
, NULL
);
1106 examine_prologue (func_start
, 0, fi
, saved_regs_addr
);
1108 /* Flat register window frame. */
1109 saved_regs_addr
[RP_REGNUM
] = fi
->extra_info
->pc_addr
;
1110 saved_regs_addr
[I7_REGNUM
] = fi
->extra_info
->fp_addr
;
1114 /* Normal frame. Just Local and In registers */
1115 frame_addr
= fi
->extra_info
->bottom
?
1116 fi
->extra_info
->bottom
: read_sp ();
1117 for (regnum
= L0_REGNUM
; regnum
< L0_REGNUM
+ 8; regnum
++)
1118 saved_regs_addr
[regnum
] =
1119 (frame_addr
+ (regnum
- L0_REGNUM
) * SPARC_INTREG_SIZE
1121 for (regnum
= I0_REGNUM
; regnum
< I0_REGNUM
+ 8; regnum
++)
1122 saved_regs_addr
[regnum
] =
1123 (frame_addr
+ (regnum
- I0_REGNUM
) * SPARC_INTREG_SIZE
1128 if (fi
->extra_info
->flat
)
1130 saved_regs_addr
[O7_REGNUM
] = fi
->extra_info
->pc_addr
;
1134 /* Pull off either the next frame pointer or the stack pointer */
1135 CORE_ADDR next_next_frame_addr
=
1136 (fi
->next
->extra_info
->bottom
?
1137 fi
->next
->extra_info
->bottom
: read_sp ());
1138 for (regnum
= O0_REGNUM
; regnum
< O0_REGNUM
+ 8; regnum
++)
1139 saved_regs_addr
[regnum
] =
1140 (next_next_frame_addr
1141 + (regnum
- O0_REGNUM
) * SPARC_INTREG_SIZE
1145 /* Otherwise, whatever we would get from ptrace(GETREGS) is accurate */
1146 /* FIXME -- should this adjust for the sparc64 offset? */
1147 saved_regs_addr
[SP_REGNUM
] = FRAME_FP (fi
);
1150 /* Discard from the stack the innermost frame, restoring all saved registers.
1152 Note that the values stored in fsr by get_frame_saved_regs are *in
1153 the context of the called frame*. What this means is that the i
1154 regs of fsr must be restored into the o regs of the (calling) frame that
1155 we pop into. We don't care about the output regs of the calling frame,
1156 since unless it's a dummy frame, it won't have any output regs in it.
1158 We never have to bother with %l (local) regs, since the called routine's
1159 locals get tossed, and the calling routine's locals are already saved
1162 /* Definitely see tm-sparc.h for more doc of the frame format here. */
1165 sparc_pop_frame (void)
1167 register struct frame_info
*frame
= get_current_frame ();
1168 register CORE_ADDR pc
;
1173 fsr
= alloca (NUM_REGS
* sizeof (CORE_ADDR
));
1174 raw_buffer
= alloca (REGISTER_BYTES
);
1175 sparc_frame_find_saved_regs (frame
, &fsr
[0]);
1178 if (fsr
[FP0_REGNUM
])
1180 read_memory (fsr
[FP0_REGNUM
], raw_buffer
, FP_REGISTER_BYTES
);
1181 write_register_bytes (REGISTER_BYTE (FP0_REGNUM
),
1182 raw_buffer
, FP_REGISTER_BYTES
);
1184 if (!(GDB_TARGET_IS_SPARC64
))
1186 if (fsr
[FPS_REGNUM
])
1188 read_memory (fsr
[FPS_REGNUM
], raw_buffer
, SPARC_INTREG_SIZE
);
1189 write_register_gen (FPS_REGNUM
, raw_buffer
);
1191 if (fsr
[CPS_REGNUM
])
1193 read_memory (fsr
[CPS_REGNUM
], raw_buffer
, SPARC_INTREG_SIZE
);
1194 write_register_gen (CPS_REGNUM
, raw_buffer
);
1200 read_memory (fsr
[G1_REGNUM
], raw_buffer
, 7 * SPARC_INTREG_SIZE
);
1201 write_register_bytes (REGISTER_BYTE (G1_REGNUM
), raw_buffer
,
1202 7 * SPARC_INTREG_SIZE
);
1205 if (frame
->extra_info
->flat
)
1207 /* Each register might or might not have been saved, need to test
1209 for (regnum
= L0_REGNUM
; regnum
< L0_REGNUM
+ 8; ++regnum
)
1211 write_register (regnum
, read_memory_integer (fsr
[regnum
],
1212 SPARC_INTREG_SIZE
));
1213 for (regnum
= I0_REGNUM
; regnum
< I0_REGNUM
+ 8; ++regnum
)
1215 write_register (regnum
, read_memory_integer (fsr
[regnum
],
1216 SPARC_INTREG_SIZE
));
1218 /* Handle all outs except stack pointer (o0-o5; o7). */
1219 for (regnum
= O0_REGNUM
; regnum
< O0_REGNUM
+ 6; ++regnum
)
1221 write_register (regnum
, read_memory_integer (fsr
[regnum
],
1222 SPARC_INTREG_SIZE
));
1223 if (fsr
[O0_REGNUM
+ 7])
1224 write_register (O0_REGNUM
+ 7,
1225 read_memory_integer (fsr
[O0_REGNUM
+ 7],
1226 SPARC_INTREG_SIZE
));
1228 write_sp (frame
->frame
);
1230 else if (fsr
[I0_REGNUM
])
1236 reg_temp
= alloca (REGISTER_BYTES
);
1238 read_memory (fsr
[I0_REGNUM
], raw_buffer
, 8 * SPARC_INTREG_SIZE
);
1240 /* Get the ins and locals which we are about to restore. Just
1241 moving the stack pointer is all that is really needed, except
1242 store_inferior_registers is then going to write the ins and
1243 locals from the registers array, so we need to muck with the
1245 sp
= fsr
[SP_REGNUM
];
1247 if (GDB_TARGET_IS_SPARC64
&& (sp
& 1))
1250 read_memory (sp
, reg_temp
, SPARC_INTREG_SIZE
* 16);
1252 /* Restore the out registers.
1253 Among other things this writes the new stack pointer. */
1254 write_register_bytes (REGISTER_BYTE (O0_REGNUM
), raw_buffer
,
1255 SPARC_INTREG_SIZE
* 8);
1257 write_register_bytes (REGISTER_BYTE (L0_REGNUM
), reg_temp
,
1258 SPARC_INTREG_SIZE
* 16);
1261 if (!(GDB_TARGET_IS_SPARC64
))
1263 write_register (PS_REGNUM
,
1264 read_memory_integer (fsr
[PS_REGNUM
],
1265 REGISTER_RAW_SIZE (PS_REGNUM
)));
1268 write_register (Y_REGNUM
,
1269 read_memory_integer (fsr
[Y_REGNUM
],
1270 REGISTER_RAW_SIZE (Y_REGNUM
)));
1273 /* Explicitly specified PC (and maybe NPC) -- just restore them. */
1274 write_register (PC_REGNUM
,
1275 read_memory_integer (fsr
[PC_REGNUM
],
1276 REGISTER_RAW_SIZE (PC_REGNUM
)));
1277 if (fsr
[NPC_REGNUM
])
1278 write_register (NPC_REGNUM
,
1279 read_memory_integer (fsr
[NPC_REGNUM
],
1280 REGISTER_RAW_SIZE (NPC_REGNUM
)));
1282 else if (frame
->extra_info
->flat
)
1284 if (frame
->extra_info
->pc_addr
)
1285 pc
= PC_ADJUST ((CORE_ADDR
)
1286 read_memory_integer (frame
->extra_info
->pc_addr
,
1287 REGISTER_RAW_SIZE (PC_REGNUM
)));
1290 /* I think this happens only in the innermost frame, if so then
1291 it is a complicated way of saying
1292 "pc = read_register (O7_REGNUM);". */
1295 buf
= alloca (MAX_REGISTER_RAW_SIZE
);
1296 get_saved_register (buf
, 0, 0, frame
, O7_REGNUM
, 0);
1297 pc
= PC_ADJUST (extract_address
1298 (buf
, REGISTER_RAW_SIZE (O7_REGNUM
)));
1301 write_register (PC_REGNUM
, pc
);
1302 write_register (NPC_REGNUM
, pc
+ 4);
1304 else if (fsr
[I7_REGNUM
])
1306 /* Return address in %i7 -- adjust it, then restore PC and NPC from it */
1307 pc
= PC_ADJUST ((CORE_ADDR
) read_memory_integer (fsr
[I7_REGNUM
],
1308 SPARC_INTREG_SIZE
));
1309 write_register (PC_REGNUM
, pc
);
1310 write_register (NPC_REGNUM
, pc
+ 4);
1312 flush_cached_frames ();
1315 /* On the Sun 4 under SunOS, the compile will leave a fake insn which
1316 encodes the structure size being returned. If we detect such
1317 a fake insn, step past it. */
1320 sparc_pc_adjust (CORE_ADDR pc
)
1326 err
= target_read_memory (pc
+ 8, buf
, 4);
1327 insn
= extract_unsigned_integer (buf
, 4);
1328 if ((err
== 0) && (insn
& 0xffc00000) == 0)
1334 /* If pc is in a shared library trampoline, return its target.
1335 The SunOs 4.x linker rewrites the jump table entries for PIC
1336 compiled modules in the main executable to bypass the dynamic linker
1337 with jumps of the form
1340 and removes the corresponding jump table relocation entry in the
1341 dynamic relocations.
1342 find_solib_trampoline_target relies on the presence of the jump
1343 table relocation entry, so we have to detect these jump instructions
1347 sunos4_skip_trampoline_code (CORE_ADDR pc
)
1349 unsigned long insn1
;
1353 err
= target_read_memory (pc
, buf
, 4);
1354 insn1
= extract_unsigned_integer (buf
, 4);
1355 if (err
== 0 && (insn1
& 0xffc00000) == 0x03000000)
1357 unsigned long insn2
;
1359 err
= target_read_memory (pc
+ 4, buf
, 4);
1360 insn2
= extract_unsigned_integer (buf
, 4);
1361 if (err
== 0 && (insn2
& 0xffffe000) == 0x81c06000)
1363 CORE_ADDR target_pc
= (insn1
& 0x3fffff) << 10;
1364 int delta
= insn2
& 0x1fff;
1366 /* Sign extend the displacement. */
1369 return target_pc
+ delta
;
1372 return find_solib_trampoline_target (pc
);
1375 #ifdef USE_PROC_FS /* Target dependent support for /proc */
1377 /* The /proc interface divides the target machine's register set up into
1378 two different sets, the general register set (gregset) and the floating
1379 point register set (fpregset). For each set, there is an ioctl to get
1380 the current register set and another ioctl to set the current values.
1382 The actual structure passed through the ioctl interface is, of course,
1383 naturally machine dependent, and is different for each set of registers.
1384 For the sparc for example, the general register set is typically defined
1387 typedef int gregset_t[38];
1393 and the floating point set by:
1395 typedef struct prfpregset {
1398 double pr_dregs[16];
1403 u_char pr_q_entrysize;
1408 These routines provide the packing and unpacking of gregset_t and
1409 fpregset_t formatted data.
1414 /* Given a pointer to a general register set in /proc format (gregset_t *),
1415 unpack the register contents and supply them as gdb's idea of the current
1419 supply_gregset (gdb_gregset_t
*gregsetp
)
1421 prgreg_t
*regp
= (prgreg_t
*) gregsetp
;
1422 int regi
, offset
= 0;
1424 /* If the host is 64-bit sparc, but the target is 32-bit sparc,
1425 then the gregset may contain 64-bit ints while supply_register
1426 is expecting 32-bit ints. Compensate. */
1427 if (sizeof (regp
[0]) == 8 && SPARC_INTREG_SIZE
== 4)
1430 /* GDB register numbers for Gn, On, Ln, In all match /proc reg numbers. */
1431 /* FIXME MVS: assumes the order of the first 32 elements... */
1432 for (regi
= G0_REGNUM
; regi
<= I7_REGNUM
; regi
++)
1434 supply_register (regi
, ((char *) (regp
+ regi
)) + offset
);
1437 /* These require a bit more care. */
1438 supply_register (PC_REGNUM
, ((char *) (regp
+ R_PC
)) + offset
);
1439 supply_register (NPC_REGNUM
, ((char *) (regp
+ R_nPC
)) + offset
);
1440 supply_register (Y_REGNUM
, ((char *) (regp
+ R_Y
)) + offset
);
1442 if (GDB_TARGET_IS_SPARC64
)
1445 supply_register (CCR_REGNUM
, ((char *) (regp
+ R_CCR
)) + offset
);
1447 supply_register (CCR_REGNUM
, NULL
);
1450 supply_register (FPRS_REGNUM
, ((char *) (regp
+ R_FPRS
)) + offset
);
1452 supply_register (FPRS_REGNUM
, NULL
);
1455 supply_register (ASI_REGNUM
, ((char *) (regp
+ R_ASI
)) + offset
);
1457 supply_register (ASI_REGNUM
, NULL
);
1463 supply_register (PS_REGNUM
, ((char *) (regp
+ R_PS
)) + offset
);
1465 supply_register (PS_REGNUM
, NULL
);
1468 /* For 64-bit hosts, R_WIM and R_TBR may not be defined.
1469 Steal R_ASI and R_FPRS, and hope for the best! */
1471 #if !defined (R_WIM) && defined (R_ASI)
1475 #if !defined (R_TBR) && defined (R_FPRS)
1476 #define R_TBR R_FPRS
1480 supply_register (WIM_REGNUM
, ((char *) (regp
+ R_WIM
)) + offset
);
1482 supply_register (WIM_REGNUM
, NULL
);
1486 supply_register (TBR_REGNUM
, ((char *) (regp
+ R_TBR
)) + offset
);
1488 supply_register (TBR_REGNUM
, NULL
);
1492 /* Fill inaccessible registers with zero. */
1493 if (GDB_TARGET_IS_SPARC64
)
1496 * don't know how to get value of any of the following:
1498 supply_register (VER_REGNUM
, NULL
);
1499 supply_register (TICK_REGNUM
, NULL
);
1500 supply_register (PIL_REGNUM
, NULL
);
1501 supply_register (PSTATE_REGNUM
, NULL
);
1502 supply_register (TSTATE_REGNUM
, NULL
);
1503 supply_register (TBA_REGNUM
, NULL
);
1504 supply_register (TL_REGNUM
, NULL
);
1505 supply_register (TT_REGNUM
, NULL
);
1506 supply_register (TPC_REGNUM
, NULL
);
1507 supply_register (TNPC_REGNUM
, NULL
);
1508 supply_register (WSTATE_REGNUM
, NULL
);
1509 supply_register (CWP_REGNUM
, NULL
);
1510 supply_register (CANSAVE_REGNUM
, NULL
);
1511 supply_register (CANRESTORE_REGNUM
, NULL
);
1512 supply_register (CLEANWIN_REGNUM
, NULL
);
1513 supply_register (OTHERWIN_REGNUM
, NULL
);
1514 supply_register (ASR16_REGNUM
, NULL
);
1515 supply_register (ASR17_REGNUM
, NULL
);
1516 supply_register (ASR18_REGNUM
, NULL
);
1517 supply_register (ASR19_REGNUM
, NULL
);
1518 supply_register (ASR20_REGNUM
, NULL
);
1519 supply_register (ASR21_REGNUM
, NULL
);
1520 supply_register (ASR22_REGNUM
, NULL
);
1521 supply_register (ASR23_REGNUM
, NULL
);
1522 supply_register (ASR24_REGNUM
, NULL
);
1523 supply_register (ASR25_REGNUM
, NULL
);
1524 supply_register (ASR26_REGNUM
, NULL
);
1525 supply_register (ASR27_REGNUM
, NULL
);
1526 supply_register (ASR28_REGNUM
, NULL
);
1527 supply_register (ASR29_REGNUM
, NULL
);
1528 supply_register (ASR30_REGNUM
, NULL
);
1529 supply_register (ASR31_REGNUM
, NULL
);
1530 supply_register (ICC_REGNUM
, NULL
);
1531 supply_register (XCC_REGNUM
, NULL
);
1535 supply_register (CPS_REGNUM
, NULL
);
1540 fill_gregset (gdb_gregset_t
*gregsetp
, int regno
)
1542 prgreg_t
*regp
= (prgreg_t
*) gregsetp
;
1543 int regi
, offset
= 0;
1545 /* If the host is 64-bit sparc, but the target is 32-bit sparc,
1546 then the gregset may contain 64-bit ints while supply_register
1547 is expecting 32-bit ints. Compensate. */
1548 if (sizeof (regp
[0]) == 8 && SPARC_INTREG_SIZE
== 4)
1551 for (regi
= 0; regi
<= R_I7
; regi
++)
1552 if ((regno
== -1) || (regno
== regi
))
1553 read_register_gen (regi
, (char *) (regp
+ regi
) + offset
);
1555 if ((regno
== -1) || (regno
== PC_REGNUM
))
1556 read_register_gen (PC_REGNUM
, (char *) (regp
+ R_PC
) + offset
);
1558 if ((regno
== -1) || (regno
== NPC_REGNUM
))
1559 read_register_gen (NPC_REGNUM
, (char *) (regp
+ R_nPC
) + offset
);
1561 if ((regno
== -1) || (regno
== Y_REGNUM
))
1562 read_register_gen (Y_REGNUM
, (char *) (regp
+ R_Y
) + offset
);
1564 if (GDB_TARGET_IS_SPARC64
)
1567 if (regno
== -1 || regno
== CCR_REGNUM
)
1568 read_register_gen (CCR_REGNUM
, ((char *) (regp
+ R_CCR
)) + offset
);
1571 if (regno
== -1 || regno
== FPRS_REGNUM
)
1572 read_register_gen (FPRS_REGNUM
, ((char *) (regp
+ R_FPRS
)) + offset
);
1575 if (regno
== -1 || regno
== ASI_REGNUM
)
1576 read_register_gen (ASI_REGNUM
, ((char *) (regp
+ R_ASI
)) + offset
);
1582 if (regno
== -1 || regno
== PS_REGNUM
)
1583 read_register_gen (PS_REGNUM
, ((char *) (regp
+ R_PS
)) + offset
);
1586 /* For 64-bit hosts, R_WIM and R_TBR may not be defined.
1587 Steal R_ASI and R_FPRS, and hope for the best! */
1589 #if !defined (R_WIM) && defined (R_ASI)
1593 #if !defined (R_TBR) && defined (R_FPRS)
1594 #define R_TBR R_FPRS
1598 if (regno
== -1 || regno
== WIM_REGNUM
)
1599 read_register_gen (WIM_REGNUM
, ((char *) (regp
+ R_WIM
)) + offset
);
1601 if (regno
== -1 || regno
== WIM_REGNUM
)
1602 read_register_gen (WIM_REGNUM
, NULL
);
1606 if (regno
== -1 || regno
== TBR_REGNUM
)
1607 read_register_gen (TBR_REGNUM
, ((char *) (regp
+ R_TBR
)) + offset
);
1609 if (regno
== -1 || regno
== TBR_REGNUM
)
1610 read_register_gen (TBR_REGNUM
, NULL
);
1615 /* Given a pointer to a floating point register set in /proc format
1616 (fpregset_t *), unpack the register contents and supply them as gdb's
1617 idea of the current floating point register values. */
1620 supply_fpregset (gdb_fpregset_t
*fpregsetp
)
1628 for (regi
= FP0_REGNUM
; regi
< FP_MAX_REGNUM
; regi
++)
1630 from
= (char *) &fpregsetp
->pr_fr
.pr_regs
[regi
- FP0_REGNUM
];
1631 supply_register (regi
, from
);
1634 if (GDB_TARGET_IS_SPARC64
)
1637 * don't know how to get value of the following.
1639 supply_register (FSR_REGNUM
, NULL
); /* zero it out for now */
1640 supply_register (FCC0_REGNUM
, NULL
);
1641 supply_register (FCC1_REGNUM
, NULL
); /* don't know how to get value */
1642 supply_register (FCC2_REGNUM
, NULL
); /* don't know how to get value */
1643 supply_register (FCC3_REGNUM
, NULL
); /* don't know how to get value */
1647 supply_register (FPS_REGNUM
, (char *) &(fpregsetp
->pr_fsr
));
1651 /* Given a pointer to a floating point register set in /proc format
1652 (fpregset_t *), update the register specified by REGNO from gdb's idea
1653 of the current floating point register set. If REGNO is -1, update
1655 /* This will probably need some changes for sparc64. */
1658 fill_fpregset (gdb_fpregset_t
*fpregsetp
, int regno
)
1667 for (regi
= FP0_REGNUM
; regi
< FP_MAX_REGNUM
; regi
++)
1669 if ((regno
== -1) || (regno
== regi
))
1671 from
= (char *) ®isters
[REGISTER_BYTE (regi
)];
1672 to
= (char *) &fpregsetp
->pr_fr
.pr_regs
[regi
- FP0_REGNUM
];
1673 memcpy (to
, from
, REGISTER_RAW_SIZE (regi
));
1677 if (!(GDB_TARGET_IS_SPARC64
)) /* FIXME: does Sparc64 have this register? */
1678 if ((regno
== -1) || (regno
== FPS_REGNUM
))
1680 from
= (char *)®isters
[REGISTER_BYTE (FPS_REGNUM
)];
1681 to
= (char *) &fpregsetp
->pr_fsr
;
1682 memcpy (to
, from
, REGISTER_RAW_SIZE (FPS_REGNUM
));
1686 #endif /* USE_PROC_FS */
1689 #ifdef GET_LONGJMP_TARGET
1691 /* Figure out where the longjmp will land. We expect that we have just entered
1692 longjmp and haven't yet setup the stack frame, so the args are still in the
1693 output regs. %o0 (O0_REGNUM) points at the jmp_buf structure from which we
1694 extract the pc (JB_PC) that we will land at. The pc is copied into ADDR.
1695 This routine returns true on success */
1698 get_longjmp_target (CORE_ADDR
*pc
)
1701 #define LONGJMP_TARGET_SIZE 4
1702 char buf
[LONGJMP_TARGET_SIZE
];
1704 jb_addr
= read_register (O0_REGNUM
);
1706 if (target_read_memory (jb_addr
+ JB_PC
* JB_ELEMENT_SIZE
, buf
,
1707 LONGJMP_TARGET_SIZE
))
1710 *pc
= extract_address (buf
, LONGJMP_TARGET_SIZE
);
1714 #endif /* GET_LONGJMP_TARGET */
1716 #ifdef STATIC_TRANSFORM_NAME
1717 /* SunPRO (3.0 at least), encodes the static variables. This is not
1718 related to C++ mangling, it is done for C too. */
1721 sunpro_static_transform_name (char *name
)
1726 /* For file-local statics there will be a dollar sign, a bunch
1727 of junk (the contents of which match a string given in the
1728 N_OPT), a period and the name. For function-local statics
1729 there will be a bunch of junk (which seems to change the
1730 second character from 'A' to 'B'), a period, the name of the
1731 function, and the name. So just skip everything before the
1733 p
= strrchr (name
, '.');
1739 #endif /* STATIC_TRANSFORM_NAME */
1742 /* Utilities for printing registers.
1743 Page numbers refer to the SPARC Architecture Manual. */
1745 static void dump_ccreg (char *, int);
1748 dump_ccreg (char *reg
, int val
)
1751 printf_unfiltered ("%s:%s,%s,%s,%s", reg
,
1752 val
& 8 ? "N" : "NN",
1753 val
& 4 ? "Z" : "NZ",
1754 val
& 2 ? "O" : "NO",
1755 val
& 1 ? "C" : "NC");
1759 decode_asi (int val
)
1765 return "ASI_NUCLEUS";
1767 return "ASI_NUCLEUS_LITTLE";
1769 return "ASI_AS_IF_USER_PRIMARY";
1771 return "ASI_AS_IF_USER_SECONDARY";
1773 return "ASI_AS_IF_USER_PRIMARY_LITTLE";
1775 return "ASI_AS_IF_USER_SECONDARY_LITTLE";
1777 return "ASI_PRIMARY";
1779 return "ASI_SECONDARY";
1781 return "ASI_PRIMARY_NOFAULT";
1783 return "ASI_SECONDARY_NOFAULT";
1785 return "ASI_PRIMARY_LITTLE";
1787 return "ASI_SECONDARY_LITTLE";
1789 return "ASI_PRIMARY_NOFAULT_LITTLE";
1791 return "ASI_SECONDARY_NOFAULT_LITTLE";
1797 /* PRINT_REGISTER_HOOK routine.
1798 Pretty print various registers. */
1799 /* FIXME: Would be nice if this did some fancy things for 32 bit sparc. */
1802 sparc_print_register_hook (int regno
)
1806 /* Handle double/quad versions of lower 32 fp regs. */
1807 if (regno
>= FP0_REGNUM
&& regno
< FP0_REGNUM
+ 32
1808 && (regno
& 1) == 0)
1812 if (!read_relative_register_raw_bytes (regno
, value
)
1813 && !read_relative_register_raw_bytes (regno
+ 1, value
+ 4))
1815 printf_unfiltered ("\t");
1816 print_floating (value
, builtin_type_double
, gdb_stdout
);
1818 #if 0 /* FIXME: gdb doesn't handle long doubles */
1819 if ((regno
& 3) == 0)
1821 if (!read_relative_register_raw_bytes (regno
+ 2, value
+ 8)
1822 && !read_relative_register_raw_bytes (regno
+ 3, value
+ 12))
1824 printf_unfiltered ("\t");
1825 print_floating (value
, builtin_type_long_double
, gdb_stdout
);
1832 #if 0 /* FIXME: gdb doesn't handle long doubles */
1833 /* Print upper fp regs as long double if appropriate. */
1834 if (regno
>= FP0_REGNUM
+ 32 && regno
< FP_MAX_REGNUM
1835 /* We test for even numbered regs and not a multiple of 4 because
1836 the upper fp regs are recorded as doubles. */
1837 && (regno
& 1) == 0)
1841 if (!read_relative_register_raw_bytes (regno
, value
)
1842 && !read_relative_register_raw_bytes (regno
+ 1, value
+ 8))
1844 printf_unfiltered ("\t");
1845 print_floating (value
, builtin_type_long_double
, gdb_stdout
);
1851 /* FIXME: Some of these are priviledged registers.
1852 Not sure how they should be handled. */
1854 #define BITS(n, mask) ((int) (((val) >> (n)) & (mask)))
1856 val
= read_register (regno
);
1859 if (GDB_TARGET_IS_SPARC64
)
1863 printf_unfiltered ("\t");
1864 dump_ccreg ("xcc", val
>> 4);
1865 printf_unfiltered (", ");
1866 dump_ccreg ("icc", val
& 15);
1869 printf ("\tfef:%d, du:%d, dl:%d",
1870 BITS (2, 1), BITS (1, 1), BITS (0, 1));
1874 static char *fcc
[4] =
1875 {"=", "<", ">", "?"};
1876 static char *rd
[4] =
1877 {"N", "0", "+", "-"};
1878 /* Long, but I'd rather leave it as is and use a wide screen. */
1879 printf_filtered ("\t0:%s, 1:%s, 2:%s, 3:%s, rd:%s, tem:%d, ",
1880 fcc
[BITS (10, 3)], fcc
[BITS (32, 3)],
1881 fcc
[BITS (34, 3)], fcc
[BITS (36, 3)],
1882 rd
[BITS (30, 3)], BITS (23, 31));
1883 printf_filtered ("ns:%d, ver:%d, ftt:%d, qne:%d, aexc:%d, cexc:%d",
1884 BITS (22, 1), BITS (17, 7), BITS (14, 7),
1885 BITS (13, 1), BITS (5, 31), BITS (0, 31));
1890 char *asi
= decode_asi (val
);
1892 printf ("\t%s", asi
);
1896 printf ("\tmanuf:%d, impl:%d, mask:%d, maxtl:%d, maxwin:%d",
1897 BITS (48, 0xffff), BITS (32, 0xffff),
1898 BITS (24, 0xff), BITS (8, 0xff), BITS (0, 31));
1902 static char *mm
[4] =
1903 {"tso", "pso", "rso", "?"};
1904 printf_filtered ("\tcle:%d, tle:%d, mm:%s, red:%d, ",
1905 BITS (9, 1), BITS (8, 1),
1906 mm
[BITS (6, 3)], BITS (5, 1));
1907 printf_filtered ("pef:%d, am:%d, priv:%d, ie:%d, ag:%d",
1908 BITS (4, 1), BITS (3, 1), BITS (2, 1),
1909 BITS (1, 1), BITS (0, 1));
1913 /* FIXME: print all 4? */
1916 /* FIXME: print all 4? */
1919 /* FIXME: print all 4? */
1922 /* FIXME: print all 4? */
1925 printf ("\tother:%d, normal:%d", BITS (3, 7), BITS (0, 7));
1928 printf ("\t%d", BITS (0, 31));
1930 case CANSAVE_REGNUM
:
1931 printf ("\t%-2d before spill", BITS (0, 31));
1933 case CANRESTORE_REGNUM
:
1934 printf ("\t%-2d before fill", BITS (0, 31));
1936 case CLEANWIN_REGNUM
:
1937 printf ("\t%-2d before clean", BITS (0, 31));
1939 case OTHERWIN_REGNUM
:
1940 printf ("\t%d", BITS (0, 31));
1947 printf ("\ticc:%c%c%c%c, pil:%d, s:%d, ps:%d, et:%d, cwp:%d",
1948 BITS (23, 1) ? 'N' : '-', BITS (22, 1) ? 'Z' : '-',
1949 BITS (21, 1) ? 'V' : '-', BITS (20, 1) ? 'C' : '-',
1950 BITS (8, 15), BITS (7, 1), BITS (6, 1), BITS (5, 1),
1955 static char *fcc
[4] =
1956 {"=", "<", ">", "?"};
1957 static char *rd
[4] =
1958 {"N", "0", "+", "-"};
1959 /* Long, but I'd rather leave it as is and use a wide screen. */
1960 printf ("\trd:%s, tem:%d, ns:%d, ver:%d, ftt:%d, qne:%d, "
1961 "fcc:%s, aexc:%d, cexc:%d",
1962 rd
[BITS (30, 3)], BITS (23, 31), BITS (22, 1), BITS (17, 7),
1963 BITS (14, 7), BITS (13, 1), fcc
[BITS (10, 3)], BITS (5, 31),
1973 gdb_print_insn_sparc (bfd_vma memaddr
, disassemble_info
*info
)
1975 /* It's necessary to override mach again because print_insn messes it up. */
1976 info
->mach
= TARGET_ARCHITECTURE
->mach
;
1977 return print_insn_sparc (memaddr
, info
);
1980 /* The SPARC passes the arguments on the stack; arguments smaller
1981 than an int are promoted to an int. The first 6 words worth of
1982 args are also passed in registers o0 - o5. */
1985 sparc32_push_arguments (int nargs
, value_ptr
*args
, CORE_ADDR sp
,
1986 int struct_return
, CORE_ADDR struct_addr
)
1989 int accumulate_size
= 0;
1996 struct sparc_arg
*sparc_args
=
1997 (struct sparc_arg
*) alloca (nargs
* sizeof (struct sparc_arg
));
1998 struct sparc_arg
*m_arg
;
2000 /* Promote arguments if necessary, and calculate their stack offsets
2002 for (i
= 0, m_arg
= sparc_args
; i
< nargs
; i
++, m_arg
++)
2004 value_ptr arg
= args
[i
];
2005 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
2006 /* Cast argument to long if necessary as the compiler does it too. */
2007 switch (TYPE_CODE (arg_type
))
2010 case TYPE_CODE_BOOL
:
2011 case TYPE_CODE_CHAR
:
2012 case TYPE_CODE_RANGE
:
2013 case TYPE_CODE_ENUM
:
2014 if (TYPE_LENGTH (arg_type
) < TYPE_LENGTH (builtin_type_long
))
2016 arg_type
= builtin_type_long
;
2017 arg
= value_cast (arg_type
, arg
);
2023 m_arg
->len
= TYPE_LENGTH (arg_type
);
2024 m_arg
->offset
= accumulate_size
;
2025 accumulate_size
= (accumulate_size
+ m_arg
->len
+ 3) & ~3;
2026 m_arg
->contents
= VALUE_CONTENTS (arg
);
2029 /* Make room for the arguments on the stack. */
2030 accumulate_size
+= CALL_DUMMY_STACK_ADJUST
;
2031 sp
= ((sp
- accumulate_size
) & ~7) + CALL_DUMMY_STACK_ADJUST
;
2033 /* `Push' arguments on the stack. */
2034 for (i
= 0, oregnum
= 0, m_arg
= sparc_args
;
2038 write_memory (sp
+ m_arg
->offset
, m_arg
->contents
, m_arg
->len
);
2040 j
< m_arg
->len
&& oregnum
< 6;
2041 j
+= SPARC_INTREG_SIZE
, oregnum
++)
2042 write_register_gen (O0_REGNUM
+ oregnum
, m_arg
->contents
+ j
);
2049 /* Extract from an array REGBUF containing the (raw) register state
2050 a function return value of type TYPE, and copy that, in virtual format,
2054 sparc32_extract_return_value (struct type
*type
, char *regbuf
, char *valbuf
)
2056 int typelen
= TYPE_LENGTH (type
);
2057 int regsize
= REGISTER_RAW_SIZE (O0_REGNUM
);
2059 if (TYPE_CODE (type
) == TYPE_CODE_FLT
&& SPARC_HAS_FPU
)
2060 memcpy (valbuf
, ®buf
[REGISTER_BYTE (FP0_REGNUM
)], typelen
);
2063 ®buf
[O0_REGNUM
* regsize
+
2065 || TARGET_BYTE_ORDER
== LITTLE_ENDIAN
? 0
2066 : regsize
- typelen
)],
2071 /* Write into appropriate registers a function return value
2072 of type TYPE, given in virtual format. On SPARCs with FPUs,
2073 float values are returned in %f0 (and %f1). In all other cases,
2074 values are returned in register %o0. */
2077 sparc_store_return_value (struct type
*type
, char *valbuf
)
2082 buffer
= alloca(MAX_REGISTER_RAW_SIZE
);
2084 if (TYPE_CODE (type
) == TYPE_CODE_FLT
&& SPARC_HAS_FPU
)
2085 /* Floating-point values are returned in the register pair */
2086 /* formed by %f0 and %f1 (doubles are, anyway). */
2089 /* Other values are returned in register %o0. */
2092 /* Add leading zeros to the value. */
2093 if (TYPE_LENGTH (type
) < REGISTER_RAW_SIZE (regno
))
2095 memset (buffer
, 0, REGISTER_RAW_SIZE (regno
));
2096 memcpy (buffer
+ REGISTER_RAW_SIZE (regno
) - TYPE_LENGTH (type
), valbuf
,
2097 TYPE_LENGTH (type
));
2098 write_register_gen (regno
, buffer
);
2101 write_register_bytes (REGISTER_BYTE (regno
), valbuf
, TYPE_LENGTH (type
));
2105 sparclet_store_return_value (struct type
*type
, char *valbuf
)
2107 /* Other values are returned in register %o0. */
2108 write_register_bytes (REGISTER_BYTE (O0_REGNUM
), valbuf
,
2109 TYPE_LENGTH (type
));
2113 #ifndef CALL_DUMMY_CALL_OFFSET
2114 #define CALL_DUMMY_CALL_OFFSET \
2115 (gdbarch_tdep (current_gdbarch)->call_dummy_call_offset)
2116 #endif /* CALL_DUMMY_CALL_OFFSET */
2118 /* Insert the function address into a call dummy instruction sequence
2121 For structs and unions, if the function was compiled with Sun cc,
2122 it expects 'unimp' after the call. But gcc doesn't use that
2123 (twisted) convention. So leave a nop there for gcc (FIX_CALL_DUMMY
2124 can assume it is operating on a pristine CALL_DUMMY, not one that
2125 has already been customized for a different function). */
2128 sparc_fix_call_dummy (char *dummy
, CORE_ADDR pc
, CORE_ADDR fun
,
2129 struct type
*value_type
, int using_gcc
)
2133 /* Store the relative adddress of the target function into the
2134 'call' instruction. */
2135 store_unsigned_integer (dummy
+ CALL_DUMMY_CALL_OFFSET
, 4,
2137 | (((fun
- (pc
+ CALL_DUMMY_CALL_OFFSET
)) >> 2)
2140 /* If the called function returns an aggregate value, fill in the UNIMP
2141 instruction containing the size of the returned aggregate return value,
2142 which follows the call instruction.
2143 For details see the SPARC Architecture Manual Version 8, Appendix D.3.
2145 Adjust the call_dummy_breakpoint_offset for the bp_call_dummy breakpoint
2146 to the proper address in the call dummy, so that `finish' after a stop
2147 in a call dummy works.
2148 Tweeking current_gdbarch is not an optimal solution, but the call to
2149 sparc_fix_call_dummy is immediately followed by a call to run_stack_dummy,
2150 which is the only function where dummy_breakpoint_offset is actually
2151 used, if it is non-zero. */
2152 if (TYPE_CODE (value_type
) == TYPE_CODE_STRUCT
2153 || TYPE_CODE (value_type
) == TYPE_CODE_UNION
)
2155 store_unsigned_integer (dummy
+ CALL_DUMMY_CALL_OFFSET
+ 8, 4,
2156 TYPE_LENGTH (value_type
) & 0x1fff);
2157 set_gdbarch_call_dummy_breakpoint_offset (current_gdbarch
, 0x30);
2160 set_gdbarch_call_dummy_breakpoint_offset (current_gdbarch
, 0x2c);
2162 if (!(GDB_TARGET_IS_SPARC64
))
2164 /* If this is not a simulator target, change the first four
2165 instructions of the call dummy to NOPs. Those instructions
2166 include a 'save' instruction and are designed to work around
2167 problems with register window flushing in the simulator. */
2169 if (strcmp (target_shortname
, "sim") != 0)
2171 for (i
= 0; i
< 4; i
++)
2172 store_unsigned_integer (dummy
+ (i
* 4), 4, 0x01000000);
2176 /* If this is a bi-endian target, GDB has written the call dummy
2177 in little-endian order. We must byte-swap it back to big-endian. */
2180 for (i
= 0; i
< CALL_DUMMY_LENGTH
; i
+= 4)
2182 char tmp
= dummy
[i
];
2183 dummy
[i
] = dummy
[i
+ 3];
2186 dummy
[i
+ 1] = dummy
[i
+ 2];
2193 /* Set target byte order based on machine type. */
2196 sparc_target_architecture_hook (const bfd_arch_info_type
*ap
)
2200 if (ap
->mach
== bfd_mach_sparc_sparclite_le
)
2202 if (TARGET_BYTE_ORDER_SELECTABLE_P
)
2204 target_byte_order
= LITTLE_ENDIAN
;
2209 warning ("This GDB does not support little endian sparclite.");
2219 * Module "constructor" function.
2222 static struct gdbarch
* sparc_gdbarch_init (struct gdbarch_info info
,
2223 struct gdbarch_list
*arches
);
2226 _initialize_sparc_tdep (void)
2228 /* Hook us into the gdbarch mechanism. */
2229 register_gdbarch_init (bfd_arch_sparc
, sparc_gdbarch_init
);
2231 tm_print_insn
= gdb_print_insn_sparc
;
2232 tm_print_insn_info
.mach
= TM_PRINT_INSN_MACH
; /* Selects sparc/sparclite */
2233 target_architecture_hook
= sparc_target_architecture_hook
;
2236 /* Compensate for stack bias. Note that we currently don't handle
2237 mixed 32/64 bit code. */
2240 sparc64_read_sp (void)
2242 CORE_ADDR sp
= read_register (SP_REGNUM
);
2250 sparc64_read_fp (void)
2252 CORE_ADDR fp
= read_register (FP_REGNUM
);
2260 sparc64_write_sp (CORE_ADDR val
)
2262 CORE_ADDR oldsp
= read_register (SP_REGNUM
);
2264 write_register (SP_REGNUM
, val
- 2047);
2266 write_register (SP_REGNUM
, val
);
2270 sparc64_write_fp (CORE_ADDR val
)
2272 CORE_ADDR oldfp
= read_register (FP_REGNUM
);
2274 write_register (FP_REGNUM
, val
- 2047);
2276 write_register (FP_REGNUM
, val
);
2279 /* The SPARC 64 ABI passes floating-point arguments in FP0 to FP31,
2280 and all other arguments in O0 to O5. They are also copied onto
2281 the stack in the correct places. Apparently (empirically),
2282 structs of less than 16 bytes are passed member-by-member in
2283 separate registers, but I am unable to figure out the algorithm.
2284 Some members go in floating point regs, but I don't know which.
2286 FIXME: Handle small structs (less than 16 bytes containing floats).
2288 The counting regimen for using both integer and FP registers
2289 for argument passing is rather odd -- a single counter is used
2290 for both; this means that if the arguments alternate between
2291 int and float, we will waste every other register of both types. */
2294 sparc64_push_arguments (int nargs
, value_ptr
*args
, CORE_ADDR sp
,
2295 int struct_return
, CORE_ADDR struct_retaddr
)
2297 int i
, j
, register_counter
= 0;
2299 struct type
*sparc_intreg_type
=
2300 TYPE_LENGTH (builtin_type_long
) == SPARC_INTREG_SIZE
?
2301 builtin_type_long
: builtin_type_long_long
;
2303 sp
= (sp
& ~(((unsigned long) SPARC_INTREG_SIZE
) - 1UL));
2305 /* Figure out how much space we'll need. */
2306 for (i
= nargs
- 1; i
>= 0; i
--)
2308 int len
= TYPE_LENGTH (check_typedef (VALUE_TYPE (args
[i
])));
2309 value_ptr copyarg
= args
[i
];
2312 if (copylen
< SPARC_INTREG_SIZE
)
2314 copyarg
= value_cast (sparc_intreg_type
, copyarg
);
2315 copylen
= SPARC_INTREG_SIZE
;
2324 /* if STRUCT_RETURN, then first argument is the struct return location. */
2326 write_register (O0_REGNUM
+ register_counter
++, struct_retaddr
);
2328 /* Now write the arguments onto the stack, while writing FP
2329 arguments into the FP registers, and other arguments into the
2330 first six 'O' registers. */
2332 for (i
= 0; i
< nargs
; i
++)
2334 int len
= TYPE_LENGTH (check_typedef (VALUE_TYPE (args
[i
])));
2335 value_ptr copyarg
= args
[i
];
2336 enum type_code typecode
= TYPE_CODE (VALUE_TYPE (args
[i
]));
2339 if (typecode
== TYPE_CODE_INT
||
2340 typecode
== TYPE_CODE_BOOL
||
2341 typecode
== TYPE_CODE_CHAR
||
2342 typecode
== TYPE_CODE_RANGE
||
2343 typecode
== TYPE_CODE_ENUM
)
2344 if (len
< SPARC_INTREG_SIZE
)
2346 /* Small ints will all take up the size of one intreg on
2348 copyarg
= value_cast (sparc_intreg_type
, copyarg
);
2349 copylen
= SPARC_INTREG_SIZE
;
2352 write_memory (tempsp
, VALUE_CONTENTS (copyarg
), copylen
);
2355 /* Corner case: Structs consisting of a single float member are floats.
2356 * FIXME! I don't know about structs containing multiple floats!
2357 * Structs containing mixed floats and ints are even more weird.
2362 /* Separate float args from all other args. */
2363 if (typecode
== TYPE_CODE_FLT
&& SPARC_HAS_FPU
)
2365 if (register_counter
< 16)
2367 /* This arg gets copied into a FP register. */
2371 case 4: /* Single-precision (float) */
2372 fpreg
= FP0_REGNUM
+ 2 * register_counter
+ 1;
2373 register_counter
+= 1;
2375 case 8: /* Double-precision (double) */
2376 fpreg
= FP0_REGNUM
+ 2 * register_counter
;
2377 register_counter
+= 1;
2379 case 16: /* Quad-precision (long double) */
2380 fpreg
= FP0_REGNUM
+ 2 * register_counter
;
2381 register_counter
+= 2;
2384 write_register_bytes (REGISTER_BYTE (fpreg
),
2385 VALUE_CONTENTS (args
[i
]),
2389 else /* all other args go into the first six 'o' registers */
2392 j
< len
&& register_counter
< 6;
2393 j
+= SPARC_INTREG_SIZE
)
2395 int oreg
= O0_REGNUM
+ register_counter
;
2397 write_register_gen (oreg
, VALUE_CONTENTS (copyarg
) + j
);
2398 register_counter
+= 1;
2405 /* Values <= 32 bytes are returned in o0-o3 (floating-point values are
2406 returned in f0-f3). */
2409 sp64_extract_return_value (struct type
*type
, char *regbuf
, char *valbuf
,
2412 int typelen
= TYPE_LENGTH (type
);
2413 int regsize
= REGISTER_RAW_SIZE (O0_REGNUM
);
2415 if (TYPE_CODE (type
) == TYPE_CODE_FLT
&& SPARC_HAS_FPU
)
2417 memcpy (valbuf
, ®buf
[REGISTER_BYTE (FP0_REGNUM
)], typelen
);
2421 if (TYPE_CODE (type
) != TYPE_CODE_STRUCT
2422 || (TYPE_LENGTH (type
) > 32))
2425 ®buf
[O0_REGNUM
* regsize
+
2426 (typelen
>= regsize
? 0 : regsize
- typelen
)],
2432 char *o0
= ®buf
[O0_REGNUM
* regsize
];
2433 char *f0
= ®buf
[FP0_REGNUM
* regsize
];
2436 for (x
= 0; x
< TYPE_NFIELDS (type
); x
++)
2438 struct field
*f
= &TYPE_FIELDS (type
)[x
];
2439 /* FIXME: We may need to handle static fields here. */
2440 int whichreg
= (f
->loc
.bitpos
+ bitoffset
) / 32;
2441 int remainder
= ((f
->loc
.bitpos
+ bitoffset
) % 32) / 8;
2442 int where
= (f
->loc
.bitpos
+ bitoffset
) / 8;
2443 int size
= TYPE_LENGTH (f
->type
);
2444 int typecode
= TYPE_CODE (f
->type
);
2446 if (typecode
== TYPE_CODE_STRUCT
)
2448 sp64_extract_return_value (f
->type
,
2451 bitoffset
+ f
->loc
.bitpos
);
2453 else if (typecode
== TYPE_CODE_FLT
&& SPARC_HAS_FPU
)
2455 memcpy (valbuf
+ where
, &f0
[whichreg
* 4] + remainder
, size
);
2459 memcpy (valbuf
+ where
, &o0
[whichreg
* 4] + remainder
, size
);
2466 sparc64_extract_return_value (struct type
*type
, char *regbuf
, char *valbuf
)
2468 sp64_extract_return_value (type
, regbuf
, valbuf
, 0);
2472 sparclet_extract_return_value (struct type
*type
,
2476 regbuf
+= REGISTER_RAW_SIZE (O0_REGNUM
) * 8;
2477 if (TYPE_LENGTH (type
) < REGISTER_RAW_SIZE (O0_REGNUM
))
2478 regbuf
+= REGISTER_RAW_SIZE (O0_REGNUM
) - TYPE_LENGTH (type
);
2480 memcpy ((void *) valbuf
, regbuf
, TYPE_LENGTH (type
));
2485 sparc32_stack_align (CORE_ADDR addr
)
2487 return ((addr
+ 7) & -8);
2491 sparc64_stack_align (CORE_ADDR addr
)
2493 return ((addr
+ 15) & -16);
2497 sparc_print_extra_frame_info (struct frame_info
*fi
)
2499 if (fi
&& fi
->extra_info
&& fi
->extra_info
->flat
)
2500 printf_filtered (" flat, pc saved at 0x%s, fp saved at 0x%s\n",
2501 paddr_nz (fi
->extra_info
->pc_addr
),
2502 paddr_nz (fi
->extra_info
->fp_addr
));
2505 /* MULTI_ARCH support */
2508 sparc32_register_name (int regno
)
2510 static char *register_names
[] =
2511 { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
2512 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
2513 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
2514 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
2516 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
2517 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
2518 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
2519 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
2521 "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr"
2525 regno
>= (sizeof (register_names
) / sizeof (register_names
[0])))
2528 return register_names
[regno
];
2532 sparc64_register_name (int regno
)
2534 static char *register_names
[] =
2535 { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
2536 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
2537 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
2538 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
2540 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
2541 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
2542 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
2543 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
2544 "f32", "f34", "f36", "f38", "f40", "f42", "f44", "f46",
2545 "f48", "f50", "f52", "f54", "f56", "f58", "f60", "f62",
2547 "pc", "npc", "ccr", "fsr", "fprs", "y", "asi", "ver",
2548 "tick", "pil", "pstate", "tstate", "tba", "tl", "tt", "tpc",
2549 "tnpc", "wstate", "cwp", "cansave", "canrestore", "cleanwin", "otherwin",
2550 "asr16", "asr17", "asr18", "asr19", "asr20", "asr21", "asr22", "asr23",
2551 "asr24", "asr25", "asr26", "asr27", "asr28", "asr29", "asr30", "asr31",
2552 /* These are here at the end to simplify removing them if we have to. */
2553 "icc", "xcc", "fcc0", "fcc1", "fcc2", "fcc3"
2557 regno
>= (sizeof (register_names
) / sizeof (register_names
[0])))
2560 return register_names
[regno
];
2564 sparclite_register_name (int regno
)
2566 static char *register_names
[] =
2567 { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
2568 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
2569 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
2570 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
2572 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
2573 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
2574 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
2575 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
2577 "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr",
2578 "dia1", "dia2", "dda1", "dda2", "ddv1", "ddv2", "dcr", "dsr"
2582 regno
>= (sizeof (register_names
) / sizeof (register_names
[0])))
2585 return register_names
[regno
];
2589 sparclet_register_name (int regno
)
2591 static char *register_names
[] =
2592 { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
2593 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
2594 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
2595 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
2597 "", "", "", "", "", "", "", "", /* no floating point registers */
2598 "", "", "", "", "", "", "", "",
2599 "", "", "", "", "", "", "", "",
2600 "", "", "", "", "", "", "", "",
2602 "y", "psr", "wim", "tbr", "pc", "npc", "", "", /* no FPSR or CPSR */
2603 "ccsr", "ccpr", "cccrcr", "ccor", "ccobr", "ccibr", "ccir", "",
2605 /* ASR15 ASR19 (don't display them) */
2606 "asr1", "", "asr17", "asr18", "", "asr20", "asr21", "asr22"
2607 /* None of the rest get displayed */
2609 "awr0", "awr1", "awr2", "awr3", "awr4", "awr5", "awr6", "awr7",
2610 "awr8", "awr9", "awr10", "awr11", "awr12", "awr13", "awr14", "awr15",
2611 "awr16", "awr17", "awr18", "awr19", "awr20", "awr21", "awr22", "awr23",
2612 "awr24", "awr25", "awr26", "awr27", "awr28", "awr29", "awr30", "awr31",
2618 regno
>= (sizeof (register_names
) / sizeof (register_names
[0])))
2621 return register_names
[regno
];
2625 sparc_push_return_address (CORE_ADDR pc_unused
, CORE_ADDR sp
)
2627 if (CALL_DUMMY_LOCATION
== AT_ENTRY_POINT
)
2629 /* The return PC of the dummy_frame is the former 'current' PC
2630 (where we were before we made the target function call).
2631 This is saved in %i7 by push_dummy_frame.
2633 We will save the 'call dummy location' (ie. the address
2634 to which the target function will return) in %o7.
2635 This address will actually be the program's entry point.
2636 There will be a special call_dummy breakpoint there. */
2638 write_register (O7_REGNUM
,
2639 CALL_DUMMY_ADDRESS () - 8);
2645 /* Should call_function allocate stack space for a struct return? */
2648 sparc64_use_struct_convention (int gcc_p
, struct type
*type
)
2650 return (TYPE_LENGTH (type
) > 32);
2653 /* Store the address of the place in which to copy the structure the
2654 subroutine will return. This is called from call_function_by_hand.
2655 The ultimate mystery is, tho, what is the value "16"?
2657 MVS: That's the offset from where the sp is now, to where the
2658 subroutine is gonna expect to find the struct return address. */
2661 sparc32_store_struct_return (CORE_ADDR addr
, CORE_ADDR sp
)
2666 val
= alloca (SPARC_INTREG_SIZE
);
2667 store_unsigned_integer (val
, SPARC_INTREG_SIZE
, addr
);
2668 write_memory (sp
+ (16 * SPARC_INTREG_SIZE
), val
, SPARC_INTREG_SIZE
);
2670 if (CALL_DUMMY_LOCATION
== AT_ENTRY_POINT
)
2672 /* Now adjust the value of the link register, which was previously
2673 stored by push_return_address. Functions that return structs are
2674 peculiar in that they return to link register + 12, rather than
2675 link register + 8. */
2677 o7
= read_register (O7_REGNUM
);
2678 write_register (O7_REGNUM
, o7
- 4);
2683 sparc64_store_struct_return (CORE_ADDR addr
, CORE_ADDR sp
)
2685 /* FIXME: V9 uses %o0 for this. */
2686 /* FIXME MVS: Only for small enough structs!!! */
2688 target_write_memory (sp
+ (16 * SPARC_INTREG_SIZE
),
2689 (char *) &addr
, SPARC_INTREG_SIZE
);
2691 if (CALL_DUMMY_LOCATION
== AT_ENTRY_POINT
)
2693 /* Now adjust the value of the link register, which was previously
2694 stored by push_return_address. Functions that return structs are
2695 peculiar in that they return to link register + 12, rather than
2696 link register + 8. */
2698 write_register (O7_REGNUM
, read_register (O7_REGNUM
) - 4);
2703 /* Default target data type for register REGNO. */
2705 static struct type
*
2706 sparc32_register_virtual_type (int regno
)
2708 if (regno
== PC_REGNUM
||
2709 regno
== FP_REGNUM
||
2711 return builtin_type_unsigned_int
;
2713 return builtin_type_int
;
2715 return builtin_type_float
;
2716 return builtin_type_int
;
2719 static struct type
*
2720 sparc64_register_virtual_type (int regno
)
2722 if (regno
== PC_REGNUM
||
2723 regno
== FP_REGNUM
||
2725 return builtin_type_unsigned_long_long
;
2727 return builtin_type_long_long
;
2729 return builtin_type_float
;
2731 return builtin_type_double
;
2732 return builtin_type_long_long
;
2735 /* Number of bytes of storage in the actual machine representation for
2739 sparc32_register_size (int regno
)
2745 sparc64_register_size (int regno
)
2747 return (regno
< 32 ? 8 : regno
< 64 ? 4 : 8);
2750 /* Index within the `registers' buffer of the first byte of the space
2751 for register REGNO. */
2754 sparc32_register_byte (int regno
)
2760 sparc64_register_byte (int regno
)
2764 else if (regno
< 64)
2765 return 32 * 8 + (regno
- 32) * 4;
2766 else if (regno
< 80)
2767 return 32 * 8 + 32 * 4 + (regno
- 64) * 8;
2769 return 64 * 8 + (regno
- 80) * 8;
2772 /* Advance PC across any function entry prologue instructions to reach
2773 some "real" code. SKIP_PROLOGUE_FRAMELESS_P advances the PC past
2774 some of the prologue, but stops as soon as it knows that the
2775 function has a frame. Its result is equal to its input PC if the
2776 function is frameless, unequal otherwise. */
2779 sparc_gdbarch_skip_prologue (CORE_ADDR ip
)
2781 return examine_prologue (ip
, 0, NULL
, NULL
);
2784 /* Immediately after a function call, return the saved pc.
2785 Can't go through the frames for this because on some machines
2786 the new frame is not set up until the new function executes
2787 some instructions. */
2790 sparc_saved_pc_after_call (struct frame_info
*fi
)
2792 return sparc_pc_adjust (read_register (RP_REGNUM
));
2795 /* Convert registers between 'raw' and 'virtual' formats.
2796 They are the same on sparc, so there's nothing to do. */
2799 sparc_convert_to_virtual (int regnum
, struct type
*type
, char *from
, char *to
)
2800 { /* do nothing (should never be called) */
2804 sparc_convert_to_raw (struct type
*type
, int regnum
, char *from
, char *to
)
2805 { /* do nothing (should never be called) */
2808 /* Init saved regs: nothing to do, just a place-holder function. */
2811 sparc_frame_init_saved_regs (struct frame_info
*fi_ignored
)
2815 /* gdbarch fix call dummy:
2816 All this function does is rearrange the arguments before calling
2817 sparc_fix_call_dummy (which does the real work). */
2820 sparc_gdbarch_fix_call_dummy (char *dummy
,
2824 struct value
**args
,
2828 if (CALL_DUMMY_LOCATION
== ON_STACK
)
2829 sparc_fix_call_dummy (dummy
, pc
, fun
, type
, gcc_p
);
2832 /* Coerce float to double: a no-op. */
2835 sparc_coerce_float_to_double (struct type
*formal
, struct type
*actual
)
2840 /* CALL_DUMMY_ADDRESS: fetch the breakpoint address for a call dummy. */
2843 sparc_call_dummy_address (void)
2845 return (CALL_DUMMY_START_OFFSET
) + CALL_DUMMY_BREAKPOINT_OFFSET
;
2848 /* Supply the Y register number to those that need it. */
2851 sparc_y_regnum (void)
2853 return gdbarch_tdep (current_gdbarch
)->y_regnum
;
2857 sparc_reg_struct_has_addr (int gcc_p
, struct type
*type
)
2859 if (GDB_TARGET_IS_SPARC64
)
2860 return (TYPE_LENGTH (type
) > 32);
2862 return (gcc_p
!= 1);
2866 sparc_intreg_size (void)
2868 return SPARC_INTREG_SIZE
;
2872 sparc_return_value_on_stack (struct type
*type
)
2874 if (TYPE_CODE (type
) == TYPE_CODE_FLT
&&
2875 TYPE_LENGTH (type
) > 8)
2882 * Gdbarch "constructor" function.
2885 #define SPARC32_CALL_DUMMY_ON_STACK
2887 #define SPARC_SP_REGNUM 14
2888 #define SPARC_FP_REGNUM 30
2889 #define SPARC_FP0_REGNUM 32
2890 #define SPARC32_NPC_REGNUM 69
2891 #define SPARC32_PC_REGNUM 68
2892 #define SPARC32_Y_REGNUM 64
2893 #define SPARC64_PC_REGNUM 80
2894 #define SPARC64_NPC_REGNUM 81
2895 #define SPARC64_Y_REGNUM 85
2897 static struct gdbarch
*
2898 sparc_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2900 struct gdbarch
*gdbarch
;
2901 struct gdbarch_tdep
*tdep
;
2903 static LONGEST call_dummy_32
[] =
2904 { 0xbc100001, 0x9de38000, 0xbc100002, 0xbe100003,
2905 0xda03a058, 0xd803a054, 0xd603a050, 0xd403a04c,
2906 0xd203a048, 0x40000000, 0xd003a044, 0x01000000,
2907 0x91d02001, 0x01000000
2909 static LONGEST call_dummy_64
[] =
2910 { 0x9de3bec0fd3fa7f7LL
, 0xf93fa7eff53fa7e7LL
,
2911 0xf13fa7dfed3fa7d7LL
, 0xe93fa7cfe53fa7c7LL
,
2912 0xe13fa7bfdd3fa7b7LL
, 0xd93fa7afd53fa7a7LL
,
2913 0xd13fa79fcd3fa797LL
, 0xc93fa78fc53fa787LL
,
2914 0xc13fa77fcc3fa777LL
, 0xc83fa76fc43fa767LL
,
2915 0xc03fa75ffc3fa757LL
, 0xf83fa74ff43fa747LL
,
2916 0xf03fa73f01000000LL
, 0x0100000001000000LL
,
2917 0x0100000091580000LL
, 0xd027a72b93500000LL
,
2918 0xd027a72791480000LL
, 0xd027a72391400000LL
,
2919 0xd027a71fda5ba8a7LL
, 0xd85ba89fd65ba897LL
,
2920 0xd45ba88fd25ba887LL
, 0x9fc02000d05ba87fLL
,
2921 0x0100000091d02001LL
, 0x0100000001000000LL
2923 static LONGEST call_dummy_nil
[] = {0};
2925 /* First see if there is already a gdbarch that can satisfy the request. */
2926 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
2928 return arches
->gdbarch
;
2930 /* None found: is the request for a sparc architecture? */
2931 if (info
.bfd_architecture
!= bfd_arch_sparc
)
2932 return NULL
; /* No; then it's not for us. */
2934 /* Yes: create a new gdbarch for the specified machine type. */
2935 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
2936 gdbarch
= gdbarch_alloc (&info
, tdep
);
2938 /* First set settings that are common for all sparc architectures. */
2939 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
2940 set_gdbarch_breakpoint_from_pc (gdbarch
, memory_breakpoint_from_pc
);
2941 set_gdbarch_coerce_float_to_double (gdbarch
,
2942 sparc_coerce_float_to_double
);
2943 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch
, 1);
2944 set_gdbarch_call_dummy_p (gdbarch
, 1);
2945 set_gdbarch_call_dummy_stack_adjust_p (gdbarch
, 1);
2946 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
2947 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2948 set_gdbarch_extract_struct_value_address (gdbarch
,
2949 sparc_extract_struct_value_address
);
2950 set_gdbarch_fix_call_dummy (gdbarch
, sparc_gdbarch_fix_call_dummy
);
2951 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2952 set_gdbarch_fp_regnum (gdbarch
, SPARC_FP_REGNUM
);
2953 set_gdbarch_fp0_regnum (gdbarch
, SPARC_FP0_REGNUM
);
2954 set_gdbarch_frame_args_address (gdbarch
, default_frame_address
);
2955 set_gdbarch_frame_chain (gdbarch
, sparc_frame_chain
);
2956 set_gdbarch_frame_init_saved_regs (gdbarch
, sparc_frame_init_saved_regs
);
2957 set_gdbarch_frame_locals_address (gdbarch
, default_frame_address
);
2958 set_gdbarch_frame_num_args (gdbarch
, frame_num_args_unknown
);
2959 set_gdbarch_frame_saved_pc (gdbarch
, sparc_frame_saved_pc
);
2960 set_gdbarch_frameless_function_invocation (gdbarch
,
2961 frameless_look_for_prologue
);
2962 set_gdbarch_get_saved_register (gdbarch
, sparc_get_saved_register
);
2963 set_gdbarch_ieee_float (gdbarch
, 1);
2964 set_gdbarch_init_extra_frame_info (gdbarch
, sparc_init_extra_frame_info
);
2965 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2966 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2967 set_gdbarch_long_double_bit (gdbarch
, 16 * TARGET_CHAR_BIT
);
2968 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2969 set_gdbarch_max_register_raw_size (gdbarch
, 8);
2970 set_gdbarch_max_register_virtual_size (gdbarch
, 8);
2971 set_gdbarch_pop_frame (gdbarch
, sparc_pop_frame
);
2972 set_gdbarch_push_return_address (gdbarch
, sparc_push_return_address
);
2973 set_gdbarch_push_dummy_frame (gdbarch
, sparc_push_dummy_frame
);
2974 set_gdbarch_read_pc (gdbarch
, generic_target_read_pc
);
2975 set_gdbarch_register_convert_to_raw (gdbarch
, sparc_convert_to_raw
);
2976 set_gdbarch_register_convert_to_virtual (gdbarch
,
2977 sparc_convert_to_virtual
);
2978 set_gdbarch_register_convertible (gdbarch
,
2979 generic_register_convertible_not
);
2980 set_gdbarch_reg_struct_has_addr (gdbarch
, sparc_reg_struct_has_addr
);
2981 set_gdbarch_return_value_on_stack (gdbarch
, sparc_return_value_on_stack
);
2982 set_gdbarch_saved_pc_after_call (gdbarch
, sparc_saved_pc_after_call
);
2983 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
2984 set_gdbarch_skip_prologue (gdbarch
, sparc_gdbarch_skip_prologue
);
2985 set_gdbarch_sp_regnum (gdbarch
, SPARC_SP_REGNUM
);
2986 set_gdbarch_use_generic_dummy_frames (gdbarch
, 0);
2987 set_gdbarch_write_pc (gdbarch
, generic_target_write_pc
);
2990 * Settings that depend only on 32/64 bit word size
2993 switch (info
.bfd_arch_info
->mach
)
2995 case bfd_mach_sparc
:
2996 case bfd_mach_sparc_sparclet
:
2997 case bfd_mach_sparc_sparclite
:
2998 case bfd_mach_sparc_v8plus
:
2999 case bfd_mach_sparc_v8plusa
:
3000 case bfd_mach_sparc_sparclite_le
:
3001 /* 32-bit machine types: */
3003 #ifdef SPARC32_CALL_DUMMY_ON_STACK
3004 set_gdbarch_pc_in_call_dummy (gdbarch
, pc_in_call_dummy_on_stack
);
3005 set_gdbarch_call_dummy_address (gdbarch
, sparc_call_dummy_address
);
3006 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0x30);
3007 set_gdbarch_call_dummy_length (gdbarch
, 0x38);
3008 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
3009 set_gdbarch_call_dummy_words (gdbarch
, call_dummy_32
);
3011 set_gdbarch_pc_in_call_dummy (gdbarch
, pc_in_call_dummy_at_entry_point
);
3012 set_gdbarch_call_dummy_address (gdbarch
, entry_point_address
);
3013 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0);
3014 set_gdbarch_call_dummy_length (gdbarch
, 0);
3015 set_gdbarch_call_dummy_location (gdbarch
, AT_ENTRY_POINT
);
3016 set_gdbarch_call_dummy_words (gdbarch
, call_dummy_nil
);
3018 set_gdbarch_call_dummy_stack_adjust (gdbarch
, 68);
3019 set_gdbarch_call_dummy_start_offset (gdbarch
, 0);
3020 set_gdbarch_frame_args_skip (gdbarch
, 68);
3021 set_gdbarch_function_start_offset (gdbarch
, 0);
3022 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
3023 set_gdbarch_npc_regnum (gdbarch
, SPARC32_NPC_REGNUM
);
3024 set_gdbarch_pc_regnum (gdbarch
, SPARC32_PC_REGNUM
);
3025 set_gdbarch_ptr_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
3026 set_gdbarch_push_arguments (gdbarch
, sparc32_push_arguments
);
3027 set_gdbarch_read_fp (gdbarch
, generic_target_read_fp
);
3028 set_gdbarch_read_sp (gdbarch
, generic_target_read_sp
);
3030 set_gdbarch_register_byte (gdbarch
, sparc32_register_byte
);
3031 set_gdbarch_register_raw_size (gdbarch
, sparc32_register_size
);
3032 set_gdbarch_register_size (gdbarch
, 4);
3033 set_gdbarch_register_virtual_size (gdbarch
, sparc32_register_size
);
3034 set_gdbarch_register_virtual_type (gdbarch
,
3035 sparc32_register_virtual_type
);
3036 #ifdef SPARC32_CALL_DUMMY_ON_STACK
3037 set_gdbarch_sizeof_call_dummy_words (gdbarch
, sizeof (call_dummy_32
));
3039 set_gdbarch_sizeof_call_dummy_words (gdbarch
, 0);
3041 set_gdbarch_stack_align (gdbarch
, sparc32_stack_align
);
3042 set_gdbarch_store_struct_return (gdbarch
, sparc32_store_struct_return
);
3043 set_gdbarch_use_struct_convention (gdbarch
,
3044 generic_use_struct_convention
);
3045 set_gdbarch_write_fp (gdbarch
, generic_target_write_fp
);
3046 set_gdbarch_write_sp (gdbarch
, generic_target_write_sp
);
3047 tdep
->y_regnum
= SPARC32_Y_REGNUM
;
3048 tdep
->fp_max_regnum
= SPARC_FP0_REGNUM
+ 32;
3049 tdep
->intreg_size
= 4;
3050 tdep
->reg_save_offset
= 0x60;
3051 tdep
->call_dummy_call_offset
= 0x24;
3054 case bfd_mach_sparc_v9
:
3055 case bfd_mach_sparc_v9a
:
3056 /* 64-bit machine types: */
3057 default: /* Any new machine type is likely to be 64-bit. */
3059 #ifdef SPARC64_CALL_DUMMY_ON_STACK
3060 set_gdbarch_pc_in_call_dummy (gdbarch
, pc_in_call_dummy_on_stack
);
3061 set_gdbarch_call_dummy_address (gdbarch
, sparc_call_dummy_address
);
3062 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 8 * 4);
3063 set_gdbarch_call_dummy_length (gdbarch
, 192);
3064 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
3065 set_gdbarch_call_dummy_start_offset (gdbarch
, 148);
3066 set_gdbarch_call_dummy_words (gdbarch
, call_dummy_64
);
3068 set_gdbarch_pc_in_call_dummy (gdbarch
, pc_in_call_dummy_at_entry_point
);
3069 set_gdbarch_call_dummy_address (gdbarch
, entry_point_address
);
3070 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0);
3071 set_gdbarch_call_dummy_length (gdbarch
, 0);
3072 set_gdbarch_call_dummy_location (gdbarch
, AT_ENTRY_POINT
);
3073 set_gdbarch_call_dummy_start_offset (gdbarch
, 0);
3074 set_gdbarch_call_dummy_words (gdbarch
, call_dummy_nil
);
3076 set_gdbarch_call_dummy_stack_adjust (gdbarch
, 128);
3077 set_gdbarch_frame_args_skip (gdbarch
, 136);
3078 set_gdbarch_function_start_offset (gdbarch
, 0);
3079 set_gdbarch_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
3080 set_gdbarch_npc_regnum (gdbarch
, SPARC64_NPC_REGNUM
);
3081 set_gdbarch_pc_regnum (gdbarch
, SPARC64_PC_REGNUM
);
3082 set_gdbarch_ptr_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
3083 set_gdbarch_push_arguments (gdbarch
, sparc64_push_arguments
);
3084 /* NOTE different for at_entry */
3085 set_gdbarch_read_fp (gdbarch
, sparc64_read_fp
);
3086 set_gdbarch_read_sp (gdbarch
, sparc64_read_sp
);
3087 /* Some of the registers aren't 64 bits, but it's a lot simpler just
3088 to assume they all are (since most of them are). */
3089 set_gdbarch_register_byte (gdbarch
, sparc64_register_byte
);
3090 set_gdbarch_register_raw_size (gdbarch
, sparc64_register_size
);
3091 set_gdbarch_register_size (gdbarch
, 8);
3092 set_gdbarch_register_virtual_size (gdbarch
, sparc64_register_size
);
3093 set_gdbarch_register_virtual_type (gdbarch
,
3094 sparc64_register_virtual_type
);
3095 #ifdef SPARC64_CALL_DUMMY_ON_STACK
3096 set_gdbarch_sizeof_call_dummy_words (gdbarch
, sizeof (call_dummy_64
));
3098 set_gdbarch_sizeof_call_dummy_words (gdbarch
, 0);
3100 set_gdbarch_stack_align (gdbarch
, sparc64_stack_align
);
3101 set_gdbarch_store_struct_return (gdbarch
, sparc64_store_struct_return
);
3102 set_gdbarch_use_struct_convention (gdbarch
,
3103 sparc64_use_struct_convention
);
3104 set_gdbarch_write_fp (gdbarch
, sparc64_write_fp
);
3105 set_gdbarch_write_sp (gdbarch
, sparc64_write_sp
);
3106 tdep
->y_regnum
= SPARC64_Y_REGNUM
;
3107 tdep
->fp_max_regnum
= SPARC_FP0_REGNUM
+ 48;
3108 tdep
->intreg_size
= 8;
3109 tdep
->reg_save_offset
= 0x90;
3110 tdep
->call_dummy_call_offset
= 148 + 4 * 5;
3115 * Settings that vary per-architecture:
3118 switch (info
.bfd_arch_info
->mach
)
3120 case bfd_mach_sparc
:
3121 set_gdbarch_extract_return_value (gdbarch
, sparc32_extract_return_value
);
3122 set_gdbarch_frame_chain_valid (gdbarch
, file_frame_chain_valid
);
3123 set_gdbarch_num_regs (gdbarch
, 72);
3124 set_gdbarch_register_bytes (gdbarch
, 32*4 + 32*4 + 8*4);
3125 set_gdbarch_register_name (gdbarch
, sparc32_register_name
);
3126 set_gdbarch_store_return_value (gdbarch
, sparc_store_return_value
);
3127 tdep
->has_fpu
= 1; /* (all but sparclet and sparclite) */
3128 tdep
->fp_register_bytes
= 32 * 4;
3129 tdep
->print_insn_mach
= bfd_mach_sparc
;
3131 case bfd_mach_sparc_sparclet
:
3132 set_gdbarch_extract_return_value (gdbarch
,
3133 sparclet_extract_return_value
);
3134 set_gdbarch_frame_chain_valid (gdbarch
, file_frame_chain_valid
);
3135 set_gdbarch_num_regs (gdbarch
, 32 + 32 + 8 + 8 + 8);
3136 set_gdbarch_register_bytes (gdbarch
, 32*4 + 32*4 + 8*4 + 8*4 + 8*4);
3137 set_gdbarch_register_name (gdbarch
, sparclet_register_name
);
3138 set_gdbarch_store_return_value (gdbarch
, sparclet_store_return_value
);
3139 tdep
->has_fpu
= 0; /* (all but sparclet and sparclite) */
3140 tdep
->fp_register_bytes
= 0;
3141 tdep
->print_insn_mach
= bfd_mach_sparc_sparclet
;
3143 case bfd_mach_sparc_sparclite
:
3144 set_gdbarch_extract_return_value (gdbarch
, sparc32_extract_return_value
);
3145 set_gdbarch_frame_chain_valid (gdbarch
, func_frame_chain_valid
);
3146 set_gdbarch_num_regs (gdbarch
, 80);
3147 set_gdbarch_register_bytes (gdbarch
, 32*4 + 32*4 + 8*4 + 8*4);
3148 set_gdbarch_register_name (gdbarch
, sparclite_register_name
);
3149 set_gdbarch_store_return_value (gdbarch
, sparc_store_return_value
);
3150 tdep
->has_fpu
= 0; /* (all but sparclet and sparclite) */
3151 tdep
->fp_register_bytes
= 0;
3152 tdep
->print_insn_mach
= bfd_mach_sparc_sparclite
;
3154 case bfd_mach_sparc_v8plus
:
3155 set_gdbarch_extract_return_value (gdbarch
, sparc32_extract_return_value
);
3156 set_gdbarch_frame_chain_valid (gdbarch
, file_frame_chain_valid
);
3157 set_gdbarch_num_regs (gdbarch
, 72);
3158 set_gdbarch_register_bytes (gdbarch
, 32*4 + 32*4 + 8*4);
3159 set_gdbarch_register_name (gdbarch
, sparc32_register_name
);
3160 set_gdbarch_store_return_value (gdbarch
, sparc_store_return_value
);
3161 tdep
->print_insn_mach
= bfd_mach_sparc
;
3162 tdep
->fp_register_bytes
= 32 * 4;
3163 tdep
->has_fpu
= 1; /* (all but sparclet and sparclite) */
3165 case bfd_mach_sparc_v8plusa
:
3166 set_gdbarch_extract_return_value (gdbarch
, sparc32_extract_return_value
);
3167 set_gdbarch_frame_chain_valid (gdbarch
, file_frame_chain_valid
);
3168 set_gdbarch_num_regs (gdbarch
, 72);
3169 set_gdbarch_register_bytes (gdbarch
, 32*4 + 32*4 + 8*4);
3170 set_gdbarch_register_name (gdbarch
, sparc32_register_name
);
3171 set_gdbarch_store_return_value (gdbarch
, sparc_store_return_value
);
3172 tdep
->has_fpu
= 1; /* (all but sparclet and sparclite) */
3173 tdep
->fp_register_bytes
= 32 * 4;
3174 tdep
->print_insn_mach
= bfd_mach_sparc
;
3176 case bfd_mach_sparc_sparclite_le
:
3177 set_gdbarch_extract_return_value (gdbarch
, sparc32_extract_return_value
);
3178 set_gdbarch_frame_chain_valid (gdbarch
, func_frame_chain_valid
);
3179 set_gdbarch_num_regs (gdbarch
, 80);
3180 set_gdbarch_register_bytes (gdbarch
, 32*4 + 32*4 + 8*4 + 8*4);
3181 set_gdbarch_register_name (gdbarch
, sparclite_register_name
);
3182 set_gdbarch_store_return_value (gdbarch
, sparc_store_return_value
);
3183 tdep
->has_fpu
= 0; /* (all but sparclet and sparclite) */
3184 tdep
->fp_register_bytes
= 0;
3185 tdep
->print_insn_mach
= bfd_mach_sparc_sparclite
;
3187 case bfd_mach_sparc_v9
:
3188 set_gdbarch_extract_return_value (gdbarch
, sparc64_extract_return_value
);
3189 set_gdbarch_frame_chain_valid (gdbarch
, file_frame_chain_valid
);
3190 set_gdbarch_num_regs (gdbarch
, 125);
3191 set_gdbarch_register_bytes (gdbarch
, 32*8 + 32*8 + 45*8);
3192 set_gdbarch_register_name (gdbarch
, sparc64_register_name
);
3193 set_gdbarch_store_return_value (gdbarch
, sparc_store_return_value
);
3194 tdep
->has_fpu
= 1; /* (all but sparclet and sparclite) */
3195 tdep
->fp_register_bytes
= 64 * 4;
3196 tdep
->print_insn_mach
= bfd_mach_sparc_v9a
;
3198 case bfd_mach_sparc_v9a
:
3199 set_gdbarch_extract_return_value (gdbarch
, sparc64_extract_return_value
);
3200 set_gdbarch_frame_chain_valid (gdbarch
, file_frame_chain_valid
);
3201 set_gdbarch_num_regs (gdbarch
, 125);
3202 set_gdbarch_register_bytes (gdbarch
, 32*8 + 32*8 + 45*8);
3203 set_gdbarch_register_name (gdbarch
, sparc64_register_name
);
3204 set_gdbarch_store_return_value (gdbarch
, sparc_store_return_value
);
3205 tdep
->has_fpu
= 1; /* (all but sparclet and sparclite) */
3206 tdep
->fp_register_bytes
= 64 * 4;
3207 tdep
->print_insn_mach
= bfd_mach_sparc_v9a
;