1 /* Target-dependent code for SPARC.
3 Copyright (C) 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include "arch-utils.h"
24 #include "dwarf2-frame.h"
25 #include "floatformat.h"
27 #include "frame-base.h"
28 #include "frame-unwind.h"
39 #include "gdb_assert.h"
40 #include "gdb_string.h"
42 #include "sparc-tdep.h"
46 /* This file implements the SPARC 32-bit ABI as defined by the section
47 "Low-Level System Information" of the SPARC Compliance Definition
48 (SCD) 2.4.1, which is the 32-bit System V psABI for SPARC. The SCD
49 lists changes with respect to the original 32-bit psABI as defined
50 in the "System V ABI, SPARC Processor Supplement".
52 Note that if we talk about SunOS, we mean SunOS 4.x, which was
53 BSD-based, which is sometimes (retroactively?) referred to as
54 Solaris 1.x. If we talk about Solaris we mean Solaris 2.x and
55 above (Solaris 7, 8 and 9 are nothing but Solaris 2.7, 2.8 and 2.9
56 suffering from severe version number inflation). Solaris 2.x is
57 also known as SunOS 5.x, since that's what uname(1) says. Solaris
60 /* Please use the sparc32_-prefix for 32-bit specific code, the
61 sparc64_-prefix for 64-bit specific code and the sparc_-prefix for
62 code that can handle both. The 64-bit specific code lives in
63 sparc64-tdep.c; don't add any here. */
65 /* The SPARC Floating-Point Quad-Precision format is similar to
66 big-endian IA-64 Quad-recision format. */
67 #define floatformats_sparc_quad floatformats_ia64_quad
69 /* The stack pointer is offset from the stack frame by a BIAS of 2047
70 (0x7ff) for 64-bit code. BIAS is likely to be defined on SPARC
71 hosts, so undefine it first. */
75 /* Macros to extract fields from SPARC instructions. */
76 #define X_OP(i) (((i) >> 30) & 0x3)
77 #define X_RD(i) (((i) >> 25) & 0x1f)
78 #define X_A(i) (((i) >> 29) & 1)
79 #define X_COND(i) (((i) >> 25) & 0xf)
80 #define X_OP2(i) (((i) >> 22) & 0x7)
81 #define X_IMM22(i) ((i) & 0x3fffff)
82 #define X_OP3(i) (((i) >> 19) & 0x3f)
83 #define X_RS1(i) (((i) >> 14) & 0x1f)
84 #define X_RS2(i) ((i) & 0x1f)
85 #define X_I(i) (((i) >> 13) & 1)
86 /* Sign extension macros. */
87 #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000)
88 #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000)
89 #define X_SIMM13(i) ((((i) & 0x1fff) ^ 0x1000) - 0x1000)
91 /* Fetch the instruction at PC. Instructions are always big-endian
92 even if the processor operates in little-endian mode. */
95 sparc_fetch_instruction (CORE_ADDR pc
)
101 /* If we can't read the instruction at PC, return zero. */
102 if (target_read_memory (pc
, buf
, sizeof (buf
)))
106 for (i
= 0; i
< sizeof (buf
); i
++)
107 insn
= (insn
<< 8) | buf
[i
];
112 /* Return non-zero if the instruction corresponding to PC is an "unimp"
116 sparc_is_unimp_insn (CORE_ADDR pc
)
118 const unsigned long insn
= sparc_fetch_instruction (pc
);
120 return ((insn
& 0xc1c00000) == 0);
123 /* OpenBSD/sparc includes StackGhost, which according to the author's
124 website http://stackghost.cerias.purdue.edu "... transparently and
125 automatically protects applications' stack frames; more
126 specifically, it guards the return pointers. The protection
127 mechanisms require no application source or binary modification and
128 imposes only a negligible performance penalty."
130 The same website provides the following description of how
133 "StackGhost interfaces with the kernel trap handler that would
134 normally write out registers to the stack and the handler that
135 would read them back in. By XORing a cookie into the
136 return-address saved in the user stack when it is actually written
137 to the stack, and then XOR it out when the return-address is pulled
138 from the stack, StackGhost can cause attacker corrupted return
139 pointers to behave in a manner the attacker cannot predict.
140 StackGhost can also use several unused bits in the return pointer
141 to detect a smashed return pointer and abort the process."
143 For GDB this means that whenever we're reading %i7 from a stack
144 frame's window save area, we'll have to XOR the cookie.
146 More information on StackGuard can be found on in:
148 Mike Frantzen and Mike Shuey. "StackGhost: Hardware Facilitated
149 Stack Protection." 2001. Published in USENIX Security Symposium
152 /* Fetch StackGhost Per-Process XOR cookie. */
155 sparc_fetch_wcookie (void)
157 struct target_ops
*ops
= ¤t_target
;
161 len
= target_read (ops
, TARGET_OBJECT_WCOOKIE
, NULL
, buf
, 0, 8);
165 /* We should have either an 32-bit or an 64-bit cookie. */
166 gdb_assert (len
== 4 || len
== 8);
168 return extract_unsigned_integer (buf
, len
);
172 /* The functions on this page are intended to be used to classify
173 function arguments. */
175 /* Check whether TYPE is "Integral or Pointer". */
178 sparc_integral_or_pointer_p (const struct type
*type
)
180 int len
= TYPE_LENGTH (type
);
182 switch (TYPE_CODE (type
))
188 case TYPE_CODE_RANGE
:
189 /* We have byte, half-word, word and extended-word/doubleword
190 integral types. The doubleword is an extension to the
191 original 32-bit ABI by the SCD 2.4.x. */
192 return (len
== 1 || len
== 2 || len
== 4 || len
== 8);
195 /* Allow either 32-bit or 64-bit pointers. */
196 return (len
== 4 || len
== 8);
204 /* Check whether TYPE is "Floating". */
207 sparc_floating_p (const struct type
*type
)
209 switch (TYPE_CODE (type
))
213 int len
= TYPE_LENGTH (type
);
214 return (len
== 4 || len
== 8 || len
== 16);
223 /* Check whether TYPE is "Structure or Union". */
226 sparc_structure_or_union_p (const struct type
*type
)
228 switch (TYPE_CODE (type
))
230 case TYPE_CODE_STRUCT
:
231 case TYPE_CODE_UNION
:
240 /* Register information. */
242 static const char *sparc32_register_names
[] =
244 "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
245 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
246 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
247 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
249 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
250 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
251 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
252 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
254 "y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr"
257 /* Total number of registers. */
258 #define SPARC32_NUM_REGS ARRAY_SIZE (sparc32_register_names)
260 /* We provide the aliases %d0..%d30 for the floating registers as
261 "psuedo" registers. */
263 static const char *sparc32_pseudo_register_names
[] =
265 "d0", "d2", "d4", "d6", "d8", "d10", "d12", "d14",
266 "d16", "d18", "d20", "d22", "d24", "d26", "d28", "d30"
269 /* Total number of pseudo registers. */
270 #define SPARC32_NUM_PSEUDO_REGS ARRAY_SIZE (sparc32_pseudo_register_names)
272 /* Return the name of register REGNUM. */
275 sparc32_register_name (struct gdbarch
*gdbarch
, int regnum
)
277 if (regnum
>= 0 && regnum
< SPARC32_NUM_REGS
)
278 return sparc32_register_names
[regnum
];
280 if (regnum
< SPARC32_NUM_REGS
+ SPARC32_NUM_PSEUDO_REGS
)
281 return sparc32_pseudo_register_names
[regnum
- SPARC32_NUM_REGS
];
288 struct type
*sparc_psr_type
;
291 struct type
*sparc_fsr_type
;
293 /* Construct types for ISA-specific registers. */
296 sparc_init_types (void)
300 type
= init_flags_type ("builtin_type_sparc_psr", 4);
301 append_flags_type_flag (type
, 5, "ET");
302 append_flags_type_flag (type
, 6, "PS");
303 append_flags_type_flag (type
, 7, "S");
304 append_flags_type_flag (type
, 12, "EF");
305 append_flags_type_flag (type
, 13, "EC");
306 sparc_psr_type
= type
;
308 type
= init_flags_type ("builtin_type_sparc_fsr", 4);
309 append_flags_type_flag (type
, 0, "NXA");
310 append_flags_type_flag (type
, 1, "DZA");
311 append_flags_type_flag (type
, 2, "UFA");
312 append_flags_type_flag (type
, 3, "OFA");
313 append_flags_type_flag (type
, 4, "NVA");
314 append_flags_type_flag (type
, 5, "NXC");
315 append_flags_type_flag (type
, 6, "DZC");
316 append_flags_type_flag (type
, 7, "UFC");
317 append_flags_type_flag (type
, 8, "OFC");
318 append_flags_type_flag (type
, 9, "NVC");
319 append_flags_type_flag (type
, 22, "NS");
320 append_flags_type_flag (type
, 23, "NXM");
321 append_flags_type_flag (type
, 24, "DZM");
322 append_flags_type_flag (type
, 25, "UFM");
323 append_flags_type_flag (type
, 26, "OFM");
324 append_flags_type_flag (type
, 27, "NVM");
325 sparc_fsr_type
= type
;
328 /* Return the GDB type object for the "standard" data type of data in
332 sparc32_register_type (struct gdbarch
*gdbarch
, int regnum
)
334 if (regnum
>= SPARC_F0_REGNUM
&& regnum
<= SPARC_F31_REGNUM
)
335 return builtin_type_float
;
337 if (regnum
>= SPARC32_D0_REGNUM
&& regnum
<= SPARC32_D30_REGNUM
)
338 return builtin_type_double
;
340 if (regnum
== SPARC_SP_REGNUM
|| regnum
== SPARC_FP_REGNUM
)
341 return builtin_type_void_data_ptr
;
343 if (regnum
== SPARC32_PC_REGNUM
|| regnum
== SPARC32_NPC_REGNUM
)
344 return builtin_type_void_func_ptr
;
346 if (regnum
== SPARC32_PSR_REGNUM
)
347 return sparc_psr_type
;
349 if (regnum
== SPARC32_FSR_REGNUM
)
350 return sparc_fsr_type
;
352 return builtin_type_int32
;
356 sparc32_pseudo_register_read (struct gdbarch
*gdbarch
,
357 struct regcache
*regcache
,
358 int regnum
, gdb_byte
*buf
)
360 gdb_assert (regnum
>= SPARC32_D0_REGNUM
&& regnum
<= SPARC32_D30_REGNUM
);
362 regnum
= SPARC_F0_REGNUM
+ 2 * (regnum
- SPARC32_D0_REGNUM
);
363 regcache_raw_read (regcache
, regnum
, buf
);
364 regcache_raw_read (regcache
, regnum
+ 1, buf
+ 4);
368 sparc32_pseudo_register_write (struct gdbarch
*gdbarch
,
369 struct regcache
*regcache
,
370 int regnum
, const gdb_byte
*buf
)
372 gdb_assert (regnum
>= SPARC32_D0_REGNUM
&& regnum
<= SPARC32_D30_REGNUM
);
374 regnum
= SPARC_F0_REGNUM
+ 2 * (regnum
- SPARC32_D0_REGNUM
);
375 regcache_raw_write (regcache
, regnum
, buf
);
376 regcache_raw_write (regcache
, regnum
+ 1, buf
+ 4);
381 sparc32_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
383 struct value
**args
, int nargs
,
384 struct type
*value_type
,
385 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
386 struct regcache
*regcache
)
391 if (using_struct_return (SYMBOL_TYPE (find_pc_function (funcaddr
)),
396 /* This is an UNIMP instruction. */
397 store_unsigned_integer (buf
, 4, TYPE_LENGTH (value_type
) & 0x1fff);
398 write_memory (sp
- 8, buf
, 4);
406 sparc32_store_arguments (struct regcache
*regcache
, int nargs
,
407 struct value
**args
, CORE_ADDR sp
,
408 int struct_return
, CORE_ADDR struct_addr
)
410 /* Number of words in the "parameter array". */
411 int num_elements
= 0;
415 for (i
= 0; i
< nargs
; i
++)
417 struct type
*type
= value_type (args
[i
]);
418 int len
= TYPE_LENGTH (type
);
420 if (sparc_structure_or_union_p (type
)
421 || (sparc_floating_p (type
) && len
== 16))
423 /* Structure, Union and Quad-Precision Arguments. */
426 /* Use doubleword alignment for these values. That's always
427 correct, and wasting a few bytes shouldn't be a problem. */
430 write_memory (sp
, value_contents (args
[i
]), len
);
431 args
[i
] = value_from_pointer (lookup_pointer_type (type
), sp
);
434 else if (sparc_floating_p (type
))
436 /* Floating arguments. */
437 gdb_assert (len
== 4 || len
== 8);
438 num_elements
+= (len
/ 4);
442 /* Integral and pointer arguments. */
443 gdb_assert (sparc_integral_or_pointer_p (type
));
446 args
[i
] = value_cast (builtin_type_int32
, args
[i
]);
447 num_elements
+= ((len
+ 3) / 4);
451 /* Always allocate at least six words. */
452 sp
-= max (6, num_elements
) * 4;
454 /* The psABI says that "Software convention requires space for the
455 struct/union return value pointer, even if the word is unused." */
458 /* The psABI says that "Although software convention and the
459 operating system require every stack frame to be doubleword
463 for (i
= 0; i
< nargs
; i
++)
465 const bfd_byte
*valbuf
= value_contents (args
[i
]);
466 struct type
*type
= value_type (args
[i
]);
467 int len
= TYPE_LENGTH (type
);
469 gdb_assert (len
== 4 || len
== 8);
473 int regnum
= SPARC_O0_REGNUM
+ element
;
475 regcache_cooked_write (regcache
, regnum
, valbuf
);
476 if (len
> 4 && element
< 5)
477 regcache_cooked_write (regcache
, regnum
+ 1, valbuf
+ 4);
480 /* Always store the argument in memory. */
481 write_memory (sp
+ 4 + element
* 4, valbuf
, len
);
485 gdb_assert (element
== num_elements
);
491 store_unsigned_integer (buf
, 4, struct_addr
);
492 write_memory (sp
, buf
, 4);
499 sparc32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
500 struct regcache
*regcache
, CORE_ADDR bp_addr
,
501 int nargs
, struct value
**args
, CORE_ADDR sp
,
502 int struct_return
, CORE_ADDR struct_addr
)
504 CORE_ADDR call_pc
= (struct_return
? (bp_addr
- 12) : (bp_addr
- 8));
506 /* Set return address. */
507 regcache_cooked_write_unsigned (regcache
, SPARC_O7_REGNUM
, call_pc
);
509 /* Set up function arguments. */
510 sp
= sparc32_store_arguments (regcache
, nargs
, args
, sp
,
511 struct_return
, struct_addr
);
513 /* Allocate the 16-word window save area. */
516 /* Stack should be doubleword aligned at this point. */
517 gdb_assert (sp
% 8 == 0);
519 /* Finally, update the stack pointer. */
520 regcache_cooked_write_unsigned (regcache
, SPARC_SP_REGNUM
, sp
);
526 /* Use the program counter to determine the contents and size of a
527 breakpoint instruction. Return a pointer to a string of bytes that
528 encode a breakpoint instruction, store the length of the string in
529 *LEN and optionally adjust *PC to point to the correct memory
530 location for inserting the breakpoint. */
532 static const gdb_byte
*
533 sparc_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pc
, int *len
)
535 static const gdb_byte break_insn
[] = { 0x91, 0xd0, 0x20, 0x01 };
537 *len
= sizeof (break_insn
);
542 /* Allocate and initialize a frame cache. */
544 static struct sparc_frame_cache
*
545 sparc_alloc_frame_cache (void)
547 struct sparc_frame_cache
*cache
;
550 cache
= FRAME_OBSTACK_ZALLOC (struct sparc_frame_cache
);
556 /* Frameless until proven otherwise. */
557 cache
->frameless_p
= 1;
559 cache
->struct_return_p
= 0;
564 /* GCC generates several well-known sequences of instructions at the begining
565 of each function prologue when compiling with -fstack-check. If one of
566 such sequences starts at START_PC, then return the address of the
567 instruction immediately past this sequence. Otherwise, return START_PC. */
570 sparc_skip_stack_check (const CORE_ADDR start_pc
)
572 CORE_ADDR pc
= start_pc
;
574 int offset_stack_checking_sequence
= 0;
576 /* With GCC, all stack checking sequences begin with the same two
579 /* sethi <some immediate>,%g1 */
580 insn
= sparc_fetch_instruction (pc
);
582 if (!(X_OP (insn
) == 0 && X_OP2 (insn
) == 0x4 && X_RD (insn
) == 1))
585 /* sub %sp, %g1, %g1 */
586 insn
= sparc_fetch_instruction (pc
);
588 if (!(X_OP (insn
) == 2 && X_OP3 (insn
) == 0x4 && !X_I(insn
)
589 && X_RD (insn
) == 1 && X_RS1 (insn
) == 14 && X_RS2 (insn
) == 1))
592 insn
= sparc_fetch_instruction (pc
);
595 /* First possible sequence:
596 [first two instructions above]
597 clr [%g1 - some immediate] */
599 /* clr [%g1 - some immediate] */
600 if (X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && X_I(insn
)
601 && X_RS1 (insn
) == 1 && X_RD (insn
) == 0)
603 /* Valid stack-check sequence, return the new PC. */
607 /* Second possible sequence: A small number of probes.
608 [first two instructions above]
610 add %g1, -<some immediate>, %g1
612 [repeat the two instructions above any (small) number of times]
613 clr [%g1 - some immediate] */
616 else if (X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && !X_I(insn
)
617 && X_RS1 (insn
) == 1 && X_RD (insn
) == 0)
621 /* add %g1, -<some immediate>, %g1 */
622 insn
= sparc_fetch_instruction (pc
);
624 if (!(X_OP (insn
) == 2 && X_OP3(insn
) == 0 && X_I(insn
)
625 && X_RS1 (insn
) == 1 && X_RD (insn
) == 1))
629 insn
= sparc_fetch_instruction (pc
);
631 if (!(X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && !X_I(insn
)
632 && X_RD (insn
) == 0 && X_RS1 (insn
) == 1))
636 /* clr [%g1 - some immediate] */
637 if (!(X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && X_I(insn
)
638 && X_RS1 (insn
) == 1 && X_RD (insn
) == 0))
641 /* We found a valid stack-check sequence, return the new PC. */
645 /* Third sequence: A probing loop.
646 [first two instructions above]
647 sethi <some immediate>, %g4
651 add %g1, -<some immediate>, %g1
654 clr [%g4 - some immediate] */
656 /* sethi <some immediate>, %g4 */
657 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 0x4 && X_RD (insn
) == 4)
659 /* sub %g1, %g4, %g4 */
660 insn
= sparc_fetch_instruction (pc
);
662 if (!(X_OP (insn
) == 2 && X_OP3 (insn
) == 0x4 && !X_I(insn
)
663 && X_RD (insn
) == 4 && X_RS1 (insn
) == 1 && X_RS2 (insn
) == 4))
667 insn
= sparc_fetch_instruction (pc
);
669 if (!(X_OP (insn
) == 2 && X_OP3 (insn
) == 0x14 && !X_I(insn
)
670 && X_RD (insn
) == 0 && X_RS1 (insn
) == 1 && X_RS2 (insn
) == 4))
674 insn
= sparc_fetch_instruction (pc
);
676 if (!(X_OP (insn
) == 0 && X_COND (insn
) == 0x1))
679 /* add %g1, -<some immediate>, %g1 */
680 insn
= sparc_fetch_instruction (pc
);
682 if (!(X_OP (insn
) == 2 && X_OP3(insn
) == 0 && X_I(insn
)
683 && X_RS1 (insn
) == 1 && X_RD (insn
) == 1))
687 insn
= sparc_fetch_instruction (pc
);
689 if (!(X_OP (insn
) == 0 && X_COND (insn
) == 0x8))
693 insn
= sparc_fetch_instruction (pc
);
695 if (!(X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && !X_I(insn
)
696 && X_RD (insn
) == 0 && X_RS1 (insn
) == 1))
699 /* clr [%g4 - some immediate] */
700 insn
= sparc_fetch_instruction (pc
);
702 if (!(X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && X_I(insn
)
703 && X_RS1 (insn
) == 4 && X_RD (insn
) == 0))
706 /* We found a valid stack-check sequence, return the new PC. */
710 /* No stack check code in our prologue, return the start_pc. */
715 sparc_analyze_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
716 CORE_ADDR current_pc
, struct sparc_frame_cache
*cache
)
718 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
723 pc
= sparc_skip_stack_check (pc
);
725 if (current_pc
<= pc
)
728 /* We have to handle to "Procedure Linkage Table" (PLT) special. On
729 SPARC the linker usually defines a symbol (typically
730 _PROCEDURE_LINKAGE_TABLE_) at the start of the .plt section.
731 This symbol makes us end up here with PC pointing at the start of
732 the PLT and CURRENT_PC probably pointing at a PLT entry. If we
733 would do our normal prologue analysis, we would probably conclude
734 that we've got a frame when in reality we don't, since the
735 dynamic linker patches up the first PLT with some code that
736 starts with a SAVE instruction. Patch up PC such that it points
737 at the start of our PLT entry. */
738 if (tdep
->plt_entry_size
> 0 && in_plt_section (current_pc
, NULL
))
739 pc
= current_pc
- ((current_pc
- pc
) % tdep
->plt_entry_size
);
741 insn
= sparc_fetch_instruction (pc
);
743 /* Recognize a SETHI insn and record its destination. */
744 if (X_OP (insn
) == 0 && X_OP2 (insn
) == 0x04)
749 insn
= sparc_fetch_instruction (pc
+ 4);
752 /* Allow for an arithmetic operation on DEST or %g1. */
753 if (X_OP (insn
) == 2 && X_I (insn
)
754 && (X_RD (insn
) == 1 || X_RD (insn
) == dest
))
758 insn
= sparc_fetch_instruction (pc
+ 8);
761 /* Check for the SAVE instruction that sets up the frame. */
762 if (X_OP (insn
) == 2 && X_OP3 (insn
) == 0x3c)
764 cache
->frameless_p
= 0;
765 return pc
+ offset
+ 4;
772 sparc_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
774 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
775 return frame_unwind_register_unsigned (next_frame
, tdep
->pc_regnum
);
778 /* Return PC of first real instruction of the function starting at
782 sparc32_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
784 struct symtab_and_line sal
;
785 CORE_ADDR func_start
, func_end
;
786 struct sparc_frame_cache cache
;
788 /* This is the preferred method, find the end of the prologue by
789 using the debugging information. */
790 if (find_pc_partial_function (start_pc
, NULL
, &func_start
, &func_end
))
792 sal
= find_pc_line (func_start
, 0);
794 if (sal
.end
< func_end
795 && start_pc
<= sal
.end
)
799 start_pc
= sparc_analyze_prologue (gdbarch
, start_pc
, 0xffffffffUL
, &cache
);
801 /* The psABI says that "Although the first 6 words of arguments
802 reside in registers, the standard stack frame reserves space for
803 them.". It also suggests that a function may use that space to
804 "write incoming arguments 0 to 5" into that space, and that's
805 indeed what GCC seems to be doing. In that case GCC will
806 generate debug information that points to the stack slots instead
807 of the registers, so we should consider the instructions that
808 write out these incoming arguments onto the stack. Of course we
809 only need to do this if we have a stack frame. */
811 while (!cache
.frameless_p
)
813 unsigned long insn
= sparc_fetch_instruction (start_pc
);
815 /* Recognize instructions that store incoming arguments in
816 %i0...%i5 into the corresponding stack slot. */
817 if (X_OP (insn
) == 3 && (X_OP3 (insn
) & 0x3c) == 0x04 && X_I (insn
)
818 && (X_RD (insn
) >= 24 && X_RD (insn
) <= 29) && X_RS1 (insn
) == 30
819 && X_SIMM13 (insn
) == 68 + (X_RD (insn
) - 24) * 4)
833 struct sparc_frame_cache
*
834 sparc_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
836 struct sparc_frame_cache
*cache
;
841 cache
= sparc_alloc_frame_cache ();
844 cache
->pc
= frame_func_unwind (next_frame
, NORMAL_FRAME
);
846 sparc_analyze_prologue (get_frame_arch (next_frame
), cache
->pc
,
847 frame_pc_unwind (next_frame
), cache
);
849 if (cache
->frameless_p
)
851 /* This function is frameless, so %fp (%i6) holds the frame
852 pointer for our calling frame. Use %sp (%o6) as this frame's
855 frame_unwind_register_unsigned (next_frame
, SPARC_SP_REGNUM
);
859 /* For normal frames, %fp (%i6) holds the frame pointer, the
860 base address for the current stack frame. */
862 frame_unwind_register_unsigned (next_frame
, SPARC_FP_REGNUM
);
872 sparc32_struct_return_from_sym (struct symbol
*sym
)
874 struct type
*type
= check_typedef (SYMBOL_TYPE (sym
));
875 enum type_code code
= TYPE_CODE (type
);
877 if (code
== TYPE_CODE_FUNC
|| code
== TYPE_CODE_METHOD
)
879 type
= check_typedef (TYPE_TARGET_TYPE (type
));
880 if (sparc_structure_or_union_p (type
)
881 || (sparc_floating_p (type
) && TYPE_LENGTH (type
) == 16))
888 struct sparc_frame_cache
*
889 sparc32_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
891 struct sparc_frame_cache
*cache
;
897 cache
= sparc_frame_cache (next_frame
, this_cache
);
899 sym
= find_pc_function (cache
->pc
);
902 cache
->struct_return_p
= sparc32_struct_return_from_sym (sym
);
906 /* There is no debugging information for this function to
907 help us determine whether this function returns a struct
908 or not. So we rely on another heuristic which is to check
909 the instruction at the return address and see if this is
910 an "unimp" instruction. If it is, then it is a struct-return
913 int regnum
= cache
->frameless_p
? SPARC_O7_REGNUM
: SPARC_I7_REGNUM
;
915 pc
= frame_unwind_register_unsigned (next_frame
, regnum
) + 8;
916 if (sparc_is_unimp_insn (pc
))
917 cache
->struct_return_p
= 1;
924 sparc32_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
925 struct frame_id
*this_id
)
927 struct sparc_frame_cache
*cache
=
928 sparc32_frame_cache (next_frame
, this_cache
);
930 /* This marks the outermost frame. */
931 if (cache
->base
== 0)
934 (*this_id
) = frame_id_build (cache
->base
, cache
->pc
);
938 sparc32_frame_prev_register (struct frame_info
*next_frame
, void **this_cache
,
939 int regnum
, int *optimizedp
,
940 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
941 int *realnump
, gdb_byte
*valuep
)
943 struct sparc_frame_cache
*cache
=
944 sparc32_frame_cache (next_frame
, this_cache
);
946 if (regnum
== SPARC32_PC_REGNUM
|| regnum
== SPARC32_NPC_REGNUM
)
954 CORE_ADDR pc
= (regnum
== SPARC32_NPC_REGNUM
) ? 4 : 0;
956 /* If this functions has a Structure, Union or
957 Quad-Precision return value, we have to skip the UNIMP
958 instruction that encodes the size of the structure. */
959 if (cache
->struct_return_p
)
962 regnum
= cache
->frameless_p
? SPARC_O7_REGNUM
: SPARC_I7_REGNUM
;
963 pc
+= frame_unwind_register_unsigned (next_frame
, regnum
) + 8;
964 store_unsigned_integer (valuep
, 4, pc
);
969 /* Handle StackGhost. */
971 ULONGEST wcookie
= sparc_fetch_wcookie ();
973 if (wcookie
!= 0 && !cache
->frameless_p
&& regnum
== SPARC_I7_REGNUM
)
981 CORE_ADDR addr
= cache
->base
+ (regnum
- SPARC_L0_REGNUM
) * 4;
984 /* Read the value in from memory. */
985 i7
= get_frame_memory_unsigned (next_frame
, addr
, 4);
986 store_unsigned_integer (valuep
, 4, i7
^ wcookie
);
992 /* The previous frame's `local' and `in' registers have been saved
993 in the register save area. */
994 if (!cache
->frameless_p
995 && regnum
>= SPARC_L0_REGNUM
&& regnum
<= SPARC_I7_REGNUM
)
998 *lvalp
= lval_memory
;
999 *addrp
= cache
->base
+ (regnum
- SPARC_L0_REGNUM
) * 4;
1003 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
1005 /* Read the value in from memory. */
1006 read_memory (*addrp
, valuep
, register_size (gdbarch
, regnum
));
1011 /* The previous frame's `out' registers are accessable as the
1012 current frame's `in' registers. */
1013 if (!cache
->frameless_p
1014 && regnum
>= SPARC_O0_REGNUM
&& regnum
<= SPARC_O7_REGNUM
)
1015 regnum
+= (SPARC_I0_REGNUM
- SPARC_O0_REGNUM
);
1018 *lvalp
= lval_register
;
1022 frame_unwind_register (next_frame
, (*realnump
), valuep
);
1025 static const struct frame_unwind sparc32_frame_unwind
=
1028 sparc32_frame_this_id
,
1029 sparc32_frame_prev_register
1032 static const struct frame_unwind
*
1033 sparc32_frame_sniffer (struct frame_info
*next_frame
)
1035 return &sparc32_frame_unwind
;
1040 sparc32_frame_base_address (struct frame_info
*next_frame
, void **this_cache
)
1042 struct sparc_frame_cache
*cache
=
1043 sparc32_frame_cache (next_frame
, this_cache
);
1048 static const struct frame_base sparc32_frame_base
=
1050 &sparc32_frame_unwind
,
1051 sparc32_frame_base_address
,
1052 sparc32_frame_base_address
,
1053 sparc32_frame_base_address
1056 static struct frame_id
1057 sparc_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1061 sp
= frame_unwind_register_unsigned (next_frame
, SPARC_SP_REGNUM
);
1064 return frame_id_build (sp
, frame_pc_unwind (next_frame
));
1068 /* Extract from an array REGBUF containing the (raw) register state, a
1069 function return value of TYPE, and copy that into VALBUF. */
1072 sparc32_extract_return_value (struct type
*type
, struct regcache
*regcache
,
1075 int len
= TYPE_LENGTH (type
);
1078 gdb_assert (!sparc_structure_or_union_p (type
));
1079 gdb_assert (!(sparc_floating_p (type
) && len
== 16));
1081 if (sparc_floating_p (type
))
1083 /* Floating return values. */
1084 regcache_cooked_read (regcache
, SPARC_F0_REGNUM
, buf
);
1086 regcache_cooked_read (regcache
, SPARC_F1_REGNUM
, buf
+ 4);
1087 memcpy (valbuf
, buf
, len
);
1091 /* Integral and pointer return values. */
1092 gdb_assert (sparc_integral_or_pointer_p (type
));
1094 regcache_cooked_read (regcache
, SPARC_O0_REGNUM
, buf
);
1097 regcache_cooked_read (regcache
, SPARC_O1_REGNUM
, buf
+ 4);
1098 gdb_assert (len
== 8);
1099 memcpy (valbuf
, buf
, 8);
1103 /* Just stripping off any unused bytes should preserve the
1104 signed-ness just fine. */
1105 memcpy (valbuf
, buf
+ 4 - len
, len
);
1110 /* Write into the appropriate registers a function return value stored
1111 in VALBUF of type TYPE. */
1114 sparc32_store_return_value (struct type
*type
, struct regcache
*regcache
,
1115 const gdb_byte
*valbuf
)
1117 int len
= TYPE_LENGTH (type
);
1120 gdb_assert (!sparc_structure_or_union_p (type
));
1121 gdb_assert (!(sparc_floating_p (type
) && len
== 16));
1123 if (sparc_floating_p (type
))
1125 /* Floating return values. */
1126 memcpy (buf
, valbuf
, len
);
1127 regcache_cooked_write (regcache
, SPARC_F0_REGNUM
, buf
);
1129 regcache_cooked_write (regcache
, SPARC_F1_REGNUM
, buf
+ 4);
1133 /* Integral and pointer return values. */
1134 gdb_assert (sparc_integral_or_pointer_p (type
));
1138 gdb_assert (len
== 8);
1139 memcpy (buf
, valbuf
, 8);
1140 regcache_cooked_write (regcache
, SPARC_O1_REGNUM
, buf
+ 4);
1144 /* ??? Do we need to do any sign-extension here? */
1145 memcpy (buf
+ 4 - len
, valbuf
, len
);
1147 regcache_cooked_write (regcache
, SPARC_O0_REGNUM
, buf
);
1151 static enum return_value_convention
1152 sparc32_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
1153 struct type
*type
, struct regcache
*regcache
,
1154 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
1156 /* The psABI says that "...every stack frame reserves the word at
1157 %fp+64. If a function returns a structure, union, or
1158 quad-precision value, this word should hold the address of the
1159 object into which the return value should be copied." This
1160 guarantees that we can always find the return value, not just
1161 before the function returns. */
1163 if (sparc_structure_or_union_p (type
)
1164 || (sparc_floating_p (type
) && TYPE_LENGTH (type
) == 16))
1171 regcache_cooked_read_unsigned (regcache
, SPARC_SP_REGNUM
, &sp
);
1172 addr
= read_memory_unsigned_integer (sp
+ 64, 4);
1173 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
1176 return RETURN_VALUE_ABI_PRESERVES_ADDRESS
;
1180 sparc32_extract_return_value (type
, regcache
, readbuf
);
1182 sparc32_store_return_value (type
, regcache
, writebuf
);
1184 return RETURN_VALUE_REGISTER_CONVENTION
;
1188 sparc32_stabs_argument_has_addr (struct gdbarch
*gdbarch
, struct type
*type
)
1190 return (sparc_structure_or_union_p (type
)
1191 || (sparc_floating_p (type
) && TYPE_LENGTH (type
) == 16));
1195 sparc32_dwarf2_struct_return_p (struct frame_info
*next_frame
)
1197 CORE_ADDR pc
= frame_unwind_address_in_block (next_frame
, NORMAL_FRAME
);
1198 struct symbol
*sym
= find_pc_function (pc
);
1201 return sparc32_struct_return_from_sym (sym
);
1206 sparc32_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
1207 struct dwarf2_frame_state_reg
*reg
,
1208 struct frame_info
*next_frame
)
1214 case SPARC_G0_REGNUM
:
1215 /* Since %g0 is always zero, there is no point in saving it, and
1216 people will be inclined omit it from the CFI. Make sure we
1217 don't warn about that. */
1218 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
1220 case SPARC_SP_REGNUM
:
1221 reg
->how
= DWARF2_FRAME_REG_CFA
;
1223 case SPARC32_PC_REGNUM
:
1224 case SPARC32_NPC_REGNUM
:
1225 reg
->how
= DWARF2_FRAME_REG_RA_OFFSET
;
1227 if (sparc32_dwarf2_struct_return_p (next_frame
))
1229 if (regnum
== SPARC32_NPC_REGNUM
)
1231 reg
->loc
.offset
= off
;
1237 /* The SPARC Architecture doesn't have hardware single-step support,
1238 and most operating systems don't implement it either, so we provide
1239 software single-step mechanism. */
1242 sparc_analyze_control_transfer (struct frame_info
*frame
,
1243 CORE_ADDR pc
, CORE_ADDR
*npc
)
1245 unsigned long insn
= sparc_fetch_instruction (pc
);
1246 int conditional_p
= X_COND (insn
) & 0x7;
1248 long offset
= 0; /* Must be signed for sign-extend. */
1250 if (X_OP (insn
) == 0 && X_OP2 (insn
) == 3 && (insn
& 0x1000000) == 0)
1252 /* Branch on Integer Register with Prediction (BPr). */
1256 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 6)
1258 /* Branch on Floating-Point Condition Codes (FBfcc). */
1260 offset
= 4 * X_DISP22 (insn
);
1262 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 5)
1264 /* Branch on Floating-Point Condition Codes with Prediction
1267 offset
= 4 * X_DISP19 (insn
);
1269 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 2)
1271 /* Branch on Integer Condition Codes (Bicc). */
1273 offset
= 4 * X_DISP22 (insn
);
1275 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 1)
1277 /* Branch on Integer Condition Codes with Prediction (BPcc). */
1279 offset
= 4 * X_DISP19 (insn
);
1281 else if (X_OP (insn
) == 2 && X_OP3 (insn
) == 0x3a)
1283 /* Trap instruction (TRAP). */
1284 return gdbarch_tdep (get_frame_arch (frame
))->step_trap (frame
, insn
);
1287 /* FIXME: Handle DONE and RETRY instructions. */
1293 /* For conditional branches, return nPC + 4 iff the annul
1295 return (X_A (insn
) ? *npc
+ 4 : 0);
1299 /* For unconditional branches, return the target if its
1300 specified condition is "always" and return nPC + 4 if the
1301 condition is "never". If the annul bit is 1, set *NPC to
1303 if (X_COND (insn
) == 0x0)
1304 pc
= *npc
, offset
= 4;
1308 gdb_assert (offset
!= 0);
1317 sparc_step_trap (struct frame_info
*frame
, unsigned long insn
)
1323 sparc_software_single_step (struct frame_info
*frame
)
1325 struct gdbarch
*arch
= get_frame_arch (frame
);
1326 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
1327 CORE_ADDR npc
, nnpc
;
1329 CORE_ADDR pc
, orig_npc
;
1331 pc
= get_frame_register_unsigned (frame
, tdep
->pc_regnum
);
1332 orig_npc
= npc
= get_frame_register_unsigned (frame
, tdep
->npc_regnum
);
1334 /* Analyze the instruction at PC. */
1335 nnpc
= sparc_analyze_control_transfer (frame
, pc
, &npc
);
1337 insert_single_step_breakpoint (npc
);
1340 insert_single_step_breakpoint (nnpc
);
1342 /* Assert that we have set at least one breakpoint, and that
1343 they're not set at the same spot - unless we're going
1344 from here straight to NULL, i.e. a call or jump to 0. */
1345 gdb_assert (npc
!= 0 || nnpc
!= 0 || orig_npc
== 0);
1346 gdb_assert (nnpc
!= npc
|| orig_npc
== 0);
1352 sparc_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1354 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_regcache_arch (regcache
));
1356 regcache_cooked_write_unsigned (regcache
, tdep
->pc_regnum
, pc
);
1357 regcache_cooked_write_unsigned (regcache
, tdep
->npc_regnum
, pc
+ 4);
1361 /* Return the appropriate register set for the core section identified
1362 by SECT_NAME and SECT_SIZE. */
1364 const struct regset
*
1365 sparc_regset_from_core_section (struct gdbarch
*gdbarch
,
1366 const char *sect_name
, size_t sect_size
)
1368 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1370 if (strcmp (sect_name
, ".reg") == 0 && sect_size
>= tdep
->sizeof_gregset
)
1371 return tdep
->gregset
;
1373 if (strcmp (sect_name
, ".reg2") == 0 && sect_size
>= tdep
->sizeof_fpregset
)
1374 return tdep
->fpregset
;
1380 static struct gdbarch
*
1381 sparc32_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
1383 struct gdbarch_tdep
*tdep
;
1384 struct gdbarch
*gdbarch
;
1386 /* If there is already a candidate, use it. */
1387 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
1389 return arches
->gdbarch
;
1391 /* Allocate space for the new architecture. */
1392 tdep
= XMALLOC (struct gdbarch_tdep
);
1393 gdbarch
= gdbarch_alloc (&info
, tdep
);
1395 tdep
->pc_regnum
= SPARC32_PC_REGNUM
;
1396 tdep
->npc_regnum
= SPARC32_NPC_REGNUM
;
1397 tdep
->gregset
= NULL
;
1398 tdep
->sizeof_gregset
= 0;
1399 tdep
->fpregset
= NULL
;
1400 tdep
->sizeof_fpregset
= 0;
1401 tdep
->plt_entry_size
= 0;
1402 tdep
->step_trap
= sparc_step_trap
;
1404 set_gdbarch_long_double_bit (gdbarch
, 128);
1405 set_gdbarch_long_double_format (gdbarch
, floatformats_sparc_quad
);
1407 set_gdbarch_num_regs (gdbarch
, SPARC32_NUM_REGS
);
1408 set_gdbarch_register_name (gdbarch
, sparc32_register_name
);
1409 set_gdbarch_register_type (gdbarch
, sparc32_register_type
);
1410 set_gdbarch_num_pseudo_regs (gdbarch
, SPARC32_NUM_PSEUDO_REGS
);
1411 set_gdbarch_pseudo_register_read (gdbarch
, sparc32_pseudo_register_read
);
1412 set_gdbarch_pseudo_register_write (gdbarch
, sparc32_pseudo_register_write
);
1414 /* Register numbers of various important registers. */
1415 set_gdbarch_sp_regnum (gdbarch
, SPARC_SP_REGNUM
); /* %sp */
1416 set_gdbarch_pc_regnum (gdbarch
, SPARC32_PC_REGNUM
); /* %pc */
1417 set_gdbarch_fp0_regnum (gdbarch
, SPARC_F0_REGNUM
); /* %f0 */
1419 /* Call dummy code. */
1420 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
1421 set_gdbarch_push_dummy_code (gdbarch
, sparc32_push_dummy_code
);
1422 set_gdbarch_push_dummy_call (gdbarch
, sparc32_push_dummy_call
);
1424 set_gdbarch_return_value (gdbarch
, sparc32_return_value
);
1425 set_gdbarch_stabs_argument_has_addr
1426 (gdbarch
, sparc32_stabs_argument_has_addr
);
1428 set_gdbarch_skip_prologue (gdbarch
, sparc32_skip_prologue
);
1430 /* Stack grows downward. */
1431 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
1433 set_gdbarch_breakpoint_from_pc (gdbarch
, sparc_breakpoint_from_pc
);
1435 set_gdbarch_frame_args_skip (gdbarch
, 8);
1437 set_gdbarch_print_insn (gdbarch
, print_insn_sparc
);
1439 set_gdbarch_software_single_step (gdbarch
, sparc_software_single_step
);
1440 set_gdbarch_write_pc (gdbarch
, sparc_write_pc
);
1442 set_gdbarch_unwind_dummy_id (gdbarch
, sparc_unwind_dummy_id
);
1444 set_gdbarch_unwind_pc (gdbarch
, sparc_unwind_pc
);
1446 frame_base_set_default (gdbarch
, &sparc32_frame_base
);
1448 /* Hook in the DWARF CFI frame unwinder. */
1449 dwarf2_frame_set_init_reg (gdbarch
, sparc32_dwarf2_frame_init_reg
);
1450 /* FIXME: kettenis/20050423: Don't enable the unwinder until the
1451 StackGhost issues have been resolved. */
1453 /* Hook in ABI-specific overrides, if they have been registered. */
1454 gdbarch_init_osabi (info
, gdbarch
);
1456 frame_unwind_append_sniffer (gdbarch
, sparc32_frame_sniffer
);
1458 /* If we have register sets, enable the generic core file support. */
1460 set_gdbarch_regset_from_core_section (gdbarch
,
1461 sparc_regset_from_core_section
);
1466 /* Helper functions for dealing with register windows. */
1469 sparc_supply_rwindow (struct regcache
*regcache
, CORE_ADDR sp
, int regnum
)
1477 /* Registers are 64-bit. */
1480 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1482 if (regnum
== i
|| regnum
== -1)
1484 target_read_memory (sp
+ ((i
- SPARC_L0_REGNUM
) * 8), buf
, 8);
1486 /* Handle StackGhost. */
1487 if (i
== SPARC_I7_REGNUM
)
1489 ULONGEST wcookie
= sparc_fetch_wcookie ();
1490 ULONGEST i7
= extract_unsigned_integer (buf
+ offset
, 8);
1492 store_unsigned_integer (buf
+ offset
, 8, i7
^ wcookie
);
1495 regcache_raw_supply (regcache
, i
, buf
);
1501 /* Registers are 32-bit. Toss any sign-extension of the stack
1505 /* Clear out the top half of the temporary buffer, and put the
1506 register value in the bottom half if we're in 64-bit mode. */
1507 if (gdbarch_ptr_bit (get_regcache_arch (regcache
)) == 64)
1513 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1515 if (regnum
== i
|| regnum
== -1)
1517 target_read_memory (sp
+ ((i
- SPARC_L0_REGNUM
) * 4),
1520 /* Handle StackGhost. */
1521 if (i
== SPARC_I7_REGNUM
)
1523 ULONGEST wcookie
= sparc_fetch_wcookie ();
1524 ULONGEST i7
= extract_unsigned_integer (buf
+ offset
, 4);
1526 store_unsigned_integer (buf
+ offset
, 4, i7
^ wcookie
);
1529 regcache_raw_supply (regcache
, i
, buf
);
1536 sparc_collect_rwindow (const struct regcache
*regcache
,
1537 CORE_ADDR sp
, int regnum
)
1545 /* Registers are 64-bit. */
1548 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1550 if (regnum
== -1 || regnum
== SPARC_SP_REGNUM
|| regnum
== i
)
1552 regcache_raw_collect (regcache
, i
, buf
);
1554 /* Handle StackGhost. */
1555 if (i
== SPARC_I7_REGNUM
)
1557 ULONGEST wcookie
= sparc_fetch_wcookie ();
1558 ULONGEST i7
= extract_unsigned_integer (buf
+ offset
, 8);
1560 store_unsigned_integer (buf
, 8, i7
^ wcookie
);
1563 target_write_memory (sp
+ ((i
- SPARC_L0_REGNUM
) * 8), buf
, 8);
1569 /* Registers are 32-bit. Toss any sign-extension of the stack
1573 /* Only use the bottom half if we're in 64-bit mode. */
1574 if (gdbarch_ptr_bit (get_regcache_arch (regcache
)) == 64)
1577 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1579 if (regnum
== -1 || regnum
== SPARC_SP_REGNUM
|| regnum
== i
)
1581 regcache_raw_collect (regcache
, i
, buf
);
1583 /* Handle StackGhost. */
1584 if (i
== SPARC_I7_REGNUM
)
1586 ULONGEST wcookie
= sparc_fetch_wcookie ();
1587 ULONGEST i7
= extract_unsigned_integer (buf
+ offset
, 4);
1589 store_unsigned_integer (buf
+ offset
, 4, i7
^ wcookie
);
1592 target_write_memory (sp
+ ((i
- SPARC_L0_REGNUM
) * 4),
1599 /* Helper functions for dealing with register sets. */
1602 sparc32_supply_gregset (const struct sparc_gregset
*gregset
,
1603 struct regcache
*regcache
,
1604 int regnum
, const void *gregs
)
1606 const gdb_byte
*regs
= gregs
;
1609 if (regnum
== SPARC32_PSR_REGNUM
|| regnum
== -1)
1610 regcache_raw_supply (regcache
, SPARC32_PSR_REGNUM
,
1611 regs
+ gregset
->r_psr_offset
);
1613 if (regnum
== SPARC32_PC_REGNUM
|| regnum
== -1)
1614 regcache_raw_supply (regcache
, SPARC32_PC_REGNUM
,
1615 regs
+ gregset
->r_pc_offset
);
1617 if (regnum
== SPARC32_NPC_REGNUM
|| regnum
== -1)
1618 regcache_raw_supply (regcache
, SPARC32_NPC_REGNUM
,
1619 regs
+ gregset
->r_npc_offset
);
1621 if (regnum
== SPARC32_Y_REGNUM
|| regnum
== -1)
1622 regcache_raw_supply (regcache
, SPARC32_Y_REGNUM
,
1623 regs
+ gregset
->r_y_offset
);
1625 if (regnum
== SPARC_G0_REGNUM
|| regnum
== -1)
1626 regcache_raw_supply (regcache
, SPARC_G0_REGNUM
, NULL
);
1628 if ((regnum
>= SPARC_G1_REGNUM
&& regnum
<= SPARC_O7_REGNUM
) || regnum
== -1)
1630 int offset
= gregset
->r_g1_offset
;
1632 for (i
= SPARC_G1_REGNUM
; i
<= SPARC_O7_REGNUM
; i
++)
1634 if (regnum
== i
|| regnum
== -1)
1635 regcache_raw_supply (regcache
, i
, regs
+ offset
);
1640 if ((regnum
>= SPARC_L0_REGNUM
&& regnum
<= SPARC_I7_REGNUM
) || regnum
== -1)
1642 /* Not all of the register set variants include Locals and
1643 Inputs. For those that don't, we read them off the stack. */
1644 if (gregset
->r_l0_offset
== -1)
1648 regcache_cooked_read_unsigned (regcache
, SPARC_SP_REGNUM
, &sp
);
1649 sparc_supply_rwindow (regcache
, sp
, regnum
);
1653 int offset
= gregset
->r_l0_offset
;
1655 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1657 if (regnum
== i
|| regnum
== -1)
1658 regcache_raw_supply (regcache
, i
, regs
+ offset
);
1666 sparc32_collect_gregset (const struct sparc_gregset
*gregset
,
1667 const struct regcache
*regcache
,
1668 int regnum
, void *gregs
)
1670 gdb_byte
*regs
= gregs
;
1673 if (regnum
== SPARC32_PSR_REGNUM
|| regnum
== -1)
1674 regcache_raw_collect (regcache
, SPARC32_PSR_REGNUM
,
1675 regs
+ gregset
->r_psr_offset
);
1677 if (regnum
== SPARC32_PC_REGNUM
|| regnum
== -1)
1678 regcache_raw_collect (regcache
, SPARC32_PC_REGNUM
,
1679 regs
+ gregset
->r_pc_offset
);
1681 if (regnum
== SPARC32_NPC_REGNUM
|| regnum
== -1)
1682 regcache_raw_collect (regcache
, SPARC32_NPC_REGNUM
,
1683 regs
+ gregset
->r_npc_offset
);
1685 if (regnum
== SPARC32_Y_REGNUM
|| regnum
== -1)
1686 regcache_raw_collect (regcache
, SPARC32_Y_REGNUM
,
1687 regs
+ gregset
->r_y_offset
);
1689 if ((regnum
>= SPARC_G1_REGNUM
&& regnum
<= SPARC_O7_REGNUM
) || regnum
== -1)
1691 int offset
= gregset
->r_g1_offset
;
1693 /* %g0 is always zero. */
1694 for (i
= SPARC_G1_REGNUM
; i
<= SPARC_O7_REGNUM
; i
++)
1696 if (regnum
== i
|| regnum
== -1)
1697 regcache_raw_collect (regcache
, i
, regs
+ offset
);
1702 if ((regnum
>= SPARC_L0_REGNUM
&& regnum
<= SPARC_I7_REGNUM
) || regnum
== -1)
1704 /* Not all of the register set variants include Locals and
1705 Inputs. For those that don't, we read them off the stack. */
1706 if (gregset
->r_l0_offset
!= -1)
1708 int offset
= gregset
->r_l0_offset
;
1710 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1712 if (regnum
== i
|| regnum
== -1)
1713 regcache_raw_collect (regcache
, i
, regs
+ offset
);
1721 sparc32_supply_fpregset (struct regcache
*regcache
,
1722 int regnum
, const void *fpregs
)
1724 const gdb_byte
*regs
= fpregs
;
1727 for (i
= 0; i
< 32; i
++)
1729 if (regnum
== (SPARC_F0_REGNUM
+ i
) || regnum
== -1)
1730 regcache_raw_supply (regcache
, SPARC_F0_REGNUM
+ i
, regs
+ (i
* 4));
1733 if (regnum
== SPARC32_FSR_REGNUM
|| regnum
== -1)
1734 regcache_raw_supply (regcache
, SPARC32_FSR_REGNUM
, regs
+ (32 * 4) + 4);
1738 sparc32_collect_fpregset (const struct regcache
*regcache
,
1739 int regnum
, void *fpregs
)
1741 gdb_byte
*regs
= fpregs
;
1744 for (i
= 0; i
< 32; i
++)
1746 if (regnum
== (SPARC_F0_REGNUM
+ i
) || regnum
== -1)
1747 regcache_raw_collect (regcache
, SPARC_F0_REGNUM
+ i
, regs
+ (i
* 4));
1750 if (regnum
== SPARC32_FSR_REGNUM
|| regnum
== -1)
1751 regcache_raw_collect (regcache
, SPARC32_FSR_REGNUM
, regs
+ (32 * 4) + 4);
1757 /* From <machine/reg.h>. */
1758 const struct sparc_gregset sparc32_sunos4_gregset
=
1771 /* Provide a prototype to silence -Wmissing-prototypes. */
1772 void _initialize_sparc_tdep (void);
1775 _initialize_sparc_tdep (void)
1777 register_gdbarch_init (bfd_arch_sparc
, sparc32_gdbarch_init
);
1779 /* Initialize the SPARC-specific register types. */