1 /* Target-dependent code for SPARC.
3 Copyright (C) 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include "arch-utils.h"
24 #include "dwarf2-frame.h"
25 #include "floatformat.h"
27 #include "frame-base.h"
28 #include "frame-unwind.h"
39 #include "gdb_assert.h"
40 #include "gdb_string.h"
42 #include "sparc-tdep.h"
46 /* This file implements the SPARC 32-bit ABI as defined by the section
47 "Low-Level System Information" of the SPARC Compliance Definition
48 (SCD) 2.4.1, which is the 32-bit System V psABI for SPARC. The SCD
49 lists changes with respect to the original 32-bit psABI as defined
50 in the "System V ABI, SPARC Processor Supplement".
52 Note that if we talk about SunOS, we mean SunOS 4.x, which was
53 BSD-based, which is sometimes (retroactively?) referred to as
54 Solaris 1.x. If we talk about Solaris we mean Solaris 2.x and
55 above (Solaris 7, 8 and 9 are nothing but Solaris 2.7, 2.8 and 2.9
56 suffering from severe version number inflation). Solaris 2.x is
57 also known as SunOS 5.x, since that's what uname(1) says. Solaris
60 /* Please use the sparc32_-prefix for 32-bit specific code, the
61 sparc64_-prefix for 64-bit specific code and the sparc_-prefix for
62 code that can handle both. The 64-bit specific code lives in
63 sparc64-tdep.c; don't add any here. */
65 /* The SPARC Floating-Point Quad-Precision format is similar to
66 big-endian IA-64 Quad-recision format. */
67 #define floatformats_sparc_quad floatformats_ia64_quad
69 /* The stack pointer is offset from the stack frame by a BIAS of 2047
70 (0x7ff) for 64-bit code. BIAS is likely to be defined on SPARC
71 hosts, so undefine it first. */
75 /* Macros to extract fields from SPARC instructions. */
76 #define X_OP(i) (((i) >> 30) & 0x3)
77 #define X_RD(i) (((i) >> 25) & 0x1f)
78 #define X_A(i) (((i) >> 29) & 1)
79 #define X_COND(i) (((i) >> 25) & 0xf)
80 #define X_OP2(i) (((i) >> 22) & 0x7)
81 #define X_IMM22(i) ((i) & 0x3fffff)
82 #define X_OP3(i) (((i) >> 19) & 0x3f)
83 #define X_RS1(i) (((i) >> 14) & 0x1f)
84 #define X_RS2(i) ((i) & 0x1f)
85 #define X_I(i) (((i) >> 13) & 1)
86 /* Sign extension macros. */
87 #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000)
88 #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000)
89 #define X_SIMM13(i) ((((i) & 0x1fff) ^ 0x1000) - 0x1000)
91 /* Fetch the instruction at PC. Instructions are always big-endian
92 even if the processor operates in little-endian mode. */
95 sparc_fetch_instruction (CORE_ADDR pc
)
101 /* If we can't read the instruction at PC, return zero. */
102 if (target_read_memory (pc
, buf
, sizeof (buf
)))
106 for (i
= 0; i
< sizeof (buf
); i
++)
107 insn
= (insn
<< 8) | buf
[i
];
112 /* Return non-zero if the instruction corresponding to PC is an "unimp"
116 sparc_is_unimp_insn (CORE_ADDR pc
)
118 const unsigned long insn
= sparc_fetch_instruction (pc
);
120 return ((insn
& 0xc1c00000) == 0);
123 /* OpenBSD/sparc includes StackGhost, which according to the author's
124 website http://stackghost.cerias.purdue.edu "... transparently and
125 automatically protects applications' stack frames; more
126 specifically, it guards the return pointers. The protection
127 mechanisms require no application source or binary modification and
128 imposes only a negligible performance penalty."
130 The same website provides the following description of how
133 "StackGhost interfaces with the kernel trap handler that would
134 normally write out registers to the stack and the handler that
135 would read them back in. By XORing a cookie into the
136 return-address saved in the user stack when it is actually written
137 to the stack, and then XOR it out when the return-address is pulled
138 from the stack, StackGhost can cause attacker corrupted return
139 pointers to behave in a manner the attacker cannot predict.
140 StackGhost can also use several unused bits in the return pointer
141 to detect a smashed return pointer and abort the process."
143 For GDB this means that whenever we're reading %i7 from a stack
144 frame's window save area, we'll have to XOR the cookie.
146 More information on StackGuard can be found on in:
148 Mike Frantzen and Mike Shuey. "StackGhost: Hardware Facilitated
149 Stack Protection." 2001. Published in USENIX Security Symposium
152 /* Fetch StackGhost Per-Process XOR cookie. */
155 sparc_fetch_wcookie (void)
157 struct target_ops
*ops
= ¤t_target
;
161 len
= target_read (ops
, TARGET_OBJECT_WCOOKIE
, NULL
, buf
, 0, 8);
165 /* We should have either an 32-bit or an 64-bit cookie. */
166 gdb_assert (len
== 4 || len
== 8);
168 return extract_unsigned_integer (buf
, len
);
172 /* The functions on this page are intended to be used to classify
173 function arguments. */
175 /* Check whether TYPE is "Integral or Pointer". */
178 sparc_integral_or_pointer_p (const struct type
*type
)
180 int len
= TYPE_LENGTH (type
);
182 switch (TYPE_CODE (type
))
188 case TYPE_CODE_RANGE
:
189 /* We have byte, half-word, word and extended-word/doubleword
190 integral types. The doubleword is an extension to the
191 original 32-bit ABI by the SCD 2.4.x. */
192 return (len
== 1 || len
== 2 || len
== 4 || len
== 8);
195 /* Allow either 32-bit or 64-bit pointers. */
196 return (len
== 4 || len
== 8);
204 /* Check whether TYPE is "Floating". */
207 sparc_floating_p (const struct type
*type
)
209 switch (TYPE_CODE (type
))
213 int len
= TYPE_LENGTH (type
);
214 return (len
== 4 || len
== 8 || len
== 16);
223 /* Check whether TYPE is "Structure or Union". */
226 sparc_structure_or_union_p (const struct type
*type
)
228 switch (TYPE_CODE (type
))
230 case TYPE_CODE_STRUCT
:
231 case TYPE_CODE_UNION
:
240 /* Register information. */
242 static const char *sparc32_register_names
[] =
244 "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
245 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
246 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
247 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
249 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
250 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
251 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
252 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
254 "y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr"
257 /* Total number of registers. */
258 #define SPARC32_NUM_REGS ARRAY_SIZE (sparc32_register_names)
260 /* We provide the aliases %d0..%d30 for the floating registers as
261 "psuedo" registers. */
263 static const char *sparc32_pseudo_register_names
[] =
265 "d0", "d2", "d4", "d6", "d8", "d10", "d12", "d14",
266 "d16", "d18", "d20", "d22", "d24", "d26", "d28", "d30"
269 /* Total number of pseudo registers. */
270 #define SPARC32_NUM_PSEUDO_REGS ARRAY_SIZE (sparc32_pseudo_register_names)
272 /* Return the name of register REGNUM. */
275 sparc32_register_name (struct gdbarch
*gdbarch
, int regnum
)
277 if (regnum
>= 0 && regnum
< SPARC32_NUM_REGS
)
278 return sparc32_register_names
[regnum
];
280 if (regnum
< SPARC32_NUM_REGS
+ SPARC32_NUM_PSEUDO_REGS
)
281 return sparc32_pseudo_register_names
[regnum
- SPARC32_NUM_REGS
];
288 struct type
*sparc_psr_type
;
291 struct type
*sparc_fsr_type
;
293 /* Construct types for ISA-specific registers. */
296 sparc_init_types (void)
300 type
= init_flags_type ("builtin_type_sparc_psr", 4);
301 append_flags_type_flag (type
, 5, "ET");
302 append_flags_type_flag (type
, 6, "PS");
303 append_flags_type_flag (type
, 7, "S");
304 append_flags_type_flag (type
, 12, "EF");
305 append_flags_type_flag (type
, 13, "EC");
306 sparc_psr_type
= type
;
308 type
= init_flags_type ("builtin_type_sparc_fsr", 4);
309 append_flags_type_flag (type
, 0, "NXA");
310 append_flags_type_flag (type
, 1, "DZA");
311 append_flags_type_flag (type
, 2, "UFA");
312 append_flags_type_flag (type
, 3, "OFA");
313 append_flags_type_flag (type
, 4, "NVA");
314 append_flags_type_flag (type
, 5, "NXC");
315 append_flags_type_flag (type
, 6, "DZC");
316 append_flags_type_flag (type
, 7, "UFC");
317 append_flags_type_flag (type
, 8, "OFC");
318 append_flags_type_flag (type
, 9, "NVC");
319 append_flags_type_flag (type
, 22, "NS");
320 append_flags_type_flag (type
, 23, "NXM");
321 append_flags_type_flag (type
, 24, "DZM");
322 append_flags_type_flag (type
, 25, "UFM");
323 append_flags_type_flag (type
, 26, "OFM");
324 append_flags_type_flag (type
, 27, "NVM");
325 sparc_fsr_type
= type
;
328 /* Return the GDB type object for the "standard" data type of data in
332 sparc32_register_type (struct gdbarch
*gdbarch
, int regnum
)
334 if (regnum
>= SPARC_F0_REGNUM
&& regnum
<= SPARC_F31_REGNUM
)
335 return builtin_type (gdbarch
)->builtin_float
;
337 if (regnum
>= SPARC32_D0_REGNUM
&& regnum
<= SPARC32_D30_REGNUM
)
338 return builtin_type (gdbarch
)->builtin_double
;
340 if (regnum
== SPARC_SP_REGNUM
|| regnum
== SPARC_FP_REGNUM
)
341 return builtin_type (gdbarch
)->builtin_data_ptr
;
343 if (regnum
== SPARC32_PC_REGNUM
|| regnum
== SPARC32_NPC_REGNUM
)
344 return builtin_type (gdbarch
)->builtin_func_ptr
;
346 if (regnum
== SPARC32_PSR_REGNUM
)
347 return sparc_psr_type
;
349 if (regnum
== SPARC32_FSR_REGNUM
)
350 return sparc_fsr_type
;
352 return builtin_type (gdbarch
)->builtin_int32
;
356 sparc32_pseudo_register_read (struct gdbarch
*gdbarch
,
357 struct regcache
*regcache
,
358 int regnum
, gdb_byte
*buf
)
360 gdb_assert (regnum
>= SPARC32_D0_REGNUM
&& regnum
<= SPARC32_D30_REGNUM
);
362 regnum
= SPARC_F0_REGNUM
+ 2 * (regnum
- SPARC32_D0_REGNUM
);
363 regcache_raw_read (regcache
, regnum
, buf
);
364 regcache_raw_read (regcache
, regnum
+ 1, buf
+ 4);
368 sparc32_pseudo_register_write (struct gdbarch
*gdbarch
,
369 struct regcache
*regcache
,
370 int regnum
, const gdb_byte
*buf
)
372 gdb_assert (regnum
>= SPARC32_D0_REGNUM
&& regnum
<= SPARC32_D30_REGNUM
);
374 regnum
= SPARC_F0_REGNUM
+ 2 * (regnum
- SPARC32_D0_REGNUM
);
375 regcache_raw_write (regcache
, regnum
, buf
);
376 regcache_raw_write (regcache
, regnum
+ 1, buf
+ 4);
381 sparc32_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
383 struct value
**args
, int nargs
,
384 struct type
*value_type
,
385 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
386 struct regcache
*regcache
)
391 if (using_struct_return (gdbarch
, NULL
, value_type
))
395 /* This is an UNIMP instruction. */
396 store_unsigned_integer (buf
, 4, TYPE_LENGTH (value_type
) & 0x1fff);
397 write_memory (sp
- 8, buf
, 4);
405 sparc32_store_arguments (struct regcache
*regcache
, int nargs
,
406 struct value
**args
, CORE_ADDR sp
,
407 int struct_return
, CORE_ADDR struct_addr
)
409 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
410 /* Number of words in the "parameter array". */
411 int num_elements
= 0;
415 for (i
= 0; i
< nargs
; i
++)
417 struct type
*type
= value_type (args
[i
]);
418 int len
= TYPE_LENGTH (type
);
420 if (sparc_structure_or_union_p (type
)
421 || (sparc_floating_p (type
) && len
== 16))
423 /* Structure, Union and Quad-Precision Arguments. */
426 /* Use doubleword alignment for these values. That's always
427 correct, and wasting a few bytes shouldn't be a problem. */
430 write_memory (sp
, value_contents (args
[i
]), len
);
431 args
[i
] = value_from_pointer (lookup_pointer_type (type
), sp
);
434 else if (sparc_floating_p (type
))
436 /* Floating arguments. */
437 gdb_assert (len
== 4 || len
== 8);
438 num_elements
+= (len
/ 4);
442 /* Integral and pointer arguments. */
443 gdb_assert (sparc_integral_or_pointer_p (type
));
446 args
[i
] = value_cast (builtin_type (gdbarch
)->builtin_int32
,
448 num_elements
+= ((len
+ 3) / 4);
452 /* Always allocate at least six words. */
453 sp
-= max (6, num_elements
) * 4;
455 /* The psABI says that "Software convention requires space for the
456 struct/union return value pointer, even if the word is unused." */
459 /* The psABI says that "Although software convention and the
460 operating system require every stack frame to be doubleword
464 for (i
= 0; i
< nargs
; i
++)
466 const bfd_byte
*valbuf
= value_contents (args
[i
]);
467 struct type
*type
= value_type (args
[i
]);
468 int len
= TYPE_LENGTH (type
);
470 gdb_assert (len
== 4 || len
== 8);
474 int regnum
= SPARC_O0_REGNUM
+ element
;
476 regcache_cooked_write (regcache
, regnum
, valbuf
);
477 if (len
> 4 && element
< 5)
478 regcache_cooked_write (regcache
, regnum
+ 1, valbuf
+ 4);
481 /* Always store the argument in memory. */
482 write_memory (sp
+ 4 + element
* 4, valbuf
, len
);
486 gdb_assert (element
== num_elements
);
492 store_unsigned_integer (buf
, 4, struct_addr
);
493 write_memory (sp
, buf
, 4);
500 sparc32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
501 struct regcache
*regcache
, CORE_ADDR bp_addr
,
502 int nargs
, struct value
**args
, CORE_ADDR sp
,
503 int struct_return
, CORE_ADDR struct_addr
)
505 CORE_ADDR call_pc
= (struct_return
? (bp_addr
- 12) : (bp_addr
- 8));
507 /* Set return address. */
508 regcache_cooked_write_unsigned (regcache
, SPARC_O7_REGNUM
, call_pc
);
510 /* Set up function arguments. */
511 sp
= sparc32_store_arguments (regcache
, nargs
, args
, sp
,
512 struct_return
, struct_addr
);
514 /* Allocate the 16-word window save area. */
517 /* Stack should be doubleword aligned at this point. */
518 gdb_assert (sp
% 8 == 0);
520 /* Finally, update the stack pointer. */
521 regcache_cooked_write_unsigned (regcache
, SPARC_SP_REGNUM
, sp
);
527 /* Use the program counter to determine the contents and size of a
528 breakpoint instruction. Return a pointer to a string of bytes that
529 encode a breakpoint instruction, store the length of the string in
530 *LEN and optionally adjust *PC to point to the correct memory
531 location for inserting the breakpoint. */
533 static const gdb_byte
*
534 sparc_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pc
, int *len
)
536 static const gdb_byte break_insn
[] = { 0x91, 0xd0, 0x20, 0x01 };
538 *len
= sizeof (break_insn
);
543 /* Allocate and initialize a frame cache. */
545 static struct sparc_frame_cache
*
546 sparc_alloc_frame_cache (void)
548 struct sparc_frame_cache
*cache
;
551 cache
= FRAME_OBSTACK_ZALLOC (struct sparc_frame_cache
);
557 /* Frameless until proven otherwise. */
558 cache
->frameless_p
= 1;
560 cache
->struct_return_p
= 0;
565 /* GCC generates several well-known sequences of instructions at the begining
566 of each function prologue when compiling with -fstack-check. If one of
567 such sequences starts at START_PC, then return the address of the
568 instruction immediately past this sequence. Otherwise, return START_PC. */
571 sparc_skip_stack_check (const CORE_ADDR start_pc
)
573 CORE_ADDR pc
= start_pc
;
575 int offset_stack_checking_sequence
= 0;
577 /* With GCC, all stack checking sequences begin with the same two
580 /* sethi <some immediate>,%g1 */
581 insn
= sparc_fetch_instruction (pc
);
583 if (!(X_OP (insn
) == 0 && X_OP2 (insn
) == 0x4 && X_RD (insn
) == 1))
586 /* sub %sp, %g1, %g1 */
587 insn
= sparc_fetch_instruction (pc
);
589 if (!(X_OP (insn
) == 2 && X_OP3 (insn
) == 0x4 && !X_I(insn
)
590 && X_RD (insn
) == 1 && X_RS1 (insn
) == 14 && X_RS2 (insn
) == 1))
593 insn
= sparc_fetch_instruction (pc
);
596 /* First possible sequence:
597 [first two instructions above]
598 clr [%g1 - some immediate] */
600 /* clr [%g1 - some immediate] */
601 if (X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && X_I(insn
)
602 && X_RS1 (insn
) == 1 && X_RD (insn
) == 0)
604 /* Valid stack-check sequence, return the new PC. */
608 /* Second possible sequence: A small number of probes.
609 [first two instructions above]
611 add %g1, -<some immediate>, %g1
613 [repeat the two instructions above any (small) number of times]
614 clr [%g1 - some immediate] */
617 else if (X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && !X_I(insn
)
618 && X_RS1 (insn
) == 1 && X_RD (insn
) == 0)
622 /* add %g1, -<some immediate>, %g1 */
623 insn
= sparc_fetch_instruction (pc
);
625 if (!(X_OP (insn
) == 2 && X_OP3(insn
) == 0 && X_I(insn
)
626 && X_RS1 (insn
) == 1 && X_RD (insn
) == 1))
630 insn
= sparc_fetch_instruction (pc
);
632 if (!(X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && !X_I(insn
)
633 && X_RD (insn
) == 0 && X_RS1 (insn
) == 1))
637 /* clr [%g1 - some immediate] */
638 if (!(X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && X_I(insn
)
639 && X_RS1 (insn
) == 1 && X_RD (insn
) == 0))
642 /* We found a valid stack-check sequence, return the new PC. */
646 /* Third sequence: A probing loop.
647 [first two instructions above]
648 sethi <some immediate>, %g4
652 add %g1, -<some immediate>, %g1
655 clr [%g4 - some immediate] */
657 /* sethi <some immediate>, %g4 */
658 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 0x4 && X_RD (insn
) == 4)
660 /* sub %g1, %g4, %g4 */
661 insn
= sparc_fetch_instruction (pc
);
663 if (!(X_OP (insn
) == 2 && X_OP3 (insn
) == 0x4 && !X_I(insn
)
664 && X_RD (insn
) == 4 && X_RS1 (insn
) == 1 && X_RS2 (insn
) == 4))
668 insn
= sparc_fetch_instruction (pc
);
670 if (!(X_OP (insn
) == 2 && X_OP3 (insn
) == 0x14 && !X_I(insn
)
671 && X_RD (insn
) == 0 && X_RS1 (insn
) == 1 && X_RS2 (insn
) == 4))
675 insn
= sparc_fetch_instruction (pc
);
677 if (!(X_OP (insn
) == 0 && X_COND (insn
) == 0x1))
680 /* add %g1, -<some immediate>, %g1 */
681 insn
= sparc_fetch_instruction (pc
);
683 if (!(X_OP (insn
) == 2 && X_OP3(insn
) == 0 && X_I(insn
)
684 && X_RS1 (insn
) == 1 && X_RD (insn
) == 1))
688 insn
= sparc_fetch_instruction (pc
);
690 if (!(X_OP (insn
) == 0 && X_COND (insn
) == 0x8))
694 insn
= sparc_fetch_instruction (pc
);
696 if (!(X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && !X_I(insn
)
697 && X_RD (insn
) == 0 && X_RS1 (insn
) == 1))
700 /* clr [%g4 - some immediate] */
701 insn
= sparc_fetch_instruction (pc
);
703 if (!(X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && X_I(insn
)
704 && X_RS1 (insn
) == 4 && X_RD (insn
) == 0))
707 /* We found a valid stack-check sequence, return the new PC. */
711 /* No stack check code in our prologue, return the start_pc. */
716 sparc_analyze_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
717 CORE_ADDR current_pc
, struct sparc_frame_cache
*cache
)
719 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
724 pc
= sparc_skip_stack_check (pc
);
726 if (current_pc
<= pc
)
729 /* We have to handle to "Procedure Linkage Table" (PLT) special. On
730 SPARC the linker usually defines a symbol (typically
731 _PROCEDURE_LINKAGE_TABLE_) at the start of the .plt section.
732 This symbol makes us end up here with PC pointing at the start of
733 the PLT and CURRENT_PC probably pointing at a PLT entry. If we
734 would do our normal prologue analysis, we would probably conclude
735 that we've got a frame when in reality we don't, since the
736 dynamic linker patches up the first PLT with some code that
737 starts with a SAVE instruction. Patch up PC such that it points
738 at the start of our PLT entry. */
739 if (tdep
->plt_entry_size
> 0 && in_plt_section (current_pc
, NULL
))
740 pc
= current_pc
- ((current_pc
- pc
) % tdep
->plt_entry_size
);
742 insn
= sparc_fetch_instruction (pc
);
744 /* Recognize a SETHI insn and record its destination. */
745 if (X_OP (insn
) == 0 && X_OP2 (insn
) == 0x04)
750 insn
= sparc_fetch_instruction (pc
+ 4);
753 /* Allow for an arithmetic operation on DEST or %g1. */
754 if (X_OP (insn
) == 2 && X_I (insn
)
755 && (X_RD (insn
) == 1 || X_RD (insn
) == dest
))
759 insn
= sparc_fetch_instruction (pc
+ 8);
762 /* Check for the SAVE instruction that sets up the frame. */
763 if (X_OP (insn
) == 2 && X_OP3 (insn
) == 0x3c)
765 cache
->frameless_p
= 0;
766 return pc
+ offset
+ 4;
773 sparc_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
775 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
776 return frame_unwind_register_unsigned (this_frame
, tdep
->pc_regnum
);
779 /* Return PC of first real instruction of the function starting at
783 sparc32_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
785 struct symtab_and_line sal
;
786 CORE_ADDR func_start
, func_end
;
787 struct sparc_frame_cache cache
;
789 /* This is the preferred method, find the end of the prologue by
790 using the debugging information. */
791 if (find_pc_partial_function (start_pc
, NULL
, &func_start
, &func_end
))
793 sal
= find_pc_line (func_start
, 0);
795 if (sal
.end
< func_end
796 && start_pc
<= sal
.end
)
800 start_pc
= sparc_analyze_prologue (gdbarch
, start_pc
, 0xffffffffUL
, &cache
);
802 /* The psABI says that "Although the first 6 words of arguments
803 reside in registers, the standard stack frame reserves space for
804 them.". It also suggests that a function may use that space to
805 "write incoming arguments 0 to 5" into that space, and that's
806 indeed what GCC seems to be doing. In that case GCC will
807 generate debug information that points to the stack slots instead
808 of the registers, so we should consider the instructions that
809 write out these incoming arguments onto the stack. Of course we
810 only need to do this if we have a stack frame. */
812 while (!cache
.frameless_p
)
814 unsigned long insn
= sparc_fetch_instruction (start_pc
);
816 /* Recognize instructions that store incoming arguments in
817 %i0...%i5 into the corresponding stack slot. */
818 if (X_OP (insn
) == 3 && (X_OP3 (insn
) & 0x3c) == 0x04 && X_I (insn
)
819 && (X_RD (insn
) >= 24 && X_RD (insn
) <= 29) && X_RS1 (insn
) == 30
820 && X_SIMM13 (insn
) == 68 + (X_RD (insn
) - 24) * 4)
834 struct sparc_frame_cache
*
835 sparc_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
837 struct sparc_frame_cache
*cache
;
842 cache
= sparc_alloc_frame_cache ();
845 cache
->pc
= get_frame_func (this_frame
);
847 sparc_analyze_prologue (get_frame_arch (this_frame
), cache
->pc
,
848 get_frame_pc (this_frame
), cache
);
850 if (cache
->frameless_p
)
852 /* This function is frameless, so %fp (%i6) holds the frame
853 pointer for our calling frame. Use %sp (%o6) as this frame's
856 get_frame_register_unsigned (this_frame
, SPARC_SP_REGNUM
);
860 /* For normal frames, %fp (%i6) holds the frame pointer, the
861 base address for the current stack frame. */
863 get_frame_register_unsigned (this_frame
, SPARC_FP_REGNUM
);
873 sparc32_struct_return_from_sym (struct symbol
*sym
)
875 struct type
*type
= check_typedef (SYMBOL_TYPE (sym
));
876 enum type_code code
= TYPE_CODE (type
);
878 if (code
== TYPE_CODE_FUNC
|| code
== TYPE_CODE_METHOD
)
880 type
= check_typedef (TYPE_TARGET_TYPE (type
));
881 if (sparc_structure_or_union_p (type
)
882 || (sparc_floating_p (type
) && TYPE_LENGTH (type
) == 16))
889 struct sparc_frame_cache
*
890 sparc32_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
892 struct sparc_frame_cache
*cache
;
898 cache
= sparc_frame_cache (this_frame
, this_cache
);
900 sym
= find_pc_function (cache
->pc
);
903 cache
->struct_return_p
= sparc32_struct_return_from_sym (sym
);
907 /* There is no debugging information for this function to
908 help us determine whether this function returns a struct
909 or not. So we rely on another heuristic which is to check
910 the instruction at the return address and see if this is
911 an "unimp" instruction. If it is, then it is a struct-return
914 int regnum
= cache
->frameless_p
? SPARC_O7_REGNUM
: SPARC_I7_REGNUM
;
916 pc
= get_frame_register_unsigned (this_frame
, regnum
) + 8;
917 if (sparc_is_unimp_insn (pc
))
918 cache
->struct_return_p
= 1;
925 sparc32_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
926 struct frame_id
*this_id
)
928 struct sparc_frame_cache
*cache
=
929 sparc32_frame_cache (this_frame
, this_cache
);
931 /* This marks the outermost frame. */
932 if (cache
->base
== 0)
935 (*this_id
) = frame_id_build (cache
->base
, cache
->pc
);
938 static struct value
*
939 sparc32_frame_prev_register (struct frame_info
*this_frame
,
940 void **this_cache
, int regnum
)
942 struct sparc_frame_cache
*cache
=
943 sparc32_frame_cache (this_frame
, this_cache
);
945 if (regnum
== SPARC32_PC_REGNUM
|| regnum
== SPARC32_NPC_REGNUM
)
947 CORE_ADDR pc
= (regnum
== SPARC32_NPC_REGNUM
) ? 4 : 0;
949 /* If this functions has a Structure, Union or Quad-Precision
950 return value, we have to skip the UNIMP instruction that encodes
951 the size of the structure. */
952 if (cache
->struct_return_p
)
955 regnum
= cache
->frameless_p
? SPARC_O7_REGNUM
: SPARC_I7_REGNUM
;
956 pc
+= get_frame_register_unsigned (this_frame
, regnum
) + 8;
957 return frame_unwind_got_constant (this_frame
, regnum
, pc
);
960 /* Handle StackGhost. */
962 ULONGEST wcookie
= sparc_fetch_wcookie ();
964 if (wcookie
!= 0 && !cache
->frameless_p
&& regnum
== SPARC_I7_REGNUM
)
966 CORE_ADDR addr
= cache
->base
+ (regnum
- SPARC_L0_REGNUM
) * 4;
969 /* Read the value in from memory. */
970 i7
= get_frame_memory_unsigned (this_frame
, addr
, 4);
971 return frame_unwind_got_constant (this_frame
, regnum
, i7
^ wcookie
);
975 /* The previous frame's `local' and `in' registers have been saved
976 in the register save area. */
977 if (!cache
->frameless_p
978 && regnum
>= SPARC_L0_REGNUM
&& regnum
<= SPARC_I7_REGNUM
)
980 CORE_ADDR addr
= cache
->base
+ (regnum
- SPARC_L0_REGNUM
) * 4;
982 return frame_unwind_got_memory (this_frame
, regnum
, addr
);
985 /* The previous frame's `out' registers are accessible as the
986 current frame's `in' registers. */
987 if (!cache
->frameless_p
988 && regnum
>= SPARC_O0_REGNUM
&& regnum
<= SPARC_O7_REGNUM
)
989 regnum
+= (SPARC_I0_REGNUM
- SPARC_O0_REGNUM
);
991 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
994 static const struct frame_unwind sparc32_frame_unwind
=
997 sparc32_frame_this_id
,
998 sparc32_frame_prev_register
,
1000 default_frame_sniffer
1005 sparc32_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
1007 struct sparc_frame_cache
*cache
=
1008 sparc32_frame_cache (this_frame
, this_cache
);
1013 static const struct frame_base sparc32_frame_base
=
1015 &sparc32_frame_unwind
,
1016 sparc32_frame_base_address
,
1017 sparc32_frame_base_address
,
1018 sparc32_frame_base_address
1021 static struct frame_id
1022 sparc_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1026 sp
= get_frame_register_unsigned (this_frame
, SPARC_SP_REGNUM
);
1029 return frame_id_build (sp
, get_frame_pc (this_frame
));
1033 /* Extract a function return value of TYPE from REGCACHE, and copy
1034 that into VALBUF. */
1037 sparc32_extract_return_value (struct type
*type
, struct regcache
*regcache
,
1040 int len
= TYPE_LENGTH (type
);
1043 gdb_assert (!sparc_structure_or_union_p (type
));
1044 gdb_assert (!(sparc_floating_p (type
) && len
== 16));
1046 if (sparc_floating_p (type
))
1048 /* Floating return values. */
1049 regcache_cooked_read (regcache
, SPARC_F0_REGNUM
, buf
);
1051 regcache_cooked_read (regcache
, SPARC_F1_REGNUM
, buf
+ 4);
1052 memcpy (valbuf
, buf
, len
);
1056 /* Integral and pointer return values. */
1057 gdb_assert (sparc_integral_or_pointer_p (type
));
1059 regcache_cooked_read (regcache
, SPARC_O0_REGNUM
, buf
);
1062 regcache_cooked_read (regcache
, SPARC_O1_REGNUM
, buf
+ 4);
1063 gdb_assert (len
== 8);
1064 memcpy (valbuf
, buf
, 8);
1068 /* Just stripping off any unused bytes should preserve the
1069 signed-ness just fine. */
1070 memcpy (valbuf
, buf
+ 4 - len
, len
);
1075 /* Store the function return value of type TYPE from VALBUF into
1079 sparc32_store_return_value (struct type
*type
, struct regcache
*regcache
,
1080 const gdb_byte
*valbuf
)
1082 int len
= TYPE_LENGTH (type
);
1085 gdb_assert (!sparc_structure_or_union_p (type
));
1086 gdb_assert (!(sparc_floating_p (type
) && len
== 16));
1088 if (sparc_floating_p (type
))
1090 /* Floating return values. */
1091 memcpy (buf
, valbuf
, len
);
1092 regcache_cooked_write (regcache
, SPARC_F0_REGNUM
, buf
);
1094 regcache_cooked_write (regcache
, SPARC_F1_REGNUM
, buf
+ 4);
1098 /* Integral and pointer return values. */
1099 gdb_assert (sparc_integral_or_pointer_p (type
));
1103 gdb_assert (len
== 8);
1104 memcpy (buf
, valbuf
, 8);
1105 regcache_cooked_write (regcache
, SPARC_O1_REGNUM
, buf
+ 4);
1109 /* ??? Do we need to do any sign-extension here? */
1110 memcpy (buf
+ 4 - len
, valbuf
, len
);
1112 regcache_cooked_write (regcache
, SPARC_O0_REGNUM
, buf
);
1116 static enum return_value_convention
1117 sparc32_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
1118 struct type
*type
, struct regcache
*regcache
,
1119 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
1121 /* The psABI says that "...every stack frame reserves the word at
1122 %fp+64. If a function returns a structure, union, or
1123 quad-precision value, this word should hold the address of the
1124 object into which the return value should be copied." This
1125 guarantees that we can always find the return value, not just
1126 before the function returns. */
1128 if (sparc_structure_or_union_p (type
)
1129 || (sparc_floating_p (type
) && TYPE_LENGTH (type
) == 16))
1136 regcache_cooked_read_unsigned (regcache
, SPARC_SP_REGNUM
, &sp
);
1137 addr
= read_memory_unsigned_integer (sp
+ 64, 4);
1138 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
1141 return RETURN_VALUE_ABI_PRESERVES_ADDRESS
;
1145 sparc32_extract_return_value (type
, regcache
, readbuf
);
1147 sparc32_store_return_value (type
, regcache
, writebuf
);
1149 return RETURN_VALUE_REGISTER_CONVENTION
;
1153 sparc32_stabs_argument_has_addr (struct gdbarch
*gdbarch
, struct type
*type
)
1155 return (sparc_structure_or_union_p (type
)
1156 || (sparc_floating_p (type
) && TYPE_LENGTH (type
) == 16));
1160 sparc32_dwarf2_struct_return_p (struct frame_info
*this_frame
)
1162 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
1163 struct symbol
*sym
= find_pc_function (pc
);
1166 return sparc32_struct_return_from_sym (sym
);
1171 sparc32_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
1172 struct dwarf2_frame_state_reg
*reg
,
1173 struct frame_info
*this_frame
)
1179 case SPARC_G0_REGNUM
:
1180 /* Since %g0 is always zero, there is no point in saving it, and
1181 people will be inclined omit it from the CFI. Make sure we
1182 don't warn about that. */
1183 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
1185 case SPARC_SP_REGNUM
:
1186 reg
->how
= DWARF2_FRAME_REG_CFA
;
1188 case SPARC32_PC_REGNUM
:
1189 case SPARC32_NPC_REGNUM
:
1190 reg
->how
= DWARF2_FRAME_REG_RA_OFFSET
;
1192 if (sparc32_dwarf2_struct_return_p (this_frame
))
1194 if (regnum
== SPARC32_NPC_REGNUM
)
1196 reg
->loc
.offset
= off
;
1202 /* The SPARC Architecture doesn't have hardware single-step support,
1203 and most operating systems don't implement it either, so we provide
1204 software single-step mechanism. */
1207 sparc_analyze_control_transfer (struct frame_info
*frame
,
1208 CORE_ADDR pc
, CORE_ADDR
*npc
)
1210 unsigned long insn
= sparc_fetch_instruction (pc
);
1211 int conditional_p
= X_COND (insn
) & 0x7;
1213 long offset
= 0; /* Must be signed for sign-extend. */
1215 if (X_OP (insn
) == 0 && X_OP2 (insn
) == 3 && (insn
& 0x1000000) == 0)
1217 /* Branch on Integer Register with Prediction (BPr). */
1221 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 6)
1223 /* Branch on Floating-Point Condition Codes (FBfcc). */
1225 offset
= 4 * X_DISP22 (insn
);
1227 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 5)
1229 /* Branch on Floating-Point Condition Codes with Prediction
1232 offset
= 4 * X_DISP19 (insn
);
1234 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 2)
1236 /* Branch on Integer Condition Codes (Bicc). */
1238 offset
= 4 * X_DISP22 (insn
);
1240 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 1)
1242 /* Branch on Integer Condition Codes with Prediction (BPcc). */
1244 offset
= 4 * X_DISP19 (insn
);
1246 else if (X_OP (insn
) == 2 && X_OP3 (insn
) == 0x3a)
1248 /* Trap instruction (TRAP). */
1249 return gdbarch_tdep (get_frame_arch (frame
))->step_trap (frame
, insn
);
1252 /* FIXME: Handle DONE and RETRY instructions. */
1258 /* For conditional branches, return nPC + 4 iff the annul
1260 return (X_A (insn
) ? *npc
+ 4 : 0);
1264 /* For unconditional branches, return the target if its
1265 specified condition is "always" and return nPC + 4 if the
1266 condition is "never". If the annul bit is 1, set *NPC to
1268 if (X_COND (insn
) == 0x0)
1269 pc
= *npc
, offset
= 4;
1273 gdb_assert (offset
!= 0);
1282 sparc_step_trap (struct frame_info
*frame
, unsigned long insn
)
1288 sparc_software_single_step (struct frame_info
*frame
)
1290 struct gdbarch
*arch
= get_frame_arch (frame
);
1291 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
1292 CORE_ADDR npc
, nnpc
;
1294 CORE_ADDR pc
, orig_npc
;
1296 pc
= get_frame_register_unsigned (frame
, tdep
->pc_regnum
);
1297 orig_npc
= npc
= get_frame_register_unsigned (frame
, tdep
->npc_regnum
);
1299 /* Analyze the instruction at PC. */
1300 nnpc
= sparc_analyze_control_transfer (frame
, pc
, &npc
);
1302 insert_single_step_breakpoint (npc
);
1305 insert_single_step_breakpoint (nnpc
);
1307 /* Assert that we have set at least one breakpoint, and that
1308 they're not set at the same spot - unless we're going
1309 from here straight to NULL, i.e. a call or jump to 0. */
1310 gdb_assert (npc
!= 0 || nnpc
!= 0 || orig_npc
== 0);
1311 gdb_assert (nnpc
!= npc
|| orig_npc
== 0);
1317 sparc_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1319 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_regcache_arch (regcache
));
1321 regcache_cooked_write_unsigned (regcache
, tdep
->pc_regnum
, pc
);
1322 regcache_cooked_write_unsigned (regcache
, tdep
->npc_regnum
, pc
+ 4);
1326 /* Return the appropriate register set for the core section identified
1327 by SECT_NAME and SECT_SIZE. */
1329 static const struct regset
*
1330 sparc_regset_from_core_section (struct gdbarch
*gdbarch
,
1331 const char *sect_name
, size_t sect_size
)
1333 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1335 if (strcmp (sect_name
, ".reg") == 0 && sect_size
>= tdep
->sizeof_gregset
)
1336 return tdep
->gregset
;
1338 if (strcmp (sect_name
, ".reg2") == 0 && sect_size
>= tdep
->sizeof_fpregset
)
1339 return tdep
->fpregset
;
1345 static struct gdbarch
*
1346 sparc32_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
1348 struct gdbarch_tdep
*tdep
;
1349 struct gdbarch
*gdbarch
;
1351 /* If there is already a candidate, use it. */
1352 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
1354 return arches
->gdbarch
;
1356 /* Allocate space for the new architecture. */
1357 tdep
= XMALLOC (struct gdbarch_tdep
);
1358 gdbarch
= gdbarch_alloc (&info
, tdep
);
1360 tdep
->pc_regnum
= SPARC32_PC_REGNUM
;
1361 tdep
->npc_regnum
= SPARC32_NPC_REGNUM
;
1362 tdep
->gregset
= NULL
;
1363 tdep
->sizeof_gregset
= 0;
1364 tdep
->fpregset
= NULL
;
1365 tdep
->sizeof_fpregset
= 0;
1366 tdep
->plt_entry_size
= 0;
1367 tdep
->step_trap
= sparc_step_trap
;
1369 set_gdbarch_long_double_bit (gdbarch
, 128);
1370 set_gdbarch_long_double_format (gdbarch
, floatformats_sparc_quad
);
1372 set_gdbarch_num_regs (gdbarch
, SPARC32_NUM_REGS
);
1373 set_gdbarch_register_name (gdbarch
, sparc32_register_name
);
1374 set_gdbarch_register_type (gdbarch
, sparc32_register_type
);
1375 set_gdbarch_num_pseudo_regs (gdbarch
, SPARC32_NUM_PSEUDO_REGS
);
1376 set_gdbarch_pseudo_register_read (gdbarch
, sparc32_pseudo_register_read
);
1377 set_gdbarch_pseudo_register_write (gdbarch
, sparc32_pseudo_register_write
);
1379 /* Register numbers of various important registers. */
1380 set_gdbarch_sp_regnum (gdbarch
, SPARC_SP_REGNUM
); /* %sp */
1381 set_gdbarch_pc_regnum (gdbarch
, SPARC32_PC_REGNUM
); /* %pc */
1382 set_gdbarch_fp0_regnum (gdbarch
, SPARC_F0_REGNUM
); /* %f0 */
1384 /* Call dummy code. */
1385 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
1386 set_gdbarch_push_dummy_code (gdbarch
, sparc32_push_dummy_code
);
1387 set_gdbarch_push_dummy_call (gdbarch
, sparc32_push_dummy_call
);
1389 set_gdbarch_return_value (gdbarch
, sparc32_return_value
);
1390 set_gdbarch_stabs_argument_has_addr
1391 (gdbarch
, sparc32_stabs_argument_has_addr
);
1393 set_gdbarch_skip_prologue (gdbarch
, sparc32_skip_prologue
);
1395 /* Stack grows downward. */
1396 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
1398 set_gdbarch_breakpoint_from_pc (gdbarch
, sparc_breakpoint_from_pc
);
1400 set_gdbarch_frame_args_skip (gdbarch
, 8);
1402 set_gdbarch_print_insn (gdbarch
, print_insn_sparc
);
1404 set_gdbarch_software_single_step (gdbarch
, sparc_software_single_step
);
1405 set_gdbarch_write_pc (gdbarch
, sparc_write_pc
);
1407 set_gdbarch_dummy_id (gdbarch
, sparc_dummy_id
);
1409 set_gdbarch_unwind_pc (gdbarch
, sparc_unwind_pc
);
1411 frame_base_set_default (gdbarch
, &sparc32_frame_base
);
1413 /* Hook in the DWARF CFI frame unwinder. */
1414 dwarf2_frame_set_init_reg (gdbarch
, sparc32_dwarf2_frame_init_reg
);
1415 /* FIXME: kettenis/20050423: Don't enable the unwinder until the
1416 StackGhost issues have been resolved. */
1418 /* Hook in ABI-specific overrides, if they have been registered. */
1419 gdbarch_init_osabi (info
, gdbarch
);
1421 frame_unwind_append_unwinder (gdbarch
, &sparc32_frame_unwind
);
1423 /* If we have register sets, enable the generic core file support. */
1425 set_gdbarch_regset_from_core_section (gdbarch
,
1426 sparc_regset_from_core_section
);
1431 /* Helper functions for dealing with register windows. */
1434 sparc_supply_rwindow (struct regcache
*regcache
, CORE_ADDR sp
, int regnum
)
1442 /* Registers are 64-bit. */
1445 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1447 if (regnum
== i
|| regnum
== -1)
1449 target_read_memory (sp
+ ((i
- SPARC_L0_REGNUM
) * 8), buf
, 8);
1451 /* Handle StackGhost. */
1452 if (i
== SPARC_I7_REGNUM
)
1454 ULONGEST wcookie
= sparc_fetch_wcookie ();
1455 ULONGEST i7
= extract_unsigned_integer (buf
+ offset
, 8);
1457 store_unsigned_integer (buf
+ offset
, 8, i7
^ wcookie
);
1460 regcache_raw_supply (regcache
, i
, buf
);
1466 /* Registers are 32-bit. Toss any sign-extension of the stack
1470 /* Clear out the top half of the temporary buffer, and put the
1471 register value in the bottom half if we're in 64-bit mode. */
1472 if (gdbarch_ptr_bit (get_regcache_arch (regcache
)) == 64)
1478 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1480 if (regnum
== i
|| regnum
== -1)
1482 target_read_memory (sp
+ ((i
- SPARC_L0_REGNUM
) * 4),
1485 /* Handle StackGhost. */
1486 if (i
== SPARC_I7_REGNUM
)
1488 ULONGEST wcookie
= sparc_fetch_wcookie ();
1489 ULONGEST i7
= extract_unsigned_integer (buf
+ offset
, 4);
1491 store_unsigned_integer (buf
+ offset
, 4, i7
^ wcookie
);
1494 regcache_raw_supply (regcache
, i
, buf
);
1501 sparc_collect_rwindow (const struct regcache
*regcache
,
1502 CORE_ADDR sp
, int regnum
)
1510 /* Registers are 64-bit. */
1513 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1515 if (regnum
== -1 || regnum
== SPARC_SP_REGNUM
|| regnum
== i
)
1517 regcache_raw_collect (regcache
, i
, buf
);
1519 /* Handle StackGhost. */
1520 if (i
== SPARC_I7_REGNUM
)
1522 ULONGEST wcookie
= sparc_fetch_wcookie ();
1523 ULONGEST i7
= extract_unsigned_integer (buf
+ offset
, 8);
1525 store_unsigned_integer (buf
, 8, i7
^ wcookie
);
1528 target_write_memory (sp
+ ((i
- SPARC_L0_REGNUM
) * 8), buf
, 8);
1534 /* Registers are 32-bit. Toss any sign-extension of the stack
1538 /* Only use the bottom half if we're in 64-bit mode. */
1539 if (gdbarch_ptr_bit (get_regcache_arch (regcache
)) == 64)
1542 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1544 if (regnum
== -1 || regnum
== SPARC_SP_REGNUM
|| regnum
== i
)
1546 regcache_raw_collect (regcache
, i
, buf
);
1548 /* Handle StackGhost. */
1549 if (i
== SPARC_I7_REGNUM
)
1551 ULONGEST wcookie
= sparc_fetch_wcookie ();
1552 ULONGEST i7
= extract_unsigned_integer (buf
+ offset
, 4);
1554 store_unsigned_integer (buf
+ offset
, 4, i7
^ wcookie
);
1557 target_write_memory (sp
+ ((i
- SPARC_L0_REGNUM
) * 4),
1564 /* Helper functions for dealing with register sets. */
1567 sparc32_supply_gregset (const struct sparc_gregset
*gregset
,
1568 struct regcache
*regcache
,
1569 int regnum
, const void *gregs
)
1571 const gdb_byte
*regs
= gregs
;
1574 if (regnum
== SPARC32_PSR_REGNUM
|| regnum
== -1)
1575 regcache_raw_supply (regcache
, SPARC32_PSR_REGNUM
,
1576 regs
+ gregset
->r_psr_offset
);
1578 if (regnum
== SPARC32_PC_REGNUM
|| regnum
== -1)
1579 regcache_raw_supply (regcache
, SPARC32_PC_REGNUM
,
1580 regs
+ gregset
->r_pc_offset
);
1582 if (regnum
== SPARC32_NPC_REGNUM
|| regnum
== -1)
1583 regcache_raw_supply (regcache
, SPARC32_NPC_REGNUM
,
1584 regs
+ gregset
->r_npc_offset
);
1586 if (regnum
== SPARC32_Y_REGNUM
|| regnum
== -1)
1587 regcache_raw_supply (regcache
, SPARC32_Y_REGNUM
,
1588 regs
+ gregset
->r_y_offset
);
1590 if (regnum
== SPARC_G0_REGNUM
|| regnum
== -1)
1591 regcache_raw_supply (regcache
, SPARC_G0_REGNUM
, NULL
);
1593 if ((regnum
>= SPARC_G1_REGNUM
&& regnum
<= SPARC_O7_REGNUM
) || regnum
== -1)
1595 int offset
= gregset
->r_g1_offset
;
1597 for (i
= SPARC_G1_REGNUM
; i
<= SPARC_O7_REGNUM
; i
++)
1599 if (regnum
== i
|| regnum
== -1)
1600 regcache_raw_supply (regcache
, i
, regs
+ offset
);
1605 if ((regnum
>= SPARC_L0_REGNUM
&& regnum
<= SPARC_I7_REGNUM
) || regnum
== -1)
1607 /* Not all of the register set variants include Locals and
1608 Inputs. For those that don't, we read them off the stack. */
1609 if (gregset
->r_l0_offset
== -1)
1613 regcache_cooked_read_unsigned (regcache
, SPARC_SP_REGNUM
, &sp
);
1614 sparc_supply_rwindow (regcache
, sp
, regnum
);
1618 int offset
= gregset
->r_l0_offset
;
1620 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1622 if (regnum
== i
|| regnum
== -1)
1623 regcache_raw_supply (regcache
, i
, regs
+ offset
);
1631 sparc32_collect_gregset (const struct sparc_gregset
*gregset
,
1632 const struct regcache
*regcache
,
1633 int regnum
, void *gregs
)
1635 gdb_byte
*regs
= gregs
;
1638 if (regnum
== SPARC32_PSR_REGNUM
|| regnum
== -1)
1639 regcache_raw_collect (regcache
, SPARC32_PSR_REGNUM
,
1640 regs
+ gregset
->r_psr_offset
);
1642 if (regnum
== SPARC32_PC_REGNUM
|| regnum
== -1)
1643 regcache_raw_collect (regcache
, SPARC32_PC_REGNUM
,
1644 regs
+ gregset
->r_pc_offset
);
1646 if (regnum
== SPARC32_NPC_REGNUM
|| regnum
== -1)
1647 regcache_raw_collect (regcache
, SPARC32_NPC_REGNUM
,
1648 regs
+ gregset
->r_npc_offset
);
1650 if (regnum
== SPARC32_Y_REGNUM
|| regnum
== -1)
1651 regcache_raw_collect (regcache
, SPARC32_Y_REGNUM
,
1652 regs
+ gregset
->r_y_offset
);
1654 if ((regnum
>= SPARC_G1_REGNUM
&& regnum
<= SPARC_O7_REGNUM
) || regnum
== -1)
1656 int offset
= gregset
->r_g1_offset
;
1658 /* %g0 is always zero. */
1659 for (i
= SPARC_G1_REGNUM
; i
<= SPARC_O7_REGNUM
; i
++)
1661 if (regnum
== i
|| regnum
== -1)
1662 regcache_raw_collect (regcache
, i
, regs
+ offset
);
1667 if ((regnum
>= SPARC_L0_REGNUM
&& regnum
<= SPARC_I7_REGNUM
) || regnum
== -1)
1669 /* Not all of the register set variants include Locals and
1670 Inputs. For those that don't, we read them off the stack. */
1671 if (gregset
->r_l0_offset
!= -1)
1673 int offset
= gregset
->r_l0_offset
;
1675 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1677 if (regnum
== i
|| regnum
== -1)
1678 regcache_raw_collect (regcache
, i
, regs
+ offset
);
1686 sparc32_supply_fpregset (struct regcache
*regcache
,
1687 int regnum
, const void *fpregs
)
1689 const gdb_byte
*regs
= fpregs
;
1692 for (i
= 0; i
< 32; i
++)
1694 if (regnum
== (SPARC_F0_REGNUM
+ i
) || regnum
== -1)
1695 regcache_raw_supply (regcache
, SPARC_F0_REGNUM
+ i
, regs
+ (i
* 4));
1698 if (regnum
== SPARC32_FSR_REGNUM
|| regnum
== -1)
1699 regcache_raw_supply (regcache
, SPARC32_FSR_REGNUM
, regs
+ (32 * 4) + 4);
1703 sparc32_collect_fpregset (const struct regcache
*regcache
,
1704 int regnum
, void *fpregs
)
1706 gdb_byte
*regs
= fpregs
;
1709 for (i
= 0; i
< 32; i
++)
1711 if (regnum
== (SPARC_F0_REGNUM
+ i
) || regnum
== -1)
1712 regcache_raw_collect (regcache
, SPARC_F0_REGNUM
+ i
, regs
+ (i
* 4));
1715 if (regnum
== SPARC32_FSR_REGNUM
|| regnum
== -1)
1716 regcache_raw_collect (regcache
, SPARC32_FSR_REGNUM
, regs
+ (32 * 4) + 4);
1722 /* From <machine/reg.h>. */
1723 const struct sparc_gregset sparc32_sunos4_gregset
=
1736 /* Provide a prototype to silence -Wmissing-prototypes. */
1737 void _initialize_sparc_tdep (void);
1740 _initialize_sparc_tdep (void)
1742 register_gdbarch_init (bfd_arch_sparc
, sparc32_gdbarch_init
);
1744 /* Initialize the SPARC-specific register types. */