gdb/testsuite/gdb.arch/vsx-regs.exp

   1 # Copyright (C) 2008-2012 Free Software Foundation, Inc.
   2 #
   3 # This program is free software; you can redistribute it and/or modify
   4 # it under the terms of the GNU General Public License as published by
   5 # the Free Software Foundation; either version 3 of the License, or
   6 # (at your option) any later version.
   7 #
   8 # This program is distributed in the hope that it will be useful,
   9 # but WITHOUT ANY WARRANTY; without even the implied warranty of
  10 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11 # GNU General Public License for more details.
  12 #
  13 # You should have received a copy of the GNU General Public License
  14 # along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15 #
  16
  17 #
  18 # Test the use of VSX registers, for Powerpc.
  19 #
  20
  21
  22 if {![istarget "powerpc*"] || [skip_vsx_tests]} then {
  23     verbose "Skipping vsx register tests."
  24     return
  25 }
  26
  27 set testfile "vsx-regs"
  28 set binfile ${objdir}/${subdir}/${testfile}
  29 set srcfile ${testfile}.c
  30
  31 set compile_flags {debug nowarnings quiet}
  32 if [get_compiler_info] {
  33     warning "get_compiler failed"
  34     return -1
  35 }
  36
  37 if [test_compiler_info gcc*] {
  38     set compile_flags "$compile_flags additional_flags=-maltivec additional_flags=-mabi=altivec"
  39 } elseif [test_compiler_info xlc*] {
  40     set compile_flags "$compile_flags additional_flags=-qaltivec"
  41 } else {
  42     warning "unknown compiler"
  43     return -1
  44 }
  45
  46 if  { [gdb_compile ${srcdir}/${subdir}/${srcfile} ${binfile} executable $compile_flags] != "" } {
  47      untested vsx-regs.exp
  48      return -1
  49 }
  50
  51 gdb_start
  52 gdb_reinitialize_dir $srcdir/$subdir
  53 gdb_load ${binfile}
  54
  55 # Run to `main' where we begin our tests.
  56
  57 if ![runto_main] then {
  58     gdb_suppress_tests
  59 }
  60
  61 # Data sets used throughout the test
  62
  63 set vector_register1 ".uint128 = 0x3ff4cccccccccccc0000000000000000, v2_double = .0x1, 0x0., v4_float = .0x1, 0xf99999a0, 0x0, 0x0., v4_int32 = .0x3ff4cccc, 0xcccccccc, 0x0, 0x0., v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccc, 0x0, 0x0, 0x0, 0x0., v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0.."
  64
  65 set vector_register1_vr ".uint128 = 0x3ff4cccccccccccc0000000100000001, v4_float = .0x1, 0xf99999a0, 0x0, 0x0., v4_int32 = .0x3ff4cccc, 0xcccccccc, 0x1, 0x1., v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccc, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
  66
  67 set vector_register2 "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v2_double = .0x1, 0x1., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.."
  68
  69 set vector_register2_vr "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.."
  70
  71 set vector_register3 ".uint128 = 0x00000001000000010000000100000001, v2_double = .0x0, 0x0., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
  72
  73 set vector_register3_vr ".uint128 = 0x00000001000000010000000100000001, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
  74
  75 set float_register ".raw 0xdeadbeefdeadbeef."
  76
  77 # First run the F0~F31/VS0~VS31 tests
  78
  79 # 1: Set F0~F31 registers and check if it reflects on VS0~VS31.
  80 for {set i 0} {$i < 32} {incr i 1} {
  81     gdb_test_no_output "set \$f$i = 1\.3"
  82 }
  83
  84 for {set i 0} {$i < 32} {incr i 1} {
  85     gdb_test "info reg vs$i" "vs$i.*$vector_register1" "info reg vs$i (doubleword 0)"
  86 }
  87
  88 # 2: Set VS0~VS31 registers and check if it reflects on F0~F31.
  89 for {set i 0} {$i < 32} {incr i 1} {
  90         for {set j 0} {$j < 4} {incr j 1} {
  91            gdb_test_no_output "set \$vs$i.v4_int32\[$j\] = 0xdeadbeef"
  92         }
  93 }
  94
  95 for {set i 0} {$i < 32} {incr i 1} {
  96     gdb_test "info reg f$i" "f$i.*$float_register" "info reg f$i"
  97 }
  98
  99 for {set i 0} {$i < 32} {incr i 1} {
 100     gdb_test "info reg vs$i" "vs$i.*$vector_register2" "info reg vs$i (doubleword 1)"
 101 }
 102
 103 # Now run the VR0~VR31/VS32~VS63 tests
 104
 105 # 1: Set VR0~VR31 registers and check if it reflects on VS32~VS63.
 106 for {set i 0} {$i < 32} {incr i 1} {
 107         for {set j 0} {$j < 4} {incr j 1} {
 108            gdb_test_no_output "set \$vr$i.v4_int32\[$j\] = 1"
 109         }
 110 }
 111
 112 for {set i 32} {$i < 64} {incr i 1} {
 113     gdb_test "info reg vs$i" "vs$i.*$vector_register3" "info reg vs$i"
 114 }
 115 # 2: Set VS32~VS63 registers and check if it reflects on VR0~VR31.
 116 for {set i 32} {$i < 64} {incr i 1} {
 117         for {set j 0} {$j < 4} {incr j 1} {
 118            gdb_test_no_output "set \$vs$i.v4_int32\[$j\] = 1"
 119         }
 120 }
 121
 122 for {set i 0} {$i < 32} {incr i 1} {
 123     gdb_test "info reg vr$i" "vr$i.*$vector_register3_vr" "info reg vr$i"
 124 }
 125
 126 # Create a core file.  We create the core file before the F32~F63/VR0~VR31 test
 127 # below because then we'll have more interesting register values to verify
 128 # later when loading the core file (i.e., different register values for different
 129 # vector register banks).
 130
 131 set escapedfilename [string_to_regexp ${objdir}/${subdir}/vsx-core.test]
 132
 133 set core_supported 0
 134
 135 gdb_test_multiple "gcore ${objdir}/${subdir}/vsx-core.test" \
 136         "Save a VSX-enabled corefile" \
 137 {
 138   -re "Saved corefile ${escapedfilename}\[\r\n\]+$gdb_prompt $" {
 139     pass "Save a VSX-enabled corefile"
 140     global core_supported
 141     set core_supported 1
 142   }
 143   -re "Can't create a corefile\[\r\n\]+$gdb_prompt $" {
 144     unsupported "Save a VSX-enabled corefile"
 145     global core_supported
 146     set core_supported 0
 147   }
 148 }
 149
 150 # Now run the F32~F63/VR0~VR31 tests.
 151
 152 # 1: Set F32~F63 registers and check if it reflects on VR0~VR31.
 153 for {set i 32} {$i < 64} {incr i 1} {
 154     gdb_test_no_output "set \$f$i = 1\.3"
 155 }
 156
 157 for {set i 0} {$i < 32} {incr i 1} {
 158     gdb_test "info reg vr$i" "vr$i.*$vector_register1_vr" "info reg vr$i (doubleword 0)"
 159 }
 160
 161 # 2: Set VR0~VR31 registers and check if it reflects on F32~F63.
 162 for {set i 0} {$i < 32} {incr i 1} {
 163         for {set j 0} {$j < 4} {incr j 1} {
 164            gdb_test_no_output "set \$vr$i.v4_int32\[$j\] = 0xdeadbeef"
 165         }
 166 }
 167
 168 for {set i 32} {$i < 64} {incr i 1} {
 169     gdb_test "info reg f$i" "f$i.*$float_register" "info reg f$i"
 170 }
 171
 172 for {set i 0} {$i < 32} {incr i 1} {
 173     gdb_test "info reg vr$i" "vr$i.*$vector_register2_vr" "info reg vr$i (doubleword 1)"
 174 }
 175
 176 # Test reading the core file.
 177
 178 if {!$core_supported} {
 179   return -1
 180 }
 181
 182 gdb_exit
 183 gdb_start
 184 gdb_reinitialize_dir $srcdir/$subdir
 185 gdb_load ${binfile}
 186
 187 gdb_test_multiple "core ${objdir}/${subdir}/vsx-core.test" \
 188         "re-load generated corefile" \
 189 {
 190     -re ".* is not a core dump:.*$gdb_prompt $" {
 191         fail "re-load generated corefile (bad file format)"
 192         # No use proceeding from here.
 193         return;
 194     }
 195     -re ".*: No such file or directory.*$gdb_prompt $" {
 196         fail "re-load generated corefile (file not found)"
 197         # No use proceeding from here.
 198         return;
 199     }
 200     -re ".*Couldn't find .* registers in core file.*$gdb_prompt $" {
 201         fail "re-load generated corefile (incomplete note section)"
 202     }
 203     -re "Core was generated by .*$gdb_prompt $" {
 204         pass "re-load generated corefile"
 205     }
 206     -re ".*$gdb_prompt $" {
 207         fail "re-load generated corefile"
 208     }
 209     timeout {
 210         fail "re-load generated corefile (timeout)"
 211     }
 212 }
 213
 214 for {set i 0} {$i < 32} {incr i 1} {
 215     gdb_test "info reg vs$i" "vs$i.*$vector_register2" "Restore vs$i from core file"
 216 }
 217
 218 for {set i 32} {$i < 64} {incr i 1} {
 219     gdb_test "info reg vs$i" "vs$i.*$vector_register3" "Restore vs$i from core file"
 220 }