1 /* Target dependent code for GDB on TI C6x systems.
3 Copyright (C) 2010, 2011.
4 Free Software Foundation, Inc.
5 Contributed by Andrew Jenner <andrew@codesourcery.com>
6 Contributed by Yao Qi <yao@codesourcery.com>
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
25 #include "frame-unwind.h"
26 #include "frame-base.h"
27 #include "trad-frame.h"
28 #include "dwarf2-frame.h"
39 #include "arch-utils.h"
40 #include "floatformat.h"
41 #include "glibc-tdep.h"
44 #include "tramp-frame.h"
45 #include "linux-tdep.h"
48 #include "gdb_assert.h"
50 #include "tic6x-tdep.h"
52 #include "target-descriptions.h"
54 #include "features/tic6x-c64xp.c"
55 #include "features/tic6x-c64x.c"
56 #include "features/tic6x-c62x.c"
58 #define TIC6X_OPCODE_SIZE 4
59 #define TIC6X_FETCH_PACKET_SIZE 32
61 #define INST_S_BIT(INST) ((INST >> 1) & 1)
62 #define INST_X_BIT(INST) ((INST >> 12) & 1)
64 struct tic6x_unwind_cache
66 /* The frame's base, optionally used by the high-level debug info. */
69 /* The previous frame's inner most stack address. Used as this
70 frame ID's stack_addr. */
73 /* The address of the first instruction in this function */
76 /* Which register holds the return address for the frame. */
79 /* The offset of register saved on stack. If register is not saved, the
80 corresponding element is -1. */
81 CORE_ADDR reg_saved
[TIC6X_NUM_CORE_REGS
];
85 /* Name of TI C6x core registers. */
86 static const char *const tic6x_register_names
[] =
88 "A0", "A1", "A2", "A3", /* 0 1 2 3 */
89 "A4", "A5", "A6", "A7", /* 4 5 6 7 */
90 "A8", "A9", "A10", "A11", /* 8 9 10 11 */
91 "A12", "A13", "A14", "A15", /* 12 13 14 15 */
92 "B0", "B1", "B2", "B3", /* 16 17 18 19 */
93 "B4", "B5", "B6", "B7", /* 20 21 22 23 */
94 "B8", "B9", "B10", "B11", /* 24 25 26 27 */
95 "B12", "B13", "B14", "B15", /* 28 29 30 31 */
96 "CSR", "PC", /* 32 33 */
99 /* This array maps the arguments to the register number which passes argument
100 in function call according to C6000 ELF ABI. */
101 static const int arg_regs
[] = { 4, 20, 6, 22, 8, 24, 10, 26, 12, 28 };
103 /* This is the implementation of gdbarch method register_name. */
106 tic6x_register_name (struct gdbarch
*gdbarch
, int regno
)
111 if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
112 return tdesc_register_name (gdbarch
, regno
);
113 else if (regno
>= ARRAY_SIZE (tic6x_register_names
))
116 return tic6x_register_names
[regno
];
119 /* This is the implementation of gdbarch method register_type. */
122 tic6x_register_type (struct gdbarch
*gdbarch
, int regno
)
125 if (regno
== TIC6X_PC_REGNUM
)
126 return builtin_type (gdbarch
)->builtin_func_ptr
;
128 return builtin_type (gdbarch
)->builtin_uint32
;
132 tic6x_setup_default (struct tic6x_unwind_cache
*cache
)
136 for (i
= 0; i
< TIC6X_NUM_CORE_REGS
; i
++)
137 cache
->reg_saved
[i
] = -1;
140 static unsigned long tic6x_fetch_instruction (struct gdbarch
*, CORE_ADDR
);
141 static int tic6x_register_number (int reg
, int side
, int crosspath
);
143 /* Do a full analysis of the prologue at START_PC and update CACHE accordingly.
144 Bail out early if CURRENT_PC is reached. Returns the address of the first
145 instruction after the prologue. */
148 tic6x_analyze_prologue (struct gdbarch
*gdbarch
, const CORE_ADDR start_pc
,
149 const CORE_ADDR current_pc
,
150 struct tic6x_unwind_cache
*cache
,
151 struct frame_info
*this_frame
)
153 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
155 unsigned int src_reg
, base_reg
, dst_reg
;
157 CORE_ADDR pc
= start_pc
;
158 CORE_ADDR return_pc
= start_pc
;
159 int frame_base_offset_to_sp
= 0;
160 /* Counter of non-stw instructions after first insn ` sub sp, xxx, sp'. */
161 int non_stw_insn_counter
= 0;
163 if (start_pc
>= current_pc
)
164 return_pc
= current_pc
;
168 /* The landmarks in prologue is one or two SUB instructions to SP.
169 Instructions on setting up dsbt are in the last part of prologue, if
170 needed. In maxim, prologue can be divided to three parts by two
171 `sub sp, xx, sp' insns. */
173 /* Step 1: Look for the 1st and 2nd insn `sub sp, xx, sp', in which, the
174 2nd one is optional. */
175 while (pc
< current_pc
)
179 unsigned long inst
= tic6x_fetch_instruction (gdbarch
, pc
);
181 if ((inst
& 0x1ffc) == 0x1dc0 || (inst
& 0x1ffc) == 0x1bc0
182 || (inst
& 0x0ffc) == 0x9c0)
184 /* SUBAW/SUBAH/SUB, and src1 is ucst 5. */
185 unsigned int src2
= tic6x_register_number ((inst
>> 18) & 0x1f,
186 INST_S_BIT (inst
), 0);
187 unsigned int dst
= tic6x_register_number ((inst
>> 23) & 0x1f,
188 INST_S_BIT (inst
), 0);
190 if (src2
== TIC6X_SP_REGNUM
&& dst
== TIC6X_SP_REGNUM
)
192 /* Extract const from insn SUBAW/SUBAH/SUB, and translate it to
193 offset. The constant offset is decoded in bit 13-17 in all
194 these three kinds of instructions. */
195 unsigned int ucst5
= (inst
>> 13) & 0x1f;
197 if ((inst
& 0x1ffc) == 0x1dc0) /* SUBAW */
198 frame_base_offset_to_sp
+= ucst5
<< 2;
199 else if ((inst
& 0x1ffc) == 0x1bc0) /* SUBAH */
200 frame_base_offset_to_sp
+= ucst5
<< 1;
201 else if ((inst
& 0x0ffc) == 0x9c0) /* SUB */
202 frame_base_offset_to_sp
+= ucst5
;
204 gdb_assert_not_reached ("unexpected instruction");
209 else if ((inst
& 0x174) == 0x74) /* stw SRC, *+b15(uconst) */
211 /* The y bit determines which file base is read from. */
212 base_reg
= tic6x_register_number ((inst
>> 18) & 0x1f,
215 if (base_reg
== TIC6X_SP_REGNUM
)
217 src_reg
= tic6x_register_number ((inst
>> 23) & 0x1f,
218 INST_S_BIT (inst
), 0);
220 cache
->reg_saved
[src_reg
] = ((inst
>> 13) & 0x1f) << 2;
224 non_stw_insn_counter
= 0;
228 non_stw_insn_counter
++;
229 /* Following instruction sequence may be emitted in prologue:
231 <+0>: subah .D2 b15,28,b15
232 <+4>: or .L2X 0,a4,b0
233 <+8>: || stw .D2T2 b14,*+b15(56)
234 <+12>:[!b0] b .S1 0xe50e4c1c <sleep+220>
235 <+16>:|| stw .D2T1 a10,*+b15(48)
236 <+20>:stw .D2T2 b3,*+b15(52)
237 <+24>:stw .D2T1 a4,*+b15(40)
239 we should look forward for next instruction instead of breaking loop
240 here. So far, we allow almost two sequential non-stw instructions
242 if (non_stw_insn_counter
>= 2)
249 /* Step 2: Skip insn on setting up dsbt if it is. Usually, it looks like,
250 ldw .D2T2 *+b14(0),b14 */
251 inst
= tic6x_fetch_instruction (gdbarch
, pc
);
252 /* The s bit determines which file dst will be loaded into, same effect as
254 dst_reg
= tic6x_register_number ((inst
>> 23) & 0x1f, (inst
>> 1) & 1, 0);
255 /* The y bit (bit 7), instead of s bit, determines which file base be
257 base_reg
= tic6x_register_number ((inst
>> 18) & 0x1f, (inst
>> 7) & 1, 0);
259 if ((inst
& 0x164) == 0x64 /* ldw */
260 && dst_reg
== TIC6X_DP_REGNUM
/* dst is B14 */
261 && base_reg
== TIC6X_DP_REGNUM
) /* baseR is B14 */
268 cache
->base
= get_frame_register_unsigned (this_frame
, TIC6X_SP_REGNUM
);
270 if (cache
->reg_saved
[TIC6X_FP_REGNUM
] != -1)
272 /* If the FP now holds an offset from the CFA then this is a frame
273 which uses the frame pointer. */
275 cache
->cfa
= get_frame_register_unsigned (this_frame
,
280 /* FP doesn't hold an offset from the CFA. If SP still holds an
281 offset from the CFA then we might be in a function which omits
282 the frame pointer. */
284 cache
->cfa
= cache
->base
+ frame_base_offset_to_sp
;
288 /* Adjust all the saved registers such that they contain addresses
289 instead of offsets. */
290 for (i
= 0; i
< TIC6X_NUM_CORE_REGS
; i
++)
291 if (cache
->reg_saved
[i
] != -1)
292 cache
->reg_saved
[i
] = cache
->base
+ cache
->reg_saved
[i
];
297 /* This is the implementation of gdbarch method skip_prologue. */
300 tic6x_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
304 struct tic6x_unwind_cache cache
;
306 /* See if we can determine the end of the prologue via the symbol table.
307 If so, then return either PC, or the PC after the prologue, whichever is
309 if (find_pc_partial_function (start_pc
, NULL
, &func_addr
, NULL
))
311 CORE_ADDR post_prologue_pc
312 = skip_prologue_using_sal (gdbarch
, func_addr
);
313 if (post_prologue_pc
!= 0)
314 return max (start_pc
, post_prologue_pc
);
317 /* Can't determine prologue from the symbol table, need to examine
319 return tic6x_analyze_prologue (gdbarch
, start_pc
, (CORE_ADDR
) -1, &cache
,
323 /* This is the implementation of gdbarch method breakpiont_from_pc. */
326 tic6x_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*bp_addr
,
329 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
333 if (tdep
== NULL
|| tdep
->breakpoint
== NULL
)
335 if (BFD_ENDIAN_BIG
== gdbarch_byte_order_for_code (gdbarch
))
336 return tic6x_bkpt_illegal_opcode_be
;
338 return tic6x_bkpt_illegal_opcode_le
;
341 return tdep
->breakpoint
;
344 /* This is the implementation of gdbarch method print_insn. */
347 tic6x_print_insn (bfd_vma memaddr
, disassemble_info
*info
)
349 return print_insn_tic6x (memaddr
, info
);
353 tic6x_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
354 struct dwarf2_frame_state_reg
*reg
,
355 struct frame_info
*this_frame
)
357 /* Mark the PC as the destination for the return address. */
358 if (regnum
== gdbarch_pc_regnum (gdbarch
))
359 reg
->how
= DWARF2_FRAME_REG_RA
;
361 /* Mark the stack pointer as the call frame address. */
362 else if (regnum
== gdbarch_sp_regnum (gdbarch
))
363 reg
->how
= DWARF2_FRAME_REG_CFA
;
365 /* The above was taken from the default init_reg in dwarf2-frame.c
366 while the below is c6x specific. */
368 /* Callee save registers. The ABI designates A10-A15 and B10-B15 as
370 else if ((regnum
>= 10 && regnum
<= 15) || (regnum
>= 26 && regnum
<= 31))
371 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
373 /* All other registers are caller-save. */
374 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
377 /* This is the implementation of gdbarch method unwind_pc. */
380 tic6x_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
384 frame_unwind_register (next_frame
, TIC6X_PC_REGNUM
, buf
);
385 return extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
388 /* This is the implementation of gdbarch method unwind_sp. */
391 tic6x_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
393 return frame_unwind_register_unsigned (this_frame
, TIC6X_SP_REGNUM
);
397 /* Frame base handling. */
399 struct tic6x_unwind_cache
*
400 tic6x_frame_unwind_cache (struct frame_info
*this_frame
,
401 void **this_prologue_cache
)
403 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
404 CORE_ADDR current_pc
;
405 struct tic6x_unwind_cache
*cache
;
408 if (*this_prologue_cache
)
409 return *this_prologue_cache
;
411 cache
= FRAME_OBSTACK_ZALLOC (struct tic6x_unwind_cache
);
412 (*this_prologue_cache
) = cache
;
414 cache
->return_regnum
= TIC6X_RA_REGNUM
;
416 tic6x_setup_default (cache
);
418 cache
->pc
= get_frame_func (this_frame
);
419 current_pc
= get_frame_pc (this_frame
);
421 /* Prologue analysis does the rest... */
423 tic6x_analyze_prologue (gdbarch
, cache
->pc
, current_pc
, cache
, this_frame
);
429 tic6x_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
430 struct frame_id
*this_id
)
432 struct tic6x_unwind_cache
*cache
=
433 tic6x_frame_unwind_cache (this_frame
, this_cache
);
435 /* This marks the outermost frame. */
436 if (cache
->base
== 0)
439 (*this_id
) = frame_id_build (cache
->cfa
, cache
->pc
);
442 static struct value
*
443 tic6x_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
446 struct tic6x_unwind_cache
*cache
=
447 tic6x_frame_unwind_cache (this_frame
, this_cache
);
449 gdb_assert (regnum
>= 0);
451 /* The PC of the previous frame is stored in the RA register of
452 the current frame. Frob regnum so that we pull the value from
453 the correct place. */
454 if (regnum
== TIC6X_PC_REGNUM
)
455 regnum
= cache
->return_regnum
;
457 if (regnum
== TIC6X_SP_REGNUM
&& cache
->cfa
)
458 return frame_unwind_got_constant (this_frame
, regnum
, cache
->cfa
);
460 /* If we've worked out where a register is stored then load it from
462 if (regnum
< TIC6X_NUM_CORE_REGS
&& cache
->reg_saved
[regnum
] != -1)
463 return frame_unwind_got_memory (this_frame
, regnum
,
464 cache
->reg_saved
[regnum
]);
466 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
470 tic6x_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
472 struct tic6x_unwind_cache
*info
473 = tic6x_frame_unwind_cache (this_frame
, this_cache
);
477 static const struct frame_unwind tic6x_frame_unwind
=
480 default_frame_unwind_stop_reason
,
482 tic6x_frame_prev_register
,
484 default_frame_sniffer
487 static const struct frame_base tic6x_frame_base
=
490 tic6x_frame_base_address
,
491 tic6x_frame_base_address
,
492 tic6x_frame_base_address
496 static struct tic6x_unwind_cache
*
497 tic6x_make_stub_cache (struct frame_info
*this_frame
)
499 struct tic6x_unwind_cache
*cache
;
501 cache
= FRAME_OBSTACK_ZALLOC (struct tic6x_unwind_cache
);
503 cache
->return_regnum
= TIC6X_RA_REGNUM
;
505 tic6x_setup_default (cache
);
507 cache
->cfa
= get_frame_register_unsigned (this_frame
, TIC6X_SP_REGNUM
);
513 tic6x_stub_this_id (struct frame_info
*this_frame
, void **this_cache
,
514 struct frame_id
*this_id
)
516 struct tic6x_unwind_cache
*cache
;
518 if (*this_cache
== NULL
)
519 *this_cache
= tic6x_make_stub_cache (this_frame
);
522 *this_id
= frame_id_build (cache
->cfa
, get_frame_pc (this_frame
));
526 tic6x_stub_unwind_sniffer (const struct frame_unwind
*self
,
527 struct frame_info
*this_frame
,
528 void **this_prologue_cache
)
530 CORE_ADDR addr_in_block
;
532 addr_in_block
= get_frame_address_in_block (this_frame
);
533 if (in_plt_section (addr_in_block
, NULL
))
539 static const struct frame_unwind tic6x_stub_unwind
=
542 default_frame_unwind_stop_reason
,
544 tic6x_frame_prev_register
,
546 tic6x_stub_unwind_sniffer
549 /* Return the instruction on address PC. */
552 tic6x_fetch_instruction (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
554 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
555 return read_memory_unsigned_integer (pc
, TIC6X_OPCODE_SIZE
, byte_order
);
558 /* Compute the condition of INST if it is a conditional instruction. Always
559 return 1 if INST is not a conditional instruction. */
562 tic6x_condition_true (struct frame_info
*frame
, unsigned long inst
)
566 static const int register_numbers
[8] = { -1, 16, 17, 18, 1, 2, 0, -1 };
568 register_number
= register_numbers
[(inst
>> 29) & 7];
569 if (register_number
== -1)
572 register_value
= get_frame_register_signed (frame
, register_number
);
573 if ((inst
& 0x10000000) != 0)
574 return register_value
== 0;
575 return register_value
!= 0;
578 /* Get the register number by decoding raw bits REG, SIDE, and CROSSPATH in
582 tic6x_register_number (int reg
, int side
, int crosspath
)
584 int r
= (reg
& 15) | ((crosspath
^ side
) << 4);
585 if ((reg
& 16) != 0) /* A16 - A31, B16 - B31 */
591 tic6x_extract_signed_field (int value
, int low_bit
, int bits
)
593 int mask
= (1 << bits
) - 1;
594 int r
= (value
>> low_bit
) & mask
;
595 if ((r
& (1 << (bits
- 1))) != 0)
600 /* Determine where to set a single step breakpoint. */
603 tic6x_get_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
605 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
613 inst
= tic6x_fetch_instruction (gdbarch
, pc
);
617 if (inst
== TIC6X_INST_SWE
)
619 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
621 if (tdep
->syscall_next_pc
!= NULL
)
622 return tdep
->syscall_next_pc (frame
);
625 if (tic6x_condition_true (frame
, inst
))
627 if ((inst
& 0x0000007c) == 0x00000010)
629 /* B with displacement */
630 pc
&= ~(TIC6X_FETCH_PACKET_SIZE
- 1);
631 pc
+= tic6x_extract_signed_field (inst
, 7, 21) << 2;
634 if ((inst
& 0x0f83effc) == 0x00000360)
636 /* B with register */
638 register_number
= tic6x_register_number ((inst
>> 18) & 0x1f,
641 pc
= get_frame_register_unsigned (frame
, register_number
);
644 if ((inst
& 0x00001ffc) == 0x00001020)
647 register_number
= tic6x_register_number ((inst
>> 23) & 0x1f,
648 INST_S_BIT (inst
), 0);
649 if (get_frame_register_signed (frame
, register_number
) >= 0)
651 pc
&= ~(TIC6X_FETCH_PACKET_SIZE
- 1);
652 pc
+= tic6x_extract_signed_field (inst
, 7, 10) << 2;
656 if ((inst
& 0x00001ffc) == 0x00000120)
658 /* BNOP with displacement */
659 pc
&= ~(TIC6X_FETCH_PACKET_SIZE
- 1);
660 pc
+= tic6x_extract_signed_field (inst
, 16, 12) << 2;
663 if ((inst
& 0x0f830ffe) == 0x00800362)
665 /* BNOP with register */
666 register_number
= tic6x_register_number ((inst
>> 18) & 0x1f,
667 1, INST_X_BIT (inst
));
668 pc
= get_frame_register_unsigned (frame
, register_number
);
671 if ((inst
& 0x00001ffc) == 0x00000020)
674 register_number
= tic6x_register_number ((inst
>> 23) & 0x1f,
675 INST_S_BIT (inst
), 0);
676 if (get_frame_register_signed (frame
, register_number
) >= 0)
678 pc
&= ~(TIC6X_FETCH_PACKET_SIZE
- 1);
679 pc
+= tic6x_extract_signed_field (inst
, 13, 10) << 2;
683 if ((inst
& 0xf000007c) == 0x10000010)
686 pc
&= ~(TIC6X_FETCH_PACKET_SIZE
- 1);
687 pc
+= tic6x_extract_signed_field (inst
, 7, 21) << 2;
691 pc
+= TIC6X_OPCODE_SIZE
;
697 /* This is the implementation of gdbarch method software_single_step. */
700 tic6x_software_single_step (struct frame_info
*frame
)
702 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
703 struct address_space
*aspace
= get_frame_address_space (frame
);
704 CORE_ADDR next_pc
= tic6x_get_next_pc (frame
, get_frame_pc (frame
));
706 insert_single_step_breakpoint (gdbarch
, aspace
, next_pc
);
711 /* This is the implementation of gdbarch method frame_align. */
714 tic6x_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
716 return align_down (addr
, 8);
719 /* This is the implementation of gdbarch method register_to_value. */
722 tic6x_register_to_value (struct frame_info
*frame
, int regnum
,
723 struct type
*type
, gdb_byte
* to
,
724 int *optimizedp
, int *unavailablep
)
726 get_frame_register (frame
, regnum
, (char *) to
);
727 *optimizedp
= *unavailablep
= 0;
731 /* This is the implementation of gdbarch method value_to_register. */
734 tic6x_value_to_register (struct frame_info
*frame
, int regnum
,
735 struct type
*type
, const gdb_byte
*from
)
737 put_frame_register (frame
, regnum
, from
);
740 /* Given a return value in REGCACHE with a type VALTYPE, extract and copy its
741 value into VALBUF. */
744 tic6x_extract_return_value (struct type
*valtype
, struct regcache
*regcache
,
745 enum bfd_endian byte_order
, gdb_byte
*valbuf
)
747 int len
= TYPE_LENGTH (valtype
);
749 /* pointer types are returned in register A4,
750 up to 32-bit types in A4
751 up to 64-bit types in A5:A4 */
755 - one-byte structure or union occupies the LSB of single even register.
756 - for two-byte structure or union, the first byte occupies byte 1 of
757 register and the second byte occupies byte 0.
758 so, we read the contents in VAL from the LSBs of register. */
759 if (len
< 3 && byte_order
== BFD_ENDIAN_BIG
)
760 regcache_cooked_read_part (regcache
, TIC6X_A4_REGNUM
, 4 - len
, len
,
763 regcache_cooked_read (regcache
, TIC6X_A4_REGNUM
, valbuf
);
767 /* For a 5-8 byte structure or union in big-endian, the first byte
768 occupies byte 3 (the MSB) of the upper (odd) register and the
769 remaining bytes fill the decreasingly significant bytes. 5-7
770 byte structures or unions have padding in the LSBs of the
771 lower (even) register. */
772 if (byte_order
== BFD_ENDIAN_BIG
)
774 regcache_cooked_read (regcache
, TIC6X_A4_REGNUM
, valbuf
+ 4);
775 regcache_cooked_read (regcache
, TIC6X_A5_REGNUM
, valbuf
);
779 regcache_cooked_read (regcache
, TIC6X_A4_REGNUM
, valbuf
);
780 regcache_cooked_read (regcache
, TIC6X_A5_REGNUM
, valbuf
+ 4);
785 /* Write into appropriate registers a function return value
786 of type TYPE, given in virtual format. */
789 tic6x_store_return_value (struct type
*valtype
, struct regcache
*regcache
,
790 enum bfd_endian byte_order
, const gdb_byte
*valbuf
)
792 int len
= TYPE_LENGTH (valtype
);
794 /* return values of up to 8 bytes are returned in A5:A4 */
798 if (len
< 3 && byte_order
== BFD_ENDIAN_BIG
)
799 regcache_cooked_write_part (regcache
, TIC6X_A4_REGNUM
, 4 - len
, len
,
802 regcache_cooked_write (regcache
, TIC6X_A4_REGNUM
, valbuf
);
806 if (byte_order
== BFD_ENDIAN_BIG
)
808 regcache_cooked_write (regcache
, TIC6X_A4_REGNUM
, valbuf
+ 4);
809 regcache_cooked_write (regcache
, TIC6X_A5_REGNUM
, valbuf
);
813 regcache_cooked_write (regcache
, TIC6X_A4_REGNUM
, valbuf
);
814 regcache_cooked_write (regcache
, TIC6X_A5_REGNUM
, valbuf
+ 4);
819 /* This is the implementation of gdbarch method return_value. */
821 static enum return_value_convention
822 tic6x_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
823 struct type
*type
, struct regcache
*regcache
,
824 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
826 if (TYPE_LENGTH (type
) > 8)
827 return RETURN_VALUE_STRUCT_CONVENTION
;
830 tic6x_extract_return_value (type
, regcache
,
831 gdbarch_byte_order (gdbarch
), readbuf
);
833 tic6x_store_return_value (type
, regcache
,
834 gdbarch_byte_order (gdbarch
), writebuf
);
836 return RETURN_VALUE_REGISTER_CONVENTION
;
839 /* This is the implementation of gdbarch method dummy_id. */
841 static struct frame_id
842 tic6x_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
844 return frame_id_build
845 (get_frame_register_unsigned (this_frame
, TIC6X_SP_REGNUM
),
846 get_frame_pc (this_frame
));
849 /* Get the alignment requirement of TYPE. */
852 tic6x_arg_type_alignment (struct type
*type
)
854 int len
= TYPE_LENGTH (check_typedef (type
));
855 enum type_code typecode
= TYPE_CODE (check_typedef (type
));
857 if (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
859 /* The stack alignment of a structure (and union) passed by value is the
860 smallest power of two greater than or equal to its size.
861 This cannot exceed 8 bytes, which is the largest allowable size for
862 a structure passed by value. */
871 gdb_assert_not_reached ("unexpected length of data");
879 if (typecode
== TYPE_CODE_COMPLEX
)
886 if (typecode
== TYPE_CODE_COMPLEX
)
892 internal_error (__FILE__
, __LINE__
, _("unexpected length %d of type"),
897 /* This is the implementation of gdbarch method push_dummy_call. */
900 tic6x_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
901 struct regcache
*regcache
, CORE_ADDR bp_addr
,
902 int nargs
, struct value
**args
, CORE_ADDR sp
,
903 int struct_return
, CORE_ADDR struct_addr
)
908 int stack_offset
= 4;
909 int references_offset
= 4;
910 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
911 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
912 struct type
*func_type
= value_type (function
);
913 /* The first arg passed on stack. Mostly the first 10 args are passed by
915 int first_arg_on_stack
= 10;
916 /* If this inf-call is a cpp method call, and return value is passed by
917 reference, this flag is set to 1, otherwise set to 0. We need this flag
918 because computation of the return location in
919 infcall.c:call_function_by_hand is wrong for C6000 ELF ABI. In
920 call_function_by_hand, the language is considered first, and then
921 target ABI is considered. If language_pass_by_reference returns true,
922 the return location is passed as the first parameter to the function,
923 which is conflict with C6000 ELF ABI. If this flag is true, we should
924 adjust args and return locations accordingly to comply with C6000 ELF
926 int cplus_return_struct_by_reference
= 0;
928 if (current_language
->la_language
== language_cplus
)
930 struct type
*values_type
;
932 find_function_addr (function
, &values_type
);
936 CHECK_TYPEDEF (values_type
);
937 if (language_pass_by_reference (values_type
))
938 cplus_return_struct_by_reference
= 1;
942 /* Set the return address register to point to the entry point of
943 the program, where a breakpoint lies in wait. */
944 regcache_cooked_write_unsigned (regcache
, TIC6X_RA_REGNUM
, bp_addr
);
946 /* The caller must pass an argument in A3 containing a destination address
947 for the returned value. The callee returns the object by copying it to
948 the address in A3. */
950 regcache_cooked_write_unsigned (regcache
, 3, struct_addr
);
951 else if (cplus_return_struct_by_reference
)
952 /* When cplus_return_struct_by_reference is 1, means local variable
953 lang_struct_return in call_function_by_hand is 1, so struct is
954 returned by reference, even STRUCT_RETURN is 0. Note that STRUCT_ADDR
955 is still valid in this case. */
956 regcache_cooked_write_unsigned (regcache
, 3, struct_addr
);
958 /* Determine the type of this function. */
959 func_type
= check_typedef (func_type
);
960 if (TYPE_CODE (func_type
) == TYPE_CODE_PTR
)
961 func_type
= check_typedef (TYPE_TARGET_TYPE (func_type
));
963 gdb_assert (TYPE_CODE (func_type
) == TYPE_CODE_FUNC
964 || TYPE_CODE (func_type
) == TYPE_CODE_METHOD
);
966 /* For a variadic C function, the last explicitly declared argument and all
967 remaining arguments are passed on the stack. */
968 if (TYPE_VARARGS (func_type
))
969 first_arg_on_stack
= TYPE_NFIELDS (func_type
) - 1;
971 /* Now make space on the stack for the args. If
972 cplus_return_struct_by_reference is 1, means GDB pass an extra parameter
973 in ARGS, which is useless here, skip it. */
974 for (argnum
= cplus_return_struct_by_reference
; argnum
< nargs
; argnum
++)
976 int len
= align_up (TYPE_LENGTH (value_type (args
[argnum
])), 4);
977 if (argnum
>= 10 - argreg
)
978 references_offset
+= len
;
982 /* SP should be 8-byte aligned, see C6000 ABI section 4.4.1
984 sp
= align_down (sp
, 8);
987 /* Now load as many as possible of the first arguments into
988 registers, and push the rest onto the stack. Loop through args
989 from first to last. */
990 for (argnum
= cplus_return_struct_by_reference
; argnum
< nargs
; argnum
++)
993 struct value
*arg
= args
[argnum
];
994 struct type
*arg_type
= check_typedef (value_type (arg
));
995 int len
= TYPE_LENGTH (arg_type
);
996 enum type_code typecode
= TYPE_CODE (arg_type
);
998 val
= value_contents (arg
);
1000 /* Copy the argument to general registers or the stack in
1001 register-sized pieces. */
1002 if (argreg
< first_arg_on_stack
)
1006 if (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
1009 - one-byte structure or union occupies the LSB of single
1011 - for two-byte structure or union, the first byte
1012 occupies byte 1 of register and the second byte occupies
1014 so, we write the contents in VAL to the lsp of
1016 if (len
< 3 && byte_order
== BFD_ENDIAN_BIG
)
1017 regcache_cooked_write_part (regcache
, arg_regs
[argreg
],
1020 regcache_cooked_write (regcache
, arg_regs
[argreg
], val
);
1024 /* The argument is being passed by value in a single
1026 CORE_ADDR regval
= extract_unsigned_integer (val
, len
,
1029 regcache_cooked_write_unsigned (regcache
, arg_regs
[argreg
],
1037 if (typecode
== TYPE_CODE_STRUCT
1038 || typecode
== TYPE_CODE_UNION
)
1040 /* For a 5-8 byte structure or union in big-endian, the
1041 first byte occupies byte 3 (the MSB) of the upper (odd)
1042 register and the remaining bytes fill the decreasingly
1043 significant bytes. 5-7 byte structures or unions have
1044 padding in the LSBs of the lower (even) register. */
1045 if (byte_order
== BFD_ENDIAN_BIG
)
1047 regcache_cooked_write (regcache
,
1048 arg_regs
[argreg
] + 1, val
);
1049 regcache_cooked_write_part (regcache
,
1050 arg_regs
[argreg
], 0,
1055 regcache_cooked_write (regcache
, arg_regs
[argreg
],
1057 regcache_cooked_write_part (regcache
,
1058 arg_regs
[argreg
] + 1, 0,
1064 /* The argument is being passed by value in a pair of
1066 ULONGEST regval
= extract_unsigned_integer (val
, len
,
1069 regcache_cooked_write_unsigned (regcache
,
1072 regcache_cooked_write_unsigned (regcache
,
1073 arg_regs
[argreg
] + 1,
1079 /* The argument is being passed by reference in a single
1083 /* It is not necessary to adjust REFERENCES_OFFSET to
1084 8-byte aligned in some cases, in which 4-byte alignment
1085 is sufficient. For simplicity, we adjust
1086 REFERENCES_OFFSET to 8-byte aligned. */
1087 references_offset
= align_up (references_offset
, 8);
1089 addr
= sp
+ references_offset
;
1090 write_memory (addr
, val
, len
);
1091 references_offset
+= align_up (len
, 4);
1092 regcache_cooked_write_unsigned (regcache
, arg_regs
[argreg
],
1100 /* The argument is being passed on the stack. */
1103 /* There are six different cases of alignment, and these rules can
1104 be found in tic6x_arg_type_alignment:
1106 1) 4-byte aligned if size is less than or equal to 4 byte, such
1107 as short, int, struct, union etc.
1108 2) 8-byte aligned if size is less than or equal to 8-byte, such
1109 as double, long long,
1110 3) 4-byte aligned if it is of type _Complex float, even its size
1112 4) 8-byte aligned if it is of type _Complex double or _Complex
1113 long double, even its size is 16-byte. Because, the address of
1114 variable is passed as reference.
1115 5) struct and union larger than 8-byte are passed by reference, so
1116 it is 4-byte aligned.
1117 6) struct and union of size between 4 byte and 8 byte varies.
1118 alignment of struct variable is the alignment of its first field,
1119 while alignment of union variable is the max of all its fields'
1123 ; /* Default is 4-byte aligned. Nothing to be done. */
1125 stack_offset
= align_up (stack_offset
,
1126 tic6x_arg_type_alignment (arg_type
));
1129 /* _Complex double or _Complex long double */
1130 if (typecode
== TYPE_CODE_COMPLEX
)
1132 /* The argument is being passed by reference on stack. */
1134 references_offset
= align_up (references_offset
, 8);
1136 addr
= sp
+ references_offset
;
1137 /* Store variable on stack. */
1138 write_memory (addr
, val
, len
);
1140 references_offset
+= align_up (len
, 4);
1142 /* Pass the address of variable on stack as reference. */
1143 store_unsigned_integer ((gdb_byte
*) val
, 4, byte_order
,
1149 internal_error (__FILE__
, __LINE__
,
1150 _("unexpected type %d of arg %d"),
1154 internal_error (__FILE__
, __LINE__
,
1155 _("unexpected length %d of arg %d"), len
, argnum
);
1157 addr
= sp
+ stack_offset
;
1158 write_memory (addr
, val
, len
);
1159 stack_offset
+= align_up (len
, 4);
1163 regcache_cooked_write_signed (regcache
, TIC6X_SP_REGNUM
, sp
);
1165 /* Return adjusted stack pointer. */
1169 /* This is the implementation of gdbarch method in_function_epilogue_p. */
1172 tic6x_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1174 unsigned long inst
= tic6x_fetch_instruction (gdbarch
, pc
);
1175 /* Normally, the epilogue is composed by instruction `b .S2 b3'. */
1176 if ((inst
& 0x0f83effc) == 0x360)
1178 unsigned int src2
= tic6x_register_number ((inst
>> 18) & 0x1f,
1181 if (src2
== TIC6X_RA_REGNUM
)
1188 /* This is the implementation of gdbarch method get_longjmp_target. */
1191 tic6x_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
1193 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1194 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1198 /* JMP_BUF is passed by reference in A4. */
1199 jb_addr
= get_frame_register_unsigned (frame
, 4);
1201 /* JMP_BUF contains 13 elements of type int, and return address is stored
1202 in the last slot. */
1203 if (target_read_memory (jb_addr
+ 12 * 4, buf
, 4))
1206 *pc
= extract_unsigned_integer (buf
, 4, byte_order
);
1211 static struct gdbarch
*
1212 tic6x_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
1214 struct gdbarch
*gdbarch
;
1215 struct gdbarch_tdep
*tdep
;
1216 struct tdesc_arch_data
*tdesc_data
= NULL
;
1217 const struct target_desc
*tdesc
= info
.target_desc
;
1220 /* Check any target description for validity. */
1221 if (tdesc_has_registers (tdesc
))
1223 const struct tdesc_feature
*feature
;
1226 feature
= tdesc_find_feature (tdesc
, "org.gnu.gdb.tic6x.core");
1228 if (feature
== NULL
)
1231 tdesc_data
= tdesc_data_alloc ();
1234 for (i
= 0; i
< 32; i
++) /* A0 - A15, B0 - B15 */
1235 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
1236 tic6x_register_names
[i
]);
1239 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
++,
1240 tic6x_register_names
[TIC6X_CSR_REGNUM
]);
1241 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
++,
1242 tic6x_register_names
[TIC6X_PC_REGNUM
]);
1246 tdesc_data_cleanup (tdesc_data
);
1250 feature
= tdesc_find_feature (tdesc
, "org.gnu.gdb.tic6x.gp");
1254 static const char *const gp
[] =
1256 "A16", "A17", "A18", "A19", "A20", "A21", "A22", "A23",
1257 "A24", "A25", "A26", "A27", "A28", "A29", "A30", "A31",
1258 "B16", "B17", "B18", "B19", "B20", "B21", "B22", "B23",
1259 "B24", "B25", "B26", "B27", "B28", "B29", "B30", "B31",
1264 for (j
= 0; j
< 32; j
++) /* A16 - A31, B16 - B31 */
1265 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
++,
1270 tdesc_data_cleanup (tdesc_data
);
1275 feature
= tdesc_find_feature (tdesc
, "org.gnu.gdb.tic6x.c6xp");
1278 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
++, "TSR");
1279 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
++, "ILC");
1280 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
++, "RILC");
1284 tdesc_data_cleanup (tdesc_data
);
1291 /* Find a candidate among extant architectures. */
1292 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
1294 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
1296 tdep
= gdbarch_tdep (arches
->gdbarch
);
1298 if (has_gp
!= tdep
->has_gp
)
1301 if (tdep
&& tdep
->breakpoint
)
1302 return arches
->gdbarch
;
1305 tdep
= xcalloc (1, sizeof (struct gdbarch_tdep
));
1307 tdep
->has_gp
= has_gp
;
1308 gdbarch
= gdbarch_alloc (&info
, tdep
);
1310 /* Data type sizes. */
1311 set_gdbarch_ptr_bit (gdbarch
, 32);
1312 set_gdbarch_addr_bit (gdbarch
, 32);
1313 set_gdbarch_short_bit (gdbarch
, 16);
1314 set_gdbarch_int_bit (gdbarch
, 32);
1315 set_gdbarch_long_bit (gdbarch
, 32);
1316 set_gdbarch_long_long_bit (gdbarch
, 64);
1317 set_gdbarch_float_bit (gdbarch
, 32);
1318 set_gdbarch_double_bit (gdbarch
, 64);
1320 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
1321 set_gdbarch_double_format (gdbarch
, floatformats_ieee_double
);
1323 /* The register set. */
1324 set_gdbarch_num_regs (gdbarch
, TIC6X_NUM_REGS
);
1325 set_gdbarch_sp_regnum (gdbarch
, TIC6X_SP_REGNUM
);
1326 set_gdbarch_pc_regnum (gdbarch
, TIC6X_PC_REGNUM
);
1328 set_gdbarch_register_name (gdbarch
, tic6x_register_name
);
1329 set_gdbarch_register_type (gdbarch
, tic6x_register_type
);
1331 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
1333 set_gdbarch_skip_prologue (gdbarch
, tic6x_skip_prologue
);
1334 set_gdbarch_breakpoint_from_pc (gdbarch
, tic6x_breakpoint_from_pc
);
1336 set_gdbarch_unwind_pc (gdbarch
, tic6x_unwind_pc
);
1337 set_gdbarch_unwind_sp (gdbarch
, tic6x_unwind_sp
);
1340 dwarf2_append_unwinders (gdbarch
);
1342 frame_unwind_append_unwinder (gdbarch
, &tic6x_stub_unwind
);
1343 frame_unwind_append_unwinder (gdbarch
, &tic6x_frame_unwind
);
1345 dwarf2_frame_set_init_reg (gdbarch
, tic6x_dwarf2_frame_init_reg
);
1347 /* Single stepping. */
1348 set_gdbarch_software_single_step (gdbarch
, tic6x_software_single_step
);
1350 set_gdbarch_print_insn (gdbarch
, tic6x_print_insn
);
1352 /* Call dummy code. */
1353 set_gdbarch_frame_align (gdbarch
, tic6x_frame_align
);
1355 set_gdbarch_register_to_value (gdbarch
, tic6x_register_to_value
);
1356 set_gdbarch_value_to_register (gdbarch
, tic6x_value_to_register
);
1358 set_gdbarch_return_value (gdbarch
, tic6x_return_value
);
1360 set_gdbarch_dummy_id (gdbarch
, tic6x_dummy_id
);
1362 /* Enable inferior call support. */
1363 set_gdbarch_push_dummy_call (gdbarch
, tic6x_push_dummy_call
);
1365 set_gdbarch_get_longjmp_target (gdbarch
, tic6x_get_longjmp_target
);
1367 set_gdbarch_in_function_epilogue_p (gdbarch
, tic6x_in_function_epilogue_p
);
1369 /* Hook in ABI-specific overrides, if they have been registered. */
1370 gdbarch_init_osabi (info
, gdbarch
);
1373 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
1379 _initialize_tic6x_tdep (void)
1381 register_gdbarch_init (bfd_arch_tic6x
, tic6x_gdbarch_init
);
1383 initialize_tdesc_tic6x_c64xp ();
1384 initialize_tdesc_tic6x_c64x ();
1385 initialize_tdesc_tic6x_c62x ();