1 /* Target-dependent code for the NEC V850 for GDB, the GNU debugger.
3 Copyright (C) 1996-2021 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include "frame-base.h"
23 #include "trad-frame.h"
24 #include "frame-unwind.h"
25 #include "dwarf2/frame.h"
29 #include "arch-utils.h"
38 /* General purpose registers. */
42 E_R3_REGNUM
, E_SP_REGNUM
= E_R3_REGNUM
,
45 E_R6_REGNUM
, E_ARG0_REGNUM
= E_R6_REGNUM
,
48 E_R9_REGNUM
, E_ARGLAST_REGNUM
= E_R9_REGNUM
,
49 E_R10_REGNUM
, E_V0_REGNUM
= E_R10_REGNUM
,
50 E_R11_REGNUM
, E_V1_REGNUM
= E_R11_REGNUM
,
68 E_R29_REGNUM
, E_FP_REGNUM
= E_R29_REGNUM
,
69 E_R30_REGNUM
, E_EP_REGNUM
= E_R30_REGNUM
,
70 E_R31_REGNUM
, E_LP_REGNUM
= E_R31_REGNUM
,
72 /* System registers - main banks. */
73 E_R32_REGNUM
, E_SR0_REGNUM
= E_R32_REGNUM
,
78 E_R37_REGNUM
, E_PS_REGNUM
= E_R37_REGNUM
,
93 E_R52_REGNUM
, E_CTBP_REGNUM
= E_R52_REGNUM
,
107 E_R64_REGNUM
, E_PC_REGNUM
= E_R64_REGNUM
,
110 E_NUM_OF_V850E_REGS
= E_NUM_OF_V850_REGS
,
112 /* System registers - MPV (PROT00) bank. */
113 E_R66_REGNUM
= E_NUM_OF_V850_REGS
,
142 /* System registers - MPU (PROT01) bank. */
172 /* FPU system registers. */
179 E_R128_REGNUM
, E_FPSR_REGNUM
= E_R128_REGNUM
,
180 E_R129_REGNUM
, E_FPEPC_REGNUM
= E_R129_REGNUM
,
181 E_R130_REGNUM
, E_FPST_REGNUM
= E_R130_REGNUM
,
182 E_R131_REGNUM
, E_FPCC_REGNUM
= E_R131_REGNUM
,
183 E_R132_REGNUM
, E_FPCFG_REGNUM
= E_R132_REGNUM
,
201 E_NUM_OF_V850E2_REGS
,
203 /* v850e3v5 system registers, selID 1 thru 7. */
204 E_SELID_1_R0_REGNUM
= E_NUM_OF_V850E2_REGS
,
205 E_SELID_1_R31_REGNUM
= E_SELID_1_R0_REGNUM
+ 31,
208 E_SELID_2_R31_REGNUM
= E_SELID_2_R0_REGNUM
+ 31,
211 E_SELID_3_R31_REGNUM
= E_SELID_3_R0_REGNUM
+ 31,
214 E_SELID_4_R31_REGNUM
= E_SELID_4_R0_REGNUM
+ 31,
217 E_SELID_5_R31_REGNUM
= E_SELID_5_R0_REGNUM
+ 31,
220 E_SELID_6_R31_REGNUM
= E_SELID_6_R0_REGNUM
+ 31,
223 E_SELID_7_R31_REGNUM
= E_SELID_7_R0_REGNUM
+ 31,
225 /* v850e3v5 vector registers. */
227 E_VR31_REGNUM
= E_VR0_REGNUM
+ 31,
229 E_NUM_OF_V850E3V5_REGS
,
231 /* Total number of possible registers. */
232 E_NUM_REGS
= E_NUM_OF_V850E3V5_REGS
240 /* Size of return datatype which fits into all return registers. */
243 E_MAX_RETTYPE_SIZE_IN_REGS
= 2 * v850_reg_size
246 /* When v850 support was added to GCC in the late nineties, the intention
247 was to follow the Green Hills ABI for v850. In fact, the authors of
248 that support at the time thought that they were doing so. As far as
249 I can tell, the calling conventions are correct, but the return value
250 conventions were not quite right. Over time, the return value code
251 in this file was modified to mostly reflect what GCC was actually
252 doing instead of to actually follow the Green Hills ABI as it did
253 when the code was first written.
255 Renesas defined the RH850 ABI which they use in their compiler. It
256 is similar to the original Green Hills ABI with some minor
265 /* Architecture specific data. */
267 struct v850_gdbarch_tdep
: gdbarch_tdep
269 /* Fields from the ELF header. */
273 /* Which ABI are we using? */
274 enum v850_abi abi
{};
275 int eight_byte_align
= 0;
278 struct v850_frame_cache
285 /* Flag showing that a frame has been created in the prologue code. */
288 /* Saved registers. */
289 trad_frame_saved_reg
*saved_regs
;
292 /* Info gleaned from scanning a function's prologue. */
293 struct pifsr
/* Info about one saved register. */
295 int offset
; /* Offset from sp or fp. */
296 int cur_frameoffset
; /* Current frameoffset. */
297 int reg
; /* Saved register number. */
301 v850_register_name (struct gdbarch
*gdbarch
, int regnum
)
303 static const char *v850_reg_names
[] =
304 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
305 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
306 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
307 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
308 "eipc", "eipsw", "fepc", "fepsw", "ecr", "psw", "sr6", "sr7",
309 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15",
310 "sr16", "sr17", "sr18", "sr19", "sr20", "sr21", "sr22", "sr23",
311 "sr24", "sr25", "sr26", "sr27", "sr28", "sr29", "sr30", "sr31",
314 if (regnum
< 0 || regnum
> E_NUM_OF_V850_REGS
)
316 return v850_reg_names
[regnum
];
320 v850e_register_name (struct gdbarch
*gdbarch
, int regnum
)
322 static const char *v850e_reg_names
[] =
324 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
325 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
326 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
327 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
328 "eipc", "eipsw", "fepc", "fepsw", "ecr", "psw", "sr6", "sr7",
329 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15",
330 "ctpc", "ctpsw", "dbpc", "dbpsw", "ctbp", "sr21", "sr22", "sr23",
331 "sr24", "sr25", "sr26", "sr27", "sr28", "sr29", "sr30", "sr31",
334 if (regnum
< 0 || regnum
> E_NUM_OF_V850E_REGS
)
336 return v850e_reg_names
[regnum
];
340 v850e2_register_name (struct gdbarch
*gdbarch
, int regnum
)
342 static const char *v850e2_reg_names
[] =
344 /* General purpose registers. */
345 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
346 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
347 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
348 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
350 /* System registers - main banks. */
351 "eipc", "eipsw", "fepc", "fepsw", "ecr", "psw", "pid", "cfg",
352 "", "", "", "sccfg", "scbp", "eiic", "feic", "dbic",
353 "ctpc", "ctpsw", "dbpc", "dbpsw", "ctbp", "dir", "", "",
354 "", "", "", "", "eiwr", "fewr", "dbwr", "bsel",
360 /* System registers - MPV (PROT00) bank. */
361 "vsecr", "vstid", "vsadr", "", "vmecr", "vmtid", "vmadr", "",
362 "vpecr", "vptid", "vpadr", "", "", "", "", "",
363 "", "", "", "", "", "", "", "",
364 "mca", "mcs", "mcc", "mcr",
366 /* System registers - MPU (PROT01) bank. */
367 "mpm", "mpc", "tid", "", "", "", "ipa0l", "ipa0u",
368 "ipa1l", "ipa1u", "ipa2l", "ipa2u", "ipa3l", "ipa3u", "ipa4l", "ipa4u",
369 "dpa0l", "dpa0u", "dpa1l", "dpa1u", "dpa2l", "dpa2u", "dpa3l", "dpa3u",
370 "dpa4l", "dpa4u", "dpa5l", "dpa5u",
372 /* FPU system registers. */
373 "", "", "", "", "", "", "fpsr", "fpepc",
374 "fpst", "fpcc", "fpcfg", "fpec", "", "", "", "",
375 "", "", "", "", "", "", "", "",
378 if (regnum
< 0 || regnum
>= E_NUM_OF_V850E2_REGS
)
380 return v850e2_reg_names
[regnum
];
383 /* Implement the "register_name" gdbarch method for v850e3v5. */
386 v850e3v5_register_name (struct gdbarch
*gdbarch
, int regnum
)
388 static const char *v850e3v5_reg_names
[] =
390 /* General purpose registers. */
391 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
392 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
393 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
394 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
396 /* selID 0, not including FPU registers. The FPU registers are
398 "eipc", "eipsw", "fepc", "fepsw",
399 "", "psw", "" /* fpsr */, "" /* fpepc */,
400 "" /* fpst */, "" /* fpcc */, "" /* fpcfg */, "" /* fpec */,
401 "sesr", "eiic", "feic", "",
402 "ctpc", "ctpsw", "", "", "ctbp", "", "", "",
403 "", "", "", "", "eiwr", "fewr", "", "bsel",
409 /* v850e2 MPV bank. */
410 "", "", "", "", "", "", "", "",
411 "", "", "", "", "", "", "", "",
412 "", "", "", "", "", "", "", "",
415 /* Skip v850e2 MPU bank. It's tempting to reuse these, but we need
416 32 entries for this bank. */
417 "", "", "", "", "", "", "", "",
418 "", "", "", "", "", "", "", "",
419 "", "", "", "", "", "", "", "",
422 /* FPU system registers. These are actually in selID 0, but
423 are placed here to preserve register numbering compatibility
424 with previous architectures. */
425 "", "", "", "", "", "", "fpsr", "fpepc",
426 "fpst", "fpcc", "fpcfg", "fpec", "", "", "", "",
427 "", "", "", "", "", "", "", "",
431 "mcfg0", "mcfg1", "rbase", "ebase", "intbp", "mctl", "pid", "fpipr",
432 "", "", "tcsel", "sccfg", "scbp", "hvccfg", "hvcbp", "vsel",
433 "vmprt0", "vmprt1", "vmprt2", "", "", "", "", "vmscctl",
434 "vmsctbl0", "vmsctbl1", "vmsctbl2", "vmsctbl3", "", "", "", "",
437 "htcfg0", "", "", "", "", "htctl", "mea", "asid",
438 "mei", "ispr", "pmr", "icsr", "intcfg", "", "", "",
439 "tlbsch", "", "", "", "", "", "", "htscctl",
440 "htsctbl0", "htsctbl1", "htsctbl2", "htsctbl3",
441 "htsctbl4", "htsctbl5", "htsctbl6", "htsctbl7",
444 "", "", "", "", "", "", "", "",
445 "", "", "", "", "", "", "", "",
446 "", "", "", "", "", "", "", "",
447 "", "", "", "", "", "", "", "",
450 "tlbidx", "", "", "", "telo0", "telo1", "tehi0", "tehi1",
451 "", "", "tlbcfg", "", "bwerrl", "bwerrh", "brerrl", "brerrh",
452 "ictagl", "ictagh", "icdatl", "icdath",
453 "dctagl", "dctagh", "dcdatl", "dcdath",
454 "icctrl", "dcctrl", "iccfg", "dccfg", "icerr", "dcerr", "", "",
457 "mpm", "mprc", "", "", "mpbrgn", "mptrgn", "", "",
458 "mca", "mcs", "mcc", "mcr", "", "", "", "",
459 "", "", "", "", "mpprt0", "mpprt1", "mpprt2", "",
460 "", "", "", "", "", "", "", "",
463 "mpla0", "mpua0", "mpat0", "", "mpla1", "mpua1", "mpat1", "",
464 "mpla2", "mpua2", "mpat2", "", "mpla3", "mpua3", "mpat3", "",
465 "mpla4", "mpua4", "mpat4", "", "mpla5", "mpua5", "mpat5", "",
466 "mpla6", "mpua6", "mpat6", "", "mpla7", "mpua7", "mpat7", "",
469 "mpla8", "mpua8", "mpat8", "", "mpla9", "mpua9", "mpat9", "",
470 "mpla10", "mpua10", "mpat10", "", "mpla11", "mpua11", "mpat11", "",
471 "mpla12", "mpua12", "mpat12", "", "mpla13", "mpua13", "mpat13", "",
472 "mpla14", "mpua14", "mpat14", "", "mpla15", "mpua15", "mpat15", "",
474 /* Vector Registers */
475 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7",
476 "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15",
477 "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23",
478 "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31",
481 if (regnum
< 0 || regnum
>= E_NUM_OF_V850E3V5_REGS
)
483 return v850e3v5_reg_names
[regnum
];
486 /* Returns the default type for register N. */
489 v850_register_type (struct gdbarch
*gdbarch
, int regnum
)
491 if (regnum
== E_PC_REGNUM
)
492 return builtin_type (gdbarch
)->builtin_func_ptr
;
493 else if (E_VR0_REGNUM
<= regnum
&& regnum
<= E_VR31_REGNUM
)
494 return builtin_type (gdbarch
)->builtin_uint64
;
495 return builtin_type (gdbarch
)->builtin_int32
;
499 v850_type_is_scalar (struct type
*t
)
501 return (t
->code () != TYPE_CODE_STRUCT
502 && t
->code () != TYPE_CODE_UNION
503 && t
->code () != TYPE_CODE_ARRAY
);
506 /* Should call_function allocate stack space for a struct return? */
509 v850_use_struct_convention (struct gdbarch
*gdbarch
, struct type
*type
)
512 struct type
*fld_type
, *tgt_type
;
513 v850_gdbarch_tdep
*tdep
= (v850_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
515 if (tdep
->abi
== V850_ABI_RH850
)
517 if (v850_type_is_scalar (type
) && TYPE_LENGTH(type
) <= 8)
520 /* Structs are never returned in registers for this ABI. */
523 /* 1. The value is greater than 8 bytes -> returned by copying. */
524 if (TYPE_LENGTH (type
) > 8)
527 /* 2. The value is a single basic type -> returned in register. */
528 if (v850_type_is_scalar (type
))
531 /* The value is a structure or union with a single element and that
532 element is either a single basic type or an array of a single basic
533 type whose size is greater than or equal to 4 -> returned in register. */
534 if ((type
->code () == TYPE_CODE_STRUCT
535 || type
->code () == TYPE_CODE_UNION
)
536 && type
->num_fields () == 1)
538 fld_type
= type
->field (0).type ();
539 if (v850_type_is_scalar (fld_type
) && TYPE_LENGTH (fld_type
) >= 4)
542 if (fld_type
->code () == TYPE_CODE_ARRAY
)
544 tgt_type
= TYPE_TARGET_TYPE (fld_type
);
545 if (v850_type_is_scalar (tgt_type
) && TYPE_LENGTH (tgt_type
) >= 4)
550 /* The value is a structure whose first element is an integer or a float,
551 and which contains no arrays of more than two elements -> returned in
553 if (type
->code () == TYPE_CODE_STRUCT
554 && v850_type_is_scalar (type
->field (0).type ())
555 && TYPE_LENGTH (type
->field (0).type ()) == 4)
557 for (i
= 1; i
< type
->num_fields (); ++i
)
559 fld_type
= type
->field (0).type ();
560 if (fld_type
->code () == TYPE_CODE_ARRAY
)
562 tgt_type
= TYPE_TARGET_TYPE (fld_type
);
563 if (TYPE_LENGTH (tgt_type
) > 0
564 && TYPE_LENGTH (fld_type
) / TYPE_LENGTH (tgt_type
) > 2)
571 /* The value is a union which contains at least one field which
572 would be returned in registers according to these rules ->
573 returned in register. */
574 if (type
->code () == TYPE_CODE_UNION
)
576 for (i
= 0; i
< type
->num_fields (); ++i
)
578 fld_type
= type
->field (0).type ();
579 if (!v850_use_struct_convention (gdbarch
, fld_type
))
587 /* Structure for mapping bits in register lists to register numbers. */
595 /* Helper function for v850_scan_prologue to handle prepare instruction. */
598 v850_handle_prepare (int insn
, int insn2
, CORE_ADDR
* current_pc_ptr
,
599 struct v850_frame_cache
*pi
, struct pifsr
**pifsr_ptr
)
601 CORE_ADDR current_pc
= *current_pc_ptr
;
602 struct pifsr
*pifsr
= *pifsr_ptr
;
603 long next
= insn2
& 0xffff;
604 long list12
= ((insn
& 1) << 16) + (next
& 0xffe0);
605 long offset
= (insn
& 0x3e) << 1;
606 static struct reg_list reg_table
[] =
608 {0x00800, 20}, /* r20 */
609 {0x00400, 21}, /* r21 */
610 {0x00200, 22}, /* r22 */
611 {0x00100, 23}, /* r23 */
612 {0x08000, 24}, /* r24 */
613 {0x04000, 25}, /* r25 */
614 {0x02000, 26}, /* r26 */
615 {0x01000, 27}, /* r27 */
616 {0x00080, 28}, /* r28 */
617 {0x00040, 29}, /* r29 */
618 {0x10000, 30}, /* ep */
619 {0x00020, 31}, /* lp */
620 {0, 0} /* end of table */
624 if ((next
& 0x1f) == 0x0b) /* skip imm16 argument */
626 else if ((next
& 0x1f) == 0x13) /* skip imm16 argument */
628 else if ((next
& 0x1f) == 0x1b) /* skip imm32 argument */
631 /* Calculate the total size of the saved registers, and add it to the
632 immediate value used to adjust SP. */
633 for (i
= 0; reg_table
[i
].mask
!= 0; i
++)
634 if (list12
& reg_table
[i
].mask
)
635 offset
+= v850_reg_size
;
636 pi
->sp_offset
-= offset
;
638 /* Calculate the offsets of the registers relative to the value the SP
639 will have after the registers have been pushed and the imm5 value has
640 been subtracted from it. */
643 for (i
= 0; reg_table
[i
].mask
!= 0; i
++)
645 if (list12
& reg_table
[i
].mask
)
647 int reg
= reg_table
[i
].regno
;
648 offset
-= v850_reg_size
;
650 pifsr
->offset
= offset
;
651 pifsr
->cur_frameoffset
= pi
->sp_offset
;
657 /* Set result parameters. */
658 *current_pc_ptr
= current_pc
;
663 /* Helper function for v850_scan_prologue to handle pushm/pushl instructions.
664 The SR bit of the register list is not supported. gcc does not generate
668 v850_handle_pushm (int insn
, int insn2
, struct v850_frame_cache
*pi
,
669 struct pifsr
**pifsr_ptr
)
671 struct pifsr
*pifsr
= *pifsr_ptr
;
672 long list12
= ((insn
& 0x0f) << 16) + (insn2
& 0xfff0);
674 static struct reg_list pushml_reg_table
[] =
676 {0x80000, E_PS_REGNUM
}, /* PSW */
677 {0x40000, 1}, /* r1 */
678 {0x20000, 2}, /* r2 */
679 {0x10000, 3}, /* r3 */
680 {0x00800, 4}, /* r4 */
681 {0x00400, 5}, /* r5 */
682 {0x00200, 6}, /* r6 */
683 {0x00100, 7}, /* r7 */
684 {0x08000, 8}, /* r8 */
685 {0x04000, 9}, /* r9 */
686 {0x02000, 10}, /* r10 */
687 {0x01000, 11}, /* r11 */
688 {0x00080, 12}, /* r12 */
689 {0x00040, 13}, /* r13 */
690 {0x00020, 14}, /* r14 */
691 {0x00010, 15}, /* r15 */
692 {0, 0} /* end of table */
694 static struct reg_list pushmh_reg_table
[] =
696 {0x80000, 16}, /* r16 */
697 {0x40000, 17}, /* r17 */
698 {0x20000, 18}, /* r18 */
699 {0x10000, 19}, /* r19 */
700 {0x00800, 20}, /* r20 */
701 {0x00400, 21}, /* r21 */
702 {0x00200, 22}, /* r22 */
703 {0x00100, 23}, /* r23 */
704 {0x08000, 24}, /* r24 */
705 {0x04000, 25}, /* r25 */
706 {0x02000, 26}, /* r26 */
707 {0x01000, 27}, /* r27 */
708 {0x00080, 28}, /* r28 */
709 {0x00040, 29}, /* r29 */
710 {0x00010, 30}, /* r30 */
711 {0x00020, 31}, /* r31 */
712 {0, 0} /* end of table */
714 struct reg_list
*reg_table
;
717 /* Is this a pushml or a pushmh? */
718 if ((insn2
& 7) == 1)
719 reg_table
= pushml_reg_table
;
721 reg_table
= pushmh_reg_table
;
723 /* Calculate the total size of the saved registers, and add it to the
724 immediate value used to adjust SP. */
725 for (i
= 0; reg_table
[i
].mask
!= 0; i
++)
726 if (list12
& reg_table
[i
].mask
)
727 offset
+= v850_reg_size
;
728 pi
->sp_offset
-= offset
;
730 /* Calculate the offsets of the registers relative to the value the SP
731 will have after the registers have been pushed and the imm5 value is
732 subtracted from it. */
735 for (i
= 0; reg_table
[i
].mask
!= 0; i
++)
737 if (list12
& reg_table
[i
].mask
)
739 int reg
= reg_table
[i
].regno
;
740 offset
-= v850_reg_size
;
742 pifsr
->offset
= offset
;
743 pifsr
->cur_frameoffset
= pi
->sp_offset
;
749 /* Set result parameters. */
753 /* Helper function to evaluate if register is one of the "save" registers.
754 This allows to simplify conditionals in v850_analyze_prologue a lot. */
757 v850_is_save_register (int reg
)
759 /* The caller-save registers are R2, R20 - R29 and R31. All other
760 registers are either special purpose (PC, SP), argument registers,
761 or just considered free for use in the caller. */
762 return reg
== E_R2_REGNUM
763 || (reg
>= E_R20_REGNUM
&& reg
<= E_R29_REGNUM
)
764 || reg
== E_R31_REGNUM
;
767 /* Scan the prologue of the function that contains PC, and record what
768 we find in PI. Returns the pc after the prologue. Note that the
769 addresses saved in frame->saved_regs are just frame relative (negative
770 offsets from the frame pointer). This is because we don't know the
771 actual value of the frame pointer yet. In some circumstances, the
772 frame pointer can't be determined till after we have scanned the
776 v850_analyze_prologue (struct gdbarch
*gdbarch
,
777 CORE_ADDR func_addr
, CORE_ADDR pc
,
778 struct v850_frame_cache
*pi
, ULONGEST ctbp
)
780 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
781 CORE_ADDR prologue_end
, current_pc
;
782 struct pifsr pifsrs
[E_NUM_REGS
+ 1];
783 struct pifsr
*pifsr
, *pifsr_tmp
;
786 CORE_ADDR save_pc
, save_end
;
790 memset (&pifsrs
, 0, sizeof pifsrs
);
795 /* Now, search the prologue looking for instructions that setup fp, save
796 rp, adjust sp and such. We also record the frame offset of any saved
807 for (current_pc
= func_addr
; current_pc
< prologue_end
;)
810 int insn2
= -1; /* dummy value */
812 insn
= read_memory_integer (current_pc
, 2, byte_order
);
814 if ((insn
& 0x0780) >= 0x0600) /* Four byte instruction? */
816 insn2
= read_memory_integer (current_pc
, 2, byte_order
);
820 if ((insn
& 0xffc0) == ((10 << 11) | 0x0780) && !regsave_func_p
)
821 { /* jarl <func>,10 */
822 long low_disp
= insn2
& ~(long) 1;
823 long disp
= (((((insn
& 0x3f) << 16) + low_disp
)
824 & ~(long) 1) ^ 0x00200000) - 0x00200000;
826 save_pc
= current_pc
;
827 save_end
= prologue_end
;
829 current_pc
+= disp
- 4;
830 prologue_end
= (current_pc
831 + (2 * 3) /* moves to/from ep */
832 + 4 /* addi <const>,sp,sp */
834 + (2 * 12) /* sst.w to save r2, r20-r29, r31 */
835 + 20); /* slop area */
837 else if ((insn
& 0xffc0) == 0x0200 && !regsave_func_p
)
839 long adr
= ctbp
+ ((insn
& 0x3f) << 1);
841 save_pc
= current_pc
;
842 save_end
= prologue_end
;
844 current_pc
= ctbp
+ (read_memory_unsigned_integer (adr
, 2, byte_order
)
846 prologue_end
= (current_pc
847 + (2 * 3) /* prepare list2,imm5,sp/imm */
849 + 20); /* slop area */
852 else if ((insn
& 0xffc0) == 0x0780) /* prepare list2,imm5 */
854 v850_handle_prepare (insn
, insn2
, ¤t_pc
, pi
, &pifsr
);
857 else if (insn
== 0x07e0 && regsave_func_p
&& insn2
== 0x0144)
858 { /* ctret after processing register save. */
859 current_pc
= save_pc
;
860 prologue_end
= save_end
;
864 else if ((insn
& 0xfff0) == 0x07e0 && (insn2
& 5) == 1)
865 { /* pushml, pushmh */
866 v850_handle_pushm (insn
, insn2
, pi
, &pifsr
);
869 else if ((insn
& 0xffe0) == 0x0060 && regsave_func_p
)
870 { /* jmp after processing register save. */
871 current_pc
= save_pc
;
872 prologue_end
= save_end
;
876 else if ((insn
& 0x07c0) == 0x0780 /* jarl or jr */
877 || (insn
& 0xffe0) == 0x0060 /* jmp */
878 || (insn
& 0x0780) == 0x0580) /* branch */
880 break; /* Ran into end of prologue. */
883 else if ((insn
& 0xffe0) == ((E_SP_REGNUM
<< 11) | 0x0240))
885 pi
->sp_offset
+= ((insn
& 0x1f) ^ 0x10) - 0x10;
886 else if (insn
== ((E_SP_REGNUM
<< 11) | 0x0600 | E_SP_REGNUM
))
887 /* addi <imm>,sp,sp */
888 pi
->sp_offset
+= insn2
;
889 else if (insn
== ((E_FP_REGNUM
<< 11) | 0x0000 | E_SP_REGNUM
))
892 else if (insn
== ((E_R12_REGNUM
<< 11) | 0x0640 | E_R0_REGNUM
))
893 /* movhi hi(const),r0,r12 */
894 r12_tmp
= insn2
<< 16;
895 else if (insn
== ((E_R12_REGNUM
<< 11) | 0x0620 | E_R12_REGNUM
))
896 /* movea lo(const),r12,r12 */
898 else if (insn
== ((E_SP_REGNUM
<< 11) | 0x01c0 | E_R12_REGNUM
) && r12_tmp
)
900 pi
->sp_offset
+= r12_tmp
;
901 else if (insn
== ((E_EP_REGNUM
<< 11) | 0x0000 | E_SP_REGNUM
))
904 else if (insn
== ((E_EP_REGNUM
<< 11) | 0x0000 | E_R1_REGNUM
))
907 else if (((insn
& 0x07ff) == (0x0760 | E_SP_REGNUM
)
909 && (insn
& 0x07ff) == (0x0760 | E_FP_REGNUM
)))
911 && v850_is_save_register (reg
= (insn
>> 11) & 0x1f))
913 /* st.w <reg>,<offset>[sp] or st.w <reg>,<offset>[fp] */
915 pifsr
->offset
= insn2
& ~1;
916 pifsr
->cur_frameoffset
= pi
->sp_offset
;
920 && ((insn
& 0x0781) == 0x0501)
922 && v850_is_save_register (reg
= (insn
>> 11) & 0x1f))
924 /* sst.w <reg>,<offset>[ep] */
926 pifsr
->offset
= (insn
& 0x007e) << 1;
927 pifsr
->cur_frameoffset
= pi
->sp_offset
;
932 /* Fix up any offsets to the final offset. If a frame pointer was created,
933 use it instead of the stack pointer. */
934 for (pifsr_tmp
= pifsrs
; pifsr_tmp
!= pifsr
; pifsr_tmp
++)
936 pifsr_tmp
->offset
-= pi
->sp_offset
- pifsr_tmp
->cur_frameoffset
;
937 pi
->saved_regs
[pifsr_tmp
->reg
].set_addr (pifsr_tmp
->offset
);
943 /* Return the address of the first code past the prologue of the function. */
946 v850_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
948 CORE_ADDR func_addr
, func_end
;
950 /* See what the symbol table says. */
952 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
954 struct symtab_and_line sal
;
956 sal
= find_pc_line (func_addr
, 0);
957 if (sal
.line
!= 0 && sal
.end
< func_end
)
960 /* Either there's no line info, or the line after the prologue is after
961 the end of the function. In this case, there probably isn't a
966 /* We can't find the start of this function, so there's nothing we
971 /* Return 1 if the data structure has any 8-byte fields that'll require
972 the entire data structure to be aligned. Otherwise, return 0. */
975 v850_eight_byte_align_p (struct type
*type
)
977 type
= check_typedef (type
);
979 if (v850_type_is_scalar (type
))
980 return (TYPE_LENGTH (type
) == 8);
985 for (i
= 0; i
< type
->num_fields (); i
++)
987 if (v850_eight_byte_align_p (type
->field (i
).type ()))
995 v850_frame_align (struct gdbarch
*ignore
, CORE_ADDR sp
)
1000 /* Setup arguments and LP for a call to the target. First four args
1001 go in R6->R9, subsequent args go into sp + 16 -> sp + ... Structs
1002 are passed by reference. 64 bit quantities (doubles and long longs)
1003 may be split between the regs and the stack. When calling a function
1004 that returns a struct, a pointer to the struct is passed in as a secret
1005 first argument (always in R6).
1007 Stack space for the args has NOT been allocated: that job is up to us. */
1010 v850_push_dummy_call (struct gdbarch
*gdbarch
,
1011 struct value
*function
,
1012 struct regcache
*regcache
,
1015 struct value
**args
,
1017 function_call_return_method return_method
,
1018 CORE_ADDR struct_addr
)
1020 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1025 v850_gdbarch_tdep
*tdep
= (v850_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
1027 if (tdep
->abi
== V850_ABI_RH850
)
1031 /* The offset onto the stack at which we will start copying parameters
1032 (after the registers are used up) begins at 16 rather than at zero.
1033 That's how the ABI is defined, though there's no indication that these
1034 16 bytes are used for anything, not even for saving incoming
1035 argument registers. */
1039 /* Now make space on the stack for the args. */
1040 for (argnum
= 0; argnum
< nargs
; argnum
++)
1041 arg_space
+= ((TYPE_LENGTH (value_type (args
[argnum
])) + 3) & ~3);
1042 sp
-= arg_space
+ stack_offset
;
1044 argreg
= E_ARG0_REGNUM
;
1045 /* The struct_return pointer occupies the first parameter register. */
1046 if (return_method
== return_method_struct
)
1047 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
1049 /* Now load as many as possible of the first arguments into
1050 registers, and push the rest onto the stack. There are 16 bytes
1051 in four registers available. Loop thru args from first to last. */
1052 for (argnum
= 0; argnum
< nargs
; argnum
++)
1056 gdb_byte valbuf
[v850_reg_size
];
1058 if (!v850_type_is_scalar (value_type (*args
))
1059 && tdep
->abi
== V850_ABI_GCC
1060 && TYPE_LENGTH (value_type (*args
)) > E_MAX_RETTYPE_SIZE_IN_REGS
)
1062 store_unsigned_integer (valbuf
, 4, byte_order
,
1063 value_address (*args
));
1069 len
= TYPE_LENGTH (value_type (*args
));
1070 val
= (gdb_byte
*) value_contents (*args
).data ();
1073 if (tdep
->eight_byte_align
1074 && v850_eight_byte_align_p (value_type (*args
)))
1076 if (argreg
<= E_ARGLAST_REGNUM
&& (argreg
& 1))
1078 else if (stack_offset
& 0x4)
1083 if (argreg
<= E_ARGLAST_REGNUM
)
1087 regval
= extract_unsigned_integer (val
, v850_reg_size
, byte_order
);
1088 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
1090 len
-= v850_reg_size
;
1091 val
+= v850_reg_size
;
1096 write_memory (sp
+ stack_offset
, val
, 4);
1105 /* Store return address. */
1106 regcache_cooked_write_unsigned (regcache
, E_LP_REGNUM
, bp_addr
);
1108 /* Update stack pointer. */
1109 regcache_cooked_write_unsigned (regcache
, E_SP_REGNUM
, sp
);
1115 v850_extract_return_value (struct type
*type
, struct regcache
*regcache
,
1118 struct gdbarch
*gdbarch
= regcache
->arch ();
1119 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1120 int len
= TYPE_LENGTH (type
);
1122 if (len
<= v850_reg_size
)
1126 regcache_cooked_read_unsigned (regcache
, E_V0_REGNUM
, &val
);
1127 store_unsigned_integer (valbuf
, len
, byte_order
, val
);
1129 else if (len
<= 2 * v850_reg_size
)
1131 int i
, regnum
= E_V0_REGNUM
;
1132 gdb_byte buf
[v850_reg_size
];
1133 for (i
= 0; len
> 0; i
+= 4, len
-= 4)
1135 regcache
->raw_read (regnum
++, buf
);
1136 memcpy (valbuf
+ i
, buf
, len
> 4 ? 4 : len
);
1142 v850_store_return_value (struct type
*type
, struct regcache
*regcache
,
1143 const gdb_byte
*valbuf
)
1145 struct gdbarch
*gdbarch
= regcache
->arch ();
1146 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1147 int len
= TYPE_LENGTH (type
);
1149 if (len
<= v850_reg_size
)
1150 regcache_cooked_write_unsigned
1151 (regcache
, E_V0_REGNUM
,
1152 extract_unsigned_integer (valbuf
, len
, byte_order
));
1153 else if (len
<= 2 * v850_reg_size
)
1155 int i
, regnum
= E_V0_REGNUM
;
1156 for (i
= 0; i
< len
; i
+= 4)
1157 regcache
->raw_write (regnum
++, valbuf
+ i
);
1161 static enum return_value_convention
1162 v850_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
1163 struct type
*type
, struct regcache
*regcache
,
1164 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
1166 if (v850_use_struct_convention (gdbarch
, type
))
1167 return RETURN_VALUE_STRUCT_CONVENTION
;
1169 v850_store_return_value (type
, regcache
, writebuf
);
1171 v850_extract_return_value (type
, regcache
, readbuf
);
1172 return RETURN_VALUE_REGISTER_CONVENTION
;
1175 /* Implement the breakpoint_kind_from_pc gdbarch method. */
1178 v850_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
1183 /* Implement the sw_breakpoint_from_kind gdbarch method. */
1185 static const gdb_byte
*
1186 v850_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
1190 switch (gdbarch_bfd_arch_info (gdbarch
)->mach
)
1192 case bfd_mach_v850e2
:
1193 case bfd_mach_v850e2v3
:
1194 case bfd_mach_v850e3v5
:
1196 /* Implement software breakpoints by using the dbtrap instruction.
1197 Older architectures had no such instruction. For those, an
1198 unconditional branch to self instruction is used. */
1200 static unsigned char dbtrap_breakpoint
[] = { 0x40, 0xf8 };
1202 return dbtrap_breakpoint
;
1207 static unsigned char breakpoint
[] = { 0x85, 0x05 };
1215 static struct v850_frame_cache
*
1216 v850_alloc_frame_cache (struct frame_info
*this_frame
)
1218 struct v850_frame_cache
*cache
;
1220 cache
= FRAME_OBSTACK_ZALLOC (struct v850_frame_cache
);
1221 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1225 cache
->sp_offset
= 0;
1228 /* Frameless until proven otherwise. */
1234 static struct v850_frame_cache
*
1235 v850_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1237 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1238 struct v850_frame_cache
*cache
;
1239 CORE_ADDR current_pc
;
1243 return (struct v850_frame_cache
*) *this_cache
;
1245 cache
= v850_alloc_frame_cache (this_frame
);
1246 *this_cache
= cache
;
1248 /* In principle, for normal frames, fp holds the frame pointer,
1249 which holds the base address for the current stack frame.
1250 However, for functions that don't need it, the frame pointer is
1251 optional. For these "frameless" functions the frame pointer is
1252 actually the frame pointer of the calling frame. */
1253 cache
->base
= get_frame_register_unsigned (this_frame
, E_FP_REGNUM
);
1254 if (cache
->base
== 0)
1257 cache
->pc
= get_frame_func (this_frame
);
1258 current_pc
= get_frame_pc (this_frame
);
1262 ctbp
= get_frame_register_unsigned (this_frame
, E_CTBP_REGNUM
);
1263 v850_analyze_prologue (gdbarch
, cache
->pc
, current_pc
, cache
, ctbp
);
1266 if (!cache
->uses_fp
)
1268 /* We didn't find a valid frame, which means that CACHE->base
1269 currently holds the frame pointer for our calling frame. If
1270 we're at the start of a function, or somewhere half-way its
1271 prologue, the function's frame probably hasn't been fully
1272 setup yet. Try to reconstruct the base address for the stack
1273 frame by looking at the stack pointer. For truly "frameless"
1274 functions this might work too. */
1275 cache
->base
= get_frame_register_unsigned (this_frame
, E_SP_REGNUM
);
1278 /* Now that we have the base address for the stack frame we can
1279 calculate the value of sp in the calling frame. */
1280 cache
->saved_regs
[E_SP_REGNUM
].set_value (cache
->base
- cache
->sp_offset
);
1282 /* Adjust all the saved registers such that they contain addresses
1283 instead of offsets. */
1284 for (i
= 0; i
< gdbarch_num_regs (gdbarch
); i
++)
1285 if (cache
->saved_regs
[i
].is_addr ())
1286 cache
->saved_regs
[i
].set_addr (cache
->saved_regs
[i
].addr ()
1289 /* The call instruction moves the caller's PC in the callee's LP.
1290 Since this is an unwind, do the reverse. Copy the location of LP
1291 into PC (the address / regnum) so that a request for PC will be
1292 converted into a request for the LP. */
1294 cache
->saved_regs
[E_PC_REGNUM
] = cache
->saved_regs
[E_LP_REGNUM
];
1300 static struct value
*
1301 v850_frame_prev_register (struct frame_info
*this_frame
,
1302 void **this_cache
, int regnum
)
1304 struct v850_frame_cache
*cache
= v850_frame_cache (this_frame
, this_cache
);
1306 gdb_assert (regnum
>= 0);
1308 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
, regnum
);
1312 v850_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1313 struct frame_id
*this_id
)
1315 struct v850_frame_cache
*cache
= v850_frame_cache (this_frame
, this_cache
);
1317 /* This marks the outermost frame. */
1318 if (cache
->base
== 0)
1321 *this_id
= frame_id_build (cache
->saved_regs
[E_SP_REGNUM
].addr (), cache
->pc
);
1324 static const struct frame_unwind v850_frame_unwind
= {
1327 default_frame_unwind_stop_reason
,
1329 v850_frame_prev_register
,
1331 default_frame_sniffer
1335 v850_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
1337 struct v850_frame_cache
*cache
= v850_frame_cache (this_frame
, this_cache
);
1342 static const struct frame_base v850_frame_base
= {
1344 v850_frame_base_address
,
1345 v850_frame_base_address
,
1346 v850_frame_base_address
1349 static struct gdbarch
*
1350 v850_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
1352 struct gdbarch
*gdbarch
;
1353 int e_flags
, e_machine
;
1355 /* Extract the elf_flags if available. */
1356 if (info
.abfd
!= NULL
1357 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
1359 e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
1360 e_machine
= elf_elfheader (info
.abfd
)->e_machine
;
1369 /* Try to find the architecture in the list of already defined
1371 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
1373 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
1375 v850_gdbarch_tdep
*tdep
1376 = (v850_gdbarch_tdep
*) gdbarch_tdep (arches
->gdbarch
);
1378 if (tdep
->e_flags
!= e_flags
|| tdep
->e_machine
!= e_machine
)
1381 return arches
->gdbarch
;
1384 v850_gdbarch_tdep
*tdep
= new v850_gdbarch_tdep
;
1385 tdep
->e_flags
= e_flags
;
1386 tdep
->e_machine
= e_machine
;
1388 switch (tdep
->e_machine
)
1391 tdep
->abi
= V850_ABI_RH850
;
1394 tdep
->abi
= V850_ABI_GCC
;
1398 tdep
->eight_byte_align
= (tdep
->e_flags
& EF_RH850_DATA_ALIGN8
) ? 1 : 0;
1399 gdbarch
= gdbarch_alloc (&info
, tdep
);
1401 switch (info
.bfd_arch_info
->mach
)
1404 set_gdbarch_register_name (gdbarch
, v850_register_name
);
1405 set_gdbarch_num_regs (gdbarch
, E_NUM_OF_V850_REGS
);
1407 case bfd_mach_v850e
:
1408 case bfd_mach_v850e1
:
1409 set_gdbarch_register_name (gdbarch
, v850e_register_name
);
1410 set_gdbarch_num_regs (gdbarch
, E_NUM_OF_V850E_REGS
);
1412 case bfd_mach_v850e2
:
1413 case bfd_mach_v850e2v3
:
1414 set_gdbarch_register_name (gdbarch
, v850e2_register_name
);
1415 set_gdbarch_num_regs (gdbarch
, E_NUM_REGS
);
1417 case bfd_mach_v850e3v5
:
1418 set_gdbarch_register_name (gdbarch
, v850e3v5_register_name
);
1419 set_gdbarch_num_regs (gdbarch
, E_NUM_OF_V850E3V5_REGS
);
1423 set_gdbarch_num_pseudo_regs (gdbarch
, 0);
1424 set_gdbarch_sp_regnum (gdbarch
, E_SP_REGNUM
);
1425 set_gdbarch_pc_regnum (gdbarch
, E_PC_REGNUM
);
1426 set_gdbarch_fp0_regnum (gdbarch
, -1);
1428 set_gdbarch_register_type (gdbarch
, v850_register_type
);
1430 set_gdbarch_char_signed (gdbarch
, 1);
1431 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
1432 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
1433 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
1434 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
1436 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
1437 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
1438 set_gdbarch_long_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
1440 set_gdbarch_ptr_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
1441 set_gdbarch_addr_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
1443 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
1445 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, v850_breakpoint_kind_from_pc
);
1446 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, v850_sw_breakpoint_from_kind
);
1447 set_gdbarch_return_value (gdbarch
, v850_return_value
);
1448 set_gdbarch_push_dummy_call (gdbarch
, v850_push_dummy_call
);
1449 set_gdbarch_skip_prologue (gdbarch
, v850_skip_prologue
);
1451 set_gdbarch_frame_align (gdbarch
, v850_frame_align
);
1452 frame_base_set_default (gdbarch
, &v850_frame_base
);
1454 /* Hook in ABI-specific overrides, if they have been registered. */
1455 gdbarch_init_osabi (info
, gdbarch
);
1457 dwarf2_append_unwinders (gdbarch
);
1458 frame_unwind_append_unwinder (gdbarch
, &v850_frame_unwind
);
1463 void _initialize_v850_tdep ();
1465 _initialize_v850_tdep ()
1467 register_gdbarch_init (bfd_arch_v850
, v850_gdbarch_init
);
1468 register_gdbarch_init (bfd_arch_v850_rh850
, v850_gdbarch_init
);