1 /* Target-dependent code for the Xtensa port of GDB, the GNU debugger.
3 Copyright (C) 2003-2022 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include "solib-svr4.h"
29 #include "reggroups.h"
32 #include "dwarf2/frame.h"
33 #include "frame-base.h"
34 #include "frame-unwind.h"
36 #include "arch-utils.h"
42 #include "xtensa-isa.h"
43 #include "xtensa-tdep.h"
44 #include "xtensa-config.h"
48 static unsigned int xtensa_debug_level
= 0;
50 #define DEBUGWARN(args...) \
51 if (xtensa_debug_level > 0) \
52 fprintf_unfiltered (gdb_stdlog, "(warn ) " args)
54 #define DEBUGINFO(args...) \
55 if (xtensa_debug_level > 1) \
56 fprintf_unfiltered (gdb_stdlog, "(info ) " args)
58 #define DEBUGTRACE(args...) \
59 if (xtensa_debug_level > 2) \
60 fprintf_unfiltered (gdb_stdlog, "(trace) " args)
62 #define DEBUGVERB(args...) \
63 if (xtensa_debug_level > 3) \
64 fprintf_unfiltered (gdb_stdlog, "(verb ) " args)
67 /* According to the ABI, the SP must be aligned to 16-byte boundaries. */
68 #define SP_ALIGNMENT 16
71 /* On Windowed ABI, we use a6 through a11 for passing arguments
72 to a function called by GDB because CALL4 is used. */
73 #define ARGS_NUM_REGS 6
74 #define REGISTER_SIZE 4
77 /* Extract the call size from the return address or PS register. */
78 #define PS_CALLINC_SHIFT 16
79 #define PS_CALLINC_MASK 0x00030000
80 #define CALLINC(ps) (((ps) & PS_CALLINC_MASK) >> PS_CALLINC_SHIFT)
81 #define WINSIZE(ra) (4 * (( (ra) >> 30) & 0x3))
83 /* On TX, hardware can be configured without Exception Option.
84 There is no PS register in this case. Inside XT-GDB, let us treat
85 it as a virtual read-only register always holding the same value. */
88 /* ABI-independent macros. */
89 #define ARG_NOF(tdep) \
91 == CallAbiCall0Only ? C0_NARGS : (ARGS_NUM_REGS))
92 #define ARG_1ST(tdep) \
93 (tdep->call_abi == CallAbiCall0Only \
94 ? (tdep->a0_base + C0_ARGS) \
95 : (tdep->a0_base + 6))
97 /* XTENSA_IS_ENTRY tests whether the first byte of an instruction
98 indicates that the instruction is an ENTRY instruction. */
100 #define XTENSA_IS_ENTRY(gdbarch, op1) \
101 ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) \
102 ? ((op1) == 0x6c) : ((op1) == 0x36))
104 #define XTENSA_ENTRY_LENGTH 3
106 /* windowing_enabled() returns true, if windowing is enabled.
107 WOE must be set to 1; EXCM to 0.
108 Note: We assume that EXCM is always 0 for XEA1. */
110 #define PS_WOE (1<<18)
111 #define PS_EXC (1<<4)
113 /* Big enough to hold the size of the largest register in bytes. */
114 #define XTENSA_MAX_REGISTER_SIZE 64
117 windowing_enabled (struct gdbarch
*gdbarch
, unsigned int ps
)
119 xtensa_gdbarch_tdep
*tdep
= (xtensa_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
121 /* If we know CALL0 ABI is set explicitly, say it is Call0. */
122 if (tdep
->call_abi
== CallAbiCall0Only
)
125 return ((ps
& PS_EXC
) == 0 && (ps
& PS_WOE
) != 0);
128 /* Convert a live A-register number to the corresponding AR-register
131 arreg_number (struct gdbarch
*gdbarch
, int a_regnum
, ULONGEST wb
)
133 xtensa_gdbarch_tdep
*tdep
= (xtensa_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
136 arreg
= a_regnum
- tdep
->a0_base
;
137 arreg
+= (wb
& ((tdep
->num_aregs
- 1) >> 2)) << WB_SHIFT
;
138 arreg
&= tdep
->num_aregs
- 1;
140 return arreg
+ tdep
->ar_base
;
143 /* Convert a live AR-register number to the corresponding A-register order
144 number in a range [0..15]. Return -1, if AR_REGNUM is out of WB window. */
146 areg_number (struct gdbarch
*gdbarch
, int ar_regnum
, unsigned int wb
)
148 xtensa_gdbarch_tdep
*tdep
= (xtensa_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
151 areg
= ar_regnum
- tdep
->ar_base
;
152 if (areg
< 0 || areg
>= tdep
->num_aregs
)
154 areg
= (areg
- wb
* 4) & (tdep
->num_aregs
- 1);
155 return (areg
> 15) ? -1 : areg
;
158 /* Read Xtensa register directly from the hardware. */
160 xtensa_read_register (int regnum
)
164 regcache_raw_read_unsigned (get_current_regcache (), regnum
, &value
);
165 return (unsigned long) value
;
168 /* Write Xtensa register directly to the hardware. */
170 xtensa_write_register (int regnum
, ULONGEST value
)
172 regcache_raw_write_unsigned (get_current_regcache (), regnum
, value
);
175 /* Return the window size of the previous call to the function from which we
178 This function is used to extract the return value after a called function
179 has returned to the caller. On Xtensa, the register that holds the return
180 value (from the perspective of the caller) depends on what call
181 instruction was used. For now, we are assuming that the call instruction
182 precedes the current address, so we simply analyze the call instruction.
183 If we are in a dummy frame, we simply return 4 as we used a 'pseudo-call4'
184 method to call the inferior function. */
187 extract_call_winsize (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
189 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
194 DEBUGTRACE ("extract_call_winsize (pc = 0x%08x)\n", (int) pc
);
196 /* Read the previous instruction (should be a call[x]{4|8|12}. */
197 read_memory (pc
-3, buf
, 3);
198 insn
= extract_unsigned_integer (buf
, 3, byte_order
);
200 /* Decode call instruction:
202 call{0,4,8,12} OFFSET || {00,01,10,11} || 0101
203 callx{0,4,8,12} OFFSET || 11 || {00,01,10,11} || 0000
205 call{0,4,8,12} 0101 || {00,01,10,11} || OFFSET
206 callx{0,4,8,12} 0000 || {00,01,10,11} || 11 || OFFSET. */
208 if (byte_order
== BFD_ENDIAN_LITTLE
)
210 if (((insn
& 0xf) == 0x5) || ((insn
& 0xcf) == 0xc0))
211 winsize
= (insn
& 0x30) >> 2; /* 0, 4, 8, 12. */
215 if (((insn
>> 20) == 0x5) || (((insn
>> 16) & 0xf3) == 0x03))
216 winsize
= (insn
>> 16) & 0xc; /* 0, 4, 8, 12. */
222 /* REGISTER INFORMATION */
224 /* Find register by name. */
226 xtensa_find_register_by_name (struct gdbarch
*gdbarch
, const char *name
)
229 xtensa_gdbarch_tdep
*tdep
= (xtensa_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
231 for (i
= 0; i
< gdbarch_num_cooked_regs (gdbarch
); i
++)
232 if (strcasecmp (tdep
->regmap
[i
].name
, name
) == 0)
238 /* Returns the name of a register. */
240 xtensa_register_name (struct gdbarch
*gdbarch
, int regnum
)
242 xtensa_gdbarch_tdep
*tdep
= (xtensa_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
244 /* Return the name stored in the register map. */
245 if (regnum
>= 0 && regnum
< gdbarch_num_cooked_regs (gdbarch
))
246 return tdep
->regmap
[regnum
].name
;
248 internal_error (__FILE__
, __LINE__
, _("invalid register %d"), regnum
);
252 /* Return the type of a register. Create a new type, if necessary. */
255 xtensa_register_type (struct gdbarch
*gdbarch
, int regnum
)
257 xtensa_gdbarch_tdep
*tdep
= (xtensa_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
259 /* Return signed integer for ARx and Ax registers. */
260 if ((regnum
>= tdep
->ar_base
261 && regnum
< tdep
->ar_base
+ tdep
->num_aregs
)
262 || (regnum
>= tdep
->a0_base
263 && regnum
< tdep
->a0_base
+ 16))
264 return builtin_type (gdbarch
)->builtin_int
;
266 if (regnum
== gdbarch_pc_regnum (gdbarch
)
267 || regnum
== tdep
->a0_base
+ 1)
268 return builtin_type (gdbarch
)->builtin_data_ptr
;
270 /* Return the stored type for all other registers. */
271 else if (regnum
>= 0 && regnum
< gdbarch_num_cooked_regs (gdbarch
))
273 xtensa_register_t
* reg
= &tdep
->regmap
[regnum
];
275 /* Set ctype for this register (only the first time). */
279 struct ctype_cache
*tp
;
280 int size
= reg
->byte_size
;
282 /* We always use the memory representation,
283 even if the register width is smaller. */
287 reg
->ctype
= builtin_type (gdbarch
)->builtin_uint8
;
291 reg
->ctype
= builtin_type (gdbarch
)->builtin_uint16
;
295 reg
->ctype
= builtin_type (gdbarch
)->builtin_uint32
;
299 reg
->ctype
= builtin_type (gdbarch
)->builtin_uint64
;
303 reg
->ctype
= builtin_type (gdbarch
)->builtin_uint128
;
307 for (tp
= tdep
->type_entries
; tp
!= NULL
; tp
= tp
->next
)
308 if (tp
->size
== size
)
313 std::string name
= string_printf ("int%d", size
* 8);
315 tp
= XNEW (struct ctype_cache
);
316 tp
->next
= tdep
->type_entries
;
317 tdep
->type_entries
= tp
;
320 = arch_integer_type (gdbarch
, size
* 8, 1, name
.c_str ());
323 reg
->ctype
= tp
->virtual_type
;
329 internal_error (__FILE__
, __LINE__
, _("invalid register number %d"), regnum
);
334 /* Return the 'local' register number for stubs, dwarf2, etc.
335 The debugging information enumerates registers starting from 0 for A0
336 to n for An. So, we only have to add the base number for A0. */
339 xtensa_reg_to_regnum (struct gdbarch
*gdbarch
, int regnum
)
342 xtensa_gdbarch_tdep
*tdep
= (xtensa_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
344 if (regnum
>= 0 && regnum
< 16)
345 return tdep
->a0_base
+ regnum
;
347 for (i
= 0; i
< gdbarch_num_cooked_regs (gdbarch
); i
++)
348 if (regnum
== tdep
->regmap
[i
].target_number
)
355 /* Write the bits of a masked register to the various registers.
356 Only the masked areas of these registers are modified; the other
357 fields are untouched. The size of masked registers is always less
358 than or equal to 32 bits. */
361 xtensa_register_write_masked (struct regcache
*regcache
,
362 xtensa_register_t
*reg
, const gdb_byte
*buffer
)
364 unsigned int value
[(XTENSA_MAX_REGISTER_SIZE
+ 3) / 4];
365 const xtensa_mask_t
*mask
= reg
->mask
;
367 int shift
= 0; /* Shift for next mask (mod 32). */
368 int start
, size
; /* Start bit and size of current mask. */
370 unsigned int *ptr
= value
;
371 unsigned int regval
, m
, mem
= 0;
373 int bytesize
= reg
->byte_size
;
374 int bitsize
= bytesize
* 8;
377 DEBUGTRACE ("xtensa_register_write_masked ()\n");
379 /* Copy the masked register to host byte-order. */
380 if (gdbarch_byte_order (regcache
->arch ()) == BFD_ENDIAN_BIG
)
381 for (i
= 0; i
< bytesize
; i
++)
384 mem
|= (buffer
[bytesize
- i
- 1] << 24);
389 for (i
= 0; i
< bytesize
; i
++)
392 mem
|= (buffer
[i
] << 24);
397 /* We might have to shift the final value:
398 bytesize & 3 == 0 -> nothing to do, we use the full 32 bits,
399 bytesize & 3 == x -> shift (4-x) * 8. */
401 *ptr
= mem
>> (((0 - bytesize
) & 3) * 8);
405 /* Write the bits to the masked areas of the other registers. */
406 for (i
= 0; i
< mask
->count
; i
++)
408 start
= mask
->mask
[i
].bit_start
;
409 size
= mask
->mask
[i
].bit_size
;
410 regval
= mem
>> shift
;
412 if ((shift
+= size
) > bitsize
)
413 error (_("size of all masks is larger than the register"));
422 regval
|= mem
<< (size
- shift
);
425 /* Make sure we have a valid register. */
426 r
= mask
->mask
[i
].reg_num
;
427 if (r
>= 0 && size
> 0)
429 /* Don't overwrite the unmasked areas. */
431 regcache_cooked_read_unsigned (regcache
, r
, &old_val
);
432 m
= 0xffffffff >> (32 - size
) << start
;
434 regval
= (regval
& m
) | (old_val
& ~m
);
435 regcache_cooked_write_unsigned (regcache
, r
, regval
);
441 /* Read a tie state or mapped registers. Read the masked areas
442 of the registers and assemble them into a single value. */
444 static enum register_status
445 xtensa_register_read_masked (readable_regcache
*regcache
,
446 xtensa_register_t
*reg
, gdb_byte
*buffer
)
448 unsigned int value
[(XTENSA_MAX_REGISTER_SIZE
+ 3) / 4];
449 const xtensa_mask_t
*mask
= reg
->mask
;
454 unsigned int *ptr
= value
;
455 unsigned int regval
, mem
= 0;
457 int bytesize
= reg
->byte_size
;
458 int bitsize
= bytesize
* 8;
461 DEBUGTRACE ("xtensa_register_read_masked (reg \"%s\", ...)\n",
462 reg
->name
== 0 ? "" : reg
->name
);
464 /* Assemble the register from the masked areas of other registers. */
465 for (i
= 0; i
< mask
->count
; i
++)
467 int r
= mask
->mask
[i
].reg_num
;
470 enum register_status status
;
473 status
= regcache
->cooked_read (r
, &val
);
474 if (status
!= REG_VALID
)
476 regval
= (unsigned int) val
;
481 start
= mask
->mask
[i
].bit_start
;
482 size
= mask
->mask
[i
].bit_size
;
487 regval
&= (0xffffffff >> (32 - size
));
489 mem
|= regval
<< shift
;
491 if ((shift
+= size
) > bitsize
)
492 error (_("size of all masks is larger than the register"));
503 mem
= regval
>> (size
- shift
);
510 /* Copy value to target byte order. */
514 if (gdbarch_byte_order (regcache
->arch ()) == BFD_ENDIAN_BIG
)
515 for (i
= 0; i
< bytesize
; i
++)
519 buffer
[bytesize
- i
- 1] = mem
& 0xff;
523 for (i
= 0; i
< bytesize
; i
++)
527 buffer
[i
] = mem
& 0xff;
535 /* Read pseudo registers. */
537 static enum register_status
538 xtensa_pseudo_register_read (struct gdbarch
*gdbarch
,
539 readable_regcache
*regcache
,
543 DEBUGTRACE ("xtensa_pseudo_register_read (... regnum = %d (%s) ...)\n",
544 regnum
, xtensa_register_name (gdbarch
, regnum
));
545 xtensa_gdbarch_tdep
*tdep
= (xtensa_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
547 /* Read aliases a0..a15, if this is a Windowed ABI. */
548 if (tdep
->isa_use_windowed_registers
549 && (regnum
>= tdep
->a0_base
)
550 && (regnum
<= tdep
->a0_base
+ 15))
553 enum register_status status
;
555 status
= regcache
->raw_read (tdep
->wb_regnum
,
557 if (status
!= REG_VALID
)
559 regnum
= arreg_number (gdbarch
, regnum
, value
);
562 /* We can always read non-pseudo registers. */
563 if (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
))
564 return regcache
->raw_read (regnum
, buffer
);
566 /* We have to find out how to deal with priveleged registers.
567 Let's treat them as pseudo-registers, but we cannot read/write them. */
569 else if (tdep
->call_abi
== CallAbiCall0Only
570 || regnum
< tdep
->a0_base
)
572 buffer
[0] = (gdb_byte
)0;
573 buffer
[1] = (gdb_byte
)0;
574 buffer
[2] = (gdb_byte
)0;
575 buffer
[3] = (gdb_byte
)0;
578 /* Pseudo registers. */
579 else if (regnum
>= 0 && regnum
< gdbarch_num_cooked_regs (gdbarch
))
581 xtensa_register_t
*reg
= &tdep
->regmap
[regnum
];
582 xtensa_register_type_t type
= reg
->type
;
583 int flags
= tdep
->target_flags
;
585 /* We cannot read Unknown or Unmapped registers. */
586 if (type
== xtRegisterTypeUnmapped
|| type
== xtRegisterTypeUnknown
)
588 if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
590 warning (_("cannot read register %s"),
591 xtensa_register_name (gdbarch
, regnum
));
596 /* Some targets cannot read TIE register files. */
597 else if (type
== xtRegisterTypeTieRegfile
)
599 /* Use 'fetch' to get register? */
600 if (flags
& xtTargetFlagsUseFetchStore
)
602 warning (_("cannot read register"));
606 /* On some targets (esp. simulators), we can always read the reg. */
607 else if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
609 warning (_("cannot read register"));
614 /* We can always read mapped registers. */
615 else if (type
== xtRegisterTypeMapped
|| type
== xtRegisterTypeTieState
)
616 return xtensa_register_read_masked (regcache
, reg
, buffer
);
618 /* Assume that we can read the register. */
619 return regcache
->raw_read (regnum
, buffer
);
622 internal_error (__FILE__
, __LINE__
,
623 _("invalid register number %d"), regnum
);
627 /* Write pseudo registers. */
630 xtensa_pseudo_register_write (struct gdbarch
*gdbarch
,
631 struct regcache
*regcache
,
633 const gdb_byte
*buffer
)
635 DEBUGTRACE ("xtensa_pseudo_register_write (... regnum = %d (%s) ...)\n",
636 regnum
, xtensa_register_name (gdbarch
, regnum
));
637 xtensa_gdbarch_tdep
*tdep
= (xtensa_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
639 /* Renumber register, if aliases a0..a15 on Windowed ABI. */
640 if (tdep
->isa_use_windowed_registers
641 && (regnum
>= tdep
->a0_base
)
642 && (regnum
<= tdep
->a0_base
+ 15))
645 regcache_raw_read_unsigned (regcache
,
646 tdep
->wb_regnum
, &value
);
647 regnum
= arreg_number (gdbarch
, regnum
, value
);
650 /* We can always write 'core' registers.
651 Note: We might have converted Ax->ARy. */
652 if (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
))
653 regcache
->raw_write (regnum
, buffer
);
655 /* We have to find out how to deal with priveleged registers.
656 Let's treat them as pseudo-registers, but we cannot read/write them. */
658 else if (regnum
< tdep
->a0_base
)
662 /* Pseudo registers. */
663 else if (regnum
>= 0 && regnum
< gdbarch_num_cooked_regs (gdbarch
))
665 xtensa_register_t
*reg
= &tdep
->regmap
[regnum
];
666 xtensa_register_type_t type
= reg
->type
;
667 int flags
= tdep
->target_flags
;
669 /* On most targets, we cannot write registers
670 of type "Unknown" or "Unmapped". */
671 if (type
== xtRegisterTypeUnmapped
|| type
== xtRegisterTypeUnknown
)
673 if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
675 warning (_("cannot write register %s"),
676 xtensa_register_name (gdbarch
, regnum
));
681 /* Some targets cannot read TIE register files. */
682 else if (type
== xtRegisterTypeTieRegfile
)
684 /* Use 'store' to get register? */
685 if (flags
& xtTargetFlagsUseFetchStore
)
687 warning (_("cannot write register"));
691 /* On some targets (esp. simulators), we can always write
693 else if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
695 warning (_("cannot write register"));
700 /* We can always write mapped registers. */
701 else if (type
== xtRegisterTypeMapped
|| type
== xtRegisterTypeTieState
)
703 xtensa_register_write_masked (regcache
, reg
, buffer
);
707 /* Assume that we can write the register. */
708 regcache
->raw_write (regnum
, buffer
);
711 internal_error (__FILE__
, __LINE__
,
712 _("invalid register number %d"), regnum
);
715 static struct reggroup
*xtensa_ar_reggroup
;
716 static struct reggroup
*xtensa_user_reggroup
;
717 static struct reggroup
*xtensa_vectra_reggroup
;
718 static struct reggroup
*xtensa_cp
[XTENSA_MAX_COPROCESSOR
];
721 xtensa_init_reggroups (void)
725 xtensa_ar_reggroup
= reggroup_new ("ar", USER_REGGROUP
);
726 xtensa_user_reggroup
= reggroup_new ("user", USER_REGGROUP
);
727 xtensa_vectra_reggroup
= reggroup_new ("vectra", USER_REGGROUP
);
729 for (i
= 0; i
< XTENSA_MAX_COPROCESSOR
; i
++)
730 xtensa_cp
[i
] = reggroup_new (xstrprintf ("cp%d", i
).release (),
735 xtensa_add_reggroups (struct gdbarch
*gdbarch
)
739 /* Predefined groups. */
740 reggroup_add (gdbarch
, all_reggroup
);
741 reggroup_add (gdbarch
, save_reggroup
);
742 reggroup_add (gdbarch
, restore_reggroup
);
743 reggroup_add (gdbarch
, system_reggroup
);
744 reggroup_add (gdbarch
, vector_reggroup
);
745 reggroup_add (gdbarch
, general_reggroup
);
746 reggroup_add (gdbarch
, float_reggroup
);
748 /* Xtensa-specific groups. */
749 reggroup_add (gdbarch
, xtensa_ar_reggroup
);
750 reggroup_add (gdbarch
, xtensa_user_reggroup
);
751 reggroup_add (gdbarch
, xtensa_vectra_reggroup
);
753 for (i
= 0; i
< XTENSA_MAX_COPROCESSOR
; i
++)
754 reggroup_add (gdbarch
, xtensa_cp
[i
]);
758 xtensa_coprocessor_register_group (struct reggroup
*group
)
762 for (i
= 0; i
< XTENSA_MAX_COPROCESSOR
; i
++)
763 if (group
== xtensa_cp
[i
])
769 #define SAVE_REST_FLAGS (XTENSA_REGISTER_FLAGS_READABLE \
770 | XTENSA_REGISTER_FLAGS_WRITABLE \
771 | XTENSA_REGISTER_FLAGS_VOLATILE)
773 #define SAVE_REST_VALID (XTENSA_REGISTER_FLAGS_READABLE \
774 | XTENSA_REGISTER_FLAGS_WRITABLE)
777 xtensa_register_reggroup_p (struct gdbarch
*gdbarch
,
779 struct reggroup
*group
)
781 xtensa_gdbarch_tdep
*tdep
= (xtensa_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
782 xtensa_register_t
* reg
= &tdep
->regmap
[regnum
];
783 xtensa_register_type_t type
= reg
->type
;
784 xtensa_register_group_t rg
= reg
->group
;
787 if (group
== save_reggroup
)
788 /* Every single register should be included into the list of registers
789 to be watched for changes while using -data-list-changed-registers. */
792 /* First, skip registers that are not visible to this target
793 (unknown and unmapped registers when not using ISS). */
795 if (type
== xtRegisterTypeUnmapped
|| type
== xtRegisterTypeUnknown
)
797 if (group
== all_reggroup
)
799 if (group
== xtensa_ar_reggroup
)
800 return rg
& xtRegisterGroupAddrReg
;
801 if (group
== xtensa_user_reggroup
)
802 return rg
& xtRegisterGroupUser
;
803 if (group
== float_reggroup
)
804 return rg
& xtRegisterGroupFloat
;
805 if (group
== general_reggroup
)
806 return rg
& xtRegisterGroupGeneral
;
807 if (group
== system_reggroup
)
808 return rg
& xtRegisterGroupState
;
809 if (group
== vector_reggroup
|| group
== xtensa_vectra_reggroup
)
810 return rg
& xtRegisterGroupVectra
;
811 if (group
== restore_reggroup
)
812 return (regnum
< gdbarch_num_regs (gdbarch
)
813 && (reg
->flags
& SAVE_REST_FLAGS
) == SAVE_REST_VALID
);
814 cp_number
= xtensa_coprocessor_register_group (group
);
816 return rg
& (xtRegisterGroupCP0
<< cp_number
);
822 /* Supply register REGNUM from the buffer specified by GREGS and LEN
823 in the general-purpose register set REGSET to register cache
824 REGCACHE. If REGNUM is -1 do this for all registers in REGSET. */
827 xtensa_supply_gregset (const struct regset
*regset
,
833 const xtensa_elf_gregset_t
*regs
= (const xtensa_elf_gregset_t
*) gregs
;
834 struct gdbarch
*gdbarch
= rc
->arch ();
835 xtensa_gdbarch_tdep
*tdep
= (xtensa_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
838 DEBUGTRACE ("xtensa_supply_gregset (..., regnum==%d, ...)\n", regnum
);
840 if (regnum
== gdbarch_pc_regnum (gdbarch
) || regnum
== -1)
841 rc
->raw_supply (gdbarch_pc_regnum (gdbarch
), (char *) ®s
->pc
);
842 if (regnum
== gdbarch_ps_regnum (gdbarch
) || regnum
== -1)
843 rc
->raw_supply (gdbarch_ps_regnum (gdbarch
), (char *) ®s
->ps
);
844 if (regnum
== tdep
->wb_regnum
|| regnum
== -1)
845 rc
->raw_supply (tdep
->wb_regnum
,
846 (char *) ®s
->windowbase
);
847 if (regnum
== tdep
->ws_regnum
|| regnum
== -1)
848 rc
->raw_supply (tdep
->ws_regnum
,
849 (char *) ®s
->windowstart
);
850 if (regnum
== tdep
->lbeg_regnum
|| regnum
== -1)
851 rc
->raw_supply (tdep
->lbeg_regnum
,
852 (char *) ®s
->lbeg
);
853 if (regnum
== tdep
->lend_regnum
|| regnum
== -1)
854 rc
->raw_supply (tdep
->lend_regnum
,
855 (char *) ®s
->lend
);
856 if (regnum
== tdep
->lcount_regnum
|| regnum
== -1)
857 rc
->raw_supply (tdep
->lcount_regnum
,
858 (char *) ®s
->lcount
);
859 if (regnum
== tdep
->sar_regnum
|| regnum
== -1)
860 rc
->raw_supply (tdep
->sar_regnum
,
861 (char *) ®s
->sar
);
862 if (regnum
>=tdep
->ar_base
863 && regnum
< tdep
->ar_base
866 (regnum
, (char *) ®s
->ar
[regnum
- tdep
->ar_base
]);
867 else if (regnum
== -1)
869 for (i
= 0; i
< tdep
->num_aregs
; ++i
)
870 rc
->raw_supply (tdep
->ar_base
+ i
,
871 (char *) ®s
->ar
[i
]);
876 /* Xtensa register set. */
882 xtensa_supply_gregset
886 /* Iterate over supported core file register note sections. */
889 xtensa_iterate_over_regset_sections (struct gdbarch
*gdbarch
,
890 iterate_over_regset_sections_cb
*cb
,
892 const struct regcache
*regcache
)
894 DEBUGTRACE ("xtensa_iterate_over_regset_sections\n");
896 cb (".reg", sizeof (xtensa_elf_gregset_t
), sizeof (xtensa_elf_gregset_t
),
897 &xtensa_gregset
, NULL
, cb_data
);
901 /* Handling frames. */
903 /* Number of registers to save in case of Windowed ABI. */
904 #define XTENSA_NUM_SAVED_AREGS 12
906 /* Frame cache part for Windowed ABI. */
907 typedef struct xtensa_windowed_frame_cache
909 int wb
; /* WINDOWBASE of the previous frame. */
910 int callsize
; /* Call size of this frame. */
911 int ws
; /* WINDOWSTART of the previous frame. It keeps track of
912 life windows only. If there is no bit set for the
913 window, that means it had been already spilled
914 because of window overflow. */
916 /* Addresses of spilled A-registers.
917 AREGS[i] == -1, if corresponding AR is alive. */
918 CORE_ADDR aregs
[XTENSA_NUM_SAVED_AREGS
];
919 } xtensa_windowed_frame_cache_t
;
921 /* Call0 ABI Definitions. */
923 #define C0_MAXOPDS 3 /* Maximum number of operands for prologue
925 #define C0_CLESV 12 /* Callee-saved registers are here and up. */
926 #define C0_SP 1 /* Register used as SP. */
927 #define C0_FP 15 /* Register used as FP. */
928 #define C0_RA 0 /* Register used as return address. */
929 #define C0_ARGS 2 /* Register used as first arg/retval. */
930 #define C0_NARGS 6 /* Number of A-regs for args/retvals. */
932 /* Each element of xtensa_call0_frame_cache.c0_rt[] describes for each
933 A-register where the current content of the reg came from (in terms
934 of an original reg and a constant). Negative values of c0_rt[n].fp_reg
935 mean that the original content of the register was saved to the stack.
936 c0_rt[n].fr.ofs is NOT the offset from the frame base because we don't
937 know where SP will end up until the entire prologue has been analyzed. */
939 #define C0_CONST -1 /* fr_reg value if register contains a constant. */
940 #define C0_INEXP -2 /* fr_reg value if inexpressible as reg + offset. */
941 #define C0_NOSTK -1 /* to_stk value if register has not been stored. */
943 extern xtensa_isa xtensa_default_isa
;
945 typedef struct xtensa_c0reg
947 int fr_reg
; /* original register from which register content
948 is derived, or C0_CONST, or C0_INEXP. */
949 int fr_ofs
; /* constant offset from reg, or immediate value. */
950 int to_stk
; /* offset from original SP to register (4-byte aligned),
951 or C0_NOSTK if register has not been saved. */
954 /* Frame cache part for Call0 ABI. */
955 typedef struct xtensa_call0_frame_cache
957 int c0_frmsz
; /* Stack frame size. */
958 int c0_hasfp
; /* Current frame uses frame pointer. */
959 int fp_regnum
; /* A-register used as FP. */
960 int c0_fp
; /* Actual value of frame pointer. */
961 int c0_fpalign
; /* Dynamic adjustment for the stack
962 pointer. It's an AND mask. Zero,
963 if alignment was not adjusted. */
964 int c0_old_sp
; /* In case of dynamic adjustment, it is
965 a register holding unaligned sp.
966 C0_INEXP, when undefined. */
967 int c0_sp_ofs
; /* If "c0_old_sp" was spilled it's a
968 stack offset. C0_NOSTK otherwise. */
970 xtensa_c0reg_t c0_rt
[C0_NREGS
]; /* Register tracking information. */
971 } xtensa_call0_frame_cache_t
;
973 typedef struct xtensa_frame_cache
975 CORE_ADDR base
; /* Stack pointer of this frame. */
976 CORE_ADDR pc
; /* PC of this frame at the function entry point. */
977 CORE_ADDR ra
; /* The raw return address of this frame. */
978 CORE_ADDR ps
; /* The PS register of the previous (older) frame. */
979 CORE_ADDR prev_sp
; /* Stack Pointer of the previous (older) frame. */
980 int call0
; /* It's a call0 framework (else windowed). */
983 xtensa_windowed_frame_cache_t wd
; /* call0 == false. */
984 xtensa_call0_frame_cache_t c0
; /* call0 == true. */
986 } xtensa_frame_cache_t
;
989 static struct xtensa_frame_cache
*
990 xtensa_alloc_frame_cache (int windowed
)
992 xtensa_frame_cache_t
*cache
;
995 DEBUGTRACE ("xtensa_alloc_frame_cache ()\n");
997 cache
= FRAME_OBSTACK_ZALLOC (xtensa_frame_cache_t
);
1004 cache
->call0
= !windowed
;
1007 cache
->c0
.c0_frmsz
= -1;
1008 cache
->c0
.c0_hasfp
= 0;
1009 cache
->c0
.fp_regnum
= -1;
1010 cache
->c0
.c0_fp
= -1;
1011 cache
->c0
.c0_fpalign
= 0;
1012 cache
->c0
.c0_old_sp
= C0_INEXP
;
1013 cache
->c0
.c0_sp_ofs
= C0_NOSTK
;
1015 for (i
= 0; i
< C0_NREGS
; i
++)
1017 cache
->c0
.c0_rt
[i
].fr_reg
= i
;
1018 cache
->c0
.c0_rt
[i
].fr_ofs
= 0;
1019 cache
->c0
.c0_rt
[i
].to_stk
= C0_NOSTK
;
1026 cache
->wd
.callsize
= -1;
1028 for (i
= 0; i
< XTENSA_NUM_SAVED_AREGS
; i
++)
1029 cache
->wd
.aregs
[i
] = -1;
1036 xtensa_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR address
)
1038 return address
& ~15;
1043 xtensa_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1048 DEBUGTRACE ("xtensa_unwind_pc (next_frame = %s)\n",
1049 host_address_to_string (next_frame
));
1051 frame_unwind_register (next_frame
, gdbarch_pc_regnum (gdbarch
), buf
);
1052 pc
= extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
1054 DEBUGINFO ("[xtensa_unwind_pc] pc = 0x%08x\n", (unsigned int) pc
);
1060 static struct frame_id
1061 xtensa_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1064 xtensa_gdbarch_tdep
*tdep
= (xtensa_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
1066 /* THIS-FRAME is a dummy frame. Return a frame ID of that frame. */
1068 pc
= get_frame_pc (this_frame
);
1069 fp
= get_frame_register_unsigned
1070 (this_frame
, tdep
->a0_base
+ 1);
1072 /* Make dummy frame ID unique by adding a constant. */
1073 return frame_id_build (fp
+ SP_ALIGNMENT
, pc
);
1076 /* Returns true, if instruction to execute next is unique to Xtensa Window
1077 Interrupt Handlers. It can only be one of L32E, S32E, RFWO, or RFWU. */
1080 xtensa_window_interrupt_insn (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1082 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1083 unsigned int insn
= read_memory_integer (pc
, 4, byte_order
);
1086 if (byte_order
== BFD_ENDIAN_BIG
)
1088 /* Check, if this is L32E or S32E. */
1089 code
= insn
& 0xf000ff00;
1090 if ((code
== 0x00009000) || (code
== 0x00009400))
1092 /* Check, if this is RFWU or RFWO. */
1093 code
= insn
& 0xffffff00;
1094 return ((code
== 0x00430000) || (code
== 0x00530000));
1098 /* Check, if this is L32E or S32E. */
1099 code
= insn
& 0x00ff000f;
1100 if ((code
== 0x090000) || (code
== 0x490000))
1102 /* Check, if this is RFWU or RFWO. */
1103 code
= insn
& 0x00ffffff;
1104 return ((code
== 0x00003400) || (code
== 0x00003500));
1108 /* Returns the best guess about which register is a frame pointer
1109 for the function containing CURRENT_PC. */
1111 #define XTENSA_ISA_BSZ 32 /* Instruction buffer size. */
1112 #define XTENSA_ISA_BADPC ((CORE_ADDR)0) /* Bad PC value. */
1115 xtensa_scan_prologue (struct gdbarch
*gdbarch
, CORE_ADDR current_pc
)
1117 #define RETURN_FP goto done
1119 xtensa_gdbarch_tdep
*tdep
= (xtensa_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
1120 unsigned int fp_regnum
= tdep
->a0_base
+ 1;
1121 CORE_ADDR start_addr
;
1123 xtensa_insnbuf ins
, slot
;
1124 gdb_byte ibuf
[XTENSA_ISA_BSZ
];
1125 CORE_ADDR ia
, bt
, ba
;
1127 int ilen
, islots
, is
;
1129 const char *opcname
;
1131 find_pc_partial_function (current_pc
, NULL
, &start_addr
, NULL
);
1132 if (start_addr
== 0)
1135 isa
= xtensa_default_isa
;
1136 gdb_assert (XTENSA_ISA_BSZ
>= xtensa_isa_maxlength (isa
));
1137 ins
= xtensa_insnbuf_alloc (isa
);
1138 slot
= xtensa_insnbuf_alloc (isa
);
1141 for (ia
= start_addr
, bt
= ia
; ia
< current_pc
; ia
+= ilen
)
1143 if (ia
+ xtensa_isa_maxlength (isa
) > bt
)
1146 bt
= (ba
+ XTENSA_ISA_BSZ
) < current_pc
1147 ? ba
+ XTENSA_ISA_BSZ
: current_pc
;
1148 if (target_read_memory (ba
, ibuf
, bt
- ba
) != 0)
1152 xtensa_insnbuf_from_chars (isa
, ins
, &ibuf
[ia
-ba
], 0);
1153 ifmt
= xtensa_format_decode (isa
, ins
);
1154 if (ifmt
== XTENSA_UNDEFINED
)
1156 ilen
= xtensa_format_length (isa
, ifmt
);
1157 if (ilen
== XTENSA_UNDEFINED
)
1159 islots
= xtensa_format_num_slots (isa
, ifmt
);
1160 if (islots
== XTENSA_UNDEFINED
)
1163 for (is
= 0; is
< islots
; ++is
)
1165 if (xtensa_format_get_slot (isa
, ifmt
, is
, ins
, slot
))
1168 opc
= xtensa_opcode_decode (isa
, ifmt
, is
, slot
);
1169 if (opc
== XTENSA_UNDEFINED
)
1172 opcname
= xtensa_opcode_name (isa
, opc
);
1174 if (strcasecmp (opcname
, "mov.n") == 0
1175 || strcasecmp (opcname
, "or") == 0)
1177 unsigned int register_operand
;
1179 /* Possible candidate for setting frame pointer
1180 from A1. This is what we are looking for. */
1182 if (xtensa_operand_get_field (isa
, opc
, 1, ifmt
,
1183 is
, slot
, ®ister_operand
) != 0)
1185 if (xtensa_operand_decode (isa
, opc
, 1, ®ister_operand
) != 0)
1187 if (register_operand
== 1) /* Mov{.n} FP A1. */
1189 if (xtensa_operand_get_field (isa
, opc
, 0, ifmt
, is
, slot
,
1190 ®ister_operand
) != 0)
1192 if (xtensa_operand_decode (isa
, opc
, 0,
1193 ®ister_operand
) != 0)
1197 = tdep
->a0_base
+ register_operand
;
1203 /* We have problems decoding the memory. */
1205 || strcasecmp (opcname
, "ill") == 0
1206 || strcasecmp (opcname
, "ill.n") == 0
1207 /* Hit planted breakpoint. */
1208 || strcasecmp (opcname
, "break") == 0
1209 || strcasecmp (opcname
, "break.n") == 0
1210 /* Flow control instructions finish prologue. */
1211 || xtensa_opcode_is_branch (isa
, opc
) > 0
1212 || xtensa_opcode_is_jump (isa
, opc
) > 0
1213 || xtensa_opcode_is_loop (isa
, opc
) > 0
1214 || xtensa_opcode_is_call (isa
, opc
) > 0
1215 || strcasecmp (opcname
, "simcall") == 0
1216 || strcasecmp (opcname
, "syscall") == 0)
1217 /* Can not continue analysis. */
1222 xtensa_insnbuf_free(isa
, slot
);
1223 xtensa_insnbuf_free(isa
, ins
);
1227 /* The key values to identify the frame using "cache" are
1229 cache->base = SP (or best guess about FP) of this frame;
1230 cache->pc = entry-PC (entry point of the frame function);
1231 cache->prev_sp = SP of the previous frame. */
1234 call0_frame_cache (struct frame_info
*this_frame
,
1235 xtensa_frame_cache_t
*cache
, CORE_ADDR pc
);
1238 xtensa_window_interrupt_frame_cache (struct frame_info
*this_frame
,
1239 xtensa_frame_cache_t
*cache
,
1242 static struct xtensa_frame_cache
*
1243 xtensa_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1245 xtensa_frame_cache_t
*cache
;
1246 CORE_ADDR ra
, wb
, ws
, pc
, sp
, ps
;
1247 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1248 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1249 unsigned int fp_regnum
;
1250 int windowed
, ps_regnum
;
1253 return (struct xtensa_frame_cache
*) *this_cache
;
1255 pc
= get_frame_register_unsigned (this_frame
, gdbarch_pc_regnum (gdbarch
));
1256 ps_regnum
= gdbarch_ps_regnum (gdbarch
);
1257 ps
= (ps_regnum
>= 0
1258 ? get_frame_register_unsigned (this_frame
, ps_regnum
) : TX_PS
);
1260 windowed
= windowing_enabled (gdbarch
, ps
);
1262 /* Get pristine xtensa-frame. */
1263 cache
= xtensa_alloc_frame_cache (windowed
);
1264 *this_cache
= cache
;
1269 xtensa_gdbarch_tdep
*tdep
= (xtensa_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
1271 /* Get WINDOWBASE, WINDOWSTART, and PS registers. */
1272 wb
= get_frame_register_unsigned (this_frame
,
1274 ws
= get_frame_register_unsigned (this_frame
,
1277 if (safe_read_memory_integer (pc
, 1, byte_order
, &op1
)
1278 && XTENSA_IS_ENTRY (gdbarch
, op1
))
1280 int callinc
= CALLINC (ps
);
1281 ra
= get_frame_register_unsigned
1282 (this_frame
, tdep
->a0_base
+ callinc
* 4);
1284 /* ENTRY hasn't been executed yet, therefore callsize is still 0. */
1285 cache
->wd
.callsize
= 0;
1288 cache
->prev_sp
= get_frame_register_unsigned
1289 (this_frame
, tdep
->a0_base
+ 1);
1291 /* This only can be the outermost frame since we are
1292 just about to execute ENTRY. SP hasn't been set yet.
1293 We can assume any frame size, because it does not
1294 matter, and, let's fake frame base in cache. */
1295 cache
->base
= cache
->prev_sp
- 16;
1298 cache
->ra
= (cache
->pc
& 0xc0000000) | (ra
& 0x3fffffff);
1299 cache
->ps
= (ps
& ~PS_CALLINC_MASK
)
1300 | ((WINSIZE(ra
)/4) << PS_CALLINC_SHIFT
);
1306 fp_regnum
= xtensa_scan_prologue (gdbarch
, pc
);
1307 ra
= get_frame_register_unsigned (this_frame
,
1309 cache
->wd
.callsize
= WINSIZE (ra
);
1310 cache
->wd
.wb
= (wb
- cache
->wd
.callsize
/ 4)
1311 & (tdep
->num_aregs
/ 4 - 1);
1312 cache
->wd
.ws
= ws
& ~(1 << wb
);
1314 cache
->pc
= get_frame_func (this_frame
);
1315 cache
->ra
= (pc
& 0xc0000000) | (ra
& 0x3fffffff);
1316 cache
->ps
= (ps
& ~PS_CALLINC_MASK
)
1317 | ((WINSIZE(ra
)/4) << PS_CALLINC_SHIFT
);
1320 if (cache
->wd
.ws
== 0)
1325 sp
= get_frame_register_unsigned
1326 (this_frame
, tdep
->a0_base
+ 1) - 16;
1328 for (i
= 0; i
< 4; i
++, sp
+= 4)
1330 cache
->wd
.aregs
[i
] = sp
;
1333 if (cache
->wd
.callsize
> 4)
1335 /* Set A4...A7/A11. */
1336 /* Get the SP of the frame previous to the previous one.
1337 To achieve this, we have to dereference SP twice. */
1338 sp
= (CORE_ADDR
) read_memory_integer (sp
- 12, 4, byte_order
);
1339 sp
= (CORE_ADDR
) read_memory_integer (sp
- 12, 4, byte_order
);
1340 sp
-= cache
->wd
.callsize
* 4;
1342 for ( i
= 4; i
< cache
->wd
.callsize
; i
++, sp
+= 4)
1344 cache
->wd
.aregs
[i
] = sp
;
1349 if ((cache
->prev_sp
== 0) && ( ra
!= 0 ))
1350 /* If RA is equal to 0 this frame is an outermost frame. Leave
1351 cache->prev_sp unchanged marking the boundary of the frame stack. */
1353 if ((cache
->wd
.ws
& (1 << cache
->wd
.wb
)) == 0)
1355 /* Register window overflow already happened.
1356 We can read caller's SP from the proper spill location. */
1357 sp
= get_frame_register_unsigned
1358 (this_frame
, tdep
->a0_base
+ 1);
1359 cache
->prev_sp
= read_memory_integer (sp
- 12, 4, byte_order
);
1363 /* Read caller's frame SP directly from the previous window. */
1364 int regnum
= arreg_number
1365 (gdbarch
, tdep
->a0_base
+ 1,
1368 cache
->prev_sp
= xtensa_read_register (regnum
);
1372 else if (xtensa_window_interrupt_insn (gdbarch
, pc
))
1374 /* Execution stopped inside Xtensa Window Interrupt Handler. */
1376 xtensa_window_interrupt_frame_cache (this_frame
, cache
, pc
);
1377 /* Everything was set already, including cache->base. */
1380 else /* Call0 framework. */
1382 call0_frame_cache (this_frame
, cache
, pc
);
1383 fp_regnum
= cache
->c0
.fp_regnum
;
1386 cache
->base
= get_frame_register_unsigned (this_frame
, fp_regnum
);
1391 static int xtensa_session_once_reported
= 1;
1393 /* Report a problem with prologue analysis while doing backtracing.
1394 But, do it only once to avoid annoying repeated messages. */
1399 if (xtensa_session_once_reported
== 0)
1401 \nUnrecognised function prologue. Stack trace cannot be resolved. \
1402 This message will not be repeated in this session.\n"));
1404 xtensa_session_once_reported
= 1;
1409 xtensa_frame_this_id (struct frame_info
*this_frame
,
1411 struct frame_id
*this_id
)
1413 struct xtensa_frame_cache
*cache
=
1414 xtensa_frame_cache (this_frame
, this_cache
);
1416 if (cache
->prev_sp
== 0)
1419 (*this_id
) = frame_id_build (cache
->prev_sp
, cache
->pc
);
1422 static struct value
*
1423 xtensa_frame_prev_register (struct frame_info
*this_frame
,
1427 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1428 struct xtensa_frame_cache
*cache
;
1429 ULONGEST saved_reg
= 0;
1431 xtensa_gdbarch_tdep
*tdep
= (xtensa_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
1433 if (*this_cache
== NULL
)
1434 *this_cache
= xtensa_frame_cache (this_frame
, this_cache
);
1435 cache
= (struct xtensa_frame_cache
*) *this_cache
;
1437 if (regnum
==gdbarch_pc_regnum (gdbarch
))
1438 saved_reg
= cache
->ra
;
1439 else if (regnum
== tdep
->a0_base
+ 1)
1440 saved_reg
= cache
->prev_sp
;
1441 else if (!cache
->call0
)
1443 if (regnum
== tdep
->ws_regnum
)
1444 saved_reg
= cache
->wd
.ws
;
1445 else if (regnum
== tdep
->wb_regnum
)
1446 saved_reg
= cache
->wd
.wb
;
1447 else if (regnum
== gdbarch_ps_regnum (gdbarch
))
1448 saved_reg
= cache
->ps
;
1456 return frame_unwind_got_constant (this_frame
, regnum
, saved_reg
);
1458 if (!cache
->call0
) /* Windowed ABI. */
1460 /* Convert A-register numbers to AR-register numbers,
1461 if we deal with A-register. */
1462 if (regnum
>= tdep
->a0_base
1463 && regnum
<= tdep
->a0_base
+ 15)
1464 regnum
= arreg_number (gdbarch
, regnum
, cache
->wd
.wb
);
1466 /* Check, if we deal with AR-register saved on stack. */
1467 if (regnum
>= tdep
->ar_base
1468 && regnum
<= (tdep
->ar_base
1471 int areg
= areg_number (gdbarch
, regnum
, cache
->wd
.wb
);
1474 && areg
< XTENSA_NUM_SAVED_AREGS
1475 && cache
->wd
.aregs
[areg
] != -1)
1476 return frame_unwind_got_memory (this_frame
, regnum
,
1477 cache
->wd
.aregs
[areg
]);
1480 else /* Call0 ABI. */
1482 int reg
= (regnum
>= tdep
->ar_base
1483 && regnum
<= (tdep
->ar_base
1485 ? regnum
- tdep
->ar_base
: regnum
;
1492 /* If register was saved in the prologue, retrieve it. */
1493 stkofs
= cache
->c0
.c0_rt
[reg
].to_stk
;
1494 if (stkofs
!= C0_NOSTK
)
1496 /* Determine SP on entry based on FP. */
1497 spe
= cache
->c0
.c0_fp
1498 - cache
->c0
.c0_rt
[cache
->c0
.fp_regnum
].fr_ofs
;
1500 return frame_unwind_got_memory (this_frame
, regnum
,
1506 /* All other registers have been either saved to
1507 the stack or are still alive in the processor. */
1509 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
1513 static const struct frame_unwind
1518 default_frame_unwind_stop_reason
,
1519 xtensa_frame_this_id
,
1520 xtensa_frame_prev_register
,
1522 default_frame_sniffer
1526 xtensa_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
1528 struct xtensa_frame_cache
*cache
=
1529 xtensa_frame_cache (this_frame
, this_cache
);
1534 static const struct frame_base
1538 xtensa_frame_base_address
,
1539 xtensa_frame_base_address
,
1540 xtensa_frame_base_address
1545 xtensa_extract_return_value (struct type
*type
,
1546 struct regcache
*regcache
,
1549 struct gdbarch
*gdbarch
= regcache
->arch ();
1550 bfd_byte
*valbuf
= (bfd_byte
*) dst
;
1551 int len
= TYPE_LENGTH (type
);
1556 DEBUGTRACE ("xtensa_extract_return_value (...)\n");
1558 gdb_assert(len
> 0);
1560 xtensa_gdbarch_tdep
*tdep
= (xtensa_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
1561 if (tdep
->call_abi
!= CallAbiCall0Only
)
1563 /* First, we have to find the caller window in the register file. */
1564 regcache_raw_read_unsigned (regcache
, gdbarch_pc_regnum (gdbarch
), &pc
);
1565 callsize
= extract_call_winsize (gdbarch
, pc
);
1567 /* On Xtensa, we can return up to 4 words (or 2 for call12). */
1568 if (len
> (callsize
> 8 ? 8 : 16))
1569 internal_error (__FILE__
, __LINE__
,
1570 _("cannot extract return value of %d bytes long"),
1573 /* Get the register offset of the return
1574 register (A2) in the caller window. */
1575 regcache_raw_read_unsigned
1576 (regcache
, tdep
->wb_regnum
, &wb
);
1577 areg
= arreg_number (gdbarch
,
1578 tdep
->a0_base
+ 2 + callsize
, wb
);
1582 /* No windowing hardware - Call0 ABI. */
1583 areg
= tdep
->a0_base
+ C0_ARGS
;
1586 DEBUGINFO ("[xtensa_extract_return_value] areg %d len %d\n", areg
, len
);
1588 if (len
< 4 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1591 for (; len
> 0; len
-= 4, areg
++, valbuf
+= 4)
1594 regcache
->raw_read_part (areg
, offset
, len
, valbuf
);
1596 regcache
->raw_read (areg
, valbuf
);
1602 xtensa_store_return_value (struct type
*type
,
1603 struct regcache
*regcache
,
1606 struct gdbarch
*gdbarch
= regcache
->arch ();
1607 const bfd_byte
*valbuf
= (const bfd_byte
*) dst
;
1611 int len
= TYPE_LENGTH (type
);
1614 DEBUGTRACE ("xtensa_store_return_value (...)\n");
1616 xtensa_gdbarch_tdep
*tdep
= (xtensa_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
1617 if (tdep
->call_abi
!= CallAbiCall0Only
)
1619 regcache_raw_read_unsigned
1620 (regcache
, tdep
->wb_regnum
, &wb
);
1621 regcache_raw_read_unsigned (regcache
, gdbarch_pc_regnum (gdbarch
), &pc
);
1622 callsize
= extract_call_winsize (gdbarch
, pc
);
1624 if (len
> (callsize
> 8 ? 8 : 16))
1625 internal_error (__FILE__
, __LINE__
,
1626 _("unimplemented for this length: %s"),
1627 pulongest (TYPE_LENGTH (type
)));
1628 areg
= arreg_number (gdbarch
,
1629 tdep
->a0_base
+ 2 + callsize
, wb
);
1631 DEBUGTRACE ("[xtensa_store_return_value] callsize %d wb %d\n",
1632 callsize
, (int) wb
);
1636 areg
= tdep
->a0_base
+ C0_ARGS
;
1639 if (len
< 4 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1642 for (; len
> 0; len
-= 4, areg
++, valbuf
+= 4)
1645 regcache
->raw_write_part (areg
, offset
, len
, valbuf
);
1647 regcache
->raw_write (areg
, valbuf
);
1652 static enum return_value_convention
1653 xtensa_return_value (struct gdbarch
*gdbarch
,
1654 struct value
*function
,
1655 struct type
*valtype
,
1656 struct regcache
*regcache
,
1658 const gdb_byte
*writebuf
)
1660 /* Structures up to 16 bytes are returned in registers. */
1662 int struct_return
= ((valtype
->code () == TYPE_CODE_STRUCT
1663 || valtype
->code () == TYPE_CODE_UNION
1664 || valtype
->code () == TYPE_CODE_ARRAY
)
1665 && TYPE_LENGTH (valtype
) > 16);
1668 return RETURN_VALUE_STRUCT_CONVENTION
;
1670 DEBUGTRACE ("xtensa_return_value(...)\n");
1672 if (writebuf
!= NULL
)
1674 xtensa_store_return_value (valtype
, regcache
, writebuf
);
1677 if (readbuf
!= NULL
)
1679 gdb_assert (!struct_return
);
1680 xtensa_extract_return_value (valtype
, regcache
, readbuf
);
1682 return RETURN_VALUE_REGISTER_CONVENTION
;
1689 xtensa_push_dummy_call (struct gdbarch
*gdbarch
,
1690 struct value
*function
,
1691 struct regcache
*regcache
,
1694 struct value
**args
,
1696 function_call_return_method return_method
,
1697 CORE_ADDR struct_addr
)
1699 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1700 xtensa_gdbarch_tdep
*tdep
= (xtensa_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
1701 int size
, onstack_size
;
1702 gdb_byte
*buf
= (gdb_byte
*) alloca (16);
1704 struct argument_info
1706 const bfd_byte
*contents
;
1708 int onstack
; /* onstack == 0 => in reg */
1709 int align
; /* alignment */
1712 int offset
; /* stack offset if on stack. */
1713 int regno
; /* regno if in register. */
1717 struct argument_info
*arg_info
=
1718 (struct argument_info
*) alloca (nargs
* sizeof (struct argument_info
));
1722 DEBUGTRACE ("xtensa_push_dummy_call (...)\n");
1724 if (xtensa_debug_level
> 3)
1726 DEBUGINFO ("[xtensa_push_dummy_call] nargs = %d\n", nargs
);
1727 DEBUGINFO ("[xtensa_push_dummy_call] sp=0x%x, return_method=%d, "
1728 "struct_addr=0x%x\n",
1729 (int) sp
, (int) return_method
, (int) struct_addr
);
1731 for (int i
= 0; i
< nargs
; i
++)
1733 struct value
*arg
= args
[i
];
1734 struct type
*arg_type
= check_typedef (value_type (arg
));
1735 fprintf_unfiltered (gdb_stdlog
, "%2d: %s %3s ", i
,
1736 host_address_to_string (arg
),
1737 pulongest (TYPE_LENGTH (arg_type
)));
1738 switch (arg_type
->code ())
1741 fprintf_unfiltered (gdb_stdlog
, "int");
1743 case TYPE_CODE_STRUCT
:
1744 fprintf_unfiltered (gdb_stdlog
, "struct");
1747 fprintf_unfiltered (gdb_stdlog
, "%3d", arg_type
->code ());
1750 fprintf_unfiltered (gdb_stdlog
, " %s\n",
1751 host_address_to_string (value_contents (arg
).data ()));
1755 /* First loop: collect information.
1756 Cast into type_long. (This shouldn't happen often for C because
1757 GDB already does this earlier.) It's possible that GDB could
1758 do it all the time but it's harmless to leave this code here. */
1763 if (return_method
== return_method_struct
)
1764 size
= REGISTER_SIZE
;
1766 for (int i
= 0; i
< nargs
; i
++)
1768 struct argument_info
*info
= &arg_info
[i
];
1769 struct value
*arg
= args
[i
];
1770 struct type
*arg_type
= check_typedef (value_type (arg
));
1772 switch (arg_type
->code ())
1775 case TYPE_CODE_BOOL
:
1776 case TYPE_CODE_CHAR
:
1777 case TYPE_CODE_RANGE
:
1778 case TYPE_CODE_ENUM
:
1780 /* Cast argument to long if necessary as the mask does it too. */
1781 if (TYPE_LENGTH (arg_type
)
1782 < TYPE_LENGTH (builtin_type (gdbarch
)->builtin_long
))
1784 arg_type
= builtin_type (gdbarch
)->builtin_long
;
1785 arg
= value_cast (arg_type
, arg
);
1787 /* Aligment is equal to the type length for the basic types. */
1788 info
->align
= TYPE_LENGTH (arg_type
);
1793 /* Align doubles correctly. */
1794 if (TYPE_LENGTH (arg_type
)
1795 == TYPE_LENGTH (builtin_type (gdbarch
)->builtin_double
))
1796 info
->align
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_double
);
1798 info
->align
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_long
);
1801 case TYPE_CODE_STRUCT
:
1803 info
->align
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_long
);
1806 info
->length
= TYPE_LENGTH (arg_type
);
1807 info
->contents
= value_contents (arg
).data ();
1809 /* Align size and onstack_size. */
1810 size
= (size
+ info
->align
- 1) & ~(info
->align
- 1);
1811 onstack_size
= (onstack_size
+ info
->align
- 1) & ~(info
->align
- 1);
1813 if (size
+ info
->length
> REGISTER_SIZE
* ARG_NOF (tdep
))
1816 info
->u
.offset
= onstack_size
;
1817 onstack_size
+= info
->length
;
1822 info
->u
.regno
= ARG_1ST (tdep
) + size
/ REGISTER_SIZE
;
1824 size
+= info
->length
;
1827 /* Adjust the stack pointer and align it. */
1828 sp
= align_down (sp
- onstack_size
, SP_ALIGNMENT
);
1830 /* Simulate MOVSP, if Windowed ABI. */
1831 if ((tdep
->call_abi
!= CallAbiCall0Only
)
1834 read_memory (osp
- 16, buf
, 16);
1835 write_memory (sp
- 16, buf
, 16);
1838 /* Second Loop: Load arguments. */
1840 if (return_method
== return_method_struct
)
1842 store_unsigned_integer (buf
, REGISTER_SIZE
, byte_order
, struct_addr
);
1843 regcache
->cooked_write (ARG_1ST (tdep
), buf
);
1846 for (int i
= 0; i
< nargs
; i
++)
1848 struct argument_info
*info
= &arg_info
[i
];
1852 int n
= info
->length
;
1853 CORE_ADDR offset
= sp
+ info
->u
.offset
;
1855 /* Odd-sized structs are aligned to the lower side of a memory
1856 word in big-endian mode and require a shift. This only
1857 applies for structures smaller than one word. */
1859 if (n
< REGISTER_SIZE
1860 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1861 offset
+= (REGISTER_SIZE
- n
);
1863 write_memory (offset
, info
->contents
, info
->length
);
1868 int n
= info
->length
;
1869 const bfd_byte
*cp
= info
->contents
;
1870 int r
= info
->u
.regno
;
1872 /* Odd-sized structs are aligned to the lower side of registers in
1873 big-endian mode and require a shift. The odd-sized leftover will
1874 be at the end. Note that this is only true for structures smaller
1875 than REGISTER_SIZE; for larger odd-sized structures the excess
1876 will be left-aligned in the register on both endiannesses. */
1878 if (n
< REGISTER_SIZE
&& byte_order
== BFD_ENDIAN_BIG
)
1881 v
= extract_unsigned_integer (cp
, REGISTER_SIZE
, byte_order
);
1882 v
= v
>> ((REGISTER_SIZE
- n
) * TARGET_CHAR_BIT
);
1884 store_unsigned_integer (buf
, REGISTER_SIZE
, byte_order
, v
);
1885 regcache
->cooked_write (r
, buf
);
1887 cp
+= REGISTER_SIZE
;
1894 regcache
->cooked_write (r
, cp
);
1896 cp
+= REGISTER_SIZE
;
1903 /* Set the return address of dummy frame to the dummy address.
1904 The return address for the current function (in A0) is
1905 saved in the dummy frame, so we can safely overwrite A0 here. */
1907 if (tdep
->call_abi
!= CallAbiCall0Only
)
1911 ra
= (bp_addr
& 0x3fffffff) | 0x40000000;
1912 regcache_raw_read_unsigned (regcache
, gdbarch_ps_regnum (gdbarch
), &val
);
1913 ps
= (unsigned long) val
& ~0x00030000;
1914 regcache_cooked_write_unsigned
1915 (regcache
, tdep
->a0_base
+ 4, ra
);
1916 regcache_cooked_write_unsigned (regcache
,
1917 gdbarch_ps_regnum (gdbarch
),
1920 /* All the registers have been saved. After executing
1921 dummy call, they all will be restored. So it's safe
1922 to modify WINDOWSTART register to make it look like there
1923 is only one register window corresponding to WINDOWEBASE. */
1925 regcache
->raw_read (tdep
->wb_regnum
, buf
);
1926 regcache_cooked_write_unsigned
1927 (regcache
, tdep
->ws_regnum
,
1928 1 << extract_unsigned_integer (buf
, 4, byte_order
));
1932 /* Simulate CALL0: write RA into A0 register. */
1933 regcache_cooked_write_unsigned
1934 (regcache
, tdep
->a0_base
, bp_addr
);
1937 /* Set new stack pointer and return it. */
1938 regcache_cooked_write_unsigned (regcache
,
1939 tdep
->a0_base
+ 1, sp
);
1940 /* Make dummy frame ID unique by adding a constant. */
1941 return sp
+ SP_ALIGNMENT
;
1944 /* Implement the breakpoint_kind_from_pc gdbarch method. */
1947 xtensa_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
1949 xtensa_gdbarch_tdep
*tdep
= (xtensa_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
1951 if (tdep
->isa_use_density_instructions
)
1957 /* Return a breakpoint for the current location of PC. We always use
1958 the density version if we have density instructions (regardless of the
1959 current instruction at PC), and use regular instructions otherwise. */
1961 #define BIG_BREAKPOINT { 0x00, 0x04, 0x00 }
1962 #define LITTLE_BREAKPOINT { 0x00, 0x40, 0x00 }
1963 #define DENSITY_BIG_BREAKPOINT { 0xd2, 0x0f }
1964 #define DENSITY_LITTLE_BREAKPOINT { 0x2d, 0xf0 }
1966 /* Implement the sw_breakpoint_from_kind gdbarch method. */
1968 static const gdb_byte
*
1969 xtensa_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
1975 static unsigned char big_breakpoint
[] = BIG_BREAKPOINT
;
1976 static unsigned char little_breakpoint
[] = LITTLE_BREAKPOINT
;
1978 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1979 return big_breakpoint
;
1981 return little_breakpoint
;
1985 static unsigned char density_big_breakpoint
[] = DENSITY_BIG_BREAKPOINT
;
1986 static unsigned char density_little_breakpoint
[]
1987 = DENSITY_LITTLE_BREAKPOINT
;
1989 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1990 return density_big_breakpoint
;
1992 return density_little_breakpoint
;
1996 /* Call0 ABI support routines. */
1998 /* Return true, if PC points to "ret" or "ret.n". */
2001 call0_ret (CORE_ADDR start_pc
, CORE_ADDR finish_pc
)
2003 #define RETURN_RET goto done
2005 xtensa_insnbuf ins
, slot
;
2006 gdb_byte ibuf
[XTENSA_ISA_BSZ
];
2007 CORE_ADDR ia
, bt
, ba
;
2009 int ilen
, islots
, is
;
2011 const char *opcname
;
2014 isa
= xtensa_default_isa
;
2015 gdb_assert (XTENSA_ISA_BSZ
>= xtensa_isa_maxlength (isa
));
2016 ins
= xtensa_insnbuf_alloc (isa
);
2017 slot
= xtensa_insnbuf_alloc (isa
);
2020 for (ia
= start_pc
, bt
= ia
; ia
< finish_pc
; ia
+= ilen
)
2022 if (ia
+ xtensa_isa_maxlength (isa
) > bt
)
2025 bt
= (ba
+ XTENSA_ISA_BSZ
) < finish_pc
2026 ? ba
+ XTENSA_ISA_BSZ
: finish_pc
;
2027 if (target_read_memory (ba
, ibuf
, bt
- ba
) != 0 )
2031 xtensa_insnbuf_from_chars (isa
, ins
, &ibuf
[ia
-ba
], 0);
2032 ifmt
= xtensa_format_decode (isa
, ins
);
2033 if (ifmt
== XTENSA_UNDEFINED
)
2035 ilen
= xtensa_format_length (isa
, ifmt
);
2036 if (ilen
== XTENSA_UNDEFINED
)
2038 islots
= xtensa_format_num_slots (isa
, ifmt
);
2039 if (islots
== XTENSA_UNDEFINED
)
2042 for (is
= 0; is
< islots
; ++is
)
2044 if (xtensa_format_get_slot (isa
, ifmt
, is
, ins
, slot
))
2047 opc
= xtensa_opcode_decode (isa
, ifmt
, is
, slot
);
2048 if (opc
== XTENSA_UNDEFINED
)
2051 opcname
= xtensa_opcode_name (isa
, opc
);
2053 if ((strcasecmp (opcname
, "ret.n") == 0)
2054 || (strcasecmp (opcname
, "ret") == 0))
2062 xtensa_insnbuf_free(isa
, slot
);
2063 xtensa_insnbuf_free(isa
, ins
);
2067 /* Call0 opcode class. Opcodes are preclassified according to what they
2068 mean for Call0 prologue analysis, and their number of significant operands.
2069 The purpose of this is to simplify prologue analysis by separating
2070 instruction decoding (libisa) from the semantics of prologue analysis. */
2074 c0opc_illegal
, /* Unknown to libisa (invalid) or 'ill' opcode. */
2075 c0opc_uninteresting
, /* Not interesting for Call0 prologue analysis. */
2076 c0opc_flow
, /* Flow control insn. */
2077 c0opc_entry
, /* ENTRY indicates non-Call0 prologue. */
2078 c0opc_break
, /* Debugger software breakpoints. */
2079 c0opc_add
, /* Adding two registers. */
2080 c0opc_addi
, /* Adding a register and an immediate. */
2081 c0opc_and
, /* Bitwise "and"-ing two registers. */
2082 c0opc_sub
, /* Subtracting a register from a register. */
2083 c0opc_mov
, /* Moving a register to a register. */
2084 c0opc_movi
, /* Moving an immediate to a register. */
2085 c0opc_l32r
, /* Loading a literal. */
2086 c0opc_s32i
, /* Storing word at fixed offset from a base register. */
2087 c0opc_rwxsr
, /* RSR, WRS, or XSR instructions. */
2088 c0opc_l32e
, /* L32E instruction. */
2089 c0opc_s32e
, /* S32E instruction. */
2090 c0opc_rfwo
, /* RFWO instruction. */
2091 c0opc_rfwu
, /* RFWU instruction. */
2092 c0opc_NrOf
/* Number of opcode classifications. */
2095 /* Return true, if OPCNAME is RSR, WRS, or XSR instruction. */
2098 rwx_special_register (const char *opcname
)
2100 char ch
= *opcname
++;
2102 if ((ch
!= 'r') && (ch
!= 'w') && (ch
!= 'x'))
2104 if (*opcname
++ != 's')
2106 if (*opcname
++ != 'r')
2108 if (*opcname
++ != '.')
2114 /* Classify an opcode based on what it means for Call0 prologue analysis. */
2116 static xtensa_insn_kind
2117 call0_classify_opcode (xtensa_isa isa
, xtensa_opcode opc
)
2119 const char *opcname
;
2120 xtensa_insn_kind opclass
= c0opc_uninteresting
;
2122 DEBUGTRACE ("call0_classify_opcode (..., opc = %d)\n", opc
);
2124 /* Get opcode name and handle special classifications. */
2126 opcname
= xtensa_opcode_name (isa
, opc
);
2129 || strcasecmp (opcname
, "ill") == 0
2130 || strcasecmp (opcname
, "ill.n") == 0)
2131 opclass
= c0opc_illegal
;
2132 else if (strcasecmp (opcname
, "break") == 0
2133 || strcasecmp (opcname
, "break.n") == 0)
2134 opclass
= c0opc_break
;
2135 else if (strcasecmp (opcname
, "entry") == 0)
2136 opclass
= c0opc_entry
;
2137 else if (strcasecmp (opcname
, "rfwo") == 0)
2138 opclass
= c0opc_rfwo
;
2139 else if (strcasecmp (opcname
, "rfwu") == 0)
2140 opclass
= c0opc_rfwu
;
2141 else if (xtensa_opcode_is_branch (isa
, opc
) > 0
2142 || xtensa_opcode_is_jump (isa
, opc
) > 0
2143 || xtensa_opcode_is_loop (isa
, opc
) > 0
2144 || xtensa_opcode_is_call (isa
, opc
) > 0
2145 || strcasecmp (opcname
, "simcall") == 0
2146 || strcasecmp (opcname
, "syscall") == 0)
2147 opclass
= c0opc_flow
;
2149 /* Also, classify specific opcodes that need to be tracked. */
2150 else if (strcasecmp (opcname
, "add") == 0
2151 || strcasecmp (opcname
, "add.n") == 0)
2152 opclass
= c0opc_add
;
2153 else if (strcasecmp (opcname
, "and") == 0)
2154 opclass
= c0opc_and
;
2155 else if (strcasecmp (opcname
, "addi") == 0
2156 || strcasecmp (opcname
, "addi.n") == 0
2157 || strcasecmp (opcname
, "addmi") == 0)
2158 opclass
= c0opc_addi
;
2159 else if (strcasecmp (opcname
, "sub") == 0)
2160 opclass
= c0opc_sub
;
2161 else if (strcasecmp (opcname
, "mov.n") == 0
2162 || strcasecmp (opcname
, "or") == 0) /* Could be 'mov' asm macro. */
2163 opclass
= c0opc_mov
;
2164 else if (strcasecmp (opcname
, "movi") == 0
2165 || strcasecmp (opcname
, "movi.n") == 0)
2166 opclass
= c0opc_movi
;
2167 else if (strcasecmp (opcname
, "l32r") == 0)
2168 opclass
= c0opc_l32r
;
2169 else if (strcasecmp (opcname
, "s32i") == 0
2170 || strcasecmp (opcname
, "s32i.n") == 0)
2171 opclass
= c0opc_s32i
;
2172 else if (strcasecmp (opcname
, "l32e") == 0)
2173 opclass
= c0opc_l32e
;
2174 else if (strcasecmp (opcname
, "s32e") == 0)
2175 opclass
= c0opc_s32e
;
2176 else if (rwx_special_register (opcname
))
2177 opclass
= c0opc_rwxsr
;
2182 /* Tracks register movement/mutation for a given operation, which may
2183 be within a bundle. Updates the destination register tracking info
2184 accordingly. The pc is needed only for pc-relative load instructions
2185 (eg. l32r). The SP register number is needed to identify stores to
2186 the stack frame. Returns 0, if analysis was successful, non-zero
2190 call0_track_op (struct gdbarch
*gdbarch
, xtensa_c0reg_t dst
[], xtensa_c0reg_t src
[],
2191 xtensa_insn_kind opclass
, int nods
, unsigned odv
[],
2192 CORE_ADDR pc
, int spreg
, xtensa_frame_cache_t
*cache
)
2194 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2195 unsigned litbase
, litaddr
, litval
;
2196 xtensa_gdbarch_tdep
*tdep
= (xtensa_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
2201 /* 3 operands: dst, src, imm. */
2202 gdb_assert (nods
== 3);
2203 dst
[odv
[0]].fr_reg
= src
[odv
[1]].fr_reg
;
2204 dst
[odv
[0]].fr_ofs
= src
[odv
[1]].fr_ofs
+ odv
[2];
2207 /* 3 operands: dst, src1, src2. */
2208 gdb_assert (nods
== 3);
2209 if (src
[odv
[1]].fr_reg
== C0_CONST
)
2211 dst
[odv
[0]].fr_reg
= src
[odv
[2]].fr_reg
;
2212 dst
[odv
[0]].fr_ofs
= src
[odv
[2]].fr_ofs
+ src
[odv
[1]].fr_ofs
;
2214 else if (src
[odv
[2]].fr_reg
== C0_CONST
)
2216 dst
[odv
[0]].fr_reg
= src
[odv
[1]].fr_reg
;
2217 dst
[odv
[0]].fr_ofs
= src
[odv
[1]].fr_ofs
+ src
[odv
[2]].fr_ofs
;
2219 else dst
[odv
[0]].fr_reg
= C0_INEXP
;
2222 /* 3 operands: dst, src1, src2. */
2223 gdb_assert (nods
== 3);
2224 if (cache
->c0
.c0_fpalign
== 0)
2226 /* Handle dynamic stack alignment. */
2227 if ((src
[odv
[0]].fr_reg
== spreg
) && (src
[odv
[1]].fr_reg
== spreg
))
2229 if (src
[odv
[2]].fr_reg
== C0_CONST
)
2230 cache
->c0
.c0_fpalign
= src
[odv
[2]].fr_ofs
;
2233 else if ((src
[odv
[0]].fr_reg
== spreg
)
2234 && (src
[odv
[2]].fr_reg
== spreg
))
2236 if (src
[odv
[1]].fr_reg
== C0_CONST
)
2237 cache
->c0
.c0_fpalign
= src
[odv
[1]].fr_ofs
;
2240 /* else fall through. */
2242 if (src
[odv
[1]].fr_reg
== C0_CONST
)
2244 dst
[odv
[0]].fr_reg
= src
[odv
[2]].fr_reg
;
2245 dst
[odv
[0]].fr_ofs
= src
[odv
[2]].fr_ofs
& src
[odv
[1]].fr_ofs
;
2247 else if (src
[odv
[2]].fr_reg
== C0_CONST
)
2249 dst
[odv
[0]].fr_reg
= src
[odv
[1]].fr_reg
;
2250 dst
[odv
[0]].fr_ofs
= src
[odv
[1]].fr_ofs
& src
[odv
[2]].fr_ofs
;
2252 else dst
[odv
[0]].fr_reg
= C0_INEXP
;
2255 /* 3 operands: dst, src1, src2. */
2256 gdb_assert (nods
== 3);
2257 if (src
[odv
[2]].fr_reg
== C0_CONST
)
2259 dst
[odv
[0]].fr_reg
= src
[odv
[1]].fr_reg
;
2260 dst
[odv
[0]].fr_ofs
= src
[odv
[1]].fr_ofs
- src
[odv
[2]].fr_ofs
;
2262 else dst
[odv
[0]].fr_reg
= C0_INEXP
;
2265 /* 2 operands: dst, src [, src]. */
2266 gdb_assert (nods
== 2);
2267 /* First, check if it's a special case of saving unaligned SP
2268 to a spare register in case of dynamic stack adjustment.
2269 But, only do it one time. The second time could be initializing
2270 frame pointer. We don't want to overwrite the first one. */
2271 if ((odv
[1] == spreg
) && (cache
->c0
.c0_old_sp
== C0_INEXP
))
2272 cache
->c0
.c0_old_sp
= odv
[0];
2274 dst
[odv
[0]].fr_reg
= src
[odv
[1]].fr_reg
;
2275 dst
[odv
[0]].fr_ofs
= src
[odv
[1]].fr_ofs
;
2278 /* 2 operands: dst, imm. */
2279 gdb_assert (nods
== 2);
2280 dst
[odv
[0]].fr_reg
= C0_CONST
;
2281 dst
[odv
[0]].fr_ofs
= odv
[1];
2284 /* 2 operands: dst, literal offset. */
2285 gdb_assert (nods
== 2);
2286 /* litbase = xtensa_get_litbase (pc); can be also used. */
2287 litbase
= (tdep
->litbase_regnum
== -1)
2288 ? 0 : xtensa_read_register
2289 (tdep
->litbase_regnum
);
2290 litaddr
= litbase
& 1
2291 ? (litbase
& ~1) + (signed)odv
[1]
2292 : (pc
+ 3 + (signed)odv
[1]) & ~3;
2293 litval
= read_memory_integer (litaddr
, 4, byte_order
);
2294 dst
[odv
[0]].fr_reg
= C0_CONST
;
2295 dst
[odv
[0]].fr_ofs
= litval
;
2298 /* 3 operands: value, base, offset. */
2299 gdb_assert (nods
== 3 && spreg
>= 0 && spreg
< C0_NREGS
);
2300 /* First, check if it's a spill for saved unaligned SP,
2301 when dynamic stack adjustment was applied to this frame. */
2302 if ((cache
->c0
.c0_fpalign
!= 0) /* Dynamic stack adjustment. */
2303 && (odv
[1] == spreg
) /* SP usage indicates spill. */
2304 && (odv
[0] == cache
->c0
.c0_old_sp
)) /* Old SP register spilled. */
2305 cache
->c0
.c0_sp_ofs
= odv
[2];
2307 if (src
[odv
[1]].fr_reg
== spreg
/* Store to stack frame. */
2308 && (src
[odv
[1]].fr_ofs
& 3) == 0 /* Alignment preserved. */
2309 && src
[odv
[0]].fr_reg
>= 0 /* Value is from a register. */
2310 && src
[odv
[0]].fr_ofs
== 0 /* Value hasn't been modified. */
2311 && src
[src
[odv
[0]].fr_reg
].to_stk
== C0_NOSTK
) /* First time. */
2313 /* ISA encoding guarantees alignment. But, check it anyway. */
2314 gdb_assert ((odv
[2] & 3) == 0);
2315 dst
[src
[odv
[0]].fr_reg
].to_stk
= src
[odv
[1]].fr_ofs
+ odv
[2];
2318 /* If we end up inside Window Overflow / Underflow interrupt handler
2319 report an error because these handlers should have been handled
2320 already in a different way. */
2332 /* Analyze prologue of the function at start address to determine if it uses
2333 the Call0 ABI, and if so track register moves and linear modifications
2334 in the prologue up to the PC or just beyond the prologue, whichever is
2335 first. An 'entry' instruction indicates non-Call0 ABI and the end of the
2336 prologue. The prologue may overlap non-prologue instructions but is
2337 guaranteed to end by the first flow-control instruction (jump, branch,
2338 call or return). Since an optimized function may move information around
2339 and change the stack frame arbitrarily during the prologue, the information
2340 is guaranteed valid only at the point in the function indicated by the PC.
2341 May be used to skip the prologue or identify the ABI, w/o tracking.
2343 Returns: Address of first instruction after prologue, or PC (whichever
2344 is first), or 0, if decoding failed (in libisa).
2346 start Start address of function/prologue.
2347 pc Program counter to stop at. Use 0 to continue to end of prologue.
2348 If 0, avoids infinite run-on in corrupt code memory by bounding
2349 the scan to the end of the function if that can be determined.
2350 nregs Number of general registers to track.
2352 cache Xtensa frame cache.
2354 Note that these may produce useful results even if decoding fails
2355 because they begin with default assumptions that analysis may change. */
2358 call0_analyze_prologue (struct gdbarch
*gdbarch
,
2359 CORE_ADDR start
, CORE_ADDR pc
,
2360 int nregs
, xtensa_frame_cache_t
*cache
)
2362 CORE_ADDR ia
; /* Current insn address in prologue. */
2363 CORE_ADDR ba
= 0; /* Current address at base of insn buffer. */
2364 CORE_ADDR bt
; /* Current address at top+1 of insn buffer. */
2365 gdb_byte ibuf
[XTENSA_ISA_BSZ
];/* Instruction buffer for decoding prologue. */
2366 xtensa_isa isa
; /* libisa ISA handle. */
2367 xtensa_insnbuf ins
, slot
; /* libisa handle to decoded insn, slot. */
2368 xtensa_format ifmt
; /* libisa instruction format. */
2369 int ilen
, islots
, is
; /* Instruction length, nbr slots, current slot. */
2370 xtensa_opcode opc
; /* Opcode in current slot. */
2371 xtensa_insn_kind opclass
; /* Opcode class for Call0 prologue analysis. */
2372 int nods
; /* Opcode number of operands. */
2373 unsigned odv
[C0_MAXOPDS
]; /* Operand values in order provided by libisa. */
2374 xtensa_c0reg_t
*rtmp
; /* Register tracking info snapshot. */
2375 int j
; /* General loop counter. */
2376 int fail
= 0; /* Set non-zero and exit, if decoding fails. */
2377 CORE_ADDR body_pc
; /* The PC for the first non-prologue insn. */
2378 CORE_ADDR end_pc
; /* The PC for the lust function insn. */
2380 struct symtab_and_line prologue_sal
;
2382 DEBUGTRACE ("call0_analyze_prologue (start = 0x%08x, pc = 0x%08x, ...)\n",
2383 (int)start
, (int)pc
);
2385 /* Try to limit the scan to the end of the function if a non-zero pc
2386 arg was not supplied to avoid probing beyond the end of valid memory.
2387 If memory is full of garbage that classifies as c0opc_uninteresting.
2388 If this fails (eg. if no symbols) pc ends up 0 as it was.
2389 Initialize the Call0 frame and register tracking info.
2390 Assume it's Call0 until an 'entry' instruction is encountered.
2391 Assume we may be in the prologue until we hit a flow control instr. */
2397 /* Find out, if we have an information about the prologue from DWARF. */
2398 prologue_sal
= find_pc_line (start
, 0);
2399 if (prologue_sal
.line
!= 0) /* Found debug info. */
2400 body_pc
= prologue_sal
.end
;
2402 /* If we are going to analyze the prologue in general without knowing about
2403 the current PC, make the best assumption for the end of the prologue. */
2406 find_pc_partial_function (start
, 0, NULL
, &end_pc
);
2407 body_pc
= std::min (end_pc
, body_pc
);
2410 body_pc
= std::min (pc
, body_pc
);
2413 rtmp
= (xtensa_c0reg_t
*) alloca(nregs
* sizeof(xtensa_c0reg_t
));
2415 isa
= xtensa_default_isa
;
2416 gdb_assert (XTENSA_ISA_BSZ
>= xtensa_isa_maxlength (isa
));
2417 ins
= xtensa_insnbuf_alloc (isa
);
2418 slot
= xtensa_insnbuf_alloc (isa
);
2420 for (ia
= start
, bt
= ia
; ia
< body_pc
; ia
+= ilen
)
2422 /* (Re)fill instruction buffer from memory if necessary, but do not
2423 read memory beyond PC to be sure we stay within text section
2424 (this protection only works if a non-zero pc is supplied). */
2426 if (ia
+ xtensa_isa_maxlength (isa
) > bt
)
2429 bt
= (ba
+ XTENSA_ISA_BSZ
) < body_pc
? ba
+ XTENSA_ISA_BSZ
: body_pc
;
2430 if (target_read_memory (ba
, ibuf
, bt
- ba
) != 0 )
2431 error (_("Unable to read target memory ..."));
2434 /* Decode format information. */
2436 xtensa_insnbuf_from_chars (isa
, ins
, &ibuf
[ia
-ba
], 0);
2437 ifmt
= xtensa_format_decode (isa
, ins
);
2438 if (ifmt
== XTENSA_UNDEFINED
)
2443 ilen
= xtensa_format_length (isa
, ifmt
);
2444 if (ilen
== XTENSA_UNDEFINED
)
2449 islots
= xtensa_format_num_slots (isa
, ifmt
);
2450 if (islots
== XTENSA_UNDEFINED
)
2456 /* Analyze a bundle or a single instruction, using a snapshot of
2457 the register tracking info as input for the entire bundle so that
2458 register changes do not take effect within this bundle. */
2460 for (j
= 0; j
< nregs
; ++j
)
2461 rtmp
[j
] = cache
->c0
.c0_rt
[j
];
2463 for (is
= 0; is
< islots
; ++is
)
2465 /* Decode a slot and classify the opcode. */
2467 fail
= xtensa_format_get_slot (isa
, ifmt
, is
, ins
, slot
);
2471 opc
= xtensa_opcode_decode (isa
, ifmt
, is
, slot
);
2472 DEBUGVERB ("[call0_analyze_prologue] instr addr = 0x%08x, opc = %d\n",
2474 if (opc
== XTENSA_UNDEFINED
)
2475 opclass
= c0opc_illegal
;
2477 opclass
= call0_classify_opcode (isa
, opc
);
2479 /* Decide whether to track this opcode, ignore it, or bail out. */
2488 case c0opc_uninteresting
:
2491 case c0opc_flow
: /* Flow control instructions stop analysis. */
2492 case c0opc_rwxsr
: /* RSR, WSR, XSR instructions stop analysis. */
2497 ia
+= ilen
; /* Skip over 'entry' insn. */
2504 /* Only expected opcodes should get this far. */
2506 /* Extract and decode the operands. */
2507 nods
= xtensa_opcode_num_operands (isa
, opc
);
2508 if (nods
== XTENSA_UNDEFINED
)
2514 for (j
= 0; j
< nods
&& j
< C0_MAXOPDS
; ++j
)
2516 fail
= xtensa_operand_get_field (isa
, opc
, j
, ifmt
,
2521 fail
= xtensa_operand_decode (isa
, opc
, j
, &odv
[j
]);
2526 /* Check operands to verify use of 'mov' assembler macro. */
2527 if (opclass
== c0opc_mov
&& nods
== 3)
2529 if (odv
[2] == odv
[1])
2532 if ((odv
[0] == 1) && (odv
[1] != 1))
2533 /* OR A1, An, An , where n != 1.
2534 This means we are inside epilogue already. */
2539 opclass
= c0opc_uninteresting
;
2544 /* Track register movement and modification for this operation. */
2545 fail
= call0_track_op (gdbarch
, cache
->c0
.c0_rt
, rtmp
,
2546 opclass
, nods
, odv
, ia
, 1, cache
);
2552 DEBUGVERB ("[call0_analyze_prologue] stopped at instr addr 0x%08x, %s\n",
2553 (unsigned)ia
, fail
? "failed" : "succeeded");
2554 xtensa_insnbuf_free(isa
, slot
);
2555 xtensa_insnbuf_free(isa
, ins
);
2556 return fail
? XTENSA_ISA_BADPC
: ia
;
2559 /* Initialize frame cache for the current frame in CALL0 ABI. */
2562 call0_frame_cache (struct frame_info
*this_frame
,
2563 xtensa_frame_cache_t
*cache
, CORE_ADDR pc
)
2565 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2566 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2567 CORE_ADDR start_pc
; /* The beginning of the function. */
2568 CORE_ADDR body_pc
=UINT_MAX
; /* PC, where prologue analysis stopped. */
2569 CORE_ADDR sp
, fp
, ra
;
2570 int fp_regnum
= C0_SP
, c0_hasfp
= 0, c0_frmsz
= 0, prev_sp
= 0, to_stk
;
2571 xtensa_gdbarch_tdep
*tdep
= (xtensa_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
2573 sp
= get_frame_register_unsigned
2574 (this_frame
, tdep
->a0_base
+ 1);
2575 fp
= sp
; /* Assume FP == SP until proven otherwise. */
2577 /* Find the beginning of the prologue of the function containing the PC
2578 and analyze it up to the PC or the end of the prologue. */
2580 if (find_pc_partial_function (pc
, NULL
, &start_pc
, NULL
))
2582 body_pc
= call0_analyze_prologue (gdbarch
, start_pc
, pc
, C0_NREGS
, cache
);
2584 if (body_pc
== XTENSA_ISA_BADPC
)
2588 goto finish_frame_analysis
;
2592 /* Get the frame information and FP (if used) at the current PC.
2593 If PC is in the prologue, the prologue analysis is more reliable
2594 than DWARF info. We don't not know for sure, if PC is in the prologue,
2595 but we do know no calls have yet taken place, so we can almost
2596 certainly rely on the prologue analysis. */
2600 /* Prologue analysis was successful up to the PC.
2601 It includes the cases when PC == START_PC. */
2602 c0_hasfp
= cache
->c0
.c0_rt
[C0_FP
].fr_reg
== C0_SP
;
2603 /* c0_hasfp == true means there is a frame pointer because
2604 we analyzed the prologue and found that cache->c0.c0_rt[C0_FP]
2605 was derived from SP. Otherwise, it would be C0_FP. */
2606 fp_regnum
= c0_hasfp
? C0_FP
: C0_SP
;
2607 c0_frmsz
= - cache
->c0
.c0_rt
[fp_regnum
].fr_ofs
;
2608 fp_regnum
+= tdep
->a0_base
;
2610 else /* No data from the prologue analysis. */
2613 fp_regnum
= tdep
->a0_base
+ C0_SP
;
2618 if (cache
->c0
.c0_fpalign
)
2620 /* This frame has a special prologue with a dynamic stack adjustment
2621 to force an alignment, which is bigger than standard 16 bytes. */
2623 CORE_ADDR unaligned_sp
;
2625 if (cache
->c0
.c0_old_sp
== C0_INEXP
)
2626 /* This can't be. Prologue code should be consistent.
2627 Unaligned stack pointer should be saved in a spare register. */
2631 goto finish_frame_analysis
;
2634 if (cache
->c0
.c0_sp_ofs
== C0_NOSTK
)
2635 /* Saved unaligned value of SP is kept in a register. */
2636 unaligned_sp
= get_frame_register_unsigned
2637 (this_frame
, tdep
->a0_base
+ cache
->c0
.c0_old_sp
);
2639 /* Get the value from stack. */
2640 unaligned_sp
= (CORE_ADDR
)
2641 read_memory_integer (fp
+ cache
->c0
.c0_sp_ofs
, 4, byte_order
);
2643 prev_sp
= unaligned_sp
+ c0_frmsz
;
2646 prev_sp
= fp
+ c0_frmsz
;
2648 /* Frame size from debug info or prologue tracking does not account for
2649 alloca() and other dynamic allocations. Adjust frame size by FP - SP. */
2652 fp
= get_frame_register_unsigned (this_frame
, fp_regnum
);
2654 /* Update the stack frame size. */
2655 c0_frmsz
+= fp
- sp
;
2658 /* Get the return address (RA) from the stack if saved,
2659 or try to get it from a register. */
2661 to_stk
= cache
->c0
.c0_rt
[C0_RA
].to_stk
;
2662 if (to_stk
!= C0_NOSTK
)
2664 read_memory_integer (sp
+ c0_frmsz
+ cache
->c0
.c0_rt
[C0_RA
].to_stk
,
2667 else if (cache
->c0
.c0_rt
[C0_RA
].fr_reg
== C0_CONST
2668 && cache
->c0
.c0_rt
[C0_RA
].fr_ofs
== 0)
2670 /* Special case for terminating backtrace at a function that wants to
2671 be seen as the outermost one. Such a function will clear it's RA (A0)
2672 register to 0 in the prologue instead of saving its original value. */
2677 /* RA was copied to another register or (before any function call) may
2678 still be in the original RA register. This is not always reliable:
2679 even in a leaf function, register tracking stops after prologue, and
2680 even in prologue, non-prologue instructions (not tracked) may overwrite
2681 RA or any register it was copied to. If likely in prologue or before
2682 any call, use retracking info and hope for the best (compiler should
2683 have saved RA in stack if not in a leaf function). If not in prologue,
2689 && (i
== C0_RA
|| cache
->c0
.c0_rt
[i
].fr_reg
!= C0_RA
);
2691 if (i
>= C0_NREGS
&& cache
->c0
.c0_rt
[C0_RA
].fr_reg
== C0_RA
)
2695 ra
= get_frame_register_unsigned
2697 tdep
->a0_base
+ cache
->c0
.c0_rt
[i
].fr_reg
);
2702 finish_frame_analysis
:
2703 cache
->pc
= start_pc
;
2705 /* RA == 0 marks the outermost frame. Do not go past it. */
2706 cache
->prev_sp
= (ra
!= 0) ? prev_sp
: 0;
2707 cache
->c0
.fp_regnum
= fp_regnum
;
2708 cache
->c0
.c0_frmsz
= c0_frmsz
;
2709 cache
->c0
.c0_hasfp
= c0_hasfp
;
2710 cache
->c0
.c0_fp
= fp
;
2713 static CORE_ADDR a0_saved
;
2714 static CORE_ADDR a7_saved
;
2715 static CORE_ADDR a11_saved
;
2716 static int a0_was_saved
;
2717 static int a7_was_saved
;
2718 static int a11_was_saved
;
2720 /* Simulate L32E instruction: AT <-- ref (AS + offset). */
2722 execute_l32e (struct gdbarch
*gdbarch
, int at
, int as
, int offset
, CORE_ADDR wb
)
2724 xtensa_gdbarch_tdep
*tdep
= (xtensa_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
2725 int atreg
= arreg_number (gdbarch
, tdep
->a0_base
+ at
, wb
);
2726 int asreg
= arreg_number (gdbarch
, tdep
->a0_base
+ as
, wb
);
2727 CORE_ADDR addr
= xtensa_read_register (asreg
) + offset
;
2728 unsigned int spilled_value
2729 = read_memory_unsigned_integer (addr
, 4, gdbarch_byte_order (gdbarch
));
2731 if ((at
== 0) && !a0_was_saved
)
2733 a0_saved
= xtensa_read_register (atreg
);
2736 else if ((at
== 7) && !a7_was_saved
)
2738 a7_saved
= xtensa_read_register (atreg
);
2741 else if ((at
== 11) && !a11_was_saved
)
2743 a11_saved
= xtensa_read_register (atreg
);
2747 xtensa_write_register (atreg
, spilled_value
);
2750 /* Simulate S32E instruction: AT --> ref (AS + offset). */
2752 execute_s32e (struct gdbarch
*gdbarch
, int at
, int as
, int offset
, CORE_ADDR wb
)
2754 xtensa_gdbarch_tdep
*tdep
= (xtensa_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
2755 int atreg
= arreg_number (gdbarch
, tdep
->a0_base
+ at
, wb
);
2756 int asreg
= arreg_number (gdbarch
, tdep
->a0_base
+ as
, wb
);
2757 CORE_ADDR addr
= xtensa_read_register (asreg
) + offset
;
2758 ULONGEST spilled_value
= xtensa_read_register (atreg
);
2760 write_memory_unsigned_integer (addr
, 4,
2761 gdbarch_byte_order (gdbarch
),
2765 #define XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN 200
2771 xtNoExceptionHandler
2772 } xtensa_exception_handler_t
;
2774 /* Execute instruction stream from current PC until hitting RFWU or RFWO.
2775 Return type of Xtensa Window Interrupt Handler on success. */
2776 static xtensa_exception_handler_t
2777 execute_code (struct gdbarch
*gdbarch
, CORE_ADDR current_pc
, CORE_ADDR wb
)
2780 xtensa_insnbuf ins
, slot
;
2781 gdb_byte ibuf
[XTENSA_ISA_BSZ
];
2782 CORE_ADDR ia
, bt
, ba
;
2784 int ilen
, islots
, is
;
2787 void (*func
) (struct gdbarch
*, int, int, int, CORE_ADDR
);
2788 xtensa_gdbarch_tdep
*tdep
= (xtensa_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
2790 uint32_t at
, as
, offset
;
2792 /* WindowUnderflow12 = true, when inside _WindowUnderflow12. */
2793 int WindowUnderflow12
= (current_pc
& 0x1ff) >= 0x140;
2795 isa
= xtensa_default_isa
;
2796 gdb_assert (XTENSA_ISA_BSZ
>= xtensa_isa_maxlength (isa
));
2797 ins
= xtensa_insnbuf_alloc (isa
);
2798 slot
= xtensa_insnbuf_alloc (isa
);
2807 while (insn_num
++ < XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN
)
2809 if (ia
+ xtensa_isa_maxlength (isa
) > bt
)
2812 bt
= (ba
+ XTENSA_ISA_BSZ
);
2813 if (target_read_memory (ba
, ibuf
, bt
- ba
) != 0)
2814 return xtNoExceptionHandler
;
2816 xtensa_insnbuf_from_chars (isa
, ins
, &ibuf
[ia
-ba
], 0);
2817 ifmt
= xtensa_format_decode (isa
, ins
);
2818 if (ifmt
== XTENSA_UNDEFINED
)
2819 return xtNoExceptionHandler
;
2820 ilen
= xtensa_format_length (isa
, ifmt
);
2821 if (ilen
== XTENSA_UNDEFINED
)
2822 return xtNoExceptionHandler
;
2823 islots
= xtensa_format_num_slots (isa
, ifmt
);
2824 if (islots
== XTENSA_UNDEFINED
)
2825 return xtNoExceptionHandler
;
2826 for (is
= 0; is
< islots
; ++is
)
2828 if (xtensa_format_get_slot (isa
, ifmt
, is
, ins
, slot
))
2829 return xtNoExceptionHandler
;
2830 opc
= xtensa_opcode_decode (isa
, ifmt
, is
, slot
);
2831 if (opc
== XTENSA_UNDEFINED
)
2832 return xtNoExceptionHandler
;
2833 switch (call0_classify_opcode (isa
, opc
))
2839 /* We expect none of them here. */
2840 return xtNoExceptionHandler
;
2842 func
= execute_l32e
;
2845 func
= execute_s32e
;
2847 case c0opc_rfwo
: /* RFWO. */
2848 /* Here, we return from WindowOverflow handler and,
2849 if we stopped at the very beginning, which means
2850 A0 was saved, we have to restore it now. */
2853 int arreg
= arreg_number (gdbarch
,
2856 xtensa_write_register (arreg
, a0_saved
);
2858 return xtWindowOverflow
;
2859 case c0opc_rfwu
: /* RFWU. */
2860 /* Here, we return from WindowUnderflow handler.
2861 Let's see if either A7 or A11 has to be restored. */
2862 if (WindowUnderflow12
)
2866 int arreg
= arreg_number (gdbarch
,
2869 xtensa_write_register (arreg
, a11_saved
);
2872 else if (a7_was_saved
)
2874 int arreg
= arreg_number (gdbarch
,
2877 xtensa_write_register (arreg
, a7_saved
);
2879 return xtWindowUnderflow
;
2880 default: /* Simply skip this insns. */
2884 /* Decode arguments for L32E / S32E and simulate their execution. */
2885 if ( xtensa_opcode_num_operands (isa
, opc
) != 3 )
2886 return xtNoExceptionHandler
;
2887 if (xtensa_operand_get_field (isa
, opc
, 0, ifmt
, is
, slot
, &at
))
2888 return xtNoExceptionHandler
;
2889 if (xtensa_operand_decode (isa
, opc
, 0, &at
))
2890 return xtNoExceptionHandler
;
2891 if (xtensa_operand_get_field (isa
, opc
, 1, ifmt
, is
, slot
, &as
))
2892 return xtNoExceptionHandler
;
2893 if (xtensa_operand_decode (isa
, opc
, 1, &as
))
2894 return xtNoExceptionHandler
;
2895 if (xtensa_operand_get_field (isa
, opc
, 2, ifmt
, is
, slot
, &offset
))
2896 return xtNoExceptionHandler
;
2897 if (xtensa_operand_decode (isa
, opc
, 2, &offset
))
2898 return xtNoExceptionHandler
;
2900 (*func
) (gdbarch
, at
, as
, offset
, wb
);
2905 return xtNoExceptionHandler
;
2908 /* Handle Window Overflow / Underflow exception frames. */
2911 xtensa_window_interrupt_frame_cache (struct frame_info
*this_frame
,
2912 xtensa_frame_cache_t
*cache
,
2915 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2916 CORE_ADDR ps
, wb
, ws
, ra
;
2917 int epc1_regnum
, i
, regnum
;
2918 xtensa_exception_handler_t eh_type
;
2919 xtensa_gdbarch_tdep
*tdep
= (xtensa_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
2921 /* Read PS, WB, and WS from the hardware. Note that PS register
2922 must be present, if Windowed ABI is supported. */
2923 ps
= xtensa_read_register (gdbarch_ps_regnum (gdbarch
));
2924 wb
= xtensa_read_register (tdep
->wb_regnum
);
2925 ws
= xtensa_read_register (tdep
->ws_regnum
);
2927 /* Execute all the remaining instructions from Window Interrupt Handler
2928 by simulating them on the remote protocol level. On return, set the
2929 type of Xtensa Window Interrupt Handler, or report an error. */
2930 eh_type
= execute_code (gdbarch
, pc
, wb
);
2931 if (eh_type
== xtNoExceptionHandler
)
2933 Unable to decode Xtensa Window Interrupt Handler's code."));
2935 cache
->ps
= ps
^ PS_EXC
; /* Clear the exception bit in PS. */
2936 cache
->call0
= 0; /* It's Windowed ABI. */
2938 /* All registers for the cached frame will be alive. */
2939 for (i
= 0; i
< XTENSA_NUM_SAVED_AREGS
; i
++)
2940 cache
->wd
.aregs
[i
] = -1;
2942 if (eh_type
== xtWindowOverflow
)
2943 cache
->wd
.ws
= ws
^ (1 << wb
);
2944 else /* eh_type == xtWindowUnderflow. */
2945 cache
->wd
.ws
= ws
| (1 << wb
);
2947 cache
->wd
.wb
= (ps
& 0xf00) >> 8; /* Set WB to OWB. */
2948 regnum
= arreg_number (gdbarch
, tdep
->a0_base
,
2950 ra
= xtensa_read_register (regnum
);
2951 cache
->wd
.callsize
= WINSIZE (ra
);
2952 cache
->prev_sp
= xtensa_read_register (regnum
+ 1);
2953 /* Set regnum to a frame pointer of the frame being cached. */
2954 regnum
= xtensa_scan_prologue (gdbarch
, pc
);
2955 regnum
= arreg_number (gdbarch
,
2956 tdep
->a0_base
+ regnum
,
2958 cache
->base
= get_frame_register_unsigned (this_frame
, regnum
);
2960 /* Read PC of interrupted function from EPC1 register. */
2961 epc1_regnum
= xtensa_find_register_by_name (gdbarch
,"epc1");
2962 if (epc1_regnum
< 0)
2963 error(_("Unable to read Xtensa register EPC1"));
2964 cache
->ra
= xtensa_read_register (epc1_regnum
);
2965 cache
->pc
= get_frame_func (this_frame
);
2969 /* Skip function prologue.
2971 Return the pc of the first instruction after prologue. GDB calls this to
2972 find the address of the first line of the function or (if there is no line
2973 number information) to skip the prologue for planting breakpoints on
2974 function entries. Use debug info (if present) or prologue analysis to skip
2975 the prologue to achieve reliable debugging behavior. For windowed ABI,
2976 only the 'entry' instruction is skipped. It is not strictly necessary to
2977 skip the prologue (Call0) or 'entry' (Windowed) because xt-gdb knows how to
2978 backtrace at any point in the prologue, however certain potential hazards
2979 are avoided and a more "normal" debugging experience is ensured by
2980 skipping the prologue (can be disabled by defining DONT_SKIP_PROLOG).
2981 For example, if we don't skip the prologue:
2982 - Some args may not yet have been saved to the stack where the debug
2983 info expects to find them (true anyway when only 'entry' is skipped);
2984 - Software breakpoints ('break' instrs) may not have been unplanted
2985 when the prologue analysis is done on initializing the frame cache,
2986 and breaks in the prologue will throw off the analysis.
2988 If we have debug info ( line-number info, in particular ) we simply skip
2989 the code associated with the first function line effectively skipping
2990 the prologue code. It works even in cases like
2993 { int local_var = 1;
2997 because, for this source code, both Xtensa compilers will generate two
2998 separate entries ( with the same line number ) in dwarf line-number
2999 section to make sure there is a boundary between the prologue code and
3000 the rest of the function.
3002 If there is no debug info, we need to analyze the code. */
3004 /* #define DONT_SKIP_PROLOGUE */
3007 xtensa_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
3009 struct symtab_and_line prologue_sal
;
3012 DEBUGTRACE ("xtensa_skip_prologue (start_pc = 0x%08x)\n", (int) start_pc
);
3014 #if DONT_SKIP_PROLOGUE
3018 /* Try to find first body line from debug info. */
3020 prologue_sal
= find_pc_line (start_pc
, 0);
3021 if (prologue_sal
.line
!= 0) /* Found debug info. */
3023 /* In Call0, it is possible to have a function with only one instruction
3024 ('ret') resulting from a one-line optimized function that does nothing.
3025 In that case, prologue_sal.end may actually point to the start of the
3026 next function in the text section, causing a breakpoint to be set at
3027 the wrong place. Check, if the end address is within a different
3028 function, and if so return the start PC. We know we have symbol
3033 xtensa_gdbarch_tdep
*tdep
= (xtensa_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
3034 if ((tdep
->call_abi
== CallAbiCall0Only
)
3035 && call0_ret (start_pc
, prologue_sal
.end
))
3038 find_pc_partial_function (prologue_sal
.end
, NULL
, &end_func
, NULL
);
3039 if (end_func
!= start_pc
)
3042 return prologue_sal
.end
;
3045 /* No debug line info. Analyze prologue for Call0 or simply skip ENTRY. */
3046 body_pc
= call0_analyze_prologue (gdbarch
, start_pc
, 0, 0,
3047 xtensa_alloc_frame_cache (0));
3048 return body_pc
!= 0 ? body_pc
: start_pc
;
3051 /* Verify the current configuration. */
3053 xtensa_verify_config (struct gdbarch
*gdbarch
)
3055 xtensa_gdbarch_tdep
*tdep
= (xtensa_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
3058 /* Verify that we got a reasonable number of AREGS. */
3059 if ((tdep
->num_aregs
& -tdep
->num_aregs
) != tdep
->num_aregs
)
3061 \n\tnum_aregs: Number of AR registers (%d) is not a power of two!"),
3064 /* Verify that certain registers exist. */
3066 if (tdep
->pc_regnum
== -1)
3067 log
.printf (_("\n\tpc_regnum: No PC register"));
3068 if (tdep
->isa_use_exceptions
&& tdep
->ps_regnum
== -1)
3069 log
.printf (_("\n\tps_regnum: No PS register"));
3071 if (tdep
->isa_use_windowed_registers
)
3073 if (tdep
->wb_regnum
== -1)
3074 log
.printf (_("\n\twb_regnum: No WB register"));
3075 if (tdep
->ws_regnum
== -1)
3076 log
.printf (_("\n\tws_regnum: No WS register"));
3077 if (tdep
->ar_base
== -1)
3078 log
.printf (_("\n\tar_base: No AR registers"));
3081 if (tdep
->a0_base
== -1)
3082 log
.printf (_("\n\ta0_base: No Ax registers"));
3085 internal_error (__FILE__
, __LINE__
,
3086 _("the following are invalid: %s"), log
.c_str ());
3090 /* Derive specific register numbers from the array of registers. */
3093 xtensa_derive_tdep (xtensa_gdbarch_tdep
*tdep
)
3095 xtensa_register_t
* rmap
;
3096 int n
, max_size
= 4;
3099 tdep
->num_nopriv_regs
= 0;
3101 /* Special registers 0..255 (core). */
3102 #define XTENSA_DBREGN_SREG(n) (0x0200+(n))
3103 /* User registers 0..255. */
3104 #define XTENSA_DBREGN_UREG(n) (0x0300+(n))
3106 for (rmap
= tdep
->regmap
, n
= 0; rmap
->target_number
!= -1; n
++, rmap
++)
3108 if (rmap
->target_number
== 0x0020)
3109 tdep
->pc_regnum
= n
;
3110 else if (rmap
->target_number
== 0x0100)
3112 else if (rmap
->target_number
== 0x0000)
3114 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(72))
3115 tdep
->wb_regnum
= n
;
3116 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(73))
3117 tdep
->ws_regnum
= n
;
3118 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(233))
3119 tdep
->debugcause_regnum
= n
;
3120 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(232))
3121 tdep
->exccause_regnum
= n
;
3122 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(238))
3123 tdep
->excvaddr_regnum
= n
;
3124 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(0))
3125 tdep
->lbeg_regnum
= n
;
3126 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(1))
3127 tdep
->lend_regnum
= n
;
3128 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(2))
3129 tdep
->lcount_regnum
= n
;
3130 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(3))
3131 tdep
->sar_regnum
= n
;
3132 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(5))
3133 tdep
->litbase_regnum
= n
;
3134 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(230))
3135 tdep
->ps_regnum
= n
;
3136 else if (rmap
->target_number
== XTENSA_DBREGN_UREG(231))
3137 tdep
->threadptr_regnum
= n
;
3139 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(226))
3140 tdep
->interrupt_regnum
= n
;
3141 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(227))
3142 tdep
->interrupt2_regnum
= n
;
3143 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(224))
3144 tdep
->cpenable_regnum
= n
;
3147 if (rmap
->byte_size
> max_size
)
3148 max_size
= rmap
->byte_size
;
3149 if (rmap
->mask
!= 0 && tdep
->num_regs
== 0)
3151 if ((rmap
->flags
& XTENSA_REGISTER_FLAGS_PRIVILEGED
) != 0
3152 && tdep
->num_nopriv_regs
== 0)
3153 tdep
->num_nopriv_regs
= n
;
3155 if (tdep
->num_regs
== 0)
3156 tdep
->num_regs
= tdep
->num_nopriv_regs
;
3158 /* Number of pseudo registers. */
3159 tdep
->num_pseudo_regs
= n
- tdep
->num_regs
;
3161 /* Empirically determined maximum sizes. */
3162 tdep
->max_register_raw_size
= max_size
;
3163 tdep
->max_register_virtual_size
= max_size
;
3166 /* Module "constructor" function. */
3168 extern xtensa_gdbarch_tdep xtensa_tdep
;
3170 static struct gdbarch
*
3171 xtensa_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
3173 struct gdbarch
*gdbarch
;
3175 DEBUGTRACE ("gdbarch_init()\n");
3177 if (!xtensa_default_isa
)
3178 xtensa_default_isa
= xtensa_isa_init (0, 0);
3180 /* We have to set the byte order before we call gdbarch_alloc. */
3181 info
.byte_order
= XCHAL_HAVE_BE
? BFD_ENDIAN_BIG
: BFD_ENDIAN_LITTLE
;
3183 xtensa_gdbarch_tdep
*tdep
= &xtensa_tdep
;
3184 gdbarch
= gdbarch_alloc (&info
, tdep
);
3185 xtensa_derive_tdep (tdep
);
3187 /* Verify our configuration. */
3188 xtensa_verify_config (gdbarch
);
3189 xtensa_session_once_reported
= 0;
3191 set_gdbarch_wchar_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
3192 set_gdbarch_wchar_signed (gdbarch
, 0);
3194 /* Pseudo-Register read/write. */
3195 set_gdbarch_pseudo_register_read (gdbarch
, xtensa_pseudo_register_read
);
3196 set_gdbarch_pseudo_register_write (gdbarch
, xtensa_pseudo_register_write
);
3198 /* Set target information. */
3199 set_gdbarch_num_regs (gdbarch
, tdep
->num_regs
);
3200 set_gdbarch_num_pseudo_regs (gdbarch
, tdep
->num_pseudo_regs
);
3201 set_gdbarch_sp_regnum (gdbarch
, tdep
->a0_base
+ 1);
3202 set_gdbarch_pc_regnum (gdbarch
, tdep
->pc_regnum
);
3203 set_gdbarch_ps_regnum (gdbarch
, tdep
->ps_regnum
);
3205 /* Renumber registers for known formats (stabs and dwarf2). */
3206 set_gdbarch_stab_reg_to_regnum (gdbarch
, xtensa_reg_to_regnum
);
3207 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, xtensa_reg_to_regnum
);
3209 /* We provide our own function to get register information. */
3210 set_gdbarch_register_name (gdbarch
, xtensa_register_name
);
3211 set_gdbarch_register_type (gdbarch
, xtensa_register_type
);
3213 /* To call functions from GDB using dummy frame. */
3214 set_gdbarch_push_dummy_call (gdbarch
, xtensa_push_dummy_call
);
3216 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
3218 set_gdbarch_return_value (gdbarch
, xtensa_return_value
);
3220 /* Advance PC across any prologue instructions to reach "real" code. */
3221 set_gdbarch_skip_prologue (gdbarch
, xtensa_skip_prologue
);
3223 /* Stack grows downward. */
3224 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
3226 /* Set breakpoints. */
3227 set_gdbarch_breakpoint_kind_from_pc (gdbarch
,
3228 xtensa_breakpoint_kind_from_pc
);
3229 set_gdbarch_sw_breakpoint_from_kind (gdbarch
,
3230 xtensa_sw_breakpoint_from_kind
);
3232 /* After breakpoint instruction or illegal instruction, pc still
3233 points at break instruction, so don't decrement. */
3234 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
3236 /* We don't skip args. */
3237 set_gdbarch_frame_args_skip (gdbarch
, 0);
3239 set_gdbarch_unwind_pc (gdbarch
, xtensa_unwind_pc
);
3241 set_gdbarch_frame_align (gdbarch
, xtensa_frame_align
);
3243 set_gdbarch_dummy_id (gdbarch
, xtensa_dummy_id
);
3245 /* Frame handling. */
3246 frame_base_set_default (gdbarch
, &xtensa_frame_base
);
3247 frame_unwind_append_unwinder (gdbarch
, &xtensa_unwind
);
3248 dwarf2_append_unwinders (gdbarch
);
3250 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
3252 xtensa_add_reggroups (gdbarch
);
3253 set_gdbarch_register_reggroup_p (gdbarch
, xtensa_register_reggroup_p
);
3255 set_gdbarch_iterate_over_regset_sections
3256 (gdbarch
, xtensa_iterate_over_regset_sections
);
3258 set_solib_svr4_fetch_link_map_offsets
3259 (gdbarch
, svr4_ilp32_fetch_link_map_offsets
);
3261 /* Hook in the ABI-specific overrides, if they have been registered. */
3262 gdbarch_init_osabi (info
, gdbarch
);
3268 xtensa_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
3270 error (_("xtensa_dump_tdep(): not implemented"));
3273 void _initialize_xtensa_tdep ();
3275 _initialize_xtensa_tdep ()
3277 gdbarch_register (bfd_arch_xtensa
, xtensa_gdbarch_init
, xtensa_dump_tdep
);
3278 xtensa_init_reggroups ();
3280 add_setshow_zuinteger_cmd ("xtensa",
3282 &xtensa_debug_level
,
3283 _("Set Xtensa debugging."),
3284 _("Show Xtensa debugging."), _("\
3285 When non-zero, Xtensa-specific debugging is enabled. \
3286 Can be 1, 2, 3, or 4 indicating the level of debugging."),
3289 &setdebuglist
, &showdebuglist
);