1 /* Target-dependent code for the Xtensa port of GDB, the GNU debugger.
3 Copyright (C) 2003-2021 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include "solib-svr4.h"
29 #include "reggroups.h"
32 #include "dwarf2/frame.h"
33 #include "frame-base.h"
34 #include "frame-unwind.h"
36 #include "arch-utils.h"
42 #include "xtensa-isa.h"
43 #include "xtensa-tdep.h"
44 #include "xtensa-config.h"
48 static unsigned int xtensa_debug_level
= 0;
50 #define DEBUGWARN(args...) \
51 if (xtensa_debug_level > 0) \
52 fprintf_unfiltered (gdb_stdlog, "(warn ) " args)
54 #define DEBUGINFO(args...) \
55 if (xtensa_debug_level > 1) \
56 fprintf_unfiltered (gdb_stdlog, "(info ) " args)
58 #define DEBUGTRACE(args...) \
59 if (xtensa_debug_level > 2) \
60 fprintf_unfiltered (gdb_stdlog, "(trace) " args)
62 #define DEBUGVERB(args...) \
63 if (xtensa_debug_level > 3) \
64 fprintf_unfiltered (gdb_stdlog, "(verb ) " args)
67 /* According to the ABI, the SP must be aligned to 16-byte boundaries. */
68 #define SP_ALIGNMENT 16
71 /* On Windowed ABI, we use a6 through a11 for passing arguments
72 to a function called by GDB because CALL4 is used. */
73 #define ARGS_NUM_REGS 6
74 #define REGISTER_SIZE 4
77 /* Extract the call size from the return address or PS register. */
78 #define PS_CALLINC_SHIFT 16
79 #define PS_CALLINC_MASK 0x00030000
80 #define CALLINC(ps) (((ps) & PS_CALLINC_MASK) >> PS_CALLINC_SHIFT)
81 #define WINSIZE(ra) (4 * (( (ra) >> 30) & 0x3))
83 /* On TX, hardware can be configured without Exception Option.
84 There is no PS register in this case. Inside XT-GDB, let us treat
85 it as a virtual read-only register always holding the same value. */
88 /* ABI-independent macros. */
89 #define ARG_NOF(tdep) \
91 == CallAbiCall0Only ? C0_NARGS : (ARGS_NUM_REGS))
92 #define ARG_1ST(tdep) \
93 (tdep->call_abi == CallAbiCall0Only \
94 ? (tdep->a0_base + C0_ARGS) \
95 : (tdep->a0_base + 6))
97 /* XTENSA_IS_ENTRY tests whether the first byte of an instruction
98 indicates that the instruction is an ENTRY instruction. */
100 #define XTENSA_IS_ENTRY(gdbarch, op1) \
101 ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) \
102 ? ((op1) == 0x6c) : ((op1) == 0x36))
104 #define XTENSA_ENTRY_LENGTH 3
106 /* windowing_enabled() returns true, if windowing is enabled.
107 WOE must be set to 1; EXCM to 0.
108 Note: We assume that EXCM is always 0 for XEA1. */
110 #define PS_WOE (1<<18)
111 #define PS_EXC (1<<4)
113 /* Big enough to hold the size of the largest register in bytes. */
114 #define XTENSA_MAX_REGISTER_SIZE 64
117 windowing_enabled (struct gdbarch
*gdbarch
, unsigned int ps
)
119 xtensa_gdbarch_tdep
*tdep
= (xtensa_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
121 /* If we know CALL0 ABI is set explicitly, say it is Call0. */
122 if (tdep
->call_abi
== CallAbiCall0Only
)
125 return ((ps
& PS_EXC
) == 0 && (ps
& PS_WOE
) != 0);
128 /* Convert a live A-register number to the corresponding AR-register
131 arreg_number (struct gdbarch
*gdbarch
, int a_regnum
, ULONGEST wb
)
133 xtensa_gdbarch_tdep
*tdep
= (xtensa_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
136 arreg
= a_regnum
- tdep
->a0_base
;
137 arreg
+= (wb
& ((tdep
->num_aregs
- 1) >> 2)) << WB_SHIFT
;
138 arreg
&= tdep
->num_aregs
- 1;
140 return arreg
+ tdep
->ar_base
;
143 /* Convert a live AR-register number to the corresponding A-register order
144 number in a range [0..15]. Return -1, if AR_REGNUM is out of WB window. */
146 areg_number (struct gdbarch
*gdbarch
, int ar_regnum
, unsigned int wb
)
148 xtensa_gdbarch_tdep
*tdep
= (xtensa_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
151 areg
= ar_regnum
- tdep
->ar_base
;
152 if (areg
< 0 || areg
>= tdep
->num_aregs
)
154 areg
= (areg
- wb
* 4) & (tdep
->num_aregs
- 1);
155 return (areg
> 15) ? -1 : areg
;
158 /* Read Xtensa register directly from the hardware. */
160 xtensa_read_register (int regnum
)
164 regcache_raw_read_unsigned (get_current_regcache (), regnum
, &value
);
165 return (unsigned long) value
;
168 /* Write Xtensa register directly to the hardware. */
170 xtensa_write_register (int regnum
, ULONGEST value
)
172 regcache_raw_write_unsigned (get_current_regcache (), regnum
, value
);
175 /* Return the window size of the previous call to the function from which we
178 This function is used to extract the return value after a called function
179 has returned to the caller. On Xtensa, the register that holds the return
180 value (from the perspective of the caller) depends on what call
181 instruction was used. For now, we are assuming that the call instruction
182 precedes the current address, so we simply analyze the call instruction.
183 If we are in a dummy frame, we simply return 4 as we used a 'pseudo-call4'
184 method to call the inferior function. */
187 extract_call_winsize (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
189 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
194 DEBUGTRACE ("extract_call_winsize (pc = 0x%08x)\n", (int) pc
);
196 /* Read the previous instruction (should be a call[x]{4|8|12}. */
197 read_memory (pc
-3, buf
, 3);
198 insn
= extract_unsigned_integer (buf
, 3, byte_order
);
200 /* Decode call instruction:
202 call{0,4,8,12} OFFSET || {00,01,10,11} || 0101
203 callx{0,4,8,12} OFFSET || 11 || {00,01,10,11} || 0000
205 call{0,4,8,12} 0101 || {00,01,10,11} || OFFSET
206 callx{0,4,8,12} 0000 || {00,01,10,11} || 11 || OFFSET. */
208 if (byte_order
== BFD_ENDIAN_LITTLE
)
210 if (((insn
& 0xf) == 0x5) || ((insn
& 0xcf) == 0xc0))
211 winsize
= (insn
& 0x30) >> 2; /* 0, 4, 8, 12. */
215 if (((insn
>> 20) == 0x5) || (((insn
>> 16) & 0xf3) == 0x03))
216 winsize
= (insn
>> 16) & 0xc; /* 0, 4, 8, 12. */
222 /* REGISTER INFORMATION */
224 /* Find register by name. */
226 xtensa_find_register_by_name (struct gdbarch
*gdbarch
, const char *name
)
229 xtensa_gdbarch_tdep
*tdep
= (xtensa_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
231 for (i
= 0; i
< gdbarch_num_cooked_regs (gdbarch
); i
++)
232 if (strcasecmp (tdep
->regmap
[i
].name
, name
) == 0)
238 /* Returns the name of a register. */
240 xtensa_register_name (struct gdbarch
*gdbarch
, int regnum
)
242 xtensa_gdbarch_tdep
*tdep
= (xtensa_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
244 /* Return the name stored in the register map. */
245 if (regnum
>= 0 && regnum
< gdbarch_num_cooked_regs (gdbarch
))
246 return tdep
->regmap
[regnum
].name
;
248 internal_error (__FILE__
, __LINE__
, _("invalid register %d"), regnum
);
252 /* Return the type of a register. Create a new type, if necessary. */
255 xtensa_register_type (struct gdbarch
*gdbarch
, int regnum
)
257 xtensa_gdbarch_tdep
*tdep
= (xtensa_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
259 /* Return signed integer for ARx and Ax registers. */
260 if ((regnum
>= tdep
->ar_base
261 && regnum
< tdep
->ar_base
+ tdep
->num_aregs
)
262 || (regnum
>= tdep
->a0_base
263 && regnum
< tdep
->a0_base
+ 16))
264 return builtin_type (gdbarch
)->builtin_int
;
266 if (regnum
== gdbarch_pc_regnum (gdbarch
)
267 || regnum
== tdep
->a0_base
+ 1)
268 return builtin_type (gdbarch
)->builtin_data_ptr
;
270 /* Return the stored type for all other registers. */
271 else if (regnum
>= 0 && regnum
< gdbarch_num_cooked_regs (gdbarch
))
273 xtensa_register_t
* reg
= &tdep
->regmap
[regnum
];
275 /* Set ctype for this register (only the first time). */
279 struct ctype_cache
*tp
;
280 int size
= reg
->byte_size
;
282 /* We always use the memory representation,
283 even if the register width is smaller. */
287 reg
->ctype
= builtin_type (gdbarch
)->builtin_uint8
;
291 reg
->ctype
= builtin_type (gdbarch
)->builtin_uint16
;
295 reg
->ctype
= builtin_type (gdbarch
)->builtin_uint32
;
299 reg
->ctype
= builtin_type (gdbarch
)->builtin_uint64
;
303 reg
->ctype
= builtin_type (gdbarch
)->builtin_uint128
;
307 for (tp
= tdep
->type_entries
; tp
!= NULL
; tp
= tp
->next
)
308 if (tp
->size
== size
)
313 std::string name
= string_printf ("int%d", size
* 8);
315 tp
= XNEW (struct ctype_cache
);
316 tp
->next
= tdep
->type_entries
;
317 tdep
->type_entries
= tp
;
320 = arch_integer_type (gdbarch
, size
* 8, 1, name
.c_str ());
323 reg
->ctype
= tp
->virtual_type
;
329 internal_error (__FILE__
, __LINE__
, _("invalid register number %d"), regnum
);
334 /* Return the 'local' register number for stubs, dwarf2, etc.
335 The debugging information enumerates registers starting from 0 for A0
336 to n for An. So, we only have to add the base number for A0. */
339 xtensa_reg_to_regnum (struct gdbarch
*gdbarch
, int regnum
)
342 xtensa_gdbarch_tdep
*tdep
= (xtensa_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
344 if (regnum
>= 0 && regnum
< 16)
345 return tdep
->a0_base
+ regnum
;
347 for (i
= 0; i
< gdbarch_num_cooked_regs (gdbarch
); i
++)
348 if (regnum
== tdep
->regmap
[i
].target_number
)
355 /* Write the bits of a masked register to the various registers.
356 Only the masked areas of these registers are modified; the other
357 fields are untouched. The size of masked registers is always less
358 than or equal to 32 bits. */
361 xtensa_register_write_masked (struct regcache
*regcache
,
362 xtensa_register_t
*reg
, const gdb_byte
*buffer
)
364 unsigned int value
[(XTENSA_MAX_REGISTER_SIZE
+ 3) / 4];
365 const xtensa_mask_t
*mask
= reg
->mask
;
367 int shift
= 0; /* Shift for next mask (mod 32). */
368 int start
, size
; /* Start bit and size of current mask. */
370 unsigned int *ptr
= value
;
371 unsigned int regval
, m
, mem
= 0;
373 int bytesize
= reg
->byte_size
;
374 int bitsize
= bytesize
* 8;
377 DEBUGTRACE ("xtensa_register_write_masked ()\n");
379 /* Copy the masked register to host byte-order. */
380 if (gdbarch_byte_order (regcache
->arch ()) == BFD_ENDIAN_BIG
)
381 for (i
= 0; i
< bytesize
; i
++)
384 mem
|= (buffer
[bytesize
- i
- 1] << 24);
389 for (i
= 0; i
< bytesize
; i
++)
392 mem
|= (buffer
[i
] << 24);
397 /* We might have to shift the final value:
398 bytesize & 3 == 0 -> nothing to do, we use the full 32 bits,
399 bytesize & 3 == x -> shift (4-x) * 8. */
401 *ptr
= mem
>> (((0 - bytesize
) & 3) * 8);
405 /* Write the bits to the masked areas of the other registers. */
406 for (i
= 0; i
< mask
->count
; i
++)
408 start
= mask
->mask
[i
].bit_start
;
409 size
= mask
->mask
[i
].bit_size
;
410 regval
= mem
>> shift
;
412 if ((shift
+= size
) > bitsize
)
413 error (_("size of all masks is larger than the register"));
422 regval
|= mem
<< (size
- shift
);
425 /* Make sure we have a valid register. */
426 r
= mask
->mask
[i
].reg_num
;
427 if (r
>= 0 && size
> 0)
429 /* Don't overwrite the unmasked areas. */
431 regcache_cooked_read_unsigned (regcache
, r
, &old_val
);
432 m
= 0xffffffff >> (32 - size
) << start
;
434 regval
= (regval
& m
) | (old_val
& ~m
);
435 regcache_cooked_write_unsigned (regcache
, r
, regval
);
441 /* Read a tie state or mapped registers. Read the masked areas
442 of the registers and assemble them into a single value. */
444 static enum register_status
445 xtensa_register_read_masked (readable_regcache
*regcache
,
446 xtensa_register_t
*reg
, gdb_byte
*buffer
)
448 unsigned int value
[(XTENSA_MAX_REGISTER_SIZE
+ 3) / 4];
449 const xtensa_mask_t
*mask
= reg
->mask
;
454 unsigned int *ptr
= value
;
455 unsigned int regval
, mem
= 0;
457 int bytesize
= reg
->byte_size
;
458 int bitsize
= bytesize
* 8;
461 DEBUGTRACE ("xtensa_register_read_masked (reg \"%s\", ...)\n",
462 reg
->name
== 0 ? "" : reg
->name
);
464 /* Assemble the register from the masked areas of other registers. */
465 for (i
= 0; i
< mask
->count
; i
++)
467 int r
= mask
->mask
[i
].reg_num
;
470 enum register_status status
;
473 status
= regcache
->cooked_read (r
, &val
);
474 if (status
!= REG_VALID
)
476 regval
= (unsigned int) val
;
481 start
= mask
->mask
[i
].bit_start
;
482 size
= mask
->mask
[i
].bit_size
;
487 regval
&= (0xffffffff >> (32 - size
));
489 mem
|= regval
<< shift
;
491 if ((shift
+= size
) > bitsize
)
492 error (_("size of all masks is larger than the register"));
503 mem
= regval
>> (size
- shift
);
510 /* Copy value to target byte order. */
514 if (gdbarch_byte_order (regcache
->arch ()) == BFD_ENDIAN_BIG
)
515 for (i
= 0; i
< bytesize
; i
++)
519 buffer
[bytesize
- i
- 1] = mem
& 0xff;
523 for (i
= 0; i
< bytesize
; i
++)
527 buffer
[i
] = mem
& 0xff;
535 /* Read pseudo registers. */
537 static enum register_status
538 xtensa_pseudo_register_read (struct gdbarch
*gdbarch
,
539 readable_regcache
*regcache
,
543 DEBUGTRACE ("xtensa_pseudo_register_read (... regnum = %d (%s) ...)\n",
544 regnum
, xtensa_register_name (gdbarch
, regnum
));
545 xtensa_gdbarch_tdep
*tdep
= (xtensa_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
547 /* Read aliases a0..a15, if this is a Windowed ABI. */
548 if (tdep
->isa_use_windowed_registers
549 && (regnum
>= tdep
->a0_base
)
550 && (regnum
<= tdep
->a0_base
+ 15))
553 enum register_status status
;
555 status
= regcache
->raw_read (tdep
->wb_regnum
,
557 if (status
!= REG_VALID
)
559 regnum
= arreg_number (gdbarch
, regnum
, value
);
562 /* We can always read non-pseudo registers. */
563 if (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
))
564 return regcache
->raw_read (regnum
, buffer
);
566 /* We have to find out how to deal with priveleged registers.
567 Let's treat them as pseudo-registers, but we cannot read/write them. */
569 else if (tdep
->call_abi
== CallAbiCall0Only
570 || regnum
< tdep
->a0_base
)
572 buffer
[0] = (gdb_byte
)0;
573 buffer
[1] = (gdb_byte
)0;
574 buffer
[2] = (gdb_byte
)0;
575 buffer
[3] = (gdb_byte
)0;
578 /* Pseudo registers. */
579 else if (regnum
>= 0 && regnum
< gdbarch_num_cooked_regs (gdbarch
))
581 xtensa_register_t
*reg
= &tdep
->regmap
[regnum
];
582 xtensa_register_type_t type
= reg
->type
;
583 int flags
= tdep
->target_flags
;
585 /* We cannot read Unknown or Unmapped registers. */
586 if (type
== xtRegisterTypeUnmapped
|| type
== xtRegisterTypeUnknown
)
588 if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
590 warning (_("cannot read register %s"),
591 xtensa_register_name (gdbarch
, regnum
));
596 /* Some targets cannot read TIE register files. */
597 else if (type
== xtRegisterTypeTieRegfile
)
599 /* Use 'fetch' to get register? */
600 if (flags
& xtTargetFlagsUseFetchStore
)
602 warning (_("cannot read register"));
606 /* On some targets (esp. simulators), we can always read the reg. */
607 else if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
609 warning (_("cannot read register"));
614 /* We can always read mapped registers. */
615 else if (type
== xtRegisterTypeMapped
|| type
== xtRegisterTypeTieState
)
616 return xtensa_register_read_masked (regcache
, reg
, buffer
);
618 /* Assume that we can read the register. */
619 return regcache
->raw_read (regnum
, buffer
);
622 internal_error (__FILE__
, __LINE__
,
623 _("invalid register number %d"), regnum
);
627 /* Write pseudo registers. */
630 xtensa_pseudo_register_write (struct gdbarch
*gdbarch
,
631 struct regcache
*regcache
,
633 const gdb_byte
*buffer
)
635 DEBUGTRACE ("xtensa_pseudo_register_write (... regnum = %d (%s) ...)\n",
636 regnum
, xtensa_register_name (gdbarch
, regnum
));
637 xtensa_gdbarch_tdep
*tdep
= (xtensa_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
639 /* Renumber register, if aliases a0..a15 on Windowed ABI. */
640 if (tdep
->isa_use_windowed_registers
641 && (regnum
>= tdep
->a0_base
)
642 && (regnum
<= tdep
->a0_base
+ 15))
645 regcache_raw_read_unsigned (regcache
,
646 tdep
->wb_regnum
, &value
);
647 regnum
= arreg_number (gdbarch
, regnum
, value
);
650 /* We can always write 'core' registers.
651 Note: We might have converted Ax->ARy. */
652 if (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
))
653 regcache
->raw_write (regnum
, buffer
);
655 /* We have to find out how to deal with priveleged registers.
656 Let's treat them as pseudo-registers, but we cannot read/write them. */
658 else if (regnum
< tdep
->a0_base
)
662 /* Pseudo registers. */
663 else if (regnum
>= 0 && regnum
< gdbarch_num_cooked_regs (gdbarch
))
665 xtensa_register_t
*reg
= &tdep
->regmap
[regnum
];
666 xtensa_register_type_t type
= reg
->type
;
667 int flags
= tdep
->target_flags
;
669 /* On most targets, we cannot write registers
670 of type "Unknown" or "Unmapped". */
671 if (type
== xtRegisterTypeUnmapped
|| type
== xtRegisterTypeUnknown
)
673 if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
675 warning (_("cannot write register %s"),
676 xtensa_register_name (gdbarch
, regnum
));
681 /* Some targets cannot read TIE register files. */
682 else if (type
== xtRegisterTypeTieRegfile
)
684 /* Use 'store' to get register? */
685 if (flags
& xtTargetFlagsUseFetchStore
)
687 warning (_("cannot write register"));
691 /* On some targets (esp. simulators), we can always write
693 else if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
695 warning (_("cannot write register"));
700 /* We can always write mapped registers. */
701 else if (type
== xtRegisterTypeMapped
|| type
== xtRegisterTypeTieState
)
703 xtensa_register_write_masked (regcache
, reg
, buffer
);
707 /* Assume that we can write the register. */
708 regcache
->raw_write (regnum
, buffer
);
711 internal_error (__FILE__
, __LINE__
,
712 _("invalid register number %d"), regnum
);
715 static struct reggroup
*xtensa_ar_reggroup
;
716 static struct reggroup
*xtensa_user_reggroup
;
717 static struct reggroup
*xtensa_vectra_reggroup
;
718 static struct reggroup
*xtensa_cp
[XTENSA_MAX_COPROCESSOR
];
721 xtensa_init_reggroups (void)
725 xtensa_ar_reggroup
= reggroup_new ("ar", USER_REGGROUP
);
726 xtensa_user_reggroup
= reggroup_new ("user", USER_REGGROUP
);
727 xtensa_vectra_reggroup
= reggroup_new ("vectra", USER_REGGROUP
);
729 for (i
= 0; i
< XTENSA_MAX_COPROCESSOR
; i
++)
730 xtensa_cp
[i
] = reggroup_new (xstrprintf ("cp%d", i
), USER_REGGROUP
);
734 xtensa_add_reggroups (struct gdbarch
*gdbarch
)
738 /* Predefined groups. */
739 reggroup_add (gdbarch
, all_reggroup
);
740 reggroup_add (gdbarch
, save_reggroup
);
741 reggroup_add (gdbarch
, restore_reggroup
);
742 reggroup_add (gdbarch
, system_reggroup
);
743 reggroup_add (gdbarch
, vector_reggroup
);
744 reggroup_add (gdbarch
, general_reggroup
);
745 reggroup_add (gdbarch
, float_reggroup
);
747 /* Xtensa-specific groups. */
748 reggroup_add (gdbarch
, xtensa_ar_reggroup
);
749 reggroup_add (gdbarch
, xtensa_user_reggroup
);
750 reggroup_add (gdbarch
, xtensa_vectra_reggroup
);
752 for (i
= 0; i
< XTENSA_MAX_COPROCESSOR
; i
++)
753 reggroup_add (gdbarch
, xtensa_cp
[i
]);
757 xtensa_coprocessor_register_group (struct reggroup
*group
)
761 for (i
= 0; i
< XTENSA_MAX_COPROCESSOR
; i
++)
762 if (group
== xtensa_cp
[i
])
768 #define SAVE_REST_FLAGS (XTENSA_REGISTER_FLAGS_READABLE \
769 | XTENSA_REGISTER_FLAGS_WRITABLE \
770 | XTENSA_REGISTER_FLAGS_VOLATILE)
772 #define SAVE_REST_VALID (XTENSA_REGISTER_FLAGS_READABLE \
773 | XTENSA_REGISTER_FLAGS_WRITABLE)
776 xtensa_register_reggroup_p (struct gdbarch
*gdbarch
,
778 struct reggroup
*group
)
780 xtensa_gdbarch_tdep
*tdep
= (xtensa_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
781 xtensa_register_t
* reg
= &tdep
->regmap
[regnum
];
782 xtensa_register_type_t type
= reg
->type
;
783 xtensa_register_group_t rg
= reg
->group
;
786 if (group
== save_reggroup
)
787 /* Every single register should be included into the list of registers
788 to be watched for changes while using -data-list-changed-registers. */
791 /* First, skip registers that are not visible to this target
792 (unknown and unmapped registers when not using ISS). */
794 if (type
== xtRegisterTypeUnmapped
|| type
== xtRegisterTypeUnknown
)
796 if (group
== all_reggroup
)
798 if (group
== xtensa_ar_reggroup
)
799 return rg
& xtRegisterGroupAddrReg
;
800 if (group
== xtensa_user_reggroup
)
801 return rg
& xtRegisterGroupUser
;
802 if (group
== float_reggroup
)
803 return rg
& xtRegisterGroupFloat
;
804 if (group
== general_reggroup
)
805 return rg
& xtRegisterGroupGeneral
;
806 if (group
== system_reggroup
)
807 return rg
& xtRegisterGroupState
;
808 if (group
== vector_reggroup
|| group
== xtensa_vectra_reggroup
)
809 return rg
& xtRegisterGroupVectra
;
810 if (group
== restore_reggroup
)
811 return (regnum
< gdbarch_num_regs (gdbarch
)
812 && (reg
->flags
& SAVE_REST_FLAGS
) == SAVE_REST_VALID
);
813 cp_number
= xtensa_coprocessor_register_group (group
);
815 return rg
& (xtRegisterGroupCP0
<< cp_number
);
821 /* Supply register REGNUM from the buffer specified by GREGS and LEN
822 in the general-purpose register set REGSET to register cache
823 REGCACHE. If REGNUM is -1 do this for all registers in REGSET. */
826 xtensa_supply_gregset (const struct regset
*regset
,
832 const xtensa_elf_gregset_t
*regs
= (const xtensa_elf_gregset_t
*) gregs
;
833 struct gdbarch
*gdbarch
= rc
->arch ();
834 xtensa_gdbarch_tdep
*tdep
= (xtensa_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
837 DEBUGTRACE ("xtensa_supply_gregset (..., regnum==%d, ...)\n", regnum
);
839 if (regnum
== gdbarch_pc_regnum (gdbarch
) || regnum
== -1)
840 rc
->raw_supply (gdbarch_pc_regnum (gdbarch
), (char *) ®s
->pc
);
841 if (regnum
== gdbarch_ps_regnum (gdbarch
) || regnum
== -1)
842 rc
->raw_supply (gdbarch_ps_regnum (gdbarch
), (char *) ®s
->ps
);
843 if (regnum
== tdep
->wb_regnum
|| regnum
== -1)
844 rc
->raw_supply (tdep
->wb_regnum
,
845 (char *) ®s
->windowbase
);
846 if (regnum
== tdep
->ws_regnum
|| regnum
== -1)
847 rc
->raw_supply (tdep
->ws_regnum
,
848 (char *) ®s
->windowstart
);
849 if (regnum
== tdep
->lbeg_regnum
|| regnum
== -1)
850 rc
->raw_supply (tdep
->lbeg_regnum
,
851 (char *) ®s
->lbeg
);
852 if (regnum
== tdep
->lend_regnum
|| regnum
== -1)
853 rc
->raw_supply (tdep
->lend_regnum
,
854 (char *) ®s
->lend
);
855 if (regnum
== tdep
->lcount_regnum
|| regnum
== -1)
856 rc
->raw_supply (tdep
->lcount_regnum
,
857 (char *) ®s
->lcount
);
858 if (regnum
== tdep
->sar_regnum
|| regnum
== -1)
859 rc
->raw_supply (tdep
->sar_regnum
,
860 (char *) ®s
->sar
);
861 if (regnum
>=tdep
->ar_base
862 && regnum
< tdep
->ar_base
865 (regnum
, (char *) ®s
->ar
[regnum
- tdep
->ar_base
]);
866 else if (regnum
== -1)
868 for (i
= 0; i
< tdep
->num_aregs
; ++i
)
869 rc
->raw_supply (tdep
->ar_base
+ i
,
870 (char *) ®s
->ar
[i
]);
875 /* Xtensa register set. */
881 xtensa_supply_gregset
885 /* Iterate over supported core file register note sections. */
888 xtensa_iterate_over_regset_sections (struct gdbarch
*gdbarch
,
889 iterate_over_regset_sections_cb
*cb
,
891 const struct regcache
*regcache
)
893 DEBUGTRACE ("xtensa_iterate_over_regset_sections\n");
895 cb (".reg", sizeof (xtensa_elf_gregset_t
), sizeof (xtensa_elf_gregset_t
),
896 &xtensa_gregset
, NULL
, cb_data
);
900 /* Handling frames. */
902 /* Number of registers to save in case of Windowed ABI. */
903 #define XTENSA_NUM_SAVED_AREGS 12
905 /* Frame cache part for Windowed ABI. */
906 typedef struct xtensa_windowed_frame_cache
908 int wb
; /* WINDOWBASE of the previous frame. */
909 int callsize
; /* Call size of this frame. */
910 int ws
; /* WINDOWSTART of the previous frame. It keeps track of
911 life windows only. If there is no bit set for the
912 window, that means it had been already spilled
913 because of window overflow. */
915 /* Addresses of spilled A-registers.
916 AREGS[i] == -1, if corresponding AR is alive. */
917 CORE_ADDR aregs
[XTENSA_NUM_SAVED_AREGS
];
918 } xtensa_windowed_frame_cache_t
;
920 /* Call0 ABI Definitions. */
922 #define C0_MAXOPDS 3 /* Maximum number of operands for prologue
924 #define C0_CLESV 12 /* Callee-saved registers are here and up. */
925 #define C0_SP 1 /* Register used as SP. */
926 #define C0_FP 15 /* Register used as FP. */
927 #define C0_RA 0 /* Register used as return address. */
928 #define C0_ARGS 2 /* Register used as first arg/retval. */
929 #define C0_NARGS 6 /* Number of A-regs for args/retvals. */
931 /* Each element of xtensa_call0_frame_cache.c0_rt[] describes for each
932 A-register where the current content of the reg came from (in terms
933 of an original reg and a constant). Negative values of c0_rt[n].fp_reg
934 mean that the original content of the register was saved to the stack.
935 c0_rt[n].fr.ofs is NOT the offset from the frame base because we don't
936 know where SP will end up until the entire prologue has been analyzed. */
938 #define C0_CONST -1 /* fr_reg value if register contains a constant. */
939 #define C0_INEXP -2 /* fr_reg value if inexpressible as reg + offset. */
940 #define C0_NOSTK -1 /* to_stk value if register has not been stored. */
942 extern xtensa_isa xtensa_default_isa
;
944 typedef struct xtensa_c0reg
946 int fr_reg
; /* original register from which register content
947 is derived, or C0_CONST, or C0_INEXP. */
948 int fr_ofs
; /* constant offset from reg, or immediate value. */
949 int to_stk
; /* offset from original SP to register (4-byte aligned),
950 or C0_NOSTK if register has not been saved. */
953 /* Frame cache part for Call0 ABI. */
954 typedef struct xtensa_call0_frame_cache
956 int c0_frmsz
; /* Stack frame size. */
957 int c0_hasfp
; /* Current frame uses frame pointer. */
958 int fp_regnum
; /* A-register used as FP. */
959 int c0_fp
; /* Actual value of frame pointer. */
960 int c0_fpalign
; /* Dynamic adjustment for the stack
961 pointer. It's an AND mask. Zero,
962 if alignment was not adjusted. */
963 int c0_old_sp
; /* In case of dynamic adjustment, it is
964 a register holding unaligned sp.
965 C0_INEXP, when undefined. */
966 int c0_sp_ofs
; /* If "c0_old_sp" was spilled it's a
967 stack offset. C0_NOSTK otherwise. */
969 xtensa_c0reg_t c0_rt
[C0_NREGS
]; /* Register tracking information. */
970 } xtensa_call0_frame_cache_t
;
972 typedef struct xtensa_frame_cache
974 CORE_ADDR base
; /* Stack pointer of this frame. */
975 CORE_ADDR pc
; /* PC of this frame at the function entry point. */
976 CORE_ADDR ra
; /* The raw return address of this frame. */
977 CORE_ADDR ps
; /* The PS register of the previous (older) frame. */
978 CORE_ADDR prev_sp
; /* Stack Pointer of the previous (older) frame. */
979 int call0
; /* It's a call0 framework (else windowed). */
982 xtensa_windowed_frame_cache_t wd
; /* call0 == false. */
983 xtensa_call0_frame_cache_t c0
; /* call0 == true. */
985 } xtensa_frame_cache_t
;
988 static struct xtensa_frame_cache
*
989 xtensa_alloc_frame_cache (int windowed
)
991 xtensa_frame_cache_t
*cache
;
994 DEBUGTRACE ("xtensa_alloc_frame_cache ()\n");
996 cache
= FRAME_OBSTACK_ZALLOC (xtensa_frame_cache_t
);
1003 cache
->call0
= !windowed
;
1006 cache
->c0
.c0_frmsz
= -1;
1007 cache
->c0
.c0_hasfp
= 0;
1008 cache
->c0
.fp_regnum
= -1;
1009 cache
->c0
.c0_fp
= -1;
1010 cache
->c0
.c0_fpalign
= 0;
1011 cache
->c0
.c0_old_sp
= C0_INEXP
;
1012 cache
->c0
.c0_sp_ofs
= C0_NOSTK
;
1014 for (i
= 0; i
< C0_NREGS
; i
++)
1016 cache
->c0
.c0_rt
[i
].fr_reg
= i
;
1017 cache
->c0
.c0_rt
[i
].fr_ofs
= 0;
1018 cache
->c0
.c0_rt
[i
].to_stk
= C0_NOSTK
;
1025 cache
->wd
.callsize
= -1;
1027 for (i
= 0; i
< XTENSA_NUM_SAVED_AREGS
; i
++)
1028 cache
->wd
.aregs
[i
] = -1;
1035 xtensa_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR address
)
1037 return address
& ~15;
1042 xtensa_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1047 DEBUGTRACE ("xtensa_unwind_pc (next_frame = %s)\n",
1048 host_address_to_string (next_frame
));
1050 frame_unwind_register (next_frame
, gdbarch_pc_regnum (gdbarch
), buf
);
1051 pc
= extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
1053 DEBUGINFO ("[xtensa_unwind_pc] pc = 0x%08x\n", (unsigned int) pc
);
1059 static struct frame_id
1060 xtensa_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1063 xtensa_gdbarch_tdep
*tdep
= (xtensa_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
1065 /* THIS-FRAME is a dummy frame. Return a frame ID of that frame. */
1067 pc
= get_frame_pc (this_frame
);
1068 fp
= get_frame_register_unsigned
1069 (this_frame
, tdep
->a0_base
+ 1);
1071 /* Make dummy frame ID unique by adding a constant. */
1072 return frame_id_build (fp
+ SP_ALIGNMENT
, pc
);
1075 /* Returns true, if instruction to execute next is unique to Xtensa Window
1076 Interrupt Handlers. It can only be one of L32E, S32E, RFWO, or RFWU. */
1079 xtensa_window_interrupt_insn (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1081 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1082 unsigned int insn
= read_memory_integer (pc
, 4, byte_order
);
1085 if (byte_order
== BFD_ENDIAN_BIG
)
1087 /* Check, if this is L32E or S32E. */
1088 code
= insn
& 0xf000ff00;
1089 if ((code
== 0x00009000) || (code
== 0x00009400))
1091 /* Check, if this is RFWU or RFWO. */
1092 code
= insn
& 0xffffff00;
1093 return ((code
== 0x00430000) || (code
== 0x00530000));
1097 /* Check, if this is L32E or S32E. */
1098 code
= insn
& 0x00ff000f;
1099 if ((code
== 0x090000) || (code
== 0x490000))
1101 /* Check, if this is RFWU or RFWO. */
1102 code
= insn
& 0x00ffffff;
1103 return ((code
== 0x00003400) || (code
== 0x00003500));
1107 /* Returns the best guess about which register is a frame pointer
1108 for the function containing CURRENT_PC. */
1110 #define XTENSA_ISA_BSZ 32 /* Instruction buffer size. */
1111 #define XTENSA_ISA_BADPC ((CORE_ADDR)0) /* Bad PC value. */
1114 xtensa_scan_prologue (struct gdbarch
*gdbarch
, CORE_ADDR current_pc
)
1116 #define RETURN_FP goto done
1118 xtensa_gdbarch_tdep
*tdep
= (xtensa_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
1119 unsigned int fp_regnum
= tdep
->a0_base
+ 1;
1120 CORE_ADDR start_addr
;
1122 xtensa_insnbuf ins
, slot
;
1123 gdb_byte ibuf
[XTENSA_ISA_BSZ
];
1124 CORE_ADDR ia
, bt
, ba
;
1126 int ilen
, islots
, is
;
1128 const char *opcname
;
1130 find_pc_partial_function (current_pc
, NULL
, &start_addr
, NULL
);
1131 if (start_addr
== 0)
1134 isa
= xtensa_default_isa
;
1135 gdb_assert (XTENSA_ISA_BSZ
>= xtensa_isa_maxlength (isa
));
1136 ins
= xtensa_insnbuf_alloc (isa
);
1137 slot
= xtensa_insnbuf_alloc (isa
);
1140 for (ia
= start_addr
, bt
= ia
; ia
< current_pc
; ia
+= ilen
)
1142 if (ia
+ xtensa_isa_maxlength (isa
) > bt
)
1145 bt
= (ba
+ XTENSA_ISA_BSZ
) < current_pc
1146 ? ba
+ XTENSA_ISA_BSZ
: current_pc
;
1147 if (target_read_memory (ba
, ibuf
, bt
- ba
) != 0)
1151 xtensa_insnbuf_from_chars (isa
, ins
, &ibuf
[ia
-ba
], 0);
1152 ifmt
= xtensa_format_decode (isa
, ins
);
1153 if (ifmt
== XTENSA_UNDEFINED
)
1155 ilen
= xtensa_format_length (isa
, ifmt
);
1156 if (ilen
== XTENSA_UNDEFINED
)
1158 islots
= xtensa_format_num_slots (isa
, ifmt
);
1159 if (islots
== XTENSA_UNDEFINED
)
1162 for (is
= 0; is
< islots
; ++is
)
1164 if (xtensa_format_get_slot (isa
, ifmt
, is
, ins
, slot
))
1167 opc
= xtensa_opcode_decode (isa
, ifmt
, is
, slot
);
1168 if (opc
== XTENSA_UNDEFINED
)
1171 opcname
= xtensa_opcode_name (isa
, opc
);
1173 if (strcasecmp (opcname
, "mov.n") == 0
1174 || strcasecmp (opcname
, "or") == 0)
1176 unsigned int register_operand
;
1178 /* Possible candidate for setting frame pointer
1179 from A1. This is what we are looking for. */
1181 if (xtensa_operand_get_field (isa
, opc
, 1, ifmt
,
1182 is
, slot
, ®ister_operand
) != 0)
1184 if (xtensa_operand_decode (isa
, opc
, 1, ®ister_operand
) != 0)
1186 if (register_operand
== 1) /* Mov{.n} FP A1. */
1188 if (xtensa_operand_get_field (isa
, opc
, 0, ifmt
, is
, slot
,
1189 ®ister_operand
) != 0)
1191 if (xtensa_operand_decode (isa
, opc
, 0,
1192 ®ister_operand
) != 0)
1196 = tdep
->a0_base
+ register_operand
;
1202 /* We have problems decoding the memory. */
1204 || strcasecmp (opcname
, "ill") == 0
1205 || strcasecmp (opcname
, "ill.n") == 0
1206 /* Hit planted breakpoint. */
1207 || strcasecmp (opcname
, "break") == 0
1208 || strcasecmp (opcname
, "break.n") == 0
1209 /* Flow control instructions finish prologue. */
1210 || xtensa_opcode_is_branch (isa
, opc
) > 0
1211 || xtensa_opcode_is_jump (isa
, opc
) > 0
1212 || xtensa_opcode_is_loop (isa
, opc
) > 0
1213 || xtensa_opcode_is_call (isa
, opc
) > 0
1214 || strcasecmp (opcname
, "simcall") == 0
1215 || strcasecmp (opcname
, "syscall") == 0)
1216 /* Can not continue analysis. */
1221 xtensa_insnbuf_free(isa
, slot
);
1222 xtensa_insnbuf_free(isa
, ins
);
1226 /* The key values to identify the frame using "cache" are
1228 cache->base = SP (or best guess about FP) of this frame;
1229 cache->pc = entry-PC (entry point of the frame function);
1230 cache->prev_sp = SP of the previous frame. */
1233 call0_frame_cache (struct frame_info
*this_frame
,
1234 xtensa_frame_cache_t
*cache
, CORE_ADDR pc
);
1237 xtensa_window_interrupt_frame_cache (struct frame_info
*this_frame
,
1238 xtensa_frame_cache_t
*cache
,
1241 static struct xtensa_frame_cache
*
1242 xtensa_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1244 xtensa_frame_cache_t
*cache
;
1245 CORE_ADDR ra
, wb
, ws
, pc
, sp
, ps
;
1246 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1247 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1248 unsigned int fp_regnum
;
1249 int windowed
, ps_regnum
;
1252 return (struct xtensa_frame_cache
*) *this_cache
;
1254 pc
= get_frame_register_unsigned (this_frame
, gdbarch_pc_regnum (gdbarch
));
1255 ps_regnum
= gdbarch_ps_regnum (gdbarch
);
1256 ps
= (ps_regnum
>= 0
1257 ? get_frame_register_unsigned (this_frame
, ps_regnum
) : TX_PS
);
1259 windowed
= windowing_enabled (gdbarch
, ps
);
1261 /* Get pristine xtensa-frame. */
1262 cache
= xtensa_alloc_frame_cache (windowed
);
1263 *this_cache
= cache
;
1268 xtensa_gdbarch_tdep
*tdep
= (xtensa_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
1270 /* Get WINDOWBASE, WINDOWSTART, and PS registers. */
1271 wb
= get_frame_register_unsigned (this_frame
,
1273 ws
= get_frame_register_unsigned (this_frame
,
1276 if (safe_read_memory_integer (pc
, 1, byte_order
, &op1
)
1277 && XTENSA_IS_ENTRY (gdbarch
, op1
))
1279 int callinc
= CALLINC (ps
);
1280 ra
= get_frame_register_unsigned
1281 (this_frame
, tdep
->a0_base
+ callinc
* 4);
1283 /* ENTRY hasn't been executed yet, therefore callsize is still 0. */
1284 cache
->wd
.callsize
= 0;
1287 cache
->prev_sp
= get_frame_register_unsigned
1288 (this_frame
, tdep
->a0_base
+ 1);
1290 /* This only can be the outermost frame since we are
1291 just about to execute ENTRY. SP hasn't been set yet.
1292 We can assume any frame size, because it does not
1293 matter, and, let's fake frame base in cache. */
1294 cache
->base
= cache
->prev_sp
- 16;
1297 cache
->ra
= (cache
->pc
& 0xc0000000) | (ra
& 0x3fffffff);
1298 cache
->ps
= (ps
& ~PS_CALLINC_MASK
)
1299 | ((WINSIZE(ra
)/4) << PS_CALLINC_SHIFT
);
1305 fp_regnum
= xtensa_scan_prologue (gdbarch
, pc
);
1306 ra
= get_frame_register_unsigned (this_frame
,
1308 cache
->wd
.callsize
= WINSIZE (ra
);
1309 cache
->wd
.wb
= (wb
- cache
->wd
.callsize
/ 4)
1310 & (tdep
->num_aregs
/ 4 - 1);
1311 cache
->wd
.ws
= ws
& ~(1 << wb
);
1313 cache
->pc
= get_frame_func (this_frame
);
1314 cache
->ra
= (pc
& 0xc0000000) | (ra
& 0x3fffffff);
1315 cache
->ps
= (ps
& ~PS_CALLINC_MASK
)
1316 | ((WINSIZE(ra
)/4) << PS_CALLINC_SHIFT
);
1319 if (cache
->wd
.ws
== 0)
1324 sp
= get_frame_register_unsigned
1325 (this_frame
, tdep
->a0_base
+ 1) - 16;
1327 for (i
= 0; i
< 4; i
++, sp
+= 4)
1329 cache
->wd
.aregs
[i
] = sp
;
1332 if (cache
->wd
.callsize
> 4)
1334 /* Set A4...A7/A11. */
1335 /* Get the SP of the frame previous to the previous one.
1336 To achieve this, we have to dereference SP twice. */
1337 sp
= (CORE_ADDR
) read_memory_integer (sp
- 12, 4, byte_order
);
1338 sp
= (CORE_ADDR
) read_memory_integer (sp
- 12, 4, byte_order
);
1339 sp
-= cache
->wd
.callsize
* 4;
1341 for ( i
= 4; i
< cache
->wd
.callsize
; i
++, sp
+= 4)
1343 cache
->wd
.aregs
[i
] = sp
;
1348 if ((cache
->prev_sp
== 0) && ( ra
!= 0 ))
1349 /* If RA is equal to 0 this frame is an outermost frame. Leave
1350 cache->prev_sp unchanged marking the boundary of the frame stack. */
1352 if ((cache
->wd
.ws
& (1 << cache
->wd
.wb
)) == 0)
1354 /* Register window overflow already happened.
1355 We can read caller's SP from the proper spill location. */
1356 sp
= get_frame_register_unsigned
1357 (this_frame
, tdep
->a0_base
+ 1);
1358 cache
->prev_sp
= read_memory_integer (sp
- 12, 4, byte_order
);
1362 /* Read caller's frame SP directly from the previous window. */
1363 int regnum
= arreg_number
1364 (gdbarch
, tdep
->a0_base
+ 1,
1367 cache
->prev_sp
= xtensa_read_register (regnum
);
1371 else if (xtensa_window_interrupt_insn (gdbarch
, pc
))
1373 /* Execution stopped inside Xtensa Window Interrupt Handler. */
1375 xtensa_window_interrupt_frame_cache (this_frame
, cache
, pc
);
1376 /* Everything was set already, including cache->base. */
1379 else /* Call0 framework. */
1381 call0_frame_cache (this_frame
, cache
, pc
);
1382 fp_regnum
= cache
->c0
.fp_regnum
;
1385 cache
->base
= get_frame_register_unsigned (this_frame
, fp_regnum
);
1390 static int xtensa_session_once_reported
= 1;
1392 /* Report a problem with prologue analysis while doing backtracing.
1393 But, do it only once to avoid annoying repeated messages. */
1398 if (xtensa_session_once_reported
== 0)
1400 \nUnrecognised function prologue. Stack trace cannot be resolved. \
1401 This message will not be repeated in this session.\n"));
1403 xtensa_session_once_reported
= 1;
1408 xtensa_frame_this_id (struct frame_info
*this_frame
,
1410 struct frame_id
*this_id
)
1412 struct xtensa_frame_cache
*cache
=
1413 xtensa_frame_cache (this_frame
, this_cache
);
1415 if (cache
->prev_sp
== 0)
1418 (*this_id
) = frame_id_build (cache
->prev_sp
, cache
->pc
);
1421 static struct value
*
1422 xtensa_frame_prev_register (struct frame_info
*this_frame
,
1426 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1427 struct xtensa_frame_cache
*cache
;
1428 ULONGEST saved_reg
= 0;
1430 xtensa_gdbarch_tdep
*tdep
= (xtensa_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
1432 if (*this_cache
== NULL
)
1433 *this_cache
= xtensa_frame_cache (this_frame
, this_cache
);
1434 cache
= (struct xtensa_frame_cache
*) *this_cache
;
1436 if (regnum
==gdbarch_pc_regnum (gdbarch
))
1437 saved_reg
= cache
->ra
;
1438 else if (regnum
== tdep
->a0_base
+ 1)
1439 saved_reg
= cache
->prev_sp
;
1440 else if (!cache
->call0
)
1442 if (regnum
== tdep
->ws_regnum
)
1443 saved_reg
= cache
->wd
.ws
;
1444 else if (regnum
== tdep
->wb_regnum
)
1445 saved_reg
= cache
->wd
.wb
;
1446 else if (regnum
== gdbarch_ps_regnum (gdbarch
))
1447 saved_reg
= cache
->ps
;
1455 return frame_unwind_got_constant (this_frame
, regnum
, saved_reg
);
1457 if (!cache
->call0
) /* Windowed ABI. */
1459 /* Convert A-register numbers to AR-register numbers,
1460 if we deal with A-register. */
1461 if (regnum
>= tdep
->a0_base
1462 && regnum
<= tdep
->a0_base
+ 15)
1463 regnum
= arreg_number (gdbarch
, regnum
, cache
->wd
.wb
);
1465 /* Check, if we deal with AR-register saved on stack. */
1466 if (regnum
>= tdep
->ar_base
1467 && regnum
<= (tdep
->ar_base
1470 int areg
= areg_number (gdbarch
, regnum
, cache
->wd
.wb
);
1473 && areg
< XTENSA_NUM_SAVED_AREGS
1474 && cache
->wd
.aregs
[areg
] != -1)
1475 return frame_unwind_got_memory (this_frame
, regnum
,
1476 cache
->wd
.aregs
[areg
]);
1479 else /* Call0 ABI. */
1481 int reg
= (regnum
>= tdep
->ar_base
1482 && regnum
<= (tdep
->ar_base
1484 ? regnum
- tdep
->ar_base
: regnum
;
1491 /* If register was saved in the prologue, retrieve it. */
1492 stkofs
= cache
->c0
.c0_rt
[reg
].to_stk
;
1493 if (stkofs
!= C0_NOSTK
)
1495 /* Determine SP on entry based on FP. */
1496 spe
= cache
->c0
.c0_fp
1497 - cache
->c0
.c0_rt
[cache
->c0
.fp_regnum
].fr_ofs
;
1499 return frame_unwind_got_memory (this_frame
, regnum
,
1505 /* All other registers have been either saved to
1506 the stack or are still alive in the processor. */
1508 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
1512 static const struct frame_unwind
1517 default_frame_unwind_stop_reason
,
1518 xtensa_frame_this_id
,
1519 xtensa_frame_prev_register
,
1521 default_frame_sniffer
1525 xtensa_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
1527 struct xtensa_frame_cache
*cache
=
1528 xtensa_frame_cache (this_frame
, this_cache
);
1533 static const struct frame_base
1537 xtensa_frame_base_address
,
1538 xtensa_frame_base_address
,
1539 xtensa_frame_base_address
1544 xtensa_extract_return_value (struct type
*type
,
1545 struct regcache
*regcache
,
1548 struct gdbarch
*gdbarch
= regcache
->arch ();
1549 bfd_byte
*valbuf
= (bfd_byte
*) dst
;
1550 int len
= TYPE_LENGTH (type
);
1555 DEBUGTRACE ("xtensa_extract_return_value (...)\n");
1557 gdb_assert(len
> 0);
1559 xtensa_gdbarch_tdep
*tdep
= (xtensa_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
1560 if (tdep
->call_abi
!= CallAbiCall0Only
)
1562 /* First, we have to find the caller window in the register file. */
1563 regcache_raw_read_unsigned (regcache
, gdbarch_pc_regnum (gdbarch
), &pc
);
1564 callsize
= extract_call_winsize (gdbarch
, pc
);
1566 /* On Xtensa, we can return up to 4 words (or 2 for call12). */
1567 if (len
> (callsize
> 8 ? 8 : 16))
1568 internal_error (__FILE__
, __LINE__
,
1569 _("cannot extract return value of %d bytes long"),
1572 /* Get the register offset of the return
1573 register (A2) in the caller window. */
1574 regcache_raw_read_unsigned
1575 (regcache
, tdep
->wb_regnum
, &wb
);
1576 areg
= arreg_number (gdbarch
,
1577 tdep
->a0_base
+ 2 + callsize
, wb
);
1581 /* No windowing hardware - Call0 ABI. */
1582 areg
= tdep
->a0_base
+ C0_ARGS
;
1585 DEBUGINFO ("[xtensa_extract_return_value] areg %d len %d\n", areg
, len
);
1587 if (len
< 4 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1590 for (; len
> 0; len
-= 4, areg
++, valbuf
+= 4)
1593 regcache
->raw_read_part (areg
, offset
, len
, valbuf
);
1595 regcache
->raw_read (areg
, valbuf
);
1601 xtensa_store_return_value (struct type
*type
,
1602 struct regcache
*regcache
,
1605 struct gdbarch
*gdbarch
= regcache
->arch ();
1606 const bfd_byte
*valbuf
= (const bfd_byte
*) dst
;
1610 int len
= TYPE_LENGTH (type
);
1613 DEBUGTRACE ("xtensa_store_return_value (...)\n");
1615 xtensa_gdbarch_tdep
*tdep
= (xtensa_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
1616 if (tdep
->call_abi
!= CallAbiCall0Only
)
1618 regcache_raw_read_unsigned
1619 (regcache
, tdep
->wb_regnum
, &wb
);
1620 regcache_raw_read_unsigned (regcache
, gdbarch_pc_regnum (gdbarch
), &pc
);
1621 callsize
= extract_call_winsize (gdbarch
, pc
);
1623 if (len
> (callsize
> 8 ? 8 : 16))
1624 internal_error (__FILE__
, __LINE__
,
1625 _("unimplemented for this length: %s"),
1626 pulongest (TYPE_LENGTH (type
)));
1627 areg
= arreg_number (gdbarch
,
1628 tdep
->a0_base
+ 2 + callsize
, wb
);
1630 DEBUGTRACE ("[xtensa_store_return_value] callsize %d wb %d\n",
1631 callsize
, (int) wb
);
1635 areg
= tdep
->a0_base
+ C0_ARGS
;
1638 if (len
< 4 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1641 for (; len
> 0; len
-= 4, areg
++, valbuf
+= 4)
1644 regcache
->raw_write_part (areg
, offset
, len
, valbuf
);
1646 regcache
->raw_write (areg
, valbuf
);
1651 static enum return_value_convention
1652 xtensa_return_value (struct gdbarch
*gdbarch
,
1653 struct value
*function
,
1654 struct type
*valtype
,
1655 struct regcache
*regcache
,
1657 const gdb_byte
*writebuf
)
1659 /* Structures up to 16 bytes are returned in registers. */
1661 int struct_return
= ((valtype
->code () == TYPE_CODE_STRUCT
1662 || valtype
->code () == TYPE_CODE_UNION
1663 || valtype
->code () == TYPE_CODE_ARRAY
)
1664 && TYPE_LENGTH (valtype
) > 16);
1667 return RETURN_VALUE_STRUCT_CONVENTION
;
1669 DEBUGTRACE ("xtensa_return_value(...)\n");
1671 if (writebuf
!= NULL
)
1673 xtensa_store_return_value (valtype
, regcache
, writebuf
);
1676 if (readbuf
!= NULL
)
1678 gdb_assert (!struct_return
);
1679 xtensa_extract_return_value (valtype
, regcache
, readbuf
);
1681 return RETURN_VALUE_REGISTER_CONVENTION
;
1688 xtensa_push_dummy_call (struct gdbarch
*gdbarch
,
1689 struct value
*function
,
1690 struct regcache
*regcache
,
1693 struct value
**args
,
1695 function_call_return_method return_method
,
1696 CORE_ADDR struct_addr
)
1698 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1699 xtensa_gdbarch_tdep
*tdep
= (xtensa_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
1700 int size
, onstack_size
;
1701 gdb_byte
*buf
= (gdb_byte
*) alloca (16);
1703 struct argument_info
1705 const bfd_byte
*contents
;
1707 int onstack
; /* onstack == 0 => in reg */
1708 int align
; /* alignment */
1711 int offset
; /* stack offset if on stack. */
1712 int regno
; /* regno if in register. */
1716 struct argument_info
*arg_info
=
1717 (struct argument_info
*) alloca (nargs
* sizeof (struct argument_info
));
1721 DEBUGTRACE ("xtensa_push_dummy_call (...)\n");
1723 if (xtensa_debug_level
> 3)
1725 DEBUGINFO ("[xtensa_push_dummy_call] nargs = %d\n", nargs
);
1726 DEBUGINFO ("[xtensa_push_dummy_call] sp=0x%x, return_method=%d, "
1727 "struct_addr=0x%x\n",
1728 (int) sp
, (int) return_method
, (int) struct_addr
);
1730 for (int i
= 0; i
< nargs
; i
++)
1732 struct value
*arg
= args
[i
];
1733 struct type
*arg_type
= check_typedef (value_type (arg
));
1734 fprintf_unfiltered (gdb_stdlog
, "%2d: %s %3s ", i
,
1735 host_address_to_string (arg
),
1736 pulongest (TYPE_LENGTH (arg_type
)));
1737 switch (arg_type
->code ())
1740 fprintf_unfiltered (gdb_stdlog
, "int");
1742 case TYPE_CODE_STRUCT
:
1743 fprintf_unfiltered (gdb_stdlog
, "struct");
1746 fprintf_unfiltered (gdb_stdlog
, "%3d", arg_type
->code ());
1749 fprintf_unfiltered (gdb_stdlog
, " %s\n",
1750 host_address_to_string (value_contents (arg
).data ()));
1754 /* First loop: collect information.
1755 Cast into type_long. (This shouldn't happen often for C because
1756 GDB already does this earlier.) It's possible that GDB could
1757 do it all the time but it's harmless to leave this code here. */
1762 if (return_method
== return_method_struct
)
1763 size
= REGISTER_SIZE
;
1765 for (int i
= 0; i
< nargs
; i
++)
1767 struct argument_info
*info
= &arg_info
[i
];
1768 struct value
*arg
= args
[i
];
1769 struct type
*arg_type
= check_typedef (value_type (arg
));
1771 switch (arg_type
->code ())
1774 case TYPE_CODE_BOOL
:
1775 case TYPE_CODE_CHAR
:
1776 case TYPE_CODE_RANGE
:
1777 case TYPE_CODE_ENUM
:
1779 /* Cast argument to long if necessary as the mask does it too. */
1780 if (TYPE_LENGTH (arg_type
)
1781 < TYPE_LENGTH (builtin_type (gdbarch
)->builtin_long
))
1783 arg_type
= builtin_type (gdbarch
)->builtin_long
;
1784 arg
= value_cast (arg_type
, arg
);
1786 /* Aligment is equal to the type length for the basic types. */
1787 info
->align
= TYPE_LENGTH (arg_type
);
1792 /* Align doubles correctly. */
1793 if (TYPE_LENGTH (arg_type
)
1794 == TYPE_LENGTH (builtin_type (gdbarch
)->builtin_double
))
1795 info
->align
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_double
);
1797 info
->align
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_long
);
1800 case TYPE_CODE_STRUCT
:
1802 info
->align
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_long
);
1805 info
->length
= TYPE_LENGTH (arg_type
);
1806 info
->contents
= value_contents (arg
).data ();
1808 /* Align size and onstack_size. */
1809 size
= (size
+ info
->align
- 1) & ~(info
->align
- 1);
1810 onstack_size
= (onstack_size
+ info
->align
- 1) & ~(info
->align
- 1);
1812 if (size
+ info
->length
> REGISTER_SIZE
* ARG_NOF (tdep
))
1815 info
->u
.offset
= onstack_size
;
1816 onstack_size
+= info
->length
;
1821 info
->u
.regno
= ARG_1ST (tdep
) + size
/ REGISTER_SIZE
;
1823 size
+= info
->length
;
1826 /* Adjust the stack pointer and align it. */
1827 sp
= align_down (sp
- onstack_size
, SP_ALIGNMENT
);
1829 /* Simulate MOVSP, if Windowed ABI. */
1830 if ((tdep
->call_abi
!= CallAbiCall0Only
)
1833 read_memory (osp
- 16, buf
, 16);
1834 write_memory (sp
- 16, buf
, 16);
1837 /* Second Loop: Load arguments. */
1839 if (return_method
== return_method_struct
)
1841 store_unsigned_integer (buf
, REGISTER_SIZE
, byte_order
, struct_addr
);
1842 regcache
->cooked_write (ARG_1ST (tdep
), buf
);
1845 for (int i
= 0; i
< nargs
; i
++)
1847 struct argument_info
*info
= &arg_info
[i
];
1851 int n
= info
->length
;
1852 CORE_ADDR offset
= sp
+ info
->u
.offset
;
1854 /* Odd-sized structs are aligned to the lower side of a memory
1855 word in big-endian mode and require a shift. This only
1856 applies for structures smaller than one word. */
1858 if (n
< REGISTER_SIZE
1859 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1860 offset
+= (REGISTER_SIZE
- n
);
1862 write_memory (offset
, info
->contents
, info
->length
);
1867 int n
= info
->length
;
1868 const bfd_byte
*cp
= info
->contents
;
1869 int r
= info
->u
.regno
;
1871 /* Odd-sized structs are aligned to the lower side of registers in
1872 big-endian mode and require a shift. The odd-sized leftover will
1873 be at the end. Note that this is only true for structures smaller
1874 than REGISTER_SIZE; for larger odd-sized structures the excess
1875 will be left-aligned in the register on both endiannesses. */
1877 if (n
< REGISTER_SIZE
&& byte_order
== BFD_ENDIAN_BIG
)
1880 v
= extract_unsigned_integer (cp
, REGISTER_SIZE
, byte_order
);
1881 v
= v
>> ((REGISTER_SIZE
- n
) * TARGET_CHAR_BIT
);
1883 store_unsigned_integer (buf
, REGISTER_SIZE
, byte_order
, v
);
1884 regcache
->cooked_write (r
, buf
);
1886 cp
+= REGISTER_SIZE
;
1893 regcache
->cooked_write (r
, cp
);
1895 cp
+= REGISTER_SIZE
;
1902 /* Set the return address of dummy frame to the dummy address.
1903 The return address for the current function (in A0) is
1904 saved in the dummy frame, so we can safely overwrite A0 here. */
1906 if (tdep
->call_abi
!= CallAbiCall0Only
)
1910 ra
= (bp_addr
& 0x3fffffff) | 0x40000000;
1911 regcache_raw_read_unsigned (regcache
, gdbarch_ps_regnum (gdbarch
), &val
);
1912 ps
= (unsigned long) val
& ~0x00030000;
1913 regcache_cooked_write_unsigned
1914 (regcache
, tdep
->a0_base
+ 4, ra
);
1915 regcache_cooked_write_unsigned (regcache
,
1916 gdbarch_ps_regnum (gdbarch
),
1919 /* All the registers have been saved. After executing
1920 dummy call, they all will be restored. So it's safe
1921 to modify WINDOWSTART register to make it look like there
1922 is only one register window corresponding to WINDOWEBASE. */
1924 regcache
->raw_read (tdep
->wb_regnum
, buf
);
1925 regcache_cooked_write_unsigned
1926 (regcache
, tdep
->ws_regnum
,
1927 1 << extract_unsigned_integer (buf
, 4, byte_order
));
1931 /* Simulate CALL0: write RA into A0 register. */
1932 regcache_cooked_write_unsigned
1933 (regcache
, tdep
->a0_base
, bp_addr
);
1936 /* Set new stack pointer and return it. */
1937 regcache_cooked_write_unsigned (regcache
,
1938 tdep
->a0_base
+ 1, sp
);
1939 /* Make dummy frame ID unique by adding a constant. */
1940 return sp
+ SP_ALIGNMENT
;
1943 /* Implement the breakpoint_kind_from_pc gdbarch method. */
1946 xtensa_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
1948 xtensa_gdbarch_tdep
*tdep
= (xtensa_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
1950 if (tdep
->isa_use_density_instructions
)
1956 /* Return a breakpoint for the current location of PC. We always use
1957 the density version if we have density instructions (regardless of the
1958 current instruction at PC), and use regular instructions otherwise. */
1960 #define BIG_BREAKPOINT { 0x00, 0x04, 0x00 }
1961 #define LITTLE_BREAKPOINT { 0x00, 0x40, 0x00 }
1962 #define DENSITY_BIG_BREAKPOINT { 0xd2, 0x0f }
1963 #define DENSITY_LITTLE_BREAKPOINT { 0x2d, 0xf0 }
1965 /* Implement the sw_breakpoint_from_kind gdbarch method. */
1967 static const gdb_byte
*
1968 xtensa_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
1974 static unsigned char big_breakpoint
[] = BIG_BREAKPOINT
;
1975 static unsigned char little_breakpoint
[] = LITTLE_BREAKPOINT
;
1977 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1978 return big_breakpoint
;
1980 return little_breakpoint
;
1984 static unsigned char density_big_breakpoint
[] = DENSITY_BIG_BREAKPOINT
;
1985 static unsigned char density_little_breakpoint
[]
1986 = DENSITY_LITTLE_BREAKPOINT
;
1988 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1989 return density_big_breakpoint
;
1991 return density_little_breakpoint
;
1995 /* Call0 ABI support routines. */
1997 /* Return true, if PC points to "ret" or "ret.n". */
2000 call0_ret (CORE_ADDR start_pc
, CORE_ADDR finish_pc
)
2002 #define RETURN_RET goto done
2004 xtensa_insnbuf ins
, slot
;
2005 gdb_byte ibuf
[XTENSA_ISA_BSZ
];
2006 CORE_ADDR ia
, bt
, ba
;
2008 int ilen
, islots
, is
;
2010 const char *opcname
;
2013 isa
= xtensa_default_isa
;
2014 gdb_assert (XTENSA_ISA_BSZ
>= xtensa_isa_maxlength (isa
));
2015 ins
= xtensa_insnbuf_alloc (isa
);
2016 slot
= xtensa_insnbuf_alloc (isa
);
2019 for (ia
= start_pc
, bt
= ia
; ia
< finish_pc
; ia
+= ilen
)
2021 if (ia
+ xtensa_isa_maxlength (isa
) > bt
)
2024 bt
= (ba
+ XTENSA_ISA_BSZ
) < finish_pc
2025 ? ba
+ XTENSA_ISA_BSZ
: finish_pc
;
2026 if (target_read_memory (ba
, ibuf
, bt
- ba
) != 0 )
2030 xtensa_insnbuf_from_chars (isa
, ins
, &ibuf
[ia
-ba
], 0);
2031 ifmt
= xtensa_format_decode (isa
, ins
);
2032 if (ifmt
== XTENSA_UNDEFINED
)
2034 ilen
= xtensa_format_length (isa
, ifmt
);
2035 if (ilen
== XTENSA_UNDEFINED
)
2037 islots
= xtensa_format_num_slots (isa
, ifmt
);
2038 if (islots
== XTENSA_UNDEFINED
)
2041 for (is
= 0; is
< islots
; ++is
)
2043 if (xtensa_format_get_slot (isa
, ifmt
, is
, ins
, slot
))
2046 opc
= xtensa_opcode_decode (isa
, ifmt
, is
, slot
);
2047 if (opc
== XTENSA_UNDEFINED
)
2050 opcname
= xtensa_opcode_name (isa
, opc
);
2052 if ((strcasecmp (opcname
, "ret.n") == 0)
2053 || (strcasecmp (opcname
, "ret") == 0))
2061 xtensa_insnbuf_free(isa
, slot
);
2062 xtensa_insnbuf_free(isa
, ins
);
2066 /* Call0 opcode class. Opcodes are preclassified according to what they
2067 mean for Call0 prologue analysis, and their number of significant operands.
2068 The purpose of this is to simplify prologue analysis by separating
2069 instruction decoding (libisa) from the semantics of prologue analysis. */
2073 c0opc_illegal
, /* Unknown to libisa (invalid) or 'ill' opcode. */
2074 c0opc_uninteresting
, /* Not interesting for Call0 prologue analysis. */
2075 c0opc_flow
, /* Flow control insn. */
2076 c0opc_entry
, /* ENTRY indicates non-Call0 prologue. */
2077 c0opc_break
, /* Debugger software breakpoints. */
2078 c0opc_add
, /* Adding two registers. */
2079 c0opc_addi
, /* Adding a register and an immediate. */
2080 c0opc_and
, /* Bitwise "and"-ing two registers. */
2081 c0opc_sub
, /* Subtracting a register from a register. */
2082 c0opc_mov
, /* Moving a register to a register. */
2083 c0opc_movi
, /* Moving an immediate to a register. */
2084 c0opc_l32r
, /* Loading a literal. */
2085 c0opc_s32i
, /* Storing word at fixed offset from a base register. */
2086 c0opc_rwxsr
, /* RSR, WRS, or XSR instructions. */
2087 c0opc_l32e
, /* L32E instruction. */
2088 c0opc_s32e
, /* S32E instruction. */
2089 c0opc_rfwo
, /* RFWO instruction. */
2090 c0opc_rfwu
, /* RFWU instruction. */
2091 c0opc_NrOf
/* Number of opcode classifications. */
2094 /* Return true, if OPCNAME is RSR, WRS, or XSR instruction. */
2097 rwx_special_register (const char *opcname
)
2099 char ch
= *opcname
++;
2101 if ((ch
!= 'r') && (ch
!= 'w') && (ch
!= 'x'))
2103 if (*opcname
++ != 's')
2105 if (*opcname
++ != 'r')
2107 if (*opcname
++ != '.')
2113 /* Classify an opcode based on what it means for Call0 prologue analysis. */
2115 static xtensa_insn_kind
2116 call0_classify_opcode (xtensa_isa isa
, xtensa_opcode opc
)
2118 const char *opcname
;
2119 xtensa_insn_kind opclass
= c0opc_uninteresting
;
2121 DEBUGTRACE ("call0_classify_opcode (..., opc = %d)\n", opc
);
2123 /* Get opcode name and handle special classifications. */
2125 opcname
= xtensa_opcode_name (isa
, opc
);
2128 || strcasecmp (opcname
, "ill") == 0
2129 || strcasecmp (opcname
, "ill.n") == 0)
2130 opclass
= c0opc_illegal
;
2131 else if (strcasecmp (opcname
, "break") == 0
2132 || strcasecmp (opcname
, "break.n") == 0)
2133 opclass
= c0opc_break
;
2134 else if (strcasecmp (opcname
, "entry") == 0)
2135 opclass
= c0opc_entry
;
2136 else if (strcasecmp (opcname
, "rfwo") == 0)
2137 opclass
= c0opc_rfwo
;
2138 else if (strcasecmp (opcname
, "rfwu") == 0)
2139 opclass
= c0opc_rfwu
;
2140 else if (xtensa_opcode_is_branch (isa
, opc
) > 0
2141 || xtensa_opcode_is_jump (isa
, opc
) > 0
2142 || xtensa_opcode_is_loop (isa
, opc
) > 0
2143 || xtensa_opcode_is_call (isa
, opc
) > 0
2144 || strcasecmp (opcname
, "simcall") == 0
2145 || strcasecmp (opcname
, "syscall") == 0)
2146 opclass
= c0opc_flow
;
2148 /* Also, classify specific opcodes that need to be tracked. */
2149 else if (strcasecmp (opcname
, "add") == 0
2150 || strcasecmp (opcname
, "add.n") == 0)
2151 opclass
= c0opc_add
;
2152 else if (strcasecmp (opcname
, "and") == 0)
2153 opclass
= c0opc_and
;
2154 else if (strcasecmp (opcname
, "addi") == 0
2155 || strcasecmp (opcname
, "addi.n") == 0
2156 || strcasecmp (opcname
, "addmi") == 0)
2157 opclass
= c0opc_addi
;
2158 else if (strcasecmp (opcname
, "sub") == 0)
2159 opclass
= c0opc_sub
;
2160 else if (strcasecmp (opcname
, "mov.n") == 0
2161 || strcasecmp (opcname
, "or") == 0) /* Could be 'mov' asm macro. */
2162 opclass
= c0opc_mov
;
2163 else if (strcasecmp (opcname
, "movi") == 0
2164 || strcasecmp (opcname
, "movi.n") == 0)
2165 opclass
= c0opc_movi
;
2166 else if (strcasecmp (opcname
, "l32r") == 0)
2167 opclass
= c0opc_l32r
;
2168 else if (strcasecmp (opcname
, "s32i") == 0
2169 || strcasecmp (opcname
, "s32i.n") == 0)
2170 opclass
= c0opc_s32i
;
2171 else if (strcasecmp (opcname
, "l32e") == 0)
2172 opclass
= c0opc_l32e
;
2173 else if (strcasecmp (opcname
, "s32e") == 0)
2174 opclass
= c0opc_s32e
;
2175 else if (rwx_special_register (opcname
))
2176 opclass
= c0opc_rwxsr
;
2181 /* Tracks register movement/mutation for a given operation, which may
2182 be within a bundle. Updates the destination register tracking info
2183 accordingly. The pc is needed only for pc-relative load instructions
2184 (eg. l32r). The SP register number is needed to identify stores to
2185 the stack frame. Returns 0, if analysis was successful, non-zero
2189 call0_track_op (struct gdbarch
*gdbarch
, xtensa_c0reg_t dst
[], xtensa_c0reg_t src
[],
2190 xtensa_insn_kind opclass
, int nods
, unsigned odv
[],
2191 CORE_ADDR pc
, int spreg
, xtensa_frame_cache_t
*cache
)
2193 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2194 unsigned litbase
, litaddr
, litval
;
2195 xtensa_gdbarch_tdep
*tdep
= (xtensa_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
2200 /* 3 operands: dst, src, imm. */
2201 gdb_assert (nods
== 3);
2202 dst
[odv
[0]].fr_reg
= src
[odv
[1]].fr_reg
;
2203 dst
[odv
[0]].fr_ofs
= src
[odv
[1]].fr_ofs
+ odv
[2];
2206 /* 3 operands: dst, src1, src2. */
2207 gdb_assert (nods
== 3);
2208 if (src
[odv
[1]].fr_reg
== C0_CONST
)
2210 dst
[odv
[0]].fr_reg
= src
[odv
[2]].fr_reg
;
2211 dst
[odv
[0]].fr_ofs
= src
[odv
[2]].fr_ofs
+ src
[odv
[1]].fr_ofs
;
2213 else if (src
[odv
[2]].fr_reg
== C0_CONST
)
2215 dst
[odv
[0]].fr_reg
= src
[odv
[1]].fr_reg
;
2216 dst
[odv
[0]].fr_ofs
= src
[odv
[1]].fr_ofs
+ src
[odv
[2]].fr_ofs
;
2218 else dst
[odv
[0]].fr_reg
= C0_INEXP
;
2221 /* 3 operands: dst, src1, src2. */
2222 gdb_assert (nods
== 3);
2223 if (cache
->c0
.c0_fpalign
== 0)
2225 /* Handle dynamic stack alignment. */
2226 if ((src
[odv
[0]].fr_reg
== spreg
) && (src
[odv
[1]].fr_reg
== spreg
))
2228 if (src
[odv
[2]].fr_reg
== C0_CONST
)
2229 cache
->c0
.c0_fpalign
= src
[odv
[2]].fr_ofs
;
2232 else if ((src
[odv
[0]].fr_reg
== spreg
)
2233 && (src
[odv
[2]].fr_reg
== spreg
))
2235 if (src
[odv
[1]].fr_reg
== C0_CONST
)
2236 cache
->c0
.c0_fpalign
= src
[odv
[1]].fr_ofs
;
2239 /* else fall through. */
2241 if (src
[odv
[1]].fr_reg
== C0_CONST
)
2243 dst
[odv
[0]].fr_reg
= src
[odv
[2]].fr_reg
;
2244 dst
[odv
[0]].fr_ofs
= src
[odv
[2]].fr_ofs
& src
[odv
[1]].fr_ofs
;
2246 else if (src
[odv
[2]].fr_reg
== C0_CONST
)
2248 dst
[odv
[0]].fr_reg
= src
[odv
[1]].fr_reg
;
2249 dst
[odv
[0]].fr_ofs
= src
[odv
[1]].fr_ofs
& src
[odv
[2]].fr_ofs
;
2251 else dst
[odv
[0]].fr_reg
= C0_INEXP
;
2254 /* 3 operands: dst, src1, src2. */
2255 gdb_assert (nods
== 3);
2256 if (src
[odv
[2]].fr_reg
== C0_CONST
)
2258 dst
[odv
[0]].fr_reg
= src
[odv
[1]].fr_reg
;
2259 dst
[odv
[0]].fr_ofs
= src
[odv
[1]].fr_ofs
- src
[odv
[2]].fr_ofs
;
2261 else dst
[odv
[0]].fr_reg
= C0_INEXP
;
2264 /* 2 operands: dst, src [, src]. */
2265 gdb_assert (nods
== 2);
2266 /* First, check if it's a special case of saving unaligned SP
2267 to a spare register in case of dynamic stack adjustment.
2268 But, only do it one time. The second time could be initializing
2269 frame pointer. We don't want to overwrite the first one. */
2270 if ((odv
[1] == spreg
) && (cache
->c0
.c0_old_sp
== C0_INEXP
))
2271 cache
->c0
.c0_old_sp
= odv
[0];
2273 dst
[odv
[0]].fr_reg
= src
[odv
[1]].fr_reg
;
2274 dst
[odv
[0]].fr_ofs
= src
[odv
[1]].fr_ofs
;
2277 /* 2 operands: dst, imm. */
2278 gdb_assert (nods
== 2);
2279 dst
[odv
[0]].fr_reg
= C0_CONST
;
2280 dst
[odv
[0]].fr_ofs
= odv
[1];
2283 /* 2 operands: dst, literal offset. */
2284 gdb_assert (nods
== 2);
2285 /* litbase = xtensa_get_litbase (pc); can be also used. */
2286 litbase
= (tdep
->litbase_regnum
== -1)
2287 ? 0 : xtensa_read_register
2288 (tdep
->litbase_regnum
);
2289 litaddr
= litbase
& 1
2290 ? (litbase
& ~1) + (signed)odv
[1]
2291 : (pc
+ 3 + (signed)odv
[1]) & ~3;
2292 litval
= read_memory_integer (litaddr
, 4, byte_order
);
2293 dst
[odv
[0]].fr_reg
= C0_CONST
;
2294 dst
[odv
[0]].fr_ofs
= litval
;
2297 /* 3 operands: value, base, offset. */
2298 gdb_assert (nods
== 3 && spreg
>= 0 && spreg
< C0_NREGS
);
2299 /* First, check if it's a spill for saved unaligned SP,
2300 when dynamic stack adjustment was applied to this frame. */
2301 if ((cache
->c0
.c0_fpalign
!= 0) /* Dynamic stack adjustment. */
2302 && (odv
[1] == spreg
) /* SP usage indicates spill. */
2303 && (odv
[0] == cache
->c0
.c0_old_sp
)) /* Old SP register spilled. */
2304 cache
->c0
.c0_sp_ofs
= odv
[2];
2306 if (src
[odv
[1]].fr_reg
== spreg
/* Store to stack frame. */
2307 && (src
[odv
[1]].fr_ofs
& 3) == 0 /* Alignment preserved. */
2308 && src
[odv
[0]].fr_reg
>= 0 /* Value is from a register. */
2309 && src
[odv
[0]].fr_ofs
== 0 /* Value hasn't been modified. */
2310 && src
[src
[odv
[0]].fr_reg
].to_stk
== C0_NOSTK
) /* First time. */
2312 /* ISA encoding guarantees alignment. But, check it anyway. */
2313 gdb_assert ((odv
[2] & 3) == 0);
2314 dst
[src
[odv
[0]].fr_reg
].to_stk
= src
[odv
[1]].fr_ofs
+ odv
[2];
2317 /* If we end up inside Window Overflow / Underflow interrupt handler
2318 report an error because these handlers should have been handled
2319 already in a different way. */
2331 /* Analyze prologue of the function at start address to determine if it uses
2332 the Call0 ABI, and if so track register moves and linear modifications
2333 in the prologue up to the PC or just beyond the prologue, whichever is
2334 first. An 'entry' instruction indicates non-Call0 ABI and the end of the
2335 prologue. The prologue may overlap non-prologue instructions but is
2336 guaranteed to end by the first flow-control instruction (jump, branch,
2337 call or return). Since an optimized function may move information around
2338 and change the stack frame arbitrarily during the prologue, the information
2339 is guaranteed valid only at the point in the function indicated by the PC.
2340 May be used to skip the prologue or identify the ABI, w/o tracking.
2342 Returns: Address of first instruction after prologue, or PC (whichever
2343 is first), or 0, if decoding failed (in libisa).
2345 start Start address of function/prologue.
2346 pc Program counter to stop at. Use 0 to continue to end of prologue.
2347 If 0, avoids infinite run-on in corrupt code memory by bounding
2348 the scan to the end of the function if that can be determined.
2349 nregs Number of general registers to track.
2351 cache Xtensa frame cache.
2353 Note that these may produce useful results even if decoding fails
2354 because they begin with default assumptions that analysis may change. */
2357 call0_analyze_prologue (struct gdbarch
*gdbarch
,
2358 CORE_ADDR start
, CORE_ADDR pc
,
2359 int nregs
, xtensa_frame_cache_t
*cache
)
2361 CORE_ADDR ia
; /* Current insn address in prologue. */
2362 CORE_ADDR ba
= 0; /* Current address at base of insn buffer. */
2363 CORE_ADDR bt
; /* Current address at top+1 of insn buffer. */
2364 gdb_byte ibuf
[XTENSA_ISA_BSZ
];/* Instruction buffer for decoding prologue. */
2365 xtensa_isa isa
; /* libisa ISA handle. */
2366 xtensa_insnbuf ins
, slot
; /* libisa handle to decoded insn, slot. */
2367 xtensa_format ifmt
; /* libisa instruction format. */
2368 int ilen
, islots
, is
; /* Instruction length, nbr slots, current slot. */
2369 xtensa_opcode opc
; /* Opcode in current slot. */
2370 xtensa_insn_kind opclass
; /* Opcode class for Call0 prologue analysis. */
2371 int nods
; /* Opcode number of operands. */
2372 unsigned odv
[C0_MAXOPDS
]; /* Operand values in order provided by libisa. */
2373 xtensa_c0reg_t
*rtmp
; /* Register tracking info snapshot. */
2374 int j
; /* General loop counter. */
2375 int fail
= 0; /* Set non-zero and exit, if decoding fails. */
2376 CORE_ADDR body_pc
; /* The PC for the first non-prologue insn. */
2377 CORE_ADDR end_pc
; /* The PC for the lust function insn. */
2379 struct symtab_and_line prologue_sal
;
2381 DEBUGTRACE ("call0_analyze_prologue (start = 0x%08x, pc = 0x%08x, ...)\n",
2382 (int)start
, (int)pc
);
2384 /* Try to limit the scan to the end of the function if a non-zero pc
2385 arg was not supplied to avoid probing beyond the end of valid memory.
2386 If memory is full of garbage that classifies as c0opc_uninteresting.
2387 If this fails (eg. if no symbols) pc ends up 0 as it was.
2388 Initialize the Call0 frame and register tracking info.
2389 Assume it's Call0 until an 'entry' instruction is encountered.
2390 Assume we may be in the prologue until we hit a flow control instr. */
2396 /* Find out, if we have an information about the prologue from DWARF. */
2397 prologue_sal
= find_pc_line (start
, 0);
2398 if (prologue_sal
.line
!= 0) /* Found debug info. */
2399 body_pc
= prologue_sal
.end
;
2401 /* If we are going to analyze the prologue in general without knowing about
2402 the current PC, make the best assumption for the end of the prologue. */
2405 find_pc_partial_function (start
, 0, NULL
, &end_pc
);
2406 body_pc
= std::min (end_pc
, body_pc
);
2409 body_pc
= std::min (pc
, body_pc
);
2412 rtmp
= (xtensa_c0reg_t
*) alloca(nregs
* sizeof(xtensa_c0reg_t
));
2414 isa
= xtensa_default_isa
;
2415 gdb_assert (XTENSA_ISA_BSZ
>= xtensa_isa_maxlength (isa
));
2416 ins
= xtensa_insnbuf_alloc (isa
);
2417 slot
= xtensa_insnbuf_alloc (isa
);
2419 for (ia
= start
, bt
= ia
; ia
< body_pc
; ia
+= ilen
)
2421 /* (Re)fill instruction buffer from memory if necessary, but do not
2422 read memory beyond PC to be sure we stay within text section
2423 (this protection only works if a non-zero pc is supplied). */
2425 if (ia
+ xtensa_isa_maxlength (isa
) > bt
)
2428 bt
= (ba
+ XTENSA_ISA_BSZ
) < body_pc
? ba
+ XTENSA_ISA_BSZ
: body_pc
;
2429 if (target_read_memory (ba
, ibuf
, bt
- ba
) != 0 )
2430 error (_("Unable to read target memory ..."));
2433 /* Decode format information. */
2435 xtensa_insnbuf_from_chars (isa
, ins
, &ibuf
[ia
-ba
], 0);
2436 ifmt
= xtensa_format_decode (isa
, ins
);
2437 if (ifmt
== XTENSA_UNDEFINED
)
2442 ilen
= xtensa_format_length (isa
, ifmt
);
2443 if (ilen
== XTENSA_UNDEFINED
)
2448 islots
= xtensa_format_num_slots (isa
, ifmt
);
2449 if (islots
== XTENSA_UNDEFINED
)
2455 /* Analyze a bundle or a single instruction, using a snapshot of
2456 the register tracking info as input for the entire bundle so that
2457 register changes do not take effect within this bundle. */
2459 for (j
= 0; j
< nregs
; ++j
)
2460 rtmp
[j
] = cache
->c0
.c0_rt
[j
];
2462 for (is
= 0; is
< islots
; ++is
)
2464 /* Decode a slot and classify the opcode. */
2466 fail
= xtensa_format_get_slot (isa
, ifmt
, is
, ins
, slot
);
2470 opc
= xtensa_opcode_decode (isa
, ifmt
, is
, slot
);
2471 DEBUGVERB ("[call0_analyze_prologue] instr addr = 0x%08x, opc = %d\n",
2473 if (opc
== XTENSA_UNDEFINED
)
2474 opclass
= c0opc_illegal
;
2476 opclass
= call0_classify_opcode (isa
, opc
);
2478 /* Decide whether to track this opcode, ignore it, or bail out. */
2487 case c0opc_uninteresting
:
2490 case c0opc_flow
: /* Flow control instructions stop analysis. */
2491 case c0opc_rwxsr
: /* RSR, WSR, XSR instructions stop analysis. */
2496 ia
+= ilen
; /* Skip over 'entry' insn. */
2503 /* Only expected opcodes should get this far. */
2505 /* Extract and decode the operands. */
2506 nods
= xtensa_opcode_num_operands (isa
, opc
);
2507 if (nods
== XTENSA_UNDEFINED
)
2513 for (j
= 0; j
< nods
&& j
< C0_MAXOPDS
; ++j
)
2515 fail
= xtensa_operand_get_field (isa
, opc
, j
, ifmt
,
2520 fail
= xtensa_operand_decode (isa
, opc
, j
, &odv
[j
]);
2525 /* Check operands to verify use of 'mov' assembler macro. */
2526 if (opclass
== c0opc_mov
&& nods
== 3)
2528 if (odv
[2] == odv
[1])
2531 if ((odv
[0] == 1) && (odv
[1] != 1))
2532 /* OR A1, An, An , where n != 1.
2533 This means we are inside epilogue already. */
2538 opclass
= c0opc_uninteresting
;
2543 /* Track register movement and modification for this operation. */
2544 fail
= call0_track_op (gdbarch
, cache
->c0
.c0_rt
, rtmp
,
2545 opclass
, nods
, odv
, ia
, 1, cache
);
2551 DEBUGVERB ("[call0_analyze_prologue] stopped at instr addr 0x%08x, %s\n",
2552 (unsigned)ia
, fail
? "failed" : "succeeded");
2553 xtensa_insnbuf_free(isa
, slot
);
2554 xtensa_insnbuf_free(isa
, ins
);
2555 return fail
? XTENSA_ISA_BADPC
: ia
;
2558 /* Initialize frame cache for the current frame in CALL0 ABI. */
2561 call0_frame_cache (struct frame_info
*this_frame
,
2562 xtensa_frame_cache_t
*cache
, CORE_ADDR pc
)
2564 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2565 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2566 CORE_ADDR start_pc
; /* The beginning of the function. */
2567 CORE_ADDR body_pc
=UINT_MAX
; /* PC, where prologue analysis stopped. */
2568 CORE_ADDR sp
, fp
, ra
;
2569 int fp_regnum
= C0_SP
, c0_hasfp
= 0, c0_frmsz
= 0, prev_sp
= 0, to_stk
;
2570 xtensa_gdbarch_tdep
*tdep
= (xtensa_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
2572 sp
= get_frame_register_unsigned
2573 (this_frame
, tdep
->a0_base
+ 1);
2574 fp
= sp
; /* Assume FP == SP until proven otherwise. */
2576 /* Find the beginning of the prologue of the function containing the PC
2577 and analyze it up to the PC or the end of the prologue. */
2579 if (find_pc_partial_function (pc
, NULL
, &start_pc
, NULL
))
2581 body_pc
= call0_analyze_prologue (gdbarch
, start_pc
, pc
, C0_NREGS
, cache
);
2583 if (body_pc
== XTENSA_ISA_BADPC
)
2587 goto finish_frame_analysis
;
2591 /* Get the frame information and FP (if used) at the current PC.
2592 If PC is in the prologue, the prologue analysis is more reliable
2593 than DWARF info. We don't not know for sure, if PC is in the prologue,
2594 but we do know no calls have yet taken place, so we can almost
2595 certainly rely on the prologue analysis. */
2599 /* Prologue analysis was successful up to the PC.
2600 It includes the cases when PC == START_PC. */
2601 c0_hasfp
= cache
->c0
.c0_rt
[C0_FP
].fr_reg
== C0_SP
;
2602 /* c0_hasfp == true means there is a frame pointer because
2603 we analyzed the prologue and found that cache->c0.c0_rt[C0_FP]
2604 was derived from SP. Otherwise, it would be C0_FP. */
2605 fp_regnum
= c0_hasfp
? C0_FP
: C0_SP
;
2606 c0_frmsz
= - cache
->c0
.c0_rt
[fp_regnum
].fr_ofs
;
2607 fp_regnum
+= tdep
->a0_base
;
2609 else /* No data from the prologue analysis. */
2612 fp_regnum
= tdep
->a0_base
+ C0_SP
;
2617 if (cache
->c0
.c0_fpalign
)
2619 /* This frame has a special prologue with a dynamic stack adjustment
2620 to force an alignment, which is bigger than standard 16 bytes. */
2622 CORE_ADDR unaligned_sp
;
2624 if (cache
->c0
.c0_old_sp
== C0_INEXP
)
2625 /* This can't be. Prologue code should be consistent.
2626 Unaligned stack pointer should be saved in a spare register. */
2630 goto finish_frame_analysis
;
2633 if (cache
->c0
.c0_sp_ofs
== C0_NOSTK
)
2634 /* Saved unaligned value of SP is kept in a register. */
2635 unaligned_sp
= get_frame_register_unsigned
2636 (this_frame
, tdep
->a0_base
+ cache
->c0
.c0_old_sp
);
2638 /* Get the value from stack. */
2639 unaligned_sp
= (CORE_ADDR
)
2640 read_memory_integer (fp
+ cache
->c0
.c0_sp_ofs
, 4, byte_order
);
2642 prev_sp
= unaligned_sp
+ c0_frmsz
;
2645 prev_sp
= fp
+ c0_frmsz
;
2647 /* Frame size from debug info or prologue tracking does not account for
2648 alloca() and other dynamic allocations. Adjust frame size by FP - SP. */
2651 fp
= get_frame_register_unsigned (this_frame
, fp_regnum
);
2653 /* Update the stack frame size. */
2654 c0_frmsz
+= fp
- sp
;
2657 /* Get the return address (RA) from the stack if saved,
2658 or try to get it from a register. */
2660 to_stk
= cache
->c0
.c0_rt
[C0_RA
].to_stk
;
2661 if (to_stk
!= C0_NOSTK
)
2663 read_memory_integer (sp
+ c0_frmsz
+ cache
->c0
.c0_rt
[C0_RA
].to_stk
,
2666 else if (cache
->c0
.c0_rt
[C0_RA
].fr_reg
== C0_CONST
2667 && cache
->c0
.c0_rt
[C0_RA
].fr_ofs
== 0)
2669 /* Special case for terminating backtrace at a function that wants to
2670 be seen as the outermost one. Such a function will clear it's RA (A0)
2671 register to 0 in the prologue instead of saving its original value. */
2676 /* RA was copied to another register or (before any function call) may
2677 still be in the original RA register. This is not always reliable:
2678 even in a leaf function, register tracking stops after prologue, and
2679 even in prologue, non-prologue instructions (not tracked) may overwrite
2680 RA or any register it was copied to. If likely in prologue or before
2681 any call, use retracking info and hope for the best (compiler should
2682 have saved RA in stack if not in a leaf function). If not in prologue,
2688 && (i
== C0_RA
|| cache
->c0
.c0_rt
[i
].fr_reg
!= C0_RA
);
2690 if (i
>= C0_NREGS
&& cache
->c0
.c0_rt
[C0_RA
].fr_reg
== C0_RA
)
2694 ra
= get_frame_register_unsigned
2696 tdep
->a0_base
+ cache
->c0
.c0_rt
[i
].fr_reg
);
2701 finish_frame_analysis
:
2702 cache
->pc
= start_pc
;
2704 /* RA == 0 marks the outermost frame. Do not go past it. */
2705 cache
->prev_sp
= (ra
!= 0) ? prev_sp
: 0;
2706 cache
->c0
.fp_regnum
= fp_regnum
;
2707 cache
->c0
.c0_frmsz
= c0_frmsz
;
2708 cache
->c0
.c0_hasfp
= c0_hasfp
;
2709 cache
->c0
.c0_fp
= fp
;
2712 static CORE_ADDR a0_saved
;
2713 static CORE_ADDR a7_saved
;
2714 static CORE_ADDR a11_saved
;
2715 static int a0_was_saved
;
2716 static int a7_was_saved
;
2717 static int a11_was_saved
;
2719 /* Simulate L32E instruction: AT <-- ref (AS + offset). */
2721 execute_l32e (struct gdbarch
*gdbarch
, int at
, int as
, int offset
, CORE_ADDR wb
)
2723 xtensa_gdbarch_tdep
*tdep
= (xtensa_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
2724 int atreg
= arreg_number (gdbarch
, tdep
->a0_base
+ at
, wb
);
2725 int asreg
= arreg_number (gdbarch
, tdep
->a0_base
+ as
, wb
);
2726 CORE_ADDR addr
= xtensa_read_register (asreg
) + offset
;
2727 unsigned int spilled_value
2728 = read_memory_unsigned_integer (addr
, 4, gdbarch_byte_order (gdbarch
));
2730 if ((at
== 0) && !a0_was_saved
)
2732 a0_saved
= xtensa_read_register (atreg
);
2735 else if ((at
== 7) && !a7_was_saved
)
2737 a7_saved
= xtensa_read_register (atreg
);
2740 else if ((at
== 11) && !a11_was_saved
)
2742 a11_saved
= xtensa_read_register (atreg
);
2746 xtensa_write_register (atreg
, spilled_value
);
2749 /* Simulate S32E instruction: AT --> ref (AS + offset). */
2751 execute_s32e (struct gdbarch
*gdbarch
, int at
, int as
, int offset
, CORE_ADDR wb
)
2753 xtensa_gdbarch_tdep
*tdep
= (xtensa_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
2754 int atreg
= arreg_number (gdbarch
, tdep
->a0_base
+ at
, wb
);
2755 int asreg
= arreg_number (gdbarch
, tdep
->a0_base
+ as
, wb
);
2756 CORE_ADDR addr
= xtensa_read_register (asreg
) + offset
;
2757 ULONGEST spilled_value
= xtensa_read_register (atreg
);
2759 write_memory_unsigned_integer (addr
, 4,
2760 gdbarch_byte_order (gdbarch
),
2764 #define XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN 200
2770 xtNoExceptionHandler
2771 } xtensa_exception_handler_t
;
2773 /* Execute instruction stream from current PC until hitting RFWU or RFWO.
2774 Return type of Xtensa Window Interrupt Handler on success. */
2775 static xtensa_exception_handler_t
2776 execute_code (struct gdbarch
*gdbarch
, CORE_ADDR current_pc
, CORE_ADDR wb
)
2779 xtensa_insnbuf ins
, slot
;
2780 gdb_byte ibuf
[XTENSA_ISA_BSZ
];
2781 CORE_ADDR ia
, bt
, ba
;
2783 int ilen
, islots
, is
;
2786 void (*func
) (struct gdbarch
*, int, int, int, CORE_ADDR
);
2787 xtensa_gdbarch_tdep
*tdep
= (xtensa_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
2789 uint32_t at
, as
, offset
;
2791 /* WindowUnderflow12 = true, when inside _WindowUnderflow12. */
2792 int WindowUnderflow12
= (current_pc
& 0x1ff) >= 0x140;
2794 isa
= xtensa_default_isa
;
2795 gdb_assert (XTENSA_ISA_BSZ
>= xtensa_isa_maxlength (isa
));
2796 ins
= xtensa_insnbuf_alloc (isa
);
2797 slot
= xtensa_insnbuf_alloc (isa
);
2806 while (insn_num
++ < XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN
)
2808 if (ia
+ xtensa_isa_maxlength (isa
) > bt
)
2811 bt
= (ba
+ XTENSA_ISA_BSZ
);
2812 if (target_read_memory (ba
, ibuf
, bt
- ba
) != 0)
2813 return xtNoExceptionHandler
;
2815 xtensa_insnbuf_from_chars (isa
, ins
, &ibuf
[ia
-ba
], 0);
2816 ifmt
= xtensa_format_decode (isa
, ins
);
2817 if (ifmt
== XTENSA_UNDEFINED
)
2818 return xtNoExceptionHandler
;
2819 ilen
= xtensa_format_length (isa
, ifmt
);
2820 if (ilen
== XTENSA_UNDEFINED
)
2821 return xtNoExceptionHandler
;
2822 islots
= xtensa_format_num_slots (isa
, ifmt
);
2823 if (islots
== XTENSA_UNDEFINED
)
2824 return xtNoExceptionHandler
;
2825 for (is
= 0; is
< islots
; ++is
)
2827 if (xtensa_format_get_slot (isa
, ifmt
, is
, ins
, slot
))
2828 return xtNoExceptionHandler
;
2829 opc
= xtensa_opcode_decode (isa
, ifmt
, is
, slot
);
2830 if (opc
== XTENSA_UNDEFINED
)
2831 return xtNoExceptionHandler
;
2832 switch (call0_classify_opcode (isa
, opc
))
2838 /* We expect none of them here. */
2839 return xtNoExceptionHandler
;
2841 func
= execute_l32e
;
2844 func
= execute_s32e
;
2846 case c0opc_rfwo
: /* RFWO. */
2847 /* Here, we return from WindowOverflow handler and,
2848 if we stopped at the very beginning, which means
2849 A0 was saved, we have to restore it now. */
2852 int arreg
= arreg_number (gdbarch
,
2855 xtensa_write_register (arreg
, a0_saved
);
2857 return xtWindowOverflow
;
2858 case c0opc_rfwu
: /* RFWU. */
2859 /* Here, we return from WindowUnderflow handler.
2860 Let's see if either A7 or A11 has to be restored. */
2861 if (WindowUnderflow12
)
2865 int arreg
= arreg_number (gdbarch
,
2868 xtensa_write_register (arreg
, a11_saved
);
2871 else if (a7_was_saved
)
2873 int arreg
= arreg_number (gdbarch
,
2876 xtensa_write_register (arreg
, a7_saved
);
2878 return xtWindowUnderflow
;
2879 default: /* Simply skip this insns. */
2883 /* Decode arguments for L32E / S32E and simulate their execution. */
2884 if ( xtensa_opcode_num_operands (isa
, opc
) != 3 )
2885 return xtNoExceptionHandler
;
2886 if (xtensa_operand_get_field (isa
, opc
, 0, ifmt
, is
, slot
, &at
))
2887 return xtNoExceptionHandler
;
2888 if (xtensa_operand_decode (isa
, opc
, 0, &at
))
2889 return xtNoExceptionHandler
;
2890 if (xtensa_operand_get_field (isa
, opc
, 1, ifmt
, is
, slot
, &as
))
2891 return xtNoExceptionHandler
;
2892 if (xtensa_operand_decode (isa
, opc
, 1, &as
))
2893 return xtNoExceptionHandler
;
2894 if (xtensa_operand_get_field (isa
, opc
, 2, ifmt
, is
, slot
, &offset
))
2895 return xtNoExceptionHandler
;
2896 if (xtensa_operand_decode (isa
, opc
, 2, &offset
))
2897 return xtNoExceptionHandler
;
2899 (*func
) (gdbarch
, at
, as
, offset
, wb
);
2904 return xtNoExceptionHandler
;
2907 /* Handle Window Overflow / Underflow exception frames. */
2910 xtensa_window_interrupt_frame_cache (struct frame_info
*this_frame
,
2911 xtensa_frame_cache_t
*cache
,
2914 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2915 CORE_ADDR ps
, wb
, ws
, ra
;
2916 int epc1_regnum
, i
, regnum
;
2917 xtensa_exception_handler_t eh_type
;
2918 xtensa_gdbarch_tdep
*tdep
= (xtensa_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
2920 /* Read PS, WB, and WS from the hardware. Note that PS register
2921 must be present, if Windowed ABI is supported. */
2922 ps
= xtensa_read_register (gdbarch_ps_regnum (gdbarch
));
2923 wb
= xtensa_read_register (tdep
->wb_regnum
);
2924 ws
= xtensa_read_register (tdep
->ws_regnum
);
2926 /* Execute all the remaining instructions from Window Interrupt Handler
2927 by simulating them on the remote protocol level. On return, set the
2928 type of Xtensa Window Interrupt Handler, or report an error. */
2929 eh_type
= execute_code (gdbarch
, pc
, wb
);
2930 if (eh_type
== xtNoExceptionHandler
)
2932 Unable to decode Xtensa Window Interrupt Handler's code."));
2934 cache
->ps
= ps
^ PS_EXC
; /* Clear the exception bit in PS. */
2935 cache
->call0
= 0; /* It's Windowed ABI. */
2937 /* All registers for the cached frame will be alive. */
2938 for (i
= 0; i
< XTENSA_NUM_SAVED_AREGS
; i
++)
2939 cache
->wd
.aregs
[i
] = -1;
2941 if (eh_type
== xtWindowOverflow
)
2942 cache
->wd
.ws
= ws
^ (1 << wb
);
2943 else /* eh_type == xtWindowUnderflow. */
2944 cache
->wd
.ws
= ws
| (1 << wb
);
2946 cache
->wd
.wb
= (ps
& 0xf00) >> 8; /* Set WB to OWB. */
2947 regnum
= arreg_number (gdbarch
, tdep
->a0_base
,
2949 ra
= xtensa_read_register (regnum
);
2950 cache
->wd
.callsize
= WINSIZE (ra
);
2951 cache
->prev_sp
= xtensa_read_register (regnum
+ 1);
2952 /* Set regnum to a frame pointer of the frame being cached. */
2953 regnum
= xtensa_scan_prologue (gdbarch
, pc
);
2954 regnum
= arreg_number (gdbarch
,
2955 tdep
->a0_base
+ regnum
,
2957 cache
->base
= get_frame_register_unsigned (this_frame
, regnum
);
2959 /* Read PC of interrupted function from EPC1 register. */
2960 epc1_regnum
= xtensa_find_register_by_name (gdbarch
,"epc1");
2961 if (epc1_regnum
< 0)
2962 error(_("Unable to read Xtensa register EPC1"));
2963 cache
->ra
= xtensa_read_register (epc1_regnum
);
2964 cache
->pc
= get_frame_func (this_frame
);
2968 /* Skip function prologue.
2970 Return the pc of the first instruction after prologue. GDB calls this to
2971 find the address of the first line of the function or (if there is no line
2972 number information) to skip the prologue for planting breakpoints on
2973 function entries. Use debug info (if present) or prologue analysis to skip
2974 the prologue to achieve reliable debugging behavior. For windowed ABI,
2975 only the 'entry' instruction is skipped. It is not strictly necessary to
2976 skip the prologue (Call0) or 'entry' (Windowed) because xt-gdb knows how to
2977 backtrace at any point in the prologue, however certain potential hazards
2978 are avoided and a more "normal" debugging experience is ensured by
2979 skipping the prologue (can be disabled by defining DONT_SKIP_PROLOG).
2980 For example, if we don't skip the prologue:
2981 - Some args may not yet have been saved to the stack where the debug
2982 info expects to find them (true anyway when only 'entry' is skipped);
2983 - Software breakpoints ('break' instrs) may not have been unplanted
2984 when the prologue analysis is done on initializing the frame cache,
2985 and breaks in the prologue will throw off the analysis.
2987 If we have debug info ( line-number info, in particular ) we simply skip
2988 the code associated with the first function line effectively skipping
2989 the prologue code. It works even in cases like
2992 { int local_var = 1;
2996 because, for this source code, both Xtensa compilers will generate two
2997 separate entries ( with the same line number ) in dwarf line-number
2998 section to make sure there is a boundary between the prologue code and
2999 the rest of the function.
3001 If there is no debug info, we need to analyze the code. */
3003 /* #define DONT_SKIP_PROLOGUE */
3006 xtensa_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
3008 struct symtab_and_line prologue_sal
;
3011 DEBUGTRACE ("xtensa_skip_prologue (start_pc = 0x%08x)\n", (int) start_pc
);
3013 #if DONT_SKIP_PROLOGUE
3017 /* Try to find first body line from debug info. */
3019 prologue_sal
= find_pc_line (start_pc
, 0);
3020 if (prologue_sal
.line
!= 0) /* Found debug info. */
3022 /* In Call0, it is possible to have a function with only one instruction
3023 ('ret') resulting from a one-line optimized function that does nothing.
3024 In that case, prologue_sal.end may actually point to the start of the
3025 next function in the text section, causing a breakpoint to be set at
3026 the wrong place. Check, if the end address is within a different
3027 function, and if so return the start PC. We know we have symbol
3032 xtensa_gdbarch_tdep
*tdep
= (xtensa_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
3033 if ((tdep
->call_abi
== CallAbiCall0Only
)
3034 && call0_ret (start_pc
, prologue_sal
.end
))
3037 find_pc_partial_function (prologue_sal
.end
, NULL
, &end_func
, NULL
);
3038 if (end_func
!= start_pc
)
3041 return prologue_sal
.end
;
3044 /* No debug line info. Analyze prologue for Call0 or simply skip ENTRY. */
3045 body_pc
= call0_analyze_prologue (gdbarch
, start_pc
, 0, 0,
3046 xtensa_alloc_frame_cache (0));
3047 return body_pc
!= 0 ? body_pc
: start_pc
;
3050 /* Verify the current configuration. */
3052 xtensa_verify_config (struct gdbarch
*gdbarch
)
3054 xtensa_gdbarch_tdep
*tdep
= (xtensa_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
3057 /* Verify that we got a reasonable number of AREGS. */
3058 if ((tdep
->num_aregs
& -tdep
->num_aregs
) != tdep
->num_aregs
)
3060 \n\tnum_aregs: Number of AR registers (%d) is not a power of two!"),
3063 /* Verify that certain registers exist. */
3065 if (tdep
->pc_regnum
== -1)
3066 log
.printf (_("\n\tpc_regnum: No PC register"));
3067 if (tdep
->isa_use_exceptions
&& tdep
->ps_regnum
== -1)
3068 log
.printf (_("\n\tps_regnum: No PS register"));
3070 if (tdep
->isa_use_windowed_registers
)
3072 if (tdep
->wb_regnum
== -1)
3073 log
.printf (_("\n\twb_regnum: No WB register"));
3074 if (tdep
->ws_regnum
== -1)
3075 log
.printf (_("\n\tws_regnum: No WS register"));
3076 if (tdep
->ar_base
== -1)
3077 log
.printf (_("\n\tar_base: No AR registers"));
3080 if (tdep
->a0_base
== -1)
3081 log
.printf (_("\n\ta0_base: No Ax registers"));
3084 internal_error (__FILE__
, __LINE__
,
3085 _("the following are invalid: %s"), log
.c_str ());
3089 /* Derive specific register numbers from the array of registers. */
3092 xtensa_derive_tdep (xtensa_gdbarch_tdep
*tdep
)
3094 xtensa_register_t
* rmap
;
3095 int n
, max_size
= 4;
3098 tdep
->num_nopriv_regs
= 0;
3100 /* Special registers 0..255 (core). */
3101 #define XTENSA_DBREGN_SREG(n) (0x0200+(n))
3102 /* User registers 0..255. */
3103 #define XTENSA_DBREGN_UREG(n) (0x0300+(n))
3105 for (rmap
= tdep
->regmap
, n
= 0; rmap
->target_number
!= -1; n
++, rmap
++)
3107 if (rmap
->target_number
== 0x0020)
3108 tdep
->pc_regnum
= n
;
3109 else if (rmap
->target_number
== 0x0100)
3111 else if (rmap
->target_number
== 0x0000)
3113 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(72))
3114 tdep
->wb_regnum
= n
;
3115 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(73))
3116 tdep
->ws_regnum
= n
;
3117 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(233))
3118 tdep
->debugcause_regnum
= n
;
3119 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(232))
3120 tdep
->exccause_regnum
= n
;
3121 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(238))
3122 tdep
->excvaddr_regnum
= n
;
3123 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(0))
3124 tdep
->lbeg_regnum
= n
;
3125 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(1))
3126 tdep
->lend_regnum
= n
;
3127 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(2))
3128 tdep
->lcount_regnum
= n
;
3129 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(3))
3130 tdep
->sar_regnum
= n
;
3131 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(5))
3132 tdep
->litbase_regnum
= n
;
3133 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(230))
3134 tdep
->ps_regnum
= n
;
3135 else if (rmap
->target_number
== XTENSA_DBREGN_UREG(231))
3136 tdep
->threadptr_regnum
= n
;
3138 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(226))
3139 tdep
->interrupt_regnum
= n
;
3140 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(227))
3141 tdep
->interrupt2_regnum
= n
;
3142 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(224))
3143 tdep
->cpenable_regnum
= n
;
3146 if (rmap
->byte_size
> max_size
)
3147 max_size
= rmap
->byte_size
;
3148 if (rmap
->mask
!= 0 && tdep
->num_regs
== 0)
3150 if ((rmap
->flags
& XTENSA_REGISTER_FLAGS_PRIVILEGED
) != 0
3151 && tdep
->num_nopriv_regs
== 0)
3152 tdep
->num_nopriv_regs
= n
;
3154 if (tdep
->num_regs
== 0)
3155 tdep
->num_regs
= tdep
->num_nopriv_regs
;
3157 /* Number of pseudo registers. */
3158 tdep
->num_pseudo_regs
= n
- tdep
->num_regs
;
3160 /* Empirically determined maximum sizes. */
3161 tdep
->max_register_raw_size
= max_size
;
3162 tdep
->max_register_virtual_size
= max_size
;
3165 /* Module "constructor" function. */
3167 extern xtensa_gdbarch_tdep xtensa_tdep
;
3169 static struct gdbarch
*
3170 xtensa_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
3172 struct gdbarch
*gdbarch
;
3174 DEBUGTRACE ("gdbarch_init()\n");
3176 if (!xtensa_default_isa
)
3177 xtensa_default_isa
= xtensa_isa_init (0, 0);
3179 /* We have to set the byte order before we call gdbarch_alloc. */
3180 info
.byte_order
= XCHAL_HAVE_BE
? BFD_ENDIAN_BIG
: BFD_ENDIAN_LITTLE
;
3182 xtensa_gdbarch_tdep
*tdep
= &xtensa_tdep
;
3183 gdbarch
= gdbarch_alloc (&info
, tdep
);
3184 xtensa_derive_tdep (tdep
);
3186 /* Verify our configuration. */
3187 xtensa_verify_config (gdbarch
);
3188 xtensa_session_once_reported
= 0;
3190 set_gdbarch_wchar_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
3191 set_gdbarch_wchar_signed (gdbarch
, 0);
3193 /* Pseudo-Register read/write. */
3194 set_gdbarch_pseudo_register_read (gdbarch
, xtensa_pseudo_register_read
);
3195 set_gdbarch_pseudo_register_write (gdbarch
, xtensa_pseudo_register_write
);
3197 /* Set target information. */
3198 set_gdbarch_num_regs (gdbarch
, tdep
->num_regs
);
3199 set_gdbarch_num_pseudo_regs (gdbarch
, tdep
->num_pseudo_regs
);
3200 set_gdbarch_sp_regnum (gdbarch
, tdep
->a0_base
+ 1);
3201 set_gdbarch_pc_regnum (gdbarch
, tdep
->pc_regnum
);
3202 set_gdbarch_ps_regnum (gdbarch
, tdep
->ps_regnum
);
3204 /* Renumber registers for known formats (stabs and dwarf2). */
3205 set_gdbarch_stab_reg_to_regnum (gdbarch
, xtensa_reg_to_regnum
);
3206 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, xtensa_reg_to_regnum
);
3208 /* We provide our own function to get register information. */
3209 set_gdbarch_register_name (gdbarch
, xtensa_register_name
);
3210 set_gdbarch_register_type (gdbarch
, xtensa_register_type
);
3212 /* To call functions from GDB using dummy frame. */
3213 set_gdbarch_push_dummy_call (gdbarch
, xtensa_push_dummy_call
);
3215 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
3217 set_gdbarch_return_value (gdbarch
, xtensa_return_value
);
3219 /* Advance PC across any prologue instructions to reach "real" code. */
3220 set_gdbarch_skip_prologue (gdbarch
, xtensa_skip_prologue
);
3222 /* Stack grows downward. */
3223 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
3225 /* Set breakpoints. */
3226 set_gdbarch_breakpoint_kind_from_pc (gdbarch
,
3227 xtensa_breakpoint_kind_from_pc
);
3228 set_gdbarch_sw_breakpoint_from_kind (gdbarch
,
3229 xtensa_sw_breakpoint_from_kind
);
3231 /* After breakpoint instruction or illegal instruction, pc still
3232 points at break instruction, so don't decrement. */
3233 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
3235 /* We don't skip args. */
3236 set_gdbarch_frame_args_skip (gdbarch
, 0);
3238 set_gdbarch_unwind_pc (gdbarch
, xtensa_unwind_pc
);
3240 set_gdbarch_frame_align (gdbarch
, xtensa_frame_align
);
3242 set_gdbarch_dummy_id (gdbarch
, xtensa_dummy_id
);
3244 /* Frame handling. */
3245 frame_base_set_default (gdbarch
, &xtensa_frame_base
);
3246 frame_unwind_append_unwinder (gdbarch
, &xtensa_unwind
);
3247 dwarf2_append_unwinders (gdbarch
);
3249 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
3251 xtensa_add_reggroups (gdbarch
);
3252 set_gdbarch_register_reggroup_p (gdbarch
, xtensa_register_reggroup_p
);
3254 set_gdbarch_iterate_over_regset_sections
3255 (gdbarch
, xtensa_iterate_over_regset_sections
);
3257 set_solib_svr4_fetch_link_map_offsets
3258 (gdbarch
, svr4_ilp32_fetch_link_map_offsets
);
3260 /* Hook in the ABI-specific overrides, if they have been registered. */
3261 gdbarch_init_osabi (info
, gdbarch
);
3267 xtensa_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
3269 error (_("xtensa_dump_tdep(): not implemented"));
3272 void _initialize_xtensa_tdep ();
3274 _initialize_xtensa_tdep ()
3276 gdbarch_register (bfd_arch_xtensa
, xtensa_gdbarch_init
, xtensa_dump_tdep
);
3277 xtensa_init_reggroups ();
3279 add_setshow_zuinteger_cmd ("xtensa",
3281 &xtensa_debug_level
,
3282 _("Set Xtensa debugging."),
3283 _("Show Xtensa debugging."), _("\
3284 When non-zero, Xtensa-specific debugging is enabled. \
3285 Can be 1, 2, 3, or 4 indicating the level of debugging."),
3288 &setdebuglist
, &showdebuglist
);