1 /* GNU/Linux/AArch64 specific low level interface, for the remote server for
4 Copyright (C) 2009-2022 Free Software Foundation, Inc.
5 Contributed by ARM Ltd.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "linux-low.h"
24 #include "nat/aarch64-linux.h"
25 #include "nat/aarch64-linux-hw-point.h"
26 #include "arch/aarch64-insn.h"
27 #include "linux-aarch32-low.h"
28 #include "elf/common.h"
30 #include "tracepoint.h"
35 #include "nat/gdb_ptrace.h"
36 #include <asm/ptrace.h>
41 #include "gdb_proc_service.h"
42 #include "arch/aarch64.h"
43 #include "arch/aarch64-mte-linux.h"
44 #include "linux-aarch32-tdesc.h"
45 #include "linux-aarch64-tdesc.h"
46 #include "nat/aarch64-mte-linux-ptrace.h"
47 #include "nat/aarch64-sve-linux-ptrace.h"
58 /* Linux target op definitions for the AArch64 architecture. */
60 class aarch64_target
: public linux_process_target
64 const regs_info
*get_regs_info () override
;
66 int breakpoint_kind_from_pc (CORE_ADDR
*pcptr
) override
;
68 int breakpoint_kind_from_current_state (CORE_ADDR
*pcptr
) override
;
70 const gdb_byte
*sw_breakpoint_from_kind (int kind
, int *size
) override
;
72 bool supports_z_point_type (char z_type
) override
;
74 bool supports_tracepoints () override
;
76 bool supports_fast_tracepoints () override
;
78 int install_fast_tracepoint_jump_pad
79 (CORE_ADDR tpoint
, CORE_ADDR tpaddr
, CORE_ADDR collector
,
80 CORE_ADDR lockaddr
, ULONGEST orig_size
, CORE_ADDR
*jump_entry
,
81 CORE_ADDR
*trampoline
, ULONGEST
*trampoline_size
,
82 unsigned char *jjump_pad_insn
, ULONGEST
*jjump_pad_insn_size
,
83 CORE_ADDR
*adjusted_insn_addr
, CORE_ADDR
*adjusted_insn_addr_end
,
86 int get_min_fast_tracepoint_insn_len () override
;
88 struct emit_ops
*emit_ops () override
;
90 bool supports_memory_tagging () override
;
92 bool fetch_memtags (CORE_ADDR address
, size_t len
,
93 gdb::byte_vector
&tags
, int type
) override
;
95 bool store_memtags (CORE_ADDR address
, size_t len
,
96 const gdb::byte_vector
&tags
, int type
) override
;
100 void low_arch_setup () override
;
102 bool low_cannot_fetch_register (int regno
) override
;
104 bool low_cannot_store_register (int regno
) override
;
106 bool low_supports_breakpoints () override
;
108 CORE_ADDR
low_get_pc (regcache
*regcache
) override
;
110 void low_set_pc (regcache
*regcache
, CORE_ADDR newpc
) override
;
112 bool low_breakpoint_at (CORE_ADDR pc
) override
;
114 int low_insert_point (raw_bkpt_type type
, CORE_ADDR addr
,
115 int size
, raw_breakpoint
*bp
) override
;
117 int low_remove_point (raw_bkpt_type type
, CORE_ADDR addr
,
118 int size
, raw_breakpoint
*bp
) override
;
120 bool low_stopped_by_watchpoint () override
;
122 CORE_ADDR
low_stopped_data_address () override
;
124 bool low_siginfo_fixup (siginfo_t
*native
, gdb_byte
*inf
,
125 int direction
) override
;
127 arch_process_info
*low_new_process () override
;
129 void low_delete_process (arch_process_info
*info
) override
;
131 void low_new_thread (lwp_info
*) override
;
133 void low_delete_thread (arch_lwp_info
*) override
;
135 void low_new_fork (process_info
*parent
, process_info
*child
) override
;
137 void low_prepare_to_resume (lwp_info
*lwp
) override
;
139 int low_get_thread_area (int lwpid
, CORE_ADDR
*addrp
) override
;
141 bool low_supports_range_stepping () override
;
143 bool low_supports_catch_syscall () override
;
145 void low_get_syscall_trapinfo (regcache
*regcache
, int *sysno
) override
;
148 /* The singleton target ops object. */
150 static aarch64_target the_aarch64_target
;
153 aarch64_target::low_cannot_fetch_register (int regno
)
155 gdb_assert_not_reached ("linux target op low_cannot_fetch_register "
156 "is not implemented by the target");
160 aarch64_target::low_cannot_store_register (int regno
)
162 gdb_assert_not_reached ("linux target op low_cannot_store_register "
163 "is not implemented by the target");
167 aarch64_target::low_prepare_to_resume (lwp_info
*lwp
)
169 aarch64_linux_prepare_to_resume (lwp
);
172 /* Per-process arch-specific data we want to keep. */
174 struct arch_process_info
176 /* Hardware breakpoint/watchpoint data.
177 The reason for them to be per-process rather than per-thread is
178 due to the lack of information in the gdbserver environment;
179 gdbserver is not told that whether a requested hardware
180 breakpoint/watchpoint is thread specific or not, so it has to set
181 each hw bp/wp for every thread in the current process. The
182 higher level bp/wp management in gdb will resume a thread if a hw
183 bp/wp trap is not expected for it. Since the hw bp/wp setting is
184 same for each thread, it is reasonable for the data to live here.
186 struct aarch64_debug_reg_state debug_reg_state
;
189 /* Return true if the size of register 0 is 8 byte. */
192 is_64bit_tdesc (void)
194 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
196 return register_size (regcache
->tdesc
, 0) == 8;
200 aarch64_fill_gregset (struct regcache
*regcache
, void *buf
)
202 struct user_pt_regs
*regset
= (struct user_pt_regs
*) buf
;
205 for (i
= 0; i
< AARCH64_X_REGS_NUM
; i
++)
206 collect_register (regcache
, AARCH64_X0_REGNUM
+ i
, ®set
->regs
[i
]);
207 collect_register (regcache
, AARCH64_SP_REGNUM
, ®set
->sp
);
208 collect_register (regcache
, AARCH64_PC_REGNUM
, ®set
->pc
);
209 collect_register (regcache
, AARCH64_CPSR_REGNUM
, ®set
->pstate
);
213 aarch64_store_gregset (struct regcache
*regcache
, const void *buf
)
215 const struct user_pt_regs
*regset
= (const struct user_pt_regs
*) buf
;
218 for (i
= 0; i
< AARCH64_X_REGS_NUM
; i
++)
219 supply_register (regcache
, AARCH64_X0_REGNUM
+ i
, ®set
->regs
[i
]);
220 supply_register (regcache
, AARCH64_SP_REGNUM
, ®set
->sp
);
221 supply_register (regcache
, AARCH64_PC_REGNUM
, ®set
->pc
);
222 supply_register (regcache
, AARCH64_CPSR_REGNUM
, ®set
->pstate
);
226 aarch64_fill_fpregset (struct regcache
*regcache
, void *buf
)
228 struct user_fpsimd_state
*regset
= (struct user_fpsimd_state
*) buf
;
231 for (i
= 0; i
< AARCH64_V_REGS_NUM
; i
++)
232 collect_register (regcache
, AARCH64_V0_REGNUM
+ i
, ®set
->vregs
[i
]);
233 collect_register (regcache
, AARCH64_FPSR_REGNUM
, ®set
->fpsr
);
234 collect_register (regcache
, AARCH64_FPCR_REGNUM
, ®set
->fpcr
);
238 aarch64_store_fpregset (struct regcache
*regcache
, const void *buf
)
240 const struct user_fpsimd_state
*regset
241 = (const struct user_fpsimd_state
*) buf
;
244 for (i
= 0; i
< AARCH64_V_REGS_NUM
; i
++)
245 supply_register (regcache
, AARCH64_V0_REGNUM
+ i
, ®set
->vregs
[i
]);
246 supply_register (regcache
, AARCH64_FPSR_REGNUM
, ®set
->fpsr
);
247 supply_register (regcache
, AARCH64_FPCR_REGNUM
, ®set
->fpcr
);
250 /* Store the pauth registers to regcache. */
253 aarch64_store_pauthregset (struct regcache
*regcache
, const void *buf
)
255 uint64_t *pauth_regset
= (uint64_t *) buf
;
256 int pauth_base
= find_regno (regcache
->tdesc
, "pauth_dmask");
261 supply_register (regcache
, AARCH64_PAUTH_DMASK_REGNUM (pauth_base
),
263 supply_register (regcache
, AARCH64_PAUTH_CMASK_REGNUM (pauth_base
),
267 /* Fill BUF with the MTE registers from the regcache. */
270 aarch64_fill_mteregset (struct regcache
*regcache
, void *buf
)
272 uint64_t *mte_regset
= (uint64_t *) buf
;
273 int mte_base
= find_regno (regcache
->tdesc
, "tag_ctl");
275 collect_register (regcache
, mte_base
, mte_regset
);
278 /* Store the MTE registers to regcache. */
281 aarch64_store_mteregset (struct regcache
*regcache
, const void *buf
)
283 uint64_t *mte_regset
= (uint64_t *) buf
;
284 int mte_base
= find_regno (regcache
->tdesc
, "tag_ctl");
286 /* Tag Control register */
287 supply_register (regcache
, mte_base
, mte_regset
);
291 aarch64_target::low_supports_breakpoints ()
296 /* Implementation of linux target ops method "low_get_pc". */
299 aarch64_target::low_get_pc (regcache
*regcache
)
301 if (register_size (regcache
->tdesc
, 0) == 8)
302 return linux_get_pc_64bit (regcache
);
304 return linux_get_pc_32bit (regcache
);
307 /* Implementation of linux target ops method "low_set_pc". */
310 aarch64_target::low_set_pc (regcache
*regcache
, CORE_ADDR pc
)
312 if (register_size (regcache
->tdesc
, 0) == 8)
313 linux_set_pc_64bit (regcache
, pc
);
315 linux_set_pc_32bit (regcache
, pc
);
318 #define aarch64_breakpoint_len 4
320 /* AArch64 BRK software debug mode instruction.
321 This instruction needs to match gdb/aarch64-tdep.c
322 (aarch64_default_breakpoint). */
323 static const gdb_byte aarch64_breakpoint
[] = {0x00, 0x00, 0x20, 0xd4};
325 /* Implementation of linux target ops method "low_breakpoint_at". */
328 aarch64_target::low_breakpoint_at (CORE_ADDR where
)
330 if (is_64bit_tdesc ())
332 gdb_byte insn
[aarch64_breakpoint_len
];
334 read_memory (where
, (unsigned char *) &insn
, aarch64_breakpoint_len
);
335 if (memcmp (insn
, aarch64_breakpoint
, aarch64_breakpoint_len
) == 0)
341 return arm_breakpoint_at (where
);
345 aarch64_init_debug_reg_state (struct aarch64_debug_reg_state
*state
)
349 for (i
= 0; i
< AARCH64_HBP_MAX_NUM
; ++i
)
351 state
->dr_addr_bp
[i
] = 0;
352 state
->dr_ctrl_bp
[i
] = 0;
353 state
->dr_ref_count_bp
[i
] = 0;
356 for (i
= 0; i
< AARCH64_HWP_MAX_NUM
; ++i
)
358 state
->dr_addr_wp
[i
] = 0;
359 state
->dr_ctrl_wp
[i
] = 0;
360 state
->dr_ref_count_wp
[i
] = 0;
364 /* Return the pointer to the debug register state structure in the
365 current process' arch-specific data area. */
367 struct aarch64_debug_reg_state
*
368 aarch64_get_debug_reg_state (pid_t pid
)
370 struct process_info
*proc
= find_process_pid (pid
);
372 return &proc
->priv
->arch_private
->debug_reg_state
;
375 /* Implementation of target ops method "supports_z_point_type". */
378 aarch64_target::supports_z_point_type (char z_type
)
384 case Z_PACKET_WRITE_WP
:
385 case Z_PACKET_READ_WP
:
386 case Z_PACKET_ACCESS_WP
:
393 /* Implementation of linux target ops method "low_insert_point".
395 It actually only records the info of the to-be-inserted bp/wp;
396 the actual insertion will happen when threads are resumed. */
399 aarch64_target::low_insert_point (raw_bkpt_type type
, CORE_ADDR addr
,
400 int len
, raw_breakpoint
*bp
)
403 enum target_hw_bp_type targ_type
;
404 struct aarch64_debug_reg_state
*state
405 = aarch64_get_debug_reg_state (pid_of (current_thread
));
408 fprintf (stderr
, "insert_point on entry (addr=0x%08lx, len=%d)\n",
409 (unsigned long) addr
, len
);
411 /* Determine the type from the raw breakpoint type. */
412 targ_type
= raw_bkpt_type_to_target_hw_bp_type (type
);
414 if (targ_type
!= hw_execute
)
416 if (aarch64_region_ok_for_watchpoint (addr
, len
))
417 ret
= aarch64_handle_watchpoint (targ_type
, addr
, len
,
419 current_lwp_ptid (), state
);
427 /* LEN is 3 means the breakpoint is set on a 32-bit thumb
428 instruction. Set it to 2 to correctly encode length bit
429 mask in hardware/watchpoint control register. */
432 ret
= aarch64_handle_breakpoint (targ_type
, addr
, len
,
433 1 /* is_insert */, current_lwp_ptid (),
438 aarch64_show_debug_reg_state (state
, "insert_point", addr
, len
,
444 /* Implementation of linux target ops method "low_remove_point".
446 It actually only records the info of the to-be-removed bp/wp,
447 the actual removal will be done when threads are resumed. */
450 aarch64_target::low_remove_point (raw_bkpt_type type
, CORE_ADDR addr
,
451 int len
, raw_breakpoint
*bp
)
454 enum target_hw_bp_type targ_type
;
455 struct aarch64_debug_reg_state
*state
456 = aarch64_get_debug_reg_state (pid_of (current_thread
));
459 fprintf (stderr
, "remove_point on entry (addr=0x%08lx, len=%d)\n",
460 (unsigned long) addr
, len
);
462 /* Determine the type from the raw breakpoint type. */
463 targ_type
= raw_bkpt_type_to_target_hw_bp_type (type
);
465 /* Set up state pointers. */
466 if (targ_type
!= hw_execute
)
468 aarch64_handle_watchpoint (targ_type
, addr
, len
, 0 /* is_insert */,
469 current_lwp_ptid (), state
);
474 /* LEN is 3 means the breakpoint is set on a 32-bit thumb
475 instruction. Set it to 2 to correctly encode length bit
476 mask in hardware/watchpoint control register. */
479 ret
= aarch64_handle_breakpoint (targ_type
, addr
, len
,
480 0 /* is_insert */, current_lwp_ptid (),
485 aarch64_show_debug_reg_state (state
, "remove_point", addr
, len
,
491 /* Return the address only having significant bits. This is used to ignore
492 the top byte (TBI). */
495 address_significant (CORE_ADDR addr
)
497 /* Clear insignificant bits of a target address and sign extend resulting
501 CORE_ADDR sign
= (CORE_ADDR
) 1 << (addr_bit
- 1);
502 addr
&= ((CORE_ADDR
) 1 << addr_bit
) - 1;
503 addr
= (addr
^ sign
) - sign
;
508 /* Implementation of linux target ops method "low_stopped_data_address". */
511 aarch64_target::low_stopped_data_address ()
515 struct aarch64_debug_reg_state
*state
;
517 pid
= lwpid_of (current_thread
);
519 /* Get the siginfo. */
520 if (ptrace (PTRACE_GETSIGINFO
, pid
, NULL
, &siginfo
) != 0)
521 return (CORE_ADDR
) 0;
523 /* Need to be a hardware breakpoint/watchpoint trap. */
524 if (siginfo
.si_signo
!= SIGTRAP
525 || (siginfo
.si_code
& 0xffff) != 0x0004 /* TRAP_HWBKPT */)
526 return (CORE_ADDR
) 0;
528 /* Make sure to ignore the top byte, otherwise we may not recognize a
529 hardware watchpoint hit. The stopped data addresses coming from the
530 kernel can potentially be tagged addresses. */
531 const CORE_ADDR addr_trap
532 = address_significant ((CORE_ADDR
) siginfo
.si_addr
);
534 /* Check if the address matches any watched address. */
535 state
= aarch64_get_debug_reg_state (pid_of (current_thread
));
536 for (i
= aarch64_num_wp_regs
- 1; i
>= 0; --i
)
538 const unsigned int offset
539 = aarch64_watchpoint_offset (state
->dr_ctrl_wp
[i
]);
540 const unsigned int len
= aarch64_watchpoint_length (state
->dr_ctrl_wp
[i
]);
541 const CORE_ADDR addr_watch
= state
->dr_addr_wp
[i
] + offset
;
542 const CORE_ADDR addr_watch_aligned
= align_down (state
->dr_addr_wp
[i
], 8);
543 const CORE_ADDR addr_orig
= state
->dr_addr_orig_wp
[i
];
545 if (state
->dr_ref_count_wp
[i
]
546 && DR_CONTROL_ENABLED (state
->dr_ctrl_wp
[i
])
547 && addr_trap
>= addr_watch_aligned
548 && addr_trap
< addr_watch
+ len
)
550 /* ADDR_TRAP reports the first address of the memory range
551 accessed by the CPU, regardless of what was the memory
552 range watched. Thus, a large CPU access that straddles
553 the ADDR_WATCH..ADDR_WATCH+LEN range may result in an
554 ADDR_TRAP that is lower than the
555 ADDR_WATCH..ADDR_WATCH+LEN range. E.g.:
557 addr: | 4 | 5 | 6 | 7 | 8 |
558 |---- range watched ----|
559 |----------- range accessed ------------|
561 In this case, ADDR_TRAP will be 4.
563 To match a watchpoint known to GDB core, we must never
564 report *ADDR_P outside of any ADDR_WATCH..ADDR_WATCH+LEN
565 range. ADDR_WATCH <= ADDR_TRAP < ADDR_ORIG is a false
566 positive on kernels older than 4.10. See PR
572 return (CORE_ADDR
) 0;
575 /* Implementation of linux target ops method "low_stopped_by_watchpoint". */
578 aarch64_target::low_stopped_by_watchpoint ()
580 return (low_stopped_data_address () != 0);
583 /* Fetch the thread-local storage pointer for libthread_db. */
586 ps_get_thread_area (struct ps_prochandle
*ph
,
587 lwpid_t lwpid
, int idx
, void **base
)
589 return aarch64_ps_get_thread_area (ph
, lwpid
, idx
, base
,
593 /* Implementation of linux target ops method "low_siginfo_fixup". */
596 aarch64_target::low_siginfo_fixup (siginfo_t
*native
, gdb_byte
*inf
,
599 /* Is the inferior 32-bit? If so, then fixup the siginfo object. */
600 if (!is_64bit_tdesc ())
603 aarch64_compat_siginfo_from_siginfo ((struct compat_siginfo
*) inf
,
606 aarch64_siginfo_from_compat_siginfo (native
,
607 (struct compat_siginfo
*) inf
);
615 /* Implementation of linux target ops method "low_new_process". */
618 aarch64_target::low_new_process ()
620 struct arch_process_info
*info
= XCNEW (struct arch_process_info
);
622 aarch64_init_debug_reg_state (&info
->debug_reg_state
);
627 /* Implementation of linux target ops method "low_delete_process". */
630 aarch64_target::low_delete_process (arch_process_info
*info
)
636 aarch64_target::low_new_thread (lwp_info
*lwp
)
638 aarch64_linux_new_thread (lwp
);
642 aarch64_target::low_delete_thread (arch_lwp_info
*arch_lwp
)
644 aarch64_linux_delete_thread (arch_lwp
);
647 /* Implementation of linux target ops method "low_new_fork". */
650 aarch64_target::low_new_fork (process_info
*parent
,
653 /* These are allocated by linux_add_process. */
654 gdb_assert (parent
->priv
!= NULL
655 && parent
->priv
->arch_private
!= NULL
);
656 gdb_assert (child
->priv
!= NULL
657 && child
->priv
->arch_private
!= NULL
);
659 /* Linux kernel before 2.6.33 commit
660 72f674d203cd230426437cdcf7dd6f681dad8b0d
661 will inherit hardware debug registers from parent
662 on fork/vfork/clone. Newer Linux kernels create such tasks with
663 zeroed debug registers.
665 GDB core assumes the child inherits the watchpoints/hw
666 breakpoints of the parent, and will remove them all from the
667 forked off process. Copy the debug registers mirrors into the
668 new process so that all breakpoints and watchpoints can be
669 removed together. The debug registers mirror will become zeroed
670 in the end before detaching the forked off process, thus making
671 this compatible with older Linux kernels too. */
673 *child
->priv
->arch_private
= *parent
->priv
->arch_private
;
676 /* Wrapper for aarch64_sve_regs_copy_to_reg_buf. */
679 aarch64_sve_regs_copy_to_regcache (struct regcache
*regcache
, const void *buf
)
681 return aarch64_sve_regs_copy_to_reg_buf (regcache
, buf
);
684 /* Wrapper for aarch64_sve_regs_copy_from_reg_buf. */
687 aarch64_sve_regs_copy_from_regcache (struct regcache
*regcache
, void *buf
)
689 return aarch64_sve_regs_copy_from_reg_buf (regcache
, buf
);
692 /* Array containing all the possible register sets for AArch64/Linux. During
693 architecture setup, these will be checked against the HWCAP/HWCAP2 bits for
694 validity and enabled/disabled accordingly.
696 Their sizes are set to 0 here, but they will be adjusted later depending
697 on whether each register set is available or not. */
698 static struct regset_info aarch64_regsets
[] =
701 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PRSTATUS
,
703 aarch64_fill_gregset
, aarch64_store_gregset
},
704 /* Floating Point (FPU) registers. */
705 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_FPREGSET
,
707 aarch64_fill_fpregset
, aarch64_store_fpregset
709 /* Scalable Vector Extension (SVE) registers. */
710 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_ARM_SVE
,
712 aarch64_sve_regs_copy_from_regcache
, aarch64_sve_regs_copy_to_regcache
715 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_ARM_PAC_MASK
,
717 nullptr, aarch64_store_pauthregset
},
718 /* Tagged address control / MTE registers. */
719 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_ARM_TAGGED_ADDR_CTRL
,
721 aarch64_fill_mteregset
, aarch64_store_mteregset
},
725 static struct regsets_info aarch64_regsets_info
=
727 aarch64_regsets
, /* regsets */
729 nullptr, /* disabled_regsets */
732 static struct regs_info regs_info_aarch64
=
734 nullptr, /* regset_bitmap */
735 nullptr, /* usrregs */
736 &aarch64_regsets_info
,
739 /* Given FEATURES, adjust the available register sets by setting their
740 sizes. A size of 0 means the register set is disabled and won't be
744 aarch64_adjust_register_sets (const struct aarch64_features
&features
)
746 struct regset_info
*regset
;
748 for (regset
= aarch64_regsets
; regset
->size
>= 0; regset
++)
750 switch (regset
->nt_type
)
753 /* General purpose registers are always present. */
754 regset
->size
= sizeof (struct user_pt_regs
);
757 /* This is unavailable when SVE is present. */
759 regset
->size
= sizeof (struct user_fpsimd_state
);
763 regset
->size
= SVE_PT_SIZE (AARCH64_MAX_SVE_VQ
, SVE_PT_REGS_SVE
);
765 case NT_ARM_PAC_MASK
:
767 regset
->size
= AARCH64_PAUTH_REGS_SIZE
;
769 case NT_ARM_TAGGED_ADDR_CTRL
:
771 regset
->size
= AARCH64_LINUX_SIZEOF_MTE
;
774 gdb_assert_not_reached ("Unknown register set found.");
779 /* Matches HWCAP_PACA in kernel header arch/arm64/include/uapi/asm/hwcap.h. */
780 #define AARCH64_HWCAP_PACA (1 << 30)
782 /* Implementation of linux target ops method "low_arch_setup". */
785 aarch64_target::low_arch_setup ()
787 unsigned int machine
;
791 tid
= lwpid_of (current_thread
);
793 is_elf64
= linux_pid_exe_is_elf_64_file (tid
, &machine
);
797 struct aarch64_features features
;
799 uint64_t vq
= aarch64_sve_get_vq (tid
);
800 features
.sve
= (vq
> 0);
801 /* A-profile PAC is 64-bit only. */
802 features
.pauth
= linux_get_hwcap (8) & AARCH64_HWCAP_PACA
;
803 /* A-profile MTE is 64-bit only. */
804 features
.mte
= linux_get_hwcap2 (8) & HWCAP2_MTE
;
806 current_process ()->tdesc
807 = aarch64_linux_read_description (vq
, features
.pauth
, features
.mte
);
809 /* Adjust the register sets we should use for this particular set of
811 aarch64_adjust_register_sets (features
);
814 current_process ()->tdesc
= aarch32_linux_read_description ();
816 aarch64_linux_get_debug_reg_capacity (lwpid_of (current_thread
));
819 /* Implementation of linux target ops method "get_regs_info". */
822 aarch64_target::get_regs_info ()
824 if (!is_64bit_tdesc ())
825 return ®s_info_aarch32
;
827 /* AArch64 64-bit registers. */
828 return ®s_info_aarch64
;
831 /* Implementation of target ops method "supports_tracepoints". */
834 aarch64_target::supports_tracepoints ()
836 if (current_thread
== NULL
)
840 /* We don't support tracepoints on aarch32 now. */
841 return is_64bit_tdesc ();
845 /* Implementation of linux target ops method "low_get_thread_area". */
848 aarch64_target::low_get_thread_area (int lwpid
, CORE_ADDR
*addrp
)
853 iovec
.iov_base
= ®
;
854 iovec
.iov_len
= sizeof (reg
);
856 if (ptrace (PTRACE_GETREGSET
, lwpid
, NT_ARM_TLS
, &iovec
) != 0)
865 aarch64_target::low_supports_catch_syscall ()
870 /* Implementation of linux target ops method "low_get_syscall_trapinfo". */
873 aarch64_target::low_get_syscall_trapinfo (regcache
*regcache
, int *sysno
)
875 int use_64bit
= register_size (regcache
->tdesc
, 0) == 8;
881 collect_register_by_name (regcache
, "x8", &l_sysno
);
882 *sysno
= (int) l_sysno
;
885 collect_register_by_name (regcache
, "r7", sysno
);
888 /* List of condition codes that we need. */
890 enum aarch64_condition_codes
901 enum aarch64_operand_type
907 /* Representation of an operand. At this time, it only supports register
908 and immediate types. */
910 struct aarch64_operand
912 /* Type of the operand. */
913 enum aarch64_operand_type type
;
915 /* Value of the operand according to the type. */
919 struct aarch64_register reg
;
923 /* List of registers that we are currently using, we can add more here as
924 we need to use them. */
926 /* General purpose scratch registers (64 bit). */
927 static const struct aarch64_register x0
= { 0, 1 };
928 static const struct aarch64_register x1
= { 1, 1 };
929 static const struct aarch64_register x2
= { 2, 1 };
930 static const struct aarch64_register x3
= { 3, 1 };
931 static const struct aarch64_register x4
= { 4, 1 };
933 /* General purpose scratch registers (32 bit). */
934 static const struct aarch64_register w0
= { 0, 0 };
935 static const struct aarch64_register w2
= { 2, 0 };
937 /* Intra-procedure scratch registers. */
938 static const struct aarch64_register ip0
= { 16, 1 };
940 /* Special purpose registers. */
941 static const struct aarch64_register fp
= { 29, 1 };
942 static const struct aarch64_register lr
= { 30, 1 };
943 static const struct aarch64_register sp
= { 31, 1 };
944 static const struct aarch64_register xzr
= { 31, 1 };
946 /* Dynamically allocate a new register. If we know the register
947 statically, we should make it a global as above instead of using this
950 static struct aarch64_register
951 aarch64_register (unsigned num
, int is64
)
953 return (struct aarch64_register
) { num
, is64
};
956 /* Helper function to create a register operand, for instructions with
957 different types of operands.
960 p += emit_mov (p, x0, register_operand (x1)); */
962 static struct aarch64_operand
963 register_operand (struct aarch64_register reg
)
965 struct aarch64_operand operand
;
967 operand
.type
= OPERAND_REGISTER
;
973 /* Helper function to create an immediate operand, for instructions with
974 different types of operands.
977 p += emit_mov (p, x0, immediate_operand (12)); */
979 static struct aarch64_operand
980 immediate_operand (uint32_t imm
)
982 struct aarch64_operand operand
;
984 operand
.type
= OPERAND_IMMEDIATE
;
990 /* Helper function to create an offset memory operand.
993 p += emit_ldr (p, x0, sp, offset_memory_operand (16)); */
995 static struct aarch64_memory_operand
996 offset_memory_operand (int32_t offset
)
998 return (struct aarch64_memory_operand
) { MEMORY_OPERAND_OFFSET
, offset
};
1001 /* Helper function to create a pre-index memory operand.
1004 p += emit_ldr (p, x0, sp, preindex_memory_operand (16)); */
1006 static struct aarch64_memory_operand
1007 preindex_memory_operand (int32_t index
)
1009 return (struct aarch64_memory_operand
) { MEMORY_OPERAND_PREINDEX
, index
};
1012 /* Helper function to create a post-index memory operand.
1015 p += emit_ldr (p, x0, sp, postindex_memory_operand (16)); */
1017 static struct aarch64_memory_operand
1018 postindex_memory_operand (int32_t index
)
1020 return (struct aarch64_memory_operand
) { MEMORY_OPERAND_POSTINDEX
, index
};
1023 /* System control registers. These special registers can be written and
1024 read with the MRS and MSR instructions.
1026 - NZCV: Condition flags. GDB refers to this register under the CPSR
1028 - FPSR: Floating-point status register.
1029 - FPCR: Floating-point control registers.
1030 - TPIDR_EL0: Software thread ID register. */
1032 enum aarch64_system_control_registers
1034 /* op0 op1 crn crm op2 */
1035 NZCV
= (0x1 << 14) | (0x3 << 11) | (0x4 << 7) | (0x2 << 3) | 0x0,
1036 FPSR
= (0x1 << 14) | (0x3 << 11) | (0x4 << 7) | (0x4 << 3) | 0x1,
1037 FPCR
= (0x1 << 14) | (0x3 << 11) | (0x4 << 7) | (0x4 << 3) | 0x0,
1038 TPIDR_EL0
= (0x1 << 14) | (0x3 << 11) | (0xd << 7) | (0x0 << 3) | 0x2
1041 /* Write a BLR instruction into *BUF.
1045 RN is the register to branch to. */
1048 emit_blr (uint32_t *buf
, struct aarch64_register rn
)
1050 return aarch64_emit_insn (buf
, BLR
| ENCODE (rn
.num
, 5, 5));
1053 /* Write a RET instruction into *BUF.
1057 RN is the register to branch to. */
1060 emit_ret (uint32_t *buf
, struct aarch64_register rn
)
1062 return aarch64_emit_insn (buf
, RET
| ENCODE (rn
.num
, 5, 5));
1066 emit_load_store_pair (uint32_t *buf
, enum aarch64_opcodes opcode
,
1067 struct aarch64_register rt
,
1068 struct aarch64_register rt2
,
1069 struct aarch64_register rn
,
1070 struct aarch64_memory_operand operand
)
1074 uint32_t write_back
;
1077 opc
= ENCODE (2, 2, 30);
1079 opc
= ENCODE (0, 2, 30);
1081 switch (operand
.type
)
1083 case MEMORY_OPERAND_OFFSET
:
1085 pre_index
= ENCODE (1, 1, 24);
1086 write_back
= ENCODE (0, 1, 23);
1089 case MEMORY_OPERAND_POSTINDEX
:
1091 pre_index
= ENCODE (0, 1, 24);
1092 write_back
= ENCODE (1, 1, 23);
1095 case MEMORY_OPERAND_PREINDEX
:
1097 pre_index
= ENCODE (1, 1, 24);
1098 write_back
= ENCODE (1, 1, 23);
1105 return aarch64_emit_insn (buf
, opcode
| opc
| pre_index
| write_back
1106 | ENCODE (operand
.index
>> 3, 7, 15)
1107 | ENCODE (rt2
.num
, 5, 10)
1108 | ENCODE (rn
.num
, 5, 5) | ENCODE (rt
.num
, 5, 0));
1111 /* Write a STP instruction into *BUF.
1113 STP rt, rt2, [rn, #offset]
1114 STP rt, rt2, [rn, #index]!
1115 STP rt, rt2, [rn], #index
1117 RT and RT2 are the registers to store.
1118 RN is the base address register.
1119 OFFSET is the immediate to add to the base address. It is limited to a
1120 -512 .. 504 range (7 bits << 3). */
1123 emit_stp (uint32_t *buf
, struct aarch64_register rt
,
1124 struct aarch64_register rt2
, struct aarch64_register rn
,
1125 struct aarch64_memory_operand operand
)
1127 return emit_load_store_pair (buf
, STP
, rt
, rt2
, rn
, operand
);
1130 /* Write a LDP instruction into *BUF.
1132 LDP rt, rt2, [rn, #offset]
1133 LDP rt, rt2, [rn, #index]!
1134 LDP rt, rt2, [rn], #index
1136 RT and RT2 are the registers to store.
1137 RN is the base address register.
1138 OFFSET is the immediate to add to the base address. It is limited to a
1139 -512 .. 504 range (7 bits << 3). */
1142 emit_ldp (uint32_t *buf
, struct aarch64_register rt
,
1143 struct aarch64_register rt2
, struct aarch64_register rn
,
1144 struct aarch64_memory_operand operand
)
1146 return emit_load_store_pair (buf
, LDP
, rt
, rt2
, rn
, operand
);
1149 /* Write a LDP (SIMD&VFP) instruction using Q registers into *BUF.
1151 LDP qt, qt2, [rn, #offset]
1153 RT and RT2 are the Q registers to store.
1154 RN is the base address register.
1155 OFFSET is the immediate to add to the base address. It is limited to
1156 -1024 .. 1008 range (7 bits << 4). */
1159 emit_ldp_q_offset (uint32_t *buf
, unsigned rt
, unsigned rt2
,
1160 struct aarch64_register rn
, int32_t offset
)
1162 uint32_t opc
= ENCODE (2, 2, 30);
1163 uint32_t pre_index
= ENCODE (1, 1, 24);
1165 return aarch64_emit_insn (buf
, LDP_SIMD_VFP
| opc
| pre_index
1166 | ENCODE (offset
>> 4, 7, 15)
1167 | ENCODE (rt2
, 5, 10)
1168 | ENCODE (rn
.num
, 5, 5) | ENCODE (rt
, 5, 0));
1171 /* Write a STP (SIMD&VFP) instruction using Q registers into *BUF.
1173 STP qt, qt2, [rn, #offset]
1175 RT and RT2 are the Q registers to store.
1176 RN is the base address register.
1177 OFFSET is the immediate to add to the base address. It is limited to
1178 -1024 .. 1008 range (7 bits << 4). */
1181 emit_stp_q_offset (uint32_t *buf
, unsigned rt
, unsigned rt2
,
1182 struct aarch64_register rn
, int32_t offset
)
1184 uint32_t opc
= ENCODE (2, 2, 30);
1185 uint32_t pre_index
= ENCODE (1, 1, 24);
1187 return aarch64_emit_insn (buf
, STP_SIMD_VFP
| opc
| pre_index
1188 | ENCODE (offset
>> 4, 7, 15)
1189 | ENCODE (rt2
, 5, 10)
1190 | ENCODE (rn
.num
, 5, 5) | ENCODE (rt
, 5, 0));
1193 /* Write a LDRH instruction into *BUF.
1195 LDRH wt, [xn, #offset]
1196 LDRH wt, [xn, #index]!
1197 LDRH wt, [xn], #index
1199 RT is the register to store.
1200 RN is the base address register.
1201 OFFSET is the immediate to add to the base address. It is limited to
1202 0 .. 32760 range (12 bits << 3). */
1205 emit_ldrh (uint32_t *buf
, struct aarch64_register rt
,
1206 struct aarch64_register rn
,
1207 struct aarch64_memory_operand operand
)
1209 return aarch64_emit_load_store (buf
, 1, LDR
, rt
, rn
, operand
);
1212 /* Write a LDRB instruction into *BUF.
1214 LDRB wt, [xn, #offset]
1215 LDRB wt, [xn, #index]!
1216 LDRB wt, [xn], #index
1218 RT is the register to store.
1219 RN is the base address register.
1220 OFFSET is the immediate to add to the base address. It is limited to
1221 0 .. 32760 range (12 bits << 3). */
1224 emit_ldrb (uint32_t *buf
, struct aarch64_register rt
,
1225 struct aarch64_register rn
,
1226 struct aarch64_memory_operand operand
)
1228 return aarch64_emit_load_store (buf
, 0, LDR
, rt
, rn
, operand
);
1233 /* Write a STR instruction into *BUF.
1235 STR rt, [rn, #offset]
1236 STR rt, [rn, #index]!
1237 STR rt, [rn], #index
1239 RT is the register to store.
1240 RN is the base address register.
1241 OFFSET is the immediate to add to the base address. It is limited to
1242 0 .. 32760 range (12 bits << 3). */
1245 emit_str (uint32_t *buf
, struct aarch64_register rt
,
1246 struct aarch64_register rn
,
1247 struct aarch64_memory_operand operand
)
1249 return aarch64_emit_load_store (buf
, rt
.is64
? 3 : 2, STR
, rt
, rn
, operand
);
1252 /* Helper function emitting an exclusive load or store instruction. */
1255 emit_load_store_exclusive (uint32_t *buf
, uint32_t size
,
1256 enum aarch64_opcodes opcode
,
1257 struct aarch64_register rs
,
1258 struct aarch64_register rt
,
1259 struct aarch64_register rt2
,
1260 struct aarch64_register rn
)
1262 return aarch64_emit_insn (buf
, opcode
| ENCODE (size
, 2, 30)
1263 | ENCODE (rs
.num
, 5, 16) | ENCODE (rt2
.num
, 5, 10)
1264 | ENCODE (rn
.num
, 5, 5) | ENCODE (rt
.num
, 5, 0));
1267 /* Write a LAXR instruction into *BUF.
1271 RT is the destination register.
1272 RN is the base address register. */
1275 emit_ldaxr (uint32_t *buf
, struct aarch64_register rt
,
1276 struct aarch64_register rn
)
1278 return emit_load_store_exclusive (buf
, rt
.is64
? 3 : 2, LDAXR
, xzr
, rt
,
1282 /* Write a STXR instruction into *BUF.
1286 RS is the result register, it indicates if the store succeeded or not.
1287 RT is the destination register.
1288 RN is the base address register. */
1291 emit_stxr (uint32_t *buf
, struct aarch64_register rs
,
1292 struct aarch64_register rt
, struct aarch64_register rn
)
1294 return emit_load_store_exclusive (buf
, rt
.is64
? 3 : 2, STXR
, rs
, rt
,
1298 /* Write a STLR instruction into *BUF.
1302 RT is the register to store.
1303 RN is the base address register. */
1306 emit_stlr (uint32_t *buf
, struct aarch64_register rt
,
1307 struct aarch64_register rn
)
1309 return emit_load_store_exclusive (buf
, rt
.is64
? 3 : 2, STLR
, xzr
, rt
,
1313 /* Helper function for data processing instructions with register sources. */
1316 emit_data_processing_reg (uint32_t *buf
, uint32_t opcode
,
1317 struct aarch64_register rd
,
1318 struct aarch64_register rn
,
1319 struct aarch64_register rm
)
1321 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1323 return aarch64_emit_insn (buf
, opcode
| size
| ENCODE (rm
.num
, 5, 16)
1324 | ENCODE (rn
.num
, 5, 5) | ENCODE (rd
.num
, 5, 0));
1327 /* Helper function for data processing instructions taking either a register
1331 emit_data_processing (uint32_t *buf
, enum aarch64_opcodes opcode
,
1332 struct aarch64_register rd
,
1333 struct aarch64_register rn
,
1334 struct aarch64_operand operand
)
1336 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1337 /* The opcode is different for register and immediate source operands. */
1338 uint32_t operand_opcode
;
1340 if (operand
.type
== OPERAND_IMMEDIATE
)
1342 /* xxx1 000x xxxx xxxx xxxx xxxx xxxx xxxx */
1343 operand_opcode
= ENCODE (8, 4, 25);
1345 return aarch64_emit_insn (buf
, opcode
| operand_opcode
| size
1346 | ENCODE (operand
.imm
, 12, 10)
1347 | ENCODE (rn
.num
, 5, 5)
1348 | ENCODE (rd
.num
, 5, 0));
1352 /* xxx0 101x xxxx xxxx xxxx xxxx xxxx xxxx */
1353 operand_opcode
= ENCODE (5, 4, 25);
1355 return emit_data_processing_reg (buf
, opcode
| operand_opcode
, rd
,
1360 /* Write an ADD instruction into *BUF.
1365 This function handles both an immediate and register add.
1367 RD is the destination register.
1368 RN is the input register.
1369 OPERAND is the source operand, either of type OPERAND_IMMEDIATE or
1370 OPERAND_REGISTER. */
1373 emit_add (uint32_t *buf
, struct aarch64_register rd
,
1374 struct aarch64_register rn
, struct aarch64_operand operand
)
1376 return emit_data_processing (buf
, ADD
, rd
, rn
, operand
);
1379 /* Write a SUB instruction into *BUF.
1384 This function handles both an immediate and register sub.
1386 RD is the destination register.
1387 RN is the input register.
1388 IMM is the immediate to substract to RN. */
1391 emit_sub (uint32_t *buf
, struct aarch64_register rd
,
1392 struct aarch64_register rn
, struct aarch64_operand operand
)
1394 return emit_data_processing (buf
, SUB
, rd
, rn
, operand
);
1397 /* Write a MOV instruction into *BUF.
1402 This function handles both a wide immediate move and a register move,
1403 with the condition that the source register is not xzr. xzr and the
1404 stack pointer share the same encoding and this function only supports
1407 RD is the destination register.
1408 OPERAND is the source operand, either of type OPERAND_IMMEDIATE or
1409 OPERAND_REGISTER. */
1412 emit_mov (uint32_t *buf
, struct aarch64_register rd
,
1413 struct aarch64_operand operand
)
1415 if (operand
.type
== OPERAND_IMMEDIATE
)
1417 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1418 /* Do not shift the immediate. */
1419 uint32_t shift
= ENCODE (0, 2, 21);
1421 return aarch64_emit_insn (buf
, MOV
| size
| shift
1422 | ENCODE (operand
.imm
, 16, 5)
1423 | ENCODE (rd
.num
, 5, 0));
1426 return emit_add (buf
, rd
, operand
.reg
, immediate_operand (0));
1429 /* Write a MOVK instruction into *BUF.
1431 MOVK rd, #imm, lsl #shift
1433 RD is the destination register.
1434 IMM is the immediate.
1435 SHIFT is the logical shift left to apply to IMM. */
1438 emit_movk (uint32_t *buf
, struct aarch64_register rd
, uint32_t imm
,
1441 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1443 return aarch64_emit_insn (buf
, MOVK
| size
| ENCODE (shift
, 2, 21) |
1444 ENCODE (imm
, 16, 5) | ENCODE (rd
.num
, 5, 0));
1447 /* Write instructions into *BUF in order to move ADDR into a register.
1448 ADDR can be a 64-bit value.
1450 This function will emit a series of MOV and MOVK instructions, such as:
1453 MOVK xd, #(addr >> 16), lsl #16
1454 MOVK xd, #(addr >> 32), lsl #32
1455 MOVK xd, #(addr >> 48), lsl #48 */
1458 emit_mov_addr (uint32_t *buf
, struct aarch64_register rd
, CORE_ADDR addr
)
1462 /* The MOV (wide immediate) instruction clears to top bits of the
1464 p
+= emit_mov (p
, rd
, immediate_operand (addr
& 0xffff));
1466 if ((addr
>> 16) != 0)
1467 p
+= emit_movk (p
, rd
, (addr
>> 16) & 0xffff, 1);
1471 if ((addr
>> 32) != 0)
1472 p
+= emit_movk (p
, rd
, (addr
>> 32) & 0xffff, 2);
1476 if ((addr
>> 48) != 0)
1477 p
+= emit_movk (p
, rd
, (addr
>> 48) & 0xffff, 3);
1482 /* Write a SUBS instruction into *BUF.
1486 This instruction update the condition flags.
1488 RD is the destination register.
1489 RN and RM are the source registers. */
1492 emit_subs (uint32_t *buf
, struct aarch64_register rd
,
1493 struct aarch64_register rn
, struct aarch64_operand operand
)
1495 return emit_data_processing (buf
, SUBS
, rd
, rn
, operand
);
1498 /* Write a CMP instruction into *BUF.
1502 This instruction is an alias of SUBS xzr, rn, rm.
1504 RN and RM are the registers to compare. */
1507 emit_cmp (uint32_t *buf
, struct aarch64_register rn
,
1508 struct aarch64_operand operand
)
1510 return emit_subs (buf
, xzr
, rn
, operand
);
1513 /* Write a AND instruction into *BUF.
1517 RD is the destination register.
1518 RN and RM are the source registers. */
1521 emit_and (uint32_t *buf
, struct aarch64_register rd
,
1522 struct aarch64_register rn
, struct aarch64_register rm
)
1524 return emit_data_processing_reg (buf
, AND
, rd
, rn
, rm
);
1527 /* Write a ORR instruction into *BUF.
1531 RD is the destination register.
1532 RN and RM are the source registers. */
1535 emit_orr (uint32_t *buf
, struct aarch64_register rd
,
1536 struct aarch64_register rn
, struct aarch64_register rm
)
1538 return emit_data_processing_reg (buf
, ORR
, rd
, rn
, rm
);
1541 /* Write a ORN instruction into *BUF.
1545 RD is the destination register.
1546 RN and RM are the source registers. */
1549 emit_orn (uint32_t *buf
, struct aarch64_register rd
,
1550 struct aarch64_register rn
, struct aarch64_register rm
)
1552 return emit_data_processing_reg (buf
, ORN
, rd
, rn
, rm
);
1555 /* Write a EOR instruction into *BUF.
1559 RD is the destination register.
1560 RN and RM are the source registers. */
1563 emit_eor (uint32_t *buf
, struct aarch64_register rd
,
1564 struct aarch64_register rn
, struct aarch64_register rm
)
1566 return emit_data_processing_reg (buf
, EOR
, rd
, rn
, rm
);
1569 /* Write a MVN instruction into *BUF.
1573 This is an alias for ORN rd, xzr, rm.
1575 RD is the destination register.
1576 RM is the source register. */
1579 emit_mvn (uint32_t *buf
, struct aarch64_register rd
,
1580 struct aarch64_register rm
)
1582 return emit_orn (buf
, rd
, xzr
, rm
);
1585 /* Write a LSLV instruction into *BUF.
1589 RD is the destination register.
1590 RN and RM are the source registers. */
1593 emit_lslv (uint32_t *buf
, struct aarch64_register rd
,
1594 struct aarch64_register rn
, struct aarch64_register rm
)
1596 return emit_data_processing_reg (buf
, LSLV
, rd
, rn
, rm
);
1599 /* Write a LSRV instruction into *BUF.
1603 RD is the destination register.
1604 RN and RM are the source registers. */
1607 emit_lsrv (uint32_t *buf
, struct aarch64_register rd
,
1608 struct aarch64_register rn
, struct aarch64_register rm
)
1610 return emit_data_processing_reg (buf
, LSRV
, rd
, rn
, rm
);
1613 /* Write a ASRV instruction into *BUF.
1617 RD is the destination register.
1618 RN and RM are the source registers. */
1621 emit_asrv (uint32_t *buf
, struct aarch64_register rd
,
1622 struct aarch64_register rn
, struct aarch64_register rm
)
1624 return emit_data_processing_reg (buf
, ASRV
, rd
, rn
, rm
);
1627 /* Write a MUL instruction into *BUF.
1631 RD is the destination register.
1632 RN and RM are the source registers. */
1635 emit_mul (uint32_t *buf
, struct aarch64_register rd
,
1636 struct aarch64_register rn
, struct aarch64_register rm
)
1638 return emit_data_processing_reg (buf
, MUL
, rd
, rn
, rm
);
1641 /* Write a MRS instruction into *BUF. The register size is 64-bit.
1645 RT is the destination register.
1646 SYSTEM_REG is special purpose register to read. */
1649 emit_mrs (uint32_t *buf
, struct aarch64_register rt
,
1650 enum aarch64_system_control_registers system_reg
)
1652 return aarch64_emit_insn (buf
, MRS
| ENCODE (system_reg
, 15, 5)
1653 | ENCODE (rt
.num
, 5, 0));
1656 /* Write a MSR instruction into *BUF. The register size is 64-bit.
1660 SYSTEM_REG is special purpose register to write.
1661 RT is the input register. */
1664 emit_msr (uint32_t *buf
, enum aarch64_system_control_registers system_reg
,
1665 struct aarch64_register rt
)
1667 return aarch64_emit_insn (buf
, MSR
| ENCODE (system_reg
, 15, 5)
1668 | ENCODE (rt
.num
, 5, 0));
1671 /* Write a SEVL instruction into *BUF.
1673 This is a hint instruction telling the hardware to trigger an event. */
1676 emit_sevl (uint32_t *buf
)
1678 return aarch64_emit_insn (buf
, SEVL
);
1681 /* Write a WFE instruction into *BUF.
1683 This is a hint instruction telling the hardware to wait for an event. */
1686 emit_wfe (uint32_t *buf
)
1688 return aarch64_emit_insn (buf
, WFE
);
1691 /* Write a SBFM instruction into *BUF.
1693 SBFM rd, rn, #immr, #imms
1695 This instruction moves the bits from #immr to #imms into the
1696 destination, sign extending the result.
1698 RD is the destination register.
1699 RN is the source register.
1700 IMMR is the bit number to start at (least significant bit).
1701 IMMS is the bit number to stop at (most significant bit). */
1704 emit_sbfm (uint32_t *buf
, struct aarch64_register rd
,
1705 struct aarch64_register rn
, uint32_t immr
, uint32_t imms
)
1707 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1708 uint32_t n
= ENCODE (rd
.is64
, 1, 22);
1710 return aarch64_emit_insn (buf
, SBFM
| size
| n
| ENCODE (immr
, 6, 16)
1711 | ENCODE (imms
, 6, 10) | ENCODE (rn
.num
, 5, 5)
1712 | ENCODE (rd
.num
, 5, 0));
1715 /* Write a SBFX instruction into *BUF.
1717 SBFX rd, rn, #lsb, #width
1719 This instruction moves #width bits from #lsb into the destination, sign
1720 extending the result. This is an alias for:
1722 SBFM rd, rn, #lsb, #(lsb + width - 1)
1724 RD is the destination register.
1725 RN is the source register.
1726 LSB is the bit number to start at (least significant bit).
1727 WIDTH is the number of bits to move. */
1730 emit_sbfx (uint32_t *buf
, struct aarch64_register rd
,
1731 struct aarch64_register rn
, uint32_t lsb
, uint32_t width
)
1733 return emit_sbfm (buf
, rd
, rn
, lsb
, lsb
+ width
- 1);
1736 /* Write a UBFM instruction into *BUF.
1738 UBFM rd, rn, #immr, #imms
1740 This instruction moves the bits from #immr to #imms into the
1741 destination, extending the result with zeros.
1743 RD is the destination register.
1744 RN is the source register.
1745 IMMR is the bit number to start at (least significant bit).
1746 IMMS is the bit number to stop at (most significant bit). */
1749 emit_ubfm (uint32_t *buf
, struct aarch64_register rd
,
1750 struct aarch64_register rn
, uint32_t immr
, uint32_t imms
)
1752 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1753 uint32_t n
= ENCODE (rd
.is64
, 1, 22);
1755 return aarch64_emit_insn (buf
, UBFM
| size
| n
| ENCODE (immr
, 6, 16)
1756 | ENCODE (imms
, 6, 10) | ENCODE (rn
.num
, 5, 5)
1757 | ENCODE (rd
.num
, 5, 0));
1760 /* Write a UBFX instruction into *BUF.
1762 UBFX rd, rn, #lsb, #width
1764 This instruction moves #width bits from #lsb into the destination,
1765 extending the result with zeros. This is an alias for:
1767 UBFM rd, rn, #lsb, #(lsb + width - 1)
1769 RD is the destination register.
1770 RN is the source register.
1771 LSB is the bit number to start at (least significant bit).
1772 WIDTH is the number of bits to move. */
1775 emit_ubfx (uint32_t *buf
, struct aarch64_register rd
,
1776 struct aarch64_register rn
, uint32_t lsb
, uint32_t width
)
1778 return emit_ubfm (buf
, rd
, rn
, lsb
, lsb
+ width
- 1);
1781 /* Write a CSINC instruction into *BUF.
1783 CSINC rd, rn, rm, cond
1785 This instruction conditionally increments rn or rm and places the result
1786 in rd. rn is chosen is the condition is true.
1788 RD is the destination register.
1789 RN and RM are the source registers.
1790 COND is the encoded condition. */
1793 emit_csinc (uint32_t *buf
, struct aarch64_register rd
,
1794 struct aarch64_register rn
, struct aarch64_register rm
,
1797 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1799 return aarch64_emit_insn (buf
, CSINC
| size
| ENCODE (rm
.num
, 5, 16)
1800 | ENCODE (cond
, 4, 12) | ENCODE (rn
.num
, 5, 5)
1801 | ENCODE (rd
.num
, 5, 0));
1804 /* Write a CSET instruction into *BUF.
1808 This instruction conditionally write 1 or 0 in the destination register.
1809 1 is written if the condition is true. This is an alias for:
1811 CSINC rd, xzr, xzr, !cond
1813 Note that the condition needs to be inverted.
1815 RD is the destination register.
1816 RN and RM are the source registers.
1817 COND is the encoded condition. */
1820 emit_cset (uint32_t *buf
, struct aarch64_register rd
, unsigned cond
)
1822 /* The least significant bit of the condition needs toggling in order to
1824 return emit_csinc (buf
, rd
, xzr
, xzr
, cond
^ 0x1);
1827 /* Write LEN instructions from BUF into the inferior memory at *TO.
1829 Note instructions are always little endian on AArch64, unlike data. */
1832 append_insns (CORE_ADDR
*to
, size_t len
, const uint32_t *buf
)
1834 size_t byte_len
= len
* sizeof (uint32_t);
1835 #if (__BYTE_ORDER == __BIG_ENDIAN)
1836 uint32_t *le_buf
= (uint32_t *) xmalloc (byte_len
);
1839 for (i
= 0; i
< len
; i
++)
1840 le_buf
[i
] = htole32 (buf
[i
]);
1842 target_write_memory (*to
, (const unsigned char *) le_buf
, byte_len
);
1846 target_write_memory (*to
, (const unsigned char *) buf
, byte_len
);
1852 /* Sub-class of struct aarch64_insn_data, store information of
1853 instruction relocation for fast tracepoint. Visitor can
1854 relocate an instruction from BASE.INSN_ADDR to NEW_ADDR and save
1855 the relocated instructions in buffer pointed by INSN_PTR. */
1857 struct aarch64_insn_relocation_data
1859 struct aarch64_insn_data base
;
1861 /* The new address the instruction is relocated to. */
1863 /* Pointer to the buffer of relocated instruction(s). */
1867 /* Implementation of aarch64_insn_visitor method "b". */
1870 aarch64_ftrace_insn_reloc_b (const int is_bl
, const int32_t offset
,
1871 struct aarch64_insn_data
*data
)
1873 struct aarch64_insn_relocation_data
*insn_reloc
1874 = (struct aarch64_insn_relocation_data
*) data
;
1876 = insn_reloc
->base
.insn_addr
- insn_reloc
->new_addr
+ offset
;
1878 if (can_encode_int32 (new_offset
, 28))
1879 insn_reloc
->insn_ptr
+= emit_b (insn_reloc
->insn_ptr
, is_bl
, new_offset
);
1882 /* Implementation of aarch64_insn_visitor method "b_cond". */
1885 aarch64_ftrace_insn_reloc_b_cond (const unsigned cond
, const int32_t offset
,
1886 struct aarch64_insn_data
*data
)
1888 struct aarch64_insn_relocation_data
*insn_reloc
1889 = (struct aarch64_insn_relocation_data
*) data
;
1891 = insn_reloc
->base
.insn_addr
- insn_reloc
->new_addr
+ offset
;
1893 if (can_encode_int32 (new_offset
, 21))
1895 insn_reloc
->insn_ptr
+= emit_bcond (insn_reloc
->insn_ptr
, cond
,
1898 else if (can_encode_int32 (new_offset
, 28))
1900 /* The offset is out of range for a conditional branch
1901 instruction but not for a unconditional branch. We can use
1902 the following instructions instead:
1904 B.COND TAKEN ; If cond is true, then jump to TAKEN.
1905 B NOT_TAKEN ; Else jump over TAKEN and continue.
1912 insn_reloc
->insn_ptr
+= emit_bcond (insn_reloc
->insn_ptr
, cond
, 8);
1913 insn_reloc
->insn_ptr
+= emit_b (insn_reloc
->insn_ptr
, 0, 8);
1914 insn_reloc
->insn_ptr
+= emit_b (insn_reloc
->insn_ptr
, 0, new_offset
- 8);
1918 /* Implementation of aarch64_insn_visitor method "cb". */
1921 aarch64_ftrace_insn_reloc_cb (const int32_t offset
, const int is_cbnz
,
1922 const unsigned rn
, int is64
,
1923 struct aarch64_insn_data
*data
)
1925 struct aarch64_insn_relocation_data
*insn_reloc
1926 = (struct aarch64_insn_relocation_data
*) data
;
1928 = insn_reloc
->base
.insn_addr
- insn_reloc
->new_addr
+ offset
;
1930 if (can_encode_int32 (new_offset
, 21))
1932 insn_reloc
->insn_ptr
+= emit_cb (insn_reloc
->insn_ptr
, is_cbnz
,
1933 aarch64_register (rn
, is64
), new_offset
);
1935 else if (can_encode_int32 (new_offset
, 28))
1937 /* The offset is out of range for a compare and branch
1938 instruction but not for a unconditional branch. We can use
1939 the following instructions instead:
1941 CBZ xn, TAKEN ; xn == 0, then jump to TAKEN.
1942 B NOT_TAKEN ; Else jump over TAKEN and continue.
1948 insn_reloc
->insn_ptr
+= emit_cb (insn_reloc
->insn_ptr
, is_cbnz
,
1949 aarch64_register (rn
, is64
), 8);
1950 insn_reloc
->insn_ptr
+= emit_b (insn_reloc
->insn_ptr
, 0, 8);
1951 insn_reloc
->insn_ptr
+= emit_b (insn_reloc
->insn_ptr
, 0, new_offset
- 8);
1955 /* Implementation of aarch64_insn_visitor method "tb". */
1958 aarch64_ftrace_insn_reloc_tb (const int32_t offset
, int is_tbnz
,
1959 const unsigned rt
, unsigned bit
,
1960 struct aarch64_insn_data
*data
)
1962 struct aarch64_insn_relocation_data
*insn_reloc
1963 = (struct aarch64_insn_relocation_data
*) data
;
1965 = insn_reloc
->base
.insn_addr
- insn_reloc
->new_addr
+ offset
;
1967 if (can_encode_int32 (new_offset
, 16))
1969 insn_reloc
->insn_ptr
+= emit_tb (insn_reloc
->insn_ptr
, is_tbnz
, bit
,
1970 aarch64_register (rt
, 1), new_offset
);
1972 else if (can_encode_int32 (new_offset
, 28))
1974 /* The offset is out of range for a test bit and branch
1975 instruction but not for a unconditional branch. We can use
1976 the following instructions instead:
1978 TBZ xn, #bit, TAKEN ; xn[bit] == 0, then jump to TAKEN.
1979 B NOT_TAKEN ; Else jump over TAKEN and continue.
1985 insn_reloc
->insn_ptr
+= emit_tb (insn_reloc
->insn_ptr
, is_tbnz
, bit
,
1986 aarch64_register (rt
, 1), 8);
1987 insn_reloc
->insn_ptr
+= emit_b (insn_reloc
->insn_ptr
, 0, 8);
1988 insn_reloc
->insn_ptr
+= emit_b (insn_reloc
->insn_ptr
, 0,
1993 /* Implementation of aarch64_insn_visitor method "adr". */
1996 aarch64_ftrace_insn_reloc_adr (const int32_t offset
, const unsigned rd
,
1998 struct aarch64_insn_data
*data
)
2000 struct aarch64_insn_relocation_data
*insn_reloc
2001 = (struct aarch64_insn_relocation_data
*) data
;
2002 /* We know exactly the address the ADR{P,} instruction will compute.
2003 We can just write it to the destination register. */
2004 CORE_ADDR address
= data
->insn_addr
+ offset
;
2008 /* Clear the lower 12 bits of the offset to get the 4K page. */
2009 insn_reloc
->insn_ptr
+= emit_mov_addr (insn_reloc
->insn_ptr
,
2010 aarch64_register (rd
, 1),
2014 insn_reloc
->insn_ptr
+= emit_mov_addr (insn_reloc
->insn_ptr
,
2015 aarch64_register (rd
, 1), address
);
2018 /* Implementation of aarch64_insn_visitor method "ldr_literal". */
2021 aarch64_ftrace_insn_reloc_ldr_literal (const int32_t offset
, const int is_sw
,
2022 const unsigned rt
, const int is64
,
2023 struct aarch64_insn_data
*data
)
2025 struct aarch64_insn_relocation_data
*insn_reloc
2026 = (struct aarch64_insn_relocation_data
*) data
;
2027 CORE_ADDR address
= data
->insn_addr
+ offset
;
2029 insn_reloc
->insn_ptr
+= emit_mov_addr (insn_reloc
->insn_ptr
,
2030 aarch64_register (rt
, 1), address
);
2032 /* We know exactly what address to load from, and what register we
2035 MOV xd, #(oldloc + offset)
2036 MOVK xd, #((oldloc + offset) >> 16), lsl #16
2039 LDR xd, [xd] ; or LDRSW xd, [xd]
2044 insn_reloc
->insn_ptr
+= emit_ldrsw (insn_reloc
->insn_ptr
,
2045 aarch64_register (rt
, 1),
2046 aarch64_register (rt
, 1),
2047 offset_memory_operand (0));
2049 insn_reloc
->insn_ptr
+= emit_ldr (insn_reloc
->insn_ptr
,
2050 aarch64_register (rt
, is64
),
2051 aarch64_register (rt
, 1),
2052 offset_memory_operand (0));
2055 /* Implementation of aarch64_insn_visitor method "others". */
2058 aarch64_ftrace_insn_reloc_others (const uint32_t insn
,
2059 struct aarch64_insn_data
*data
)
2061 struct aarch64_insn_relocation_data
*insn_reloc
2062 = (struct aarch64_insn_relocation_data
*) data
;
2064 /* The instruction is not PC relative. Just re-emit it at the new
2066 insn_reloc
->insn_ptr
+= aarch64_emit_insn (insn_reloc
->insn_ptr
, insn
);
2069 static const struct aarch64_insn_visitor visitor
=
2071 aarch64_ftrace_insn_reloc_b
,
2072 aarch64_ftrace_insn_reloc_b_cond
,
2073 aarch64_ftrace_insn_reloc_cb
,
2074 aarch64_ftrace_insn_reloc_tb
,
2075 aarch64_ftrace_insn_reloc_adr
,
2076 aarch64_ftrace_insn_reloc_ldr_literal
,
2077 aarch64_ftrace_insn_reloc_others
,
2081 aarch64_target::supports_fast_tracepoints ()
2086 /* Implementation of target ops method
2087 "install_fast_tracepoint_jump_pad". */
2090 aarch64_target::install_fast_tracepoint_jump_pad
2091 (CORE_ADDR tpoint
, CORE_ADDR tpaddr
, CORE_ADDR collector
,
2092 CORE_ADDR lockaddr
, ULONGEST orig_size
, CORE_ADDR
*jump_entry
,
2093 CORE_ADDR
*trampoline
, ULONGEST
*trampoline_size
,
2094 unsigned char *jjump_pad_insn
, ULONGEST
*jjump_pad_insn_size
,
2095 CORE_ADDR
*adjusted_insn_addr
, CORE_ADDR
*adjusted_insn_addr_end
,
2103 CORE_ADDR buildaddr
= *jump_entry
;
2104 struct aarch64_insn_relocation_data insn_data
;
2106 /* We need to save the current state on the stack both to restore it
2107 later and to collect register values when the tracepoint is hit.
2109 The saved registers are pushed in a layout that needs to be in sync
2110 with aarch64_ft_collect_regmap (see linux-aarch64-ipa.c). Later on
2111 the supply_fast_tracepoint_registers function will fill in the
2112 register cache from a pointer to saved registers on the stack we build
2115 For simplicity, we set the size of each cell on the stack to 16 bytes.
2116 This way one cell can hold any register type, from system registers
2117 to the 128 bit SIMD&FP registers. Furthermore, the stack pointer
2118 has to be 16 bytes aligned anyway.
2120 Note that the CPSR register does not exist on AArch64. Instead we
2121 can access system bits describing the process state with the
2122 MRS/MSR instructions, namely the condition flags. We save them as
2123 if they are part of a CPSR register because that's how GDB
2124 interprets these system bits. At the moment, only the condition
2125 flags are saved in CPSR (NZCV).
2127 Stack layout, each cell is 16 bytes (descending):
2129 High *-------- SIMD&FP registers from 31 down to 0. --------*
2135 *---- General purpose registers from 30 down to 0. ----*
2141 *------------- Special purpose registers. -------------*
2144 | CPSR (NZCV) | 5 cells
2147 *------------- collecting_t object --------------------*
2148 | TPIDR_EL0 | struct tracepoint * |
2149 Low *------------------------------------------------------*
2151 After this stack is set up, we issue a call to the collector, passing
2152 it the saved registers at (SP + 16). */
2154 /* Push SIMD&FP registers on the stack:
2156 SUB sp, sp, #(32 * 16)
2158 STP q30, q31, [sp, #(30 * 16)]
2163 p
+= emit_sub (p
, sp
, sp
, immediate_operand (32 * 16));
2164 for (i
= 30; i
>= 0; i
-= 2)
2165 p
+= emit_stp_q_offset (p
, i
, i
+ 1, sp
, i
* 16);
2167 /* Push general purpose registers on the stack. Note that we do not need
2168 to push x31 as it represents the xzr register and not the stack
2169 pointer in a STR instruction.
2171 SUB sp, sp, #(31 * 16)
2173 STR x30, [sp, #(30 * 16)]
2178 p
+= emit_sub (p
, sp
, sp
, immediate_operand (31 * 16));
2179 for (i
= 30; i
>= 0; i
-= 1)
2180 p
+= emit_str (p
, aarch64_register (i
, 1), sp
,
2181 offset_memory_operand (i
* 16));
2183 /* Make space for 5 more cells.
2185 SUB sp, sp, #(5 * 16)
2188 p
+= emit_sub (p
, sp
, sp
, immediate_operand (5 * 16));
2193 ADD x4, sp, #((32 + 31 + 5) * 16)
2194 STR x4, [sp, #(4 * 16)]
2197 p
+= emit_add (p
, x4
, sp
, immediate_operand ((32 + 31 + 5) * 16));
2198 p
+= emit_str (p
, x4
, sp
, offset_memory_operand (4 * 16));
2200 /* Save PC (tracepoint address):
2205 STR x3, [sp, #(3 * 16)]
2209 p
+= emit_mov_addr (p
, x3
, tpaddr
);
2210 p
+= emit_str (p
, x3
, sp
, offset_memory_operand (3 * 16));
2212 /* Save CPSR (NZCV), FPSR and FPCR:
2218 STR x2, [sp, #(2 * 16)]
2219 STR x1, [sp, #(1 * 16)]
2220 STR x0, [sp, #(0 * 16)]
2223 p
+= emit_mrs (p
, x2
, NZCV
);
2224 p
+= emit_mrs (p
, x1
, FPSR
);
2225 p
+= emit_mrs (p
, x0
, FPCR
);
2226 p
+= emit_str (p
, x2
, sp
, offset_memory_operand (2 * 16));
2227 p
+= emit_str (p
, x1
, sp
, offset_memory_operand (1 * 16));
2228 p
+= emit_str (p
, x0
, sp
, offset_memory_operand (0 * 16));
2230 /* Push the collecting_t object. It consist of the address of the
2231 tracepoint and an ID for the current thread. We get the latter by
2232 reading the tpidr_el0 system register. It corresponds to the
2233 NT_ARM_TLS register accessible with ptrace.
2240 STP x0, x1, [sp, #-16]!
2244 p
+= emit_mov_addr (p
, x0
, tpoint
);
2245 p
+= emit_mrs (p
, x1
, TPIDR_EL0
);
2246 p
+= emit_stp (p
, x0
, x1
, sp
, preindex_memory_operand (-16));
2250 The shared memory for the lock is at lockaddr. It will hold zero
2251 if no-one is holding the lock, otherwise it contains the address of
2252 the collecting_t object on the stack of the thread which acquired it.
2254 At this stage, the stack pointer points to this thread's collecting_t
2257 We use the following registers:
2258 - x0: Address of the lock.
2259 - x1: Pointer to collecting_t object.
2260 - x2: Scratch register.
2266 ; Trigger an event local to this core. So the following WFE
2267 ; instruction is ignored.
2270 ; Wait for an event. The event is triggered by either the SEVL
2271 ; or STLR instructions (store release).
2274 ; Atomically read at lockaddr. This marks the memory location as
2275 ; exclusive. This instruction also has memory constraints which
2276 ; make sure all previous data reads and writes are done before
2280 ; Try again if another thread holds the lock.
2283 ; We can lock it! Write the address of the collecting_t object.
2284 ; This instruction will fail if the memory location is not marked
2285 ; as exclusive anymore. If it succeeds, it will remove the
2286 ; exclusive mark on the memory location. This way, if another
2287 ; thread executes this instruction before us, we will fail and try
2294 p
+= emit_mov_addr (p
, x0
, lockaddr
);
2295 p
+= emit_mov (p
, x1
, register_operand (sp
));
2299 p
+= emit_ldaxr (p
, x2
, x0
);
2300 p
+= emit_cb (p
, 1, w2
, -2 * 4);
2301 p
+= emit_stxr (p
, w2
, x1
, x0
);
2302 p
+= emit_cb (p
, 1, x2
, -4 * 4);
2304 /* Call collector (struct tracepoint *, unsigned char *):
2309 ; Saved registers start after the collecting_t object.
2312 ; We use an intra-procedure-call scratch register.
2313 MOV ip0, #(collector)
2316 ; And call back to C!
2321 p
+= emit_mov_addr (p
, x0
, tpoint
);
2322 p
+= emit_add (p
, x1
, sp
, immediate_operand (16));
2324 p
+= emit_mov_addr (p
, ip0
, collector
);
2325 p
+= emit_blr (p
, ip0
);
2327 /* Release the lock.
2332 ; This instruction is a normal store with memory ordering
2333 ; constraints. Thanks to this we do not have to put a data
2334 ; barrier instruction to make sure all data read and writes are done
2335 ; before this instruction is executed. Furthermore, this instruction
2336 ; will trigger an event, letting other threads know they can grab
2341 p
+= emit_mov_addr (p
, x0
, lockaddr
);
2342 p
+= emit_stlr (p
, xzr
, x0
);
2344 /* Free collecting_t object:
2349 p
+= emit_add (p
, sp
, sp
, immediate_operand (16));
2351 /* Restore CPSR (NZCV), FPSR and FPCR. And free all special purpose
2352 registers from the stack.
2354 LDR x2, [sp, #(2 * 16)]
2355 LDR x1, [sp, #(1 * 16)]
2356 LDR x0, [sp, #(0 * 16)]
2362 ADD sp, sp #(5 * 16)
2365 p
+= emit_ldr (p
, x2
, sp
, offset_memory_operand (2 * 16));
2366 p
+= emit_ldr (p
, x1
, sp
, offset_memory_operand (1 * 16));
2367 p
+= emit_ldr (p
, x0
, sp
, offset_memory_operand (0 * 16));
2368 p
+= emit_msr (p
, NZCV
, x2
);
2369 p
+= emit_msr (p
, FPSR
, x1
);
2370 p
+= emit_msr (p
, FPCR
, x0
);
2372 p
+= emit_add (p
, sp
, sp
, immediate_operand (5 * 16));
2374 /* Pop general purpose registers:
2378 LDR x30, [sp, #(30 * 16)]
2380 ADD sp, sp, #(31 * 16)
2383 for (i
= 0; i
<= 30; i
+= 1)
2384 p
+= emit_ldr (p
, aarch64_register (i
, 1), sp
,
2385 offset_memory_operand (i
* 16));
2386 p
+= emit_add (p
, sp
, sp
, immediate_operand (31 * 16));
2388 /* Pop SIMD&FP registers:
2392 LDP q30, q31, [sp, #(30 * 16)]
2394 ADD sp, sp, #(32 * 16)
2397 for (i
= 0; i
<= 30; i
+= 2)
2398 p
+= emit_ldp_q_offset (p
, i
, i
+ 1, sp
, i
* 16);
2399 p
+= emit_add (p
, sp
, sp
, immediate_operand (32 * 16));
2401 /* Write the code into the inferior memory. */
2402 append_insns (&buildaddr
, p
- buf
, buf
);
2404 /* Now emit the relocated instruction. */
2405 *adjusted_insn_addr
= buildaddr
;
2406 target_read_uint32 (tpaddr
, &insn
);
2408 insn_data
.base
.insn_addr
= tpaddr
;
2409 insn_data
.new_addr
= buildaddr
;
2410 insn_data
.insn_ptr
= buf
;
2412 aarch64_relocate_instruction (insn
, &visitor
,
2413 (struct aarch64_insn_data
*) &insn_data
);
2415 /* We may not have been able to relocate the instruction. */
2416 if (insn_data
.insn_ptr
== buf
)
2419 "E.Could not relocate instruction from %s to %s.",
2420 core_addr_to_string_nz (tpaddr
),
2421 core_addr_to_string_nz (buildaddr
));
2425 append_insns (&buildaddr
, insn_data
.insn_ptr
- buf
, buf
);
2426 *adjusted_insn_addr_end
= buildaddr
;
2428 /* Go back to the start of the buffer. */
2431 /* Emit a branch back from the jump pad. */
2432 offset
= (tpaddr
+ orig_size
- buildaddr
);
2433 if (!can_encode_int32 (offset
, 28))
2436 "E.Jump back from jump pad too far from tracepoint "
2437 "(offset 0x%" PRIx64
" cannot be encoded in 28 bits).",
2442 p
+= emit_b (p
, 0, offset
);
2443 append_insns (&buildaddr
, p
- buf
, buf
);
2445 /* Give the caller a branch instruction into the jump pad. */
2446 offset
= (*jump_entry
- tpaddr
);
2447 if (!can_encode_int32 (offset
, 28))
2450 "E.Jump pad too far from tracepoint "
2451 "(offset 0x%" PRIx64
" cannot be encoded in 28 bits).",
2456 emit_b ((uint32_t *) jjump_pad_insn
, 0, offset
);
2457 *jjump_pad_insn_size
= 4;
2459 /* Return the end address of our pad. */
2460 *jump_entry
= buildaddr
;
2465 /* Helper function writing LEN instructions from START into
2466 current_insn_ptr. */
2469 emit_ops_insns (const uint32_t *start
, int len
)
2471 CORE_ADDR buildaddr
= current_insn_ptr
;
2473 threads_debug_printf ("Adding %d instrucions at %s",
2474 len
, paddress (buildaddr
));
2476 append_insns (&buildaddr
, len
, start
);
2477 current_insn_ptr
= buildaddr
;
2480 /* Pop a register from the stack. */
2483 emit_pop (uint32_t *buf
, struct aarch64_register rt
)
2485 return emit_ldr (buf
, rt
, sp
, postindex_memory_operand (1 * 16));
2488 /* Push a register on the stack. */
2491 emit_push (uint32_t *buf
, struct aarch64_register rt
)
2493 return emit_str (buf
, rt
, sp
, preindex_memory_operand (-1 * 16));
2496 /* Implementation of emit_ops method "emit_prologue". */
2499 aarch64_emit_prologue (void)
2504 /* This function emit a prologue for the following function prototype:
2506 enum eval_result_type f (unsigned char *regs,
2509 The first argument is a buffer of raw registers. The second
2510 argument is the result of
2511 evaluating the expression, which will be set to whatever is on top of
2512 the stack at the end.
2514 The stack set up by the prologue is as such:
2516 High *------------------------------------------------------*
2519 | x1 (ULONGEST *value) |
2520 | x0 (unsigned char *regs) |
2521 Low *------------------------------------------------------*
2523 As we are implementing a stack machine, each opcode can expand the
2524 stack so we never know how far we are from the data saved by this
2525 prologue. In order to be able refer to value and regs later, we save
2526 the current stack pointer in the frame pointer. This way, it is not
2527 clobbered when calling C functions.
2529 Finally, throughout every operation, we are using register x0 as the
2530 top of the stack, and x1 as a scratch register. */
2532 p
+= emit_stp (p
, x0
, x1
, sp
, preindex_memory_operand (-2 * 16));
2533 p
+= emit_str (p
, lr
, sp
, offset_memory_operand (3 * 8));
2534 p
+= emit_str (p
, fp
, sp
, offset_memory_operand (2 * 8));
2536 p
+= emit_add (p
, fp
, sp
, immediate_operand (2 * 8));
2539 emit_ops_insns (buf
, p
- buf
);
2542 /* Implementation of emit_ops method "emit_epilogue". */
2545 aarch64_emit_epilogue (void)
2550 /* Store the result of the expression (x0) in *value. */
2551 p
+= emit_sub (p
, x1
, fp
, immediate_operand (1 * 8));
2552 p
+= emit_ldr (p
, x1
, x1
, offset_memory_operand (0));
2553 p
+= emit_str (p
, x0
, x1
, offset_memory_operand (0));
2555 /* Restore the previous state. */
2556 p
+= emit_add (p
, sp
, fp
, immediate_operand (2 * 8));
2557 p
+= emit_ldp (p
, fp
, lr
, fp
, offset_memory_operand (0));
2559 /* Return expr_eval_no_error. */
2560 p
+= emit_mov (p
, x0
, immediate_operand (expr_eval_no_error
));
2561 p
+= emit_ret (p
, lr
);
2563 emit_ops_insns (buf
, p
- buf
);
2566 /* Implementation of emit_ops method "emit_add". */
2569 aarch64_emit_add (void)
2574 p
+= emit_pop (p
, x1
);
2575 p
+= emit_add (p
, x0
, x1
, register_operand (x0
));
2577 emit_ops_insns (buf
, p
- buf
);
2580 /* Implementation of emit_ops method "emit_sub". */
2583 aarch64_emit_sub (void)
2588 p
+= emit_pop (p
, x1
);
2589 p
+= emit_sub (p
, x0
, x1
, register_operand (x0
));
2591 emit_ops_insns (buf
, p
- buf
);
2594 /* Implementation of emit_ops method "emit_mul". */
2597 aarch64_emit_mul (void)
2602 p
+= emit_pop (p
, x1
);
2603 p
+= emit_mul (p
, x0
, x1
, x0
);
2605 emit_ops_insns (buf
, p
- buf
);
2608 /* Implementation of emit_ops method "emit_lsh". */
2611 aarch64_emit_lsh (void)
2616 p
+= emit_pop (p
, x1
);
2617 p
+= emit_lslv (p
, x0
, x1
, x0
);
2619 emit_ops_insns (buf
, p
- buf
);
2622 /* Implementation of emit_ops method "emit_rsh_signed". */
2625 aarch64_emit_rsh_signed (void)
2630 p
+= emit_pop (p
, x1
);
2631 p
+= emit_asrv (p
, x0
, x1
, x0
);
2633 emit_ops_insns (buf
, p
- buf
);
2636 /* Implementation of emit_ops method "emit_rsh_unsigned". */
2639 aarch64_emit_rsh_unsigned (void)
2644 p
+= emit_pop (p
, x1
);
2645 p
+= emit_lsrv (p
, x0
, x1
, x0
);
2647 emit_ops_insns (buf
, p
- buf
);
2650 /* Implementation of emit_ops method "emit_ext". */
2653 aarch64_emit_ext (int arg
)
2658 p
+= emit_sbfx (p
, x0
, x0
, 0, arg
);
2660 emit_ops_insns (buf
, p
- buf
);
2663 /* Implementation of emit_ops method "emit_log_not". */
2666 aarch64_emit_log_not (void)
2671 /* If the top of the stack is 0, replace it with 1. Else replace it with
2674 p
+= emit_cmp (p
, x0
, immediate_operand (0));
2675 p
+= emit_cset (p
, x0
, EQ
);
2677 emit_ops_insns (buf
, p
- buf
);
2680 /* Implementation of emit_ops method "emit_bit_and". */
2683 aarch64_emit_bit_and (void)
2688 p
+= emit_pop (p
, x1
);
2689 p
+= emit_and (p
, x0
, x0
, x1
);
2691 emit_ops_insns (buf
, p
- buf
);
2694 /* Implementation of emit_ops method "emit_bit_or". */
2697 aarch64_emit_bit_or (void)
2702 p
+= emit_pop (p
, x1
);
2703 p
+= emit_orr (p
, x0
, x0
, x1
);
2705 emit_ops_insns (buf
, p
- buf
);
2708 /* Implementation of emit_ops method "emit_bit_xor". */
2711 aarch64_emit_bit_xor (void)
2716 p
+= emit_pop (p
, x1
);
2717 p
+= emit_eor (p
, x0
, x0
, x1
);
2719 emit_ops_insns (buf
, p
- buf
);
2722 /* Implementation of emit_ops method "emit_bit_not". */
2725 aarch64_emit_bit_not (void)
2730 p
+= emit_mvn (p
, x0
, x0
);
2732 emit_ops_insns (buf
, p
- buf
);
2735 /* Implementation of emit_ops method "emit_equal". */
2738 aarch64_emit_equal (void)
2743 p
+= emit_pop (p
, x1
);
2744 p
+= emit_cmp (p
, x0
, register_operand (x1
));
2745 p
+= emit_cset (p
, x0
, EQ
);
2747 emit_ops_insns (buf
, p
- buf
);
2750 /* Implementation of emit_ops method "emit_less_signed". */
2753 aarch64_emit_less_signed (void)
2758 p
+= emit_pop (p
, x1
);
2759 p
+= emit_cmp (p
, x1
, register_operand (x0
));
2760 p
+= emit_cset (p
, x0
, LT
);
2762 emit_ops_insns (buf
, p
- buf
);
2765 /* Implementation of emit_ops method "emit_less_unsigned". */
2768 aarch64_emit_less_unsigned (void)
2773 p
+= emit_pop (p
, x1
);
2774 p
+= emit_cmp (p
, x1
, register_operand (x0
));
2775 p
+= emit_cset (p
, x0
, LO
);
2777 emit_ops_insns (buf
, p
- buf
);
2780 /* Implementation of emit_ops method "emit_ref". */
2783 aarch64_emit_ref (int size
)
2791 p
+= emit_ldrb (p
, w0
, x0
, offset_memory_operand (0));
2794 p
+= emit_ldrh (p
, w0
, x0
, offset_memory_operand (0));
2797 p
+= emit_ldr (p
, w0
, x0
, offset_memory_operand (0));
2800 p
+= emit_ldr (p
, x0
, x0
, offset_memory_operand (0));
2803 /* Unknown size, bail on compilation. */
2808 emit_ops_insns (buf
, p
- buf
);
2811 /* Implementation of emit_ops method "emit_if_goto". */
2814 aarch64_emit_if_goto (int *offset_p
, int *size_p
)
2819 /* The Z flag is set or cleared here. */
2820 p
+= emit_cmp (p
, x0
, immediate_operand (0));
2821 /* This instruction must not change the Z flag. */
2822 p
+= emit_pop (p
, x0
);
2823 /* Branch over the next instruction if x0 == 0. */
2824 p
+= emit_bcond (p
, EQ
, 8);
2826 /* The NOP instruction will be patched with an unconditional branch. */
2828 *offset_p
= (p
- buf
) * 4;
2833 emit_ops_insns (buf
, p
- buf
);
2836 /* Implementation of emit_ops method "emit_goto". */
2839 aarch64_emit_goto (int *offset_p
, int *size_p
)
2844 /* The NOP instruction will be patched with an unconditional branch. */
2851 emit_ops_insns (buf
, p
- buf
);
2854 /* Implementation of emit_ops method "write_goto_address". */
2857 aarch64_write_goto_address (CORE_ADDR from
, CORE_ADDR to
, int size
)
2861 emit_b (&insn
, 0, to
- from
);
2862 append_insns (&from
, 1, &insn
);
2865 /* Implementation of emit_ops method "emit_const". */
2868 aarch64_emit_const (LONGEST num
)
2873 p
+= emit_mov_addr (p
, x0
, num
);
2875 emit_ops_insns (buf
, p
- buf
);
2878 /* Implementation of emit_ops method "emit_call". */
2881 aarch64_emit_call (CORE_ADDR fn
)
2886 p
+= emit_mov_addr (p
, ip0
, fn
);
2887 p
+= emit_blr (p
, ip0
);
2889 emit_ops_insns (buf
, p
- buf
);
2892 /* Implementation of emit_ops method "emit_reg". */
2895 aarch64_emit_reg (int reg
)
2900 /* Set x0 to unsigned char *regs. */
2901 p
+= emit_sub (p
, x0
, fp
, immediate_operand (2 * 8));
2902 p
+= emit_ldr (p
, x0
, x0
, offset_memory_operand (0));
2903 p
+= emit_mov (p
, x1
, immediate_operand (reg
));
2905 emit_ops_insns (buf
, p
- buf
);
2907 aarch64_emit_call (get_raw_reg_func_addr ());
2910 /* Implementation of emit_ops method "emit_pop". */
2913 aarch64_emit_pop (void)
2918 p
+= emit_pop (p
, x0
);
2920 emit_ops_insns (buf
, p
- buf
);
2923 /* Implementation of emit_ops method "emit_stack_flush". */
2926 aarch64_emit_stack_flush (void)
2931 p
+= emit_push (p
, x0
);
2933 emit_ops_insns (buf
, p
- buf
);
2936 /* Implementation of emit_ops method "emit_zero_ext". */
2939 aarch64_emit_zero_ext (int arg
)
2944 p
+= emit_ubfx (p
, x0
, x0
, 0, arg
);
2946 emit_ops_insns (buf
, p
- buf
);
2949 /* Implementation of emit_ops method "emit_swap". */
2952 aarch64_emit_swap (void)
2957 p
+= emit_ldr (p
, x1
, sp
, offset_memory_operand (0 * 16));
2958 p
+= emit_str (p
, x0
, sp
, offset_memory_operand (0 * 16));
2959 p
+= emit_mov (p
, x0
, register_operand (x1
));
2961 emit_ops_insns (buf
, p
- buf
);
2964 /* Implementation of emit_ops method "emit_stack_adjust". */
2967 aarch64_emit_stack_adjust (int n
)
2969 /* This is not needed with our design. */
2973 p
+= emit_add (p
, sp
, sp
, immediate_operand (n
* 16));
2975 emit_ops_insns (buf
, p
- buf
);
2978 /* Implementation of emit_ops method "emit_int_call_1". */
2981 aarch64_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
2986 p
+= emit_mov (p
, x0
, immediate_operand (arg1
));
2988 emit_ops_insns (buf
, p
- buf
);
2990 aarch64_emit_call (fn
);
2993 /* Implementation of emit_ops method "emit_void_call_2". */
2996 aarch64_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
3001 /* Push x0 on the stack. */
3002 aarch64_emit_stack_flush ();
3004 /* Setup arguments for the function call:
3007 x1: top of the stack
3012 p
+= emit_mov (p
, x1
, register_operand (x0
));
3013 p
+= emit_mov (p
, x0
, immediate_operand (arg1
));
3015 emit_ops_insns (buf
, p
- buf
);
3017 aarch64_emit_call (fn
);
3020 aarch64_emit_pop ();
3023 /* Implementation of emit_ops method "emit_eq_goto". */
3026 aarch64_emit_eq_goto (int *offset_p
, int *size_p
)
3031 p
+= emit_pop (p
, x1
);
3032 p
+= emit_cmp (p
, x1
, register_operand (x0
));
3033 /* Branch over the next instruction if x0 != x1. */
3034 p
+= emit_bcond (p
, NE
, 8);
3035 /* The NOP instruction will be patched with an unconditional branch. */
3037 *offset_p
= (p
- buf
) * 4;
3042 emit_ops_insns (buf
, p
- buf
);
3045 /* Implementation of emit_ops method "emit_ne_goto". */
3048 aarch64_emit_ne_goto (int *offset_p
, int *size_p
)
3053 p
+= emit_pop (p
, x1
);
3054 p
+= emit_cmp (p
, x1
, register_operand (x0
));
3055 /* Branch over the next instruction if x0 == x1. */
3056 p
+= emit_bcond (p
, EQ
, 8);
3057 /* The NOP instruction will be patched with an unconditional branch. */
3059 *offset_p
= (p
- buf
) * 4;
3064 emit_ops_insns (buf
, p
- buf
);
3067 /* Implementation of emit_ops method "emit_lt_goto". */
3070 aarch64_emit_lt_goto (int *offset_p
, int *size_p
)
3075 p
+= emit_pop (p
, x1
);
3076 p
+= emit_cmp (p
, x1
, register_operand (x0
));
3077 /* Branch over the next instruction if x0 >= x1. */
3078 p
+= emit_bcond (p
, GE
, 8);
3079 /* The NOP instruction will be patched with an unconditional branch. */
3081 *offset_p
= (p
- buf
) * 4;
3086 emit_ops_insns (buf
, p
- buf
);
3089 /* Implementation of emit_ops method "emit_le_goto". */
3092 aarch64_emit_le_goto (int *offset_p
, int *size_p
)
3097 p
+= emit_pop (p
, x1
);
3098 p
+= emit_cmp (p
, x1
, register_operand (x0
));
3099 /* Branch over the next instruction if x0 > x1. */
3100 p
+= emit_bcond (p
, GT
, 8);
3101 /* The NOP instruction will be patched with an unconditional branch. */
3103 *offset_p
= (p
- buf
) * 4;
3108 emit_ops_insns (buf
, p
- buf
);
3111 /* Implementation of emit_ops method "emit_gt_goto". */
3114 aarch64_emit_gt_goto (int *offset_p
, int *size_p
)
3119 p
+= emit_pop (p
, x1
);
3120 p
+= emit_cmp (p
, x1
, register_operand (x0
));
3121 /* Branch over the next instruction if x0 <= x1. */
3122 p
+= emit_bcond (p
, LE
, 8);
3123 /* The NOP instruction will be patched with an unconditional branch. */
3125 *offset_p
= (p
- buf
) * 4;
3130 emit_ops_insns (buf
, p
- buf
);
3133 /* Implementation of emit_ops method "emit_ge_got". */
3136 aarch64_emit_ge_got (int *offset_p
, int *size_p
)
3141 p
+= emit_pop (p
, x1
);
3142 p
+= emit_cmp (p
, x1
, register_operand (x0
));
3143 /* Branch over the next instruction if x0 <= x1. */
3144 p
+= emit_bcond (p
, LT
, 8);
3145 /* The NOP instruction will be patched with an unconditional branch. */
3147 *offset_p
= (p
- buf
) * 4;
3152 emit_ops_insns (buf
, p
- buf
);
3155 static struct emit_ops aarch64_emit_ops_impl
=
3157 aarch64_emit_prologue
,
3158 aarch64_emit_epilogue
,
3163 aarch64_emit_rsh_signed
,
3164 aarch64_emit_rsh_unsigned
,
3166 aarch64_emit_log_not
,
3167 aarch64_emit_bit_and
,
3168 aarch64_emit_bit_or
,
3169 aarch64_emit_bit_xor
,
3170 aarch64_emit_bit_not
,
3172 aarch64_emit_less_signed
,
3173 aarch64_emit_less_unsigned
,
3175 aarch64_emit_if_goto
,
3177 aarch64_write_goto_address
,
3182 aarch64_emit_stack_flush
,
3183 aarch64_emit_zero_ext
,
3185 aarch64_emit_stack_adjust
,
3186 aarch64_emit_int_call_1
,
3187 aarch64_emit_void_call_2
,
3188 aarch64_emit_eq_goto
,
3189 aarch64_emit_ne_goto
,
3190 aarch64_emit_lt_goto
,
3191 aarch64_emit_le_goto
,
3192 aarch64_emit_gt_goto
,
3193 aarch64_emit_ge_got
,
3196 /* Implementation of target ops method "emit_ops". */
3199 aarch64_target::emit_ops ()
3201 return &aarch64_emit_ops_impl
;
3204 /* Implementation of target ops method
3205 "get_min_fast_tracepoint_insn_len". */
3208 aarch64_target::get_min_fast_tracepoint_insn_len ()
3213 /* Implementation of linux target ops method "low_supports_range_stepping". */
3216 aarch64_target::low_supports_range_stepping ()
3221 /* Implementation of target ops method "sw_breakpoint_from_kind". */
3224 aarch64_target::sw_breakpoint_from_kind (int kind
, int *size
)
3226 if (is_64bit_tdesc ())
3228 *size
= aarch64_breakpoint_len
;
3229 return aarch64_breakpoint
;
3232 return arm_sw_breakpoint_from_kind (kind
, size
);
3235 /* Implementation of target ops method "breakpoint_kind_from_pc". */
3238 aarch64_target::breakpoint_kind_from_pc (CORE_ADDR
*pcptr
)
3240 if (is_64bit_tdesc ())
3241 return aarch64_breakpoint_len
;
3243 return arm_breakpoint_kind_from_pc (pcptr
);
3246 /* Implementation of the target ops method
3247 "breakpoint_kind_from_current_state". */
3250 aarch64_target::breakpoint_kind_from_current_state (CORE_ADDR
*pcptr
)
3252 if (is_64bit_tdesc ())
3253 return aarch64_breakpoint_len
;
3255 return arm_breakpoint_kind_from_current_state (pcptr
);
3258 /* Returns true if memory tagging is supported. */
3260 aarch64_target::supports_memory_tagging ()
3262 if (current_thread
== NULL
)
3264 /* We don't have any processes running, so don't attempt to
3265 use linux_get_hwcap2 as it will try to fetch the current
3266 thread id. Instead, just fetch the auxv from the self
3268 #ifdef HAVE_GETAUXVAL
3269 return (getauxval (AT_HWCAP2
) & HWCAP2_MTE
) != 0;
3275 return (linux_get_hwcap2 (8) & HWCAP2_MTE
) != 0;
3279 aarch64_target::fetch_memtags (CORE_ADDR address
, size_t len
,
3280 gdb::byte_vector
&tags
, int type
)
3282 /* Allocation tags are per-process, so any tid is fine. */
3283 int tid
= lwpid_of (current_thread
);
3285 /* Allocation tag? */
3286 if (type
== static_cast <int> (aarch64_memtag_type::mte_allocation
))
3287 return aarch64_mte_fetch_memtags (tid
, address
, len
, tags
);
3293 aarch64_target::store_memtags (CORE_ADDR address
, size_t len
,
3294 const gdb::byte_vector
&tags
, int type
)
3296 /* Allocation tags are per-process, so any tid is fine. */
3297 int tid
= lwpid_of (current_thread
);
3299 /* Allocation tag? */
3300 if (type
== static_cast <int> (aarch64_memtag_type::mte_allocation
))
3301 return aarch64_mte_store_memtags (tid
, address
, len
, tags
);
3306 /* The linux target ops object. */
3308 linux_process_target
*the_linux_target
= &the_aarch64_target
;
3311 initialize_low_arch (void)
3313 initialize_low_arch_aarch32 ();
3315 initialize_regsets_info (&aarch64_regsets_info
);