1 /* GNU/Linux/x86-64 specific low level interface, for the remote server
3 Copyright (C) 2002-2021 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 #include "linux-low.h"
27 #include "gdbsupport/x86-xstate.h"
28 #include "nat/gdb_ptrace.h"
31 #include "nat/amd64-linux-siginfo.h"
34 #include "gdb_proc_service.h"
35 /* Don't include elf/common.h if linux/elf.h got included by
36 gdb_proc_service.h. */
38 #include "elf/common.h"
41 #include "gdbsupport/agent.h"
43 #include "tracepoint.h"
45 #include "nat/linux-nat.h"
46 #include "nat/x86-linux.h"
47 #include "nat/x86-linux-dregs.h"
48 #include "linux-x86-tdesc.h"
51 static target_desc_up tdesc_amd64_linux_no_xml
;
53 static target_desc_up tdesc_i386_linux_no_xml
;
56 static unsigned char jump_insn
[] = { 0xe9, 0, 0, 0, 0 };
57 static unsigned char small_jump_insn
[] = { 0x66, 0xe9, 0, 0 };
59 /* Backward compatibility for gdb without XML support. */
61 static const char xmltarget_i386_linux_no_xml
[] = "@<target>\
62 <architecture>i386</architecture>\
63 <osabi>GNU/Linux</osabi>\
67 static const char xmltarget_amd64_linux_no_xml
[] = "@<target>\
68 <architecture>i386:x86-64</architecture>\
69 <osabi>GNU/Linux</osabi>\
74 #include <sys/procfs.h>
77 #ifndef PTRACE_GET_THREAD_AREA
78 #define PTRACE_GET_THREAD_AREA 25
81 /* This definition comes from prctl.h, but some kernels may not have it. */
82 #ifndef PTRACE_ARCH_PRCTL
83 #define PTRACE_ARCH_PRCTL 30
86 /* The following definitions come from prctl.h, but may be absent
87 for certain configurations. */
89 #define ARCH_SET_GS 0x1001
90 #define ARCH_SET_FS 0x1002
91 #define ARCH_GET_FS 0x1003
92 #define ARCH_GET_GS 0x1004
95 /* Linux target op definitions for the x86 architecture.
96 This is initialized assuming an amd64 target.
97 'low_arch_setup' will correct it for i386 or amd64 targets. */
99 class x86_target
: public linux_process_target
103 const regs_info
*get_regs_info () override
;
105 const gdb_byte
*sw_breakpoint_from_kind (int kind
, int *size
) override
;
107 bool supports_z_point_type (char z_type
) override
;
109 void process_qsupported (gdb::array_view
<const char * const> features
) override
;
111 bool supports_tracepoints () override
;
113 bool supports_fast_tracepoints () override
;
115 int install_fast_tracepoint_jump_pad
116 (CORE_ADDR tpoint
, CORE_ADDR tpaddr
, CORE_ADDR collector
,
117 CORE_ADDR lockaddr
, ULONGEST orig_size
, CORE_ADDR
*jump_entry
,
118 CORE_ADDR
*trampoline
, ULONGEST
*trampoline_size
,
119 unsigned char *jjump_pad_insn
, ULONGEST
*jjump_pad_insn_size
,
120 CORE_ADDR
*adjusted_insn_addr
, CORE_ADDR
*adjusted_insn_addr_end
,
123 int get_min_fast_tracepoint_insn_len () override
;
125 struct emit_ops
*emit_ops () override
;
127 int get_ipa_tdesc_idx () override
;
131 void low_arch_setup () override
;
133 bool low_cannot_fetch_register (int regno
) override
;
135 bool low_cannot_store_register (int regno
) override
;
137 bool low_supports_breakpoints () override
;
139 CORE_ADDR
low_get_pc (regcache
*regcache
) override
;
141 void low_set_pc (regcache
*regcache
, CORE_ADDR newpc
) override
;
143 int low_decr_pc_after_break () override
;
145 bool low_breakpoint_at (CORE_ADDR pc
) override
;
147 int low_insert_point (raw_bkpt_type type
, CORE_ADDR addr
,
148 int size
, raw_breakpoint
*bp
) override
;
150 int low_remove_point (raw_bkpt_type type
, CORE_ADDR addr
,
151 int size
, raw_breakpoint
*bp
) override
;
153 bool low_stopped_by_watchpoint () override
;
155 CORE_ADDR
low_stopped_data_address () override
;
157 /* collect_ptrace_register/supply_ptrace_register are not needed in the
158 native i386 case (no registers smaller than an xfer unit), and are not
159 used in the biarch case (HAVE_LINUX_USRREGS is not defined). */
161 /* Need to fix up i386 siginfo if host is amd64. */
162 bool low_siginfo_fixup (siginfo_t
*native
, gdb_byte
*inf
,
163 int direction
) override
;
165 arch_process_info
*low_new_process () override
;
167 void low_delete_process (arch_process_info
*info
) override
;
169 void low_new_thread (lwp_info
*) override
;
171 void low_delete_thread (arch_lwp_info
*) override
;
173 void low_new_fork (process_info
*parent
, process_info
*child
) override
;
175 void low_prepare_to_resume (lwp_info
*lwp
) override
;
177 int low_get_thread_area (int lwpid
, CORE_ADDR
*addrp
) override
;
179 bool low_supports_range_stepping () override
;
181 bool low_supports_catch_syscall () override
;
183 void low_get_syscall_trapinfo (regcache
*regcache
, int *sysno
) override
;
187 /* Update all the target description of all processes; a new GDB
188 connected, and it may or not support xml target descriptions. */
189 void update_xmltarget ();
192 /* The singleton target ops object. */
194 static x86_target the_x86_target
;
196 /* Per-process arch-specific data we want to keep. */
198 struct arch_process_info
200 struct x86_debug_reg_state debug_reg_state
;
205 /* Mapping between the general-purpose registers in `struct user'
206 format and GDB's register array layout.
207 Note that the transfer layout uses 64-bit regs. */
208 static /*const*/ int i386_regmap
[] =
210 RAX
* 8, RCX
* 8, RDX
* 8, RBX
* 8,
211 RSP
* 8, RBP
* 8, RSI
* 8, RDI
* 8,
212 RIP
* 8, EFLAGS
* 8, CS
* 8, SS
* 8,
213 DS
* 8, ES
* 8, FS
* 8, GS
* 8
216 #define I386_NUM_REGS (sizeof (i386_regmap) / sizeof (i386_regmap[0]))
218 /* So code below doesn't have to care, i386 or amd64. */
219 #define ORIG_EAX ORIG_RAX
222 static const int x86_64_regmap
[] =
224 RAX
* 8, RBX
* 8, RCX
* 8, RDX
* 8,
225 RSI
* 8, RDI
* 8, RBP
* 8, RSP
* 8,
226 R8
* 8, R9
* 8, R10
* 8, R11
* 8,
227 R12
* 8, R13
* 8, R14
* 8, R15
* 8,
228 RIP
* 8, EFLAGS
* 8, CS
* 8, SS
* 8,
229 DS
* 8, ES
* 8, FS
* 8, GS
* 8,
230 -1, -1, -1, -1, -1, -1, -1, -1,
231 -1, -1, -1, -1, -1, -1, -1, -1,
232 -1, -1, -1, -1, -1, -1, -1, -1,
234 -1, -1, -1, -1, -1, -1, -1, -1,
237 -1, -1, -1, -1, /* MPX registers BND0 ... BND3. */
238 -1, -1, /* MPX registers BNDCFGU, BNDSTATUS. */
239 -1, -1, -1, -1, -1, -1, -1, -1, /* xmm16 ... xmm31 (AVX512) */
240 -1, -1, -1, -1, -1, -1, -1, -1,
241 -1, -1, -1, -1, -1, -1, -1, -1, /* ymm16 ... ymm31 (AVX512) */
242 -1, -1, -1, -1, -1, -1, -1, -1,
243 -1, -1, -1, -1, -1, -1, -1, -1, /* k0 ... k7 (AVX512) */
244 -1, -1, -1, -1, -1, -1, -1, -1, /* zmm0 ... zmm31 (AVX512) */
245 -1, -1, -1, -1, -1, -1, -1, -1,
246 -1, -1, -1, -1, -1, -1, -1, -1,
247 -1, -1, -1, -1, -1, -1, -1, -1,
251 #define X86_64_NUM_REGS (sizeof (x86_64_regmap) / sizeof (x86_64_regmap[0]))
252 #define X86_64_USER_REGS (GS + 1)
254 #else /* ! __x86_64__ */
256 /* Mapping between the general-purpose registers in `struct user'
257 format and GDB's register array layout. */
258 static /*const*/ int i386_regmap
[] =
260 EAX
* 4, ECX
* 4, EDX
* 4, EBX
* 4,
261 UESP
* 4, EBP
* 4, ESI
* 4, EDI
* 4,
262 EIP
* 4, EFL
* 4, CS
* 4, SS
* 4,
263 DS
* 4, ES
* 4, FS
* 4, GS
* 4
266 #define I386_NUM_REGS (sizeof (i386_regmap) / sizeof (i386_regmap[0]))
274 /* Returns true if the current inferior belongs to a x86-64 process,
278 is_64bit_tdesc (void)
280 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
282 return register_size (regcache
->tdesc
, 0) == 8;
288 /* Called by libthread_db. */
291 ps_get_thread_area (struct ps_prochandle
*ph
,
292 lwpid_t lwpid
, int idx
, void **base
)
295 int use_64bit
= is_64bit_tdesc ();
302 if (ptrace (PTRACE_ARCH_PRCTL
, lwpid
, base
, ARCH_GET_FS
) == 0)
306 if (ptrace (PTRACE_ARCH_PRCTL
, lwpid
, base
, ARCH_GET_GS
) == 0)
317 unsigned int desc
[4];
319 if (ptrace (PTRACE_GET_THREAD_AREA
, lwpid
,
320 (void *) (intptr_t) idx
, (unsigned long) &desc
) < 0)
323 /* Ensure we properly extend the value to 64-bits for x86_64. */
324 *base
= (void *) (uintptr_t) desc
[1];
329 /* Get the thread area address. This is used to recognize which
330 thread is which when tracing with the in-process agent library. We
331 don't read anything from the address, and treat it as opaque; it's
332 the address itself that we assume is unique per-thread. */
335 x86_target::low_get_thread_area (int lwpid
, CORE_ADDR
*addr
)
338 int use_64bit
= is_64bit_tdesc ();
343 if (ptrace (PTRACE_ARCH_PRCTL
, lwpid
, &base
, ARCH_GET_FS
) == 0)
345 *addr
= (CORE_ADDR
) (uintptr_t) base
;
354 struct lwp_info
*lwp
= find_lwp_pid (ptid_t (lwpid
));
355 struct thread_info
*thr
= get_lwp_thread (lwp
);
356 struct regcache
*regcache
= get_thread_regcache (thr
, 1);
357 unsigned int desc
[4];
359 const int reg_thread_area
= 3; /* bits to scale down register value. */
362 collect_register_by_name (regcache
, "gs", &gs
);
364 idx
= gs
>> reg_thread_area
;
366 if (ptrace (PTRACE_GET_THREAD_AREA
,
368 (void *) (long) idx
, (unsigned long) &desc
) < 0)
379 x86_target::low_cannot_store_register (int regno
)
382 if (is_64bit_tdesc ())
386 return regno
>= I386_NUM_REGS
;
390 x86_target::low_cannot_fetch_register (int regno
)
393 if (is_64bit_tdesc ())
397 return regno
>= I386_NUM_REGS
;
401 collect_register_i386 (struct regcache
*regcache
, int regno
, void *buf
)
403 collect_register (regcache
, regno
, buf
);
406 /* In case of x86_64 -m32, collect_register only writes 4 bytes, but the
407 space reserved in buf for the register is 8 bytes. Make sure the entire
408 reserved space is initialized. */
410 gdb_assert (register_size (regcache
->tdesc
, regno
) == 4);
414 /* Sign extend EAX value to avoid potential syscall restart
417 See amd64_linux_collect_native_gregset() in
418 gdb/amd64-linux-nat.c for a detailed explanation. */
419 *(int64_t *) buf
= *(int32_t *) buf
;
424 *(uint64_t *) buf
= *(uint32_t *) buf
;
430 x86_fill_gregset (struct regcache
*regcache
, void *buf
)
435 if (register_size (regcache
->tdesc
, 0) == 8)
437 for (i
= 0; i
< X86_64_NUM_REGS
; i
++)
438 if (x86_64_regmap
[i
] != -1)
439 collect_register (regcache
, i
, ((char *) buf
) + x86_64_regmap
[i
]);
445 for (i
= 0; i
< I386_NUM_REGS
; i
++)
446 collect_register_i386 (regcache
, i
, ((char *) buf
) + i386_regmap
[i
]);
448 /* Handle ORIG_EAX, which is not in i386_regmap. */
449 collect_register_i386 (regcache
, find_regno (regcache
->tdesc
, "orig_eax"),
450 ((char *) buf
) + ORIG_EAX
* REGSIZE
);
454 x86_store_gregset (struct regcache
*regcache
, const void *buf
)
459 if (register_size (regcache
->tdesc
, 0) == 8)
461 for (i
= 0; i
< X86_64_NUM_REGS
; i
++)
462 if (x86_64_regmap
[i
] != -1)
463 supply_register (regcache
, i
, ((char *) buf
) + x86_64_regmap
[i
]);
469 for (i
= 0; i
< I386_NUM_REGS
; i
++)
470 supply_register (regcache
, i
, ((char *) buf
) + i386_regmap
[i
]);
472 supply_register_by_name (regcache
, "orig_eax",
473 ((char *) buf
) + ORIG_EAX
* REGSIZE
);
477 x86_fill_fpregset (struct regcache
*regcache
, void *buf
)
480 i387_cache_to_fxsave (regcache
, buf
);
482 i387_cache_to_fsave (regcache
, buf
);
487 x86_store_fpregset (struct regcache
*regcache
, const void *buf
)
490 i387_fxsave_to_cache (regcache
, buf
);
492 i387_fsave_to_cache (regcache
, buf
);
499 x86_fill_fpxregset (struct regcache
*regcache
, void *buf
)
501 i387_cache_to_fxsave (regcache
, buf
);
505 x86_store_fpxregset (struct regcache
*regcache
, const void *buf
)
507 i387_fxsave_to_cache (regcache
, buf
);
513 x86_fill_xstateregset (struct regcache
*regcache
, void *buf
)
515 i387_cache_to_xsave (regcache
, buf
);
519 x86_store_xstateregset (struct regcache
*regcache
, const void *buf
)
521 i387_xsave_to_cache (regcache
, buf
);
524 /* ??? The non-biarch i386 case stores all the i387 regs twice.
525 Once in i387_.*fsave.* and once in i387_.*fxsave.*.
526 This is, presumably, to handle the case where PTRACE_[GS]ETFPXREGS
527 doesn't work. IWBN to avoid the duplication in the case where it
528 does work. Maybe the arch_setup routine could check whether it works
529 and update the supported regsets accordingly. */
531 static struct regset_info x86_regsets
[] =
533 #ifdef HAVE_PTRACE_GETREGS
534 { PTRACE_GETREGS
, PTRACE_SETREGS
, 0, sizeof (elf_gregset_t
),
536 x86_fill_gregset
, x86_store_gregset
},
537 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_X86_XSTATE
, 0,
538 EXTENDED_REGS
, x86_fill_xstateregset
, x86_store_xstateregset
},
540 # ifdef HAVE_PTRACE_GETFPXREGS
541 { PTRACE_GETFPXREGS
, PTRACE_SETFPXREGS
, 0, sizeof (elf_fpxregset_t
),
543 x86_fill_fpxregset
, x86_store_fpxregset
},
546 { PTRACE_GETFPREGS
, PTRACE_SETFPREGS
, 0, sizeof (elf_fpregset_t
),
548 x86_fill_fpregset
, x86_store_fpregset
},
549 #endif /* HAVE_PTRACE_GETREGS */
554 x86_target::low_supports_breakpoints ()
560 x86_target::low_get_pc (regcache
*regcache
)
562 int use_64bit
= register_size (regcache
->tdesc
, 0) == 8;
568 collect_register_by_name (regcache
, "rip", &pc
);
569 return (CORE_ADDR
) pc
;
575 collect_register_by_name (regcache
, "eip", &pc
);
576 return (CORE_ADDR
) pc
;
581 x86_target::low_set_pc (regcache
*regcache
, CORE_ADDR pc
)
583 int use_64bit
= register_size (regcache
->tdesc
, 0) == 8;
589 supply_register_by_name (regcache
, "rip", &newpc
);
595 supply_register_by_name (regcache
, "eip", &newpc
);
600 x86_target::low_decr_pc_after_break ()
606 static const gdb_byte x86_breakpoint
[] = { 0xCC };
607 #define x86_breakpoint_len 1
610 x86_target::low_breakpoint_at (CORE_ADDR pc
)
614 read_memory (pc
, &c
, 1);
621 /* Low-level function vector. */
622 struct x86_dr_low_type x86_dr_low
=
624 x86_linux_dr_set_control
,
625 x86_linux_dr_set_addr
,
626 x86_linux_dr_get_addr
,
627 x86_linux_dr_get_status
,
628 x86_linux_dr_get_control
,
632 /* Breakpoint/Watchpoint support. */
635 x86_target::supports_z_point_type (char z_type
)
641 case Z_PACKET_WRITE_WP
:
642 case Z_PACKET_ACCESS_WP
:
650 x86_target::low_insert_point (raw_bkpt_type type
, CORE_ADDR addr
,
651 int size
, raw_breakpoint
*bp
)
653 struct process_info
*proc
= current_process ();
657 case raw_bkpt_type_hw
:
658 case raw_bkpt_type_write_wp
:
659 case raw_bkpt_type_access_wp
:
661 enum target_hw_bp_type hw_type
662 = raw_bkpt_type_to_target_hw_bp_type (type
);
663 struct x86_debug_reg_state
*state
664 = &proc
->priv
->arch_private
->debug_reg_state
;
666 return x86_dr_insert_watchpoint (state
, hw_type
, addr
, size
);
676 x86_target::low_remove_point (raw_bkpt_type type
, CORE_ADDR addr
,
677 int size
, raw_breakpoint
*bp
)
679 struct process_info
*proc
= current_process ();
683 case raw_bkpt_type_hw
:
684 case raw_bkpt_type_write_wp
:
685 case raw_bkpt_type_access_wp
:
687 enum target_hw_bp_type hw_type
688 = raw_bkpt_type_to_target_hw_bp_type (type
);
689 struct x86_debug_reg_state
*state
690 = &proc
->priv
->arch_private
->debug_reg_state
;
692 return x86_dr_remove_watchpoint (state
, hw_type
, addr
, size
);
701 x86_target::low_stopped_by_watchpoint ()
703 struct process_info
*proc
= current_process ();
704 return x86_dr_stopped_by_watchpoint (&proc
->priv
->arch_private
->debug_reg_state
);
708 x86_target::low_stopped_data_address ()
710 struct process_info
*proc
= current_process ();
712 if (x86_dr_stopped_data_address (&proc
->priv
->arch_private
->debug_reg_state
,
718 /* Called when a new process is created. */
721 x86_target::low_new_process ()
723 struct arch_process_info
*info
= XCNEW (struct arch_process_info
);
725 x86_low_init_dregs (&info
->debug_reg_state
);
730 /* Called when a process is being deleted. */
733 x86_target::low_delete_process (arch_process_info
*info
)
739 x86_target::low_new_thread (lwp_info
*lwp
)
741 /* This comes from nat/. */
742 x86_linux_new_thread (lwp
);
746 x86_target::low_delete_thread (arch_lwp_info
*alwp
)
748 /* This comes from nat/. */
749 x86_linux_delete_thread (alwp
);
752 /* Target routine for new_fork. */
755 x86_target::low_new_fork (process_info
*parent
, process_info
*child
)
757 /* These are allocated by linux_add_process. */
758 gdb_assert (parent
->priv
!= NULL
759 && parent
->priv
->arch_private
!= NULL
);
760 gdb_assert (child
->priv
!= NULL
761 && child
->priv
->arch_private
!= NULL
);
763 /* Linux kernel before 2.6.33 commit
764 72f674d203cd230426437cdcf7dd6f681dad8b0d
765 will inherit hardware debug registers from parent
766 on fork/vfork/clone. Newer Linux kernels create such tasks with
767 zeroed debug registers.
769 GDB core assumes the child inherits the watchpoints/hw
770 breakpoints of the parent, and will remove them all from the
771 forked off process. Copy the debug registers mirrors into the
772 new process so that all breakpoints and watchpoints can be
773 removed together. The debug registers mirror will become zeroed
774 in the end before detaching the forked off process, thus making
775 this compatible with older Linux kernels too. */
777 *child
->priv
->arch_private
= *parent
->priv
->arch_private
;
781 x86_target::low_prepare_to_resume (lwp_info
*lwp
)
783 /* This comes from nat/. */
784 x86_linux_prepare_to_resume (lwp
);
787 /* See nat/x86-dregs.h. */
789 struct x86_debug_reg_state
*
790 x86_debug_reg_state (pid_t pid
)
792 struct process_info
*proc
= find_process_pid (pid
);
794 return &proc
->priv
->arch_private
->debug_reg_state
;
797 /* When GDBSERVER is built as a 64-bit application on linux, the
798 PTRACE_GETSIGINFO data is always presented in 64-bit layout. Since
799 debugging a 32-bit inferior with a 64-bit GDBSERVER should look the same
800 as debugging it with a 32-bit GDBSERVER, we do the 32-bit <-> 64-bit
801 conversion in-place ourselves. */
803 /* Convert a ptrace/host siginfo object, into/from the siginfo in the
804 layout of the inferiors' architecture. Returns true if any
805 conversion was done; false otherwise. If DIRECTION is 1, then copy
806 from INF to PTRACE. If DIRECTION is 0, copy from PTRACE to
810 x86_target::low_siginfo_fixup (siginfo_t
*ptrace
, gdb_byte
*inf
, int direction
)
813 unsigned int machine
;
814 int tid
= lwpid_of (current_thread
);
815 int is_elf64
= linux_pid_exe_is_elf_64_file (tid
, &machine
);
817 /* Is the inferior 32-bit? If so, then fixup the siginfo object. */
818 if (!is_64bit_tdesc ())
819 return amd64_linux_siginfo_fixup_common (ptrace
, inf
, direction
,
821 /* No fixup for native x32 GDB. */
822 else if (!is_elf64
&& sizeof (void *) == 8)
823 return amd64_linux_siginfo_fixup_common (ptrace
, inf
, direction
,
832 /* Format of XSAVE extended state is:
836 sw_usable_bytes[464..511]
837 xstate_hdr_bytes[512..575]
842 Same memory layout will be used for the coredump NT_X86_XSTATE
843 representing the XSAVE extended state registers.
845 The first 8 bytes of the sw_usable_bytes[464..467] is the OS enabled
846 extended state mask, which is the same as the extended control register
847 0 (the XFEATURE_ENABLED_MASK register), XCR0. We can use this mask
848 together with the mask saved in the xstate_hdr_bytes to determine what
849 states the processor/OS supports and what state, used or initialized,
850 the process/thread is in. */
851 #define I386_LINUX_XSAVE_XCR0_OFFSET 464
853 /* Does the current host support the GETFPXREGS request? The header
854 file may or may not define it, and even if it is defined, the
855 kernel will return EIO if it's running on a pre-SSE processor. */
856 int have_ptrace_getfpxregs
=
857 #ifdef HAVE_PTRACE_GETFPXREGS
864 /* Get Linux/x86 target description from running target. */
866 static const struct target_desc
*
867 x86_linux_read_description (void)
869 unsigned int machine
;
873 static uint64_t xcr0
;
874 struct regset_info
*regset
;
876 tid
= lwpid_of (current_thread
);
878 is_elf64
= linux_pid_exe_is_elf_64_file (tid
, &machine
);
880 if (sizeof (void *) == 4)
883 error (_("Can't debug 64-bit process with 32-bit GDBserver"));
885 else if (machine
== EM_X86_64
)
886 error (_("Can't debug x86-64 process with 32-bit GDBserver"));
890 #if !defined __x86_64__ && defined HAVE_PTRACE_GETFPXREGS
891 if (machine
== EM_386
&& have_ptrace_getfpxregs
== -1)
893 elf_fpxregset_t fpxregs
;
895 if (ptrace (PTRACE_GETFPXREGS
, tid
, 0, (long) &fpxregs
) < 0)
897 have_ptrace_getfpxregs
= 0;
898 have_ptrace_getregset
= 0;
899 return i386_linux_read_description (X86_XSTATE_X87
);
902 have_ptrace_getfpxregs
= 1;
908 x86_xcr0
= X86_XSTATE_SSE_MASK
;
912 if (machine
== EM_X86_64
)
913 return tdesc_amd64_linux_no_xml
.get ();
916 return tdesc_i386_linux_no_xml
.get ();
919 if (have_ptrace_getregset
== -1)
921 uint64_t xstateregs
[(X86_XSTATE_SSE_SIZE
/ sizeof (uint64_t))];
924 iov
.iov_base
= xstateregs
;
925 iov
.iov_len
= sizeof (xstateregs
);
927 /* Check if PTRACE_GETREGSET works. */
928 if (ptrace (PTRACE_GETREGSET
, tid
,
929 (unsigned int) NT_X86_XSTATE
, (long) &iov
) < 0)
930 have_ptrace_getregset
= 0;
933 have_ptrace_getregset
= 1;
935 /* Get XCR0 from XSAVE extended state. */
936 xcr0
= xstateregs
[(I386_LINUX_XSAVE_XCR0_OFFSET
937 / sizeof (uint64_t))];
939 /* Use PTRACE_GETREGSET if it is available. */
940 for (regset
= x86_regsets
;
941 regset
->fill_function
!= NULL
; regset
++)
942 if (regset
->get_request
== PTRACE_GETREGSET
)
943 regset
->size
= X86_XSTATE_SIZE (xcr0
);
944 else if (regset
->type
!= GENERAL_REGS
)
949 /* Check the native XCR0 only if PTRACE_GETREGSET is available. */
950 xcr0_features
= (have_ptrace_getregset
951 && (xcr0
& X86_XSTATE_ALL_MASK
));
956 if (machine
== EM_X86_64
)
959 const target_desc
*tdesc
= NULL
;
963 tdesc
= amd64_linux_read_description (xcr0
& X86_XSTATE_ALL_MASK
,
968 tdesc
= amd64_linux_read_description (X86_XSTATE_SSE_MASK
, !is_elf64
);
974 const target_desc
*tdesc
= NULL
;
977 tdesc
= i386_linux_read_description (xcr0
& X86_XSTATE_ALL_MASK
);
980 tdesc
= i386_linux_read_description (X86_XSTATE_SSE
);
985 gdb_assert_not_reached ("failed to return tdesc");
988 /* Update all the target description of all processes; a new GDB
989 connected, and it may or not support xml target descriptions. */
992 x86_target::update_xmltarget ()
994 struct thread_info
*saved_thread
= current_thread
;
996 /* Before changing the register cache's internal layout, flush the
997 contents of the current valid caches back to the threads, and
998 release the current regcache objects. */
1001 for_each_process ([this] (process_info
*proc
) {
1002 int pid
= proc
->pid
;
1004 /* Look up any thread of this process. */
1005 current_thread
= find_any_thread_of_pid (pid
);
1010 current_thread
= saved_thread
;
1013 /* Process qSupported query, "xmlRegisters=". Update the buffer size for
1014 PTRACE_GETREGSET. */
1017 x86_target::process_qsupported (gdb::array_view
<const char * const> features
)
1019 /* Return if gdb doesn't support XML. If gdb sends "xmlRegisters="
1020 with "i386" in qSupported query, it supports x86 XML target
1024 for (const char *feature
: features
)
1026 if (startswith (feature
, "xmlRegisters="))
1028 char *copy
= xstrdup (feature
+ 13);
1031 for (char *p
= strtok_r (copy
, ",", &saveptr
);
1033 p
= strtok_r (NULL
, ",", &saveptr
))
1035 if (strcmp (p
, "i386") == 0)
1046 update_xmltarget ();
1049 /* Common for x86/x86-64. */
1051 static struct regsets_info x86_regsets_info
=
1053 x86_regsets
, /* regsets */
1054 0, /* num_regsets */
1055 NULL
, /* disabled_regsets */
1059 static struct regs_info amd64_linux_regs_info
=
1061 NULL
, /* regset_bitmap */
1062 NULL
, /* usrregs_info */
1066 static struct usrregs_info i386_linux_usrregs_info
=
1072 static struct regs_info i386_linux_regs_info
=
1074 NULL
, /* regset_bitmap */
1075 &i386_linux_usrregs_info
,
1080 x86_target::get_regs_info ()
1083 if (is_64bit_tdesc ())
1084 return &amd64_linux_regs_info
;
1087 return &i386_linux_regs_info
;
1090 /* Initialize the target description for the architecture of the
1094 x86_target::low_arch_setup ()
1096 current_process ()->tdesc
= x86_linux_read_description ();
1100 x86_target::low_supports_catch_syscall ()
1105 /* Fill *SYSNO and *SYSRET with the syscall nr trapped and the syscall return
1106 code. This should only be called if LWP got a SYSCALL_SIGTRAP. */
1109 x86_target::low_get_syscall_trapinfo (regcache
*regcache
, int *sysno
)
1111 int use_64bit
= register_size (regcache
->tdesc
, 0) == 8;
1117 collect_register_by_name (regcache
, "orig_rax", &l_sysno
);
1118 *sysno
= (int) l_sysno
;
1121 collect_register_by_name (regcache
, "orig_eax", sysno
);
1125 x86_target::supports_tracepoints ()
1131 append_insns (CORE_ADDR
*to
, size_t len
, const unsigned char *buf
)
1133 target_write_memory (*to
, buf
, len
);
1138 push_opcode (unsigned char *buf
, const char *op
)
1140 unsigned char *buf_org
= buf
;
1145 unsigned long ul
= strtoul (op
, &endptr
, 16);
1154 return buf
- buf_org
;
1159 /* Build a jump pad that saves registers and calls a collection
1160 function. Writes a jump instruction to the jump pad to
1161 JJUMPAD_INSN. The caller is responsible to write it in at the
1162 tracepoint address. */
1165 amd64_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint
, CORE_ADDR tpaddr
,
1166 CORE_ADDR collector
,
1169 CORE_ADDR
*jump_entry
,
1170 CORE_ADDR
*trampoline
,
1171 ULONGEST
*trampoline_size
,
1172 unsigned char *jjump_pad_insn
,
1173 ULONGEST
*jjump_pad_insn_size
,
1174 CORE_ADDR
*adjusted_insn_addr
,
1175 CORE_ADDR
*adjusted_insn_addr_end
,
1178 unsigned char buf
[40];
1182 CORE_ADDR buildaddr
= *jump_entry
;
1184 /* Build the jump pad. */
1186 /* First, do tracepoint data collection. Save registers. */
1188 /* Need to ensure stack pointer saved first. */
1189 buf
[i
++] = 0x54; /* push %rsp */
1190 buf
[i
++] = 0x55; /* push %rbp */
1191 buf
[i
++] = 0x57; /* push %rdi */
1192 buf
[i
++] = 0x56; /* push %rsi */
1193 buf
[i
++] = 0x52; /* push %rdx */
1194 buf
[i
++] = 0x51; /* push %rcx */
1195 buf
[i
++] = 0x53; /* push %rbx */
1196 buf
[i
++] = 0x50; /* push %rax */
1197 buf
[i
++] = 0x41; buf
[i
++] = 0x57; /* push %r15 */
1198 buf
[i
++] = 0x41; buf
[i
++] = 0x56; /* push %r14 */
1199 buf
[i
++] = 0x41; buf
[i
++] = 0x55; /* push %r13 */
1200 buf
[i
++] = 0x41; buf
[i
++] = 0x54; /* push %r12 */
1201 buf
[i
++] = 0x41; buf
[i
++] = 0x53; /* push %r11 */
1202 buf
[i
++] = 0x41; buf
[i
++] = 0x52; /* push %r10 */
1203 buf
[i
++] = 0x41; buf
[i
++] = 0x51; /* push %r9 */
1204 buf
[i
++] = 0x41; buf
[i
++] = 0x50; /* push %r8 */
1205 buf
[i
++] = 0x9c; /* pushfq */
1206 buf
[i
++] = 0x48; /* movabs <addr>,%rdi */
1208 memcpy (buf
+ i
, &tpaddr
, 8);
1210 buf
[i
++] = 0x57; /* push %rdi */
1211 append_insns (&buildaddr
, i
, buf
);
1213 /* Stack space for the collecting_t object. */
1215 i
+= push_opcode (&buf
[i
], "48 83 ec 18"); /* sub $0x18,%rsp */
1216 i
+= push_opcode (&buf
[i
], "48 b8"); /* mov <tpoint>,%rax */
1217 memcpy (buf
+ i
, &tpoint
, 8);
1219 i
+= push_opcode (&buf
[i
], "48 89 04 24"); /* mov %rax,(%rsp) */
1220 i
+= push_opcode (&buf
[i
],
1221 "64 48 8b 04 25 00 00 00 00"); /* mov %fs:0x0,%rax */
1222 i
+= push_opcode (&buf
[i
], "48 89 44 24 08"); /* mov %rax,0x8(%rsp) */
1223 append_insns (&buildaddr
, i
, buf
);
1227 i
+= push_opcode (&buf
[i
], "48 be"); /* movl <lockaddr>,%rsi */
1228 memcpy (&buf
[i
], (void *) &lockaddr
, 8);
1230 i
+= push_opcode (&buf
[i
], "48 89 e1"); /* mov %rsp,%rcx */
1231 i
+= push_opcode (&buf
[i
], "31 c0"); /* xor %eax,%eax */
1232 i
+= push_opcode (&buf
[i
], "f0 48 0f b1 0e"); /* lock cmpxchg %rcx,(%rsi) */
1233 i
+= push_opcode (&buf
[i
], "48 85 c0"); /* test %rax,%rax */
1234 i
+= push_opcode (&buf
[i
], "75 f4"); /* jne <again> */
1235 append_insns (&buildaddr
, i
, buf
);
1237 /* Set up the gdb_collect call. */
1238 /* At this point, (stack pointer + 0x18) is the base of our saved
1242 i
+= push_opcode (&buf
[i
], "48 89 e6"); /* mov %rsp,%rsi */
1243 i
+= push_opcode (&buf
[i
], "48 83 c6 18"); /* add $0x18,%rsi */
1245 /* tpoint address may be 64-bit wide. */
1246 i
+= push_opcode (&buf
[i
], "48 bf"); /* movl <addr>,%rdi */
1247 memcpy (buf
+ i
, &tpoint
, 8);
1249 append_insns (&buildaddr
, i
, buf
);
1251 /* The collector function being in the shared library, may be
1252 >31-bits away off the jump pad. */
1254 i
+= push_opcode (&buf
[i
], "48 b8"); /* mov $collector,%rax */
1255 memcpy (buf
+ i
, &collector
, 8);
1257 i
+= push_opcode (&buf
[i
], "ff d0"); /* callq *%rax */
1258 append_insns (&buildaddr
, i
, buf
);
1260 /* Clear the spin-lock. */
1262 i
+= push_opcode (&buf
[i
], "31 c0"); /* xor %eax,%eax */
1263 i
+= push_opcode (&buf
[i
], "48 a3"); /* mov %rax, lockaddr */
1264 memcpy (buf
+ i
, &lockaddr
, 8);
1266 append_insns (&buildaddr
, i
, buf
);
1268 /* Remove stack that had been used for the collect_t object. */
1270 i
+= push_opcode (&buf
[i
], "48 83 c4 18"); /* add $0x18,%rsp */
1271 append_insns (&buildaddr
, i
, buf
);
1273 /* Restore register state. */
1275 buf
[i
++] = 0x48; /* add $0x8,%rsp */
1279 buf
[i
++] = 0x9d; /* popfq */
1280 buf
[i
++] = 0x41; buf
[i
++] = 0x58; /* pop %r8 */
1281 buf
[i
++] = 0x41; buf
[i
++] = 0x59; /* pop %r9 */
1282 buf
[i
++] = 0x41; buf
[i
++] = 0x5a; /* pop %r10 */
1283 buf
[i
++] = 0x41; buf
[i
++] = 0x5b; /* pop %r11 */
1284 buf
[i
++] = 0x41; buf
[i
++] = 0x5c; /* pop %r12 */
1285 buf
[i
++] = 0x41; buf
[i
++] = 0x5d; /* pop %r13 */
1286 buf
[i
++] = 0x41; buf
[i
++] = 0x5e; /* pop %r14 */
1287 buf
[i
++] = 0x41; buf
[i
++] = 0x5f; /* pop %r15 */
1288 buf
[i
++] = 0x58; /* pop %rax */
1289 buf
[i
++] = 0x5b; /* pop %rbx */
1290 buf
[i
++] = 0x59; /* pop %rcx */
1291 buf
[i
++] = 0x5a; /* pop %rdx */
1292 buf
[i
++] = 0x5e; /* pop %rsi */
1293 buf
[i
++] = 0x5f; /* pop %rdi */
1294 buf
[i
++] = 0x5d; /* pop %rbp */
1295 buf
[i
++] = 0x5c; /* pop %rsp */
1296 append_insns (&buildaddr
, i
, buf
);
1298 /* Now, adjust the original instruction to execute in the jump
1300 *adjusted_insn_addr
= buildaddr
;
1301 relocate_instruction (&buildaddr
, tpaddr
);
1302 *adjusted_insn_addr_end
= buildaddr
;
1304 /* Finally, write a jump back to the program. */
1306 loffset
= (tpaddr
+ orig_size
) - (buildaddr
+ sizeof (jump_insn
));
1307 if (loffset
> INT_MAX
|| loffset
< INT_MIN
)
1310 "E.Jump back from jump pad too far from tracepoint "
1311 "(offset 0x%" PRIx64
" > int32).", loffset
);
1315 offset
= (int) loffset
;
1316 memcpy (buf
, jump_insn
, sizeof (jump_insn
));
1317 memcpy (buf
+ 1, &offset
, 4);
1318 append_insns (&buildaddr
, sizeof (jump_insn
), buf
);
1320 /* The jump pad is now built. Wire in a jump to our jump pad. This
1321 is always done last (by our caller actually), so that we can
1322 install fast tracepoints with threads running. This relies on
1323 the agent's atomic write support. */
1324 loffset
= *jump_entry
- (tpaddr
+ sizeof (jump_insn
));
1325 if (loffset
> INT_MAX
|| loffset
< INT_MIN
)
1328 "E.Jump pad too far from tracepoint "
1329 "(offset 0x%" PRIx64
" > int32).", loffset
);
1333 offset
= (int) loffset
;
1335 memcpy (buf
, jump_insn
, sizeof (jump_insn
));
1336 memcpy (buf
+ 1, &offset
, 4);
1337 memcpy (jjump_pad_insn
, buf
, sizeof (jump_insn
));
1338 *jjump_pad_insn_size
= sizeof (jump_insn
);
1340 /* Return the end address of our pad. */
1341 *jump_entry
= buildaddr
;
1346 #endif /* __x86_64__ */
1348 /* Build a jump pad that saves registers and calls a collection
1349 function. Writes a jump instruction to the jump pad to
1350 JJUMPAD_INSN. The caller is responsible to write it in at the
1351 tracepoint address. */
1354 i386_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint
, CORE_ADDR tpaddr
,
1355 CORE_ADDR collector
,
1358 CORE_ADDR
*jump_entry
,
1359 CORE_ADDR
*trampoline
,
1360 ULONGEST
*trampoline_size
,
1361 unsigned char *jjump_pad_insn
,
1362 ULONGEST
*jjump_pad_insn_size
,
1363 CORE_ADDR
*adjusted_insn_addr
,
1364 CORE_ADDR
*adjusted_insn_addr_end
,
1367 unsigned char buf
[0x100];
1369 CORE_ADDR buildaddr
= *jump_entry
;
1371 /* Build the jump pad. */
1373 /* First, do tracepoint data collection. Save registers. */
1375 buf
[i
++] = 0x60; /* pushad */
1376 buf
[i
++] = 0x68; /* push tpaddr aka $pc */
1377 *((int *)(buf
+ i
)) = (int) tpaddr
;
1379 buf
[i
++] = 0x9c; /* pushf */
1380 buf
[i
++] = 0x1e; /* push %ds */
1381 buf
[i
++] = 0x06; /* push %es */
1382 buf
[i
++] = 0x0f; /* push %fs */
1384 buf
[i
++] = 0x0f; /* push %gs */
1386 buf
[i
++] = 0x16; /* push %ss */
1387 buf
[i
++] = 0x0e; /* push %cs */
1388 append_insns (&buildaddr
, i
, buf
);
1390 /* Stack space for the collecting_t object. */
1392 i
+= push_opcode (&buf
[i
], "83 ec 08"); /* sub $0x8,%esp */
1394 /* Build the object. */
1395 i
+= push_opcode (&buf
[i
], "b8"); /* mov <tpoint>,%eax */
1396 memcpy (buf
+ i
, &tpoint
, 4);
1398 i
+= push_opcode (&buf
[i
], "89 04 24"); /* mov %eax,(%esp) */
1400 i
+= push_opcode (&buf
[i
], "65 a1 00 00 00 00"); /* mov %gs:0x0,%eax */
1401 i
+= push_opcode (&buf
[i
], "89 44 24 04"); /* mov %eax,0x4(%esp) */
1402 append_insns (&buildaddr
, i
, buf
);
1404 /* spin-lock. Note this is using cmpxchg, which leaves i386 behind.
1405 If we cared for it, this could be using xchg alternatively. */
1408 i
+= push_opcode (&buf
[i
], "31 c0"); /* xor %eax,%eax */
1409 i
+= push_opcode (&buf
[i
], "f0 0f b1 25"); /* lock cmpxchg
1411 memcpy (&buf
[i
], (void *) &lockaddr
, 4);
1413 i
+= push_opcode (&buf
[i
], "85 c0"); /* test %eax,%eax */
1414 i
+= push_opcode (&buf
[i
], "75 f2"); /* jne <again> */
1415 append_insns (&buildaddr
, i
, buf
);
1418 /* Set up arguments to the gdb_collect call. */
1420 i
+= push_opcode (&buf
[i
], "89 e0"); /* mov %esp,%eax */
1421 i
+= push_opcode (&buf
[i
], "83 c0 08"); /* add $0x08,%eax */
1422 i
+= push_opcode (&buf
[i
], "89 44 24 fc"); /* mov %eax,-0x4(%esp) */
1423 append_insns (&buildaddr
, i
, buf
);
1426 i
+= push_opcode (&buf
[i
], "83 ec 08"); /* sub $0x8,%esp */
1427 append_insns (&buildaddr
, i
, buf
);
1430 i
+= push_opcode (&buf
[i
], "c7 04 24"); /* movl <addr>,(%esp) */
1431 memcpy (&buf
[i
], (void *) &tpoint
, 4);
1433 append_insns (&buildaddr
, i
, buf
);
1435 buf
[0] = 0xe8; /* call <reladdr> */
1436 offset
= collector
- (buildaddr
+ sizeof (jump_insn
));
1437 memcpy (buf
+ 1, &offset
, 4);
1438 append_insns (&buildaddr
, 5, buf
);
1439 /* Clean up after the call. */
1440 buf
[0] = 0x83; /* add $0x8,%esp */
1443 append_insns (&buildaddr
, 3, buf
);
1446 /* Clear the spin-lock. This would need the LOCK prefix on older
1449 i
+= push_opcode (&buf
[i
], "31 c0"); /* xor %eax,%eax */
1450 i
+= push_opcode (&buf
[i
], "a3"); /* mov %eax, lockaddr */
1451 memcpy (buf
+ i
, &lockaddr
, 4);
1453 append_insns (&buildaddr
, i
, buf
);
1456 /* Remove stack that had been used for the collect_t object. */
1458 i
+= push_opcode (&buf
[i
], "83 c4 08"); /* add $0x08,%esp */
1459 append_insns (&buildaddr
, i
, buf
);
1462 buf
[i
++] = 0x83; /* add $0x4,%esp (no pop of %cs, assume unchanged) */
1465 buf
[i
++] = 0x17; /* pop %ss */
1466 buf
[i
++] = 0x0f; /* pop %gs */
1468 buf
[i
++] = 0x0f; /* pop %fs */
1470 buf
[i
++] = 0x07; /* pop %es */
1471 buf
[i
++] = 0x1f; /* pop %ds */
1472 buf
[i
++] = 0x9d; /* popf */
1473 buf
[i
++] = 0x83; /* add $0x4,%esp (pop of tpaddr aka $pc) */
1476 buf
[i
++] = 0x61; /* popad */
1477 append_insns (&buildaddr
, i
, buf
);
1479 /* Now, adjust the original instruction to execute in the jump
1481 *adjusted_insn_addr
= buildaddr
;
1482 relocate_instruction (&buildaddr
, tpaddr
);
1483 *adjusted_insn_addr_end
= buildaddr
;
1485 /* Write the jump back to the program. */
1486 offset
= (tpaddr
+ orig_size
) - (buildaddr
+ sizeof (jump_insn
));
1487 memcpy (buf
, jump_insn
, sizeof (jump_insn
));
1488 memcpy (buf
+ 1, &offset
, 4);
1489 append_insns (&buildaddr
, sizeof (jump_insn
), buf
);
1491 /* The jump pad is now built. Wire in a jump to our jump pad. This
1492 is always done last (by our caller actually), so that we can
1493 install fast tracepoints with threads running. This relies on
1494 the agent's atomic write support. */
1497 /* Create a trampoline. */
1498 *trampoline_size
= sizeof (jump_insn
);
1499 if (!claim_trampoline_space (*trampoline_size
, trampoline
))
1501 /* No trampoline space available. */
1503 "E.Cannot allocate trampoline space needed for fast "
1504 "tracepoints on 4-byte instructions.");
1508 offset
= *jump_entry
- (*trampoline
+ sizeof (jump_insn
));
1509 memcpy (buf
, jump_insn
, sizeof (jump_insn
));
1510 memcpy (buf
+ 1, &offset
, 4);
1511 target_write_memory (*trampoline
, buf
, sizeof (jump_insn
));
1513 /* Use a 16-bit relative jump instruction to jump to the trampoline. */
1514 offset
= (*trampoline
- (tpaddr
+ sizeof (small_jump_insn
))) & 0xffff;
1515 memcpy (buf
, small_jump_insn
, sizeof (small_jump_insn
));
1516 memcpy (buf
+ 2, &offset
, 2);
1517 memcpy (jjump_pad_insn
, buf
, sizeof (small_jump_insn
));
1518 *jjump_pad_insn_size
= sizeof (small_jump_insn
);
1522 /* Else use a 32-bit relative jump instruction. */
1523 offset
= *jump_entry
- (tpaddr
+ sizeof (jump_insn
));
1524 memcpy (buf
, jump_insn
, sizeof (jump_insn
));
1525 memcpy (buf
+ 1, &offset
, 4);
1526 memcpy (jjump_pad_insn
, buf
, sizeof (jump_insn
));
1527 *jjump_pad_insn_size
= sizeof (jump_insn
);
1530 /* Return the end address of our pad. */
1531 *jump_entry
= buildaddr
;
1537 x86_target::supports_fast_tracepoints ()
1543 x86_target::install_fast_tracepoint_jump_pad (CORE_ADDR tpoint
,
1545 CORE_ADDR collector
,
1548 CORE_ADDR
*jump_entry
,
1549 CORE_ADDR
*trampoline
,
1550 ULONGEST
*trampoline_size
,
1551 unsigned char *jjump_pad_insn
,
1552 ULONGEST
*jjump_pad_insn_size
,
1553 CORE_ADDR
*adjusted_insn_addr
,
1554 CORE_ADDR
*adjusted_insn_addr_end
,
1558 if (is_64bit_tdesc ())
1559 return amd64_install_fast_tracepoint_jump_pad (tpoint
, tpaddr
,
1560 collector
, lockaddr
,
1561 orig_size
, jump_entry
,
1562 trampoline
, trampoline_size
,
1564 jjump_pad_insn_size
,
1566 adjusted_insn_addr_end
,
1570 return i386_install_fast_tracepoint_jump_pad (tpoint
, tpaddr
,
1571 collector
, lockaddr
,
1572 orig_size
, jump_entry
,
1573 trampoline
, trampoline_size
,
1575 jjump_pad_insn_size
,
1577 adjusted_insn_addr_end
,
1581 /* Return the minimum instruction length for fast tracepoints on x86/x86-64
1585 x86_target::get_min_fast_tracepoint_insn_len ()
1587 static int warned_about_fast_tracepoints
= 0;
1590 /* On x86-64, 5-byte jump instructions with a 4-byte offset are always
1591 used for fast tracepoints. */
1592 if (is_64bit_tdesc ())
1596 if (agent_loaded_p ())
1598 char errbuf
[IPA_BUFSIZ
];
1602 /* On x86, if trampolines are available, then 4-byte jump instructions
1603 with a 2-byte offset may be used, otherwise 5-byte jump instructions
1604 with a 4-byte offset are used instead. */
1605 if (have_fast_tracepoint_trampoline_buffer (errbuf
))
1609 /* GDB has no channel to explain to user why a shorter fast
1610 tracepoint is not possible, but at least make GDBserver
1611 mention that something has gone awry. */
1612 if (!warned_about_fast_tracepoints
)
1614 warning ("4-byte fast tracepoints not available; %s", errbuf
);
1615 warned_about_fast_tracepoints
= 1;
1622 /* Indicate that the minimum length is currently unknown since the IPA
1623 has not loaded yet. */
1629 add_insns (unsigned char *start
, int len
)
1631 CORE_ADDR buildaddr
= current_insn_ptr
;
1634 debug_printf ("Adding %d bytes of insn at %s\n",
1635 len
, paddress (buildaddr
));
1637 append_insns (&buildaddr
, len
, start
);
1638 current_insn_ptr
= buildaddr
;
1641 /* Our general strategy for emitting code is to avoid specifying raw
1642 bytes whenever possible, and instead copy a block of inline asm
1643 that is embedded in the function. This is a little messy, because
1644 we need to keep the compiler from discarding what looks like dead
1645 code, plus suppress various warnings. */
1647 #define EMIT_ASM(NAME, INSNS) \
1650 extern unsigned char start_ ## NAME, end_ ## NAME; \
1651 add_insns (&start_ ## NAME, &end_ ## NAME - &start_ ## NAME); \
1652 __asm__ ("jmp end_" #NAME "\n" \
1653 "\t" "start_" #NAME ":" \
1655 "\t" "end_" #NAME ":"); \
1660 #define EMIT_ASM32(NAME,INSNS) \
1663 extern unsigned char start_ ## NAME, end_ ## NAME; \
1664 add_insns (&start_ ## NAME, &end_ ## NAME - &start_ ## NAME); \
1665 __asm__ (".code32\n" \
1666 "\t" "jmp end_" #NAME "\n" \
1667 "\t" "start_" #NAME ":\n" \
1669 "\t" "end_" #NAME ":\n" \
1675 #define EMIT_ASM32(NAME,INSNS) EMIT_ASM(NAME,INSNS)
1682 amd64_emit_prologue (void)
1684 EMIT_ASM (amd64_prologue
,
1686 "movq %rsp,%rbp\n\t"
1687 "sub $0x20,%rsp\n\t"
1688 "movq %rdi,-8(%rbp)\n\t"
1689 "movq %rsi,-16(%rbp)");
1694 amd64_emit_epilogue (void)
1696 EMIT_ASM (amd64_epilogue
,
1697 "movq -16(%rbp),%rdi\n\t"
1698 "movq %rax,(%rdi)\n\t"
1705 amd64_emit_add (void)
1707 EMIT_ASM (amd64_add
,
1708 "add (%rsp),%rax\n\t"
1709 "lea 0x8(%rsp),%rsp");
1713 amd64_emit_sub (void)
1715 EMIT_ASM (amd64_sub
,
1716 "sub %rax,(%rsp)\n\t"
1721 amd64_emit_mul (void)
1727 amd64_emit_lsh (void)
1733 amd64_emit_rsh_signed (void)
1739 amd64_emit_rsh_unsigned (void)
1745 amd64_emit_ext (int arg
)
1750 EMIT_ASM (amd64_ext_8
,
1756 EMIT_ASM (amd64_ext_16
,
1761 EMIT_ASM (amd64_ext_32
,
1770 amd64_emit_log_not (void)
1772 EMIT_ASM (amd64_log_not
,
1773 "test %rax,%rax\n\t"
1779 amd64_emit_bit_and (void)
1781 EMIT_ASM (amd64_and
,
1782 "and (%rsp),%rax\n\t"
1783 "lea 0x8(%rsp),%rsp");
1787 amd64_emit_bit_or (void)
1790 "or (%rsp),%rax\n\t"
1791 "lea 0x8(%rsp),%rsp");
1795 amd64_emit_bit_xor (void)
1797 EMIT_ASM (amd64_xor
,
1798 "xor (%rsp),%rax\n\t"
1799 "lea 0x8(%rsp),%rsp");
1803 amd64_emit_bit_not (void)
1805 EMIT_ASM (amd64_bit_not
,
1806 "xorq $0xffffffffffffffff,%rax");
1810 amd64_emit_equal (void)
1812 EMIT_ASM (amd64_equal
,
1813 "cmp %rax,(%rsp)\n\t"
1814 "je .Lamd64_equal_true\n\t"
1816 "jmp .Lamd64_equal_end\n\t"
1817 ".Lamd64_equal_true:\n\t"
1819 ".Lamd64_equal_end:\n\t"
1820 "lea 0x8(%rsp),%rsp");
1824 amd64_emit_less_signed (void)
1826 EMIT_ASM (amd64_less_signed
,
1827 "cmp %rax,(%rsp)\n\t"
1828 "jl .Lamd64_less_signed_true\n\t"
1830 "jmp .Lamd64_less_signed_end\n\t"
1831 ".Lamd64_less_signed_true:\n\t"
1833 ".Lamd64_less_signed_end:\n\t"
1834 "lea 0x8(%rsp),%rsp");
1838 amd64_emit_less_unsigned (void)
1840 EMIT_ASM (amd64_less_unsigned
,
1841 "cmp %rax,(%rsp)\n\t"
1842 "jb .Lamd64_less_unsigned_true\n\t"
1844 "jmp .Lamd64_less_unsigned_end\n\t"
1845 ".Lamd64_less_unsigned_true:\n\t"
1847 ".Lamd64_less_unsigned_end:\n\t"
1848 "lea 0x8(%rsp),%rsp");
1852 amd64_emit_ref (int size
)
1857 EMIT_ASM (amd64_ref1
,
1861 EMIT_ASM (amd64_ref2
,
1865 EMIT_ASM (amd64_ref4
,
1866 "movl (%rax),%eax");
1869 EMIT_ASM (amd64_ref8
,
1870 "movq (%rax),%rax");
1876 amd64_emit_if_goto (int *offset_p
, int *size_p
)
1878 EMIT_ASM (amd64_if_goto
,
1882 ".byte 0x0f, 0x85, 0x0, 0x0, 0x0, 0x0");
1890 amd64_emit_goto (int *offset_p
, int *size_p
)
1892 EMIT_ASM (amd64_goto
,
1893 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0");
1901 amd64_write_goto_address (CORE_ADDR from
, CORE_ADDR to
, int size
)
1903 int diff
= (to
- (from
+ size
));
1904 unsigned char buf
[sizeof (int)];
1912 memcpy (buf
, &diff
, sizeof (int));
1913 target_write_memory (from
, buf
, sizeof (int));
1917 amd64_emit_const (LONGEST num
)
1919 unsigned char buf
[16];
1921 CORE_ADDR buildaddr
= current_insn_ptr
;
1924 buf
[i
++] = 0x48; buf
[i
++] = 0xb8; /* mov $<n>,%rax */
1925 memcpy (&buf
[i
], &num
, sizeof (num
));
1927 append_insns (&buildaddr
, i
, buf
);
1928 current_insn_ptr
= buildaddr
;
1932 amd64_emit_call (CORE_ADDR fn
)
1934 unsigned char buf
[16];
1936 CORE_ADDR buildaddr
;
1939 /* The destination function being in the shared library, may be
1940 >31-bits away off the compiled code pad. */
1942 buildaddr
= current_insn_ptr
;
1944 offset64
= fn
- (buildaddr
+ 1 /* call op */ + 4 /* 32-bit offset */);
1948 if (offset64
> INT_MAX
|| offset64
< INT_MIN
)
1950 /* Offset is too large for a call. Use callq, but that requires
1951 a register, so avoid it if possible. Use r10, since it is
1952 call-clobbered, we don't have to push/pop it. */
1953 buf
[i
++] = 0x48; /* mov $fn,%r10 */
1955 memcpy (buf
+ i
, &fn
, 8);
1957 buf
[i
++] = 0xff; /* callq *%r10 */
1962 int offset32
= offset64
; /* we know we can't overflow here. */
1964 buf
[i
++] = 0xe8; /* call <reladdr> */
1965 memcpy (buf
+ i
, &offset32
, 4);
1969 append_insns (&buildaddr
, i
, buf
);
1970 current_insn_ptr
= buildaddr
;
1974 amd64_emit_reg (int reg
)
1976 unsigned char buf
[16];
1978 CORE_ADDR buildaddr
;
1980 /* Assume raw_regs is still in %rdi. */
1981 buildaddr
= current_insn_ptr
;
1983 buf
[i
++] = 0xbe; /* mov $<n>,%esi */
1984 memcpy (&buf
[i
], ®
, sizeof (reg
));
1986 append_insns (&buildaddr
, i
, buf
);
1987 current_insn_ptr
= buildaddr
;
1988 amd64_emit_call (get_raw_reg_func_addr ());
1992 amd64_emit_pop (void)
1994 EMIT_ASM (amd64_pop
,
1999 amd64_emit_stack_flush (void)
2001 EMIT_ASM (amd64_stack_flush
,
2006 amd64_emit_zero_ext (int arg
)
2011 EMIT_ASM (amd64_zero_ext_8
,
2015 EMIT_ASM (amd64_zero_ext_16
,
2016 "and $0xffff,%rax");
2019 EMIT_ASM (amd64_zero_ext_32
,
2020 "mov $0xffffffff,%rcx\n\t"
2029 amd64_emit_swap (void)
2031 EMIT_ASM (amd64_swap
,
2038 amd64_emit_stack_adjust (int n
)
2040 unsigned char buf
[16];
2042 CORE_ADDR buildaddr
= current_insn_ptr
;
2045 buf
[i
++] = 0x48; /* lea $<n>(%rsp),%rsp */
2049 /* This only handles adjustments up to 16, but we don't expect any more. */
2051 append_insns (&buildaddr
, i
, buf
);
2052 current_insn_ptr
= buildaddr
;
2055 /* FN's prototype is `LONGEST(*fn)(int)'. */
2058 amd64_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
2060 unsigned char buf
[16];
2062 CORE_ADDR buildaddr
;
2064 buildaddr
= current_insn_ptr
;
2066 buf
[i
++] = 0xbf; /* movl $<n>,%edi */
2067 memcpy (&buf
[i
], &arg1
, sizeof (arg1
));
2069 append_insns (&buildaddr
, i
, buf
);
2070 current_insn_ptr
= buildaddr
;
2071 amd64_emit_call (fn
);
2074 /* FN's prototype is `void(*fn)(int,LONGEST)'. */
2077 amd64_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
2079 unsigned char buf
[16];
2081 CORE_ADDR buildaddr
;
2083 buildaddr
= current_insn_ptr
;
2085 buf
[i
++] = 0xbf; /* movl $<n>,%edi */
2086 memcpy (&buf
[i
], &arg1
, sizeof (arg1
));
2088 append_insns (&buildaddr
, i
, buf
);
2089 current_insn_ptr
= buildaddr
;
2090 EMIT_ASM (amd64_void_call_2_a
,
2091 /* Save away a copy of the stack top. */
2093 /* Also pass top as the second argument. */
2095 amd64_emit_call (fn
);
2096 EMIT_ASM (amd64_void_call_2_b
,
2097 /* Restore the stack top, %rax may have been trashed. */
2102 amd64_emit_eq_goto (int *offset_p
, int *size_p
)
2105 "cmp %rax,(%rsp)\n\t"
2106 "jne .Lamd64_eq_fallthru\n\t"
2107 "lea 0x8(%rsp),%rsp\n\t"
2109 /* jmp, but don't trust the assembler to choose the right jump */
2110 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2111 ".Lamd64_eq_fallthru:\n\t"
2112 "lea 0x8(%rsp),%rsp\n\t"
2122 amd64_emit_ne_goto (int *offset_p
, int *size_p
)
2125 "cmp %rax,(%rsp)\n\t"
2126 "je .Lamd64_ne_fallthru\n\t"
2127 "lea 0x8(%rsp),%rsp\n\t"
2129 /* jmp, but don't trust the assembler to choose the right jump */
2130 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2131 ".Lamd64_ne_fallthru:\n\t"
2132 "lea 0x8(%rsp),%rsp\n\t"
2142 amd64_emit_lt_goto (int *offset_p
, int *size_p
)
2145 "cmp %rax,(%rsp)\n\t"
2146 "jnl .Lamd64_lt_fallthru\n\t"
2147 "lea 0x8(%rsp),%rsp\n\t"
2149 /* jmp, but don't trust the assembler to choose the right jump */
2150 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2151 ".Lamd64_lt_fallthru:\n\t"
2152 "lea 0x8(%rsp),%rsp\n\t"
2162 amd64_emit_le_goto (int *offset_p
, int *size_p
)
2165 "cmp %rax,(%rsp)\n\t"
2166 "jnle .Lamd64_le_fallthru\n\t"
2167 "lea 0x8(%rsp),%rsp\n\t"
2169 /* jmp, but don't trust the assembler to choose the right jump */
2170 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2171 ".Lamd64_le_fallthru:\n\t"
2172 "lea 0x8(%rsp),%rsp\n\t"
2182 amd64_emit_gt_goto (int *offset_p
, int *size_p
)
2185 "cmp %rax,(%rsp)\n\t"
2186 "jng .Lamd64_gt_fallthru\n\t"
2187 "lea 0x8(%rsp),%rsp\n\t"
2189 /* jmp, but don't trust the assembler to choose the right jump */
2190 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2191 ".Lamd64_gt_fallthru:\n\t"
2192 "lea 0x8(%rsp),%rsp\n\t"
2202 amd64_emit_ge_goto (int *offset_p
, int *size_p
)
2205 "cmp %rax,(%rsp)\n\t"
2206 "jnge .Lamd64_ge_fallthru\n\t"
2207 ".Lamd64_ge_jump:\n\t"
2208 "lea 0x8(%rsp),%rsp\n\t"
2210 /* jmp, but don't trust the assembler to choose the right jump */
2211 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2212 ".Lamd64_ge_fallthru:\n\t"
2213 "lea 0x8(%rsp),%rsp\n\t"
2222 static emit_ops amd64_emit_ops
=
2224 amd64_emit_prologue
,
2225 amd64_emit_epilogue
,
2230 amd64_emit_rsh_signed
,
2231 amd64_emit_rsh_unsigned
,
2239 amd64_emit_less_signed
,
2240 amd64_emit_less_unsigned
,
2244 amd64_write_goto_address
,
2249 amd64_emit_stack_flush
,
2250 amd64_emit_zero_ext
,
2252 amd64_emit_stack_adjust
,
2253 amd64_emit_int_call_1
,
2254 amd64_emit_void_call_2
,
2263 #endif /* __x86_64__ */
2266 i386_emit_prologue (void)
2268 EMIT_ASM32 (i386_prologue
,
2272 /* At this point, the raw regs base address is at 8(%ebp), and the
2273 value pointer is at 12(%ebp). */
2277 i386_emit_epilogue (void)
2279 EMIT_ASM32 (i386_epilogue
,
2280 "mov 12(%ebp),%ecx\n\t"
2281 "mov %eax,(%ecx)\n\t"
2282 "mov %ebx,0x4(%ecx)\n\t"
2290 i386_emit_add (void)
2292 EMIT_ASM32 (i386_add
,
2293 "add (%esp),%eax\n\t"
2294 "adc 0x4(%esp),%ebx\n\t"
2295 "lea 0x8(%esp),%esp");
2299 i386_emit_sub (void)
2301 EMIT_ASM32 (i386_sub
,
2302 "subl %eax,(%esp)\n\t"
2303 "sbbl %ebx,4(%esp)\n\t"
2309 i386_emit_mul (void)
2315 i386_emit_lsh (void)
2321 i386_emit_rsh_signed (void)
2327 i386_emit_rsh_unsigned (void)
2333 i386_emit_ext (int arg
)
2338 EMIT_ASM32 (i386_ext_8
,
2341 "movl %eax,%ebx\n\t"
2345 EMIT_ASM32 (i386_ext_16
,
2347 "movl %eax,%ebx\n\t"
2351 EMIT_ASM32 (i386_ext_32
,
2352 "movl %eax,%ebx\n\t"
2361 i386_emit_log_not (void)
2363 EMIT_ASM32 (i386_log_not
,
2365 "test %eax,%eax\n\t"
2372 i386_emit_bit_and (void)
2374 EMIT_ASM32 (i386_and
,
2375 "and (%esp),%eax\n\t"
2376 "and 0x4(%esp),%ebx\n\t"
2377 "lea 0x8(%esp),%esp");
2381 i386_emit_bit_or (void)
2383 EMIT_ASM32 (i386_or
,
2384 "or (%esp),%eax\n\t"
2385 "or 0x4(%esp),%ebx\n\t"
2386 "lea 0x8(%esp),%esp");
2390 i386_emit_bit_xor (void)
2392 EMIT_ASM32 (i386_xor
,
2393 "xor (%esp),%eax\n\t"
2394 "xor 0x4(%esp),%ebx\n\t"
2395 "lea 0x8(%esp),%esp");
2399 i386_emit_bit_not (void)
2401 EMIT_ASM32 (i386_bit_not
,
2402 "xor $0xffffffff,%eax\n\t"
2403 "xor $0xffffffff,%ebx\n\t");
2407 i386_emit_equal (void)
2409 EMIT_ASM32 (i386_equal
,
2410 "cmpl %ebx,4(%esp)\n\t"
2411 "jne .Li386_equal_false\n\t"
2412 "cmpl %eax,(%esp)\n\t"
2413 "je .Li386_equal_true\n\t"
2414 ".Li386_equal_false:\n\t"
2416 "jmp .Li386_equal_end\n\t"
2417 ".Li386_equal_true:\n\t"
2419 ".Li386_equal_end:\n\t"
2421 "lea 0x8(%esp),%esp");
2425 i386_emit_less_signed (void)
2427 EMIT_ASM32 (i386_less_signed
,
2428 "cmpl %ebx,4(%esp)\n\t"
2429 "jl .Li386_less_signed_true\n\t"
2430 "jne .Li386_less_signed_false\n\t"
2431 "cmpl %eax,(%esp)\n\t"
2432 "jl .Li386_less_signed_true\n\t"
2433 ".Li386_less_signed_false:\n\t"
2435 "jmp .Li386_less_signed_end\n\t"
2436 ".Li386_less_signed_true:\n\t"
2438 ".Li386_less_signed_end:\n\t"
2440 "lea 0x8(%esp),%esp");
2444 i386_emit_less_unsigned (void)
2446 EMIT_ASM32 (i386_less_unsigned
,
2447 "cmpl %ebx,4(%esp)\n\t"
2448 "jb .Li386_less_unsigned_true\n\t"
2449 "jne .Li386_less_unsigned_false\n\t"
2450 "cmpl %eax,(%esp)\n\t"
2451 "jb .Li386_less_unsigned_true\n\t"
2452 ".Li386_less_unsigned_false:\n\t"
2454 "jmp .Li386_less_unsigned_end\n\t"
2455 ".Li386_less_unsigned_true:\n\t"
2457 ".Li386_less_unsigned_end:\n\t"
2459 "lea 0x8(%esp),%esp");
2463 i386_emit_ref (int size
)
2468 EMIT_ASM32 (i386_ref1
,
2472 EMIT_ASM32 (i386_ref2
,
2476 EMIT_ASM32 (i386_ref4
,
2477 "movl (%eax),%eax");
2480 EMIT_ASM32 (i386_ref8
,
2481 "movl 4(%eax),%ebx\n\t"
2482 "movl (%eax),%eax");
2488 i386_emit_if_goto (int *offset_p
, int *size_p
)
2490 EMIT_ASM32 (i386_if_goto
,
2496 /* Don't trust the assembler to choose the right jump */
2497 ".byte 0x0f, 0x85, 0x0, 0x0, 0x0, 0x0");
2500 *offset_p
= 11; /* be sure that this matches the sequence above */
2506 i386_emit_goto (int *offset_p
, int *size_p
)
2508 EMIT_ASM32 (i386_goto
,
2509 /* Don't trust the assembler to choose the right jump */
2510 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0");
2518 i386_write_goto_address (CORE_ADDR from
, CORE_ADDR to
, int size
)
2520 int diff
= (to
- (from
+ size
));
2521 unsigned char buf
[sizeof (int)];
2523 /* We're only doing 4-byte sizes at the moment. */
2530 memcpy (buf
, &diff
, sizeof (int));
2531 target_write_memory (from
, buf
, sizeof (int));
2535 i386_emit_const (LONGEST num
)
2537 unsigned char buf
[16];
2539 CORE_ADDR buildaddr
= current_insn_ptr
;
2542 buf
[i
++] = 0xb8; /* mov $<n>,%eax */
2543 lo
= num
& 0xffffffff;
2544 memcpy (&buf
[i
], &lo
, sizeof (lo
));
2546 hi
= ((num
>> 32) & 0xffffffff);
2549 buf
[i
++] = 0xbb; /* mov $<n>,%ebx */
2550 memcpy (&buf
[i
], &hi
, sizeof (hi
));
2555 buf
[i
++] = 0x31; buf
[i
++] = 0xdb; /* xor %ebx,%ebx */
2557 append_insns (&buildaddr
, i
, buf
);
2558 current_insn_ptr
= buildaddr
;
2562 i386_emit_call (CORE_ADDR fn
)
2564 unsigned char buf
[16];
2566 CORE_ADDR buildaddr
;
2568 buildaddr
= current_insn_ptr
;
2570 buf
[i
++] = 0xe8; /* call <reladdr> */
2571 offset
= ((int) fn
) - (buildaddr
+ 5);
2572 memcpy (buf
+ 1, &offset
, 4);
2573 append_insns (&buildaddr
, 5, buf
);
2574 current_insn_ptr
= buildaddr
;
2578 i386_emit_reg (int reg
)
2580 unsigned char buf
[16];
2582 CORE_ADDR buildaddr
;
2584 EMIT_ASM32 (i386_reg_a
,
2586 buildaddr
= current_insn_ptr
;
2588 buf
[i
++] = 0xb8; /* mov $<n>,%eax */
2589 memcpy (&buf
[i
], ®
, sizeof (reg
));
2591 append_insns (&buildaddr
, i
, buf
);
2592 current_insn_ptr
= buildaddr
;
2593 EMIT_ASM32 (i386_reg_b
,
2594 "mov %eax,4(%esp)\n\t"
2595 "mov 8(%ebp),%eax\n\t"
2597 i386_emit_call (get_raw_reg_func_addr ());
2598 EMIT_ASM32 (i386_reg_c
,
2600 "lea 0x8(%esp),%esp");
2604 i386_emit_pop (void)
2606 EMIT_ASM32 (i386_pop
,
2612 i386_emit_stack_flush (void)
2614 EMIT_ASM32 (i386_stack_flush
,
2620 i386_emit_zero_ext (int arg
)
2625 EMIT_ASM32 (i386_zero_ext_8
,
2626 "and $0xff,%eax\n\t"
2630 EMIT_ASM32 (i386_zero_ext_16
,
2631 "and $0xffff,%eax\n\t"
2635 EMIT_ASM32 (i386_zero_ext_32
,
2644 i386_emit_swap (void)
2646 EMIT_ASM32 (i386_swap
,
2656 i386_emit_stack_adjust (int n
)
2658 unsigned char buf
[16];
2660 CORE_ADDR buildaddr
= current_insn_ptr
;
2663 buf
[i
++] = 0x8d; /* lea $<n>(%esp),%esp */
2667 append_insns (&buildaddr
, i
, buf
);
2668 current_insn_ptr
= buildaddr
;
2671 /* FN's prototype is `LONGEST(*fn)(int)'. */
2674 i386_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
2676 unsigned char buf
[16];
2678 CORE_ADDR buildaddr
;
2680 EMIT_ASM32 (i386_int_call_1_a
,
2681 /* Reserve a bit of stack space. */
2683 /* Put the one argument on the stack. */
2684 buildaddr
= current_insn_ptr
;
2686 buf
[i
++] = 0xc7; /* movl $<arg1>,(%esp) */
2689 memcpy (&buf
[i
], &arg1
, sizeof (arg1
));
2691 append_insns (&buildaddr
, i
, buf
);
2692 current_insn_ptr
= buildaddr
;
2693 i386_emit_call (fn
);
2694 EMIT_ASM32 (i386_int_call_1_c
,
2696 "lea 0x8(%esp),%esp");
2699 /* FN's prototype is `void(*fn)(int,LONGEST)'. */
2702 i386_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
2704 unsigned char buf
[16];
2706 CORE_ADDR buildaddr
;
2708 EMIT_ASM32 (i386_void_call_2_a
,
2709 /* Preserve %eax only; we don't have to worry about %ebx. */
2711 /* Reserve a bit of stack space for arguments. */
2712 "sub $0x10,%esp\n\t"
2713 /* Copy "top" to the second argument position. (Note that
2714 we can't assume function won't scribble on its
2715 arguments, so don't try to restore from this.) */
2716 "mov %eax,4(%esp)\n\t"
2717 "mov %ebx,8(%esp)");
2718 /* Put the first argument on the stack. */
2719 buildaddr
= current_insn_ptr
;
2721 buf
[i
++] = 0xc7; /* movl $<arg1>,(%esp) */
2724 memcpy (&buf
[i
], &arg1
, sizeof (arg1
));
2726 append_insns (&buildaddr
, i
, buf
);
2727 current_insn_ptr
= buildaddr
;
2728 i386_emit_call (fn
);
2729 EMIT_ASM32 (i386_void_call_2_b
,
2730 "lea 0x10(%esp),%esp\n\t"
2731 /* Restore original stack top. */
2737 i386_emit_eq_goto (int *offset_p
, int *size_p
)
2740 /* Check low half first, more likely to be decider */
2741 "cmpl %eax,(%esp)\n\t"
2742 "jne .Leq_fallthru\n\t"
2743 "cmpl %ebx,4(%esp)\n\t"
2744 "jne .Leq_fallthru\n\t"
2745 "lea 0x8(%esp),%esp\n\t"
2748 /* jmp, but don't trust the assembler to choose the right jump */
2749 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2750 ".Leq_fallthru:\n\t"
2751 "lea 0x8(%esp),%esp\n\t"
2762 i386_emit_ne_goto (int *offset_p
, int *size_p
)
2765 /* Check low half first, more likely to be decider */
2766 "cmpl %eax,(%esp)\n\t"
2768 "cmpl %ebx,4(%esp)\n\t"
2769 "je .Lne_fallthru\n\t"
2771 "lea 0x8(%esp),%esp\n\t"
2774 /* jmp, but don't trust the assembler to choose the right jump */
2775 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2776 ".Lne_fallthru:\n\t"
2777 "lea 0x8(%esp),%esp\n\t"
2788 i386_emit_lt_goto (int *offset_p
, int *size_p
)
2791 "cmpl %ebx,4(%esp)\n\t"
2793 "jne .Llt_fallthru\n\t"
2794 "cmpl %eax,(%esp)\n\t"
2795 "jnl .Llt_fallthru\n\t"
2797 "lea 0x8(%esp),%esp\n\t"
2800 /* jmp, but don't trust the assembler to choose the right jump */
2801 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2802 ".Llt_fallthru:\n\t"
2803 "lea 0x8(%esp),%esp\n\t"
2814 i386_emit_le_goto (int *offset_p
, int *size_p
)
2817 "cmpl %ebx,4(%esp)\n\t"
2819 "jne .Lle_fallthru\n\t"
2820 "cmpl %eax,(%esp)\n\t"
2821 "jnle .Lle_fallthru\n\t"
2823 "lea 0x8(%esp),%esp\n\t"
2826 /* jmp, but don't trust the assembler to choose the right jump */
2827 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2828 ".Lle_fallthru:\n\t"
2829 "lea 0x8(%esp),%esp\n\t"
2840 i386_emit_gt_goto (int *offset_p
, int *size_p
)
2843 "cmpl %ebx,4(%esp)\n\t"
2845 "jne .Lgt_fallthru\n\t"
2846 "cmpl %eax,(%esp)\n\t"
2847 "jng .Lgt_fallthru\n\t"
2849 "lea 0x8(%esp),%esp\n\t"
2852 /* jmp, but don't trust the assembler to choose the right jump */
2853 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2854 ".Lgt_fallthru:\n\t"
2855 "lea 0x8(%esp),%esp\n\t"
2866 i386_emit_ge_goto (int *offset_p
, int *size_p
)
2869 "cmpl %ebx,4(%esp)\n\t"
2871 "jne .Lge_fallthru\n\t"
2872 "cmpl %eax,(%esp)\n\t"
2873 "jnge .Lge_fallthru\n\t"
2875 "lea 0x8(%esp),%esp\n\t"
2878 /* jmp, but don't trust the assembler to choose the right jump */
2879 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2880 ".Lge_fallthru:\n\t"
2881 "lea 0x8(%esp),%esp\n\t"
2891 static emit_ops i386_emit_ops
=
2899 i386_emit_rsh_signed
,
2900 i386_emit_rsh_unsigned
,
2908 i386_emit_less_signed
,
2909 i386_emit_less_unsigned
,
2913 i386_write_goto_address
,
2918 i386_emit_stack_flush
,
2921 i386_emit_stack_adjust
,
2922 i386_emit_int_call_1
,
2923 i386_emit_void_call_2
,
2934 x86_target::emit_ops ()
2937 if (is_64bit_tdesc ())
2938 return &amd64_emit_ops
;
2941 return &i386_emit_ops
;
2944 /* Implementation of target ops method "sw_breakpoint_from_kind". */
2947 x86_target::sw_breakpoint_from_kind (int kind
, int *size
)
2949 *size
= x86_breakpoint_len
;
2950 return x86_breakpoint
;
2954 x86_target::low_supports_range_stepping ()
2960 x86_target::get_ipa_tdesc_idx ()
2962 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
2963 const struct target_desc
*tdesc
= regcache
->tdesc
;
2966 return amd64_get_ipa_tdesc_idx (tdesc
);
2969 if (tdesc
== tdesc_i386_linux_no_xml
.get ())
2970 return X86_TDESC_SSE
;
2972 return i386_get_ipa_tdesc_idx (tdesc
);
2975 /* The linux target ops object. */
2977 linux_process_target
*the_linux_target
= &the_x86_target
;
2980 initialize_low_arch (void)
2982 /* Initialize the Linux target descriptions. */
2984 tdesc_amd64_linux_no_xml
= allocate_target_description ();
2985 copy_target_description (tdesc_amd64_linux_no_xml
.get (),
2986 amd64_linux_read_description (X86_XSTATE_SSE_MASK
,
2988 tdesc_amd64_linux_no_xml
->xmltarget
= xmltarget_amd64_linux_no_xml
;
2991 tdesc_i386_linux_no_xml
= allocate_target_description ();
2992 copy_target_description (tdesc_i386_linux_no_xml
.get (),
2993 i386_linux_read_description (X86_XSTATE_SSE_MASK
));
2994 tdesc_i386_linux_no_xml
->xmltarget
= xmltarget_i386_linux_no_xml
;
2996 initialize_regsets_info (&x86_regsets_info
);