1 /* GNU/Linux/x86-64 specific low level interface, for the remote server
3 Copyright (C) 2002-2020 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 #include "linux-low.h"
27 #include "gdbsupport/x86-xstate.h"
28 #include "nat/gdb_ptrace.h"
31 #include "nat/amd64-linux-siginfo.h"
34 #include "gdb_proc_service.h"
35 /* Don't include elf/common.h if linux/elf.h got included by
36 gdb_proc_service.h. */
38 #include "elf/common.h"
41 #include "gdbsupport/agent.h"
43 #include "tracepoint.h"
45 #include "nat/linux-nat.h"
46 #include "nat/x86-linux.h"
47 #include "nat/x86-linux-dregs.h"
48 #include "linux-x86-tdesc.h"
51 static struct target_desc
*tdesc_amd64_linux_no_xml
;
53 static struct target_desc
*tdesc_i386_linux_no_xml
;
56 static unsigned char jump_insn
[] = { 0xe9, 0, 0, 0, 0 };
57 static unsigned char small_jump_insn
[] = { 0x66, 0xe9, 0, 0 };
59 /* Backward compatibility for gdb without XML support. */
61 static const char *xmltarget_i386_linux_no_xml
= "@<target>\
62 <architecture>i386</architecture>\
63 <osabi>GNU/Linux</osabi>\
67 static const char *xmltarget_amd64_linux_no_xml
= "@<target>\
68 <architecture>i386:x86-64</architecture>\
69 <osabi>GNU/Linux</osabi>\
74 #include <sys/procfs.h>
77 #ifndef PTRACE_GET_THREAD_AREA
78 #define PTRACE_GET_THREAD_AREA 25
81 /* This definition comes from prctl.h, but some kernels may not have it. */
82 #ifndef PTRACE_ARCH_PRCTL
83 #define PTRACE_ARCH_PRCTL 30
86 /* The following definitions come from prctl.h, but may be absent
87 for certain configurations. */
89 #define ARCH_SET_GS 0x1001
90 #define ARCH_SET_FS 0x1002
91 #define ARCH_GET_FS 0x1003
92 #define ARCH_GET_GS 0x1004
95 /* Linux target op definitions for the x86 architecture.
96 This is initialized assuming an amd64 target.
97 'low_arch_setup' will correct it for i386 or amd64 targets. */
99 class x86_target
: public linux_process_target
103 /* Update all the target description of all processes; a new GDB
104 connected, and it may or not support xml target descriptions. */
105 void update_xmltarget ();
107 const regs_info
*get_regs_info () override
;
109 const gdb_byte
*sw_breakpoint_from_kind (int kind
, int *size
) override
;
111 bool supports_z_point_type (char z_type
) override
;
115 void low_arch_setup () override
;
117 bool low_cannot_fetch_register (int regno
) override
;
119 bool low_cannot_store_register (int regno
) override
;
121 bool low_supports_breakpoints () override
;
123 CORE_ADDR
low_get_pc (regcache
*regcache
) override
;
125 void low_set_pc (regcache
*regcache
, CORE_ADDR newpc
) override
;
127 int low_decr_pc_after_break () override
;
129 bool low_breakpoint_at (CORE_ADDR pc
) override
;
131 int low_insert_point (raw_bkpt_type type
, CORE_ADDR addr
,
132 int size
, raw_breakpoint
*bp
) override
;
134 int low_remove_point (raw_bkpt_type type
, CORE_ADDR addr
,
135 int size
, raw_breakpoint
*bp
) override
;
137 bool low_stopped_by_watchpoint () override
;
139 CORE_ADDR
low_stopped_data_address () override
;
142 /* The singleton target ops object. */
144 static x86_target the_x86_target
;
146 /* Per-process arch-specific data we want to keep. */
148 struct arch_process_info
150 struct x86_debug_reg_state debug_reg_state
;
155 /* Mapping between the general-purpose registers in `struct user'
156 format and GDB's register array layout.
157 Note that the transfer layout uses 64-bit regs. */
158 static /*const*/ int i386_regmap
[] =
160 RAX
* 8, RCX
* 8, RDX
* 8, RBX
* 8,
161 RSP
* 8, RBP
* 8, RSI
* 8, RDI
* 8,
162 RIP
* 8, EFLAGS
* 8, CS
* 8, SS
* 8,
163 DS
* 8, ES
* 8, FS
* 8, GS
* 8
166 #define I386_NUM_REGS (sizeof (i386_regmap) / sizeof (i386_regmap[0]))
168 /* So code below doesn't have to care, i386 or amd64. */
169 #define ORIG_EAX ORIG_RAX
172 static const int x86_64_regmap
[] =
174 RAX
* 8, RBX
* 8, RCX
* 8, RDX
* 8,
175 RSI
* 8, RDI
* 8, RBP
* 8, RSP
* 8,
176 R8
* 8, R9
* 8, R10
* 8, R11
* 8,
177 R12
* 8, R13
* 8, R14
* 8, R15
* 8,
178 RIP
* 8, EFLAGS
* 8, CS
* 8, SS
* 8,
179 DS
* 8, ES
* 8, FS
* 8, GS
* 8,
180 -1, -1, -1, -1, -1, -1, -1, -1,
181 -1, -1, -1, -1, -1, -1, -1, -1,
182 -1, -1, -1, -1, -1, -1, -1, -1,
184 -1, -1, -1, -1, -1, -1, -1, -1,
186 #ifdef HAVE_STRUCT_USER_REGS_STRUCT_FS_BASE
191 -1, -1, -1, -1, /* MPX registers BND0 ... BND3. */
192 -1, -1, /* MPX registers BNDCFGU, BNDSTATUS. */
193 -1, -1, -1, -1, -1, -1, -1, -1, /* xmm16 ... xmm31 (AVX512) */
194 -1, -1, -1, -1, -1, -1, -1, -1,
195 -1, -1, -1, -1, -1, -1, -1, -1, /* ymm16 ... ymm31 (AVX512) */
196 -1, -1, -1, -1, -1, -1, -1, -1,
197 -1, -1, -1, -1, -1, -1, -1, -1, /* k0 ... k7 (AVX512) */
198 -1, -1, -1, -1, -1, -1, -1, -1, /* zmm0 ... zmm31 (AVX512) */
199 -1, -1, -1, -1, -1, -1, -1, -1,
200 -1, -1, -1, -1, -1, -1, -1, -1,
201 -1, -1, -1, -1, -1, -1, -1, -1,
205 #define X86_64_NUM_REGS (sizeof (x86_64_regmap) / sizeof (x86_64_regmap[0]))
206 #define X86_64_USER_REGS (GS + 1)
208 #else /* ! __x86_64__ */
210 /* Mapping between the general-purpose registers in `struct user'
211 format and GDB's register array layout. */
212 static /*const*/ int i386_regmap
[] =
214 EAX
* 4, ECX
* 4, EDX
* 4, EBX
* 4,
215 UESP
* 4, EBP
* 4, ESI
* 4, EDI
* 4,
216 EIP
* 4, EFL
* 4, CS
* 4, SS
* 4,
217 DS
* 4, ES
* 4, FS
* 4, GS
* 4
220 #define I386_NUM_REGS (sizeof (i386_regmap) / sizeof (i386_regmap[0]))
228 /* Returns true if the current inferior belongs to a x86-64 process,
232 is_64bit_tdesc (void)
234 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
236 return register_size (regcache
->tdesc
, 0) == 8;
242 /* Called by libthread_db. */
245 ps_get_thread_area (struct ps_prochandle
*ph
,
246 lwpid_t lwpid
, int idx
, void **base
)
249 int use_64bit
= is_64bit_tdesc ();
256 if (ptrace (PTRACE_ARCH_PRCTL
, lwpid
, base
, ARCH_GET_FS
) == 0)
260 if (ptrace (PTRACE_ARCH_PRCTL
, lwpid
, base
, ARCH_GET_GS
) == 0)
271 unsigned int desc
[4];
273 if (ptrace (PTRACE_GET_THREAD_AREA
, lwpid
,
274 (void *) (intptr_t) idx
, (unsigned long) &desc
) < 0)
277 /* Ensure we properly extend the value to 64-bits for x86_64. */
278 *base
= (void *) (uintptr_t) desc
[1];
283 /* Get the thread area address. This is used to recognize which
284 thread is which when tracing with the in-process agent library. We
285 don't read anything from the address, and treat it as opaque; it's
286 the address itself that we assume is unique per-thread. */
289 x86_get_thread_area (int lwpid
, CORE_ADDR
*addr
)
292 int use_64bit
= is_64bit_tdesc ();
297 if (ptrace (PTRACE_ARCH_PRCTL
, lwpid
, &base
, ARCH_GET_FS
) == 0)
299 *addr
= (CORE_ADDR
) (uintptr_t) base
;
308 struct lwp_info
*lwp
= find_lwp_pid (ptid_t (lwpid
));
309 struct thread_info
*thr
= get_lwp_thread (lwp
);
310 struct regcache
*regcache
= get_thread_regcache (thr
, 1);
311 unsigned int desc
[4];
313 const int reg_thread_area
= 3; /* bits to scale down register value. */
316 collect_register_by_name (regcache
, "gs", &gs
);
318 idx
= gs
>> reg_thread_area
;
320 if (ptrace (PTRACE_GET_THREAD_AREA
,
322 (void *) (long) idx
, (unsigned long) &desc
) < 0)
333 x86_target::low_cannot_store_register (int regno
)
336 if (is_64bit_tdesc ())
340 return regno
>= I386_NUM_REGS
;
344 x86_target::low_cannot_fetch_register (int regno
)
347 if (is_64bit_tdesc ())
351 return regno
>= I386_NUM_REGS
;
355 x86_fill_gregset (struct regcache
*regcache
, void *buf
)
360 if (register_size (regcache
->tdesc
, 0) == 8)
362 for (i
= 0; i
< X86_64_NUM_REGS
; i
++)
363 if (x86_64_regmap
[i
] != -1)
364 collect_register (regcache
, i
, ((char *) buf
) + x86_64_regmap
[i
]);
366 #ifndef HAVE_STRUCT_USER_REGS_STRUCT_FS_BASE
369 int lwpid
= lwpid_of (current_thread
);
371 collect_register_by_name (regcache
, "fs_base", &base
);
372 ptrace (PTRACE_ARCH_PRCTL
, lwpid
, &base
, ARCH_SET_FS
);
374 collect_register_by_name (regcache
, "gs_base", &base
);
375 ptrace (PTRACE_ARCH_PRCTL
, lwpid
, &base
, ARCH_SET_GS
);
382 /* 32-bit inferior registers need to be zero-extended.
383 Callers would read uninitialized memory otherwise. */
384 memset (buf
, 0x00, X86_64_USER_REGS
* 8);
387 for (i
= 0; i
< I386_NUM_REGS
; i
++)
388 collect_register (regcache
, i
, ((char *) buf
) + i386_regmap
[i
]);
390 collect_register_by_name (regcache
, "orig_eax",
391 ((char *) buf
) + ORIG_EAX
* REGSIZE
);
394 /* Sign extend EAX value to avoid potential syscall restart
397 See amd64_linux_collect_native_gregset() in gdb/amd64-linux-nat.c
398 for a detailed explanation. */
399 if (register_size (regcache
->tdesc
, 0) == 4)
401 void *ptr
= ((gdb_byte
*) buf
402 + i386_regmap
[find_regno (regcache
->tdesc
, "eax")]);
404 *(int64_t *) ptr
= *(int32_t *) ptr
;
410 x86_store_gregset (struct regcache
*regcache
, const void *buf
)
415 if (register_size (regcache
->tdesc
, 0) == 8)
417 for (i
= 0; i
< X86_64_NUM_REGS
; i
++)
418 if (x86_64_regmap
[i
] != -1)
419 supply_register (regcache
, i
, ((char *) buf
) + x86_64_regmap
[i
]);
421 #ifndef HAVE_STRUCT_USER_REGS_STRUCT_FS_BASE
424 int lwpid
= lwpid_of (current_thread
);
426 if (ptrace (PTRACE_ARCH_PRCTL
, lwpid
, &base
, ARCH_GET_FS
) == 0)
427 supply_register_by_name (regcache
, "fs_base", &base
);
429 if (ptrace (PTRACE_ARCH_PRCTL
, lwpid
, &base
, ARCH_GET_GS
) == 0)
430 supply_register_by_name (regcache
, "gs_base", &base
);
437 for (i
= 0; i
< I386_NUM_REGS
; i
++)
438 supply_register (regcache
, i
, ((char *) buf
) + i386_regmap
[i
]);
440 supply_register_by_name (regcache
, "orig_eax",
441 ((char *) buf
) + ORIG_EAX
* REGSIZE
);
445 x86_fill_fpregset (struct regcache
*regcache
, void *buf
)
448 i387_cache_to_fxsave (regcache
, buf
);
450 i387_cache_to_fsave (regcache
, buf
);
455 x86_store_fpregset (struct regcache
*regcache
, const void *buf
)
458 i387_fxsave_to_cache (regcache
, buf
);
460 i387_fsave_to_cache (regcache
, buf
);
467 x86_fill_fpxregset (struct regcache
*regcache
, void *buf
)
469 i387_cache_to_fxsave (regcache
, buf
);
473 x86_store_fpxregset (struct regcache
*regcache
, const void *buf
)
475 i387_fxsave_to_cache (regcache
, buf
);
481 x86_fill_xstateregset (struct regcache
*regcache
, void *buf
)
483 i387_cache_to_xsave (regcache
, buf
);
487 x86_store_xstateregset (struct regcache
*regcache
, const void *buf
)
489 i387_xsave_to_cache (regcache
, buf
);
492 /* ??? The non-biarch i386 case stores all the i387 regs twice.
493 Once in i387_.*fsave.* and once in i387_.*fxsave.*.
494 This is, presumably, to handle the case where PTRACE_[GS]ETFPXREGS
495 doesn't work. IWBN to avoid the duplication in the case where it
496 does work. Maybe the arch_setup routine could check whether it works
497 and update the supported regsets accordingly. */
499 static struct regset_info x86_regsets
[] =
501 #ifdef HAVE_PTRACE_GETREGS
502 { PTRACE_GETREGS
, PTRACE_SETREGS
, 0, sizeof (elf_gregset_t
),
504 x86_fill_gregset
, x86_store_gregset
},
505 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_X86_XSTATE
, 0,
506 EXTENDED_REGS
, x86_fill_xstateregset
, x86_store_xstateregset
},
508 # ifdef HAVE_PTRACE_GETFPXREGS
509 { PTRACE_GETFPXREGS
, PTRACE_SETFPXREGS
, 0, sizeof (elf_fpxregset_t
),
511 x86_fill_fpxregset
, x86_store_fpxregset
},
514 { PTRACE_GETFPREGS
, PTRACE_SETFPREGS
, 0, sizeof (elf_fpregset_t
),
516 x86_fill_fpregset
, x86_store_fpregset
},
517 #endif /* HAVE_PTRACE_GETREGS */
522 x86_target::low_supports_breakpoints ()
528 x86_target::low_get_pc (regcache
*regcache
)
530 int use_64bit
= register_size (regcache
->tdesc
, 0) == 8;
536 collect_register_by_name (regcache
, "rip", &pc
);
537 return (CORE_ADDR
) pc
;
543 collect_register_by_name (regcache
, "eip", &pc
);
544 return (CORE_ADDR
) pc
;
549 x86_target::low_set_pc (regcache
*regcache
, CORE_ADDR pc
)
551 int use_64bit
= register_size (regcache
->tdesc
, 0) == 8;
557 supply_register_by_name (regcache
, "rip", &newpc
);
563 supply_register_by_name (regcache
, "eip", &newpc
);
568 x86_target::low_decr_pc_after_break ()
574 static const gdb_byte x86_breakpoint
[] = { 0xCC };
575 #define x86_breakpoint_len 1
578 x86_target::low_breakpoint_at (CORE_ADDR pc
)
582 read_memory (pc
, &c
, 1);
589 /* Low-level function vector. */
590 struct x86_dr_low_type x86_dr_low
=
592 x86_linux_dr_set_control
,
593 x86_linux_dr_set_addr
,
594 x86_linux_dr_get_addr
,
595 x86_linux_dr_get_status
,
596 x86_linux_dr_get_control
,
600 /* Breakpoint/Watchpoint support. */
603 x86_target::supports_z_point_type (char z_type
)
609 case Z_PACKET_WRITE_WP
:
610 case Z_PACKET_ACCESS_WP
:
618 x86_target::low_insert_point (raw_bkpt_type type
, CORE_ADDR addr
,
619 int size
, raw_breakpoint
*bp
)
621 struct process_info
*proc
= current_process ();
625 case raw_bkpt_type_hw
:
626 case raw_bkpt_type_write_wp
:
627 case raw_bkpt_type_access_wp
:
629 enum target_hw_bp_type hw_type
630 = raw_bkpt_type_to_target_hw_bp_type (type
);
631 struct x86_debug_reg_state
*state
632 = &proc
->priv
->arch_private
->debug_reg_state
;
634 return x86_dr_insert_watchpoint (state
, hw_type
, addr
, size
);
644 x86_target::low_remove_point (raw_bkpt_type type
, CORE_ADDR addr
,
645 int size
, raw_breakpoint
*bp
)
647 struct process_info
*proc
= current_process ();
651 case raw_bkpt_type_hw
:
652 case raw_bkpt_type_write_wp
:
653 case raw_bkpt_type_access_wp
:
655 enum target_hw_bp_type hw_type
656 = raw_bkpt_type_to_target_hw_bp_type (type
);
657 struct x86_debug_reg_state
*state
658 = &proc
->priv
->arch_private
->debug_reg_state
;
660 return x86_dr_remove_watchpoint (state
, hw_type
, addr
, size
);
669 x86_target::low_stopped_by_watchpoint ()
671 struct process_info
*proc
= current_process ();
672 return x86_dr_stopped_by_watchpoint (&proc
->priv
->arch_private
->debug_reg_state
);
676 x86_target::low_stopped_data_address ()
678 struct process_info
*proc
= current_process ();
680 if (x86_dr_stopped_data_address (&proc
->priv
->arch_private
->debug_reg_state
,
686 /* Called when a new process is created. */
688 static struct arch_process_info
*
689 x86_linux_new_process (void)
691 struct arch_process_info
*info
= XCNEW (struct arch_process_info
);
693 x86_low_init_dregs (&info
->debug_reg_state
);
698 /* Called when a process is being deleted. */
701 x86_linux_delete_process (struct arch_process_info
*info
)
706 /* Target routine for linux_new_fork. */
709 x86_linux_new_fork (struct process_info
*parent
, struct process_info
*child
)
711 /* These are allocated by linux_add_process. */
712 gdb_assert (parent
->priv
!= NULL
713 && parent
->priv
->arch_private
!= NULL
);
714 gdb_assert (child
->priv
!= NULL
715 && child
->priv
->arch_private
!= NULL
);
717 /* Linux kernel before 2.6.33 commit
718 72f674d203cd230426437cdcf7dd6f681dad8b0d
719 will inherit hardware debug registers from parent
720 on fork/vfork/clone. Newer Linux kernels create such tasks with
721 zeroed debug registers.
723 GDB core assumes the child inherits the watchpoints/hw
724 breakpoints of the parent, and will remove them all from the
725 forked off process. Copy the debug registers mirrors into the
726 new process so that all breakpoints and watchpoints can be
727 removed together. The debug registers mirror will become zeroed
728 in the end before detaching the forked off process, thus making
729 this compatible with older Linux kernels too. */
731 *child
->priv
->arch_private
= *parent
->priv
->arch_private
;
734 /* See nat/x86-dregs.h. */
736 struct x86_debug_reg_state
*
737 x86_debug_reg_state (pid_t pid
)
739 struct process_info
*proc
= find_process_pid (pid
);
741 return &proc
->priv
->arch_private
->debug_reg_state
;
744 /* When GDBSERVER is built as a 64-bit application on linux, the
745 PTRACE_GETSIGINFO data is always presented in 64-bit layout. Since
746 debugging a 32-bit inferior with a 64-bit GDBSERVER should look the same
747 as debugging it with a 32-bit GDBSERVER, we do the 32-bit <-> 64-bit
748 conversion in-place ourselves. */
750 /* Convert a ptrace/host siginfo object, into/from the siginfo in the
751 layout of the inferiors' architecture. Returns true if any
752 conversion was done; false otherwise. If DIRECTION is 1, then copy
753 from INF to PTRACE. If DIRECTION is 0, copy from PTRACE to
757 x86_siginfo_fixup (siginfo_t
*ptrace
, gdb_byte
*inf
, int direction
)
760 unsigned int machine
;
761 int tid
= lwpid_of (current_thread
);
762 int is_elf64
= linux_pid_exe_is_elf_64_file (tid
, &machine
);
764 /* Is the inferior 32-bit? If so, then fixup the siginfo object. */
765 if (!is_64bit_tdesc ())
766 return amd64_linux_siginfo_fixup_common (ptrace
, inf
, direction
,
768 /* No fixup for native x32 GDB. */
769 else if (!is_elf64
&& sizeof (void *) == 8)
770 return amd64_linux_siginfo_fixup_common (ptrace
, inf
, direction
,
779 /* Format of XSAVE extended state is:
783 sw_usable_bytes[464..511]
784 xstate_hdr_bytes[512..575]
789 Same memory layout will be used for the coredump NT_X86_XSTATE
790 representing the XSAVE extended state registers.
792 The first 8 bytes of the sw_usable_bytes[464..467] is the OS enabled
793 extended state mask, which is the same as the extended control register
794 0 (the XFEATURE_ENABLED_MASK register), XCR0. We can use this mask
795 together with the mask saved in the xstate_hdr_bytes to determine what
796 states the processor/OS supports and what state, used or initialized,
797 the process/thread is in. */
798 #define I386_LINUX_XSAVE_XCR0_OFFSET 464
800 /* Does the current host support the GETFPXREGS request? The header
801 file may or may not define it, and even if it is defined, the
802 kernel will return EIO if it's running on a pre-SSE processor. */
803 int have_ptrace_getfpxregs
=
804 #ifdef HAVE_PTRACE_GETFPXREGS
811 /* Get Linux/x86 target description from running target. */
813 static const struct target_desc
*
814 x86_linux_read_description (void)
816 unsigned int machine
;
820 static uint64_t xcr0
;
821 struct regset_info
*regset
;
823 tid
= lwpid_of (current_thread
);
825 is_elf64
= linux_pid_exe_is_elf_64_file (tid
, &machine
);
827 if (sizeof (void *) == 4)
830 error (_("Can't debug 64-bit process with 32-bit GDBserver"));
832 else if (machine
== EM_X86_64
)
833 error (_("Can't debug x86-64 process with 32-bit GDBserver"));
837 #if !defined __x86_64__ && defined HAVE_PTRACE_GETFPXREGS
838 if (machine
== EM_386
&& have_ptrace_getfpxregs
== -1)
840 elf_fpxregset_t fpxregs
;
842 if (ptrace (PTRACE_GETFPXREGS
, tid
, 0, (long) &fpxregs
) < 0)
844 have_ptrace_getfpxregs
= 0;
845 have_ptrace_getregset
= 0;
846 return i386_linux_read_description (X86_XSTATE_X87
);
849 have_ptrace_getfpxregs
= 1;
855 x86_xcr0
= X86_XSTATE_SSE_MASK
;
859 if (machine
== EM_X86_64
)
860 return tdesc_amd64_linux_no_xml
;
863 return tdesc_i386_linux_no_xml
;
866 if (have_ptrace_getregset
== -1)
868 uint64_t xstateregs
[(X86_XSTATE_SSE_SIZE
/ sizeof (uint64_t))];
871 iov
.iov_base
= xstateregs
;
872 iov
.iov_len
= sizeof (xstateregs
);
874 /* Check if PTRACE_GETREGSET works. */
875 if (ptrace (PTRACE_GETREGSET
, tid
,
876 (unsigned int) NT_X86_XSTATE
, (long) &iov
) < 0)
877 have_ptrace_getregset
= 0;
880 have_ptrace_getregset
= 1;
882 /* Get XCR0 from XSAVE extended state. */
883 xcr0
= xstateregs
[(I386_LINUX_XSAVE_XCR0_OFFSET
884 / sizeof (uint64_t))];
886 /* Use PTRACE_GETREGSET if it is available. */
887 for (regset
= x86_regsets
;
888 regset
->fill_function
!= NULL
; regset
++)
889 if (regset
->get_request
== PTRACE_GETREGSET
)
890 regset
->size
= X86_XSTATE_SIZE (xcr0
);
891 else if (regset
->type
!= GENERAL_REGS
)
896 /* Check the native XCR0 only if PTRACE_GETREGSET is available. */
897 xcr0_features
= (have_ptrace_getregset
898 && (xcr0
& X86_XSTATE_ALL_MASK
));
903 if (machine
== EM_X86_64
)
906 const target_desc
*tdesc
= NULL
;
910 tdesc
= amd64_linux_read_description (xcr0
& X86_XSTATE_ALL_MASK
,
915 tdesc
= amd64_linux_read_description (X86_XSTATE_SSE_MASK
, !is_elf64
);
921 const target_desc
*tdesc
= NULL
;
924 tdesc
= i386_linux_read_description (xcr0
& X86_XSTATE_ALL_MASK
);
927 tdesc
= i386_linux_read_description (X86_XSTATE_SSE
);
932 gdb_assert_not_reached ("failed to return tdesc");
935 /* Update all the target description of all processes; a new GDB
936 connected, and it may or not support xml target descriptions. */
939 x86_target::update_xmltarget ()
941 struct thread_info
*saved_thread
= current_thread
;
943 /* Before changing the register cache's internal layout, flush the
944 contents of the current valid caches back to the threads, and
945 release the current regcache objects. */
948 for_each_process ([this] (process_info
*proc
) {
951 /* Look up any thread of this process. */
952 current_thread
= find_any_thread_of_pid (pid
);
957 current_thread
= saved_thread
;
960 /* Process qSupported query, "xmlRegisters=". Update the buffer size for
964 x86_linux_process_qsupported (char **features
, int count
)
968 /* Return if gdb doesn't support XML. If gdb sends "xmlRegisters="
969 with "i386" in qSupported query, it supports x86 XML target
972 for (i
= 0; i
< count
; i
++)
974 const char *feature
= features
[i
];
976 if (startswith (feature
, "xmlRegisters="))
978 char *copy
= xstrdup (feature
+ 13);
981 for (char *p
= strtok_r (copy
, ",", &saveptr
);
983 p
= strtok_r (NULL
, ",", &saveptr
))
985 if (strcmp (p
, "i386") == 0)
995 the_x86_target
.update_xmltarget ();
998 /* Common for x86/x86-64. */
1000 static struct regsets_info x86_regsets_info
=
1002 x86_regsets
, /* regsets */
1003 0, /* num_regsets */
1004 NULL
, /* disabled_regsets */
1008 static struct regs_info amd64_linux_regs_info
=
1010 NULL
, /* regset_bitmap */
1011 NULL
, /* usrregs_info */
1015 static struct usrregs_info i386_linux_usrregs_info
=
1021 static struct regs_info i386_linux_regs_info
=
1023 NULL
, /* regset_bitmap */
1024 &i386_linux_usrregs_info
,
1029 x86_target::get_regs_info ()
1032 if (is_64bit_tdesc ())
1033 return &amd64_linux_regs_info
;
1036 return &i386_linux_regs_info
;
1039 /* Initialize the target description for the architecture of the
1043 x86_target::low_arch_setup ()
1045 current_process ()->tdesc
= x86_linux_read_description ();
1048 /* Fill *SYSNO and *SYSRET with the syscall nr trapped and the syscall return
1049 code. This should only be called if LWP got a SYSCALL_SIGTRAP. */
1052 x86_get_syscall_trapinfo (struct regcache
*regcache
, int *sysno
)
1054 int use_64bit
= register_size (regcache
->tdesc
, 0) == 8;
1060 collect_register_by_name (regcache
, "orig_rax", &l_sysno
);
1061 *sysno
= (int) l_sysno
;
1064 collect_register_by_name (regcache
, "orig_eax", sysno
);
1068 x86_supports_tracepoints (void)
1074 append_insns (CORE_ADDR
*to
, size_t len
, const unsigned char *buf
)
1076 target_write_memory (*to
, buf
, len
);
1081 push_opcode (unsigned char *buf
, const char *op
)
1083 unsigned char *buf_org
= buf
;
1088 unsigned long ul
= strtoul (op
, &endptr
, 16);
1097 return buf
- buf_org
;
1102 /* Build a jump pad that saves registers and calls a collection
1103 function. Writes a jump instruction to the jump pad to
1104 JJUMPAD_INSN. The caller is responsible to write it in at the
1105 tracepoint address. */
1108 amd64_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint
, CORE_ADDR tpaddr
,
1109 CORE_ADDR collector
,
1112 CORE_ADDR
*jump_entry
,
1113 CORE_ADDR
*trampoline
,
1114 ULONGEST
*trampoline_size
,
1115 unsigned char *jjump_pad_insn
,
1116 ULONGEST
*jjump_pad_insn_size
,
1117 CORE_ADDR
*adjusted_insn_addr
,
1118 CORE_ADDR
*adjusted_insn_addr_end
,
1121 unsigned char buf
[40];
1125 CORE_ADDR buildaddr
= *jump_entry
;
1127 /* Build the jump pad. */
1129 /* First, do tracepoint data collection. Save registers. */
1131 /* Need to ensure stack pointer saved first. */
1132 buf
[i
++] = 0x54; /* push %rsp */
1133 buf
[i
++] = 0x55; /* push %rbp */
1134 buf
[i
++] = 0x57; /* push %rdi */
1135 buf
[i
++] = 0x56; /* push %rsi */
1136 buf
[i
++] = 0x52; /* push %rdx */
1137 buf
[i
++] = 0x51; /* push %rcx */
1138 buf
[i
++] = 0x53; /* push %rbx */
1139 buf
[i
++] = 0x50; /* push %rax */
1140 buf
[i
++] = 0x41; buf
[i
++] = 0x57; /* push %r15 */
1141 buf
[i
++] = 0x41; buf
[i
++] = 0x56; /* push %r14 */
1142 buf
[i
++] = 0x41; buf
[i
++] = 0x55; /* push %r13 */
1143 buf
[i
++] = 0x41; buf
[i
++] = 0x54; /* push %r12 */
1144 buf
[i
++] = 0x41; buf
[i
++] = 0x53; /* push %r11 */
1145 buf
[i
++] = 0x41; buf
[i
++] = 0x52; /* push %r10 */
1146 buf
[i
++] = 0x41; buf
[i
++] = 0x51; /* push %r9 */
1147 buf
[i
++] = 0x41; buf
[i
++] = 0x50; /* push %r8 */
1148 buf
[i
++] = 0x9c; /* pushfq */
1149 buf
[i
++] = 0x48; /* movabs <addr>,%rdi */
1151 memcpy (buf
+ i
, &tpaddr
, 8);
1153 buf
[i
++] = 0x57; /* push %rdi */
1154 append_insns (&buildaddr
, i
, buf
);
1156 /* Stack space for the collecting_t object. */
1158 i
+= push_opcode (&buf
[i
], "48 83 ec 18"); /* sub $0x18,%rsp */
1159 i
+= push_opcode (&buf
[i
], "48 b8"); /* mov <tpoint>,%rax */
1160 memcpy (buf
+ i
, &tpoint
, 8);
1162 i
+= push_opcode (&buf
[i
], "48 89 04 24"); /* mov %rax,(%rsp) */
1163 i
+= push_opcode (&buf
[i
],
1164 "64 48 8b 04 25 00 00 00 00"); /* mov %fs:0x0,%rax */
1165 i
+= push_opcode (&buf
[i
], "48 89 44 24 08"); /* mov %rax,0x8(%rsp) */
1166 append_insns (&buildaddr
, i
, buf
);
1170 i
+= push_opcode (&buf
[i
], "48 be"); /* movl <lockaddr>,%rsi */
1171 memcpy (&buf
[i
], (void *) &lockaddr
, 8);
1173 i
+= push_opcode (&buf
[i
], "48 89 e1"); /* mov %rsp,%rcx */
1174 i
+= push_opcode (&buf
[i
], "31 c0"); /* xor %eax,%eax */
1175 i
+= push_opcode (&buf
[i
], "f0 48 0f b1 0e"); /* lock cmpxchg %rcx,(%rsi) */
1176 i
+= push_opcode (&buf
[i
], "48 85 c0"); /* test %rax,%rax */
1177 i
+= push_opcode (&buf
[i
], "75 f4"); /* jne <again> */
1178 append_insns (&buildaddr
, i
, buf
);
1180 /* Set up the gdb_collect call. */
1181 /* At this point, (stack pointer + 0x18) is the base of our saved
1185 i
+= push_opcode (&buf
[i
], "48 89 e6"); /* mov %rsp,%rsi */
1186 i
+= push_opcode (&buf
[i
], "48 83 c6 18"); /* add $0x18,%rsi */
1188 /* tpoint address may be 64-bit wide. */
1189 i
+= push_opcode (&buf
[i
], "48 bf"); /* movl <addr>,%rdi */
1190 memcpy (buf
+ i
, &tpoint
, 8);
1192 append_insns (&buildaddr
, i
, buf
);
1194 /* The collector function being in the shared library, may be
1195 >31-bits away off the jump pad. */
1197 i
+= push_opcode (&buf
[i
], "48 b8"); /* mov $collector,%rax */
1198 memcpy (buf
+ i
, &collector
, 8);
1200 i
+= push_opcode (&buf
[i
], "ff d0"); /* callq *%rax */
1201 append_insns (&buildaddr
, i
, buf
);
1203 /* Clear the spin-lock. */
1205 i
+= push_opcode (&buf
[i
], "31 c0"); /* xor %eax,%eax */
1206 i
+= push_opcode (&buf
[i
], "48 a3"); /* mov %rax, lockaddr */
1207 memcpy (buf
+ i
, &lockaddr
, 8);
1209 append_insns (&buildaddr
, i
, buf
);
1211 /* Remove stack that had been used for the collect_t object. */
1213 i
+= push_opcode (&buf
[i
], "48 83 c4 18"); /* add $0x18,%rsp */
1214 append_insns (&buildaddr
, i
, buf
);
1216 /* Restore register state. */
1218 buf
[i
++] = 0x48; /* add $0x8,%rsp */
1222 buf
[i
++] = 0x9d; /* popfq */
1223 buf
[i
++] = 0x41; buf
[i
++] = 0x58; /* pop %r8 */
1224 buf
[i
++] = 0x41; buf
[i
++] = 0x59; /* pop %r9 */
1225 buf
[i
++] = 0x41; buf
[i
++] = 0x5a; /* pop %r10 */
1226 buf
[i
++] = 0x41; buf
[i
++] = 0x5b; /* pop %r11 */
1227 buf
[i
++] = 0x41; buf
[i
++] = 0x5c; /* pop %r12 */
1228 buf
[i
++] = 0x41; buf
[i
++] = 0x5d; /* pop %r13 */
1229 buf
[i
++] = 0x41; buf
[i
++] = 0x5e; /* pop %r14 */
1230 buf
[i
++] = 0x41; buf
[i
++] = 0x5f; /* pop %r15 */
1231 buf
[i
++] = 0x58; /* pop %rax */
1232 buf
[i
++] = 0x5b; /* pop %rbx */
1233 buf
[i
++] = 0x59; /* pop %rcx */
1234 buf
[i
++] = 0x5a; /* pop %rdx */
1235 buf
[i
++] = 0x5e; /* pop %rsi */
1236 buf
[i
++] = 0x5f; /* pop %rdi */
1237 buf
[i
++] = 0x5d; /* pop %rbp */
1238 buf
[i
++] = 0x5c; /* pop %rsp */
1239 append_insns (&buildaddr
, i
, buf
);
1241 /* Now, adjust the original instruction to execute in the jump
1243 *adjusted_insn_addr
= buildaddr
;
1244 relocate_instruction (&buildaddr
, tpaddr
);
1245 *adjusted_insn_addr_end
= buildaddr
;
1247 /* Finally, write a jump back to the program. */
1249 loffset
= (tpaddr
+ orig_size
) - (buildaddr
+ sizeof (jump_insn
));
1250 if (loffset
> INT_MAX
|| loffset
< INT_MIN
)
1253 "E.Jump back from jump pad too far from tracepoint "
1254 "(offset 0x%" PRIx64
" > int32).", loffset
);
1258 offset
= (int) loffset
;
1259 memcpy (buf
, jump_insn
, sizeof (jump_insn
));
1260 memcpy (buf
+ 1, &offset
, 4);
1261 append_insns (&buildaddr
, sizeof (jump_insn
), buf
);
1263 /* The jump pad is now built. Wire in a jump to our jump pad. This
1264 is always done last (by our caller actually), so that we can
1265 install fast tracepoints with threads running. This relies on
1266 the agent's atomic write support. */
1267 loffset
= *jump_entry
- (tpaddr
+ sizeof (jump_insn
));
1268 if (loffset
> INT_MAX
|| loffset
< INT_MIN
)
1271 "E.Jump pad too far from tracepoint "
1272 "(offset 0x%" PRIx64
" > int32).", loffset
);
1276 offset
= (int) loffset
;
1278 memcpy (buf
, jump_insn
, sizeof (jump_insn
));
1279 memcpy (buf
+ 1, &offset
, 4);
1280 memcpy (jjump_pad_insn
, buf
, sizeof (jump_insn
));
1281 *jjump_pad_insn_size
= sizeof (jump_insn
);
1283 /* Return the end address of our pad. */
1284 *jump_entry
= buildaddr
;
1289 #endif /* __x86_64__ */
1291 /* Build a jump pad that saves registers and calls a collection
1292 function. Writes a jump instruction to the jump pad to
1293 JJUMPAD_INSN. The caller is responsible to write it in at the
1294 tracepoint address. */
1297 i386_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint
, CORE_ADDR tpaddr
,
1298 CORE_ADDR collector
,
1301 CORE_ADDR
*jump_entry
,
1302 CORE_ADDR
*trampoline
,
1303 ULONGEST
*trampoline_size
,
1304 unsigned char *jjump_pad_insn
,
1305 ULONGEST
*jjump_pad_insn_size
,
1306 CORE_ADDR
*adjusted_insn_addr
,
1307 CORE_ADDR
*adjusted_insn_addr_end
,
1310 unsigned char buf
[0x100];
1312 CORE_ADDR buildaddr
= *jump_entry
;
1314 /* Build the jump pad. */
1316 /* First, do tracepoint data collection. Save registers. */
1318 buf
[i
++] = 0x60; /* pushad */
1319 buf
[i
++] = 0x68; /* push tpaddr aka $pc */
1320 *((int *)(buf
+ i
)) = (int) tpaddr
;
1322 buf
[i
++] = 0x9c; /* pushf */
1323 buf
[i
++] = 0x1e; /* push %ds */
1324 buf
[i
++] = 0x06; /* push %es */
1325 buf
[i
++] = 0x0f; /* push %fs */
1327 buf
[i
++] = 0x0f; /* push %gs */
1329 buf
[i
++] = 0x16; /* push %ss */
1330 buf
[i
++] = 0x0e; /* push %cs */
1331 append_insns (&buildaddr
, i
, buf
);
1333 /* Stack space for the collecting_t object. */
1335 i
+= push_opcode (&buf
[i
], "83 ec 08"); /* sub $0x8,%esp */
1337 /* Build the object. */
1338 i
+= push_opcode (&buf
[i
], "b8"); /* mov <tpoint>,%eax */
1339 memcpy (buf
+ i
, &tpoint
, 4);
1341 i
+= push_opcode (&buf
[i
], "89 04 24"); /* mov %eax,(%esp) */
1343 i
+= push_opcode (&buf
[i
], "65 a1 00 00 00 00"); /* mov %gs:0x0,%eax */
1344 i
+= push_opcode (&buf
[i
], "89 44 24 04"); /* mov %eax,0x4(%esp) */
1345 append_insns (&buildaddr
, i
, buf
);
1347 /* spin-lock. Note this is using cmpxchg, which leaves i386 behind.
1348 If we cared for it, this could be using xchg alternatively. */
1351 i
+= push_opcode (&buf
[i
], "31 c0"); /* xor %eax,%eax */
1352 i
+= push_opcode (&buf
[i
], "f0 0f b1 25"); /* lock cmpxchg
1354 memcpy (&buf
[i
], (void *) &lockaddr
, 4);
1356 i
+= push_opcode (&buf
[i
], "85 c0"); /* test %eax,%eax */
1357 i
+= push_opcode (&buf
[i
], "75 f2"); /* jne <again> */
1358 append_insns (&buildaddr
, i
, buf
);
1361 /* Set up arguments to the gdb_collect call. */
1363 i
+= push_opcode (&buf
[i
], "89 e0"); /* mov %esp,%eax */
1364 i
+= push_opcode (&buf
[i
], "83 c0 08"); /* add $0x08,%eax */
1365 i
+= push_opcode (&buf
[i
], "89 44 24 fc"); /* mov %eax,-0x4(%esp) */
1366 append_insns (&buildaddr
, i
, buf
);
1369 i
+= push_opcode (&buf
[i
], "83 ec 08"); /* sub $0x8,%esp */
1370 append_insns (&buildaddr
, i
, buf
);
1373 i
+= push_opcode (&buf
[i
], "c7 04 24"); /* movl <addr>,(%esp) */
1374 memcpy (&buf
[i
], (void *) &tpoint
, 4);
1376 append_insns (&buildaddr
, i
, buf
);
1378 buf
[0] = 0xe8; /* call <reladdr> */
1379 offset
= collector
- (buildaddr
+ sizeof (jump_insn
));
1380 memcpy (buf
+ 1, &offset
, 4);
1381 append_insns (&buildaddr
, 5, buf
);
1382 /* Clean up after the call. */
1383 buf
[0] = 0x83; /* add $0x8,%esp */
1386 append_insns (&buildaddr
, 3, buf
);
1389 /* Clear the spin-lock. This would need the LOCK prefix on older
1392 i
+= push_opcode (&buf
[i
], "31 c0"); /* xor %eax,%eax */
1393 i
+= push_opcode (&buf
[i
], "a3"); /* mov %eax, lockaddr */
1394 memcpy (buf
+ i
, &lockaddr
, 4);
1396 append_insns (&buildaddr
, i
, buf
);
1399 /* Remove stack that had been used for the collect_t object. */
1401 i
+= push_opcode (&buf
[i
], "83 c4 08"); /* add $0x08,%esp */
1402 append_insns (&buildaddr
, i
, buf
);
1405 buf
[i
++] = 0x83; /* add $0x4,%esp (no pop of %cs, assume unchanged) */
1408 buf
[i
++] = 0x17; /* pop %ss */
1409 buf
[i
++] = 0x0f; /* pop %gs */
1411 buf
[i
++] = 0x0f; /* pop %fs */
1413 buf
[i
++] = 0x07; /* pop %es */
1414 buf
[i
++] = 0x1f; /* pop %ds */
1415 buf
[i
++] = 0x9d; /* popf */
1416 buf
[i
++] = 0x83; /* add $0x4,%esp (pop of tpaddr aka $pc) */
1419 buf
[i
++] = 0x61; /* popad */
1420 append_insns (&buildaddr
, i
, buf
);
1422 /* Now, adjust the original instruction to execute in the jump
1424 *adjusted_insn_addr
= buildaddr
;
1425 relocate_instruction (&buildaddr
, tpaddr
);
1426 *adjusted_insn_addr_end
= buildaddr
;
1428 /* Write the jump back to the program. */
1429 offset
= (tpaddr
+ orig_size
) - (buildaddr
+ sizeof (jump_insn
));
1430 memcpy (buf
, jump_insn
, sizeof (jump_insn
));
1431 memcpy (buf
+ 1, &offset
, 4);
1432 append_insns (&buildaddr
, sizeof (jump_insn
), buf
);
1434 /* The jump pad is now built. Wire in a jump to our jump pad. This
1435 is always done last (by our caller actually), so that we can
1436 install fast tracepoints with threads running. This relies on
1437 the agent's atomic write support. */
1440 /* Create a trampoline. */
1441 *trampoline_size
= sizeof (jump_insn
);
1442 if (!claim_trampoline_space (*trampoline_size
, trampoline
))
1444 /* No trampoline space available. */
1446 "E.Cannot allocate trampoline space needed for fast "
1447 "tracepoints on 4-byte instructions.");
1451 offset
= *jump_entry
- (*trampoline
+ sizeof (jump_insn
));
1452 memcpy (buf
, jump_insn
, sizeof (jump_insn
));
1453 memcpy (buf
+ 1, &offset
, 4);
1454 target_write_memory (*trampoline
, buf
, sizeof (jump_insn
));
1456 /* Use a 16-bit relative jump instruction to jump to the trampoline. */
1457 offset
= (*trampoline
- (tpaddr
+ sizeof (small_jump_insn
))) & 0xffff;
1458 memcpy (buf
, small_jump_insn
, sizeof (small_jump_insn
));
1459 memcpy (buf
+ 2, &offset
, 2);
1460 memcpy (jjump_pad_insn
, buf
, sizeof (small_jump_insn
));
1461 *jjump_pad_insn_size
= sizeof (small_jump_insn
);
1465 /* Else use a 32-bit relative jump instruction. */
1466 offset
= *jump_entry
- (tpaddr
+ sizeof (jump_insn
));
1467 memcpy (buf
, jump_insn
, sizeof (jump_insn
));
1468 memcpy (buf
+ 1, &offset
, 4);
1469 memcpy (jjump_pad_insn
, buf
, sizeof (jump_insn
));
1470 *jjump_pad_insn_size
= sizeof (jump_insn
);
1473 /* Return the end address of our pad. */
1474 *jump_entry
= buildaddr
;
1480 x86_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint
, CORE_ADDR tpaddr
,
1481 CORE_ADDR collector
,
1484 CORE_ADDR
*jump_entry
,
1485 CORE_ADDR
*trampoline
,
1486 ULONGEST
*trampoline_size
,
1487 unsigned char *jjump_pad_insn
,
1488 ULONGEST
*jjump_pad_insn_size
,
1489 CORE_ADDR
*adjusted_insn_addr
,
1490 CORE_ADDR
*adjusted_insn_addr_end
,
1494 if (is_64bit_tdesc ())
1495 return amd64_install_fast_tracepoint_jump_pad (tpoint
, tpaddr
,
1496 collector
, lockaddr
,
1497 orig_size
, jump_entry
,
1498 trampoline
, trampoline_size
,
1500 jjump_pad_insn_size
,
1502 adjusted_insn_addr_end
,
1506 return i386_install_fast_tracepoint_jump_pad (tpoint
, tpaddr
,
1507 collector
, lockaddr
,
1508 orig_size
, jump_entry
,
1509 trampoline
, trampoline_size
,
1511 jjump_pad_insn_size
,
1513 adjusted_insn_addr_end
,
1517 /* Return the minimum instruction length for fast tracepoints on x86/x86-64
1521 x86_get_min_fast_tracepoint_insn_len (void)
1523 static int warned_about_fast_tracepoints
= 0;
1526 /* On x86-64, 5-byte jump instructions with a 4-byte offset are always
1527 used for fast tracepoints. */
1528 if (is_64bit_tdesc ())
1532 if (agent_loaded_p ())
1534 char errbuf
[IPA_BUFSIZ
];
1538 /* On x86, if trampolines are available, then 4-byte jump instructions
1539 with a 2-byte offset may be used, otherwise 5-byte jump instructions
1540 with a 4-byte offset are used instead. */
1541 if (have_fast_tracepoint_trampoline_buffer (errbuf
))
1545 /* GDB has no channel to explain to user why a shorter fast
1546 tracepoint is not possible, but at least make GDBserver
1547 mention that something has gone awry. */
1548 if (!warned_about_fast_tracepoints
)
1550 warning ("4-byte fast tracepoints not available; %s", errbuf
);
1551 warned_about_fast_tracepoints
= 1;
1558 /* Indicate that the minimum length is currently unknown since the IPA
1559 has not loaded yet. */
1565 add_insns (unsigned char *start
, int len
)
1567 CORE_ADDR buildaddr
= current_insn_ptr
;
1570 debug_printf ("Adding %d bytes of insn at %s\n",
1571 len
, paddress (buildaddr
));
1573 append_insns (&buildaddr
, len
, start
);
1574 current_insn_ptr
= buildaddr
;
1577 /* Our general strategy for emitting code is to avoid specifying raw
1578 bytes whenever possible, and instead copy a block of inline asm
1579 that is embedded in the function. This is a little messy, because
1580 we need to keep the compiler from discarding what looks like dead
1581 code, plus suppress various warnings. */
1583 #define EMIT_ASM(NAME, INSNS) \
1586 extern unsigned char start_ ## NAME, end_ ## NAME; \
1587 add_insns (&start_ ## NAME, &end_ ## NAME - &start_ ## NAME); \
1588 __asm__ ("jmp end_" #NAME "\n" \
1589 "\t" "start_" #NAME ":" \
1591 "\t" "end_" #NAME ":"); \
1596 #define EMIT_ASM32(NAME,INSNS) \
1599 extern unsigned char start_ ## NAME, end_ ## NAME; \
1600 add_insns (&start_ ## NAME, &end_ ## NAME - &start_ ## NAME); \
1601 __asm__ (".code32\n" \
1602 "\t" "jmp end_" #NAME "\n" \
1603 "\t" "start_" #NAME ":\n" \
1605 "\t" "end_" #NAME ":\n" \
1611 #define EMIT_ASM32(NAME,INSNS) EMIT_ASM(NAME,INSNS)
1618 amd64_emit_prologue (void)
1620 EMIT_ASM (amd64_prologue
,
1622 "movq %rsp,%rbp\n\t"
1623 "sub $0x20,%rsp\n\t"
1624 "movq %rdi,-8(%rbp)\n\t"
1625 "movq %rsi,-16(%rbp)");
1630 amd64_emit_epilogue (void)
1632 EMIT_ASM (amd64_epilogue
,
1633 "movq -16(%rbp),%rdi\n\t"
1634 "movq %rax,(%rdi)\n\t"
1641 amd64_emit_add (void)
1643 EMIT_ASM (amd64_add
,
1644 "add (%rsp),%rax\n\t"
1645 "lea 0x8(%rsp),%rsp");
1649 amd64_emit_sub (void)
1651 EMIT_ASM (amd64_sub
,
1652 "sub %rax,(%rsp)\n\t"
1657 amd64_emit_mul (void)
1663 amd64_emit_lsh (void)
1669 amd64_emit_rsh_signed (void)
1675 amd64_emit_rsh_unsigned (void)
1681 amd64_emit_ext (int arg
)
1686 EMIT_ASM (amd64_ext_8
,
1692 EMIT_ASM (amd64_ext_16
,
1697 EMIT_ASM (amd64_ext_32
,
1706 amd64_emit_log_not (void)
1708 EMIT_ASM (amd64_log_not
,
1709 "test %rax,%rax\n\t"
1715 amd64_emit_bit_and (void)
1717 EMIT_ASM (amd64_and
,
1718 "and (%rsp),%rax\n\t"
1719 "lea 0x8(%rsp),%rsp");
1723 amd64_emit_bit_or (void)
1726 "or (%rsp),%rax\n\t"
1727 "lea 0x8(%rsp),%rsp");
1731 amd64_emit_bit_xor (void)
1733 EMIT_ASM (amd64_xor
,
1734 "xor (%rsp),%rax\n\t"
1735 "lea 0x8(%rsp),%rsp");
1739 amd64_emit_bit_not (void)
1741 EMIT_ASM (amd64_bit_not
,
1742 "xorq $0xffffffffffffffff,%rax");
1746 amd64_emit_equal (void)
1748 EMIT_ASM (amd64_equal
,
1749 "cmp %rax,(%rsp)\n\t"
1750 "je .Lamd64_equal_true\n\t"
1752 "jmp .Lamd64_equal_end\n\t"
1753 ".Lamd64_equal_true:\n\t"
1755 ".Lamd64_equal_end:\n\t"
1756 "lea 0x8(%rsp),%rsp");
1760 amd64_emit_less_signed (void)
1762 EMIT_ASM (amd64_less_signed
,
1763 "cmp %rax,(%rsp)\n\t"
1764 "jl .Lamd64_less_signed_true\n\t"
1766 "jmp .Lamd64_less_signed_end\n\t"
1767 ".Lamd64_less_signed_true:\n\t"
1769 ".Lamd64_less_signed_end:\n\t"
1770 "lea 0x8(%rsp),%rsp");
1774 amd64_emit_less_unsigned (void)
1776 EMIT_ASM (amd64_less_unsigned
,
1777 "cmp %rax,(%rsp)\n\t"
1778 "jb .Lamd64_less_unsigned_true\n\t"
1780 "jmp .Lamd64_less_unsigned_end\n\t"
1781 ".Lamd64_less_unsigned_true:\n\t"
1783 ".Lamd64_less_unsigned_end:\n\t"
1784 "lea 0x8(%rsp),%rsp");
1788 amd64_emit_ref (int size
)
1793 EMIT_ASM (amd64_ref1
,
1797 EMIT_ASM (amd64_ref2
,
1801 EMIT_ASM (amd64_ref4
,
1802 "movl (%rax),%eax");
1805 EMIT_ASM (amd64_ref8
,
1806 "movq (%rax),%rax");
1812 amd64_emit_if_goto (int *offset_p
, int *size_p
)
1814 EMIT_ASM (amd64_if_goto
,
1818 ".byte 0x0f, 0x85, 0x0, 0x0, 0x0, 0x0");
1826 amd64_emit_goto (int *offset_p
, int *size_p
)
1828 EMIT_ASM (amd64_goto
,
1829 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0");
1837 amd64_write_goto_address (CORE_ADDR from
, CORE_ADDR to
, int size
)
1839 int diff
= (to
- (from
+ size
));
1840 unsigned char buf
[sizeof (int)];
1848 memcpy (buf
, &diff
, sizeof (int));
1849 target_write_memory (from
, buf
, sizeof (int));
1853 amd64_emit_const (LONGEST num
)
1855 unsigned char buf
[16];
1857 CORE_ADDR buildaddr
= current_insn_ptr
;
1860 buf
[i
++] = 0x48; buf
[i
++] = 0xb8; /* mov $<n>,%rax */
1861 memcpy (&buf
[i
], &num
, sizeof (num
));
1863 append_insns (&buildaddr
, i
, buf
);
1864 current_insn_ptr
= buildaddr
;
1868 amd64_emit_call (CORE_ADDR fn
)
1870 unsigned char buf
[16];
1872 CORE_ADDR buildaddr
;
1875 /* The destination function being in the shared library, may be
1876 >31-bits away off the compiled code pad. */
1878 buildaddr
= current_insn_ptr
;
1880 offset64
= fn
- (buildaddr
+ 1 /* call op */ + 4 /* 32-bit offset */);
1884 if (offset64
> INT_MAX
|| offset64
< INT_MIN
)
1886 /* Offset is too large for a call. Use callq, but that requires
1887 a register, so avoid it if possible. Use r10, since it is
1888 call-clobbered, we don't have to push/pop it. */
1889 buf
[i
++] = 0x48; /* mov $fn,%r10 */
1891 memcpy (buf
+ i
, &fn
, 8);
1893 buf
[i
++] = 0xff; /* callq *%r10 */
1898 int offset32
= offset64
; /* we know we can't overflow here. */
1900 buf
[i
++] = 0xe8; /* call <reladdr> */
1901 memcpy (buf
+ i
, &offset32
, 4);
1905 append_insns (&buildaddr
, i
, buf
);
1906 current_insn_ptr
= buildaddr
;
1910 amd64_emit_reg (int reg
)
1912 unsigned char buf
[16];
1914 CORE_ADDR buildaddr
;
1916 /* Assume raw_regs is still in %rdi. */
1917 buildaddr
= current_insn_ptr
;
1919 buf
[i
++] = 0xbe; /* mov $<n>,%esi */
1920 memcpy (&buf
[i
], ®
, sizeof (reg
));
1922 append_insns (&buildaddr
, i
, buf
);
1923 current_insn_ptr
= buildaddr
;
1924 amd64_emit_call (get_raw_reg_func_addr ());
1928 amd64_emit_pop (void)
1930 EMIT_ASM (amd64_pop
,
1935 amd64_emit_stack_flush (void)
1937 EMIT_ASM (amd64_stack_flush
,
1942 amd64_emit_zero_ext (int arg
)
1947 EMIT_ASM (amd64_zero_ext_8
,
1951 EMIT_ASM (amd64_zero_ext_16
,
1952 "and $0xffff,%rax");
1955 EMIT_ASM (amd64_zero_ext_32
,
1956 "mov $0xffffffff,%rcx\n\t"
1965 amd64_emit_swap (void)
1967 EMIT_ASM (amd64_swap
,
1974 amd64_emit_stack_adjust (int n
)
1976 unsigned char buf
[16];
1978 CORE_ADDR buildaddr
= current_insn_ptr
;
1981 buf
[i
++] = 0x48; /* lea $<n>(%rsp),%rsp */
1985 /* This only handles adjustments up to 16, but we don't expect any more. */
1987 append_insns (&buildaddr
, i
, buf
);
1988 current_insn_ptr
= buildaddr
;
1991 /* FN's prototype is `LONGEST(*fn)(int)'. */
1994 amd64_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
1996 unsigned char buf
[16];
1998 CORE_ADDR buildaddr
;
2000 buildaddr
= current_insn_ptr
;
2002 buf
[i
++] = 0xbf; /* movl $<n>,%edi */
2003 memcpy (&buf
[i
], &arg1
, sizeof (arg1
));
2005 append_insns (&buildaddr
, i
, buf
);
2006 current_insn_ptr
= buildaddr
;
2007 amd64_emit_call (fn
);
2010 /* FN's prototype is `void(*fn)(int,LONGEST)'. */
2013 amd64_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
2015 unsigned char buf
[16];
2017 CORE_ADDR buildaddr
;
2019 buildaddr
= current_insn_ptr
;
2021 buf
[i
++] = 0xbf; /* movl $<n>,%edi */
2022 memcpy (&buf
[i
], &arg1
, sizeof (arg1
));
2024 append_insns (&buildaddr
, i
, buf
);
2025 current_insn_ptr
= buildaddr
;
2026 EMIT_ASM (amd64_void_call_2_a
,
2027 /* Save away a copy of the stack top. */
2029 /* Also pass top as the second argument. */
2031 amd64_emit_call (fn
);
2032 EMIT_ASM (amd64_void_call_2_b
,
2033 /* Restore the stack top, %rax may have been trashed. */
2038 amd64_emit_eq_goto (int *offset_p
, int *size_p
)
2041 "cmp %rax,(%rsp)\n\t"
2042 "jne .Lamd64_eq_fallthru\n\t"
2043 "lea 0x8(%rsp),%rsp\n\t"
2045 /* jmp, but don't trust the assembler to choose the right jump */
2046 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2047 ".Lamd64_eq_fallthru:\n\t"
2048 "lea 0x8(%rsp),%rsp\n\t"
2058 amd64_emit_ne_goto (int *offset_p
, int *size_p
)
2061 "cmp %rax,(%rsp)\n\t"
2062 "je .Lamd64_ne_fallthru\n\t"
2063 "lea 0x8(%rsp),%rsp\n\t"
2065 /* jmp, but don't trust the assembler to choose the right jump */
2066 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2067 ".Lamd64_ne_fallthru:\n\t"
2068 "lea 0x8(%rsp),%rsp\n\t"
2078 amd64_emit_lt_goto (int *offset_p
, int *size_p
)
2081 "cmp %rax,(%rsp)\n\t"
2082 "jnl .Lamd64_lt_fallthru\n\t"
2083 "lea 0x8(%rsp),%rsp\n\t"
2085 /* jmp, but don't trust the assembler to choose the right jump */
2086 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2087 ".Lamd64_lt_fallthru:\n\t"
2088 "lea 0x8(%rsp),%rsp\n\t"
2098 amd64_emit_le_goto (int *offset_p
, int *size_p
)
2101 "cmp %rax,(%rsp)\n\t"
2102 "jnle .Lamd64_le_fallthru\n\t"
2103 "lea 0x8(%rsp),%rsp\n\t"
2105 /* jmp, but don't trust the assembler to choose the right jump */
2106 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2107 ".Lamd64_le_fallthru:\n\t"
2108 "lea 0x8(%rsp),%rsp\n\t"
2118 amd64_emit_gt_goto (int *offset_p
, int *size_p
)
2121 "cmp %rax,(%rsp)\n\t"
2122 "jng .Lamd64_gt_fallthru\n\t"
2123 "lea 0x8(%rsp),%rsp\n\t"
2125 /* jmp, but don't trust the assembler to choose the right jump */
2126 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2127 ".Lamd64_gt_fallthru:\n\t"
2128 "lea 0x8(%rsp),%rsp\n\t"
2138 amd64_emit_ge_goto (int *offset_p
, int *size_p
)
2141 "cmp %rax,(%rsp)\n\t"
2142 "jnge .Lamd64_ge_fallthru\n\t"
2143 ".Lamd64_ge_jump:\n\t"
2144 "lea 0x8(%rsp),%rsp\n\t"
2146 /* jmp, but don't trust the assembler to choose the right jump */
2147 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2148 ".Lamd64_ge_fallthru:\n\t"
2149 "lea 0x8(%rsp),%rsp\n\t"
2158 struct emit_ops amd64_emit_ops
=
2160 amd64_emit_prologue
,
2161 amd64_emit_epilogue
,
2166 amd64_emit_rsh_signed
,
2167 amd64_emit_rsh_unsigned
,
2175 amd64_emit_less_signed
,
2176 amd64_emit_less_unsigned
,
2180 amd64_write_goto_address
,
2185 amd64_emit_stack_flush
,
2186 amd64_emit_zero_ext
,
2188 amd64_emit_stack_adjust
,
2189 amd64_emit_int_call_1
,
2190 amd64_emit_void_call_2
,
2199 #endif /* __x86_64__ */
2202 i386_emit_prologue (void)
2204 EMIT_ASM32 (i386_prologue
,
2208 /* At this point, the raw regs base address is at 8(%ebp), and the
2209 value pointer is at 12(%ebp). */
2213 i386_emit_epilogue (void)
2215 EMIT_ASM32 (i386_epilogue
,
2216 "mov 12(%ebp),%ecx\n\t"
2217 "mov %eax,(%ecx)\n\t"
2218 "mov %ebx,0x4(%ecx)\n\t"
2226 i386_emit_add (void)
2228 EMIT_ASM32 (i386_add
,
2229 "add (%esp),%eax\n\t"
2230 "adc 0x4(%esp),%ebx\n\t"
2231 "lea 0x8(%esp),%esp");
2235 i386_emit_sub (void)
2237 EMIT_ASM32 (i386_sub
,
2238 "subl %eax,(%esp)\n\t"
2239 "sbbl %ebx,4(%esp)\n\t"
2245 i386_emit_mul (void)
2251 i386_emit_lsh (void)
2257 i386_emit_rsh_signed (void)
2263 i386_emit_rsh_unsigned (void)
2269 i386_emit_ext (int arg
)
2274 EMIT_ASM32 (i386_ext_8
,
2277 "movl %eax,%ebx\n\t"
2281 EMIT_ASM32 (i386_ext_16
,
2283 "movl %eax,%ebx\n\t"
2287 EMIT_ASM32 (i386_ext_32
,
2288 "movl %eax,%ebx\n\t"
2297 i386_emit_log_not (void)
2299 EMIT_ASM32 (i386_log_not
,
2301 "test %eax,%eax\n\t"
2308 i386_emit_bit_and (void)
2310 EMIT_ASM32 (i386_and
,
2311 "and (%esp),%eax\n\t"
2312 "and 0x4(%esp),%ebx\n\t"
2313 "lea 0x8(%esp),%esp");
2317 i386_emit_bit_or (void)
2319 EMIT_ASM32 (i386_or
,
2320 "or (%esp),%eax\n\t"
2321 "or 0x4(%esp),%ebx\n\t"
2322 "lea 0x8(%esp),%esp");
2326 i386_emit_bit_xor (void)
2328 EMIT_ASM32 (i386_xor
,
2329 "xor (%esp),%eax\n\t"
2330 "xor 0x4(%esp),%ebx\n\t"
2331 "lea 0x8(%esp),%esp");
2335 i386_emit_bit_not (void)
2337 EMIT_ASM32 (i386_bit_not
,
2338 "xor $0xffffffff,%eax\n\t"
2339 "xor $0xffffffff,%ebx\n\t");
2343 i386_emit_equal (void)
2345 EMIT_ASM32 (i386_equal
,
2346 "cmpl %ebx,4(%esp)\n\t"
2347 "jne .Li386_equal_false\n\t"
2348 "cmpl %eax,(%esp)\n\t"
2349 "je .Li386_equal_true\n\t"
2350 ".Li386_equal_false:\n\t"
2352 "jmp .Li386_equal_end\n\t"
2353 ".Li386_equal_true:\n\t"
2355 ".Li386_equal_end:\n\t"
2357 "lea 0x8(%esp),%esp");
2361 i386_emit_less_signed (void)
2363 EMIT_ASM32 (i386_less_signed
,
2364 "cmpl %ebx,4(%esp)\n\t"
2365 "jl .Li386_less_signed_true\n\t"
2366 "jne .Li386_less_signed_false\n\t"
2367 "cmpl %eax,(%esp)\n\t"
2368 "jl .Li386_less_signed_true\n\t"
2369 ".Li386_less_signed_false:\n\t"
2371 "jmp .Li386_less_signed_end\n\t"
2372 ".Li386_less_signed_true:\n\t"
2374 ".Li386_less_signed_end:\n\t"
2376 "lea 0x8(%esp),%esp");
2380 i386_emit_less_unsigned (void)
2382 EMIT_ASM32 (i386_less_unsigned
,
2383 "cmpl %ebx,4(%esp)\n\t"
2384 "jb .Li386_less_unsigned_true\n\t"
2385 "jne .Li386_less_unsigned_false\n\t"
2386 "cmpl %eax,(%esp)\n\t"
2387 "jb .Li386_less_unsigned_true\n\t"
2388 ".Li386_less_unsigned_false:\n\t"
2390 "jmp .Li386_less_unsigned_end\n\t"
2391 ".Li386_less_unsigned_true:\n\t"
2393 ".Li386_less_unsigned_end:\n\t"
2395 "lea 0x8(%esp),%esp");
2399 i386_emit_ref (int size
)
2404 EMIT_ASM32 (i386_ref1
,
2408 EMIT_ASM32 (i386_ref2
,
2412 EMIT_ASM32 (i386_ref4
,
2413 "movl (%eax),%eax");
2416 EMIT_ASM32 (i386_ref8
,
2417 "movl 4(%eax),%ebx\n\t"
2418 "movl (%eax),%eax");
2424 i386_emit_if_goto (int *offset_p
, int *size_p
)
2426 EMIT_ASM32 (i386_if_goto
,
2432 /* Don't trust the assembler to choose the right jump */
2433 ".byte 0x0f, 0x85, 0x0, 0x0, 0x0, 0x0");
2436 *offset_p
= 11; /* be sure that this matches the sequence above */
2442 i386_emit_goto (int *offset_p
, int *size_p
)
2444 EMIT_ASM32 (i386_goto
,
2445 /* Don't trust the assembler to choose the right jump */
2446 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0");
2454 i386_write_goto_address (CORE_ADDR from
, CORE_ADDR to
, int size
)
2456 int diff
= (to
- (from
+ size
));
2457 unsigned char buf
[sizeof (int)];
2459 /* We're only doing 4-byte sizes at the moment. */
2466 memcpy (buf
, &diff
, sizeof (int));
2467 target_write_memory (from
, buf
, sizeof (int));
2471 i386_emit_const (LONGEST num
)
2473 unsigned char buf
[16];
2475 CORE_ADDR buildaddr
= current_insn_ptr
;
2478 buf
[i
++] = 0xb8; /* mov $<n>,%eax */
2479 lo
= num
& 0xffffffff;
2480 memcpy (&buf
[i
], &lo
, sizeof (lo
));
2482 hi
= ((num
>> 32) & 0xffffffff);
2485 buf
[i
++] = 0xbb; /* mov $<n>,%ebx */
2486 memcpy (&buf
[i
], &hi
, sizeof (hi
));
2491 buf
[i
++] = 0x31; buf
[i
++] = 0xdb; /* xor %ebx,%ebx */
2493 append_insns (&buildaddr
, i
, buf
);
2494 current_insn_ptr
= buildaddr
;
2498 i386_emit_call (CORE_ADDR fn
)
2500 unsigned char buf
[16];
2502 CORE_ADDR buildaddr
;
2504 buildaddr
= current_insn_ptr
;
2506 buf
[i
++] = 0xe8; /* call <reladdr> */
2507 offset
= ((int) fn
) - (buildaddr
+ 5);
2508 memcpy (buf
+ 1, &offset
, 4);
2509 append_insns (&buildaddr
, 5, buf
);
2510 current_insn_ptr
= buildaddr
;
2514 i386_emit_reg (int reg
)
2516 unsigned char buf
[16];
2518 CORE_ADDR buildaddr
;
2520 EMIT_ASM32 (i386_reg_a
,
2522 buildaddr
= current_insn_ptr
;
2524 buf
[i
++] = 0xb8; /* mov $<n>,%eax */
2525 memcpy (&buf
[i
], ®
, sizeof (reg
));
2527 append_insns (&buildaddr
, i
, buf
);
2528 current_insn_ptr
= buildaddr
;
2529 EMIT_ASM32 (i386_reg_b
,
2530 "mov %eax,4(%esp)\n\t"
2531 "mov 8(%ebp),%eax\n\t"
2533 i386_emit_call (get_raw_reg_func_addr ());
2534 EMIT_ASM32 (i386_reg_c
,
2536 "lea 0x8(%esp),%esp");
2540 i386_emit_pop (void)
2542 EMIT_ASM32 (i386_pop
,
2548 i386_emit_stack_flush (void)
2550 EMIT_ASM32 (i386_stack_flush
,
2556 i386_emit_zero_ext (int arg
)
2561 EMIT_ASM32 (i386_zero_ext_8
,
2562 "and $0xff,%eax\n\t"
2566 EMIT_ASM32 (i386_zero_ext_16
,
2567 "and $0xffff,%eax\n\t"
2571 EMIT_ASM32 (i386_zero_ext_32
,
2580 i386_emit_swap (void)
2582 EMIT_ASM32 (i386_swap
,
2592 i386_emit_stack_adjust (int n
)
2594 unsigned char buf
[16];
2596 CORE_ADDR buildaddr
= current_insn_ptr
;
2599 buf
[i
++] = 0x8d; /* lea $<n>(%esp),%esp */
2603 append_insns (&buildaddr
, i
, buf
);
2604 current_insn_ptr
= buildaddr
;
2607 /* FN's prototype is `LONGEST(*fn)(int)'. */
2610 i386_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
2612 unsigned char buf
[16];
2614 CORE_ADDR buildaddr
;
2616 EMIT_ASM32 (i386_int_call_1_a
,
2617 /* Reserve a bit of stack space. */
2619 /* Put the one argument on the stack. */
2620 buildaddr
= current_insn_ptr
;
2622 buf
[i
++] = 0xc7; /* movl $<arg1>,(%esp) */
2625 memcpy (&buf
[i
], &arg1
, sizeof (arg1
));
2627 append_insns (&buildaddr
, i
, buf
);
2628 current_insn_ptr
= buildaddr
;
2629 i386_emit_call (fn
);
2630 EMIT_ASM32 (i386_int_call_1_c
,
2632 "lea 0x8(%esp),%esp");
2635 /* FN's prototype is `void(*fn)(int,LONGEST)'. */
2638 i386_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
2640 unsigned char buf
[16];
2642 CORE_ADDR buildaddr
;
2644 EMIT_ASM32 (i386_void_call_2_a
,
2645 /* Preserve %eax only; we don't have to worry about %ebx. */
2647 /* Reserve a bit of stack space for arguments. */
2648 "sub $0x10,%esp\n\t"
2649 /* Copy "top" to the second argument position. (Note that
2650 we can't assume function won't scribble on its
2651 arguments, so don't try to restore from this.) */
2652 "mov %eax,4(%esp)\n\t"
2653 "mov %ebx,8(%esp)");
2654 /* Put the first argument on the stack. */
2655 buildaddr
= current_insn_ptr
;
2657 buf
[i
++] = 0xc7; /* movl $<arg1>,(%esp) */
2660 memcpy (&buf
[i
], &arg1
, sizeof (arg1
));
2662 append_insns (&buildaddr
, i
, buf
);
2663 current_insn_ptr
= buildaddr
;
2664 i386_emit_call (fn
);
2665 EMIT_ASM32 (i386_void_call_2_b
,
2666 "lea 0x10(%esp),%esp\n\t"
2667 /* Restore original stack top. */
2673 i386_emit_eq_goto (int *offset_p
, int *size_p
)
2676 /* Check low half first, more likely to be decider */
2677 "cmpl %eax,(%esp)\n\t"
2678 "jne .Leq_fallthru\n\t"
2679 "cmpl %ebx,4(%esp)\n\t"
2680 "jne .Leq_fallthru\n\t"
2681 "lea 0x8(%esp),%esp\n\t"
2684 /* jmp, but don't trust the assembler to choose the right jump */
2685 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2686 ".Leq_fallthru:\n\t"
2687 "lea 0x8(%esp),%esp\n\t"
2698 i386_emit_ne_goto (int *offset_p
, int *size_p
)
2701 /* Check low half first, more likely to be decider */
2702 "cmpl %eax,(%esp)\n\t"
2704 "cmpl %ebx,4(%esp)\n\t"
2705 "je .Lne_fallthru\n\t"
2707 "lea 0x8(%esp),%esp\n\t"
2710 /* jmp, but don't trust the assembler to choose the right jump */
2711 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2712 ".Lne_fallthru:\n\t"
2713 "lea 0x8(%esp),%esp\n\t"
2724 i386_emit_lt_goto (int *offset_p
, int *size_p
)
2727 "cmpl %ebx,4(%esp)\n\t"
2729 "jne .Llt_fallthru\n\t"
2730 "cmpl %eax,(%esp)\n\t"
2731 "jnl .Llt_fallthru\n\t"
2733 "lea 0x8(%esp),%esp\n\t"
2736 /* jmp, but don't trust the assembler to choose the right jump */
2737 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2738 ".Llt_fallthru:\n\t"
2739 "lea 0x8(%esp),%esp\n\t"
2750 i386_emit_le_goto (int *offset_p
, int *size_p
)
2753 "cmpl %ebx,4(%esp)\n\t"
2755 "jne .Lle_fallthru\n\t"
2756 "cmpl %eax,(%esp)\n\t"
2757 "jnle .Lle_fallthru\n\t"
2759 "lea 0x8(%esp),%esp\n\t"
2762 /* jmp, but don't trust the assembler to choose the right jump */
2763 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2764 ".Lle_fallthru:\n\t"
2765 "lea 0x8(%esp),%esp\n\t"
2776 i386_emit_gt_goto (int *offset_p
, int *size_p
)
2779 "cmpl %ebx,4(%esp)\n\t"
2781 "jne .Lgt_fallthru\n\t"
2782 "cmpl %eax,(%esp)\n\t"
2783 "jng .Lgt_fallthru\n\t"
2785 "lea 0x8(%esp),%esp\n\t"
2788 /* jmp, but don't trust the assembler to choose the right jump */
2789 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2790 ".Lgt_fallthru:\n\t"
2791 "lea 0x8(%esp),%esp\n\t"
2802 i386_emit_ge_goto (int *offset_p
, int *size_p
)
2805 "cmpl %ebx,4(%esp)\n\t"
2807 "jne .Lge_fallthru\n\t"
2808 "cmpl %eax,(%esp)\n\t"
2809 "jnge .Lge_fallthru\n\t"
2811 "lea 0x8(%esp),%esp\n\t"
2814 /* jmp, but don't trust the assembler to choose the right jump */
2815 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2816 ".Lge_fallthru:\n\t"
2817 "lea 0x8(%esp),%esp\n\t"
2827 struct emit_ops i386_emit_ops
=
2835 i386_emit_rsh_signed
,
2836 i386_emit_rsh_unsigned
,
2844 i386_emit_less_signed
,
2845 i386_emit_less_unsigned
,
2849 i386_write_goto_address
,
2854 i386_emit_stack_flush
,
2857 i386_emit_stack_adjust
,
2858 i386_emit_int_call_1
,
2859 i386_emit_void_call_2
,
2869 static struct emit_ops
*
2873 if (is_64bit_tdesc ())
2874 return &amd64_emit_ops
;
2877 return &i386_emit_ops
;
2880 /* Implementation of target ops method "sw_breakpoint_from_kind". */
2883 x86_target::sw_breakpoint_from_kind (int kind
, int *size
)
2885 *size
= x86_breakpoint_len
;
2886 return x86_breakpoint
;
2890 x86_supports_range_stepping (void)
2895 /* Implementation of linux_target_ops method "supports_hardware_single_step".
2899 x86_supports_hardware_single_step (void)
2905 x86_get_ipa_tdesc_idx (void)
2907 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
2908 const struct target_desc
*tdesc
= regcache
->tdesc
;
2911 return amd64_get_ipa_tdesc_idx (tdesc
);
2914 if (tdesc
== tdesc_i386_linux_no_xml
)
2915 return X86_TDESC_SSE
;
2917 return i386_get_ipa_tdesc_idx (tdesc
);
2920 /* This is initialized assuming an amd64 target.
2921 x86_arch_setup will correct it for i386 or amd64 targets. */
2923 struct linux_target_ops the_low_target
=
2925 /* collect_ptrace_register/supply_ptrace_register are not needed in the
2926 native i386 case (no registers smaller than an xfer unit), and are not
2927 used in the biarch case (HAVE_LINUX_USRREGS is not defined). */
2930 /* need to fix up i386 siginfo if host is amd64 */
2932 x86_linux_new_process
,
2933 x86_linux_delete_process
,
2934 x86_linux_new_thread
,
2935 x86_linux_delete_thread
,
2937 x86_linux_prepare_to_resume
,
2938 x86_linux_process_qsupported
,
2939 x86_supports_tracepoints
,
2940 x86_get_thread_area
,
2941 x86_install_fast_tracepoint_jump_pad
,
2943 x86_get_min_fast_tracepoint_insn_len
,
2944 x86_supports_range_stepping
,
2945 x86_supports_hardware_single_step
,
2946 x86_get_syscall_trapinfo
,
2947 x86_get_ipa_tdesc_idx
,
2950 /* The linux target ops object. */
2952 linux_process_target
*the_linux_target
= &the_x86_target
;
2955 initialize_low_arch (void)
2957 /* Initialize the Linux target descriptions. */
2959 tdesc_amd64_linux_no_xml
= allocate_target_description ();
2960 copy_target_description (tdesc_amd64_linux_no_xml
,
2961 amd64_linux_read_description (X86_XSTATE_SSE_MASK
,
2963 tdesc_amd64_linux_no_xml
->xmltarget
= xmltarget_amd64_linux_no_xml
;
2966 tdesc_i386_linux_no_xml
= allocate_target_description ();
2967 copy_target_description (tdesc_i386_linux_no_xml
,
2968 i386_linux_read_description (X86_XSTATE_SSE_MASK
));
2969 tdesc_i386_linux_no_xml
->xmltarget
= xmltarget_i386_linux_no_xml
;
2971 initialize_regsets_info (&x86_regsets_info
);