gpr_hazard.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 entity gpr_hazard is
   6     generic (
   7         PIPELINE_DEPTH : natural := 1
   8         );
   9     port(
  10         clk                : in std_ulogic;
  11         busy_in            : in std_ulogic;
  12         deferred           : in std_ulogic;
  13         complete_in        : in std_ulogic;
  14         flush_in           : in std_ulogic;
  15         issuing            : in std_ulogic;
  16
  17         gpr_write_valid_in : in std_ulogic;
  18         gpr_write_in       : in std_ulogic_vector(5 downto 0);
  19         bypass_avail       : in std_ulogic;
  20         gpr_read_valid_in  : in std_ulogic;
  21         gpr_read_in        : in std_ulogic_vector(5 downto 0);
  22
  23         ugpr_write_valid   : in std_ulogic;
  24         ugpr_write_reg     : in std_ulogic_vector(5 downto 0);
  25
  26         stall_out          : out std_ulogic;
  27         use_bypass         : out std_ulogic
  28         );
  29 end entity gpr_hazard;
  30 architecture behaviour of gpr_hazard is
  31     type pipeline_entry_type is record
  32         valid  : std_ulogic;
  33         bypass : std_ulogic;
  34         gpr    : std_ulogic_vector(5 downto 0);
  35         ugpr_valid : std_ulogic;
  36         ugpr   : std_ulogic_vector(5 downto 0);
  37     end record;
  38     constant pipeline_entry_init : pipeline_entry_type := (valid => '0', bypass => '0', gpr => (others => '0'),
  39                                                            ugpr_valid => '0', ugpr => (others => '0'));
  40
  41     type pipeline_t is array(0 to PIPELINE_DEPTH) of pipeline_entry_type;
  42     constant pipeline_t_init : pipeline_t := (others => pipeline_entry_init);
  43
  44     signal r, rin : pipeline_t := pipeline_t_init;
  45 begin
  46     gpr_hazard0: process(clk)
  47     begin
  48         if rising_edge(clk) then
  49             r <= rin;
  50         end if;
  51     end process;
  52
  53     gpr_hazard1: process(all)
  54         variable v     : pipeline_t;
  55     begin
  56         v := r;
  57
  58         if complete_in = '1' then
  59             v(PIPELINE_DEPTH).valid := '0';
  60             v(PIPELINE_DEPTH).ugpr_valid := '0';
  61         end if;
  62
  63         stall_out <= '0';
  64         use_bypass <= '0';
  65         if gpr_read_valid_in = '1' then
  66             loop_0: for i in 0 to PIPELINE_DEPTH loop
  67                 if v(i).valid = '1' and r(i).gpr = gpr_read_in then
  68                     if r(i).bypass = '1' then
  69                         use_bypass <= '1';
  70                     else
  71                         stall_out <= '1';
  72                     end if;
  73                 end if;
  74                 if v(i).ugpr_valid = '1' and r(i).ugpr = gpr_read_in then
  75                     stall_out <= '1';
  76                 end if;
  77             end loop;
  78         end if;
  79
  80         -- XXX assumes PIPELINE_DEPTH = 1
  81         if busy_in = '0' then
  82             v(1) := v(0);
  83             v(0).valid := '0';
  84             v(0).ugpr_valid := '0';
  85         end if;
  86         if deferred = '0' and issuing = '1' then
  87             v(0).valid  := gpr_write_valid_in;
  88             v(0).bypass := bypass_avail;
  89             v(0).gpr    := gpr_write_in;
  90             v(0).ugpr_valid := ugpr_write_valid;
  91             v(0).ugpr   := ugpr_write_reg;
  92         end if;
  93         if flush_in = '1' then
  94             v(0).valid := '0';
  95             v(0).ugpr_valid := '0';
  96             v(1).valid := '0';
  97             v(1).ugpr_valid := '0';
  98         end if;
  99
 100         -- update registers
 101         rin <= v;
 102
 103     end process;
 104 end;