Merge pull request #132 from antonblanchard/bin2hex-move
[microwatt.git] / gpr_hazard.vhdl
1 library ieee;
2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
4
5 entity gpr_hazard is
6 generic (
7 PIPELINE_DEPTH : natural := 2
8 );
9 port(
10 clk : in std_ulogic;
11 stall_in : in std_ulogic;
12
13 gpr_write_valid_in : in std_ulogic;
14 gpr_write_in : in std_ulogic_vector(5 downto 0);
15 gpr_read_valid_in : in std_ulogic;
16 gpr_read_in : in std_ulogic_vector(5 downto 0);
17
18 stall_out : out std_ulogic
19 );
20 end entity gpr_hazard;
21 architecture behaviour of gpr_hazard is
22 type pipeline_entry_type is record
23 valid : std_ulogic;
24 gpr : std_ulogic_vector(5 downto 0);
25 end record;
26 constant pipeline_entry_init : pipeline_entry_type := (valid => '0', gpr => (others => '0'));
27
28 type pipeline_t is array(0 to PIPELINE_DEPTH-1) of pipeline_entry_type;
29 constant pipeline_t_init : pipeline_t := (others => pipeline_entry_init);
30
31 signal r, rin : pipeline_t := pipeline_t_init;
32 begin
33 gpr_hazard0: process(clk)
34 begin
35 if rising_edge(clk) then
36 if stall_in = '0' then
37 r <= rin;
38 end if;
39 end if;
40 end process;
41
42 gpr_hazard1: process(all)
43 variable v : pipeline_t;
44 begin
45 v := r;
46
47 stall_out <= '0';
48 loop_0: for i in 0 to PIPELINE_DEPTH-1 loop
49 if ((r(i).valid = gpr_read_valid_in) and r(i).gpr = gpr_read_in) then
50 stall_out <= '1';
51 end if;
52 end loop;
53
54 v(0).valid := gpr_write_valid_in;
55 v(0).gpr := gpr_write_in;
56 loop_1: for i in 0 to PIPELINE_DEPTH-2 loop
57 -- propagate to next slot
58 v(i+1) := r(i);
59 end loop;
60
61 -- asynchronous output
62 if gpr_read_valid_in = '0' then
63 stall_out <= '0';
64 end if;
65
66 -- update registers
67 rin <= v;
68
69 end process;
70 end;