gram/core/__init__.py

   1 from nmigen import *
   2
   3 from lambdasoc.periph import Peripheral
   4
   5 from gram.dfii import DFIInjector
   6 from gram.compat import CSRPrefixProxy
   7 from gram.core.controller import ControllerSettings, gramController
   8 from gram.core.crossbar import gramCrossbar
   9
  10 __ALL__ = ["gramCore"]
  11
  12 class gramCore(Peripheral, Elaboratable):
  13     def __init__(self, phy, geom_settings, timing_settings, clk_freq, **kwargs):
  14         super().__init__("core")
  15
  16         bank = self.csr_bank()
  17
  18         self._zero_ev = self.event(mode="rise")
  19
  20         self._phy = phy
  21         self._geom_settings = geom_settings
  22         self._timing_settings = timing_settings
  23         self._clk_freq = clk_freq
  24         self._kwargs = kwargs
  25
  26         self.dfii = DFIInjector(
  27             csr_bank=CSRPrefixProxy(bank, "dfii"),
  28             addressbits=self._geom_settings.addressbits,
  29             bankbits=self._geom_settings.bankbits,
  30             nranks=self._phy.settings.nranks,
  31             databits=self._phy.settings.dfi_databits,
  32             nphases=self._phy.settings.nphases)
  33
  34         self.controller = gramController(
  35             phy_settings=self._phy.settings,
  36             geom_settings=self._geom_settings,
  37             timing_settings=self._timing_settings,
  38             clk_freq=self._clk_freq,
  39             **self._kwargs)
  40
  41         # Size in bytes
  42         self.size = 2**geom_settings.bankbits * \
  43             2**geom_settings.rowbits * 2**geom_settings.colbits
  44
  45         self.crossbar = gramCrossbar(self.controller.interface)
  46
  47         self._bridge = self.bridge(data_width=32, granularity=8, alignment=2)
  48         self.bus = self._bridge.bus
  49         self.irq = self._bridge.irq
  50
  51     def elaborate(self, platform):
  52         m = Module()
  53
  54         m.submodules += self._bridge
  55
  56         m.submodules += self.dfii
  57         m.d.comb += self.dfii.master.connect(self._phy.dfi)
  58
  59         m.submodules.controller = self.controller
  60         m.d.comb += self.controller.dfi.connect(self.dfii.slave)
  61
  62         m.submodules += self.crossbar
  63
  64         return m