gram/core/controller.py

   1 # This file is Copyright (c) 2015 Sebastien Bourdeauducq <sb@m-labs.hk>
   2 # This file is Copyright (c) 2016-2019 Florent Kermarrec <florent@enjoy-digital.fr>
   3 # This file is Copyright (c) 2020 LambdaConcept <contact@lambdaconcept.com>
   4 # License: BSD
   5
   6 """LiteDRAM Controller."""
   7
   8 from nmigen import *
   9 from nmigen.utils import log2_int
  10
  11 from gram.common import *
  12 from gram.phy import dfi
  13 from gram.core.refresher import Refresher
  14 from gram.core.bankmachine import BankMachine
  15 from gram.core.multiplexer import Multiplexer
  16
  17 # Settings -----------------------------------------------------------------------------------------
  18
  19
  20 class ControllerSettings(Settings):
  21     def __init__(self,
  22                  # Command buffers
  23                  cmd_buffer_depth=8,
  24                  cmd_buffer_buffered=False,
  25
  26                  # Read/Write times
  27                  read_time=32,
  28                  write_time=16,
  29
  30                  # Refresh
  31                  with_refresh=True,
  32                  refresh_cls=Refresher,
  33                  refresh_zqcs_freq=1e0,
  34                  refresh_postponing=1,
  35
  36                  # Auto-Precharge
  37                  with_auto_precharge=True,
  38
  39                  # Address mapping
  40                  address_mapping="ROW_BANK_COL"):
  41         self.set_attributes(locals())
  42
  43 # Controller ---------------------------------------------------------------------------------------
  44
  45
  46 class gramController(Elaboratable):
  47     def __init__(self, phy_settings, geom_settings, timing_settings, clk_freq,
  48                  controller_settings=ControllerSettings()):
  49         self._address_align = log2_int(burst_lengths[phy_settings.memtype])
  50
  51         # Settings ---------------------------------------------------------------------------------
  52         self.settings = controller_settings
  53         self.settings.phy = phy_settings
  54         self.settings.geom = geom_settings
  55         self.settings.timing = timing_settings
  56
  57         # LiteDRAM Interface (User) ----------------------------------------------------------------
  58         self.interface = interface = gramInterface(
  59             self._address_align, self.settings)
  60
  61         # DFI Interface (Memory) -------------------------------------------------------------------
  62         self.dfi = dfi.Interface(
  63             addressbits=geom_settings.addressbits,
  64             bankbits=geom_settings.bankbits,
  65             nranks=phy_settings.nranks,
  66             databits=phy_settings.dfi_databits,
  67             nphases=phy_settings.nphases)
  68
  69         self._clk_freq = clk_freq
  70
  71     def elaborate(self, platform):
  72         m = Module()
  73
  74         nranks = self.settings.phy.nranks
  75         nbanks = 2**self.settings.geom.bankbits
  76
  77         # Refresher --------------------------------------------------------------------------------
  78         m.submodules.refresher = self.settings.refresh_cls(self.settings,
  79                                                            clk_freq=self._clk_freq,
  80                                                            zqcs_freq=self.settings.refresh_zqcs_freq,
  81                                                            postponing=self.settings.refresh_postponing)
  82
  83         # Bank Machines ----------------------------------------------------------------------------
  84         bank_machines = []
  85         for n in range(nranks*nbanks):
  86             bank_machine = BankMachine(n,
  87                                        address_width=self.interface.address_width,
  88                                        address_align=self._address_align,
  89                                        nranks=nranks,
  90                                        settings=self.settings)
  91             bank_machines.append(bank_machine)
  92             m.submodules += bank_machine
  93             m.d.comb += getattr(self.interface, "bank" +
  94                                 str(n)).connect(bank_machine.req)
  95
  96         # Multiplexer ------------------------------------------------------------------------------
  97         m.submodules.multiplexer = Multiplexer(
  98             settings=self.settings,
  99             bank_machines=bank_machines,
 100             refresher=m.submodules.refresher,
 101             dfi=self.dfi,
 102             interface=self.interface)
 103
 104         return m